AND8331D [ONSEMI]
Quasi-Resonant Current- Mode Controller for High- Power ac-dc Adapters; 准谐振电流 - \n对于高模式控制器\n电源AC-DC适配器
| 型号： | AND8331D |
| 厂家： | 
ONSEMI |
| 描述： | Quasi-Resonant Current-
Mode Controller for High-
Power ac-dc Adapters |
| 文件： | 总16页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AND8331/D
Quasi-Resonant Current-
Mode Controller for High-
Power ac-dc Adapters
Prepared by: Stéphanie Conseil
ON Semiconductor
http://onsemi.com
Introduction
Pin Description
This document describes the implementation of the
DAP013 inside an AC-DC adapter.
Over Power Protection pin (OPP, pin 1): applying a
negative voltage on this pin reduces the internal maximum
peak current set point.
Over Temperature Protection pin (OTP, pin 2): Connect
an NTC between this pin and ground. An internal current
source biases the NTC. When the NTC pulls the pin down,
the circuit permanently latches-off.
The DAP013 offers everything to build high performance
AC-DC converters or offline adapters. Thanks to a novel
valley lockout system, the controller is able to switch inside
the drain-source valley and is immune to valley jumping
instabilities. When the output load decreases significantly,
the controller toggles to a fixed peak current/variable
frequency mode that ensures very low standby power
consumption. And last, but not least, the DAP013 features
the usual protections that help to build cheap and safe power
supplies: OVP, OTP, Brown-Out (C and D options),
Short-circuit protection (latched for A, C versions and
auto-recovery for D, F versions), soft-start, OPP, internal
TSD...
Timer pin (Timer, pin 3): Wiring a capacitor from this pin
to ground helps selecting the timer duration.
Zero Voltage Detection pin (ZCD, pin 4): Connected to
the auxiliary winding, this pin detects the core reset event.
Timing Capacitor pin (Ct, pin 5): A capacitor connected
to this pin acts as the timing capacitor in VCO mode.
Feedback pin (FB, pin 6): Hooking an optocoupler
collector to this pin will allow regulation.
To summarise, the DAP013 offers the following
characteristics:
• Quasi-resonant Peak Current-mode Control Operation
• Valley Switching Operation with Valley-lockout for
Noise-immune Operation
Current Sense pin (CS, pin 7): This pin monitors the
primary current and triggers the fault if needed.
Ground pin (GND, pin 8): The controller ground.
Driver pin (DRV, pin 9): This pin delivers pulses to the
power MOSFET.
Power Supply pin (V , pin 10): This pin supplies the
CC
• VCO Mode (fixed peak current, variable frequency) in
Light Output Load for Improved Standby Dissipation
• Internal 5 ms Soft-start
controller and accepts voltage up to 28 V.
Brown-Out pin (BO, pin 11): Allows shutting-down the
controller for a chosen input voltage level. (C and D versions
only)
Over Voltage Protection pin (OVP, pin 12): By pulling
this pin high, the controller can be permanently latched-off.
High Voltage pin (HV, pin 14): Connected to the bulk
capacitor, this pin powers the internal current source to
• Loss-free Adjustable Over Power Protection
• Auto-recovery or Latched Internal Output Short-circuit
Protection
• Adjustable Timer for Improved Short-circuit Protection
• Over-voltage and Over-temperature Protection Inputs
• Brown-out Input for C and D Versions
deliver a start-up current that charges the V capacitor.
CC
• +500 mA / –800 mA Peak Current Source/Sink
I. Over Power Protection
Capability
1. How Does It Work?
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• 3 ms Blanking Delay to Ignore Leakage Ringing at
Turn-off
• Extremely Low No-load Standby Power
• SO14 Package
A flyback operated in Quasi Resonant mode exhibits wide
peak current variations in relationship to the input voltage
conditions. As a result, the converter output power range
widens as the input voltage increases. To cope with safety
requirements, the designer needs to make the power output
capability independent from the input conditions. A possible
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
June, 2008 − Rev. 0
AND8331/D
AND8331/D
way of doing it is call Over Power Protection (OPP). The
By applying this voltage through a resistor divider on the
OPP pin, we have an image of the input voltage transferred
to the controller via this pin. This voltage is added internally
to the 0.8 V reference and affects the maximum peak current
(see Figure 1). As the OPP voltage is negative, an increase
of input voltage implies a decrease of the maximum peak
current setpoint:
novel technique implemented in the DAP00X takes benefits
of the auxiliary winding voltage whose negative amplitude
relates to the input rail voltage. When the power MOSFET
is conducting, the auxiliary winding voltage becomes the
input voltage V affected by the auxiliary to primary turn ratio
IN
Naux
Np
ǒN
Ǔ:
+
p,aux
(eq. 2)
VCS,max + 0.8 ) VOPP
If OPP pin is grounded, there is no decrease of the peak
current setpoint.
Vaux + −Np,auxVIN
(eq. 1)
R
R
upper
CS
+
OPP
IpFlag
-
+
Aux
1
0.8 V + V
opp
ESD
Protection
+
lower
0.8 V
Figure 1. OPP Circuitry
The amount of negative voltage that can be applied on the
OPP pin is limited by the ESD diode placed on the pin to
protect the silicon. Temperature characterization shows that
But knowing the amount of current that will circulate
inside the OPP diode for these values of V , it is possible
OPP
to set a higher bias current inside the resistor divider in order
to neglect the diode leakage for OPP voltage lower than
−300 mV. Figure 2 shows the diode leakage at different
this diode will start to conduct if the applied bias (V ) is
OPP
lower than −300 mV. Thus, if a voltage lower than −300 mV
is applied on the OPP pin, the peak current decrease will no
longer be linear.
junction temperatures according to V . In any case, it is
OPP
forbidden to inject current higher than 2 mA in this pin
otherwise, substrate injections could occur, leading to a
possible erratic behaviour.
100
90
80
70
125°C
60
50
40
30
20
10
0
110°C
25°C
0.20
0.25
0.30
0.35
0.40
0.45
(V)
0.50
0.55
0.60
0.65
V
OPP
Figure 2. OPP Diode Leakage Current vs. VOPP at TJ = 255C, 1105C, 1255C
In order to filter the switching noise on OPP signal, the designer can add a small capacitor between OPP and GND. This
capacitor value can be adjusted according to the power MOSFET on-time duration at high line and must not be higher than 200 pF.
http://onsemi.com
2
AND8331/D
2. OPP Resistors Calculation
Let us assume the design needs a peak current reduction of 34% at 370 V dc, therefore, the amount of voltage we must apply
on pin 2 is:
VOPP + −0.8 0.34 + −272 mV
(eq. 3)
By using the resistor divider law on R
, R
we obtain:
upper lower
Rlower
Rupper * Rlower
VOPP + *
Np,auxVIN
(eq. 4)
Or:
Rupper
Np,aux
V
IN * VOPP
+ *
(eq. 5)
(eq. 6)
Rlower
VOPP
If our auxiliary to primary turn ratio is 0.12, we obtain:
Rupper
Rlower
0.12 370 * (−0.272)
−0.272
+ *
[ 164
Thus, we can select:
= 160 kW and R
R
= 1 kW
lower
upper
The bridge current during the on time is:
VOPP
Rlower
Ibridge
Ibridge
+
+
(eq. 7)
(eq. 8)
0.272
1000
+ 272 mA
3. Why is the OPP Non Dissipative?
Let us try to calculate the average current in the OPP bridge:
Tsw
Vaux(t)
Rupper ) Rlower
1
Tsw
(eq. 9)
ŕ
Ť
Ťdt
Ibridge,mean
+
0
After some calculations, we obtain:
T
Ton
off (VCC
Tsw
1
ǒ
) V )Ǔ
(eq. 10)
Ibridge,mean
+
Np,auxVIN )
f
Rupper ) Rlower Tsw
Keeping up with our example from before, we can measure T , T , T on our adapter at 370 V dc, light output load (we
on off sw
are in VCO mode): T = 1.2 ms, T = 3.6 ms, T = 40 ms
on
off
sw
1.2 m
160 k ) 1 k 40 m
3.6 m
40 m
1
ǒ
25.6Ǔ+ 2.26 mA
(eq. 11)
Ibridge,mean
+
0.12 370 )
If we had selected R
= 100 W and R
= 16 kW (meaning we impose a higher bias current in the resistor bridge), we
lower
upper
would have I
= 22.6 mA only!
bridge
4. OPP Trick
From our previous example, we have calculated the OPP resistors in order to have a peak current reduction of 34% at 370 V
dc that corresponds to V = -272 mV.
OPP
We obtained: R
= 1 kW and R
= 160 kW
lower
upper
Now, with these resistors what will be the peak current reduction at 110 V dc?
Rlower
Rupper ) Rlower
1
161
VOPP + −
Naux,pVIN
+
0.12 110 + 82 mV
(eq. 12)
This corresponds to a peak current reduction of 10.2% at low line. However because of the internal propagation delay, the
peak current reduction is smaller is reality.
http://onsemi.com
3
AND8331/D
I
pk
Set Point
I
pk
Set Point
100%
90%
100%
90%
66%
66%
110
220
370
110
370
V
IN
(V)
V
IN
(V)
Figure 5. Ipk Set Point over Input Voltage using a
Zener in Series with the OPP Resistors
Figure 3. Peak Current Set Point over the Input
Voltage with Rupper = 160 kW and Rlower = 1 kW
Design Example:
We want to start reducing the maximum peak current
around 220 V dc (roughly 155 Vrms).
If we want to avoid losing 10% maximum of peak current
at low line, we can introduce a simple threshold in the OPP
circuitry through a zener diode placed in series with the
resistive divider as shown in Figure 4.
This extra diode allows selecting the input voltage at
which we want to start applying over power compensation.
This corresponds to an auxiliary winding voltage:
(eq. 13)
Vaux + −Np,auxVIN + −0.12 220 + −26.4 V
So we need a zener diode with a breakdown voltage:
BVDZ + 0.12 (370 * 220) + 18 V
(eq. 14)
The new values for OPP resistors can be calculated using
Equation 15:
Zener
Rupper
Rlower
Np,aux
V
IN * BVDZ * VOPP
(eq. 15)
+ *
OPP
R
upper
VOPP
Aux
Rupper
Rlower
0.12 370 * 18 * (−0.272)
−0.272
R
(eq. 16)
+ *
+ 98
R
lower
bias
Cdec
We choose: R
= 100 kW and R
= 1 kW
upper
lower
II. Over Temperature Protection
Figure 4. OPP with Zener Diode
The adapter operating in a confined area, e.g. the plastic
case protecting the converter, it is important to look after the
internal ambient temperature. If this temperature would
increase beyond a certain point, catastrophic failures could
occur through semiconductors thermal runaway or
transformer saturation. To prevent this from happening, the
DAP00X embeds a novel Over Temperature Protection
(OTP) circuitry appearing in Figure 6.
V
DD
OVP Comp
20 ms Filter
End of
Soft−start
Ilatch
2
-
+
OTP
Cfilt
+
VOTP
NTC
Figure 6. OTP Schematic
http://onsemi.com
4
AND8331/D
The I
current (91 mA typ.) biases the Negative
During start-up and soft-start, the output of the OTP
comparator is masked to allow the voltage on pin OTP to
grow if a filtering capacitor is installed across the NTC.
The filtering capacitor value should be 1 nF.
latch
Temperature Coefficient sensor (NTC), naturally imposing
a dc voltage on the OTP pin. When the temperature
increases, the NTC’s resistance reduces (at 110°C, R
=
NTC
8.8 kW instead of 470 kW at 25°C) bringing the pin 2 voltage
down until it reaches a typical value of 0.8 V: the comparator
trips and latches-off the controller (Figure 7). Controller
In DAP013, the OTP trip point corresponds to a resistance of:
VOTP
0.8
RNTC
+
+
+ 8.79 kW
(eq. 17)
Ilatch
91 m
reset occurs when a) the V is cycled from on to off b) the
CC
brown-out pin senses a stop condition on the bulk voltage.
This corresponds to a temperature of 110°C using the
TTC03-474.
VCC
VDRV
VOTP
Figure 7. Capture of an OTP Event. Here, the NTC was Heated with a Hairdryer...
III. Timer Pin and Fault Management
Protection against short-circuit or overload is insured by
monitoring the current sense signal. The controller reaction
is thus fully independent from the auxiliary to power
comes back within safe limits, the “Max Ip” comparator
becomes silent and the PWM comparator triggers the
discharge of the timer capacitor. The timer capacitor is thus
winding coupling. When the primary current exceeds I
,
discharged by a constant current I . The internal
timerD
Limit
the “Max Ip” comparator trips and the timer capacitor
charges by the I current source. When the current
circuitry appears in Figure 8.
timerC
http://onsemi.com
5
AND8331/D
HV
Vcc
Vcc Management
S
R
Vdd
Q
Q
DRV
Fault
I
I
timerC
PNOK
PWM
Reset
Timer
PWM
Comparator
+
CS
-
+
C
timer
timerD
-
+
FB/4
R
S
Vtim Fault
Q
Q
Max Ip
Comparator
IpFlag
+
OPP
-
+
Ilimit + Vopp
+
I
limit
Figure 8. Timer Circuitry
For D and F versions, when the voltage of timer capacitor reaches V , the output pulses are stopped and the controller
timFault
tries to re-start via a triple hiccup. (see Figure 9): this is the so-called auto-recovery operation.
VCC
Vdrain
4.5 s
Vtimer
93 ms
Figure 9. The Triple Hiccup in Fault Mode
The triple hiccup helps to reduce the power consumption
in fault mode. In Figure 9, the burst is only 2% for a 60 W
For versions A and C, when V
controller stops pulsing and stays latched. To reset the
controller, the user must unplug the power supply to allow
reaches V
, the
timer
timFault
adapter (with C
= 100 mF).
Vcc
V
CC
to drop below V
level (5.5 V). (see Figure 10)
CCreset
http://onsemi.com
6
AND8331/D
VCC
VDRV
5 V fault threshold
VTimer
Figure 10. The Latched Short-circuit Protection in A and C Versions
Choosing Timer Duration and Timer Capacitor
Where :
While choosing the timer duration, the user must ensure
that it is long enough to allow the power supply to enter
regulation at low line and full load. (see Figure 11)
The timer capacitor value can be calculated with:
− T
is the duration before the fault validation
is the charging current (10 mA typ. from
fault
− I
timerC
datasheet)
− V
is the timer voltage threshold at which the
timFault
fault is validated (5 V typ. from datasheet)
Tfault timerC
VtimFault
I
Ctimer
+
(eq. 18)
VtimFault = 5 V
VFB
1 V
Softstart
Vtimer
VOUT
Vdrain
Figure 11. Timer Margin at Low Line, Full Load on a 19 V / 3 A Adapter
IV. Zero Voltage Crossing Detection
The Zero Crossing Detection circuit (ZCD) allows turning
on the power MOSFET when the drain-source voltage is the
lowest. This detection is achieved by monitoring the auxiliary
winding voltage. The typical detection level is around 50 mV
(Figure 12). By delaying this signal thanks to an RC network
(the internal ESD protection features a parasitic capacitance
of 10 pF) it is possible to switch right in the valley of the
drain-source voltage.
http://onsemi.com
7
AND8331/D
VZCD
V
Th
Figure 12. Typical ZCD Signal. Here, the Power
Supply Operates in 2nd Valley
ZCD
Rdem
Resd
+
-
demag
+
Vth
Aux
Cdem
Dz
ESD
Tblank
GND
DRV
Leakage Blanking
Figure 13. Zero Voltage Crossing Detection Circuit
R
should be calculated to limit the current inside pin
V. VCO Mode and Timing Capacitor
1. How Does it Work?
dem
4 to less than +3 mA/-2 mA.
For example, if the voltage on auxiliary winding is –45 V
At nominal power, the power supply operates in a variable
frequency system where discrete frequency steps occur as
the controller looks for the different valley positions. At low
output power, the controller enters a Voltage-Controlled
Oscillator (VCO) mode where the switching frequency is
at highest line, R
22.5 kW.
In order to avoid false triggering by the leakage
inductance, a blanking circuit masks the ZCD signal during
2 to 4 ms. So when designing the power supply, the designer
must ensure that during valley operation, the
demagnetization duration is higher than 4 ms. If not, the 1
valley will also be blanked and valley switching instabilities
will occur.
should be higher than 45/0.002 =
dem
folded back. This mode is entered when V drops below
FB
0.8 V. The controller remains in this mode until V
st
FB
increases above 1.4 V. During the VCO operation (V
<
FB
0.8 V), the peak current is frozen to 25% of its maximum
value and the frequency diminishes as the output power
decreases. (Figure 14)
http://onsemi.com
8
AND8331/D
Figure 14. Idrain, Vdrain, VCt, at Different Output Loads in VCO Mode
The switching frequency is set by the end of charge of the
timing capacitor C . This capacitor is charged by a constant
0 V and a new period starts. The relationship between FB
voltage and the internal threshold is:
t
current source I and its voltage V is compared to an
Ct
Ct
VFBth + 6.5 * (10ń3)VFB + VCt
(eq. 19)
internal threshold fixed by the FB loop. When V reaches
Ct
the threshold, the capacitor is rapidly discharged down to
V
DD
VCO
Rpullup
FB
V
FBth
6.5 − (10/3) Vfb
-
+
V
DD
DRV
S
R
Q
Q
ICt
Ct
Ct Discharge
CS Comparator
Figure 15. VCO Schematic
th
2. How to Calculate the Timing Capacitor Value?
the switching frequency in the 4 valley and the switching
The timing capacitor must be selected with care. Indeed,
when the controller leaves the valley switching mode to
enter the VCO mode, the frequency changes from a
valley-position-controlled value to a switching frequency
frequency imposed by the C capacitor, the frequency jump
t
may create an instability by forcing the peak current to leave
th
its frozen state: an hesitation between 4 valley and the
VCO mode takes place (Figure 16) and can create output
ripple and noise.
imposed by the C capacitor. If a too big gap exists between
t
http://onsemi.com
9
AND8331/D
th
Figure 17 shows a normal transition from 4 valley to the
VCO mode. At the beginning, the output load is such that it
th
imposes a V near 0.8 V in 4 valley operation, with a
VFB
FB
switching period T . Then, if the load is slightly
sw1
Vdrain
decreased, the FB voltage also passes below the 0.8 V
threshold: the VCO mode is entered and the switching
frequency decreases. (In VCO mode, the switching
frequency is imposed by the FB voltage regardless of the
position in the drain signal). The controller will stay in VCO
mode until the FB voltage increases above 1.4 V. If we have
an optimum timing capacitor value, the new steady state
point is such that V is near 1.4 V and imposes a switching
FB
period T larger than T
.
sw2
sw1
th
VCO mode
4
valley
Figure 16. The Controller Hesitates between VCO
Mode and 4th Valley: Ct is Too Big!
Load
V
FB
1.4 V
0.8 V
V
FBth
T
sw2
T
sw1
4th Valley
VCO Mode
Figure 17. 4th Valley to VCO Mode Transition with an Optimum Timing Capacitor Ct
th
To calculate C , we first need to estimate the switching period at the end of the 4 valley operation, for a FB voltage near
t
0.8 V by using Equation 20 or by directly measuring it on our adapter:
Nps
0.2
Rsense
1
) 7p Ǹ
Tsw1
+
Lp
ǒ
)
Ǔ
LpClump
(eq. 20)
VIN,minDC Vout ) Vf
Where:
− R
− N = N /N is the primary to secondary turn ratio of
ps s p
is the sense resistor
the transformer
− V is the output voltage
sense
− 0.2 relates to the voltage setpoint on the current-sense
comparator when V = 0.8 V.
out
− V is the output diode forward voltage
FB
f
− L is the primary inductance
− C
regroups all capacitances surrounding the drain
p
lump
− V
is the minimum DC input voltage, bulk
node (MOSFET capacitor, transformer parasitics...). As
a first approximation, you can use the MOSFET
IN,minDC
ripple included
drain-source capacitance C
instead of C
.
OSS
lump
http://onsemi.com
10
AND8331/D
Based on lab experiments, the switching period gap
Thus, we can deduce the timing capacitor value knowing
V , T and the charging current source I (20 mA typ.
Ct sw2 Ct
th
between the end of 4 valley operation (T ) and VCO
sw1
mode (T ) for a FB voltage near 1.4 V (which is the
from datasheet):
sw2
th
threshold for VCO mode to 4 valley transition, V
FB
ICtTsw2
1.83
Ct +
(eq. 23)
increasing ) must not exceed 12 ms. Thus, for V = 1.4 V,
we will have:
FB
Application Example: 19 V/60 W Adapter
Tsw2 + Tsw1 ) 12 ms
(eq. 21)
• V
= 100 V
• V + V = 19 + 0.6 V
IN,minDC
Equation 13 allows calculating V for V = 1.4 V:
Ct
FB
out
f
VCt + 6.5 * (10ń3) 1.4 + 1.83 V
(eq. 22)
• L = 190 mH
p
• C
= 200 pF
lump
• N = 0.25
ps
• R
= 0.25
sense
First, with Equation 14, we estimate T
which is the
sw1
switching period of our power supply for an output load
corresponding to a V = 0.8 V:
FB
Nps
0.2
1
) 7p Ǹ
Tsw1
+
+
LP
ǒ
)
Ǔ
0.25
LpClump
(eq. 24)
Rsense
VIN,minDC Vout ) Vf
0.2
1
Ǹ
190 10*6
)
200 10*12 + 7.75 ms (129 kHz)
*6
ǒ100 19 ) 0.6Ǔ) 7p 190 10
0.25
When measured on the adapter we have: T = 8.47 ms (F
= 118 kHz) corresponds to an ouput power of 9 W.
sw1
sw1
We calculate the timing capacitor value:
20 10*6(7.75 10*6 ) 12 10*6
)
ICT(Tsw1 ) 12 m)
(eq. 25)
Ct +
+
+ 216 pF
1.83
1.83
We select C = 220 pF.
t
VI. Feedback
The feedback pin features an internal pull-up resistor
which connects to the optocoupler, as shown in Figure 18.
This pin is also connected to the internal valley comparators
that will select the operating valley according to the FB
voltage (see datasheet).
It is recommended to add a capacitor between FB pin and
GND pin of the controller. This capacitor has two
advantages: it offers a filtering action on the FB signal and
it forms with R
a pole located at:
pullup
1
fp +
(eq. 26)
2p RpullupCpole
This pole will help you to stabilize the power supply.
Rpullup
FB
VII. VCC
+
V
The DAP013 includes a high voltage startup circuitry that
derives current from the bulk line to charge the V
capacitor. When the power supply is first connected to the
mains outlet, the internal current source is biased and
DD
5 V
CC
Cpole
GND
charges up the V capacitor. When the voltage on this V
CC
CC
Figure 18. FB Pin Features an Internal Pull-up
Resistor...
The pull-up resistor value is typically around 20 kW and
capacitor reaches the V
level, the current source turns
CCon
off, reducing the amount of power being dissipated. At this
time, the controller is only supplied by the V capacitor,
CC
is referenced in the datasheet.
and the auxiliary supply should take over before V
CC
collapses below V
. Figure 19 shows the internal
CCmin
arrangement of this structure:
http://onsemi.com
11
AND8331/D
14
Where:
HV
− I
is the controller consumption (see datasheet)
CC2
− Q is the MOSFET total gate charge
g
− F is the switching frequency in maximum load,
sw
+
minimum input voltage
IC1 or IC2
-
Now, we need to estimate the total startup time.
The high voltage startup circuit features two startup
10
8
+
levels, I and I . At power-up, as long as V is below
C1
C2
CC
V
(0.70 V typ.), the source delivers I (around 300 mA
Th
C1
V
V
CCon
+
typical). The duration is:
CCmin
VTh
IC1
t1 + CVcc
(eq. 28)
Then, when V reaches 0.70 V, the source smoothly
CC
transitions to I (6 mA typ.) and delivers its nominal value.
C2
When V reaches V
, the source is turned-off:
CC
CCon
Figure 19. Startup Circuitry
1. How to Choose VCC Capacitor?
VCCon * VTh
t2 + CVcc
(eq. 29)
IC2
The V capacitor is calculated to allow the power supply
The total startup time is the sum of t , t and t
.
CC
1
2
reg
to close the loop before V drops to V
the time needed by the power supply to close the loop, the
. If we call t
CC
CCmin
reg
VCCon * VTh
VTh
IC1
ǒ
Ǔ
tstartup + CVcc
)
) treg (eq. 30)
IC2
V
CC
capacitor can be estimated with:
(ICC2 ) QgFsw)treg
VCCon * VCCmin
For Example:
CVcc
+
(eq. 27)
The time needed by the power supply to enter regulation
is 45 ms worst case (full load).
The MOSFET is a 6A / 600 V with a gate charge:
Q = 24 nC
g
(2.5 10*3 ) 24 10*9 65000) 45 10*3
15 * 9
(ICC2 ) QqFsw)treg
VCCon * VCCmin
(eq. 31)
CVcc
+
+
+ 30.45 mF
We choose: C
= 47 mF
Vcc
VCC
IC2
VOUT
VTh
IC1
t1
t2
treg
Figure 20. The Dual Level Startup Current Source in Action, Here with a Vcc Capacitor of 100 mF
http://onsemi.com
12
AND8331/D
2. What is the Benefit of Using a Dual Level Startup Current Source?
The dual level startup current source allows to limit the
power dissipation of the controller in case of short-circuit
to the highest T ), the device would dissipate 370 x 3 m =
J
1.11 W.
Thanks to the dual level startup, the current source deliver
I = 300 mA if V is below 0.70 V. Thus, in case of
C1
between V and GND.
CC
Without the dual level startup, in high line conditions
cc
(V = 370 V dc), the current delivered by the startup device
short-circuit between V and GND, the power dissipation
HV
CC
will seriously increase the junction temperature. For
will drop to 370 x 300u = 111 mW.
instance, since I equals 3 mA (the minimum corresponds
C2
VIII. Brown Out
The C and D versions of DAP013 feature a Brown Out pin
(BO) which protects the power supply against low input
voltage conditions (Figure 21). This pin permanently
monitors a fraction of the bulk voltage through a voltage
divider. When this image of bulk voltage is below the BO
threshold, the controller stops switching. When the bulk
voltage comes back within safe limits, the circuit goes
through a new startup sequence including soft-start and
re-starts switching (Figure 24). The hysteresis on brown-out
pin is implemented with a low side current source sinking
10 mA when the brown-out comparator is low (V
<
bulk
V
). This offers adequate precision at shutdown.
bulk(ON)
HV−bulk
+
VBO
20 ms Noise Delay
R
upper
BO Reset
BO
11
-
+
BO Comp
R
lower
IBO
IBO “on” if BO Comp “low”
IBO “off” if BO Comp “high”
Figure 21. Brown-Out Circuit
1. Calculating the BO Resistors
V
V
bulk(ON)
bulk(OFF)
R
R
upper
upper
BO
11
BO
11
iu
il
iu
ibo
iu
IBO
R
R
lower
lower
Figure 22. Brown-out Equivalent Schematic at Startup
Figure 23. Brown-out at Shutdown
First of all, select the bulk voltage value at which the
When V
reaches V
, the hysteresis current
bulk
bulk(ON)
controller must start switching (V
) and the bulk
source is turned OFF. Thus, at shutdown, the BO voltage
bulk(ON)
voltage for shutdown (V
we have:
). According to Figure 22,
only depends of V
and R
Rlower
Rupper ) Rlower
, R
(Figure 23).
bulk(OFF)
bulk(OFF)
upper lower
VBO
+
Vbulk(OFF)
(eq. 34)
iu + il ) IBO
(eq. 32)
Deducing R
expression in Equation 33. We obtain:
from Equatio 34, we replace R
by its
upper
upper
Where: I is the brown-out hysteresis current.
BO
By replacing i and i by their values, the previous
u
l
V
BO(Vbulk(ON) * Vbulk(OFF))
equation becomes:
Rlower
+
+
(eq. 35)
(eq. 36)
Vbulk(ON) * VBO
IBO(Vbulk(OFF) * VBO)
VBO
Rlower
+
) IBO
(eq. 33)
Rupper
R
lower(Vbulk(OFF) * VBO
)
Rupper
VBO
http://onsemi.com
13
AND8331/D
Design Example
* VBO + 0.8 V
V
BO(Vbulk(ON) * Vbulk(OFF)
)
0.8(120 * 60)
10 m(60 * 0.8)
(eq. 37)
(eq. 38)
Rlower
+
+
+
+ 81.1 kW
* IBO + 10 mA
IBO(Vbulk(OFF) * VBO
)
* Vbulk(ON) + 120 V
* Vbulk(OFF) + 60 V
R
lower(Vbulk(OFF) * VBO
)
81.1 k (60 * 0.8)
Rupper
+
+ 6 MW
0.8
VBO
VCC
I
V
turnson when
is high enough
BO
CC
VBO
Vbulk
BO threshold
VDRV
I
turnsoff
BO
Figure 24. BO at Startup. The Controller Starts Pulsing if VBO > BO Threshold and VCC > VCCon
IX. Over Voltage Protection
The DAP013 also provides a protection against an over voltage condition (OVP), e.g. in case of the optocoupler destruction
(Figure 25).
VCC
Vcc
Ru
Rl
OVP
12
20 us filter
+
or
Rbias
−
Vovp
Figure 25. OVP Circuit
The OVP pin (12) is connected to an internal comparator that will latch the controller if a voltage higher than 3 V is applied
on this pin. Once the controller is latched, the user must unplug the power supply to allow V falling below V
(around
CC
CCreset
5 V) to reset the controller.
As pin 12 is high impedance, the over voltage protection can be implemented also by using a resistor divider instead of the
traditional zener diode.
http://onsemi.com
14
AND8331/D
VCC
VDRV
OVP threshold
VOVP
Figure 26. Scope Shot of an Over voltage Event. Here, the OVP
was Implemented with an 18 V Zener Diode
X. Typical Application Schematic
The schematic in Figure 27 shows the implementation of DAP013 inside a 19 V/60 W power supply.
U4
KBU4K
C14
100u
L
D2
MBR20200
L3
2.2u
FL1
Vout
Gnd
+
T1
C1
10n
C9
X2
220nF
IN
C18
100nF
R4
6.8k 6.8k
D1
R12
N
C5a
+
+
+
R1
−
C7
100uF
25V
C5b
10
R23
6Meg
1.2mF
35V
1.2mF
35V
1N4937
R25, 6.8k
U1
DAP013D
R18
8.2k
R30
270k
C15
2.2nF
C6
22p
Type = Y1
Gnd
R9
1k
14
13
12
1
2
3
4
5
6
7
Lp = 190 mH
Nps = 0.25
Nauxp = 0.22
D6
1N967
R22
3Meg
R5
27k
U5
NTC
R15
1k
R7
U2a
11
10
M1
1N4937
10
C4
330p
D5
R16
SPP06N60
9
8
39k
R31
1k
C10
47n
C17
1n
D3
R17
22k
R21
82k
R3
U2b
C5
1n
47k
C13
220n
1N4148
+
C20
R29
1k
U3
C11
33u
R8
10k
R26
0.5
R27
0.5
100n
TL431
C8
220p
Gnd
Figure 27. 19 V /60 W Power Supply Schematic with DAP013D
Conclusion
This controller associate a quasi-resonant operation mode
for high output loads with a VCO mode to improve the
efficiency of the power supply at light loads.
This application note has described in detail how to select
the components surrounding the DAP013.
The DAP013 contains all the features (OPP, OVP, OTP,
short-circuit protection, BO...) to build high performance
ac-dc power supplies.
http://onsemi.com
15
AND8331/D
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
AND8331/D
相关型号：
©2020 ICPDF网 联系我们和版权申明