AMIS42700WCGA4RH [ONSEMI]
双 CAN 收发器，高速;
| 型号： | AMIS42700WCGA4RH |
| 厂家： | 
ONSEMI |
| 描述： | 双 CAN 收发器，高速 电信 光电二极管 电信集成电路 |
| 文件： | 总15页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMIS-42700
Dual High Speed CAN
Transceiver
General Description
Controller area network (CAN) is a serial communication protocol,
which supports distributed real−time control and multiplexing with
high safety level. Typical applications of CAN−based networks can be
found in automotive and industrial environments.
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PIN CONFIGURATION
The AMIS−42700 Dual−CAN transceiver is the interface between
up to two physical bus lines and the protocol controller and will be
used for serial data interchange between different electronic units at
more than one bus line. It can be used for both 12 V and 24 V systems.
The circuit consists of following blocks:
• Two differential line transmitters
• Two differential line receivers
1
2
20
19
18
17
16
15
14
13
12
11
NC
EN2
Text
Tx0
NC
CANH2
CANL2
GND
3
4
5
GND
GND
Rx0
GND
• Interface to the CAN protocol handler
• Interface to expand the number of CAN busses
• Logic block including repeater function and the feedback suppression
• Thermal shutdown circuit (TSD)
6
GND
7
CANL1
CANH1
VCC
8
Vref1
Rint
9
• Short to battery treatment circuit
Due to the wide common−mode voltage range of the receiver inputs,
the AMIS−42700 is able to reach outstanding levels of
electromagnetic susceptibility (EMS). Similarly, extremely low
electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
10
EN1
NC
SOIC 20
WC SUFFIX
CASE 751AQ
Key Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
• Fully compatible with the ISO 11898−2 standard
• Certified “Authentication on CAN Transceiver Conformance (d1.1)”
• High speed (up to 1 Mbit/s in function of the bus topology)
• Ideally suited for 12 V and 24 V industrial and automotive
applications
• Low EME common−mode−choke is no longer required
• Differential receiver with wide common−mode range ( 35 V) for
high EMS
• No disturbance of the bus lines with an un−powered node
• Dominant time−out function
• Thermal protection
• Bus pins protected against transients in an automotive environment
• Short circuit proof to supply voltage and ground
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
January, 2009 − Rev. 5
AMIS−42700/D
AMIS−42700
Table 1. Technical Characteristics
Symbol
Parameter
Conditions
0 < V < 5.25 V; no time limit
Min.
−45
−45
1.5
Max.
+45
+45
3
Unit
V
V
DC voltage at pin CANH1/2
CANHx
CC
V
CANLx
DC voltage at pin CANL1/2
0 < V < 5.25 V; no time limit
V
CC
V
Differential bus output voltage in dominant state
Input common−mode range for comparator
42.5 W < R < 60 W
V
o(dif)(bus_dom)
LT
CM−range
Guaranteed differential receiver
threshold and leakage current
−35
+35
V
V
Common−mode peak
Common−mode step
See Figures 9 and 10 (Note 1)
See Figures 9 and 10 (Note 1)
−1000 1000
−250 250
mV
mV
CM−peak
V
CM−step
1. The parameters V
and V
guarantee low EME.
CM−peak
CM−step
VCC
12
Thermal
shutdown
POR
clock
AMIS−42700
13
19
18
CANH1
CANH2
CANL2
Timer
Timer
CANL1
14
Driver
control
Driver
control
Logic
Unit
Ri(cm)
Ri(cm)
Vcc/2
+
Vcc/2
+
COMP
COMP
Ri(cm)
Ri(cm)
VCC
VCC
VCC
VCC
8
10
3
2
5
15
16 17
7
6
4
9
VREF
Rint
GND
Tx0 Rx0
ENB2
ENB1 Text
Figure 1. Block Diagram
Typical Application
Application Description
AMIS−42700 is especially designed to provide the link
between a CAN controller (protocol IC) and two physical
busses. It is able to operate in three different modes:
• Dual CAN
• A CAN−bus extender
• A CAN−bus repeater
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2
AMIS−42700
Application Schematics
VBAT
CAN BUS 1
CAN BUS 2
5V−reg
CD
100 nF
Vref
VCC
CANH1
12
8
EN1
EN2
Rx0
Tx0
Text
Rint
13
10
2
RLT
60 W
CANL1
CANH2
14
19
7
AMIS−42700
4
RLT
3
60 W
CANL2
9
18
5
6
15 16 17
GND
Figure 2. Application Diagram CAN−bus Repeater
VBAT
CAN BUS 1
CAN BUS 2
5V−reg
CD
CD
100 nF
100 nF
VCC
VCC
Vref
13
CANH1
12
8
EN1
10
2
RLT
EN2
Rx0
60 W
CANL1
CANH2
14
19
7
mC
AMIS−42700
Tx0
CAN
con−
troller
4
Text
RLT
3
Rint
60 W
CANL2
9
18
5
6
15 16 17
GND
GND
Figure 3. Application Diagram Dual−CAN
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3
AMIS−42700
VBAT
CAN BUS 1
CAN BUS 2
5V−reg
CD
CD
100 nF
100 nF
Vref
+5
VCC
VCC
CANH1
12
8
EN1
13
10
2
RLT
EN2
Rx0
Tx0
Text
60 W
CANL1
CANH2
14
AMIS−42700
19
7
mC
CAN
con−
troller
4
3
9
RLT
Rint
60 W
CANL2
+5
18
5
6 15 16 17
GND
GND
CAN BUS 3
CAN BUS 4
CD
100 nF
VCC
Vref
CANH1
12
8
EN1
EN2
Rx0
13
10
2
RLT
60 W
CANL1
CANH2
14
19
7
AMIS−42700
Tx0
Text
4
RLT
3
Rint
60 W
CANL2
9
18
5
6
15 16 17
GND
Figure 4. Application Diagram CAN−bus Extender
Table 2. Pin Out
Pin
1
Name
NC
Description
Not connected
2
ENB2
Text
Enable input, bus system 2; internal pull−up
Multi−system transmitter Input; internal pull−up
Transmitter input; internal pull−up
Ground connection (Note 2)
Ground connection (Note 2)
Receiver output
3
4
Tx0
5
GND
GND
Rx0
6
7
8
V
REF1
Reference voltage
9
Rint
ENB1
NC
Multi−system receiver output
Enable input, bus system 1; internal pull−up
Not connected
10
11
12
13
14
15
16
17
18
19
20
VCC
Positive supply voltage
CANH1
CANL1
GND
CANH transceiver I/O bus system 1
CANL transceiver I/O bus system 1
Ground connection (Note 2)
Ground connection (Note 2)
Ground connection (Note 2)
CANL transceiver I/O bus system 2
CANH transceiver I/O bus system 2
Not connected
GND
GND
CANL2
CANH2
NC
2. In order to ensure the chip performance, all these pins need to be connected to GND on the PCB.
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AMIS−42700
Functional Description
Overall Functional Description
not connected or is accidentally interrupted. A dominant
state on the bus line is represented by a low-level at the
digital interface; a recessive state is represented by a
high-level.
Dominant state received on any bus (if enabled) causes a
dominant state on both busses, pin Rint and pin Rx0.
Dominant signal on any of the input pins Tx0 and Text
causes transmission of dominant on both bus lines (if
enabled).
Digital inputs Tx0 and Text are used for connecting the
internal logic’s of several IC’s to obtain versions with more
than two bus outputs (see Figure 4: Application Diagram
CAN-bus Extender). They have also a direct logical link to
pins Rx0 and Rint independently on the EN1x pins −
dominant on Tx0 is directly transferred to both Rx0 and Rint
pins, dominant on Text is only transferred to Rx0.
AMIS−42700 is specially designed to provide the link
between the protocol IC (CAN controller) and two physical
bus lines. Data interchange between those two bus lines is
realized via the logic unit inside the chip. To provide an
independent switch−off of the transceiver units for both bus
systems by a third device (e.g. the mC), enable−inputs for the
corresponding driving and receiving sections are provided.
As long as both lines are enabled, they appear as one logical
bus to all nodes connected to either of them.
The bus lines can have two logical states, dominant or
recessive. A bus is in the recessive state when the driving
sections of all transceivers connected to the bus are passive.
The differential voltage between the two wires is
approximately zero. If at least one driver is active, the bus
changes into the dominant state. This state is represented by
a differential voltage greater than a minimum threshold and
therefore by a current flow through the terminating resistors
of the bus line. The recessive state is overwritten by the
dominant state.
In case of a fault (like short circuit) is present on one of the
bus lines, it remains limited to that bus line where it occurs.
Data interchange from the protocol IC to the other bus
system and on this bus system itself can be continued.
AMIS−42700 can be also used for only one bus system. If
the connections for the second bus system are simply left
open it serves as a single transceiver for an electronic unit.
For correct operation, it is necessary to terminate the open
bus by the proper termination resistor.
Transmitters
The transceiver includes two transmitters, one for each
bus line, and a driver control circuit. Each transmitter is
implemented as a push and a pull driver. The drivers will be
active if the transmission of a dominant bit is required.
During the transmission of a recessive bit all drivers are
passive. The transmitters have a built−in current limiting
circuit that protects the driver stages from damage caused by
accidental short circuit to either positive supply voltage or
to ground. Additionally a thermal protection circuit is
integrated.
The driver control circuit ensures that the drivers are
switched on and off with a controlled slope to limit EME.
The driver control circuit will be controlled itself by the
thermal protection circuit, the timer circuit and the logic
unit.
Logic Unit and CAN Controller Interface
The logic unit inside AMIS−42700 provides data transfer
from/to the digital interface to/from the two busses and from
one bus to the other bus. The detailed function of the logic
unit is described in Table 3.
All digital input pins, including ENBx, have an internal
pull-up resistor to ensure a recessive state when the input is
The enable signal ENBx allows the transmitter to be
switched off by a third device (e.g. the mC). In the disabled
state (ENBx = high) the corresponding transmitter behaves
as in the recessive state.
Table 3. Function of the Logic Unit (bold letters describe input signals)
EN1B
EN2B
TX0
0
TEXT
Bus 1 State
dominant
Bus 2 State
dominant
RX0
0
RINT
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
1
0
0
0
dominant
dominant
0
1
dominant
dominant
0
1
recessive
recessive
1
1
dominant (Note 3)
dominant
dominant
0
1
dominant (Note 3)
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
dominant
dominant
recessive
recessive
recessive
recessive
recessive
0
0
0
1
0
0
0
1
1
0
dominant
recessive
dominant (Note 3)
3. Dominant detected by the corresponding receiver.
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AMIS−42700
Table 3. Function of the Logic Unit (bold letters describe input signals)
EN1B
EN2B
TX0
TEXT
Bus 1 State
Bus 2 State
RX0
RINT
0
1
1
1
recessive
dominant (Note 3)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
1
1
recessive
recessive
dominant
dominant
0
0
0
1
1
0
0
0
1
1
1
0
recessive
dominant
recessive
recessive
dominant (Note 3)
recessive
recessive
dominant (Note 3)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
recessive
recessive
recessive
recessive
0
0
0
1
1
1
0
0
1
1
1
1
recessive
recessive
recessive
recessive
dominant (Note 3)
recessive
recessive
dominant (Note 3)
3. Dominant detected by the corresponding receiver.
Receivers
on that bus line, on which a dominant is actively transmitted.
The reception becomes active again only with certain delay
after the dominant transmission on this line is finished.
Two bus receiving sections sense the states of the bus
lines. Each receiver section consists of an input filter and a
fast and accurate comparator. The aim of the input filter is
to improve the immunity against high−frequency
disturbances and also to convert the voltage at the bus lines
CANHx and CANLx, which can vary from –12 V to +12 V,
to voltages in the range 0 to 5 V, which can be applied to the
comparators.
Power−on−Reset (POR)
While Vcc voltage is below the POR level, the POR
circuit makes sure that:
• The counters are kept in the reset mode and stable state
without current consumption
The output signal of the comparators is gated by the ENBx
signal. In the disabled state (ENBX = high), the output signal
of the comparator will be replaced by a permanently
recessive state and does not depend on the bus voltage. In the
enabled state the receiver signal sent to the logic unit is
identical to the comparator output signal.
• Inputs are disabled (don’t care)
• Outputs are high impedant; only Rx0 = high−level
• Analog blocks are in power down
• Oscillator not running and in power down
• CANHx and CANLx are recessive
• VREF output high impedant for POR not released
Time−out Counters
To avoid that the transceiver drives a permanent dominant
state on either of the bus lines (blocking all communication),
time−out function is implemented. Signals on pins Tx0 and
Text as well as both bus receivers are connected to the logic
unit through independent timers. If the input of the timer
stays dominant for longer than parameter tdom, it’s replaced
by a recessive signal on the timer output.
Over Temperature Detection
A thermal protection circuit is integrated to prevent the
transceiver from damage if the junction temperature
exceeds thermal shutdown level. Because the transmitters
dissipate most of the total power, the transmitters will be
switched off only to reduce power dissipation and IC
temperature. All other IC functions continue to operate.
Feedback Suppression
Fault Behavior
The logic unit described in Table 3 constantly ensures that
dominant symbols on one bus line are transmitted to the
other bus line without imposing any priority on either of the
lines. This feature would lead to an “interlock” state with
permanent dominant signal transmitted to both bus lines, if
no extra measure is taken.
A fault like a short circuit is limited to that bus line where
it occurs; hence data interchange from the protocol IC to the
other bus system is not affected.
When the voltage at the bus lines is going out of the normal
operating range (−12 V to +12 V), the receiver is not allowed
to erroneously detect a dominant state.
Therefore a feedback suppression is included inside the
logic unit of the transceiver. This block masks−out reception
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AMIS−42700
Short Circuits
Reverse Electronic Unit (ECU) Supply
As specified in the maximum ratings, short circuits of the
bus wires CANHx and CANLx to the positive supply
voltage Vbat or to ground must not destroy the transceiver.
A short circuit between CANHx and CANLx must not
destroy the IC as well.
The dedicated comparator (L2VBAT) on CANL pin
detects the short to battery and after debounce time−out
switches off the affected driver only. The receiver of the
affected driver has to operate normally.
If the connections for ground and supply voltage of an
electronic unit (ECU) (max. 50 V) which provides Vcc for
the transceiver are exchanged, this transceiver has a ground
potential which may be up to 50 V higher than that of the
other transceivers. In this case no transceiver must be
destroyed even if several of them are connected via the bus
system.
Any exchange among the six connections CANH1,
CANH2, CANL1, CANL2, ground, and supply voltage of
the electronic unit at the connector of the unit must never
lead to the destruction of any transceiver of the bus system.
Faulty Supply
In case of a faulty supply (missing connection of the
electronic unit or the transceiver to ground, missing
connection of the electronic unit to Vbat or missing
connection of the transceiver to Vcc), the power supply
module of the electronic unit will operate such that the
transceiver is not supplied, i.e. the voltage Vcc is below the
POR level. In this condition the bus connections of the
transceiver must be in the POR state.
Electrical Characteristics
Definitions
All voltages are referenced to GND. Positive currents
flow into the IC. Sinking current means that the current is
flowing into the pin. Sourcing current means that the current
is flowing out of the pin.
If the ground line of the electronic unit is interrupted, Vbat
may be applied to the Vcc pin (measured relative to the
original ground potential, to which the other units on the bus
are connected).
Absolute Maximum Ratings
Stresses above those listed in Table 4 may cause
permanent device failure. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Conditions
Min.
−0.3
−45
Max.
+7
Unit
V
V
CC
Supply voltage
V
DC voltage at pin CANH1/2
DC voltage at pin CANL1/2
0 < V < 5.25 V; no time limit
+45
+45
V
CANHx
CC
V
CANLx
0 < V < 5.25 V; no time limit
−45
V
CC
V
DC voltage at digital IO pins (EN1B, EN2B,
Rint, Rx0, Text, Tx0)
−0.3
V
V
+ 0.3
V
digIO
CC
V
DC voltage at pin V
−0.3
−150
−150
+ 0.3
V
V
V
REF
REF
CC
V
Transient voltage at pin CANH1/2
(Note 4)
(Note 4)
+150
tran(CANHx)
V
Transient voltage at pin CANL1/2
+150
tran(CANLx)
esd(CANLx/CANHx)
V
ESD voltage at CANH1/2 and CANL1/2 pins
(Note 5)
(Note 7)
−4
−500
+4
+500
kV
V
V
esd
ESD voltage at all other pins
(Note 5)
(Note 7)
−2
−250
+2
+250
kV
V
Latch−up
Static latch−up at all pins
Storage temperature
(Note 6)
100
mA
°C
°C
°C
T
stg
−55
−40
−40
+155
+125
+150
T
amb
Ambient temperature
T
junc
Maximum junction temperature
4. Applied transient waveforms in accordance with “ISO 7637 part 3”, test pulses 1, 2, 3a, and 3b (see Figure 5).
5. Standardized human body model (HBM) ESD pulses in accordance to MIL883 method 3015. Supply pin 8 is 2 kV.
6. Static latch−up immunity: static latch−up protection level when tested according to EIA/JESD78.
7. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3−1993.
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AMIS−42700
Table 5. Thermal Characteristics
Symbol
Parameter
Conditions
In free air
In free air
Value
85
Unit
K/W
K/W
R
R
Thermal resistance from junction to ambient in SO20 package
Thermal resistance from junction to substrate of bare die
th(vj−a)
)
45
th(vj−s
Table 6. DC and Timing Characteristics (V = 4.75 to 5.25 V; T
= −40 to +150°C; R = 60 W unless specified otherwise.)
LT
CC
junc
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
SUPPLY (pin V
)
CC
I
Supply current, no loads on digital
outputs, both busses enabled
Dominant transmitted
Recessive transmitted
45
137.5
19.5
mA
V
CC
PORL_VCC
Power−on−reset level on V
2.2
4.7
CC
DIGITAL INPUTS (Tx0, Text, EN1B, EN2B)
V
High−level input voltage
Low−level input voltage
0.7 x V
−
−
V
CC
V
V
IH
CC
V
−0.3
0.3 x
IL
V
CC
I
High−level input current
Low−level input current
Input capacitance
V
= V
CC
−5
−75
−
0
−200
5
+5
mA
mA
pF
IH
IN
I
V
= 0 V
−350
IL
IN
C
Not tested
10
i
DIGITAL OUTPUTS (pin Rx0, Rint)
I
High−level output current
Low−level output current
V = 0.7 x V
−5
−10
−15
mA
mA
oh
o
CC
I
V = 0.3 x V
5
10
15
ol
o
CC
REFERENCE VOLTAGE OUTPUT (pin V
)
REF1
V
Reference output voltage
−50 mA < I
< +50 mA
0.45 x
CC
0.50 x
CC
0.55 x
CC
V
V
REF
VREF
V
V
V
V
Reference output voltage for full
common mode range
−35 V <V
< +35 V;
< +35 V
0.40 x
0.50 x
0.60 x
REF_CM
CANHx
V
CC
V
CC
V
CC
−35 V <V
CANLx
BUS LINES (pins CANH1/2 and CANL1/2)
V
Recessive bus voltage at pin
CANH1/2
V
V
= V ; no load
2.0
2.0
2.5
2.5
−
3.0
3.0
V
V
o(reces)
(CANHx)
Tx0
CC
V
Recessive bus voltage at pin
CANL1/2
= V ; no load
CC
o(reces)
(CANLx)
Tx0
I
Recessive output current at pin
CANH1/2
−35 V < V
< +35 V;
−2.5
+2.5
mA
o(reces)
(CANHx)
CANHx
0 V < V < 5.25 V
CC
I
Recessive output current at pin
CANL1/2
−35 V < V
< +35 V;
−2.5
−
+2.5
mA
o(reces)
(CANLx)
CANLx
0 V < V < 5.25 V
CC
V
Dominant output voltage at pin
CANH1/2
V
= 0 V
3.0
0. 5
1.5
3.6
1.4
2.25
0
4.25
1.75
3.0
V
V
o(dom)
(CANHx)
Tx0
Tx0
V
Dominant output voltage at pin
CANL1/2
V
= 0 V
o(dom)
(CANLx)
V
Differential bus output voltage
V
= 0 V; dominant;
42.5 W < R < 60 W
V
o(dif) (bus)
Tx0
(V
CANHx
− V
)
CANLx
LT
V
TxD
= V
;
−120
−45
45
+50
−120
120
mV
mA
mA
CC
recessive; no load
I
Short circuit output current at pin
CANH1/2
V
= 0 V;
= 0 V
−70
70
o(sc)
CANHx
V
Tx0
(CANHx)
I
Short circuit output current at pin
CANL1/2
V
= 36 V;
o(sc) (CANLx)
CANLx
V
= 0 V (Note 8)
Tx0
8. Guaranteed by design for VBAT = 36 V; measured in production for VBAT = 7 V to avoid short−2−VBAT detection
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AMIS−42700
Table 6. DC and Timing Characteristics (V = 4.75 to 5.25 V; T
= −40 to +150°C; R = 60 W unless specified otherwise.)
LT
CC
junc
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
BUS LINES (pins CANH1/2 and CANL1/2)
V
Differential receiver threshold voltage
−5 V < V
< +12 V;
0.5
0.7
0.9
V
i(dif)(th)
CANLx
−5 V < V
< +12 V;
CANHx
see Figure 6
V
Differential receiver threshold voltage
−35 V < V
< +35 V;
< +35 V;
0.3
50
0.7
70
1.05
100
V
ihcm(dif) (th)
CANLx
for high common−mode
−35 V < V
CANHx
see Figure 6
V
Differential receiver input voltage
hysteresis
−35V < V
−35 V < V
< +35 V;
< +35 V;
mV
i(dif) (hys)
CANL
CANH
see Figure 6
R
Common−mode input resistance at
15
15
−3
26
26
0
37
37
+3
KW
KW
%
i(cm)
(CANHx)
pin CANH1/2
R
Common−mode input resistance at
pin CANL1/2
i(cm)
(CANLx)
R
Matching between pin CANH1/2 and
pin CANL1/2 common−mode input
resistance
V
= V
i(cm)(m)
CANHx CANLx
R
Differential input resistance
25
50
7.5
75
20
KW
pF
pF
pF
mA
i(dif)
C
Input capacitance at pin CANH1/2
Input capacitance at pin CANL1/2
Differential input capacitance
V
V
V
= V ; not tested
CC
i(CANHx)
Tx0
Tx0
Tx0
C
= V ; not tested
7.5
20
i(CANLx)
CC
C
= V ; not tested
3.75
170
10
i(dif)
LI(CANHx)
CC
I
Input leakage current at pin CANH1/2
V
< PORL_VCC;
−350
−350
−1000
−250
7
350
CC
−5.25 V < V
< 5.25 V
CANHx
I
Input leakage current at pin CANL1/2
V
< PORL_VCC;
170
350
1000
250
9.5
mA
mV
mV
V
LI(CANLx)
CC
−5.25 V < V
< 5.25 V
CANLx
V
Common−mode peak during transition
from dom → rec or rec → dom
see Figure 10
CM−peak
V
Difference in common−mode between
dominant and recessive state
see Figure 10
CM−step
V
Detection level for CANL1/2 short to
VBAT
CANL2VBAT
THERMAL SHUTDOWN
Shutdown junction temperature
TIMING CHARACTERISTICS (see Figures 7 and 8)
T
j(sd)
150
°C
t
Delay Tx0/Text to bus active
Delay Tx0/Text to bus inactive
Delay bus active to Rx0/Rint
Delay bus inactive to Rx0/Rint
40
30
25
65
85
60
120
115
115
145
200
ns
ns
ns
ns
ns
d(Tx−BUSon)
d(Tx−BUSoff)
t
t
t
55
d(BUSon−RX)
d(BUSoff−RX)
100
100
t
Delay from EN1B to bus
active/inactive
d(ENxB)
t
Delay from Tx0 to Rx0/Rint and from
Text to Rx0 (direct logical path)
15 pF on the digital output
4
10
35
ns
d(Tx−Rx)
t
Reaction time of the CANL−to−VBAT
Short occurring
1
1
4
ms
ms
ms
ns
d(CAN2VBAT)
short detector
Short disappearing
5.5
750
330
t
Time out counter interval
250
5+
450
dom
t
Delay for feedback
suppression release
d(FBS)
t
d(BUSon−RX)
8. Guaranteed by design for VBAT = 36 V; measured in production for VBAT = 7 V to avoid short−2−VBAT detection
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9
AMIS−42700
Measurement Set−ups and Definitions
Schematics are given for single CAN transceiver.
+5V
100 nF
Vref
VCC
12
1 nF
1 nF
CANH1
8
13
Text
Transient
Generator
3
CANL1
CANH2
14
19
Rint
9
AMIS−42700
Tx0
4
7
10
Rx0
CANL2
18
2
17 16 15
6
5
GND
EN1
EN2
Figure 5. Test Circuit for Automotive Transients
VRxD
High
Low
Hysteresis
0,9
0,5
Vi(dif)(hys)
Figure 6. Hysteresis of the Receiver
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10
AMIS−42700
+5V
100 nF
VCC
12
Vref
CANH1
8
13
Text
Rint
RLT
CLT
3
60 W
100 pF
CANL1
CANH2
14
19
9
AMIS−42700
Tx0
CLT
RLT
4
7
10
100 pF
60 W
Rx0
CANL2
18
2
17 16 15
6
5
GND
EN1
EN2
Figure 7. Test Circuit for Timing Characteristics
HIGH
LOW
Tx0/
Text
CANHx
CANLx
dominant
recessive
Vi(dif)
=
0,9V
0,9V
0,5V
0,5V
VCANH −VCANL
Rx0/
Rint
0,7 x VCC
0,7 x VCC
0,3 x VCC
0,3 x VCC
td(Tx−Rx)
td(Tx−Rx)
td(BUSon−Rx)
td(BUSoff−Rx)
td(Tx−BUSon)
td(Tx−BUSoff)
Figure 8. Timing Diagram for AC Characteristics
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11
AMIS−42700
+5V
100 nF
VCC
12
Vref
13
6.2 kW
CANH1
CANL1
8
10 nF
Text
Rint
3
Active Probe
14
19
Spectrum Anayzer
9
6.2 kW
30 W
AMIS−42700
CANH2
Tx0
30 W
4
7
10
Gen
Rx0
CANL2
18
5
2
17 16 15
6
47 nF
GND
EN1
EN2
Figure 9. Basic Test Set−up for Electromagnetic Measurement
CANHx
CANLx
recessive
VCM−step
V
=
)
CM
VCM−peak
0.5*(V
+V
CANLx
CANHx
VCM−peak
Figure 10. Common−mode Voltage Peaks (see measurement set−up Figure 9)
ORDERING INFORMATION
Container
Shipping
Temperature
Range
Configuration
Quantity
38
Part Number
AMIS42700WCGA4H
AMIS42700WCGA4RH
Package
SOIC 150 20 300 GREEN
SOIC 150 20 300 GREEN
Rail
−40°C to 125°C
−40°C to 125°C
Tape & Reel
1500
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12
AMIS−42700
Soldering
• Use a double−wave soldering method comprising a
turbulent wave with high upward pressure followed by
a smooth laminar wave.
Introduction to Soldering Surface Mount Packages
This text gives a very brief insight to a complex
technology. A more in−depth account of soldering ICs can
be found in the ON Semiconductor “Data Handbook IC26;
Integrated Circuit Packages” (document order number 9398
652 90011). There is no soldering method that is ideal for all
surface mount IC packages. Wave soldering is not always
suitable for surface mount ICs, or for printed−circuit boards
with high population densities. In these situations reflow
soldering is often used.
• For packages with leads on two sides and a pitch (e):
•
Larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the print−circuit board;
•
Smaller than 1.27 mm, the footprint
longitudinal axis must be parallel to the
transport direction of the printed−circuit board.
The footprint must incorporate solder thieves at
the downstream end.
Re−flow Soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed−circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive
is cured. Typical dwell time is four seconds at 250°C. A
mildly−activated flux will eliminate the need for removal of
corrosive residues in most applications.
Re−flow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied to
the printed−circuit board by screen printing, stenciling or
pressure−syringe dispensing before package placement.
Several methods exist for re−flowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating method.
Typical re−flow peak temperatures range from 215°C to
260°C.
Wave Soldering
Manual Soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed−circuit boards
with a high component density, as solder bridging and
non−wetting can present major problems. To overcome
these problems the double−wave soldering method was
specifically developed.
Fix the component by first soldering two diagonally−
opposite end leads. Use a low voltage (24 V or less)
soldering iron applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300°C.
When using a dedicated tool, all other leads can be
soldered in one operation within two to five seconds
between 270°C and 320°C.
If wave soldering is used the following conditions must be
observed for optimal results:
Table 7. Soldering Process
Soldering Method
Wave
Re−flow (Note 9)
Suitable
Package
BGA, SQFP
Not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS
PLCC (Note 11), SO, SOJ
LQFP, QFP, TQFP
Not suitable (Note 10)
Suitable
Suitable
Suitable
Not recommended (Notes 11 and 12)
Not recommended (Note 13)
Suitable
SSOP, TSSOP, VSO
Suitable
9. All SMD packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body
size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so
called popcorn effect). For details, refer to the dry pack information in the “Data Handbook IC26; Integrated Circuit Packages; Section:
Packing Methods”.
10.These packages are not suitable for wave soldering as a solder joint between the printed−circuit board and heatsink (at bottom version) can
not be achieved, and as solder may stick to the heatsink (on top version).
11. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must
incorporate solder thieves downstream and at the side corners.
12.Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable
for packages with a pitch (e) equal or smaller than 0.65 mm.
13.Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable
for packages with a pitch (e) equal to or smaller than 0.5 mm.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC 20 W
CASE 751AQ−01
ISSUE O
DATE 19 JUN 2008
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30891E
SOIC 20 W
PAGE 1 OF 1
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