ADM1030ARQ-REEL7 [ONSEMI]
Intelligent Temperature Monitor and PWM Fan Controller; 智能温度监控器和PWM风扇控制器
| 型号： | ADM1030ARQ-REEL7 |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Temperature Monitor and PWM Fan Controller |
| 文件： | 总29页 (文件大小：558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intelligent Temperature
Monitor and PWM Fan Controller
ADM1030*
FEATURES
PRODUCT DESCRIPTION
Optimized for Pentium® III: Allows Reduced Guardbanding
Software and Automatic Fan Speed Control
Automatic Fan Speed Control Allows Control Independent
of CPU Intervention after Initial Setup
Control Loop Minimizes Acoustic Noise and Battery
Consumption
Remote Temperature Measurement Accurate to 1�C
Using Remote Diode
0.125�C Resolution on Remote Temperature Channel
Local Temperature Sensor with 0.25�C Resolution
Pulsewidth Modulation Fan Control (PWM)
Programmable PWM Frequency
Programmable PWM Duty Cycle
Tach Fan Speed Measurement
Analog Input To Measure Fan Speed of 2-Wire Fans
(Using Sense Resistor)
2-Wire System Management Bus (SMBus) with ARA
Support
The ADM1030 is an ACPI-compliant two-channel digital ther-
mometer and under/over temperature alarm, for use in computers
and thermal management systems. Optimized for the Pentium
III, the higher 1rC accuracy offered allows systems designers to
safely reduce temperature guardbanding and increase system
performance. A Pulsewidth Modulated (PWM) Fan Control out-
put controls the speed of a cooling fan by varying output duty
cycle. Duty cycle values between 33%–100% allow smooth
control of the fan. The speed of the fan can be monitored via a
TACH input for a fan with a tach output. The TACH input can
be programmed as an analog input, allowing the speed of a 2-wire
fan to be determined via a sense resistor. The device will also
detect a stalled fan. A dedicated Fan Speed Control Loop pro-
vides control even without the intervention of CPU software. It
also ensures that if the CPU or system locks up, the fan can still
be controlled based on temperature measurements, and the fan
speed adjusted to correct any changes in system temperature.
Fan Speed may also be controlled using existing ACPI software.
One input (two pins) is dedicated to a remote temperature-
sensing diode with an accuracy of ±1rC, and a local temperature
sensor allows ambient temperature to be monitored. The device
has a programmable INT output to indicate error conditions.
There is a dedicated FAN_FAULT output to signal fan failure.
The THERM pin is a fail-safe output for over-temperature
conditions that can be used to throttle a CPU clock.
Overtemperature THERM Output Pin
Programmable INT Output Pin
Configurable Offset for All Temperature Channels
3 V to 5.5 V Supply Range
Shutdown Mode to Minimize Power Consumption
APPLICATIONS
Notebook PCs, Network Servers and Personal Computers
Telecommunications Equipment
FUNCTIONAL BLOCK DIAGRAM
V
CC
ADD
SDA
SCL
SERIAL BUS
INTERFACE
SLAVE
ADM1030
ADDRESS
NC
REGISTER
ADDRESS
POINTER
REGISTER
FAN
NC
NC
CHARACTERISTICS
REGISTER
INT
FAN SPEED
PWM
INTERRUPT
STATUS
REGISTER
THERM
CONFIG
PWM_OUT
CONTROLLER
REGISTER
FAN_FAULT
T
/T
MIN RANGE
LIMIT
COMPARATOR
REGISTER
FAN
TACH SIGNAL
CONDITIONING
TACH/AIN
SPEED
VALUE AND LIMIT
REGISTERS
COUNTER
D+
D–
NC
OFFSET
REGISTERS
ANALOG
MULTIPLEXER
ADC
BANDGAP
TEMPERATURE
SENSOR
CONFIGURATION
REGISTER
2.5V
BANDGAP
REFERENCE
*Patents pending.
NC = NO CONNECT
GND
©2008 SCILLC. All rights reserved.
February 2008 - Rev. 2
Publication Order Number:
ADM1030/D
ADM1030–SPECIFICATIONS1
(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage, VCC
Supply Current, ICC
3.0
3.30
1.4
32
5.5
3
50
V
mA
mA
Interface Inactive, ADC Active
Standby Mode
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy
Resolution
External Diode Sensor Accuracy
Resolution
±1
0.25
±3
±1
rC
rC
rC
rC
mA
mA
60rC £ TD £ 100rC
0.125
180
11
Remote Sensor Source Current
High Level
Low Level
OPEN-DRAIN DIGITAL OUTPUTS
(THERM, INT, FAN_FAULT, PWM_OUT)
Output Low Voltage, VOL
0.4
1
V
mA
IOUT = –6.0 mA; VCC = 3 V
VOUT = VCC; VCC = 3 V
High-Level Output Leakage Current, IOH
0.1
5
DIGITAL INPUT LEAKAGE CURRENT
Input High Current, IIH
Input Low Current, IIL
–1
mA
mA
pF
VIN = VCC
VIN = 0
1
Input Capacitance, CIN
DIGITAL INPUT LOGIC LEVELS2
(ADD, THERM, TACH)
Input High Voltage, VIH
2.1
V
V
Input Low Voltage, VIL
0.8
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, VOL
High-Level Output Leakage Current, IOH
0.4
1
V
mA
IOUT = –6.0 mA; VCC = 3 V
VOUT = VCC
0.1
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
2.1
V
V
mV
0.8
500
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
±6
%
60rC £ TA £ 100rC
Resolution
8
Bits
TACH Nominal Input RPM
4400
2200
1100
550
RPM
RPM
RPM
RPM
ms
Divisor N = 1, Fan Count = 153
Divisor N = 2, Fan Count = 153
Divisor N = 4, Fan Count = 153
Divisor N = 8, Fan Count = 153
Conversion Cycle Time
637
SERIAL BUS TIMING3
Clock Frequency, fSCLK
Glitch Immunity, tSW
10
100
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
50
Bus Free Time, tBUF
4.7
4.7
4
4
1.3
4
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
Stop Condition Setup Time tSU;STO
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
50
1000
300
250
300
NOTES
1Typicals are at TA = 25rC and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
2ADD is a three-state input that may be pulled high, low or left open-circuit.
3Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Specifications subject to change without notice.
Rev. 2 | Page 2 of 29 | www.onsemi.com
ADM1030
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on Any Input or Output Pin . . . . . . . . –0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Maximum Junction Temperature (TJMAX) . . . . . . . . . . 150rC
Storage Temperature Range . . . . . . . . . . . . –65rC to +150rC
Lead Temperature, Soldering
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . 215rC
Infrared 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200rC
ESD Rating All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
16-Lead QSOP Package
qJA = 105rC/W, qJC = 39rC/W
tR
tF
tHD:STA
tLOW
SCL
SDA
tHD: DAT
tSU:STA
tSU:STO
tSU: DAT
tHD:STA
tHIGH
tBUF
P
S
S
P
Figure 1. Diagram for Serial Bus Timing
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM1030 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REVISION HISTORY
02/08—Rev 1: Conversion to ON Semiconductor
04/03—Data Sheet Change from Rev. 0 to Rev. A.
Rev. 2 | Page 3 of 29 | www.onsemi.com
ADM1030
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
PWM_OUT
Digital Output (Open-Drain). Pulsewidth modulated output to control fan speed. Requires pull-up
resistor (10 kW typical).
2
TACH/AIN
Digital/Analog Input. Fan tachometer input to measure fan speed. May be reprogrammed as an
analog input to measure speed of a 2-wire fan via a sense resistor (2 W typical)
3, 4, 11, 12
NC
Not Connected.
5
6
7
GND
VCC
THERM
System Ground.
Power. Can be powered by 3.3 V Standby power if monitoring in low power states is required.
Digital I/O (Open-Drain). An active low thermal overload output that indicates a violation of a
temperature set point (overtemperature). Also acts as an input to provide external fan control.
When this pin is pulled low by an external signal, a status bit is set, and the fan speed is set to full-on.
Requires pull-up resistor (10 kW).
8
9
FAN_FAULT
Digital Output (Open-Drain). Can be used to signal a fan failure. Requires pull-up resistor
(typically 10 kW).
Analog Input. Connected to cathode of an external temperature-sensing diode. The temperature-
sensing element is either a Pentium III substrate transistor or a general-purpose 2N3904.
D–
10
13
14
D+
ADD
INT
Analog Input. Connected to anode of the external temperature-sensing diode.
Three-state Logic Input. Sets two lower bits of device SMBus address.
Digital Output (Open-Drain). Can be programmed as an interrupt output for temperature/fan
speed interrupts. Requires pull-up resistor (10 kW typical).
15
16
SDA
SCL
Digital I/O. Serial Bus Bidirectional Data. Open-drain output. Requires pull-up resistor
(2.2 kW typical).
Digital Input. Serial Bus Clock. Requires pull-up resistor (2.2 kW typ).
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
SCL
SDA
PWM_OUT
TACH/AIN
NC
14 INT
ADM1030
ADD
NC
13
12
11
TOP VIEW
(Not to Scale)
NC
NC
GND
V
CC
10 D+
D–
THERM
9
FAN_FAULT
NC = NO CONNECT
Rev. 2 | Page 4 of 29 | www.onsemi.com
Typical Performance Characteristics–ADM1030
15
10
110
100
90
80
70
60
50
40
30
20
10
0
5
DXPTO GND
0
DXPTO V (3.3V)
CC
–5
–10
–15
–20
1
3.3
10
30
100
0
10
20
30
40
50
60
70
80
90 100 110
PIIITEMPERATURE – ꢀC
LEAKAGE RESISTANCE – M�
TPC 1. Temperature Error vs. PCB Track Resistance
TPC 4. Pentium III Temperature Measurement vs.
ADM1030 Reading
17
1
0
–1
–2
–3
–4
–5
–6
–7
V
= 100mV p-p
15
13
11
9
IN
–8
–9
7
–10
–11
–12
–13
–14
–15
–16
5
3
1
V
= 200mV p-p
IN
–1
0
500k
2M
4M
6M
10M
100M 400M
1
2.2
3.3
4.7
10
22
47
FREQUENCY – Hz
DXP – DXN CAPACITANCE – nF
TPC 5. Temperature Error vs. Capacitance between
D+ and D–
TPC 2. Temperature Error vs. Power Supply Noise
Frequency
110
100
90
7
6
5
4
3
80
70
V
= 5V
60
50
40
30
20
10
0
CC
V
= 40mV p-p
IN
2
1
V
= 3.3V
CC
0
V
= 20mV p-p
IN
–1
0
1
5
10
25
50
75 100 250 500 750 1000
0
100k
1M
100M 200M
300M 400M
500M
SCLK FREQUENCY – kHz
FREQUENCY – Hz
TPC 6. Standby Current vs. Clock Frequency
TPC 3. Temperature Error vs. Common-Mode Noise
Frequency
Rev. 2 | Page 5 of 29 | www.onsemi.com
ADM1030
7
0.08
0
V
= 30mV p-p
IN
6
5
4
3
2
1
0
–0.08
–0.16
–0.24
–0.32
–0.40
–0.48
–0.56
–0.64
–0.72
–0.80
V
= 20mV p-p
IN
–1
0
100k
1M
100M 200M
300M 400M 500M
0
20
40
60
80
85
100
105
120
FREQUENCY – Hz
TEMPERATURE –
�C
TPC 7. Temperature Error vs. Differential-Mode Noise
Frequency
TPC 10. Remote Sensor Error
200
180
160
140
120
100
1.30
1.25
1.20
1.15
1.10
1.05
80
ADD = Hi-Z
1.00
0.95
0.90
0.85
0.80
60
ADD = GND
40
ADD =V
CC
20
0
–20
0
1.1
1.3
1.5
1.7
1.9
2.1
2.5
2.9
4.5
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
SUPPLYVOLTAGE –V
SUPPLYVOLTAGE –V
TPC 8. Standby Supply Current vs. Supply Voltage
TPC 11. Supply Current vs. Supply Voltage
0.16
0.08
120
110
100
90
80
70
60
50
40
30
20
10
0
0
–0.08
–0.16
–0.24
–0.32
–0.40
–0.48
–0.56
–0.64
–0.72
–0.80
–0.88
0
20
40
60
80
85
100
105
120
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE –
�C
TIME – Sec
TPC 12. Response to Thermal Shock
TPC 9. Local Sensor Error
Rev. 2 | Page 6 of 29 | www.onsemi.com
ADM1030
GENERAL DESCRIPTION
three-state input that can be grounded, connected to VCC, or
left open-circuit to give three different addresses. The state of
the ADD pin is only sampled at power-up, so changing ADD
with power on will have no effect until the device is powered off,
then on again.
The ADM1030 is a temperature monitor and PWM fan control-
ler for microprocessor-based systems. The device communicates
with the system via a serial System Management Bus. The serial
bus controller has a hardwired address pin for device selection
(Pin 13), a serial data line for reading and writing addresses and
data (Pin 15), and an input line for the serial clock (Pin 16). All
control and programming functions of the ADM1030 are per-
formed over the serial bus. The device also supports the SMBus
Alert Response Address (ARA) function.
Table I. ADD Pin Truth Table
ADD Pin
GND
A1
0
A0
0
No Connect
VCC
1
0
0
1
INTERNAL REGISTERS OF THE ADM1030
A brief description of the ADM1030’s principal internal regis-
ters is given below. More detailed information on the function of
each register is given in Table XII to Table XXVI.
If ADD is left open-circuit, the default address will be 0101110.
The facility to make hardwired changes at the ADD pin allows
the user to avoid conflicts with other devices sharing the same
serial bus, for example, if more than one ADM1030 is used in
a system.
Configuration Register
Provides control and configuration of various functions on
the device.
The serial bus protocol operates as follows:
Address Pointer Register
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition, and shift in the next 8 bits, consisting of a
7-bit address (MSB first) plus an R/W bit that determines the
direction of the data transfer, i.e., whether data will be
written to or read from the slave device.
This register contains the address that selects one of the other
internal registers. When writing to the ADM1030, the first byte
of data is always a register address, which is written to the
Address Pointer Register.
Status Registers
These registers provide status of each limit comparison.
Value and Limit Registers
The results of temperature and fan speed measurements are
stored in these registers, along with their limit values.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, the master will write to the slave
device. If the R/W bit is a 1, the master will read from the
slave device.
Fan Speed Config Register
This register is used to program the PWM duty cycle for the fan.
Offset Registers
Allows the temperature channel readings to be offset by a 5-bit
two’s complement value written to these registers. These values
will automatically be added to the temperature values (or sub-
tracted from if negative). This allows the systems designer to
optimize the system if required, by adding or subtracting up to
15rC from a temperature reading.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.
Fan Characteristics Register
This register is used to select the spin-up time, PWM frequency,
and speed range for the fan used.
THERM Limit Registers
These registers contain the temperature values at which THERM
will be asserted.
TMIN/TRANGE Registers
3. When all data bytes have been read or written, stop condi-
tions are established. In WRITE mode, the master will pull
the data line high during the tenth clock pulse to assert a
STOP condition. In READ mode, the master device will
override the acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse. This is
known as No Acknowledge. The master will then take the
data line low during the low period before the tenth clock
pulse, then high during the tenth clock pulse to assert a
STOP condition.
These registers are read/write registers that hold the minimum
temperature value below which the fan will not run when the
device is in Automatic Fan Speed Control Mode. These regis-
ters also hold the values defining the range over that auto fan
control will be provided, and hence determines the temperature
at which the fan will run at full speed.
SERIAL BUS INTERFACE
Control of the ADM1030 is carried out via the SMBus. The
ADM1030 is connected to this bus as a slave device, under the
control of a master device, e.g., the 810 chipset.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
The ADM1030 has a 7-bit serial bus address. When the device
is powered up, it will do so with a default serial bus address.
The five MSBs of the address are set to 01011, the two LSBs
are determined by the logical state of Pin 13 (ADD). This is a
Rev. 2 | Page 7 of 29 | www.onsemi.com
ADM1030
as before, but only the data byte containing the register address
is sent, as data is not to be written to the register. This is
shown in Figure 2b.
In the case of the ADM1030, write operations contain either
one or two bytes, and read operations contain one byte, and
perform the following functions.
A read operation is then performed consisting of the serial bus
address, R/W bit set to 1, followed by the data byte read from
the data register. This is shown in Figure 2c.
To write data to one of the device data registers or read data
from it, the Address Pointer Register must be set so that the
correct data register is addressed; data can then be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the Address Pointer
Register. If data is to be written to the device, then the write
operation contains a second data byte that is written to the
register selected by the address pointer register.
2. If the Address Pointer Register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the Address Pointer
Register, so Figure 2b can be omitted.
NOTES
This is illustrated in Figure 2a. The device address is sent over
the bus followed by R/W set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the Address Pointer
Register. The second data byte is the data to be written to the
internal data register.
1. Although it is possible to read a data byte from a data register
without first writing to the Address Pointer Register, if the
Address Pointer Register is already at the correct value, it is
not possible to write data to a register without writing to the
Address Pointer Register, because the first data byte of a
write is always written to the Address Pointer Register.
When reading data from a register there are two possibilities:
2. In Figures 2a to 2c, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the three-state ADD pin.
1. If the ADM1030’s Address Pointer Register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADM1030
3. The ADM1030 also supports the Read Byte protocol, as
described in the System Management Bus specification.
1
9
1
9
SCL
D6
D2
0
1
0
1
1
A1
A0
D7
D5
D4
D3
D1
SDA
START BY
R/W
D0
ACK. BY
ADM1030
ACK. BY
ADM1030
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D2
D1
D7
D6
D5
D4
D3
D0
ACK. BY STOP BY
ADM1030 MASTER
FRAME 3
DATA BYTE
Figure 2a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
9
1
9
SCL
D6
D2
0
1
0
1
1
A1
A0
D7
D5
D4
D3
D1
SDA
R/W
D0
ACK. BY
ADM1030
ACK. BY
STOP BY
START BY
MASTER
ADM1030 MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 2b. Writing to the Address Pointer Register Only
1
9
1
9
SCL
D6
D2
0
1
0
1
1
A1
A0
D7
D5
D4
D3
D1
SDA
START BY
D0
R/W
ACK. BY
ADM1030
NO ACK.
STOP BY
BY MASTER MASTER
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADM1030
Figure 2c. Reading Data from a Previously Selected Register
Rev. 2 | Page 8 of 29 | www.onsemi.com
ADM1030
ALERT RESPONSE ADDRESS
Figure 3 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for tempera-
ture monitoring on some microprocessors, but it could equally
well be a discrete transistor.
Alert Response Address (ARA) is a feature of SMBus devices
that allows an interrupting device to identify itself to the host
when multiple devices exist on the same bus.
The INT output can be used as an interrupt output or can be used
as an SMBALERT. One or more INT outputs can be connected
to a common SMBALERT line connected to the master. If a
device’s INT line goes low, the following procedure occurs:
V
DD
I
N � I
I
BIAS
1. SMBALERT pulled low.
2. Master initiates a read operation and sends the Alert
Response Address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
V
V
D+
D–
OUT+
TO
ADC
REMOTE
SENSING
TRANSISTOR
BIAS
DIODE
3. The device whose INT output is low responds to the Alert
Response Address, and the master reads its device address.
The address of the device is now known and can be interro-
gated in the usual way.
OUT–
LOW-PASS
FILTER
C
f
= 65kHz
4. If more than one device’s INT output is low, the one with
the lowest device address will have priority, in accordance
with normal SMBus arbitration.
Figure 3. Signal Conditioning
If a discrete transistor is used, the collector will not be grounded,
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D– input and the base to the D+ input.
5. Once the ADM1030 has responded to the Alert Response
Address, it will reset its INT output; however, if the error
condition that caused the interrupt persists, INT will be
reasserted on the next monitoring cycle.
One LSB of the ADC corresponds to 0.125rC, so the ADM1030
can theoretically measure temperatures from –127rC to +127.75rC,
although –127rC is outside the operating range for the device.
The extended temperature resolution data format is shown in
Tables III and IV.
TEMPERATURE MEASUREMENT SYSTEM
Internal Temperature Measurement
The ADM1030 contains an on-chip bandgap temperature sen-
sor. The on-chip ADC performs conversions on the output of
this sensor and outputs the temperature data in 10-bit two’s
complement format. The resolution of the local temperature
sensor is 0.25rC. The format of the temperature data is shown
in Table II.
Table II. Temperature Data Format (Local Temperature and
Remote Temperature High Bytes)
Temperature (ꢀC)
Digital Output
External Temperature Measurement
–128rC
–125rC
–100rC
–75rC
–50rC
–25rC
–1rC
1000 0000
1000 0011
1001 1100
1011 0101
1100 1110
1110 0111
1111 1111
0000 0000
0000 0001
0000 1010
0001 1001
0011 0010
0100 1011
0110 0100
0111 1101
0111 1111
The ADM1030 can measure the temperature of an external
diode sensor or diode-connected transistor, connected to Pins
9 and 10.
These pins are a dedicated temperature input channel. The
function of Pin 7 is as a THERM input/output and is used to
flag overtemperature conditions.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about –2 mV/rC. Unfortunately, the absolute
value of VBE, varies from device to device, and individual
calibration is required to null this out, so the technique is
unsuitable for mass production.
0rC
+1rC
+10rC
+25rC
+50rC
+75rC
+100rC
+125rC
+127rC
The technique used in the ADM1030 is to measure the change
in VBE when the device is operated at two different currents.
This is given by:
DVBE = KT/q ¥ ln (N)
where:
K is Boltzmann’s constant.
q is charge on the carrier.
T is absolute temperature in Kelvins.
N is ratio of the two currents.
Rev. 2 | Page 9 of 29 | www.onsemi.com
ADM1030
Table III. Remote Sensor Extended Temperature Resolution
10MIL
10MIL
10MIL
10MIL
10MIL
10MIL
10MIL
GND
D+
Extended
Resolution (�C)
Remote Temperature
Low Bits
0.000
0.125
0.250
0.375
0.500
0.625
0.750
0.875
000
001
010
011
100
101
110
111
D–
GND
Figure 4. Arrangement of Signal Tracks
4. Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/solder joints
are used, make sure that they are in both the D+ and D–
path and at the same temperature.
The extended temperature resolution for the local and remote
channels is stored in the Extended Temperature Resolution
Register (Register 0x06), and is outlined in Table XVIII.
Thermocouple effects should not be a major problem as 1rC
corresponds to about 200 mV, and thermocouple voltages are
about 3 mV/rC of temperature difference. Unless there are two
thermocouples with a big temperature differential between
them, thermocouple voltages should be much less than 200 mV.
Table IV. Local Sensor Extended Temperature Resolution
Extended
Local Temperature
Low Bits
Resolution (�C)
0.00
0.25
0.50
0.75
00
01
10
11
5. Place a 0.1 mF bypass capacitor close to the ADM1030.
6. If the distance to the remote sensor is more than 8 inches, the
use of twisted pair cable is recommended. This will work up
to about 6 to 12 feet.
To prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to ground,
but is biased above ground by an internal diode at the D– input.
If the sensor is used in a very noisy environment, a capacitor of
value up to 1000 pF may be placed between the D+ and D–
inputs to filter the noise.
7. For really long distances (up to 100 feet) use shielded twisted
pair such as Belden #8451 microphone cable. Connect the
twisted pair to D+ and D– and the shield to GND close to
the ADM1030. Leave the remote end of the shield uncon-
nected to avoid ground loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor C1
may be reduced or removed. In any case the total shunt capaci-
tance should not exceed 1000 pF.
To measure DVBE, the sensor is switched between operating
currents of I and N ¥ I. The resulting waveform is passed through
a 65 kHz low-pass filter to remove noise, then to a chopper-
stabilized amplifier that performs the functions of amplification
and rectification of the waveform to produce a dc voltage pro-
portional to DVBE. This voltage is measured by the ADC to give
a temperature output in 11-bit two’s complement format. To
further reduce the effects of noise, digital filtering is performed
by averaging the results of 16 measurement cycles. An external
temperature measurement nominally takes 9.6 ms.
Cable resistance can also introduce errors. 1 W series resistance
introduces about 0.5rC error.
ADDRESSING THE DEVICE
ADD (Pin 13) is a three-state input. It is sampled, on power-up
to set the lowest two bits of the serial bus address. Up to three
addresses are available to the systems designer via this address
pin. This reduces the likelihood of conflicts with other devices
attached to the System Management Bus.
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments and care
must be taken to protect the analog inputs from noise, particu-
larly when measuring the very small voltages from a remote
diode sensor. The following precautions should be taken:
THE ADM1030 INTERRUPT SYSTEM
The ADM1030 has two interrupt outputs, INT and THERM.
These have different functions. INT responds to violations of
software programmed temperature limits and is maskable
(described in more detail later).
1. Place the ADM1030 as close as possible to the remote sens-
ing diode. Provided that the worst noise sources such as clock
generators, data/address buses, and CRTs are avoided, this
distance can be 4 to 8 inches.
THERM is intended as a “fail-safe” interrupt output that can-
not be masked. If the temperature is below the low temperature
limit, the INT pin will be asserted low to indicate an out-of-limit
condition. If the temperature exceeds the high temperature limit,
the INT pin will also be asserted low. A third limit; THERM
limit, may be programmed into the device to set the temperature
limit above which the overtemperature THERM pin will be
2. Route the D+ and D– tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground plane
under the tracks if possible.
3. Use wide tracks to minimize inductance and reduce noise pick-up.
10 mil track minimum width and spacing is recommended.
Rev. 2 | Page 10 of 29 | www.onsemi.com
ADM1030
asserted low. The behavior of the high limit and THERM limit
is as follows:
condition still persists. This bit may be reasserted only if the
fan is no longer at Alarm Speed. Bit 1 (Fan Fault) is set whenever
a fan tach failure is detected.
1. Whenever the temperature measured exceeds the high tem-
perature limit, the INT pin is asserted low.
Once cleared, it will reassert on subsequent fan tach failures.
Bits 2 and 3 of Status Register 1 are the Remote Temperature
High and Low status bits. Exceeding the high or low temperature
limits for the external channel sets these status bits. Reading the
status register clears these bits. However, these bits will be reasserted
if the out-of limit condition still exists on the next monitoring
cycle. Bits 6 and 7 are the Local Temperature High and Low
status bits. These behave exactly the same as the Remote Temper-
ature High and Low status bits. Bit 4 of Status Register 1 indicates
that the Remote Temperature THERM limit has been exceeded.
This bit gets cleared on a read of Status Register 1 (see Figure 5).
Bit 5 indicates a Remote Diode Error. This bit will be a 1 if a
short or open is detected on the Remote Temperature channel
on power-up. If this bit is set to 1 on power-up, it cannot be
cleared. Bit 6 of Status Register 2 (0x03) indicates that the
Local THERM limit has been exceeded. This bit is cleared on a
read of Status Register 2. Bit 7 indicates that THERM has been
pulled low as an input. This bit can also be cleared on a read of
Status Register 2.
2. If the temperature exceeds the THERM limit, the THERM
output asserts low. This can be used to throttle the CPU
clock. If the THERM-to-Fan Enable bit (Bit 7 of THERM
behavior/revision register) is cleared to 0, the fan will not run
full-speed. The THERM limit may be programmed at a
lower temperature than the high temperature limit. This
allows the system to run in silent mode, where the CPU can
be throttled while the cooling fan is off. If the temperature
continues to increase, and exceeds the high temperature limit,
an INT is generated. Software may then decide whether the
fan should run to cool the CPU. This allows the system to
run in SILENT MODE.
3. If the THERM-to-Fan Enable bit is set to 1, the fan will run
full-speed whenever THERM is asserted low. In this case,
both throttling and active cooling take place. If the high
temperature limit is programmed to a lower value than the
THERM limit, exceeding the high temperature limit will
assert INT low. Software could change the speed of the fan
depending on temperature readings. If the temperature con-
tinues to increase and exceeds the THERM limit, THERM
asserts low to throttle the CPU and the fan runs full-speed.
This allows the system to run in PERFORMANCE MODE,
where active cooling takes place and the CPU is only throttled
at high temperature.
THERM LIMIT
5�
TEMP
Using the high temperature limit and the THERM limit in this
way allows the user to gain maximum performance from the system
by only slowing it down, should it be at a critical temperature.
THERM
INT REARMED
Although the ADM1030 does not have a dedicated Interrupt
Mask Register, clearing the appropriate enable bits in Configu-
ration Register 2 will clear the appropriate interrupts and mask
out future interrupts on that channel. Disabling interrupt bits
will prevent out-of-limit conditions from generating an interrupt
or setting a bit in the Status Registers.
INT
STATUS REG. READ
Figure 5. Operation of THERM and INT Signals
Figure 5 shows the interaction between INT and THERM.
Once a critical temperature THERM limit is exceeded, both
INT and THERM assert low. Reading the Status Registers
clears the interrupt and the INT pin goes high. However, the
THERM pin remains asserted until the measured temperature
falls 5rC below the exceeded THERM limit. This feature can be
used to CPU throttle or drive a fan full-speed for maximum
cooling. Note, that the INT pin for that interrupt source is not
rearmed until the temperature has fallen below the THERM
limit –5rC. This prevents unnecessary interrupts from tying up
valuable CPU resources.
USING THERM AS AN INPUT
The THERM pin is an open-drain input/output pin. When used
as an output, it signals over-temperature conditions. When
asserted low as an output, the fan will be driven full-speed if the
THERM-to-Fan Enable bit is set to 1 (Bit 7 of Register 0x3F).
When THERM is pulled low as an input, the THERM bit (Bit 7)
of Status Register 2 is set to 1, and the fan is driven full-speed.
Note that the THERM-to-Fan Enable bit has no effect when-
ever THERM is used as an input. If THERM is pulled low as
an input, and the THERM-to-Fan Enable bit = 0, the fan will
still be driven full-speed. The THERM-to-Fan Enable bit only
affects the behavior of THERM when used as an output.
MODES OF OPERATION
The ADM1030 has four different modes of operation. These
modes determine the behavior of the system.
STATUS REGISTERS
1. Automatic Fan Speed Control Mode.
All out-of-limit conditions are flagged by status bits in Status
Registers 1 and 2 (0x02, 0x03). Bits 0 and 1 (Alarm Speed, Fan
Fault) of Status Register 1, once set, may be cleared by reading
Status Register 1. Once the Alarm Speed bit is cleared, this bit
will not be reasserted on the next monitoring cycle even if the
2. Filtered Automatic Fan Speed Control Mode.
3. PWM Duty Cycle Select Mode (directly sets fan speed under
software control).
4. RPM Feedback Mode.
Rev. 2 | Page 11 of 29 | www.onsemi.com
ADM1030
AUTOMATIC FAN SPEED CONTROL
100
93
The ADM1030 has a local temperature channel and a remote
temperature channel, which may be connected to an on-chip
diode-connected transistor on a CPU. These two temperature
channels may be used as the basis for an automatic fan speed
control loop to drive a fan using Pulsewidth Modulation (PWM).
C
�
=
5
87
RANGE
C
�
C
T
�
80
73
= 40
=
20
RANGE
HOW DOES THE CONTROL LOOP WORK?
The Automatic Fan Speed Control Loop is shown in Fig-
ure 6 below.
T
RANGE
66
T
60
53
47
C
�
= 80
RANGE
T
SPIN UP FOR 2 SECONDS
MAX
40
33
T
0
5
10
20
40
TEMPERATURE –
60
80
T
=T
+T
MIN
MAX
MIN RANGE
FAN
SPEED
�C
Figure 7. PWM Duty Cycle vs. Temperature Slopes (TRANGE
)
Figure 8 shows how, for a given TRANGE, changing the TMIN
value affects the loop. Increasing the TMIN value will increase
the TMAX (temperature at which the fan runs full speed) value,
since TMAX = TMIN + TRANGE. Note, however, that the PWM
Duty Cycle vs Temperature slope remains exactly the same.
Changing the TMIN value merely shifts the control slope. The
MIN
T
=T
+T
MIN RANGE
T
MAX
MIN
TMIN may be changed in increments of 4rC.
TEMPERATURE
Figure 6. Automatic Fan Speed Control
100
93
In order for the fan speed control loop to work, certain loop
parameters need to be programmed into the device.
87
1. TMIN. The temperature at which the fan should switch on
and run at minimum speed. The fan will only turn on once
the temperature being measured rises above the TMIN value
programmed. The fan will spin up for a predetermined time
(default = 2 secs). See Fan Spin-Up section for more details.
80
73
66
60
53
47
2. TRANGE. The temperature range over which the ADM1030
will automatically adjust the fan speed. As the temperature
increases beyond TMIN, the PWM_OUT duty cycle will be
increased accordingly. The TRANGE parameter actually defines
the fan speed versus temperature slope of the control loop.
40
33
T
3. TMAX. The temperature at which the fan will be at its maxi-
0
20
40
TEMPERATURE – �C
60
80
+T
MIN RANGE
T
=T
MIN
MAX
mum speed. At this temperature, the PWM duty cycle
driving the fan will be 100%. TMAX is given by TMIN
TRANGE. Since this parameter is the sum of the TMIN and
RANGE parameters, it does not need to be programmed into
+
Figure 8. Effect of Increasing TMIN Value on Control Loop
T
a register on-chip.
FAN SPIN-UP
As was previously mentioned, once the temperature being mea-
sured exceeds the TMIN value programmed, the fan will turn on
at minimum speed (default = 33% duty cycle). However, the
problem with fans being driven by PWM is that 33% duty cycle
is not enough to reliably start the fan spinning. The solution is
to spin the fan up for a predetermined time, and once the fan
has spun up, its running speed may be reduced in line with the
temperature being measured.
4. A hysteresis value of 5rC is included in the control loop to
prevent the fan continuously switching on and off if the tem-
perature is close to TMIN. The fan will continue to run until
such time as the temperature drops 5rC below TMIN.
Figure 7 shows the different control slopes determined by the
TRANGE value chosen, and programmed into the ADM1030.
T
MIN was set to 0rC to start all slopes from the same point. It
can be seen how changing the TRANGE value affects the PWM
duty cycle versus temperature slope.
The ADM1030 allows fan spin-up times between 200 ms and
8 seconds. Bits <2:0> of Fan Characteristics Register 1 (Register
0x20) program the fan spin-up time.
Rev. 2 | Page 12 of 29 | www.onsemi.com
ADM1030
Table V. Fan Spin-Up Times
one channel, may actually calculate a faster speed, than a higher
temperature on the other channel.
Spin-Up Time
Bits 2:0
(Fan Characteristics Register 1)
100
93
000
001
010
011
100
101
110
111
200 ms
400 ms
600 ms
800 ms
1 sec
2 secs (Default)
4 secs
8 secs
87
80
73
66
60
53
47
Once the Automatic Fan Speed Control Loop parameters have
been chosen, the ADM1030 device may be programmed. The
ADM1030 is placed into Automatic Fan Speed Control Mode
by setting Bit 7 of Configuration Register 1 (Register 0x00).
The device powers up into Automatic Fan Speed Control
Mode by default. The control mode offers further flexibility
in that the user can decide which temperature channel/chan-
nels control the fan.
40
33
0
20
40
60
T
=T
+T
RANGE
T
MIN
MAX
MIN
LOCALTEMPERATURE – �C
a.
Table VI. Auto Mode Fan Behavior
100
93
Bits 6, 5
Control Operation (Config Register 1)
87
00
11
Remote Temperature Controls the Fan.
Maximum Speed Calculated by Local and Remote
Temperature Channels Control the Fan.
80
73
66
When Bits 5 and 6 of Config Register 1 are both set to 1, it
offers increased flexibility. The local and remote temperature
channels can have independently programmed control loops
with different control parameters. Whichever control loop
calculates the fastest fan speed based on the temperature being
measured, drives the fan.
60
53
47
40
33
Figure 9 shows how the fan’s PWM duty cycle is determined by
two independent control loops. This is the type of Auto Mode
Fan Behavior seen when Bits 5 and 6 of Config Register 1 are
set to 11. Figure 9a shows the control loop for the Local Tem-
perature channel. Its TMIN value has been programmed to 20rC,
and its TRANGE value is 40rC. The local temperature’s TMAX will
thus be 60rC. Figure 9b shows the control loop for the Remote
Temperature channel. Its TMIN value has been set to 0rC, while its
TRANGE = 80rC. Therefore, the Remote Temperature’s TMAX
value will be 80rC.
0
20
40
70
80
T
T
=T
+T
MIN RANGE
MIN
MAX
REMOTETEMPERATURE – �C
b.
Figure 9. Max Speed Calculated by Local and Remote
Temperature Control Loops Drives Fan
PROGRAMMING THE AUTOMATIC FAN SPEED
CONTROL LOOP
1. Program a value for TMIN
2. Program a value for the slope TRANGE
3. TMAX = TMIN + TRANGE
.
.
Consider if both temperature channels measure 40rC. Both
control loops will calculate a PWM duty cycle of 66%. There-
fore, the fan will be driven at 66% duty cycle.
.
4. Program a value for Fan Spin-up Time.
If both temperature channels measure 20rC, the local channel
will calculate 33% PWM duty cycle, while the remote channel
will calculate 50% PWM duty cycle. Thus, the fan will be
driven at 50% PWM duty cycle. Consider the local temperature
measuring 60rC while the remote temperature is measuring
70rC. The PWM duty cycle calculated by the local temperature
control loop will be 100% (since the temperature = TMAX). The
PWM duty cycle calculated by the remote temperature control
loop at 70rC will be approximately 90%. So the fan will run
full-speed (100% duty cycle). Remember, that the fan speed will
be based on the fastest speed calculated, and is not necessarily
based on the highest temperature measured. Depending on the
control loop parameters programmed, a lower temperature on
5. Program the desired Automatic Fan Speed Control Mode
Behavior, i.e., which temperature channel controls the fan.
6. Select Automatic Fan Speed Control Mode by setting Bit 7
of Configuration Register 1.
OTHER CONTROL LOOP PARAMETERS
Having programmed all the above loop parameters, are there
any other parameters to worry about?
TMIN was defined as being the temperature at which the fan switched
on and ran at minimum speed. This minimum speed is 33% duty
cycle by default. If the minimum PWM duty cycle is programmed
to 33%, the fan control loops will operate as previously described.
Rev. 2 | Page 13 of 29 | www.onsemi.com
ADM1030
It should be noted however, that changing the minimum PWM
duty cycle affects the control loop behavior.
The temperature at which the fan will run full-speed (100%
duty cycle) is given by:
Slope 1 of Figure 10 shows TMIN set to 0rC and the TRANGE
chosen is 40rC. In this case, the fan’s PWM duty cycle will vary
over the range 33% to 100%. The fan will run full-speed at
40rC. If the minimum PWM duty cycle at which the fan runs at
TMIN is changed, its effect can be seen on Slopes 2 and 3. Take
Case 2, where the minimum PWM duty cycle is reprogrammed
from 33% (default) to 53%.
T
MAX = TMIN + ((Max DC – Min DC) ¥ TRANGE/10)
where,
TMAX
TMIN
= Temperature at which fan runs full-speed.
= Temperature at which fan will turn on.
Max DC = Maximum Duty Cycle (100%) = 15 decimal.
Min DC = Duty Cycle at TMIN, programmed into Fan Speed
Config Register (default = 33% = 5 decimal).
100
93
TRANGE = PWM Duty Cycle versus Temperature Slope.
Example 1
87
TMIN
Min DC = 53% = 8 decimal (Table VII)
Calculate TMAX
= 0rC, TRANGE = 40rC
80
73
.
66
TMAX
TMAX
TMAX
TMAX
= TMIN + ((Max DC – Min DC) ¥ TRANGE/10)
= 0 + ((100% DC – 53% DC) ¥ 40/10)
= 0 + ((15 – 8) ¥ 4) = 28
60
53
47
= 28�C (As seen on Slope 2 of Figure 10)
40
33
Example 2
TMIN = 0
0
16
28
40
60
r
C, TRANGE = 40rC
TEMPERATURE – �C
T
MIN
Min DC = 73% = 11 Decimal (Table VII)
Calculate TMAX
Figure 10. Effect of Changing Minimum Duty Cycle on
Control Loop with Fixed TMIN and TRANGE Values
.
TMAX
TMAX
TMAX
TMAX
= TMIN + ((Max DC – Min DC) ¥ TRANGE/10)
= 0 + ((100% DC – 73% DC) ¥ 40/10)
= 0 + ((15 – 11) ¥ 4) = 16
The fan will actually reach full-speed at a much lower tempera-
ture, 28rC. Case 3 shows that when the minimum PWM duty
cycle was increased to 73%, the temperature at which the fan
ran full-speed was 16rC. So the effect of increasing the mini-
mum PWM duty cycle, with a fixed TMIN and fixed TRANGE, is
that the fan will actually reach full-speed (TMAX) at a lower
temperature than TMIN + TRANGE. How can TMAX be calculated?
= 16�C (As seen on Slope 3 of Figure 10)
Example 3
TMIN = 0rC, TRANGE = 40rC
Min DC = 33% = 5 Decimal (Table VII)
Calculate TMAX
In Automatic Fan Speed Control Mode, the register that
holds the minimum PWM duty cycle at TMIN, is the Fan Speed
Config Register (Register 0x22). Table VII shows the relation-
ship between the decimal values written to the Fan Speed Config
Register and PWM duty cycle obtained.
.
TMAX
TMAX
TMAX
TMAX
= TMIN + ((Max DC – Min DC) ¥ TRANGE/10)
= 0 + ((100% DC – 33% DC) ¥ 40/10)
= 0 + ((15 – 5) ¥ 4) = 40
Table VII. Programming PWM Duty Cycle
= 40�C (As seen on Slope 1 of Figure 10)
Decimal Value
PWM Duty Cycle
In this case, since the Minimum Duty Cycle is the default 33%,
the equation for TMAX reduces to:
00
0%
01
02
03
04
05
06
7%
14%
20%
27%
33% (Default)
40%
TMAX
TMAX
TMAX
TMAX
= TMIN + ((Max DC – Min DC) ¥ TRANGE/10)
= TMIN + ((15 – 5) ¥ TRANGE/10)
= TMIN + (10 ¥ TRANGE/10)
= TMIN + TRANGE
07
08
47%
53%
09
60%
67%
73%
80%
87%
93%
100%
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
Rev. 2 | Page 14 of 29 | www.onsemi.com
ADM1030
RELEVANT REGISTERS FOR AUTOMATIC FAN SPEED
CONTROL MODE
Register 0x24 Local Temp TMIN/TRANGE
<7:3> Local Temp TMIN. These bits set the temperature at
Register 0x00 Configuration Register 1
which the fan will turn on when under Auto Fan Speed
<7> Logic 1 selects Automatic Fan Speed Control, Logic 0
selects software control (Default = 1).
Control. TMIN can be programmed in 4rC increments.
00000 = 0rC
00001 = 4rC
00010 = 8rC
<6:5> 00 = Remote Temperature controls Fan
11 = Fastest Calculated Speed controls the fan when
Bit 7 = Logic 1.
00011 = 12rC
|
|
Register 0x20 Fan Characteristics Register 1
<2:0> Fan 1 Spin-Up Time
000 = 200 ms
01000 = 32rC (Default)
|
|
001 = 400 ms
010 = 600 ms
011 = 800 ms
100 = 1 sec
101 = 2 secs (Default)
110 = 4 secs
111 = 8 secs
11110 = 120rC
11111 = 124rC
<2:0> Local Temperature TRANGE. This nibble sets the tem-
perature range over which Automatic Fan Speed Control
takes place.
000 = 5rC
001 = 10rC
010 = 20rC
011 = 40rC
100 = 80rC
<5:3> PWM Frequency Driving the Fan
000 = 11.7 Hz
001 = 15.6 Hz
010 = 23.4 Hz
011 = 31.25 Hz (Default)
100 = 37.5 Hz
101 = 46.9 Hz
Register 0x25 Remote Temperature TMIN/TRANGE
<7:3> Remote Temperature TMIN. Sets the temperature at
which the fan will switch on based on Remote Tempera-
ture Readings.
00000 = 0rC
00001 = 4rC
00010 = 8rC
00011 = 12rC
110 = 62.5 Hz
111 = 93.5 Hz
<7:6> Speed Range N; defines the lowest fan speed that can be
measured by the device.
00 = 1: Lowest Speed = 2647 RPM
01 = 2: Lowest Speed = 1324 RPM
10 = 4: Lowest Speed = 662 RPM
|
|
11 = 8: Lowest Speed = 331 RPM
01100 = 48rC
|
|
Register 0x22 Fan Speed Configuration Register
<3:0> Min Speed: This nibble contains the speed at which the
fan will run when the temperature is at TMIN. The default
is 0x05, meaning that the fan will run at 33% duty cycle
11110 = 120
11111 = 124
r
r
C
C
when the temperature is at TMIN
.
<2:0> Remote Temperature TRANGE. This nibble sets the tem-
perature range over which the fan will be controlled based
on Remote Temperature readings.
000 = 5rC
001 = 10rC
010 = 20rC
011 = 40rC
100 = 80rC
Rev. 2 | Page 15 of 29 | www.onsemi.com
ADM1030
FILTERED CONTROL MODE
READ
The Automatic Fan Speed Control Loop reacts instantaneously
to changes in temperature, i.e., the PWM duty cycle will respond
immediately to temperature change. In certain circumstances,
we may not want the PWM output to react instantaneously to
temperature changes. If significant variations in temperature
were found in a system, it would have the effect of changing the
fan speed, which could be obvious to someone in close proxim-
ity. One way to improve the system’s acoustics would be to
slow down the loop so that the fan ramps slowly to its newly
calculated fan speed. This also ensures that temperature transients
will effectively be ignored, and the fan’s operation will be smooth.
TEMPERATURE
CALCULATE
NEW PWM
DUTY CYCLE
DECREMENT
PREVIOUS
PWM VALUE
BY RAMP
RATE
NO
IS NEW
PWM VALUE >
PREVIOUS
VALUE?
There are two means by which to apply filtering to the Auto-
matic Fan Speed Control Loop. The first method is to ramp the
fan speed at a predetermined rate, to its newly calculated value
instead of jumping directly to the new fan speed. The second
approach involves changing the on-chip ADC sample rate, to
change the number of temperature readings taken per second.
YES
INCREMENT
PREVIOUS PWM
VALUE BY RAMP
RATE
The filtered mode on the ADM1030 is invoked by setting Bit 0
of the Fan Filter Register (Register 0x23). Once the Fan Filter
Register has been written to, and all other control loop param-
eters (TMIN, TRANGE, etc.) have been programmed, the device
may be placed into Automatic Fan Speed Control Mode by
setting Bit 7 of Configuration Register 1 (Register 0x00) to 1.
Figure 12. Filtered Mode Algorithm
The Filtered Mode algorithm calculates a new PWM duty cycle
based on the temperature measured. If the new PWM duty cycle
value is greater than the previous PWM value, the previous PWM
duty cycle value is incremented by either 1, 2, 4, or 8 time slots
(depending on the setting of bits <6:5> of the Fan Filter Regis-
ter). If the new PWM duty cycle value is less than the previous
PWM value, the previous PWM duty cycle is decremented by 1,
2, 4, or 8 time slots. Each time the PWM duty cycle is incremented
or decremented, it is stored as the previous PWM duty cycle for
the next comparison.
Effect of Ramp Rate on Filtered Mode
Bits <6:5> of the Fan Filter Register determine the ramp rate in
Filtered Mode. The PWM_OUT signal driving the fan will have
a period, T, given by the PWM_OUT drive frequency, f, since
T = 1/f. For a given PWM period, T, the PWM period is subdi-
vided into 240 equal time slots. One time slot corresponds to
the smallest possible increment in PWM duty cycle. A PWM
signal of 33% duty cycle will thus be high for 1/3 ¥ 240 time
slots and low for 2/3 ¥ 240 time slots. Therefore, 33% PWM
duty cycle corresponds to a signal which is high for 80 time slots
and low for 160 time slots.
So what does an increase of 1, 2, 4, or 8 time slots actually mean
in terms of PWM duty cycle?
A Ramp Rate of 1 corresponds to one time slot, which is 1/240
of the PWM period. In Filtered Auto Fan Speed Control Mode,
incrementing or decrementing by 1 changes the PWM output
duty cycle by 0.416%.
PWM_OUT
33% DUTY
CYCLE
Table VIII. Effect of Ramp Rates on PWM_OUT
80 TIME
SLOTS
160 TIME
SLOTS
Ramp Rate
PWM Duty Cycle Change
PWM OUTPUT
(ONE PERIOD) =
240 TIME SLOTS
1
2
4
8
0.416%
0.833%
1.66%
3.33%
Figure 11. 33% PWM Duty Cycle Represented in Time Slots
The ramp rates in Filtered Mode are selectable between 1, 2, 4,
and 8. The ramp rates are actually discrete time slots. For
example, if the ramp rate = 8, then eight time slots will be added
to the PWM_OUT high duty cycle each time the PWM_OUT
duty cycle needs to be increased. Figure 12 shows how the
Filtered Mode algorithm operates.
So programming a ramp rate of 1, 2, 4, or 8 simply increases
or decreases the PWM duty cycle by the amounts shown in
Table V, depending on whether the temperature is increasing
or decreasing.
Figure 13 shows remote temperature plotted against PWM duty
cycle for Filtered Mode. The ADC sample rate is the highest
sample rate; 11.25 kHz. The ramp rate is set to 8 which would
correspond to the fastest ramp rate. With these settings it took
approximately 12 seconds to go from 0% duty cycle to 100%
duty cycle (full-speed). The TMIN value = 32rC and the TRANGE
= 80rC. It can be seen that even though the temperature increased
very rapidly, the fan gradually ramps up to full speed.
Rev. 2 | Page 16 of 29 | www.onsemi.com
ADM1030
140
120
100
80
120
100
80
Finally, Figure 16 shows how the control loop reacts to tem-
perature with the slowest ramp rate. The ramp rate is set to 1,
while all other control parameters remain the same. With the
slowest ramp rate selected it took 112 seconds for the fan to
reach full speed.
R
TEMP
120
140
120
100
60
60
110
80
PWM DUTY CYCLE
40
20
40
R
TEMP
20
80
60
60
0
0
0
12
PWM DUTY CYCLE
TIME – s
40
20
0
40
20
Figure 13. Filtered Mode with Ramp Rate = 8
Figure 14 shows how changing the ramp rate from 8 to 4 affects
the control loop. The overall response of the fan is slower. Since
the ramp rate is reduced, it takes longer for the fan to achieve full
running speed. In this case, it took approximately 22 seconds for
the fan to reach full speed.
0
0
112
TIME – s
Figure 16. Filtered Mode with Ramp Rate = 1
120
140
120
100
As can be seen from Figures 13 through 16, the rate at which
the fan will react to temperature change is dependent on the
ramp rate selected in the Fan Filter Register. The higher the
ramp rate, the faster the fan will reach the newly calculated
fan speed.
110
80
R
TEMP
Figure 17 shows the behavior of the PWM output as tempera-
ture varies. As the temperature is rising, the fan speed will ramp
up. Small drops in temperature will not affect the ramp-up func-
tion since the newly calculated fan speed will still be higher than
the previous PWM value. The Filtered Mode allows the PWM
output to be made less sensitive to temperature variations. This
will be dependent on the ramp rate selected and the ADC sample
rate programmed into the Fan Filter Register.
80
60
60
PWM DUTY CYCLE
40
20
0
40
20
0
0
22
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
TIME – s
Figure 14. Filtered Mode with Ramp Rate = 4
PWM DUTY CYCLE
Figure 15 shows the PWM output response for a ramp rate of 2.
In this instance the fan took about 54 seconds to reach full
running speed.
R
TEMP
140
120
100
80
120
100
80
R
TEMP
60
60
TIME – s
PWM DUTY CYCLE
40
20
Figure 17. How Fan Reacts to Temperature Variation in
Filtered Mode
40
20
0
0
0
54
TIME – s
Figure 15. Filtered Mode with Ramp Rate = 2
Rev. 2 | Page 17 of 29 | www.onsemi.com
ADM1030
Effect of ADC Sample Rate on Filtered Mode
PROGRAMMING THE FILTERED AUTOMATIC FAN
SPEED CONTROL LOOP
The second means by which to change the Filtered Mode char-
acteristics is to adjust the ADC sample rate. The faster the ADC
sample rate, the more temperature samples are obtained per
second. One way to apply filtering to the control loop is to
slow down the ADC sampling rate. This means that the num-
ber of iterations of the Filtered Mode algorithm per second
are effectively reduced. If the number of temperature measure-
ments per second are reduced, how often the PWM_OUT
signal controlling the fan is updated is also reduced.
1. Program a value for TMIN
2. Program a value for the slope TRANGE
3. TMAX = TMIN + TRANGE
.
.
.
4. Program a value for Fan Spin-up Time.
5. Program the desired Automatic Fan Speed Control Mode
Behavior, i.e., which temperature channel controls the fan.
6. Program a ramp rate for the filtered mode.
Bits <4:2> of the Fan Filter Register (Reg 0x23) set the ADC
sample rate. The default ADC sample rate is 1.4 kHz. The
ADC sample rate is selectable from 87.5 Hz to 11.2 kHz.
Table IX shows how many temperature samples are obtained
per second, for each of the ADC sample rates.
7. Program the ADC sample rate in the Fan Filter Register.
8. Set Bit 0 to enable fan filtered mode for the fan.
9. Select Automatic Fan Speed Control Mode by setting Bit 7 of
Configuration Register 1.
Table IX. Temperature Updates per Second
PWM DUTY CYCLE SELECT MODE
The ADM1030 may be operated under software control by clear-
ing Bit 7 of Configuration Register 1 (Register 0x00). This
allows the user to directly control PWM Duty Cycle.
ADC Sample Rate
Temperature Updates/Sec
87.5 Hz
175 Hz
350 Hz
700 Hz
1.4 kHz
2.8 kHz
5.6 kHz
11.2 kHz
0.0625
0.125
0.25
0.5
Clearing Bit 5 of Configuration Register 1 allows fan control by
varying PWM duty cycle. Values of duty cycle between 0% to
100% may be written to the Fan Speed Config Register (0x22)
to control the speed of the fan. Table X shows the relationship
between hex values written to the Fan Speed Configuration
Register and PWM duty cycle obtained.
1 (Default)
2
4
8
Table X. PWM Duty Cycle Select Mode
RELEVANT REGISTERS FOR FILTERED AUTOMATIC
FAN SPEED CONTROL MODE
Hex Value
PWM Duty Cycle
In addition to the registers used to program the normal Auto-
matic Fan Speed Control Mode, the following register needs to
be programmed.
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0%
7%
14%
20%
27%
33%
40%
47%
53%
60%
67%
73%
80%
87%
93%
100%
Register 0x23 Fan Filter Register
<7> Spin-up Disable :- when this bit is set to 1, fan spin-up
is disabled. (Default = 0)
<6:5> Ramp Rate: these bits set the ramp rate for filtered mode.
00 = 1 (0.416% Duty Cycle Change)
01 = 2 (0.833% Duty Cycle Change)
10 = 4 (1.66% Duty Cycle Change)
11 = 8 (3.33% Duty Cycle Change)
<4:2> ADC Sample Rate
000 = 87.5 Hz
001 = 175 Hz
010 = 350 Hz
011 = 700 Hz
100 = 1.4 kHz (Default)
101 = 2.8 kHz
110 = 5.6 kHz
111 = 11.2 kHz
<1> Unused. Default = 0
<0> Fan 1 Filter Enable: when this bit is set to 1, it enables
filtering on Fan 1. Default = 0.
Rev. 2 | Page 18 of 29 | www.onsemi.com
ADM1030
RPM FEEDBACK MODE
Example 1:
The second method of fan speed control under software is RPM
Feedback Mode. This involves programming the desired fan
RPM value to the device to set fan speed. The advantages include
a very tightly maintained fan RPM over the fan’s life, and virtu-
ally no acoustic pollution due to fan speed variation.
If the desired value for RPM Feedback Mode is 5000 RPM,
what value needs to be programmed for Count?
Count = (f ¥ 60)/R ¥ N
Since the desired RPM value, R, is 5000 RPM, the value for
Count is:
Fans typically have manufacturing tolerances of ±20%, meaning
a wide variation in speed for a typical batch of identical fan
models. If it is required that all fans run at exactly 5000 RPM,
it may be necessary to specify fans with a nominal fan speed of
6250 RPM. However, many of these fans will run too fast and
make excess noise. A fan with nominal speed of 6250 RPM
could run as fast as 7000 RPM at 100% PWM duty cycle. RPM
Mode will allow all of these fans to be programmed to run at the
desired RPM value.
N = 2:
Count = (11250 ¥ 60)/5000 ¥ 2
Count = 675000/10000
Count = 67 (assumes 2 tach pulses/rev).
Example 2:
If the desired value for RPM Feedback Mode is 3650 RPM,
what value needs to be programmed for Count?
Clearing Bit 7 of Configuration Register 1 (Reg 0x00) to 0
places the ADM1030 under software control. Once under soft-
ware control, the device may be placed in to RPM Feedback
Mode by writing to Bit 5 of Configuration Register 1. Writing a
1 to Bit 5 selects RPM Feedback Mode for the fan. Once RPM
Feedback Mode has been selected, the required fan RPM may
be written to the Fan Tach High Limit Register (0x10). The
RPM Feedback Mode function allows a fan RPM value to be
programmed into the device, and the ADM1030 will maintain
the selected RPM value by monitoring the fan tach and speed-
ing up the fan as necessary, should the fan start to slow down.
Conversely, should the fan start to speed up due to aging, the
RPM feedback will slow the fan down to maintain the correct
RPM speed. The value to be programmed into each Fan Tach
High Limit Register is given by:
Count = (f ¥ 60)/R ¥ N
Since the desired RPM value, R, is 3650 RPM, the value for
Count is:
N = 2:
Count = (11250 ¥ 60)/3650 ¥ 2
Count = 675000/7300
Count = 92 (assumes 2 tach pulses/rev).
Once the count value has been calculated, it should be written
to the Fan Tach High Limit Register. It should be noted that in
RPM Feedback Mode, there is no high limit register for under-
speed detection that can be programmed as there are in the
other fan speed control modes. The only time each fan will
indicate a fan failure condition is whenever the count reaches
255. Since the speed range N = 2, the fan will fail if its speed
drops below 1324 RPM.
Count = (f ¥ 60)/R ¥ N
where:
Programming RPM Values
1. Choose the RPM value to be programmed.
f = 11.25 kHz
R = desired RPM value
N = Speed Range; MUST be set to 2
2. Set speed range value, N = 2.
3. Calculate count value based on RPM and speed range val-
ues chosen. Use Count Equation to calculate Count Value.
The speed range, N, really determines what the slowest fan speed
measured can be before generating an interrupt. The slowest fan
speed will be measured when the count value reaches 255.
4. Clear Bit 7 of Configuration Register 1 (Reg. 0x00) to place
the ADM1030 under software control.
Since speed range, N, = 2,
Count = (f ¥ 60)/R ¥ N
R = (f ¥ 60)/Count ¥ N
5. Write a 1 to Bit 5 of Configuration Register 1 to place the
device in RPM Feedback Mode.
6. Write the calculated Count value to the Fan Tach High
Limit Register (Reg. 0x10). The fan speed will now go to
the desired RPM value and maintain that fan speed.
R = (11250 ¥ 60)/255 ¥ 2
R = (675000)/510
RPM Feedback Mode Limitations
R = 1324 RPM, fan fail detect speed.
RPM feedback mode only controls Fan RPM over a limited fan
speed range of about 75% to 100%. However, this should be
enough range to overcome fan manufacturing tolerance. In prac-
tice, however, the program must not function at too low an RPM
value for the fan to run at, or the RPM Mode will not operate.
Programming RPM Values in RPM Feedback Mode
Rather than writing a value such as 5000 to a 16-bit register, an
8-bit count value is programmed instead. The count to be pro-
grammed is given by:
Count = (f ¥ 60)/R ¥ N
where:
To find the lowest RPM value allowed for a given fan, do the
following:
f = 11.25 kHz
R = desired RPM value
N = Speed Range = 2
Rev. 2 | Page 19 of 29 | www.onsemi.com
ADM1030
+V
1. Run the fan at 53% PWM duty cycle in Software Mode. Clear
Bits 5 and 7 of Configuration Register 1 (Reg 0x00) to enter
PWM duty cycle mode. Write 0x08 to the Fan Speed Config
Register (Reg 0x22) to set the PWM output to 53% duty cycle.
3.3V
10k�
TYPICAL
TACH
5V OR 12V
FAN
TACH/AIN
2. Measure the fan RPM. This represents the fan RPM below
which the RPM mode will fail to operate. Do NOT program a
lower RPM than this value when using RPM Feedback mode.
3.3V
ADM1030
10k�
TYPICAL
Q1
NDT3055L
PWM_OUT
3. Ensure that Speed Range, N, = 2 when using RPM Feed-
back mode.
Fans come in a variety of different options. One distinguishing
feature of fans is the number of poles that a fan has internally.
The most common fans available have four, six, or eight poles.
The number of poles the fan has generally affects the number of
pulses per revolution the fan outputs.
Figure 18. Interfacing the ADM1030 to a 3-Wire Fan
The NDT3055L n-type MOSFET was chosen since it has 3.3 V
gate drive, low on-resistance, and can handle 3.5 A of current.
Other MOSFETs may be substituted based on the system’s fan
drive requirements.
If the ADM1030 is used to drive fans other than 4-pole fans that
output 2 tach pulses/revolution, then the fan speed measurement
equation needs to be adjusted to calculate and display the cor-
rect fan speed, and also to program the correct count value in
RPM Feedback Mode.
+V
5V OR 12V
FAN
3.3V
FAN SPEED MEASUREMENT EQUATIONS
For a 4-pole fan (2 tach pulses/rev):
10k�
TYPICAL
TACH
Q1
NDT3055L
PWM_OUT
Fan RPM = (f ¥ 60)/Count ¥ N
For a 6-pole fan (3 tach pulses/rev):
Fan RPM = (f ¥ 60)/(Count ¥ N ¥ 1.5)
For an 8-pole fan (4 tach pulses/rev):
Fan RPM = (f ¥ 60)/(Count ¥ N ¥ 2)
ADM1030
TACH/AIN
0.01ꢀF
R
SENSE
(2� TYPICAL)
If in doubt as to the number of poles the fans used have, or the
number of tach output pulses/rev, consult the fan manufacturer’s
data sheet, or contact the fan vendor for more information.
Figure 19. Interfacing the ADM1030 to a 2-Wire Fan
Figure 19 shows how a 2-wire fan may be connected to the
ADM1030. This circuit allows the speed of the 2-wire fan to
be measured even though the fan has no dedicated Tach sig-
nal. A series RSENSE resistor in the fan circuit converts the fan
commutation pulses into a voltage. This is ac-coupled into
the ADM1030 through the 0.01 mF capacitor. On-chip signal
conditioning allows accurate monitoring of fan speed. For typical
notebook fans drawing approximately 170 mA, a 2 W RSENSE
value is suitable. For fans such as desktop or server fans, that
draw more current, RSENSE may be reduced. The smaller RSENSE
is the better, since more voltage will be developed across the
fan, and the fan will spin faster. Figure 20 shows a typical plot
of the sensing waveform at the TACH/AIN pin. The most
important thing is that the negative-going spikes are more than
250 mV in amplitude. This will be the case for most fans when
RSENSE = 2 W. The value of RSENSE can be reduced as long as
the voltage spikes at the TACH/AIN pin are greater than 250 mV.
This allows fan speed to be reliably determined.
FAN DRIVE USING PWM CONTROL
The external circuitry required to drive a fan using PWM con-
trol is extremely simple. A single NMOS FET is the only drive
transistor required. The specifications of the MOSFET depend
on the maximum current required by the fan being driven. Typi-
cal notebook fans draw a nominal 170 mA, and so SOT devices
can be used where board space is a constraint. If driving several
fans in parallel from a single PWM output, or driving larger
server fans, the MOSFET will need to handle the higher current
requirements. The only other stipulation is that the MOSFET
should have a gate voltage drive, VGS < 3.3 V, for direct inter-
facing to the PWM_OUT pin. The MOSFET should also have
a low on-resistance to ensure that there is not significant volt-
age drop across the FET. This would reduce the maximum
operating speed of the fan.
Figure 18 shows how a 3-wire fan may be driven using
PWM control.
Rev. 2 | Page 20 of 29 | www.onsemi.com
ADM1030
Tek PreVu
T
T
CLOCK
D: 250mV
@: –258mV
CONFIG 2
REG. BIT 2
1
FAN
INPUT
START OF
MONITORING
CYCLE
FAN
MEASUREMENT
PERIOD
Figure 21. Fan Speed Measurement
In situations where different output drive circuits are used for
fan drive, it may be desirable to invert the PWM drive signal.
Setting Bit 3 of Configuration Register 1 (0x00) to 1, inverts the
PWM_OUT signal. This makes the PWM_OUT pin high for
100% duty cycle. Bit 3 of Configuration Register 1 should gen-
erally be set to 1, when using an n-MOS device to drive the fan.
If using a p-MOS device, Bit 3 of Configuration Register 1
should be cleared to 0.
4
C
H
1
100mV
CH2 5.00mV M 4.00ms
CH4 50.0mV
A CH1 –2.00mV
CH3 50.0mV
Figure 20. Fan Speed Sensing Waveform at TACH/AIN Pin
FAN SPEED MEASUREMENT
The fan counter does not count the fan tach output pulses
directly, because the fan speed may be less than 1000 RPM
and it would take several seconds to accumulate a reasonably
large and accurate count. Instead, the period of the fan revolu-
tion is measured by gating an on-chip 11.25 kHz oscillator into
the input of an 8-bit counter. The fan speed measuring circuit is
initialized on the rising edge of a PWM high output if fan speed
measurement is enabled (Bit 2 of Configuration Register 2 =
1). It then starts counting on the rising edge of the second tach
pulse and counts for two fan tach periods, until the rising edge of
the fourth tach pulse, or until the counter overranges if the fan
tach period is too long. The measurement cycle will repeat until
monitoring is disabled. The fan speed measurement is stored in
the Fan Speed Reading register at address 0x08.
FAN FAULTS
The FAN_FAULT output (Pin 8) is an active-low, open-drain
output used to signal fan failure to the system processor. Writing a
Logic 1 to Bit 4 of Configuration Register 1 (0x00) enables the
FAN_FAULT output pin. The FAN_FAULT output is enabled
by default. The FAN_FAULT output asserts low only when
five consecutive interrupts are generated by the ADM1030 device
due to the fan running underspeed, or if the fan is completely
stalled. Note that the Fan Tach High Limit must be exceeded
by at least one before a FAN_FAULT can be generated. For
example, if we are only interested in getting a FAN_FAULT if
the fan stalls, then the fan speed value will be 0xFF for a failed
fan. Therefore, we should make the Fan Tach High Limit =
0xFE to allow FAN_FAULT to be asserted after five consecu-
tive fan tach failures.
The fan speed count is given by:
Count = (f ¥ 60)/R ¥ N
where:
Figure 22 shows the relationship between INT, FAN_FAULT,
and the PWM drive channel. The PWM_OUT channel is driv-
ing a fan at some PWM duty cycle, say 50%, and the fan’s tach
signal (or fan current for a 2-wire fan) is being monitored at the
TACH/AIN pin. Tach pulses are being generated by the fan,
during the high time of the PWM duty cycle train. The tach is
pulled high during the off time of the PWM train because the
fan is connected high-side to the n-MOS device.
f
=
=
=
11.25 kHz
R
N
Fan Speed in RPM.
Speed Range (Either 1, 2, 4, or 8)
The frequency of the oscillator can be adjusted to suit the expected
running speed of the fan by varying N, the Speed Range. The
oscillator frequency is set by Bits 7 and 6 of Fan Characteristics
Register 1 (20h) as shown in Table XI. Figure 21 shows how the
fan measurements relate to the PWM_OUT pulse trains.
Suppose the fan has already failed its fan speed measurement
twice previously. Looking at Figure 22, PWM_OUT is brought
high for two seconds, to restart the fan if it has stalled. Some-
time later a third tach failure occurs. This is evident by the tach
signal being low during the high time of the PWM pulse, causing
the Fan Speed Reading register to reach its maximum count of
255. Since the tach limit has been exceeded, an interrupt is
generated on the INT pin. The Fan Fault bit (Bit 1) of Inter-
rupt Status Register 1 (Register 0x02) will also be asserted.
Once the processor has acknowledged the INT by reading the
status register, the INT is cleared. PWM_OUT is then brought
high for another 2 seconds to restart the fan. Subsequent fan
failures cause INT to be reasserted and the PWM_OUT signal
is brought high for 2 seconds (fan spin-up default) each time to
restart the fan. Once the fifth tach failure occurs, the failure is
deemed to be catastrophic, and the FAN_FAULT pin is asserted
low. PWM_OUT is brought high to attempt to restart the fan.
Table XI. Oscillator Frequencies
Oscillator
Frequency (kHz)
Bit 7
Bit 6
N
0
0
1
1
0
1
0
1
1
2
4
8
11.25
5.625
2.812
1.406
Rev. 2 | Page 21 of 29 | www.onsemi.com
ADM1030
Figure 23 shows a typical application circuit for the ADM1030.
Temperature monitoring can be based around a CPU diode or
discrete transistor measuring thermal hotspots. Either 2- or
3-wire fans may be monitored by the ADM1030, as shown.
The INT pin will continue to generate interrupts after the asser-
tion of FAN_FAULT since tach measurement continues even
after fan failure. Should the fan recover from its failure condi-
tion, the FAN_FAULT signal will be negated, and the fan will
return to its normal operating speed.
PWM_OUT
TACH/AIN
2 SECS
FULL SPEED
2 SECS
2 SECS
3RD TACH
FAILURE
5TH TACH
FAILURE
4TH TACH
FAILURE
INT
STATUS REG READ TO
CLEAR INTERRUPT
CONTINUING
TACH FAILURE
FAN_FAULT
Figure 22. Operation of FAN_FAULT and Interrupt Pins
5V
3.3V
10k�
TYP.
FAN1
3-WIRE
FAN
3.3V 3.3V
TACH
2.2k�
TYP.
2.2k�
TYP.
3.3V
SCL
SDA
10k�
TYP.
PWM_OUT1
SCL
SDA
NDT3055L
3.3V
1
2
16
15
TACH1/AIN1
10k�
TYP.
INT (SMBALERT)
NC
NC
3
4
5
6
7
8
14
13
12
11
10
9
CPU INTERRUPT
ADD
ADM1030
GND
3.3V
3.3V
10k�
NC
V
CC
NC
D+
THERM
THERM
SIGNAL TO
THROTTLE
CPU CLOCK
FAN_FAULT
3.3V
10k�
D-
2N3904 OR PENTIUM III
CPU THERMAL DIODE
FAN_FAULT
TO SIGNAL
NC = NO CONNECT
FAN FAILURE
CONDITION
Figure 23. Typical Application Circuit
Rev. 2 | Page 22 of 29 | www.onsemi.com
ADM1030
Table XII. Registers
Address A7–A0
Register Name
in Hex
Comments
Value Registers
Device ID Register
0x06–0x1A
0x3D
See Table XIII.
This location contains the device identification number. Since this
device is the ADM1030, this register contains 0x30. This register is
read only.
Company ID
0x3E
0x3F
This location contains the company identification number (0x41).
This register is read only.
This location contains the revision number of the device. The lower
four bits reflect device revisions [3:0]. Bit 7 of this register is the
THERM-to-fan enable bit. See Table XXIV.
THERM Behavior/Revision
Configuration Register 1
Configuration Register 2
Status Register 1
Status Register 2
Manufacturer’s Test Register
0x00
0x01
0x02
0x03
0x07
See Table XIV. Power-on value = 1001 0000.
See Table XV. Power-on value = 0111 1111.
See Table XVI. Power-on value = 0000 0000.
See Table XVII. Power-on value = 0000 0000.
This register is used by the manufacturer for test purposes only. This
register should not be read from or written to in normal operation.
See Table XIX. Power-on value = 0101 1101.
See Table XX. Power-on value = 0101 0101.
See Table XXI. Power-on value = 0101 0101.
See Table XXII. Power-on value = 0100 0001.
See Table XXIII. Power-on value = 0110 0001.
Fan Characteristics Register 1
Fan Speed Configuration Register
Fan Filter Register
Local Temperature TMIN/TRANGE
Remote Temperature TMIN/TRANGE
0x20
0x22
0x23
0x24
0x25
Table XIII. Value and Limit Registers
Address
Read/Write
Description
0x06
0x08
0x0A
0x0B
0x0D
0x0E
0x10
Read/Only
Read/Write
Read/Only
Read/Only
Read/Write
Read/Write
Read/Write
Extended Temperature Resolution (see Table XVIII).
Fan Speed Reading—this register contains the fan speed tach measurement.
Local Temperature Value—this register contains the 8 MSBs of the local temperature measurement.
Remote Temperature Value—this register contains the 8 MSBs of the remote temperature reading.
Local Temperature Offset—See Table XXV.
Remote Temperature Offset—See Table XXVI.
Fan Tach High Limit—this register contains the limit for the fan tach measurement. Since
the tach circuit counts between pulses, a slow fan will result in a large measured value, so
exceeding the limit by one is the way to detect a slow or stalled fan. (Power-On Default = FFh)
Local Temperature High Limit (Power-On Default 60rC).
Local Temperature Low Limit (Power-On Default 0rC).
Local Temperature Therm Limit (Power-On Default 70rC).
Remote Temperature High Limit (Power-On Default 80rC).
Remote Temperature Low Limit (Power-On Default 0rC).
Remote Temperature Therm Limit (Power-On Default 100rC).
0x14
0x15
0x16
0x18
0x19
0x1A
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Rev. 2 | Page 23 of 29 | www.onsemi.com
ADM1030
Table XIV. Register 0x00 Configuration Register 1 Power-On Default 90h
Bit Name
R/W
Description
0
1
2
MONITOR
Read/Write
Read/Write
Read/Write
Setting this bit to a “1” enables monitoring of temperature and enables measurement of
the fan tach signals. (Power-Up Default = 0.)
Setting this bit to a “1” enables the INT output. 1 = Enabled 0 = Disabled (Power-Up
Default = 0).
Clearing this bit to “0” selects digital fan speed measurement via the TACH pins. Setting
this bit to “1” configures the TACH pins as analog inputs that can measure the speed of
2-wire fans via a sense resistor. (Power-Up Default = 0.)
INT Enable
TACH/AIN
3
PWM Invert
Read/Write
Setting this bit to “1” inverts the PWM signal on the output pin. (Power-Up Default =
0). The power-up default makes the PWM_OUT pin go low for 100% duty cycle (suitable
for driving the fan using a PMOS device). Setting this bit to “1” makes the PWM_OUT
pin high for 100% duty cycle (intended for driving the fan using an NMOS device).
Logic 1 enables FAN_FAULT pin; Logic 0 disables FAN_FAULT output. (Power-Up
Default = 1.)
4
Fan Fault Enable Read/Write
6–5 PWM Mode
Read/Write
Read/Write
These two bits control the behavior of the fan in Auto Fan Speed Control Mode.
00 = Remote Temp controls Fan. (Program PWM duty cycle in Software Mode.)
11 = Fastest Calculated Speed Controls Fan. (Program RPM speed in Software Mode.)
Logic 1 selects Automatic Fan Speed Control; Logic 0 selects SW control. (Power-Up
Default = 1) When under software control, PWM duty cycle or RPM values may be
programmed for the fan.
7
Auto/SW Ctrl
Table XV. Register 0x01 Configuration 2 Power-On Default = 7FH
Bit
Name
R/W
Description
0
1
2
3
4
5
PWM 1 En
Unused
TACH 1 En
Unused
Loc Temp En
Remote Temp En
Read/Write
Read/Write
Read/Write
Enables fan PWM output when this bit is a “1.”
Unused.
Enables Tach input when set to “1.”
Read/Write
Read/Write
Enables Interrupts on Local Channel when set to “1.”
Enables Interrupts on Remote Channel when set to “1.” Default is normally
enabled, except when a diode fault is detected on power-up.
Unused.
6
7
Unused
SW Reset
Read/Write
Read/Write
When set to “1,” resets the device. Self-clears. Power-Up Default = 0.
Rev. 2 | Page 24 of 29 | www.onsemi.com
ADM1030
Table XVI. Register 0x02 Status Register 1 Power-On Default = 00H
Bit
Name
R/W
Description
0
Alarm Speed
Read Only
This bit is set to “1” when fan is running at alarm speed. Once read, this bit
will not reassert on next monitoring cycle, even if the fan is still running at
alarm speed. This gives an indication as to when the fan is running full-speed,
such as in a THERM condition.
1
2
3
4
5
6
7
Fan Fault
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
This bit is set to “1” if fan becomes stuck or is running under speed. Once
read, this bit will reassert on next monitoring cycle, if the fan failure condi-
tion persists.
“1” indicates Remote high temperature limit has been exceeded. If the tem-
perature is still outside the Remote Temp High Limit, this bit will reassert on
next monitoring cycle.
“1” indicates Remote low temperature limit exceeded (below). If the tempera-
ture is still outside the Remote Temp Low Limit, this bit will reassert on next
monitoring cycle.
“1” indicates Remote temperature Therm limit has been exceeded. This bit is
cleared on a read of Status Register 1. Once cleared, this bit will not get reas-
serted even if the THERM condition persists.
This bit is set to “1” if a short or open is detected on the remote temperature
channel. This test is only done on power-up, and if set to 1 cannot be cleared
by reading the Status Register 1.
“1” indicates Local Temp High Limit has been exceeded. If the temperature
is still outside the Local Temp High Limit, this bit will reassert on next
monitoring cycle.
“1” indicates Local Temp Low Limit has been exceeded (below). If the tem-
perature is still outside the Local Temp Low Limit, this bit will reassert on
next monitoring cycle.
Remote Temp High
Remote Temp Low
Remote Temp Therm
Remote Diode Error
Loc Temp High
Loc Temp Low
Table XVII. Register 0x03 Status Register 2 Power-Up Default = 00H
R/W Description
Bit
Name
0
1
2
3
4
5
6
Unused
Unused
Unused
Unused
Unused
Unused
Loc Therm
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Unused.
Unused.
Unused.
Unused.
Unused.
Unused.
“1” indicates Local temperature Therm limit has been exceeded. This bit clears on a read
of Status Register 2. Once cleared, this bit will not be reasserted even if the THERM con-
dition persists.
7
THERM
Read Only
Set to “1” when THERM is pulled low as an input. This bit clears on a read of Status
Register 2. The fan also runs full-speed.
Table XVIII. Register 0x06 Extended Temperature Resolution Power-On Default = 00H
Bit
Name
R/W
Description
<2:0> Remote Temp Read Only
Holds extended temperature resolution bits for Remote Temperature channel.
Reserved.
Holds extended temperature resolution bits for Local Temperature channel.
<5:3> Reserved
Read Only
Read Only
<7:6> Local Temp
Rev. 2 | Page 25 of 29 | www.onsemi.com
ADM1030
Table XIX. Register 0x20 Fan Characteristics Register 1 Power-On Default = 5DH
Bit
Name
R/W
Description
<2:0>
Fan 1 Spin-up
PWM 1 Frequency
Speed Range
Read/Write
These bits contain the Fan Spin-up time to allow the fan to overcome its own
inertia.
000 = 200 ms
001 = 400 ms
010 = 600 ms
011 = 800 ms
100 = 1 sec
101 = 2 secs (Default)
110 = 4 secs
111 = 8 secs
<5:3>
Read/Write
These bits allow programmability of the nominal PWM output frequency
driving the fan. (Default = 31 Hz.)
000 = 11.7 Hz
001 = 15.6 Hz
010 = 23.4 Hz
011 = 31.25 Hz (Default)
100 = 37.5 Hz
101 = 46.9 Hz
110 = 62.5 Hz
111 = 93.5 Hz
These bits contain the Speed Range, N.
00 = 1 (Fail Speed = 2647 RPM)
01 = 2 (Fail Speed = 1324 RPM)
10 = 4 (Fail Speed = 662 RPM)
11 = 8 (Fail Speed = 331 RPM)
<7:6>
Read/Write
Table XX. Register 0x22 Fan Speed Config Register Power-On Default = 05H
Bit
Name
R/W
Description
<3:0>
Normal/Min Spd 1
Read/Write
This nibble contains the normal speed value for the fan. When in Automatic
Fan Speed Control Mode, this nibble contains the minimum speed at which
the fan will run. Default is 0x05 for 33% PWM duty cycle. (See Table VII.)
Unused.
<7:4>
Unused
Table XXI. Register 0x23 Fan Filter Register Power-On Default = 50H
Bit
Name
R/W
Description
<7>
<6:5>
Spin-Up Disable
Ramp Rate
Read/Write
Read/Write
When set to 1, disables fan spin-up.
These bits set the ramp rate for the PWM output.
00 = 1
01 = 2
10 = 4
11 = 8
<4:2>
ADC Sample Rate
Read/Write
These bits set the sampling rate for the ADC.
000 = 87.5 Hz 0.0625 Updates/sec
001 = 175 Hz 0.125 Updates/sec
010 = 350 Hz 0.25 Updates/sec
011 = 700 Hz 0.5 Updates/sec
100 = 1.4 kHz (Default) 1 Update/sec
101 = 2.8 kHz 2 Updates/sec
110 = 5.6 kHz 4 Updates/sec
111 = 11.2 kHz 8 Updates/sec
Unused.
<1>
<0>
Unused
Fan Filter En
Read/Write
Read/Write
Setting this bit to 1 enables filtering of the PWM_OUT signal.
Rev. 2 | Page 26 of 29 | www.onsemi.com
ADM1030
Table XXII. Register 0x24 Local Temp TMIN/TRANGE Power-On Default = 41H
Bit
Name
R/W
Description
<7:3> Local Temp TMIN
Read/Write
Contains the minimum temperature value for Automatic Fan Speed Control
based on Local Temperature Readings. TMIN can be programmed to positive
values only in 4rC increments. Default is 32rC.
00000 = 0rC
00001 = 4rC
00010 = 8rC
00011 = 12rC
|
|
01000 = 32rC (Default)
|
|
|
11110 = 120rC
11111 = 124rC
<2:0> Local Temp TRANGE
Read/Write
This nibble contains the temperature range value for Automatic Fan Speed
Control based on the Local Temperature Readings.
000 = 5rC
001 = 10rC (Default)
010 = 20rC
011 = 40rC
100 = 80rC
Table XXIII. Register 0x25 Remote Temp TMIN/TRANGE Power-On Default = 61H
Bit
Name
R/W
Description
<7:3> Remote Temp TMIN
Read/Write
Contains the minimum temperature value for Automatic Fan Speed Control
based on Remote Temperature Readings. TMIN can be programmed to posi-
tive values only in 4rC increments. Default is 48rC.
00000 = 0rC
00001 = 4rC
00010 = 8rC
00011 = 12rC
|
|
01100 = 48rC (Default)
|
|
11110 = 120rC
11111 = 124rC
<2:0> Remote Temp TRANGE
Read/Write
This nibble contains the temperature range value for Automatic Fan Speed
Control based on the Remote 1 Temperature Readings.
000 = 5rC
001 = 10rC (Default)
010 = 20rC
011 = 40rC
100 = 80rC
Rev. 2 | Page 27 of 29 | www.onsemi.com
ADM1030
Table XXIV. Register 0x3F Therm Behavior/Revision Power-On Default = 80H
Bit
Name
R/W
Description
<7>
Therm-to-Fan Enable Read/Write
Setting this bit to 1, enables the fan to run full-speed when THERM is asserted low.
This allows the system to be run in performance mode. Clearing this bit to 0 disables
the fan from running full-speed whenever THERM is asserted low. This allows
the system to run in silent mode. (Power-On Default = 1.) Note that this bit has
no effect whenever THERM is pulled low as an input.
<6:4> Unused
<3:0> Revision
Read Only
Read Only
Unused. Read back zeros.
This nibble contains the revision number for the ADM1030.
Table XXV. Register 0x0D Local Temp Offset Power-On Default = 00H
Bit
Name
R/W
Description
<7>
Sign
Read/Write
When this bit is 0, the local offset will be added to the Local Temperature Reading.
When this bit is set to 1, the local temperature offset will be subtracted from the
Local Temperature Reading.
<6:4>
<3:0>
Reserved
Local Offset
Read/Write
Read/Write
Unused. Normally read back zeros.
These four bits are used to add a two’s complement offset to the Local Temperature
Reading, allowing 15rC to be added to or subtracted from the temperature reading.
Table XXVI. Register 0x0E Remote Temp Offset Power-On Default = 00H
Bit
Name
R/W
Description
<7>
Sign
Read/Write
When this bit is 0, the remote offset will be added to the Remote Temperature
Reading. When this bit is set to 1, the remote temperature offset will be subtracted
from the Remote Temperature Reading.
<6:4>
<3:0>
Reserved
Remote Offset
Read/Write
Read/Write
Unused. Normally read back zeros.
These four bits are used to add a two’s complement offset to the Remote
Temperature Reading, allowing 15rC to be added to or subtracted from the
temperature reading.
Rev. 2 | Page 28 of 29 | www.onsemi.com
ADM1030
OUTLINE DIMENSIONS
16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
0.193
BSC
16
1
9
8
0.154
BSC
0.236
BSC
PIN 1
0.069
0.053
0.065
0.049
8�
0�
0.010
0.004
0.012
0.008
0.025
BSC
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AB
ORDERING GUIDE
Model
Temperature Range Package Description Package Option
ADM1030ARQ
0°C to 100°C
0°C to 100°C
0°C to 100°C
0°C to 100°C
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
ADM1030ARQ-REEL
ADM1030ARQ-REEL7
ADM1030ARQZ1
ADM1030ARQZ-REEL1 0°C to 100°C
ADM1030ARQZ-RL71
0°C to 100°C
1Z = Pb-Free part
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights
of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and
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literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative
Rev. 2 | Page 29 of 29 | www.onsemi.com
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