74VCX08BQX [ONSEMI]
低电压四路 2 输入 AND 门极,带 3.6V 耐压输入和输出;型号: | 74VCX08BQX |
厂家: | ONSEMI |
描述: | 低电压四路 2 输入 AND 门极,带 3.6V 耐压输入和输出 栅 逻辑集成电路 触发器 |
文件: | 总13页 (文件大小:937K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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December 2013
74VCX08
Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant
Inputs and Outputs
Features
General Description
■ 1.2V to 3.6V V supply operation
The VCX08 contains four 2-input ꢀND gates. This prod-
CC
uct is designed for low voltage (1.2V to 3.6V) V appli-
cations with I/O compatibility up to 3.6V.
■ 3.6V tolerant inputs and outputs
CC
■ t
:
PD
The VCX08 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
– 2.8ns max. for 3.0V to 3.6V V
CC
■ Power-off high impedance inputs and outputs
■ Static Drive (I /I
)
OH OL
–
24mꢀ ꢁ 3.0V V
CC
■ Uses proprietary Quiet Series™ noise/EMI reduction
circuitry
■ Latchup performance exceeds 300mꢀ
■ ESD performance:
– Human body model > 2000V
– Machine model > 250V
■ Leadless DQFN package
Ordering Information
Package
Order Number
Number
Package Description
74VCX08M
M14ꢀ
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
(1)
74VCX08BQX
MLP14ꢀ
MTC14
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 3.0mm
74VCX08MTC
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
ꢀll packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
Connection Diagrams
Logic Symbol
Pin Assignments for SOIC and TSSOP
IEEE/IEC
Pad Assignments for DQFN
(Top View)
(Bottom View)
Pin Description
Pin Names
Description
ꢀ , B
Inputs
n
n
O
Outputs
n
DAP
No Connect
Note: DAP (Die Attach Pad)
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
Supply Voltage
–0.5V to +4.6V
–0.5V to 4.6V
CC
V
DC Input Voltage
DC Output Voltage
HIGH or LOW State
I
V
O
(2)
–0.5V to V +0.5V
CC
V
= 0V
–0.5V to +4.6V
–50mꢀ
CC
I
DC Input Diode Current, V < 0V
IK
I
I
DC Output Diode Current
OK
V
< 0V
–50mꢀ
+50mꢀ
O
V
> V
CC
O
I
/ I
DC Output Source/Sink Current
+50mꢀ
OH OL
I
or GND DC V or Gound Current per Supply Pin
100mꢀ
CC
CC
T
Storage Temperature Range
–65°C to +150°C
STG
Note:
2. I ꢀbsolute Maximum Rating must be observed.
O
(3)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Power Supply Operating
Input Voltage
1.2V to 3.6V
–0.3V to 3.6V
0V to V
CC
V
I
V
Output Voltage, HIGH or LOW State
Output Current
O
CC
I
/ I
OH OL
V
V
V
V
V
= 3.0V to 3.6V
= 2.3V to 2.7V
= 1.65V to 2.3V
= 1.4V to 1.6V
= 1.2V
24mꢀ
18mꢀ
CC
CC
CC
CC
CC
6mꢀ
2mꢀ
100ꢂꢀ
T
Free ꢀir Operating Temperature
Minimum Input Edge Rate, V = 0.8V to 2.0V, V = 3.0V
–40°C to +85°C
10ns/V
ꢀ
∆t / ∆V
IN
CC
Note:
3. Floating or unused inputs must be held HIGH or LOW
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
3
DC Electrical Characteristics
Symbol
Parameter
V
(V)
Conditions
Min
2.0
Max
Units
CC
V
HIGH Level Input Voltage
2.7–3.6
2.3–2.7
1.65–2.3
1.4–1.6
1.2
V
IH
1.6
0.65 × V
0.65 × V
0.65 × V
CC
CC
CC
V
LOW Level Input Voltage
HIGH Level Output Voltage
2.7–3.6
2.3–2.7
1.65–2.3
1.4–1.6
1.2
0.8
0.7
V
V
IL
0.35 × V
0.35 × V
0.05 x V
CC
CC
CC
V
2.7–3.6
2.7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= –100ꢂꢀ
= –12mꢀ
= –18mꢀ
= –24mꢀ
= –100ꢂꢀ
= –6mꢀ
= –12mꢀ
= –18mꢀ
= –100ꢂꢀ
= –6mꢀ
= –100ꢂꢀ
= –2mꢀ
= –100ꢂꢀ
= 100ꢂꢀ
= 12mꢀ
= 18mꢀ
= 24mꢀ
= 100ꢂꢀ
= 12mꢀ
= 18mꢀ
= 100ꢂꢀ
= 6mꢀ
V
– 0.2
CC
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
2.2
3.0
2.4
2.2
3.0
2.3–2.7
2.3
V
– 0.2
CC
2.0
1.8
1.7
2.3
2.3
1.65–2.3
1.65
V
V
V
– 0.2
CC
1.25
– 0.2
1.4–1.6
1.4
CC
1.05
– 0.2
1.2
CC
V
LOW Level Output Voltage
2.7–3.6
2.7
0.2
0.4
0.4
0.55
0.2
0.4
0.6
0.2
0.2
0.2
0.35
0.05
5.0
10
V
OL
3.0
3.0
2.3–2.7
2.3
2.3
1.65–2.3
1.65
1.4–1.6
1.4
= 100ꢂꢀ
= 2mꢀ
1.2
= 100ꢂꢀ
I
Input Leakage Current
1.2–3.6
0
0 ≤ V ≤ 3.6V
ꢂꢀ
ꢂꢀ
ꢂꢀ
I
I
I
Power-OFF Leakage Current
Quiescent Supply Current
0 ≤ (V , V ) ≤ 3.6V
I O
OFF
I
1.2–3.6
V = V or GND
20
CC
I
CC
V
V
≤ V ≤ 3.6V
20
CC
I
∆I
Increase in I per Input
2.7–3.6
= V –0.6V
750
ꢂꢀ
CC
CC
IH
CC
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
4
(4)
AC Electrical Characteristics
T = –40°C to
A
+85°C
Figure
Symbol
Parameter
V
(V)
Conditions
Min.
0.6
0.8
1.0
1.0
1.5
Max.
2.8
Units Number
CC
t
, t
Propagation Delay
3.3 0.3 C = 30pF, R = 500Ω
ns
Fig. 1
Fig. 2
PHL PLH
L
L
2.5 0.2
3.7
1.8 0.15
7.4
1.5 0.1 C = 15pF, R = 2kΩ
14.8
37.0
0.5
Fig. 3
Fig. 4
L
L
1.2
3.3 0.3 C = 30pF, R = 500Ω
t
, t
Output to Output
ns
OSHL OSLH
L
L
(5)
Skew
2.5 0.2
0.5
1.8 0.15
0.75
1.5
1.5 0.1 C = 15pF, R = 2kΩ
L
L
1.2
1.5
Note:
4. For C = 50pF, add approximately 300ps to the ꢀC Maximum specification.
L
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
) or LOW-to-HIGH (t
).
OSHL
OSLH
Dynamic Switching Characteristics
T = 25°C
A
Symbol
Parameter
V
(V)
Conditions
Typical
0.25
0.6
Unit
CC
V
Quiet Output Dynamic Peak V
1.8
C = 30pF, V = V
,
V
OLP
OL
L
IH
CC
V
= 0V
IL
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
0.8
V
Quiet Output Dynamic Valley V
Quiet Output Dynamic Valley V
C = 30pF, V = V
,
–0.25
–0.6
–0.8
1.5
V
V
OLV
OL
L
IH
CC
V
= 0V
IL
V
C = 30pF, V = V
,
OHV
OH
L
IH
CC
V
= 0V
IL
1.9
2.2
Capacitance
T = +25°C
A
Symbol
Parameter
Conditions
Typical
6.0
Units
pF
C
Input Capacitance
Output Capacitance
V = 0V or V , V = 1.8V, 2.5V or 3.3V
I CC CC
IN
C
V = 0V or V , V = 1.8V, 2.5V or 3.3V
7.0
pF
OUT
I
CC CC
C
Power Dissipation
Capacitance
V = 0V or V , f = 10MHz, V = 1.8V, 2.5V or 3.3V
20.0
pF
PD
I
CC
CC
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
5
AC Loading and Waveforms (V 3.3V 0.3V to 1.8V 0.15V)
CC
Test
Switch
t
, t
Open
PLH PHL
Figure 1. AC Test Circuit
V
CC
Symbol
3.3V 0.3V
1.5V
2.5V 0.2V
1.8V 0.15V
V
V
V
/ 2
/ 2
V
V
/ 2
/ 2
mi
CC
CC
CC
CC
V
1.5V
mo
Figure 2. Waveform for Inverting and Non-inverting Functions
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
6
AC Loading and Waveforms (V 1.5 0.1V to 1.2V)
CC
Test
Switch
t
, t
Open
PLH PHL
t
, t
V
x 2 at V = 1.5V 0.1V
PZL PLZ
CC
CC
t
, t
GND
PZH PHZ
Figure 3. AC Test Circuit
V
CC
Symbol
1.5V 0.1V
V
V
V
/ 2
/ 2
mi
CC
CC
V
mo
Figure 4. Waveform for Inverting and Non-Inverting Functions
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
7
Tape and Reel Specification
Tape Format for DQFN
Package Designator
Tape Section
Number of Cavities
125 (Typ.)
Cavity Status
Empty
Cover Tape Status
Sealed
BQX
Leader (Start End)
Carrier
3000
Filled
Sealed
Trailer (Hub End)
75 (Typ.)
Empty
Sealed
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
A
B
C
D
N
W1
W2
12mm
13.0 (330.0)
0.059 (1.50)
0.512 (13.00) 0.795 (20.20) 2.165 (55.00)
0.488 (12.4)
0.724 (18.4)
©1999 Fairchild Semiconductor Corporation
74VCX08 Rev. 1.9.1
www.fairchildsemi.com
8
0.65
A
ꢀꢁꢂꢂꢂꢁꢃꢂ
0.43TYP
14
8
B
6.4
ꢄꢁꢄꢂꢂꢁꢃꢂ
6.10
3.2
1.65
0.2 C B A
ALL LEAD TIPS
1
7
PIN#1 IDENT
TOP VIEW
0.45
RECOMMENDED LAND PATTERN
SEE DETAIL A
1.2 MAX
+0.15
-0.10
0.90
0.20
0.09
ꢂꢁꢃꢂꢂꢁꢂꢀ
0.30
0.19
ALL LEAD TIPS
C
0.1 C
0.13
A B
C
0.65
ꢃꢅꢁꢂꢂꢆ723ꢆꢇꢆ%27720
FRONT VIEW
0.09 MIN
NOTES:
GAGE PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 2009.
0.25
0.09 MIN
ꢂꢉꢆꢊ
ꢂꢁꢈꢂꢁꢃ
1.00
SEATING PLANE
DETAIL A
E. LANDPATTERN STANDARD: SOP65P640X110-14M.
F. DRAWING FILE NAME: MKT-MTC14rev7.
8.75
8.50
A
0.65
7.62
14
8
14
8
B
4.00
3.80
5.60
6.00
1.70
1
7
PIN #1
IDENT.
1
7
1.27
0.51
0.35
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
TOP VIEW
1.75 MAX
A
0.25
0.19
C
0.10 C
NOTES:
1.50
1.25
0.25
0.10
SIDE VIEW
FRONT VIEW
A. CONFORMS TO JEDEC MS-012,
VARIATION AB, ISSUE C
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS
0.50
0.25
x 45
R0.10
GAGE
PLANE
D. LAND PATTERN STANDARD:
SOIC127P600X145-14M
R0.10
E. CONFORMS TO ASME Y14.5M, 2009
D. DRAWING FILENAME: MKT-M14Arev14
0.36
8°
0°
0.90
0.50
SEATING PLANE
(1.04)
DETAIL A
SCALE 16 : 1
4.00 MAX
2.20 MAX
1.40 MAX
B
3.00
0.05 C
A
2X
1.00
MAX
1.70
MAX
2.50
0.50 TYP
3.50
MAX
(0.90)
0.05 C
TOP VIEW
2X
PIN #1 QUADRANT
0.50 TYP
0.24 TYP
ꢀꢁꢈꢀꢀꢁꢀꢃ
RECOMMENDED LAND PATTERN
0.10 C
ꢀꢁꢂꢀꢀꢁꢀꢃ
0.08 C
ꢀꢁꢀꢂꢃꢀꢁꢀꢂꢃ
C
SIDE VIEW
SEATING
PLANE
ꢄꢁꢀꢀꢀꢁꢀꢃ
ꢅꢁꢆꢃꢀꢁꢀꢃ
ꢀꢁꢄꢇꢀꢀꢁꢀꢃ
(14X)
A. CONFORMS TO JEDEC REGISTRATION
MO-241, VARIATION AA
PIN #1 IDENT
0.50
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
ꢅꢁꢅꢃꢀꢁꢀꢃ
ꢂꢁꢃꢀꢀꢁꢀꢃ
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP14Arev2.
ꢀꢁꢂꢃꢀꢁꢀꢃ
(14X)
0.50
0.10
0.05
C A B
C
2.00
BOTTOM VIEW
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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相关型号:
74VCX08MX_NL
AND Gate, ALVC/VCX/A Series, 4-Func, 2-Input, CMOS, PDSO14, 0.150 INCH, LEAD FREE, MS-012, SOIC-14
FAIRCHILD
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