74LVTH574MTC_技术文档

Is Now Part of

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Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON

Semiconductor data sheets and/or speciﬁcations can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s

technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA

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is an Equal Opportunity/Afﬁrmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

January 2008

74LVT574, 74LVTH574

Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Features

General Description

■ Input and output interface capability to systems at

The LVT574 and LVTH574 are high-speed, low-power

octal D-type flip-flop featuring separate D-type inputs for

each flip-flop and 3-STATE outputs for bus-oriented

applications. A buffered Clock (CP) and Output Enable

(OE) are common to all flip-flops.

5V V

CC

■ Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH574),

also available without bushold feature (74LVT574)

■ Live insertion/extraction permitted

The LVTH574 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

■ Power Up/Down high impedance provides glitch-free

bus loading

■ Outputs source/sink –32mA/+64mA

■ Functionally compatible with the 74 series 574

■ Latch-up performance exceeds 500mA

■ ESD performance:

These octal flip-flops are designed for low-voltage (3.3V)

V

applications, but with the capability to provide a TTL

CC

interface to a 5V environment. The LVT574 and

LVTH574 are fabricated with an advanced BiCMOS

technology to achieve high speed operation similar to 5V

ABT while maintaining a low power dissipation.

– Human-body model > 2000V

– Machine model > 200V

– Charged-device model > 1000V

Ordering Information

Package

Order Number Number

Package Description

74LVT574WM

74LVT574SJ

M20B

M20D

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVT574MSA

74LVT574MTC

MSA20

MTC20

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74LVTH574WM

74LVTH574SJ

M20B

M20D

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVTH574MSA

74LVTH574MTC

MSA20

MTC20

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Description

Pin Names

Description

D –D

Data Inputs

0

7

CP

OE

Clock Pulse Input

3-STATE Output Enable Input

3-STATE Outputs

O –O

0

7

Functional Description

Truth Table

The LVT574 and LVTH574 consist of eight edge-

triggered flip-flops with individual D-type inputs and

3-STATE true outputs. The buffered clock and buffered

Output Enable are common to all flip-flops. The eight

flip-flops will store the state of their individual D-type

inputs that meet the setup and hold time requirements

on the LOW-to-HIGH Clock (CP) transition. With the Out-

put Enable (OE) LOW, the contents of the eight flip-flops

are available at the outputs. When the OE is HIGH, the

outputs go to the high impedance state. Operation of the

OE input does not affect the state of the flip-flops.

Inputs

Outputs

D

CP

OE

L

O

n

H

L

X

L

O

o

X

H

Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

= LOW-to-HIGH Transition

O = Previous O before HIGH to LOW of CP

o

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

2

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Rating

V

Supply Voltage

–0.5V to +4.6V

CC

V

DC Input Voltage

DC Output Voltage

Output in 3-STATE

–0.5V to +7.0V

I

V

O

–0.5V to +7.0V

–50mA

(1)

Output in HIGH or LOW State

I

DC Input Diode Current, V < GND

I

IK

I

DC Output Diode Current, V < GND

–50mA

OK

O

I

DC Output Current, V > V

O

CC

Output at HIGH State

Output at LOW State

64mA

128mA

I

DC Supply Current per Supply Pin

DC Ground Current per Ground Pin

Storage Temperature

64mA

CC

I

128mA

GND

T

–65°C to +150°C

STG

Note:

1. I Absolute Maximum Rating must be observed.

O

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min

2.7

0

Max

3.6

5.5

–32

64

Units

V

Supply Voltage

Input Voltage

CC

V

I

HIGH-Level Output Current

LOW-Level Output Current

Free-Air Operating Temperature

mA

°C

OH

I

OL

T

–40

0

85

A

∆t / ∆V

Input Edge Rate, V = 0.8V–2.0V, V = 3.0V

10

ns/V

IN

CC

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

4

DC Electrical Characteristics

T

_A= –40°C to +85°C

Symbol

Parameter

Input Clamp Diode Voltage

Input HIGH Voltage

V_CC(V)

2.7

Conditions

Min.

Typ.⁽²⁾Max. Units

V

I = –18mA

–1.2

0.8

V

IK

IH

I

2.7–3.6

2.7

V

≤ 0.1V or

2.0

O

≥ V – 0.1V

CC

V

Input LOW Voltage

IL

V

Output HIGH Voltage

I

= –100µA

= –8mA

= –32mA

= 100µA

= 24mA

= 16mA

= 32mA

= 64mA

V

– 0.2

CC

OH

OL

2.4

2.0

3.0

V

Output LOW Voltage

2.7

0.2

0.5

V

OL

3.0

0.4

0.5

0.55

(3)

I

Bushold Input Minimum

Drive

3.0

V = 0.8V

75

–75

500

–500

µA

I(HOLD)

I

V = 2.0V

I

(3)

(4)

I

Bushold Input Over-Drive

Current to Change State

I(OD)

(5)

I

Input Current

Control Pins

Data Pins

3.6

V = 5.5V

10

1

I

V = 0V or V

I

CC

V = 0V

–5

1

I

V = V

I

CC

I

Power Off Leakage Current

0

0V ≤ V or V ≤ 5.5V

100

µA

OFF

I

O

I

Power up/down 3-STATE

Output Current

0–1.5

V = 0.5V to 3.0V,

O

PU/PD

V = GND or V

I

CC

I

3-STATE Output Leakage

Current

3.6

V

= 0.5V

–5

5

µA

OZL

O

I

3-STATE Output Leakage

Current

= 3.0V

OZH

O

I

+

3-STATE Output Leakage

Current

< V ≤ 5.5V

10

OZH

CC

O

I

Power Supply Current

3.6

Outputs HIGH

Outputs LOW

0.19

5

mA

CCH

I

CCL

I

Outputs Disabled

0.19

CCZ

I

+

V

≤ V ≤ 5.5V,

CC O

CCZ

Outputs Disabled

One Input at V – 0.6V,

∆I

Increase in Power Supply

Current

3.6

0.2

mA

CC

(6)

Other Inputs at V or

CC

GND

Notes:

2. All typical values are at V = 3.3V, T = 25°C.

CC

A

3. Applies to bushold versions only (74LVTH574).

4. An external driver must source at least the specified current to switch from LOW-to-HIGH.

5. An external driver must sink at least the specified current to switch from HIGH-to-LOW.

6. This is the increase in supply current for each input that is at the specified voltage level rather than V or GND.

CC

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

5

(7)

Dynamic Switching Characteristics

Conditions

T = 25°C

A

Symbol

Parameter

V

(V) C = 50pF, R = 500Ω

Min. Typ. Max. Units

CC

L

(8)

V

Quiet Output Maximum

3.3

0.8

V

OLP

Dynamic V

OL

V

Quiet Output Minimum

Dynamic V

3.3

–0.8

V

OLV

OL

Notes:

7. Characterized in SOIC package. Guaranteed parameter, but not tested.

8. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.

AC Electrical Characteristics

T = –40°C to +85°C

A

C = 50pF, R = 500Ω

L

V

= 3.3V 0.3V

V

= 2.7V

CC

(9)

Symbol

Parameter

Maximum Clock Frequency

Propagation Delay, CP to O

Min.

150

1.8

1.5

2.0

0.3

3.3

Typ.

Max.

Min.

150

1.8

1.5

2.0

2.4

0.0

3.3

Max.

Units

MHz

ns

f

MAX

t

4.6

4.5

5.2

4.8

4.4

4.8

5.3

6.1

5.9

4.4

5.1

PHL

n

t

PLH

t

Output Enable Time

Output Disable Time

ns

PZL

PZH

t

PLZ

PHZ

t

Setup Time

Hold Time

Pulse Width

ns

S

H

t

W

(10)

t

, t

Output to Output Skew

1.0

OSHL OSLH

Notes:

9. All typical values are at V = 3.3V, T = 25°C.

CC

A

10. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same direction,

either HIGH-to-LOW (t

) or LOW-to-HIGH (t

).

OSHL

OSLH

(11)

Capacitance

Symbol

Parameter

Conditions

Typical

Units

pF

C

Input Capacitance

Output Capacitance

V

= Open, V = 0V or V

4

6

IN

CC

I

CC

C

= 3.0V, V = 0V or V

pF

OUT

CC

O

CC

Note:

11. Capacitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

6

Physical Dimensions

13.00

12.60

A

11.43

20

11

B

9.50

10.65 7.60

10.00 7.40

2.25

1

PIN ONE

INDICATOR

10

0.65

0.51

0.35

1.27

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

2.65 MAX

0.33

0.20

C

0.10

C

0.30

0.10

SEATING PLANE

0.75

0.25

X 45°

NOTES: UNLESS OTHERWISE SPECIFIED

(R0.10)

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

GAGE PLANE

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

0.25

8°

0°

D) CONFORMS TO ASME Y14.5M-1994

1.27

0.40

SEATING PLANE

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

F) DRAWING FILENAME: MKT-M20BREV3

(1.40)

DETAIL A

SCALE: 2:1

Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

7

Physical Dimensions (Continued)

Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

8

Physical Dimensions (Continued)

Figure 3. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

9

Physical Dimensions (Continued)

Figure 4. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

10

TRADEMARKS

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global

subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

ACEx^®

PDP-SPM™

SupreMOS™

FPS™

Power220^®

SyncFET™

Build it Now™

CorePLUS™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK^®

EZSWITCH™ *

™

FRFET^®

POWEREDGE^®

Power-SPM™

PowerTrench^®

Programmable Active Droop™

QFET^®

®

Global Power Resource^SM

Green FPS™

Green FPS™e-Series™

GTO™

i-Lo™

IntelliMAX™

ISOPLANAR™

MegaBuck™

MICROCOUPLER™

MicroFET™

The Power Franchise^®

TinyBoost™

TinyBuck™

TinyLogic^®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

µSerDes™

UHC^®

QS™

QT Optoelectronics™

Quiet Series™

RapidConfigure™

SMART START™

SPM^®

STEALTH™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

®

Fairchild^®

Fairchild Semiconductor^®

FACT Quiet Series™

FACT^®

MicroPak™

MillerDrive™

Motion-SPM™

OPTOLOGIC^®

FAST^®

Ultra FRFET™

UniFET™

VCX™

OPTOPLANAR^®

FastvCore™

®

FlashWriter^{® *}

* EZSWITCH™ and FlashWriter^®are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Advance Information

Formative or In Design

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

Preliminary

First Production

Full Production

Not In Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

No Identification Needed

Obsolete

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I33

74LVT574, 74LVTH574 Rev. 1.6.0

www.fairchildsemi.com

11

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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1


型号：	74LVTH574MTC
厂家：	ONSEMI
描述：	带 3 态输出的低电压八路 D 型触发器驱动信息通信管理光电二极管逻辑集成电路触发器
文件：	总13页 (文件大小：461K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVTH574MTC [ONSEMI]

相关型号：

74LVTH574MTCX

74LVTH574MTCX

74LVTH574MTCX

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74LVTH574MTC_08

74LVTH574PW

74LVTH574PW,112

74LVTH574PW,118

74LVTH574SJ

74LVTH574SJX

74LVTH574SJ_08

74LVTH574WM