74HC245 [ONSEMI]
Octal 3−State Noninverting Bus Transceiver; 八路三态同相总线收发器
| 型号： | 74HC245 |
| 厂家： | 
ONSEMI |
| 描述： | Octal 3−State Noninverting Bus Transceiver |
| 文件： | 总8页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC245
Octal 3−State Noninverting
Bus Transceiver
High−Performance Silicon−Gate CMOS
The 74HC245 is identical in pinout to the LS245. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
The HC245 is a 3−state noninverting transceiver that is used for
2−way asynchronous communication between data buses. The device
has an active−low Output Enable pin, which is used to place the I/O
ports into high−impedance states. The Direction control determines
whether data flows from A to B or from B to A.
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MARKING
DIAGRAMS
20
1
HC
245
TSSOP−20
DT SUFFIX
CASE 948E
20
Features
ALYW G
1
G
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
HC245 = Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
(Note: Microdot may be in either location)
• Chip Complexity: 308 FETs or 77 Equivalent Gates
• This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
March, 2007 − Rev. 1
74HC245/D
74HC245
2
18
17
16
15
14
13
DIRECTION
20
V
CC
1
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
3
4
5
6
7
A1
A2
A3
19
18
17
OUTPUT ENABLE
B3
B4
B1
B2
A
DATA
PORT
B
DATA
PORT
B5
B6
B7
B8
A4
A5
16
15
14
B3
B4
B5
8
9
12
11
A6
A7
13
12
11
B6
B7
1
DIRECTION
OUTPUT ENABLE
A8
19
PIN 10 = GND
PIN 20 = V
GND
B8
10
CC
Figure 1. Pin Assignment
Figure 2. Logic Diagram
FUNCTION TABLE
Control Inputs
Output
Enable
Direction
Operation
L
L
H
X
Data Transmitted from Bus B to Bus A
Data Transmitted from Bus A to Bus B
Buses Isolated (High−Impedance State)
L
H
X = don’t care
ORDERING INFORMATION
†
Device
Package
Shipping
74HC245DTR2G
TSSOP−20*
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74HC245
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
DC Supply Voltage
*0.5 to )7.0
CC
V
DC Input Voltage
*0.5 to V )0.5
V
IN
CC
V
DC Output Voltage
(Note 2)
*0.5 to V )0.5
V
OUT
CC
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
$20
mA
mA
mA
mA
mA
_C
IK
I
$35
OK
I
$35
OUT
I
$75
CC
I
$75
GND
T
*65 to )150
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
260
_C
L
T
)150
_C
_C/W
mW
J
q
TSSOP
TSSOP
128
450
JA
P
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
D
MSL
Level 1
F
Flammability Rating
Oxygen Index: 30% to 35%
UL 94 V−0 @ 0.125 in
R
V
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
u2000
u200
V
ESD
I
Latchup Performance
Above V and Below GND at 85_C (Note 5)
$300
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow.
2. I absolute maximum rating must observed.
O
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
DC Supply Voltage (Referenced to GND)
6.0
CC
V , V
in out
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
V
V
CC
T
A
–55
+125
_C
ns
t , t
Input Rise and Fall Time
(Figure 3)
V
V
V
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
CC
CC
CC
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3
74HC245
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
–55 to
V
CC
V
25_C
Symbol
Parameter
Test Conditions
= V – 0.1 V
v 85_C v 125_C
Unit
V
Minimum High−Level Input Voltage
V
out
2.0
3.0
4.5
6.0
1.5
2.1
1.5
2.1
1.5
2.1
V
IH
out
CC
|I | v 20 mA
3.15
4.2
3.15
4.2
3.15
4.2
V
Maximum Low−Level Input Voltage
V
out
= 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
|I | v 20 mA
V
Minimum High−Level Output
Voltage
V
in
= V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
OH
|I | v 20 mA
out
V
in
= V |I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
IH out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
V
Maximum Low−Level Output
Voltage
V
out
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
in
IL
|I | v 20 mA
V
V
= V |I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
I
Maximum Input Leakage Current
= V or GND
6.0
6.0
±0.1
±0.5
±1.0
±5.0
±1.0
±10
mA
mA
in
in
CC
I
Maximum Three−State Leakage
Current
Output in High−Impedance State
V = V or V
in
OZ
IL
IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current (per Package)
V
out
= V or GND
6.0
4.0
40
40
mA
CC
in
CC
I
= 0 mA
6. Information on typical parametric values and high frequency or heavy load considerations can be found in the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
–55 to
V
CC
25_C
V
v 85_C v 125_C
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay,
A to B, B to A
2.0
3.0
4.5
6.0
75
55
15
13
95
70
19
16
110
80
ns
PLH
t
PHL
(Figures 1 and 3)
22
19
,
Maximum Propagation Delay,
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
165
130
33
ns
ns
ns
PLZ
t
Direction or Output Enable to A or B
(Figures 2 and 4)
PHZ
24
28
,
Maximum Propagation Delay,
Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
165
130
33
PZL
t
PZH
24
28
t
,
Maximum Output Transition Time,
Any Output
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
TLH
t
THL
(Figures 1 and 3)
C
Maximum Input Capacitance (Pin 1 or Pin 19)
−
−
10
15
10
15
10
15
pF
pF
in
C
out
Maximum Three−State I/O Capacitance
(I/O in High−Impedance State)
7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
40
C
Power Dissipation Capacitance (Per Transceiver Channel) (Note 8)
pF
PD
2
8. Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see the ON
D
PD CC
CC CC
Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
74HC245
V
CC
DIRECTION
50%
GND
t
t
f
r
V
CC
V
CC
INPUT
A OR B
90%
50%
OUTPUT
ENABLE
50%
GND
10%
GND
t
t
PLZ
PZL
t
t
PHL
PLH
HIGH
IMPEDANCE
90%
50%
10%
OUTPUT
B OR A
50%
A OR B
A OR B
10%
90%
V
OL
t
t
PHZ
PZH
t
t
V
TLH
THL
OH
50%
HIGH
IMPEDANCE
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST POINT
OUTPUT
TEST POINT
CONNECT TO V WHEN
CC
1 kW
OUTPUT
TESTING t
AND t
.
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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5
74HC245
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
18
17
16
15
B1
B2
B3
B4
A
B
DATA
PORT
DATA
PORT
14
13
12
11
B5
B6
B7
B8
1
DIRECTION
19
OUTPUT ENABLE
Figure 7. Expanded Logic Diagram
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6
74HC245
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
20X K REF
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
74HC245
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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74HC245/D
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