74AC259 [ONSEMI]
8−Bit Addressable Latch; 8位可寻址锁存器
| 型号： | 74AC259 |
| 厂家： | 
ONSEMI |
| 描述： | 8−Bit Addressable Latch |
| 文件： | 总11页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC259, MC74ACT259
8−Bit Addressable Latch
The MC74AC259/74ACT259 is a high−speed 8−bit addressable
latch designed for general purpose storage applications in digital
systems. It is a multifunctional device capable of storing single line
data in eight addressable latches, and also a 1−of−8 decoder and
demultiplexer with active HIGH outputs. The device also incorporates
an active LOW Common Clear for resetting all latches, as well as an
active LOW Enable. It is functionally identical to the ALS259 8−bit
addressable latch.
http://onsemi.com
PDIP−16
N SUFFIX
CASE 648
16
• Serial−to−Parallel Conversion
• Eight Bits of Storage with Output of Each Bit Available
• Random (Addressable) Data Entry
• Active High Demultiplexing or Decoding Capability
• Easily Expandable
1
SOIC−16
D SUFFIX
CASE 751B
16
16
1
1
• Common Clear
• Pb−Free Packages are Available
SOEIAJ−16
M, MEL SUFFIX
CASE 966
V
CC
MR
E
D
Q
7
Q
Q
Q
4
6
5
16
15
14
13
12
11
10
9
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
1
2
3
4
5
6
7
8
ORDERING INFORMATION
A
0
A
1
A
2
Q
0
Q
1
Q
2
Q
3
GND
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
E
D
A
0
A
1
A
2
MR Q
Q Q Q Q Q Q Q
1 2 3 4 5 6 7
0
Figure 2. Logic Symbol
MODE SELECT TABLE
E
MR
Mode
L
H
L
H
H
L
Addressable Latch
Memory
Active HIGH 8−Channel Demultiplexer
Clear
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
November, 2005 − Rev. 6
MC74AC259/D
MC74AC259, MC74ACT259
MODE SELECT−FUNCTION TABLE
Inputs
Outputs
Operating
Mode
MR
L
E
H
D
X
A
A
A
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
0
1
2
3
4
5
6
Master Reset
X
X
X
L
L
L
L
L
L
L
L
L
L
L
•
•
•
L
L
L
•
•
•
d
d
d
•
•
•
L
H
L
•
•
•
L
L
H
•
•
•
L
L
L
•
•
•
Q = d
L
L
L
L
L
L
•
•
•
L
L
L
•
•
•
L
L
L
•
•
•
L
L
L
•
•
•
L
L
L
•
•
•
L
L
•
•
•
Q = d
Demultiplex
(Active HIGH
Decoder when
D = H)
L
•
•
•
L
Q = d
•
•
•
L
L
L
d
H
H
H
L
L
L
L
L
Q = d
Store
(Do Nothing)
H
H
X
X
X
X
q
q
q
q
q
q
q
q
0
1
1
2
3
4
5
6
7
H
H
H
•
•
•
L
L
L
•
•
•
d
d
d
•
•
•
L
H
L
•
•
•
L
L
H
•
•
•
L
L
L
•
•
•
Q = d
q
q
q
q
3
q
3
q
3
q
4
q
4
q
4
q
5
q
5
q
5
q
6
q
6
q
6
q
7
q
7
q
7
2
q
q
Q = d
0
2
q
1
Q = d
0
Addressable
Latch
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
H
L
d
H
H
H
q
0
q
1
q
2
q
3
q
4
q
5
q
6
Q = d
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW−to−HIGH Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed
or cleared.
FUNCTIONAL DESCRIPTION
Inthe one−of−eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other outputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the MC74AC/ACT259 as an addressable
latch, changing more than one bit of the address could
impose a transient wrong address. Therefore, this should
only be done while in the memory mode. The Mode Select
Function Table summarizes the operations of the
MC74AC/ACT259.
The MC74AC259/74ACT259 has four modes of
operation as shown in the Mode Selection Table. In the
addressable latch mode, data on the Data line (D) is written
into the addressed latch. The addressed latch will follow the
data input with all non−addressed latches remaining in their
previous states in the memory mode. All latches remain in
their previous state and are unaffected by the Data or
Address inputs.
http://onsemi.com
2
MC74AC259, MC74ACT259
Q
7
Q
6
Q
5
MR
Q
4
Q
3
Q
2
Q
1
A
A
2
1
A
0
D
E
Q
0
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
http://onsemi.com
3
MC74AC259, MC74ACT259
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
V
V
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
CC
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to V +0.5
V
IN
CC
−0.5 to V +0.5
V
OUT
CC
I
I
I
20
50
mA
mA
mA
°C
IN
DC Output Sink/Source Current, per Pin
OUT
CC
DC V or GND Current per Output Pin
50
CC
T
stg
Storage Temperature
−65 to +150
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
−
Max
6.0
Unit
′AC
V
V
Supply Voltage
V
V
CC
′ACT
5.5
, V
OUT
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
IN
V
CC
V
CC
V
CC
V
CC
V
CC
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
−
−
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
−
−
−
−
−
ns/V
t , t
r
f
−
−
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
t , t
ns/V
r
f
−
T
J
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
−
140
85
°C
°C
T
A
−40
−
25
−
I
I
−24
24
mA
mA
OH
OL
Output Current − Low
−
−
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
IN
http://onsemi.com
4
MC74AC259, MC74ACT259
DC CHARACTERISTICS
74AC
74AC
T =−40°C to +85°C
A
V
(V)
CC
T
A
= +25°C
Symbol
Parameter
Unit
Conditions
Typ
Guaranteed Limits
V
V
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V − 0.1 V
CC
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= −50 μA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IH
IN
IL
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
−12 mA
−24 mA
−24 mA
V
V
I
OH
V
OL
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 μA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
V
I
OL
I
IN
Maximum Input
Leakage Current
5.5
−
0.1
1.0
μA
V = V , GND
I
CC
I
I
I
5.5
5.5
−
−
−
−
75
mA
mA
V
V
= 1.65 V Max
= 3.85 V Min
†Minimum Dynamic
Output Current
OLD
OHD
CC
OLD
−75
OHD
Maximum Quiescent
Supply Current
5.5
−
8.0
80
μA
V
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
IN
and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
CC
CC
http://onsemi.com
5
MC74AC259, MC74ACT259
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
T
= −40°C
A
T
= +25°C
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Min
Typ
Max
Min
Max
Propagation Delay
D to Q
3.3
5.0
2.0
2.0
9.0
6.5
14.5
10.0
1.5
1.5
17.0
11.5
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
3−5
3−5
3−6
3−6
3−6
3−6
3−7
PLH
n
n
Propagation Delay
D to Q
3.3
5.0
2.0
2.0
9.0
6.0
13.5
9.5
1.5
1.5
16.0
11.0
PHL
PLH
PHL
PLH
PHL
PHL
n
n
Propagation Delay
E to Q
3.3
5.0
2.0
2.0
10.5
7.0
15.0
10.5
1.5
1.5
17.5
12.5
n
Propagation Delay
E to Q
3.3
5.0
2.0
2.0
8.0
7.5
12.5
9.0
1.5
1.5
15.0
11.0
n
Propagation Delay
Address to Q
3.3
5.0
2.0
2.0
12.0
8.0
19.0
13.0
1.5
1.5
22.5
15.5
n
Propagation Delay
Address to Q
3.3
5.0
2.0
2.0
10.0
7.0
16.0
11.0
1.5
1.5
19.0
13.0
n
Propagation Delay
MR to Q
3.3
5.0
2.0
2.0
8.0
6.0
12.0
9.0
1.5
1.5
13.5
10.0
*Voltage Range 3.3 V is 3.3 V 0.3 V.
*Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74AC
74AC
T
= +25°C
T
A
= −40°C to +85°C
C = 50 pF
L
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
Unit
C = 50 pF
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
D to E
n
3.3
5.0
−
−
3.5
2.5
4.5
3.5
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
3−9
3−9
3−6
3−6
3−6
3−6
s
Hold Time, HIGH or LOW
D to E
n
3.3
5.0
−
−
2.5
2.0
2.5
2.0
h
s
Setup Time
Address to E
3.3
5.0
−
−
7.0
4.0
9.0
6.0
Hold Time
Address to E
3.3
5.0
−
−
2.0
2.0
2.0
2.0
h
w
w
Minimum Pulse
Width MR
3.3
5.0
−
−
6.0
5.5
6.5
6.0
Minimum Pulse
Width E
3.3
5.0
−
−
6.5
5.5
7.0
6.0
*Voltage Range 3.3 V is 3.3 V 0.3 V.
*Voltage Range 5.0 V is 5.0 V 0.5 V.
http://onsemi.com
6
MC74AC259, MC74ACT259
DC CHARACTERISTICS
74ACT
74ACT
T = −40°C to +85°C
A
V
(V)
CC
T
= +25°C
Symbol
Parameter
Unit
Conditions
A
Typ
Guaranteed Limits
V
V
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V − 0.1 V
CC
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= −50 μA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IH
IN
IL
4.5
5.5
−
−
3.86
4.86
3.76
4.76
V
V
−24 mA
−24 mA
I
I
OH
V
OL
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
= 50 μA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN
IL
IH
4.5
5.5
−
−
0.36
0.36
0.44
0.44
V
24 mA
24 mA
I
OL
I
IN
Maximum Input
Leakage Current
5.5
−
0.1
1.0
μA
V = V , GND
I CC
ΔI
Additional Max. I /Input
5.5
5.5
5.5
0.6
−
−
−
−
1.5
75
mA
mA
mA
V = V − 2.1 V
CCT
CC
I
CC
I
V
OLD
V
OHD
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
I
−
−75
= 3.85 V Min
OHD
CC
I
Maximum Quiescent
Supply Current
5.5
−
8.0
80
μA
V = V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
T
= +25°C
T
A
= −40°C to +85°C
C = 50 pF
L
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
Unit
C = 50 pF
L
Min
Typ
Max
Min
Max
Propagation Delay
D to Q
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.0
6.5
11.0
1.5
12.5
ns
ns
ns
ns
ns
ns
ns
3−5
3−5
3−6
3−6
3−6
3−6
3−7
PLH
n
n
Propagation Delay
D or Q
2.0
2.0
2.0
2.0
2.0
2.0
7.0
10.5
9.0
10.5
14.0
12.0
11.5
10.0
10.0
1.5
1.5
1.5
1.5
1.5
1.5
12.0
16.5
14.0
13.5
12.0
11.0
PHL
PLH
PHL
PLH
PHL
PHL
n
n
Propagation Delay
E to Q
n
Propagation Delay
E or Q
n
Propagation Delay
Address to Q
8.0
n
Propagation Delay
Address to Q
6.0
n
Propagation Delay
MR to Q
*Voltage Range 5.0 V is 5.0 V 0.5 V.
http://onsemi.com
7
MC74AC259, MC74ACT259
AC OPERATING REQUIREMENTS
74ACT
74ACT
T
= +25°C
T
A
= −40°C to +85°C
C = 50 pF
L
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
Unit
C = 50 pF
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
D to E
n
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
−
3.0
2.5
4.5
2.5
7.0
7.0
4.0
ns
ns
ns
ns
ns
ns
3−9
3−9
3−6
3−6
3−6
3−6
s
h
s
h
Hold Time, HIGH or LOW
D to E
n
−
−
−
−
−
2.5
6.5
2.5
7.5
7.5
Setup Time
Address to E
Hold Time
Address to E
Minimum Pulse
Width MR
w
w
Minimum Pulse
Width E
*Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol
Value
Typ
Parameter
Unit
Test Conditions
C
C
Input Capacitance
Power Dissipation Capacitance
4.5
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
50.0
PD
CC
http://onsemi.com
8
MC74AC259, MC74ACT259
MARKING DIAGRAMS
SO−16
DIP−16
EIAJ−16
MC74AC259N
AWLYYWWG
AC259G
AWLYWW
74AC259
ALYWG
ACT259G
AWLYWW
MC74ACT259N
AWLYYWWG
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
= Pb−Free Device
G
ORDERING INFORMATION
Part Number
†
Package
Shipping
MC74AC259N
PDIP−16
25 Units/Rail
25 Units/Rail
MC74AC259NG
PDIP−16
(Pb−Free)
MC74AC259D
SOIC−16
48 Units/Rail
48 Units/Rail
MC74AC259DG
SOIC−16
(Pb−Free)
MC74AC259DR2
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
MC74AC259DR2G
SOIC−16
(Pb−Free)
MC74AC259M
SOEIAJ−16
50 Units/Rail
50 Units/Rail
MC74AC259MG
SOEIAJ−16
(Pb−Free)
MC74AC259MEL
MC74AC259MELG
SOEIAJ−16
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−16
(Pb−Free)
MC74ACT259N
PDIP−16
25 Units/Rail
25 Units/Rail
MC74ACT259NG
PDIP−16
(Pb−Free)
MC74ACT259D
SOIC−16
48 Units/Rail
48 Units/Rail
MC74ACT259DG
SOIC−16
(Pb−Free)
MC74ACT259DR2
MC74ACT259DR2G
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
SOIC−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
9
MC74AC259, MC74ACT259
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
H
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
−B−
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
R X 45
K
_
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
C
G
J
1.27 BSC
0.050 BSC
−T−
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
7
0
_
_
_
_
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
A
0.25 (0.010)
T
B
http://onsemi.com
10
MC74AC259, MC74ACT259
PACKAGE DIMENSIONS
SOEIAJ−16
M SUFFIX
CASE966−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
16
9
E
Q
1
H
E
M
_
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
−−−
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
−−−
0.05
0.35
0.10
9.90
5.10
2.05
A
1
0.20 0.002
0.50 0.014
0.20 0.007
b
c
D
E
10.50 0.390
5.45 0.201
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
_
0.035
0.031
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC74AC259/D
相关型号：
©2020 ICPDF网 联系我们和版权申明