2N6344_06 [ONSEMI]

Triacs Silicon Bidirectional Thyristors; 双向晶闸管硅双向晶闸管
2N6344_06
型号: 2N6344_06
厂家: ONSEMI    ONSEMI
描述:

Triacs Silicon Bidirectional Thyristors
双向晶闸管硅双向晶闸管

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2N6344  
Triacs  
Preferred Device  
Silicon Bidirectional Thyristors  
Designed primarily for full-wave ac control applications, such as  
light dimmers, motor controls, heating controls and power supplies; or  
wherever full−wave silicon gate controlled solid−state devices are  
needed. Triac type thyristors switch from a blocking to a conducting  
state for either polarity of applied main terminal voltage with positive  
or negative gate triggering.  
http://onsemi.com  
TRIACS  
8 AMPERES RMS  
600 thru 800 VOLTS  
Features  
Blocking Voltage to 800 V  
All Diffused and Glass Passivated Junctions for Greater Parameter  
Uniformity and Stability  
MT2  
MT1  
Small, Rugged, Thermowatt Construction for Low Thermal  
Resistance, High Heat Dissipation and Durability  
Gate Triggering Guaranteed in all Four Quadrants  
For 400 Hz Operation, Consult Factory  
Pb−Free Package is Available*  
G
MARKING  
DIAGRAM  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
Unit  
4
Peak Repetitive Off−State Voltage (Note 1)  
V
V
V
DRM,  
RRM  
(T = −40 to +110°C, Sine Wave  
J
50 to 60 Hz, Gate Open)  
2N6344  
2N6349  
600  
800  
2N6344G  
AYWW  
TO−220AB  
CASE 221A  
STYLE 4  
†On−State RMS Current (T = +80°C) Full  
I
8.0  
4.0  
A
A
C
T(RMS)  
Cycle Sine Wave 50 to 60 Hz (T = +90°C)  
1
C
2
3
†Peak Non−Repetitive Surge Current (One  
I
100  
TSM  
Full Cycle, Sine Wave 60 Hz, T = +25°C)  
C
Preceded and followed by rated current  
Circuit Fusing Consideration (t = 8.3 ms)  
†Peak Gate Power  
A
Y
= Assembly Location  
= Year  
2
2
I t  
40  
20  
A s  
WW = Work Week  
G
P
W
W
A
GM  
(T = +80°C, Pulse Width = 2 ms)  
C
= Pb−Free Package  
†Average Gate Power  
(T = +80°C, t = 8.3 ms)  
C
P
0.5  
2.0  
10  
G(AV)  
PIN ASSIGNMENT  
Main Terminal 1  
Main Terminal 2  
Gate  
†Peak Gate Current  
(T = +80°C, Pulse Width = 2.0 ms)  
C
I
GM  
1
2
3
4
†Peak Gate Voltage  
(T = +80°C, Pulse Width = 2.0 ms)  
C
V
V
GM  
†Operating Junction Temperature Range  
Storage Temperature Range  
T
J
−40 to +125 °C  
−40 to +150 °C  
Main Terminal 2  
T
stg  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
†Indicates JEDEC Registered Data.  
ORDERING INFORMATION  
Device  
Package  
Shipping  
2N6344  
TO−220AB  
500 Units / Box  
500 Units / Box  
1. V  
and V  
for all types can be applied on a continuous basis. Blocking  
DRM  
RRM  
voltages shall not be tested with a constant current source such that the  
voltage ratings of the devices are exceeded.  
2N6344G  
TO−220AB  
(Pb−Free)  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Preferred devices are recommended choices for future use  
and best overall value.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
May, 2006 − Rev. 4  
2N6344/D  
 
2N6344  
THERMAL CHARACTERISTICS  
Characteristic  
†Thermal Resistance, Junction−to−Case  
Maximum Lead Temperature for Soldering Purposes 1/8from Case for 10 Sec  
Symbol  
Max  
2.2  
Unit  
°C/W  
°C  
R
q
JC  
L
T
260  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted; Electricals apply in both directions)  
C
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
†Peak Repetitive Blocking Current  
I
I
,
DRM  
(V = Rated V  
, V  
RRM  
; Gate Open)  
D
DRM  
RRM  
10  
mA  
T = 25°C  
J
J
2.0  
mA  
T = 100°C  
ON CHARACTERISTICS  
†Peak On−State Voltage  
V
TM  
1.3  
1.55  
V
(I = "11 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle p2%)  
TM  
Gate Trigger Current (Continuous dc) (V = 12 Vdc, R = 100 W)  
I
mA  
D
L
GT  
Quadrant I: MT2(+), G(+)  
Quadrant II: MT2(+), G(−)  
Quadrant III: MT2(−), G(−)  
Quadrant IV: MT2(−), G(+)  
Both  
2N6349 only  
Both  
12  
12  
20  
35  
50  
75  
50  
2N6349 only  
75  
†MT2(+), G(+); MT2(−), G(−) T = −40°C  
†MT2(+), G(−); MT2(−), G(+) T = −40°C  
100  
125  
C
C
Gate Trigger Voltage (Continuous dc) (V = 12 Vdc, R = 100 W)  
V
GT  
V
D
L
Quadrant I: MT2(+), G(+)  
Quadrant II: MT2(+), G(−)  
Quadrant III: MT2(−), G(−)  
Quadrant IV: MT2(−), G(+)  
Both  
2N6349 only  
Both  
0.9  
0.9  
1.1  
1.4  
2.0  
2.5  
2.0  
2.5  
2.5  
3.0  
2N6349 only  
†MT2(+), G(+); MT2(−), G(−) T = −40°C  
†MT2(+), G(−); MT2(−), G(+) T = −40°C  
C
C
Gate Non−Trigger Voltage (Continuous dc)  
V
GD  
V
(V = Rated V  
, R = 10 k W, T = 100°C)  
D
DRM  
L J  
†MT2(+), G(+); MT2(−), G(−); MT2(+), G(−); MT2(−), G(−)  
0.2  
†Holding Current (V = 12 Vdc, Gate Open)  
(Initiating Current = "200 mA)  
T
= 25°C  
I
H
6.0  
40  
75  
mA  
D
C
*T = −40°C  
C
†Turn-On Time  
t
gt  
1.5  
2.0  
ms  
(V = Rated V  
, I = 11 A, I = 120 mA, Rise Time = 0.1 ms, Pulse Width = 2 ms)  
DRM TM GT  
D
DYNAMIC CHARACTERISTICS  
Critical Rate of Rise of Commutation Voltage  
dv/dt(c)  
5.0  
V/ms  
(V = Rated V  
, I = 11 A, Commutating di/dt = 4.0 A/ms, Gate Unenergized, T = 80°C)  
D
DRM TM  
C
†Indicates JEDEC Registered Data.  
http://onsemi.com  
2
2N6344  
Voltage Current Characteristic of Triacs  
(Bidirectional Device)  
+ Current  
Quadrant 1  
MainTerminal 2 +  
Symbol  
Parameter  
V
TM  
V
Peak Repetitive Forward Off State Voltage  
Peak Forward Blocking Current  
DRM  
DRM  
on state  
I
I
H
I
at V  
RRM  
V
Peak Repetitive Reverse Off State Voltage  
Peak Reverse Blocking Current  
RRM  
RRM  
RRM  
I
V
Maximum On State Voltage  
Holding Current  
+ Voltage  
off state  
TM  
I
H
I
at V  
DRM  
DRM  
I
H
Quadrant 3  
MainTerminal 2 −  
V
TM  
Quadrant Definitions for a Triac  
MT2 POSITIVE  
(Positive Half Cycle)  
+
(+) MT2  
(+) MT2  
Quadrant II  
Quadrant I  
(−) I  
(+) I  
GT  
GT  
GATE  
GATE  
2N6349  
only  
Both  
MT1  
MT1  
REF  
REF  
I
+ I  
GT  
GT  
(−) MT2  
(−) MT2  
Quadrant III  
Quadrant IV  
(+) I  
(−) I  
GT  
GT  
GATE  
GATE  
2N6349  
only  
Both  
MT1  
REF  
MT1  
REF  
MT2 NEGATIVE  
(Negative Half Cycle)  
All polarities are referenced to MT1.  
With in−phase signals (using standard AC lines) quadrants I and III are used.  
http://onsemi.com  
3
2N6344  
100  
96  
10  
dc  
α = 180°  
α = 30°  
60°  
α
8.0  
120°  
α
90°  
90°  
α = CONDUCTION ANGLE  
120°  
6.0  
4.0  
2.0  
92  
60°  
T [ 100°C  
J
30°  
180°  
α
88  
α
84  
80  
α = CONDUCTION ANGLE  
dc  
0
0
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
7.0  
8.0  
0
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
7.0  
8.0  
I
, RMS ON-STATE CURRENT (AMP)  
I
, RMS ON-STATE CURRENT, (AMP)  
T(RMS)  
T(RMS)  
Figure 1. RMS Current Derating  
Figure 2. On−State Power Dissipation  
1.8  
1.6  
1.4  
1.2  
50  
OFF-STATE VOLTAGE = 12 V  
QUADRANT 4  
OFF-STATE VOLTAGE = 12 V  
30  
20  
1.0  
0.8  
1
2
10  
1
2
QUADRANT  
QUADRANTS  
3
4
0.6  
0.4  
7.0  
5.0  
3
−60 −40 −20  
0
20  
40  
60  
80  
100 120 140  
−60 −40 −20  
0
20  
40  
60  
80 100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 3. Typical Gate Trigger Voltage  
Figure 4. Typical Gate Trigger Current  
http://onsemi.com  
4
2N6344  
20  
100  
70  
GATE OPEN  
MAIN TERMINAL #1  
POSITIVE  
50  
10  
30  
20  
7.0  
5.0  
MAIN TERMINAL #2  
POSITIVE  
T = 100°C  
J
25°C  
3.0  
2.0  
10  
7.0  
5.0  
−60 −40 −20  
0
20  
40  
60  
80  
100 120 140  
T , JUNCTION TEMPERATURE (°C)  
J
Figure 6. Typical Holding Current  
3.0  
2.0  
100  
80  
1.0  
0.7  
0.5  
60  
40  
CYCLE  
0.3  
0.2  
T = 100°C  
J
f = 60 Hz  
20  
0
Surge is preceded and followed by rated current  
0.1  
0.4  
0.8 1.2  
1.6  
2.0  
2.4  
2.8  
3.2 3.6 4.0 4.4  
1.0  
2.0  
3.0  
5.0  
7.0  
10  
v
, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)  
NUMBER OF CYCLES  
TM  
Figure 7. Maximum Non−Repetitive  
Surge Current  
Figure 5. On−State Characteristics  
1.0  
0.5  
0.2  
0.1  
Z
= r(t) R  
q
q
JC  
JC(t)  
0.05  
0.02  
0.01  
0.1  
0.2  
0.5  
1.0  
2.0  
5.0  
20  
t,TIME (ms)  
50  
100  
200  
500  
1.0 k  
2.0 k  
5.0 k 10 k  
Figure 8. Typical Thermal Response  
http://onsemi.com  
5
2N6344  
PACKAGE DIMENSIONS  
TO−220AB  
CASE 221A−07  
ISSUE AA  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
SEATING  
PLANE  
−T−  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION Z DEFINES A ZONE WHERE ALL  
BODY AND LEAD IRREGULARITIES ARE  
ALLOWED.  
B
F
C
T
S
INCHES  
DIM MIN MAX  
MILLIMETERS  
MIN  
14.48  
9.66  
4.07  
0.64  
3.61  
2.42  
2.80  
0.36  
12.70  
1.15  
4.83  
2.54  
2.04  
1.15  
5.97  
0.00  
1.15  
−−−  
MAX  
15.75  
10.28  
4.82  
0.88  
3.73  
2.66  
3.93  
0.55  
14.27  
1.52  
5.33  
3.04  
2.79  
1.39  
6.47  
1.27  
−−−  
4
3
A
B
C
D
F
0.570  
0.380  
0.160  
0.025  
0.142  
0.095  
0.110  
0.014  
0.500  
0.045  
0.190  
0.100  
0.080  
0.045  
0.235  
0.000  
0.045  
−−−  
0.620  
0.405  
0.190  
0.035  
0.147  
0.105  
0.155  
0.022  
0.562  
0.060  
0.210  
0.120  
0.110  
0.055  
0.255  
0.050  
−−−  
Q
A
K
1
2
U
H
G
H
J
Z
K
L
N
Q
R
S
T
R
J
L
V
G
U
V
Z
D
N
0.080  
2.04  
STYLE 4:  
PIN 1. MAIN TERMINAL 1  
2. MAIN TERMINAL 2  
3. GATE  
4. MAIN TERMINAL 2  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
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2N6344/D  

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