MSM6997VAS [OKI]
PCM Codec, MU-Law, 1-Func, CMOS, CDIP16, 0.300 INCH, 2.54 MM PITCH, CERDIP-16;
| 型号： | MSM6997VAS |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | PCM Codec, MU-Law, 1-Func, CMOS, CDIP16, 0.300 INCH, 2.54 MM PITCH, CERDIP-16 PC CD 电信 电信集成电路 |
| 文件： | 总21页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0010-28-81
This version: Aug. 1998
Previous version: Nov. 1996
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
Single Chip CODEC
GENERAL DESCRIPTION
TheMSM6996H/MSM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999areasingle-channel
CODECCMOSICscontainingfiltersfor A/DandD/Aconvertingofthevoicesignalrangingfrom
300 Hz to 3400 Hz.
FEATURES
• Compliance with ITU-T companding Law
MSM6996H/MSM6996V/MSM6998 :
MSM6997H/MSM6997V/MSM6999 :
A-law
m-law
• Capable of independent operation of transmission and reception
• Transmission clock in the range of 64 kHz to 2048 kHz
• Adjustable transmit gain
• 600 W drive for analog output
MSM6996H/MSM6996V/MSM6997H/MSM6997V single end drive
MSM6998/MSM6999 Push-pull drive
• Built-in analog loop back fanction
MSM6996V/MSM6997V
• Built-in reference voltage source
• Low Power Dissipation (60 mW to 70 mW Typ.)
• Package options :
16-pin plastic DIP (DIP16-P-300-2.54) (Product name : MSM6996HRS/MSM6997HRS)
(Product name : MSM6996VRS/MSM6997VRS)
(Product name : MSM6998RS/MSM6999RS)
16-pin cer DIP (DIP16-G-300-2.54-1)
(Product name : MSM6996HAS/MSM6997HAS)
(Product name : MSM6996VAS/MSM6997VAS)
(Product name : MSM6998AS/MSM6999AS)
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6996HGS-K/MSM6997HGS-K)
(Product name : MSM6996VGS-K/MSM6997VGS-K)
(Product name : MSM6998GS-K/MSM6999GS-K)
1/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
BLOCK DIAGRAM
MSM6996H/V
MSM6997H/V
SAMPLE
COMP
Transmit
PLL
+
AIN+
XSYNC
5th
3rd
Pre Filter
–
LPF
HPF
AIN–
GSX
Auto
Zero
VDD
VSS
AG
Transmit
Voltage
REF.
XCLOCK
PCMOUT
SAR
C Ladder
C Ladder
Controller
DG
T.PWD
R.PWD
*1
*2
TMC
PDN/BS
PCMIN
Receive
Controller
RCLOCK
–
AOUT
5th
+
Receive
PLL
RSYNC
LPF
*
*
1 BS : Only MSM6997H/V
2 Only MSM6996V, MSM6997V
MSM6998, MSM6999
SAMPLE
COMP
Transmit
PLL
XSYNC
+
AIN+
AIN–
GSX
5th
3rd
Pre Filter
–
LPF
HPF
Auto
Zero
VDD
VSS
AG
Transmit
XCLOCK
PCMOUT
Voltage
REF.
SAR
Controller
C Ladder
C Ladder
DG
T.PWD
R.PWD
*3
+
–
PDN/BS
PCMIN
AOUT–
AOUT+
Receive
R
Controller
RCLOCK
R
–
+
5th
Receive
PLL
RSYNC
LPF
*
3 BS : Only MSM6999
2/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AIN+
AIN–
GSX
VSS
AIN+
VSS
AIN+
VSS
PCMOUT AIN–
PCMOUT AIN–
PCMOUT
PDN/BS
DG
PDN/BS
DG
GSX
AG
PDN/BS
DG
GSX
AG
AG
AOUT
NC
XSYNC
RSYNC
XCLOCK
AOUT
TMC
VDD
XSYNC AOUT+
RSYNC AOUT–
XSYNC
RSYNC
XCLOCK
RCLOCK
VDD
XCLOCK
VDD
PCMIN
RCLOCK PCMIN
RCLOCK PCMIN
NC : No connect pin
16-Pin Plastic DIP
16-Pin Plastic DIP
16-Pin Plastic DIP
MSM6996VRS
MSM6997VRS
MSM6998RS
MSM6999RS
MSM6996HRS
MSM6997HRS
AIN+ 1
16 VSS
AIN+ 1
16 VSS
AIN+ 1
16 VSS
AIN– 2
GSX 3
AG 4
15 PCMOUT AIN–
2
15 PCMOUT AIN–
2
15 PCMOUT
14 PDN/BS
13 DG
14 PDN/BS GSX 3
13 DG AG 4
14 PDN/BS GSX 3
13 DG
AG 4
AOUT 5
NC 6
12 XSYNC AOUT 5
11 RSYNC TMC 6
12 XSYNC AOUT+
11 RSYNC AOUT–
10 XCLOCK VDD
5
6
7
8
12 XSYNC
11 RSYNC
10 XCLOCK
9 RCLOCK
VDD
7
8
10 XCLOCK VDD
RCLOCK PCMIN
7
8
PCMIN
9
9 RCLOCK PCMIN
NC : No connect pin
16-Pin Cer DIP
16-Pin Cer DIP
16-Pin Cer DIP
MSM6996VAS
MSM6997VAS
MSM6998AS
MSM6999AS
MSM6996HAS
MSM6997HAS
3/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
AIN+ 1
AIN– 2
GSX 3
AG 4
24 VSS
AIN+ 1
AIN– 2
GSX 3
AG 4
24 VSS
23 PCMOUT
22 PDN/BS
21 DG
23 PCMOUT
22 PDN/BS
21 DG
AG 5
20 NC
AG 5
20 NC
NC 6
19 NC
NC 6
19 NC
NC 7
18 NC
NC 7
18 NC
AOUT 8
NC 9
17 NC
AOUT 8
NC 9
17 NC
16 XSYNC
15 RSYNC
14 XCLOCK
13 RCLOCK
16 XSYNC
15 RSYNC
14 XCLOCK
13 RCLOCK
NC 10
TMC 10
VDD 11
PCMIN 12
VDD 11
PCMIN 12
NC : No connect pin
NC : No connect pin
24-Pin Plastic SOP
24-Pin Plastic SOP
MSM6996HGS-K
MSM6997HGS-K
MSM6996VGS-K
MSM6997VGS-K
AIN+ 1
24 VSS
AIN– 2
GSX 3
AG 4
23 PCMOUT
22 PDN/BS
21 DG
AG 5
20 NC
NC 6
19 NC
NC 7
18 NC
AOUT+ 8
NC 9
17 NC
16 XSYNC
15 RSYNC
14 XCLOCK
13 RCLOCK
AOUT– 10
VDD 11
PCMIN 12
NC : No connect pin
24-Pin Plastic SOP
MSM6998GS-K
MSM6999GS-K
4/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
These three pins are used for the transmit level adjustment.
AIN+isanon-invertinganaloginputpinwhichisconnectedtothenon-invertinginputofatransmit
amplifier.
AIN– is an inverting analog input pin which is connected to the inverting input of the transmit
amplifier.
GSX is a transmit amplifier output pin.
Adjustment can be done by following method.
C1
AIN+
Analog
+
RC
Active
Filter
Input
AIN–
GSX
R1
–
R2
R3
AG
R2
R3
Gain = 1 +
< 10
Notes: 1. R + R > 10 kW
2
3
2. When the DC off-set voltage of analog input is more than 20 mV, C1 and R1 should
provide for DC blocking.
Inthiscase,cut-offfrequencyofHPF,composedbyR andC ,shouldbelessthan30Hz.
1
1
3. R should be less than 20 kW
1
AG
AG is an analog ground.
AG is connected to the analog system ground.
AOUT
AOUT is the analog signal output pin for the MSM6996H/V and MSM6997H/V.
The output voltage range is 5 V . This output can drive the 600 W resistor.
PP
AOUT+, AOUT–
Analog output for the MSM6998 and MSM6999.
Theoutputsignalamplitudesare5V .TheAOUT–outputisinvertedtotheAOUT+output.These
PP
outputs can drive a 600 W impedance.
V
DD
V
DD
is the positive power supply.
The voltage supplied to this pin should be +5 V ±5%.
5/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
PCMIN
PCM signal input.
TheserialinputPCMsignalisconvertedfromdigitaltoanalog,synchronizingwiththesynchronous
signal RSYNC and clock signal RCLOCK.
The data rate of PCM signal ranges from 64 kbps to 2048 kbps.
ThePCMsignalisreadatthefallingedgeoftheclocksignalandlatchedintotheinternalregister
when finished to read eight bits data.
The top of the PCM data is specified by RSYNC pulse timing.
RCLOCK
Receive clock pulse input.
The frequency of this clock pulse should be identified with the data rate of PCM input signal at the
PCMIN pin.
This RCLOCK signal can be a continuous clock or a burst clock with nine bits or more.
In the case of a burst clock, input the following timing.
PCMIN
MSD
D2
D3
D4
D5
D6
D7
D8
1
2
3
4
5
6
7
8
9
RCLOCK
RSYNC
9 Clocks are required
XCLOCK
Transmit clock input.
The PCM output data rate from the PCMOUT pin is set by this clock frequency.
The applicable clock frequencies range from 64 kHz to 2048 kHz.
This XCLOCK signal can be a continuous clock or a burst clock with nine bits or more.
In the case of a burst clock, input the following timing.
PCMOUT
MSD
D2
D3
D4
D5
D6
D7
D8
1
2
3
4
5
6
7
8
9
XCLOCK
XSYNC
9 Clocks are required
6/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
The whole timing signal in the receive section are synchronize by this synchronizing signal.
This signal must be synchronize in phase with RCLOCK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics of receive section.
However,sameastheRCLOCKfrequency,thisdevicecanoperateintherangeof8kHz±2kHz,with
no guarantee of adherence to the electrical characteristics in this specification as a catalogue value.
Fixing this signal to logic "1" or "0", the receive circuit is driver in a power down state.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal.
All transmit timing signals are triggered to synchronize with this signal. This signal should be
synchronized in phase with XCLOCK pulse.
The frequency should be 8 kHz±50 ppm to guarantee the AC characteristics of transmit section.
Fixing this signal to logic "1" or "0", the transmit circuit is driver in a power down state.
DG
Ground of digital signal.
This pin is electrically separated from the AG pin in this device.
The DG pin must be connected to the AG pin on the printed circuit board to make common to the
AG pin.
PDN/BS
Power down signal input.
Whenthisinputisheldatlowlevelmorethan1ms, thedeviceisputintothepower-downmode.
PCMOUT
PCM signal output.
The PCM output signal is output in synchronization with the rising edge of XCLOCK pulse orderly
from MSD first. (The first bit of the PCM signal may output at the rising edge of XSYNC pulse,
accordingtothetimingofXSYNCandXCLOCKpulse.). DuringthePCMOUTsignaloutputexcept
the 8-bit pulses, the pin is in an open state, therefore, multiple connections by wired-OR are easily
possible at this pin.
The code companding law and output code format depend on ITU-T Recommendation G.711, and
for the MSM6996H, MSM6996V, and MSM6998 (A-law) the output PCM signals are obtained by
inverting the even bits of signals.
PCMIN/PCMOUT
Input/Output
MSM6996 (A-law)
MSM6998 (A-law)
MSM6997 (m-law)
MSM6999 (m-law)
Level
+Full scale
+0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
–0
–Full scale
7/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
TMC
Control signal input for mode selection.
This pin select the normal operating mode or analog loop-back mode.
TMC Input
> 2.0 V
Mode
Normal operation
Analog loop-back
< 0.8 V
TRANSMIT
BPF
+
–
AIN
AD
DA
PCMOUT
PCMIN
RECV
LPF
+
–
AOUT
AG
Signal flow in normal operating mode
Signal flow in analog loop-back mode
V
SS
Negative voltage power supply.
The range of power supply voltage is –5 V ±5%.
8/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VDD
Condition
Rating
0 to 7
Unit
V
—
—
—
—
—
Power Supply Voltage
VSS
–7 to 0
V
Analog Input Voltage
Digital Input Voltage
Storage Temperature
VAIN
VDD –0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
V
VDIN
V
TSTG
°C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0°C to 70°C)
Parameter
Symbol
VDD
VSS
Ta
Condition
Min.
4.75
–5.25
0
Typ.
5
Max.
5.25
–4.75
70
Unit
V
—
Power Supply Voltage
—
–5
25
—
—
—
—
8
V
Operating Temperature
Analog Input Voltage
Input High Voltage
Input Low Voltage
—
°C
VP-P
V
VAIN
VIH
VIL
fC
Connect AIN– and GSX
—
5
XSYNC, XCLOCK, PCMIN,
2.0
0
VDD
0.8
2048
—
RSYNC, RCLOCK, TMC, PDN/BS
V
Clock Frequency
XCLOCK, RCLOCK
64
kHz
kHz
%
Sync Pulse Frequency
Clock Duty Ratio
fS
XSYNC, RSYNC
—
DL
XCLOCK, RCLOCK
40
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
60
Digital Input Rise Time
Digital Input Fall Time
tIr
XSYNC, XCLOCK, PCMIN,
—
50
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
W
tIf
RSYNC, RCLOCK (Fig. 1)
—
50
tXS
tSX
tRS
tSR
tWX
tWR
tDS
tDH
tBS
tBH
XCLOCKÆXSYNC (Fig. 2)
50
—
Transmit Sync Timing
Receive Sync Timing
XSYNCÆXCLOCK (Fig. 2)
100
50
—
RCLOCKÆRSYNC (Fig. 2)
—
RSYNCÆRCLOCK (Fig. 2)
100
1/fc
1/fc
100
100
200
200
600
10
—
Transmit Sync Pulse Width
Receive Sync Pulse Width
PCMIN Set-up Time
PCMIN Hold Time
—
—
—
—
—
—
—
—
BS Set-up Time *
—
—
BS Hold Time *
—
—
AOUT, AOUT+, AOUT–
—
RAL
Analog Output Load
GSK
—
—
kW
pF
kW
pF
CAL
RDL
CDL
—
100
—
1
Digital Output Load
—
—
100
+200
+20
Allowable Analog Input
Offset Voltage
Transmit gain stage, Gain = 1
Transmit gain stage, Gain = 10
–200
–20
VIO
mV
* : The value for the MSM6997 and MSM6999
9/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = +5 V 5%, VSS = –5 V 5%, Ta = 0°C to 70ꢀC)
Parameter
Symbol
Condition
Min.
Typ.
Max.
12
Unit
IDD1
*
*
—
7.0
Power Supply Current
(Operating)
XCLOCK, RCLOCK
2048 kHz
14
mA
12
ISS1
—
6.5
14
Power Supply Current
(Stand-by)
IDD2
ISS2
VIH
VIL
—
—
—
—
3.0
1.5
—
—
mA
Input High Voltage
Input Low Voltage
2.2
—
—
V
V
—
0.8
2.0
0.5
0.4
10
IIH
—
< 0.5
< 0.2
0.1
< 5
0
Input Leakage Current
mA
IIL
—
—
Output Low Voltage
VOL
IOH
VOFF
CIN
RIN
—
V
Output Leakage Current
Analog Output Offset Voltage
Input Capacitance
—
mA
mV
pF
–150
—
+150
—
—
5
Analog Input Resistance
fIN < 3.4 kHz
—
1
—
MW
* : The upper is specified for the MSM6996/MSM6997 and the lower for the MSM6998/MSM6999
10/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
AC Characteristics
(VDD = +5 V 5%, VSS = –5 V 5%, Ta = 0°C to 70°C)
Condition
Parameter
Symbol Freq.
(Hz)
Level
Min.
Typ.
Max.
Unit
(dBm0)
LOSS T1
LOSS T2
LOSS T3
LOSS T4
LOSS T5
LOSS T6
LOSS R1
LOSS R2
LOSS R3
LOSS R4
LOSSR5
SD T1
SD T2
SD T3
SD T4
SD T5
SD R1
SD R2
SD R3
SD R4
SD R5
GT T1
GT T2
GT T3
GT T4
GT T5
GT R1
GT R2
GT R3
GT R4
GT R5
60
300
20
—
—
–0.15
—
+0.25
820
Reference
Transmit Frequency Response
0
0
dB
2020
3000
3400
300
–0.15
–0.15
0
—
+0.25
+0.25
0.8
—
—
–0.1
—
+0.2
820
Reference
Receive Frequency Response
2020
3000
3400
–0.1
–0.1
0
—
+0.2
+0.2
0.8
—
dB
dB
dB
dB
dB
—
—
3
36
—
1020
or
0
36
—
—
Transmit Signal to Noise
Ratio *1
–30
–40
–45
3
36
—
—
820
31
—
—
26
—
—
36
—
—
1020
or
0
36
—
—
Receive Signal to Noise
Ratio *1
–30
–40
–45
3
36
—
—
820
31
—
—
26
—
—
–0.2
—
+0.2
1020
or
–10
–40
–50
–55
3
Reference
Transmit Gain Tracking
Receive Gain Tracking
–0.2
–0.4
–0.8
–0.2
—
+0.2
+0.4
+0.8
+0.2
820
—
—
—
1020
or
–10
–40
–50
–55
Reference
—
–0.2
–0.4
–0.8
+0.2
+0.4
+0.8
820
—
—
Note: *1 The measurement is taken with P-message filter
11/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
AC Characteristics (Continued)
(VDD = +5 V 5%, VSS = –5 V 5%, Ta = 0°C to 70°C)
Condition
Level
Parameter
Idle Channel
Symbol Freq.
Min.
Typ.
Max.
Unit
(Hz)
—
(dBm0)
Transmit
Receive
Transmit
Receive
NIDL
NIDL
T
—
—
0
—
—
—
—
0
–75
–75
dBmOp
Noise *1
R
—
AV T 1020 or 820
AV R 1020 or 820
–0.5
–0.5
—
+0.5
+0.5
0.52
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
66
Absolute Gain *2
Absolute Delay Time
dB
0
0
tD
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ms
500
tGD T1
tGD T2
tGD T3
tGD T4
tGD T5
tGD R1
tGD R2
tGD R3
tGD R4
tGD R5
—
600
—
Transmit Group Delay Time *3
Receive Group Delay Time *3
1000
2600
2800
500
0
0
—
ms
ms
—
—
—
600
—
1000
2600
2800
—
—
—
T to R
Crosstalk Attenuation
R to T
CR T 1020 or 820
CR R 1020 or 820
—
—
0
dB
—
66
Out-of-Band Spurious
S
300 to 3400
fa = 470
fb = 320
4.6 kHz to
72 kHz
—
–30
dBmO
dBmO
Intermodulation Distortion
IMD 1
–4
—
30
—
—
–35
—
Discrimination
DIS
0
dB
dB
VDD Noise Rejection
Ratio
Transmit
PPSR T
—
—
—
—
50
50
50
50
—
30
30
—
—
Receive
Transmit
Receive
PPSR R 0 to 300
200
VSS Noise Rejection
Ratio
NPSR T
NPSR R
kHz
mVp-p
30
—
30
—
t
150
100
100
180
20
300
300
300
300
100
SD
R
DL = 2 kW
t
XD1
XD2
XD3
Digital Output Delay Time
Digital Output Fall Time
ns
ns
CDL = 100 pF
t
t
t
DO
Notes: *1 The measurement is taken with P-message filter
*2 MSM6996/MSM6998 0 dB = 1.231 Vrms
MSM6997/MSM6999 0 dB = 1.227 Vrms
*3 Reference : 1800 Hz
12/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
TIMING DIAGRAM
Wave Time Measurement Level
2.4 V
1.4 V
2.4 V
1.4 V
0.4 V
0.4 V
tWX
tWR
tIr
tIf
tDOf
Note: Timing between signal waves is judged at 1.4 V
Figure 1
Basic Timing
1
2
3
4
5
6
7
8
9
10
XCLOCK
tXS tSX
1/fC
XSYNC
tWX
tXD1
tXD3
tXD2
Transmitter
Section
PCMOUT
MSD
D2
D3
D4
D5
D6
D7
D8
tSD
Note 1): When tXS £ 1/2 ¥ fc, the Delay of the MSD bit is defined as tXD1
When tSX £ 1/2 ¥ fc, the Delay of the MSD bit is defined as tSD
.
.
1
2
3
4
5
6
7
8
9
10
RCLOCK
RSYNC
PCMIN
tRS tSR
tWR
Receiver
Section
tDS tDH
D3
MSD
D2
D4
D5
D6
D7
D8
Invalid Data
Note 2): Transmit synchronizing and clock pulse, and Receive synchronizing and clock pulse may be
asynchronous mutually.
Note 3): The threshold level is 1.4 V.
Figure 2
13/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
Timing for 7 bits Decode (Specified for MSM6997/6999)
RSYNC
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
PCMIN
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
RCLOCK
tBS tBH
Allowable Range
Disable
BS
Decoder
Operation
8 Bits Decode
7 Bits Decode
8 Bits Decode
Figure 3
Timing for Bit-steal Function Setting
RSYNC
125
more than 10ms
ms
PCMIN
RCLK
PDN/BS
more than 10ms
Notes: Follow these procedures when the Bit-steal function is used:
1. Set the RSYNC pin to OFF ("L") after the PDN/BS pin is set at "H" for 10ms or more.
2. Set the RSYNC to ON after a pulse is input at the PDN/BS pin.
3. The Bit-steal function starts to operate.
14/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
APPLICATION CIRCUIT
Basic Circuit
PCM
OUT
ANALOG
IN OUT
IN
XTAL
2.048 MHz
2 kW
+5 V
OUT
IN GSX AIN– AIN+ AOUT
10 M
PDN/BS
CLOCK SYNC
4049 4049
VSS VDD
X
R
X
R
DG AG
+
–
–
+
10 mF
10 mF
+5 V
16 6
Q4
14
Q4
M4520RS
R
E
C
R
E
C
15 10 9
8
7
2
1
Note 1
0 V –5 V +5 V
Power Down
1 : NOR
0 : Power Down
+5 V
DG
Notes: 1. Insert diode for preventing from Latch-Up at turn on Power.
Recommended Diode Specification.
• High Speed Switching
• Allowerable Power dissipation 250 mW to 300 mW
• Forward Voltage Drop < 1.3 V (at 100 mA)
2. AG and DG must be connected in the printed circuit board mounted this device, for
preventing from Latch-Up.
15/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
Example of Multi-Channel Connections (8ch)
+5 V
1 kW
Multiple
PCM
74161(1)
2
1
14
13
12
11
15
QA
QB
QC
QD
CO
CK
CLR
EP
512 kHz
+5 V
PCM
OUT
XC
XS
RC
RS
3
4
7
9
QA
QB
QC
QD
QE
QF
QG
QH
CK
No.1
10
9
ET
PCM
IN
5
LO
6
No.4
No.5
No.6
No.7
10
11
12
13
+5 V
74161(2)
CLR
9
1
2
1
7
10
9
14
13
QA
QB
A
B
CK
CLR
EP
2
No.2
+5 V
ET
74164
LO
No.3
No.8
Example of Multi-Channel Timing
74161(1) QC Output
74161(2) QB Output
QA
QB
74164
Output
QC
QH
7
8
No.
1
2
3
4
5
6
7
8
No.
1
2
3
4
5
6
7
8
Multiple PCM
512K CLK
MSD
LSD
16/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
Transmit and Receive Level Adjustment (MSM6996H/V, MSM6997H/V)
a. Transformer of turns ratio 1 : 1
1 : 1
1
2
3
AIN+
4WS
600 W
When R1 is open and the attenuator is set at
0 dB,
AIN–
GSX
600 W
4 WS maximum input level = +7.17 + L
R1 20 kW
600 W
T
AG
(dBm)
1 : 1
5
AOUT
4 WR maximum output level = +1.15 – L
(dBm)
L : Transformer loss
T
T
4WR
600 W
600 W Attenuator
b. Transformer of turns ratio 1 : 2
2 : 1
1
2
3
AIN+
When R1 is open and the attenuator is set at
0 dB,
4WS
600 W
AIN–
GSX
300 W
4 WS maximum input level = +10.18 + L
T
R1 20 kW
300 W
AG
(dBm)
2 : 1
5
4 WR maximum output level = +4.16 – L
T
AOUT
(dBm)
L : Transformer loss
T
4WR
600 W
300 W Attenuator
Transmit and Receive Level Adjustment (MSM6998, MSM6999)
1 : 1
1
2
3
AIN+
When R1 is open and the attenuator is set at
0 dB,
4WS
600 W
AIN–
GSX
600 W
AG
4 WS maximum input level = +7.17 + L
T
R1 20 kW
300 W
(dBm)
1 : 1
5
6
4 WR maximum output level = +7.17 – L
T
AOUT+
AOUT–
(dBm)
L : Transformer loss
T
4WR
600 W
300 W
600 W Attenuator
17/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
RECOMMENDATIONS FOR ACTUAL DESIGN
• Toassureproperelectricalcharacteristics,usebypasscapacitorswithexcellenthighfrequency
characteristics for the power supply and keep them as close as possible to the device pins.
• Connect the AG pin and the DG pin each other as close as possible.
Connected to the system ground with low impedance.
• Mount the device directly on the board when mounted on printed circuit board.
Do not use IC sockets.
If an IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source
such as power supply transformers surround the device.
• Keep the voltage on the V pin not lower than –0.3 V and the voltage on the V pin more than
DD
SS
+0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power
supply to avoid erroneous operation and the degradation of the characteristics of these devices.
18/21
¡ Semiconductor
PACKAGE DIMENSIONS
DIP16-P-300-2.54
MSM6996H/6996V/6997H/6997V/6998/6999
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.99 TYP.
19/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
(Unit : mm)
DIP16-G-300-2.54
9
16
8
1
7.62
20.00MAX
1.00±0.10
1.50±0.10
SEATING PLANE
2.54
0.80TYP
0.50±0.10
0.25
M
20/21
¡ Semiconductor
MSM6996H/6996V/6997H/6997V/6998/6999
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
21/21
相关型号：
MSM6997VGS-K
PCM Codec, MU-Law, 1-Func, CMOS, PDSO24, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24
OKI
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