MSM6255GS-K [OKI]
Dot Matrix LCD Controller, 128 X 256 Characters, CMOS, PQFP80, 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80;
| 型号： | MSM6255GS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Dot Matrix LCD Controller, 128 X 256 Characters, CMOS, PQFP80, 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 时钟 CD 外围集成电路 |
| 文件： | 总39页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2B0039-27-Y2
This version: Nov. 1997
Previous version: Mar. 1996
¡ Semiconductor
MSM6255
DOT MATRIX LCD CONTROLLER
GENERAL DESCRIPTION
The MSM6255 is a CMOS si-gate LSI designed to display characters and graphics on a DOT
MATRIX LCD panel.
FEATURES
• Display control capacity
16
– Graphic mode
: 512,000 dots (2 bytes)
Memory address MA to MA
: 65,536 characters (2 bytes)
0
15
16
– Character mode
Display address MA to MA
0
15
• Direct interface with 8085 or Z80 CPU
• Duty
: 1/2 to 1/256 selectable
• Attributes
– Screen clear
– Cursor ON/OFF/blink
• Scrolling and paging
• Display system
: AC inversion at each frame
• Data output (upper and lower display outputs)
4-bit parallel output, 2-bit parallel output, 1-bit serial output
• Crystal oscillation/external clock selectable
• Single +5V power supply
• Package options:
80-pin plastic QFP (QFP80-P-1420-0.80-K) (Product name: MSM6255GS-K)
80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM6255GS-BK)
1/39
¡ Semiconductor
MSM6255
BLOCK DIAGRAM
3-state
output
2/39
¡ Semiconductor
MSM6255
PIN CONFIGURATION (TOP VIEW)
64
63
62
61
1
MA5
MA4
MA3
MA2
MA1
MA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
RA3
RA2
RA1
RA0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
DB7
2
3
4
5
60
59
58
57
6
7
8
9
56
55
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
54
53
52
51 DB6
50
49
48
47
46
45
44
43
42
41
DB5
DB4
DB3
DB2
DB1
DB0
RES
WR
RD
A0
FRP
LIP
CS
80-Pin Plastic QFP
3/39
¡ Semiconductor
MSM6255
PIN DESCRIPTIONS
Pin
Symbol Type
Description
Address output for displaying RAM.
1 - 6
MA0
O
MA0 - MA15 are high impedance when ADF = "L".
71 - 80
7
MA15
A0
Memory address input pins
I
22
23
24
25
26
27
28
A15
Frame signal. Synchronization of display
Display data latch signal
FRP
LIP
O
O
O
O
O
Chip enable clock for LCD segment driver
Display data shift clock
CE
φ
CLP
FRMB
LD0
Alternate signal output pin
Display data parallel output for lower side
Supply voltage
O
O
O
31
32
33
LD3
V
DD
UD0
Display data parallel output, Upper display 4-bit output
(OD1, ED1, OD2 and ED2 outputs)
36
37
38
39
UD3
Character clock
CH
φ
O
O
I
Ready state signal. This signal is used while serial transmission stops.
Display enable signal. When this signal is "H", display is enabled.
Address floating input. When this signal is "L", MA0 - MA15, RA0 - RA3 are high impedance,
and when it is "H", A0 - A15 or a refresh address is output to MA0 - MA15.
Chip select. CS = "L"
Busy
DIEN
40
ADF
I
41
42
43
44
45
CS
RD
I
I
I
I
Read. Reading data is valid when RD = "L"
Write. Data is written when WR = "H"
WR
RES
DB0
Reset. Resets each counter.
8-bit data bus. Common pins for 3-state I/O.
I/O
I
52
53
DB7
RD0
ROM/RAM data input. Dot pattern data for the character generator
60
61
RD7
RA0
Raster address output.
*This output is not used in the graphic mode.
RA0 - RA3 are high impedance when ADF = "L".
O
I
64
65
RA3
XT
X’tal osc. When an external clock is used by setting DIV to "H", feeds it to XT.
66
67
XT
O
Ground pin.
VSS
—
"H" : EXT clock
"L" : Self oscillation
70
DIV
I
4/39
¡ Semiconductor
MSM6255
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
VDD
Condition
Ta = 25°C
Ta = 25°C
—
Rating
–0.3 to +6
–0.3 to VDD
–50 to +150
Unit
V
Input Voltage
VI
V
Storage Temperature
TSTG
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
VDD
Condition
VSS = 0V
Range
4.5 to 5.5
–20 to +85
0 to 11
Unit
V
Operating Temperature
Operating Frequency
Top
—
°C
fosc
VDD = 5V 10ꢀ
MHz
ELECTRICAL CHARACTERISTICS
Input Characteristics
(VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Applicable pin
Parameter
"H" Input Voltage
"L" Input Voltage
"H" Input Voltage
"L" Input Voltage
"H" Input Current
"L" Input Current
"H" Input Current
"L" Input Current
Symbol Min. Typ. Max. Unit
VIH
VIL
VIH
VIL
IIH
IIL
2.4
—
4.5
—
—
—
25
—
—
—
—
—
—
—
—
—
—
0.7
—
1.0
1
V
V
DB0 - DB7, CS, RD, WR, A0 - A15,
DIEN, ADF, RD0 - RD7
V
RES, DIV, XT
V
mA
mA
mA
mA
DB0 - DB7, CS, RD, WA, A0 - A15,
DIEN, ADF, RD0 - RD7, RES, DIV
–1
100
–1
IIH
IIL
TEST1, TEST2
Output Characteristics
(VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Parameter
Symbol
Condition Min. Typ. Max. Unit
Applicable pin
LD0 - LD3
UD0 - UD3
"H" Output Current
IOH
V
OH = 2.8V
–500
2.4
—
—
—
—
mA
MA0 - MA15
RA0 - RA3
CH
FRMB, BUSY, CLP
DB0 - DB
φ
, CE , LIP, FRP
φ
"L" Output Current
IOL
V
OL = 0.4V
mA
7
5/39
¡ Semiconductor
MSM6255
Supply Current
(VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Parameter
Static Current
Symbol
IDDS
V
DD
5
Condition
Min.
—
Typ.
—
Max.
50
Unit
mA
fosc = 0 Hz, no load
fosc = 10 MHz, no load
Dynamic Current
IDD
5
—
—
15
mA
Note: TEST 1 and TEST2 are open, and other inputs are either V or GND.
DD
Switching Characteristics
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
tr
tf
(VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Parameter
Rise Time
Symbol
Condition Min. Typ. Max. Unit
Applicable pin
tr
tf
CL = 60 pF
CL = 60 pF
—
—
—
—
100
100
ns
ns
All output pins
Fall Time
Operating Frequency
(VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Parameter
Symbol
Condition Min. Typ. Max. Unit
Notes
Crystal oscillator
External clock
Oscillating Frequency
Basic Clock Frequency
fosc
fs
DIV = "L"
DIV = "H"
—
—
—
—
11
MHz
MHz
5.5
6/39
¡ Semiconductor
MSM6255
TIMING DIAGRAM
LCDC Control Signal Timing Characteristics
(CL = 30pF, VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Parameter
Clock Cycle Time
Symbol
tCP
Min.
180
80
80
—
—
—
—
—
—
—
1
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Clock "H" Level Pulse Width
Clock "L" Level Pulse Width
Clock Rise/Fall Time
PWH
PWL
tcr/tcf
tCH
—
—
20
Character Clock Delay Time
Memory Address Clock Delay Time
Memory Address Disable Delay Time
Memory Address Enable Delay Time
CPU Address Delay Time
200
100
40
tMA
tAD1
tAD2
tAD3
tAD4
tRES
tAD5
40
100
100
—
Refresh Address Delay Time
Reset "H" Level Pulse Width
CPU Address Delay Time
—
100
tCP
PWL
XT
(External clock)
PWH
tcr
tcf
CHφ
tCH
Upper Side Address
Lower Side Address
MA0 - MA15
t
t
MA
MA
ADF
MA0 - MA15
RA0 - RA3
Floating
VALID
VALID
t
t
AD2
AD1
DIEN
MA0 - MA15
Refresh Address
CPU Address
Refresh Address
t
t
AD4
AD3
t
RES
RES
A
0 - A15
t
t
AD5
AD5
MA0 - MA15
7/39
¡ Semiconductor
MSM6255
Bus Timing Characteristics
(CL = 50pF, VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Parameter
Ao, CS Setup Time
RD, WR Pulse Width
Address Hold Time
Data Setup Time
Symbol
tCS
Min.
30
Typ.
—
Max.
—
Unit
ns
tCW
200
10
—
—
ns
tAH
—
—
ns
tDS
60
—
—
ns
Data Hold Time
tDH
20
—
—
ns
Output Disable Time
Access Time
tOH
0
—
40
ns
tACC
—
—
200
ns
tAH
A0, CS
tcs
tcw
WR, RD
tDS
tDH
DB0 - DB7
(WRITE)
VALID
DB0 - DB7
(READ)
VALID
tACC
tOH
8/39
¡ Semiconductor
MSM6255
LCDC Driver Interface Timing Characteristics
(CL = 30pF, VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Parameter
Data Delay Time
Symbol
tDA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
Max.
100
Unit
ns
1 Character Cycle Time
tCHφ
tR
730
—
—
ns
Latch Signal Delay Time
Latch Signal "H" Time
200
ns
tLIP
1.46
—
—
ms
ns
Chip Enable Clock Delay Time
Chip Enable Clock "H" Time
Ready Signal Delay Time
Ready Signal "H" Time
tCE
200
tCEφ
tB
730
—
—
ns
200
ns
tBUSY
tFRP
tFR
5.11
2tCHφ
—
—
ms
ns
Frame Signal Delay Time
Alternating Frame Signal Delay Time
2tCHφ +200
200
ns
CLP
UD0 - UD3
LD0 - LD3
tDA
tCHφ
CHφ
LIP
tLIP
t
t
CEφ
tCEφ
tCE
tCE
tBUSY
BUSY
tB
tB
LIP
FRP
tFRP
tFRP
FRMB
tFR
tFR
9/39
¡ Semiconductor
MSM6255
Timing for Fetching Pattern Data
(VDD = 5V 5ꢀ, Ta = –20 to +85°C)
Parameter
Upper Side Data Setup Time
Upper Side Data Hold Time
Lower Side Data Setup Time
Lower Side Data Hold Time
Symbol
tUDS
Min.
120
0
Typ.
—
Max.
—
Unit
ns
tUDH
—
—
ns
tLDS
120
0
—
—
ns
tLDH
—
—
ns
CHφ
q
w
Upper
side
Lower
side
Upper
side
Lower
side
MA0 - MA15
Upper
side data
of q
Lower
Upper
side data
of w
Lower
side data
of w
RD0 - RD7
side data
of q
tLDS
tUDH
tLDH
tUDS
10/39
¡ Semiconductor
MSM6255
FUNCTIONAL DESCRIPTION
LCDC Internal Registers
The internal registers include one instruction register (IR) and nine data registers. (See Table
1.)
Table 1 MSM6255 Internal Registers
Instruction
Data bit
register
3 2 1 0
X X X X
X X X X
L L L L
L L L H
CS A0
Register
Register name
Invalid
READ WRITE
7
6
5
4
3
2 1 0
H
L
L
L
X
H
L
–
IR
–
–
Instruction register
X X X X
X
MOR
PR
Mode control register
Character pitch register
X
L
X
Horizontal character number
register
X
L
L
L L H L
HNR
L
L
L
L
L
L
L
L
L L H H
L H L L
L H L H
L H H L
DVR
CPR
SLR
SUR
Duty number register
X
Cursor form register
Start address (lower) register
Start address (upper) register
Cursor address (lower)
register
L
L
L
L
L H H H
H L L L
CLR
CUR
Cursor address (upper)
register
Note: "L" is read if the data of the registers marked X is read.
–
Instruction register
The instruction register is a register for specifying the address of the data register which is
accessed.
This register is cleared when RES input is "L".
11/39
¡ Semiconductor
MSM6255
–
Mode control register
The mode control register is specified by writing "00 " in the instruction register.
H
Register
Instruction register
Mode control register
A0
H
D7
L
D6
D5
D4
D3
D2
D1
D0
L
L
L
L
L
L
L
L
L
MODE DATA
Output mode
1-bit serial
D6
D5
D4
D3
D2
L
D1
L
D0
2-bit parallel
H
X
L
L
Character display
Graphics
H
H
L
4-bit parallel
X
H/L
H/L
H/L
H/L
1-bit serial
L
2-bit parallel
H
X
L
H
H
H
4-bit parallel
X
H: Display ON
L: Display OFF
D5 D4
L
L
Cursor OFF
Cursor OFF
Cursor ON
Cursor blink
L
H
L
H
H
H
H: 16 frames
L: 32 frames
Half of blinking cycle
12/39
¡ Semiconductor
MSM6255
– Character pitch register
Register
Instruction register
A0
H
D7
D6
D5
D4
D3
L
D2
D1
L
D0
L
L
L
L
L
H
Character pitch register
L
(Vp – 1)
L
(Hp – 1)
Hp represents the number of bits to be displayed among one byte display data sent from RAM.
The value of Hp is the following five types.
H
p
D2
L
D1
H
L
D0
H
L
4
5
6
7
8
H
H
L
H
L
H
H
H
H
H
– Horizontal character number register
Register
Instruction register
Character number register
A0
H
D7
L
D6
D5
D4
D3
L
D2
D1
D0
L
L
L
L
H
L
L
L
(HN – 1)
Assuming that the total horizontal dot number of the display is n ,
H
n = H x H , where H = 2 to 128.
H
p
N
N
The maximum value of n = 8 x 128 = 128 bytes = 1,024 dots.
H
– Duty number register
Register
Instruction register
A0
H
D7
D6
D5
D4
D3
L
D2
D1
D0
L
L
L
L
L
H
H
Time division register
L
(N
X
– 1)
Nx = 2 to 256
– Cursor form register
Register
Instruction register
A0
H
D7
D6
D5
D4
D3
D2
D1
D0
L
L
L
L
L
H
L
L
Cursor position register
L
(Cpu – 1)
(Cpd – 1)
The cursor is displayed on the lines from C to C in the character display mode. The length
pu
pd
of the cursor in the horizontal direction is equal to the character pitch in the horizontal direction,
Hp. The cursor is not displayed in graphic mode. The relation between the cursor and V is as
p
follows.
13/39
¡ Semiconductor
MSM6255
Font configuration of H = 7 and V = 8
p
p
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
C
pu
= 8, C = 8
C
pu
= 7, C = 8
C = 2, C = 6
pu pd
pd
pd
Notes: (1) Setting of C , C > V is not available.
pu
pd
p
(2) The cursor signal and pattern data are displayed subject to EX-OR.
– Start address (lower) register
Register
Instruction register
A0
H
D7
D6
D5
D4
D3
D2
D1
D0
L
L
L
L
L
H
L
H
Display start address register (lower byte)
L
Start address (lower)
– Start address (upper) register
Register
A0
H
D7
D6
D5
D4
D3
D2
D1
D0
Instruction register
L
L
L
L
L
H
H
L
Display start address register (upper byte)
L
Start address (upper)
The display start address shows an address of the RAM which stores data displayed at the left
end and the most upper position. The start address is composed of upper and lower 8 bits (16
bits in total).
– Cursor address (lower) register
Register
Instruction register
A0
H
D7
D6
D5
D4
D3
D2
D1
D0
L
L
L
L
L
H
H
H
Cursor address register (lower byte)
L
Cursor address (lower)
– Cursor address (upper) register
Register
Instruction register
A0
H
D7
D6
D5
D4
D3
D2
D1
D0
L
L
L
L
H
L
L
L
Cursor address register (upper byte)
L
Cursor address (upper)
By this instruction, the value of the cursor address is written in the cursor address register. The
cursor is displayed at the position specified by the cursor address register.
14/39
¡ Semiconductor
MSM6255
HN
RD7
H
p
RD0
Cpu
Cpd
Fig. 1 Cursor Address (Upper) Register
Table 2 Legend
Symbol
Name
Meaning
Value
Pitch of characters in horizontal
direction
H
p
Horizontal pitch
Vertical pitch
4 - 8 dots
Pitch of characters in vertical
direction
V
p
1 - 16 dots
Number of characters per line or
HN
V
Number of characters in one line
2 - 128 characters
2 - 256
number of words per line
Display duty
Number of rows
A position where the cursor starts
display
C
pu
Cursor start position
Line 1 - 16
A position where the cursor stops
display
C
pd
Cursor end position
Line 1 - 16
15/39
¡ Semiconductor
MSM6255
– Built-in Bus Averter
The bus averter which switches the address buses A - A of the CPU with the memory
0
15
address buses of the refresh. The refresh memory addresses are output to MA - MA when
0
15
the DIEN pin is set at high level and A - A are output to MA - MA when the DIEN pin
0
15
0
15
is set at low level.
– External Clock Operation
Anexternal clockenablestheMSM6255tooperatewhen theDIV pinis setat highlevel. Input
the external clock to XT.(Leave XT open.)
When the DIV pin is set at low level, the IC enters the crystal oscillation mode.
– Address Output Floating
MA - MA and RA - RA become high impedance when the ADF pin is set at low level.
0
15
0
3
MA - MA and RA - RA become normal impedance when the ADF pin is set at high level.
0
15
0
3
– Power Down Function
The chip select function becomes enabled for the segment driver by connecting the CE pin
f
to the ECLK input of the MSM5279. The power down function is valid only in 4-bit parallel
output mode.
– Refresh Memory Address (MA - MA ) Operation
0
15
In the horizontal direction, MA is counted up at the falling edge of CH . Upper side is
xx
f
addressed while CH is set at low level and lower side is addressed while CH is set at high
f
f
level.
MA is counted up even if it exceeds the number of horizontal display characters, but this
xx
does not affect the display since no data is being transferred at the time.
The period in which the data transfer is suspended corresponds to eight characters. When the
period passes, one horizontal cycle is completed and the next cycle is commenced.
Memory address operation in the graphic mode is shown in Fig. 2 and that in the character
mode is shown in Fig. 3.
16/39
¡ Semiconductor
MSM6255
Address configuration of display RAM
MSB LSB
MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
H
N
Suspension of
data transfer
1 word
0000 0001
0050 0051
004E 004F
009E 009F
Upper
1EF0 1EF1
1F40 1F41
1F90 1F91
1F3E 1F3F
1F8E 1F8F
1FDE 1FDF
Lower
3E30 3E31
3E7E 3E7F
Fig. 2 Memory Address in Graphic Mode (640 x 200)
Note: "L" is output for RA - RA .
0
3
17/39
¡ Semiconductor
MSM6255
HN (Number of characters in horizontal display line)
1 character
Suspension of
data transfer
Raster
address
0000
0000
0001
0001
004E
004E
004F
004F
000
001
010
011
100
101
110
111
000
Line 1
0000
0050
0001
0051
004E
009E
004F
009F
Line 2
Upper
0050
0370
0051
0371
009E
03BE
009F
03BF
111
000
Line 12
111
000
0370
03C0
0371
03C1
03BE
040E
03BF
040F
Line 13
111
03C0
03C1
040E
040F
Lower
0730
0730
0731
0731
077E
077E
077F
077F
000
111
Line 24
Note : Start address is 0000, 80 characters x 24 lines and V
p
= 8
Fig. 3 Memory Address in Character Mode (80 characters x 24 lines)
18/39
¡ Semiconductor
MSM6255
– Output Mode
Three kinds of modes, 1-bit serial, 2-bit parallel and 4-bit parallel, are available as output
modes. Data flows of each mode are shown below.
Data shift
Segment
driver
UD0
Upper
LCD panel
Lower
Segment
driver
UD1
Data shift
Fig. 4 1-Bit Serial Data Transfer
UD1
UD0
Data shift
Upper
Lower
LCD panel
UD2
UD3
Data shift
Fig. 5 2-Bit Parallel Data Transfer
19/39
¡ Semiconductor
MSM6255
4
UD0 - UD3
CE
φ
Upper
Lower
LCD panel
LD0 - LD3
4
Fig. 6 4-bit Parallel Data Transfer
Time charts corresponding to data transfers shown in Fig. 4 - Fig. 6 are shown in Fig. 7 - Fig. 9.
fs, the dot clock, shown in Figs.7-9, is a signal inside the IC. For more information see "Relation
between Reference Clock (fs) and External Clock" on page 601.
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MSM6255
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– Relation Between Duty and Number of Lines
Number of lines is determined by V , number of lines in vertical direction(display duty).
r
Number of lines = V x 2
r
Note: In the character display mode, number of lines should not be odd number.
– Calculation of Crystal Oscillation Frequency (f
)
osc
Table 3 Calculation Formula of f
osc
DIV
Output mode
Calculation formula of fosc
FRP x (HN + 8) x Hp x Vr x 2
FRP x (HN + 8) x Vr x 4
Calculation exmaple (MHz)
q
w
q
w
9.856
2.464
4.928
1.232
L
FRP x (HN + 8) x Hp x Vr
FRP x (HN + 8) x Vr x 2
H
Note: (1) Table 3 shows a calculation example assuming that FRP = 70 Hz, H = 80, H = 8 and
N
p
V
r
= 100. However, the example of H = 4 to 7 in 4-bit parallel is not included.
p
(2) Output mode q : H = 4 to 7 in 1-bit serial, 2-bit parallel and 4-bit parallel
p
Output mode w : H = 8 in 4-bit parallel
p
– Calculation of Character Clock (CH ) Frequency
f
CH = FRP x (H + 8) x V
r
φ
N
Example: Assuming FRP = 70 Hz, H = 80 and Vr= 100, CH = 1.62 (ms)
N
f
– Calculation of Shift Clock (CLP) Frequency
Table 4 Calculation Formula of CLP
Output mode
1-bit serial
Calculation formula of CLP
Calculation exmaple (MHz)
RP x (HN + 8) x H
FRP x (HN + 8) x H
FRP x (HN + 8) x H
p
x Vr
4.928
2.464
1.232
2-bit parallel
4-bit parallel
p
x Vr x 1/2
x Vr x 1/4
p
Note: Table 4 shows a calculation example assuming that FRP = 70 Hz, H = 80, H = 8 and
N
p
V = 100.
r
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¡ Semiconductor
MSM6255
– Relation Between Reference Clock (f ) and External Clock
s
DIV
XT
fs
Q
T
XT
XT
fs
(DIV = 1)
f functions as a dot clock in LCDC and the dot counter inside the IC is counted up at the trailing
s
edge of f .
s
The dot counter operates as a N-ary counter on a basis of H and generates the character clocks
P
(CH ).
f
(Refer to the time charts Fig. 7 - 9 and Fig. 14.)
– Access to the Display RAM
In writing/reading the data to/from the display RAM, DIEN should be low level. By setting
DIEN signal at low level, the address from the CPU are output from MA0 - MA15, and this
enables the access to the display RAM.
There are three methods of accessing display RAM from the CPU.
(1) Direct access from CPU
Display RAM is accessed directly from the CPU, irrespective of the condition of MSM6255
(refresh cycle or not).
In this method, the RAM address changes to the CPU address when the display is on the
screen. So, frequent access to the RAM causes flickering on the screen.
(2) Access while BUSY signal is high
BUSY signal indicates the period when the data transfer stops, and BUSY signal is set high
when the data transfer stops. The period when BUSY signal is high corresponds to that of
seven characters’. If display RAM is accesed during this period (when BUSY is high), the
display on the screen does not flicker.
Note: This method is effective when the size of screen is small. In the case of big size
screen, 640 x 200 dots, 1character needs approx. 1.6ms. So, in this case, the period
when BUSY is at high level is 11.2ms, which is impossible to write or read a lot of
data.
(3) Synchronized access (only for operating the IC by external clock)
Refresh cycle and CPU cycle are alternately performed. So, there is not flickering on the
screen and there is no need to sense the BUSY signal.
When using this method, however, some external circuitry is necessary. The timing chart
of this method is described in the Figure 10 below.
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CH
φ
TC
TL
DIEN
CPU
LCDC
CPU
LCDC
CPU
LCDC
CPU
LCDC
fetching the
pattern data
display
RAM
OUT
N
M
N + 1
M + 1
tUDS
tRAM
tUDH
Fig. 10 Basic Timing of Synchronized Access to Display RAM
Legend
T
T
: Period when the address bus is occupied by CPU
: Period when the LCDC fetches the refreshed data
: Refresh address delay time + memory access time
: Upper side data set-up time
C
L
t
t
t
RAM
UDS
UDH
: Upper side data hold time
When DIEN is high, MA - MA output address to the upper side when CH is low and to the
0
15
f
lower side when CH is high.
f
To perform synchronized access method, the timing between DIEN and CH should be as
f
described in Figure 10.
WR
VDD
PR
CL
PR
CL
PR
CL
PR
CL
D
Q
D
Q
D
Q
D
Q
M-WR
M-RD
Q
Q
Q
Q
V-RAM
SELECT
DIEN
READY
DATA LATCH
Fig. 11 Wait Function Controlling Circuit
Display RAM must meet the following condition:
T > t + t
L
RAM
UDS
In writing data into the display RAM, LCDC should be synchronized so that the write pulse
occursduringtheperiodofT .InreadingthepatterndatafromtheCPU,thedataofdisplayRAM
C
should be latched first.
Figure 11 shows the controlling circuit.
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– DIEN
DIENhastobegeneratedwhenthedisplayRAMisaccessedbySynchronizedaccessmethod.
(1) When the LCD screen is not split into upper and lower ones
If, for example, an LCD panel with a total of 64 dots in vertical direction is displayed at
1/64 duty, either the upper side data or the lower side data becomes unnecessary, and
then the CHf signal can be used as a DIEN signal.
(2) When the LCD screen is split into upper and lower ones
If 4-bit parallel output mode is set and H =8, the timing diagram of the dot clock and the
P
character clock is as shown below.
XT
(dot clock)
CH
φ
tCH
DIEN signal is generated by XT and CH .
φ
DIEN signal generating circuit is shown below.
DIEN
CH
φ
D Q
XT(dot clock)
Q
When H π 8 in the 1-bit serial, 2-bit parallel and 4-bit parallel mode, the relation between
p
XT and CH should be referred to Figures 7 and 8.
φ
– Scroll◊Paging
Scroll◊paging is enabled by setting the display start address to the scroll address register.
(1) Memory address of vertical scroll◊paging
Figure2showsthememoryaddresswhenthestartaddressis0000.Whenthestartaddress
is set at 0050, the display will be vertically shifted by +1.
By setting the starting address one by one, the screen will scroll vertically.
paging will be performed by setting the start address as 3E80.
(2) Memory address of horizontal scroll
Whenthestartingaddressissetat0001inFigure2, thedisplayonthescreenwillbeshifted
by +1 byte horizontally. The data shown as 004F in Figure 2 corresponds to the memory
data in the 2nd line shown as 0050.
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MSM6255
APPLICATION CIRCUITS
Interface With CPU
MSM6255
WR
RD
8085
WR
RD
IO/M
Decoder
A1 - A7
CS
AD0 - AD7
ALE
DB0 - DB7
A0 - A15
OC
HLDA
A8 - A15
MSM6255
WR
RD
Z80
WR
RD
IORQ
Decoder
A1 - A7
CS
DB0 - DB7
A0 - A15
D0 - D7
A0 - A15
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¡ Semiconductor
MSM6255
MSM6255
WR
8086
RD
M/IO
CS
Decoder
A1 - A15
DT/R
DEN
AD0 - AD15
Trans-
ceiver
D0 - D15
D1 - D7
DB0 - DB7
A0 - A15
A
16 - A19
Latch A0 - A19
BHE
BHE
ALE
*Minimum mode
MSM6255
6800
φ
2
RD
VMA
WR
RD/WR
Decoder
A1 - A15
CS
D0 - D7
A0 - A15
DB0 - DB7
A0 - A15
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System Configuration
~
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~
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Ts
fs
Memory
address
N
N + 1
N + 2
STA
STA
STA
STA
STA
STA
STA
STA + 1
STA + 2
STA + 3
Start address
LIP
TLIP
CE
φ
TCEφ
BUSY
FRP
TBUSY
CH
φ
CH
Fig. 14 Timing Chart During Suspension of Shift Clock
CH = T x Hp
s
T
T
T
= 2CH
= CH
LIP
Condition : 4-bit parallel output mode
CEφ
H = 5
P
= 7CH
BUSY
Suspension of
shift clock
Line 1
Line 2
Memory
address
• • • • • • • •
• • • • • • • •
• • • • • • • •
• • • • • • • •
LIP
FRP
FRMB
X driver
Line N
Line 1
Line 2
Y
1
2
Y driver
Y
Y
N
Fig. 15 Timing Chart of LIP, FRP and FRMB
¡ Semiconductor
MSM6255
LIP
CLP
Counter
(Inside the IC)
0
1
2
19
0
CEf
Carry output
of segment driver
Valid
Fig.16 Timing Chart of CLP and CEf
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Figures 17-1, 17-2, and 18 show application circuits.
In these examples, the size of LCD module is 640 x 200 dots.
4-bit data transfer is applied and H = 8.
p
The synchronized access method is used as a method of access to the display VRAM.
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MSM6255
MSM5165
MSM5165
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¡ Semiconductor
MSM6255
~
→
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PACKAGE DIMENSIONS
QFP80-P-1420-0.80-K
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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¡ Semiconductor
MSM6255
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
5 mm or more
Solder plate thickness
Package weight (g)
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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相关型号：
MSM6255GS-V1K
Dot Matrix LCD Controller, 128 X 256 Characters, CMOS, PQFP80, 14 X 20 MM, PLASTIC, QFP-80
OKI
MSM6262-XXGS-BK
Dot Matrix LCD Driver, 48 X 80 Dots, CMOS, PQFP80, 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
OKI
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