MSM6222B-XXGS-L [OKI]
Dot Matrix LCD Driver, 16 X 40 Dots, CMOS, PQFP80, 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80;
| 型号： | MSM6222B-XXGS-L |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Dot Matrix LCD Driver, 16 X 40 Dots, CMOS, PQFP80, 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 驱动器 控制器 CD |
| 文件： | 总45页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2B0032-27-Y3
This version: Nov. 1997
Previous version: Mar. 1996
¡ Semiconductor
MSM6222B-xx
DOT MATRIX LCD CONTROLLER WITH 16-DOT COMMON DRIVER AND 40-DOT
SEGMENT DRIVER
GENERAL DESCRIPTION
The MSM6222B-xx is a dot matrix LCD controller which is fabricated in low power CMOS
silicon gate technology. Character display on the dot matrix character type LCD can be
controlled in combination with a 4-bit/8-bit microcontroller. This LSI consists of 16-dot
COMMON driver, 40-dot SEGMENT driver, display data RAM, character generator RAM,
character generator ROM and control circuit.
TheMSM6222B-xxistheequivalentofHitachi'sHD44780. Thereis, however, aslightdifference
between the two devices as described in the table on the last page.
The MSM6222B-xx has the character generator ROM that can be programmed by custom mask.
MSM6222B-01 is a standard version having 160 characters with lowercase (5 x 7 dots), and 32
characters with uppercase (5 x 10 dots) in this ROM.
FEATURES
• Easy interface with an 8-bit or 4-bit microcontroller.
• Dot matrix LCD controller/driver for lowercase (5 x 7 dots) or uppercase (5 x 10 dots).
• Automatic power ON reset.
• COMMON signal drivers (16) and SEGMENT signal drivers (40).
• Can control up to 80 characters when used in combination with MSM5259.
• Character generator ROM for 160 characters with lowercase (5 x 7 dots) and 32 characters with
uppercase (5 x 10 dots).
• Character patterns are programmable by character generator RAM. (Lowercase: 5 x 8 dots,
8 kinds, uppercase: 5 x 11 dots, 4 kinds).
• Oscillation circuit for external resistor or ceralock.
• 1/8 duty (1 line; 5 x 7 dots + cursor), 1/11 duty (1 line; 5 x 10 dots + cursor), or 1/16 duty (2
lines; 5 x 7 dots + cursor), selectable.
• Clear display even at 1/5 bias, 3.0V LCD driving voltage.
• Package options:
80-pin plastic QFP (QFP80-P-1420-0.80-L) (Product name: MSM6222B-xxGS-L)
80-pin plastic QFP (QFP80-P-1420-0.80-BL) (Product name: MSM6222B-xxGS-BL)
xx indicates code number.
1/45
¡ Semiconductor
MSM6222B-xx
BLOCK DIAGRAM
2/45
¡ Semiconductor
MSM6222B-xx
INPUT AND OUTPUT CONFIGURATION
VDD
VDD
VDD
P
N
P
N
Applicable to pin E.
Applicable to pins R/W and RS.
VDD
VDD
P
VDD
N
P
N
VDD
P
Applicable to pins DO, CP, L, and DF.
N
Applicable to pins DB0 - DB7.
3/45
¡ Semiconductor
MSM6222B-xx
PIN CONFIGURATION
SEG 23 80
25 OSC
2
1
2
3
4
5
L
79
SEG 24
26
27
28
29
30
31
32
33
34
35
36
37
38
V
V
V
V
V
SEG 25 78
SEG 26 77
SEG 27 76
SEG 28 75
SEG 29 74
SEG 30 73
SEG 31 72
SEG 32 71
SEG 33 70
SEG 34 69
SEG 35 68
SEG 36 67
SEG 37 66
SEG 38 65
CP
V
DD
DF
DO
RS
R/W
E
39 DB
40 DB
0
1
80-Pin Plastic QFP
Note:ThefigureforTypeLshowstheconfigurationviewedfromthereversesideofthepackage.
Pay attention to the difference in pin arrangement.
4/45
¡ Semiconductor
MSM6222B-xx
PIN DESCRIPTIONS
Symbol
Description
R/W
RS
E
Read/write selection input pin.
"H" : Read, and "L" : Write
Register selection input pin.
"H" : Data register, and "L" : Instruction register
Input pin for data input/output between CPU and MSM6222B-xx and for instruction
register activation.
DB0 - DB7
Input/output pins for data send/receive between CPU and MSM6222B-xx.
OSC1, OSC2
Clock oscillating pins required for internal operation upon receipt of the LCD drive signal
and CPU instruction.
COM1 - COM16
SEG1 - SEG40
DO
LCD COMMON signal output pins.
LCD SEGMENT signal output pins.
Output pin to be connected to MSM5259 to expand the number of characters to be
displayed.
CP
Clock output pin used when DO pin data output shifts inside of MSM5259.
Clock output pin for the serially transferred data to be latched to MSM5259.
The alternating current signal (Display Frequency) output pin.
Power supply pin.
L
DF
VDD
GND
Ground pin.
V1, V2, V3, V4, V5
Bias voltage input pins to drive the LCD.
5/45
¡ Semiconductor
MSM6222B-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
VDD
Condition
Rating
Unit
Applicable pin
VDD, GND
V1, V2, V3
V4, V5
Ta = 25°C
–0.3 to + 7.0
V
V1, V2, V3
V4, V5
VDD – 9.0 to
LCD Driving Voltage
Ta = 25°C
V
VDD + 0.3
R/W, RS, E,
DB0 - DB7
OSC1
Input Voltage
VI
Ta = 25°C
–0.3 to VDD + 0.3
V
Power Dissipation
PD
—
—
500
mW
°C
—
Storage Temperature
TSTG
–55 to + 150
—
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
Condition
—
Range
4.5 to 5.5
3.0 to 8.0
3.0 to 8.0
–20 to + 75
Unit
V
Applicable pin
VDD
VDD, GND
*2
*3
1/4 bias, VDD–V5
1/5 bias, VDD–V5
—
V
*1
LCD Driving Voltage
VLCD
VDD, V5
V
Operating Temperature
Top
°C
—
*1 Voltage between V
and V
5.
DD
*2 Voltages applicable to V , V , V and V are as follows.
1
2
3
4
V = V – 1/4 (V
– V )
1
DD
DD
5
V = V = V
– 1/2 (V
- V )
DD 5
2
3
DD
V = V – 3/4 (V
– V )
4
DD
DD
5
*3 Voltages applicable to V , V , V and V are as follows.
1
2
3
4
V = V – 1/5 (V
– V )
– V )
5
1
DD
DD
DD
DD
DD
5
V = V – 2/5 (V
2
DD
V = V – 3/5 (V
– V )
3
DD
5
V = V – 4/5 (V
– V )
5
4
DD
6/45
¡ Semiconductor
MSM6222B-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
Symbol
VIH1
VIL1
Condition
—
Min.
2.2
Typ.
Max. Unit Applicable pin
"H" Input Voltage
"L" Input Voltage
"H" Input Voltage
"L" Input Voltage
"H" Output Voltage
"L" Output Voltage
"H" Output Voltage
"L" Output Voltage
COM Voltage Drop
SEG Voltage Drop
—
—
—
—
—
—
—
—
—
—
—
—
VDD
0.6
VDD
1.0
—
V
V
R/W, RS, E,
DB0 - DB7
—
–0.3
VDD – 1.0
–0.3
2.4
VIH2
VIL2
—
V
OSC1
—
V
VOH1
VOL1
VOH2
VOL2
VC
IO = –0.205mA
IO = 1.2mA
IO = –40mA
IO = 40mA
IO = 50mA
IO = 50mA
VI = VSS
VI = VDD
VDD = 5.0V
VI = VSS
V
DB0 - DB7
—
0.4
—
V
0.9VDD
—
V
DO, CP, L,
DC, OSC2
0.1VDD
2.9
3.8
–1
V
*1
*1
—
V
COM1 - COM16
SEG1 - SEG40
VS
—
V
—
mA
mA
Input Leakage Current
IIL
E
—
1
–50
–125
–250
mA
R/W, RS
Input Current
IIL2
VI = VDD, excluding current
flowing over pullup resistor
and output drive MOS
DB0 - DB7
—
—
2
mA
*1 Applicable to the voltage drop (V ) occurring in pins V , V , V , and V to each COMMON
C
DD
1
4
5
pin (COM1 to COM16) when 50 mA flows in or out of all COM and SEG pins. Also applicable
to voltage drop (V ) occurring in pins V , V , V , and V to each SEG pin (SEG1 to SEG40).
S
DD
2
3
5
When output level is at V , V or V level, 50 mA flows out, while 50 mA flows in when the
DD
1
2
output level is at V , V or V level.
3
4
5
This occurs when +5V is input to V , V , and V , and when –3V is input to V , V , and V .
DD
1
2
3
4
5
7/45
¡ Semiconductor
MSM6222B-xx
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
Symbol
Condition
VDD = 5.0V,
Min.
Typ.
Max. Unit Applicable pin
resistor oscillation or
external clock input via
OSC1.
Supply Current (1)
IDD1
fOSC = 270kHz.
—
0.35
0.6
mA
VDD
E is in "L" level.
Other inputs are open.
Output pins are
all no load.
*2
VDD = 5.0V,
ceramic oscillation,
fOSC = 250kHz.
E is in "L" level.
Other pins are open.
Output pins are
all no load.
Supply Current (2)
IDD2
—
0.55
0.8
mA
V
VDD
*2
LCD Driving Bias
Input Voltage
VLCD1
VLCD2
1/5 bias
1/4 bias
3.0
3.0
—
—
8.0
8.0
VDD, V1, V2,
V3, V4, V5
VDD–V5 *7
*2 Applicable to the current that flows in pin V when power is input as follows:
DD
V
DD
= 5V, GND = 0V, V = 3.4V, V = 1.8V, V = 0.2V, V = –1.4V, and V = –3V.
1
2
3
4
5
AC Characteristics
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
Rf Clock Oscillation
Frequency
Symbol
Condition
Min.
Typ.
Max. Unit Applicable pin
OSC1
Rf = 91kW 2ꢀ
fOSC1
fIN
fDUTY
tr
175
250
250
50
350
350
55
kHz
kHz
ꢀ
OSC2
*3
Clock Input
OSC2 is open.
125
45
OSC1
Frequency
Input from OSC1
Input Clock Duty
OSC1
OSC1
OSC1
*4
*5
*5
Input Clock Rise
Time
—
—
0.2
0.2
ms
Input Clock Fall
Time
tf
—
—
ms
Rf = 510kW,
Ceramic Filter
Oscillation
C1 = C2 = 200 pF,
Rd = 30kW, and
Ceralock CSB250A.
OSC1
OSC2
fOSC
245
250
255
kHz
Frequency
*6
8/45
¡ Semiconductor
MSM6222B-xx
*3
OSC1
Rf=91kW 2ꢀ
Rf
OSC2
Minimum wiring is required between
OSC1 and Rf and between OSC2 and Rf.
*4 Applied to pulse input via OSC1.
tHW
tLW
0.5VDD
0.5VDD
0.5VDD
fIN
waveform
fDUTY = tHW/ (tHW + tLW) x 100(ꢀ)
*5 Applied to pulse input via OSC1.
V
DD–1.0V
–1.0VDD
1.0VDD
fIN
waveform
1.0V
tf
tr
C1
*6
OSC1
Ceralock
Rf
Rd
OSC2
C2
Ceralock : CSB250A (mfd. by MURATA MFG.Co.)
Rf : 510kW 5ꢀ
Rd : 30kW 5ꢀ
C1 : 200pF 10ꢀ
C2 : 200pF 10ꢀ
Please contact us when using this circuit.
*7 Input the voltage listed in the table below to V - V :
1
5
N (LCD lines)
1-line mode
2-line mode
Pin
VLCD
VLCD
5
V1
V2
V3
V4
V5
VDD
VDD
VDD
VDD
–
–
–
–
VDD
VDD
VDD
VDD
–
–
–
–
4
VLCD
2
2VLCD
5
VLCD
2
3VLCD
4
3VLCD
5
4VLCD
5
V
DD – VLCD
VDD – VLCD
V
is an LCD driving voltage. (For "N" (number of LCD lines),
LCD
refer to the initial set of the instruction code.)
9/45
¡ Semiconductor
MSM6222B-xx
Switching Characteristics
• Timing for input from the CPU
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
R/W and RS set-up time
E "H" pulse width
Symbol
Min.
140
280
10
Typ.
—
Max.
—
Unit
ns
tB
tW
tA
tr
—
—
ns
R/W and RS holding time
E rise time
—
—
ns
—
—
25
ns
E fall time
tf
—
—
25
ns
E "L" pulse width
tL
tC
tI
280
667
180
10
—
—
ns
E cycle time
—
—
ns
DB0 to DB7 input data set-up time
DB0 to DB7 input data holding time
—
—
ns
tH
—
—
ns
R/W
RS
VIL
VIL
VIH
VIL
VIH
VIL
tA
tB
tW
tL
VIH
VIH
VIL
VIL
tH
VIL
E
tr
tf
tI
VIH
VIH
VIL
Input data
DB0 - DB7
VIL
tC
10/45
¡ Semiconductor
MSM6222B-xx
• Timing for output to the CPU
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
R/W and RS set-up time
E "H" pulse width
Symbol
Min.
140
280
10
Typ.
—
Max.
—
Unit
ns
tB
tW
tA
tr
—
—
ns
R/W and RS holding time
E rise time
—
—
ns
—
—
25
ns
E fall time
tf
—
—
25
ns
E "L" pulse width
tL
tC
tD
tO
280
667
—
—
—
ns
E cycle time
—
—
ns
DB0 to DB7 data output delay time
DB0 to DB7 data output holding time
—
220
—
ns
20
—
ns
VIH
VIH
R/W
RS
VIH
VIL
VIH
VIL
tB
tW
tA
tL
VIH
VIH
VIL
VIL
tD
VIL
E
tr
tf
tD
VOH
VOH
VOL
Output data
tC
DB0-DB7
VOL
11/45
¡ Semiconductor
MSM6222B-xx
• Timing for output to MSM5259
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
CP "H" pulse width
CP "L" pulse width
DO set-up time
Symbol
tHW1
tLW
Min.
800
Typ.
—
Max.
—
Unit
ns
800
—
—
ns
tS
300
—
—
ns
DO holding time
tDH
300
—
—
ns
L clock set-up time
L clock holding time
L "H" pulse width
DF delay time
tSU
500
—
—
ns
tHO
100
—
—
ns
tHW2
tM
800
—
—
ns
–1000
—
1000
ns
VOH2
VOL2
VOH2
VOL2
DO
ts
tDH
tHW1
tLW
VOH2
VOH2
VOH2 VOH2
VOL2
VOL2
VOL2
CP
tSU
tHO
VOH2
VOH2
tHW2
VOL2
L
tM
DF
VOH2
12/45
¡ Semiconductor
MSM6222B-xx
FUNCTIONAL DESCRIPTION
Instruction Register (IR) and Data Register (DR)
These two registers are selected by the REGISTER SELECTOR (RS) pin.
The DR is selected when the "H" level is input to the RS pin and IR is selected when the "L"
level is input.
The IR is used to store the address of the display data RAM (DD RAM) or character
generator RAM (CG RAM) and instruction code.
The IR can be written, but not be read by the microcomputer (CPU).
The DR is used to write and read the data to and from the DD RAM or CG RAM.
The data written to DR by the CPU is automatically written to the DD RAM or CG RAM
as an internal operation.
When an address code is written to IR, the data (of the specified address) is automatically
transferred from the DD RAM or CG RAM to the DR. Next, when the CPU reads the DR,
it is possible to verify DD RAM or CG RAM data from the DR data.
After the writing of DR by the CPU, the next adress in the DD RAM or CG RAM is selected
to be ready for the next CPU writing.
Likewise, after the reading out of DR by the CPU, DD RAM or CG RAM data is read out
by the DR to be ready for the next CPU reading.
Write/read to and from both registers is carried out by the READ/WRITE (R/W) pin.
Table 1 RS and R/W pins functions
R/W
RS
L
Function
L
H
L
IR write
L
Read of busy flag (BF) and address counter (ADC)
H
DR write
DR read
H
H
Busy Flag (BF)
When the busy flag is at "H", it indicates that the MSM6222B-xx is engaged in internal
operation.
When the busy flag is at "H", any new instruction is ignored.
When R/W = "H" and RS = "L", the busy flag is output from DB .
7
New instruction should be input when busy flag is "L" level.
When the busy flag is at "H", the output code of the address counter (ADC) is undefined.
Address Counter (ADC)
The address counter (ADC) allocates the address for the DD RAM and CG RAM write/read
and also for the cursor display.
When the instruction code for a DD RAM address or CG RAM address setting is input to IR,
after deciding whether it is DD RAM or CG RAM, the address code is transferred from IR
to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM, the
ADC is incremented (decremented) by 1 internally.
The data of the ADC is output to DB - DB on the conditions that R/W = "H", RS = "L", and
0
6
BF = "L".
13/45
¡ Semiconductor
MSM6222B-xx
Timing Generator Circuit
This circuit is used to generate timing signals to activate internal operations upon receipt
of CPU instruction and also from such internal circuits as the DD RAM, CG RAM, and CG
ROM.
It is designed so that the internal operation caused by accessing from the CPU will not
interfere with the internal operation caused by LCD driving. Consequently, when data is
written from the CPU to DD RAM, flickering does not occur in a display area other than
the display area where the data is written.
In addition, this circuit generates the transfer signal to MSM5259 for display character
expansion.
Display Data RAM (DD RAM)
This RAM is used to store display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence
between the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
DB6
DB0
LSB
ADC
MSB
Hexadecimal notation
Hexadecimal notation
(Example)
When DD RAM
address is 2A
L
H
2
L
H
L
H
L
A
(1) Correspondence between address and display position in the 1-line display mode
First
digit
2
3
4
5
79 80
4E 4F
Display position
DD RAM address (hex.)
00 01 02 03 04
MSB
LSB
• When the MSM6222B-xx alone is used, up to 8 characters can be displayed from the
first to eighth digit.
First
digit
2
3
4
5
6
7
8
00 01 02 03 04 05 06 07
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
First
digit
2
3
4
5
6
7
8
(Display
shifted
to right)
4F 00 01 02 03 04 05 06
First
digit
2
3
4
5
6
7
8
(Display
shifted
to left)
01 02 03 04 05 06 07 08
14/45
¡ Semiconductor
MSM6222B-xx
• When the MSM6222B-xx is used with one MSM5259, up to 16 characters can be
displayed from the first to sixteenth digit as shown below:
First
digit
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
MSM6222B-xx display MSM5259 display
When the display is shifted by instruction, the correspondence between the LCD
display and the DD RAM address changes as shown below:
First
digit
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
(Display shifted to right)
(Display shifted to left)
4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
MSM6222B-xx display MSM5259 display
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
• Since the MSM6222B-xx has a DD RAM capacity of up to 80 characters, up to 9
MSM5259 devices can be connected to MSM6222B-xx so that 80 characters can be
displayed.
First
digit
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
73 74 75 76 77 78 79 80
42 49 4A 4B 4C 4D 4E 4F
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
MSM6222B-xx display
MSM5259 (1) display
MSM5259 (2)
- (8) display
MSM5259 (9) display
15/45
¡ Semiconductor
MSM6222B-xx
(2) Correspondence between address and display position in the 2-line display mode
First
digit
2
3
4
5
39 40
26 27
Display position
DD RAM address (hex.)
First line
00 01 02 03 04
40 41 42 43 44
Second line
66 67
(Note) The last address of the first line is not consecutive to the head address of the
second line.
• When MSM6222B-xx alone is used, up to 16 characters (8 characters x 2 lines) can be
displayed from the first to eighth digit.
First
digit
2
3
4
5
6
7
8
First line
00 01 02 03 04 05 06 07
40 41 42 43 44 45 46 47
Second line
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
First
digit
2
3
4
5
6
7
8
First line
27 00 01 02 03 04 05 06
67 40 41 42 43 44 45 46
(Display shifted to right)
(Display shifted to left)
Second line
First
digit
2
3
4
5
6
7
8
First line
01 02 03 04 05 06 07 08
41 42 43 44 45 46 47 48
Second line
• When the MSM6222B-xx is used with one MSM5259, up to 32 characters (16
characters x 2 lines) can be displayed from the first to the sixteenth digit.
First
digit
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
First line
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
Second line
MSM6222B-xx display
MSM5259 display
16/45
¡ Semiconductor
MSM6222B-xx
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
(Display shifted to right)
First
digit
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
First line
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
Second line
MSM6222B-xx display
MSM5259 display
(Display shifted to left)
First
digit
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
First line
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
Second line
MSM6222B-xx display
MSM5259 display
• Since the MSM6222B-xx has a DD RAM capacity of up to 80 characters, up to 4
MSM5259 devices can be connected to the MSM6222B-xx in the 2-line display mode.
First
digit 2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
33 34 35 36 37 38 39 40
20 21 22 23 24 25 26 27
First line
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
Second line 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51
60 61 62 63 64 65 66 67
MSM6222B-xx display
MSM5259 (1) display
MSM5259
(2) - (3) display
MSM5259 (4) display
Character Generator ROM (CG ROM)
The CG ROM is used to generate 5 x 7 dots (160 kinds) or 5 x 10 dots (32 kinds) character
patterns from an 8-bit DD RAM character code signal.
The correspondence between 8-bit character codes and character patterns is shown in
Table 2.
When the 8-bit character code of the CG ROM is written to the DD RAM, the character
patternoftheCGROMcorrespondingtothecodeisdisplayedontheLCDdisplayposition
corresponding to the DD RAM address.
17/45
Upper
4 bits
MSB
0000
Lower
4 bits
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
CG
0000
LSB
0
@
P
/
p
a
R
RAM (1)
(2)
!
1
2
3
4
5
6
7
8
9
:
A
B
C
D
E
Q
R
S
T
U
V
W
X
Y
Z
[
a
b
c
d
e
f
q
r
ä
b
e
q
Q
•
W
ü
0001
(3)
(4)
(5)
(6)
(7)
(8)
(1)
(2)
(3)
(4)
(5)
(9)
(7)
(8)
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
#
$
s
t
m
s
r
g
%
&
u
v
F
S
p
n
G
H
I
w
x
(
)
h
i
X
√
y
–1
*
+
J
j
z
x
;
K
L
k
l
{
<
=
>
?
¥
]
Ù
}
¢
£
n
ö
–
.
M
N
O
m
n
o
÷
^
_
Æ
¨
/
°
¡ Semiconductor
MSM6222B-xx
Character Generator RAM (CG RAM)
The CG RAM is used to display user's original character patterns other than character
patterns in the CG ROM.
The CG RAM has a capacity (64 bytes = 512 bits) of writing 8 kinds of characters for 5 x 7
dots and 4 kinds of characters for 5 x 10 dots.
When displaying character patterns stored in the CG RAM, write 8-bit character codes (00
to 07 or 08 to 0F; hex.) on the left side as shown in Table 2. Then it is possible to output the
character pattern to the LCD display position corresponding to the DD RAM address.
The following explains how to write and read character patterns to and from the CG RAM.
(1) When the character pattern is 5 x 7 dots (see Table 3-1).
• A method of writing character pattern to the CG RAM by CPU:
Three bits of CG RAM addresses 0-2 correspond to the line position of the character
pattern.
First, set increment or decrement by the CPU, and then input the CG RAM address.
After this, write character patterns to the CG RAM through DB - DB line by line.
0
7
DB to DB correspond to CG RAM data 0-7 in Table 3-1.
0
7
It is displayed when "H" is set as input data and is not displayed when "L" is set as
input data.
Since the ADC is automatically incremented or decremented by 1 after the writing of
data to the CG RAM, it is not necessary to set the CG RAM address again.
The line, in which the CG RAM addresses 0-2 are all "H" ("7" in hexadecimal
notation), is the cursor position. It is ORed with the cursor at the cursor position and
displayed to LCD.
For this reason, it is necessary to set all input data that become cursor positions to "L".
Although CG RAM data 0-4 bits are output to the LCD as display data, CG RAM data
bits 5-7 are not output. The latter can be written and read to and from the RAM, it
is therefore allowed to be used as data RAM.
• A method of displaying the CG RAM character pattern to the LCD:
The CG RAM is selected when upper 4 bits of the character codes are all "L".
As character code bit 3 is invalid, the display of "0" in Table 3-1, is selected by
character code "00" (hex.) or "08" (hex.).
Whenthe8-bitcharactercodeoftheCGRAMiswrittentotheDDRAM, thecharacter
pattern of the CG RAM is displayed on the LCD display position corresponding to
the DD RAM address. (DD RAM data, bits 0-2 correspond to CG RAM address, bits
3-5.)
19/45
¡ Semiconductor
MSM6222B-xx
(2) When character pattern is 5 x 10 dots (see Table 3-2).
• A method of writing character pattern into the CG RAM by the CPU:
Four bits of CG RAM address, bits 0-3, correspond to the line position of the character
pattern.
First, set increment or decrement with the CPU, and then input the address of the CG
RAM.
After this, write the character pattern code into the CG RAM, line by line from DB -
0
DB .
7
DB to DB correspond to CG RAM data, bits 0-7, in Table 3-2.
0
7
It is displayed when "H" is set as input data, while it is not displayed when "L" is set
as input data.
As the ADC is automatically incremented or decremented by 1 after the writing of
data to the CG RAM, it is not necessary to set the CG RAM address again.
The line, the CGRAM addresses 0-3 of which are "A" in hexadecimal notation, is the
cursor position. The CGRAM data is 0Red with the cursor at the cursor position and
displayed to LCD. For this reason, it is necessary to set all input data that become
cursor positions to "L".
WhentheCGRAMdata, bits0-4, andCGRAMaddresses, bits0-3, are"0"to "A", they
are displayed on the LCD as the display data. When the CG RAM data, bits of 5-7,
and CG RAM, bit data is 0-4 and CG RAM address data is "B" to "F", it is not output
to the LCD.
But in this case, CG RAM can be used as RAM and it can be written into/read out.
So, it can be used as the data RAM.
• A method of displaying the CG RAM character pattern to the LCD:
The CG RAM is selected when 4-upper order bits of the character code are all "L".
As character code bits 0 and 3 are invalid, the display of "m" is selected by character
codes "00", "01", "08", and "09" (hex.) as in Table 3-2.
When the CG RAM character code is written to the DD RAM, the CG RAM character
pattern is displayed on the LCD display position corresponding to the DD RAM
address.
(DD RAM data bits 1 and 2 correspond to CG RAM address bits 4 and 5.)
20/45
¡ Semiconductor
MSM6222B-xx
Table 3-1 Relationship between CG RAM data (character pattern), CG RAM address and
DD RAM data when the character pattern is 5 x 7 dots.
The example below indicates "OKI".
CG RAM data
DD RAM data
(character code)
CG RAM address
(character pattern)
5
MSB
4
2
1
7
5
4
2
1
7
MSB
6
L
5
4
2
1
3
0
LSB
3
0
LSB
3
0
LSB
6
MSB
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
X
X
X
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
L
L
X
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
H
L
X
X
X
L
L
L
L
X
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
X
X
X
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
X : Don't Care
21/45
¡ Semiconductor
MSM6222B-xx
Table 3-2 Relationship between CG RAM data (character pattern), CG RAM address and
DD RAM data when the character pattern is 5 x 10 dots. The examples below
W
indicate m, g and
.
CG RAM data
DD RAM data
(character code)
CG RAM address
(character pattern)
5
4
2
1
7
6
5
4
2
1
7
6
5
4
2
1
3
0
3
0
3
0
MSB
MSB
MSB
LSB
LSB
LSB
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
X
X
L
L
L
L
L
L
L
H
L
L
L
L
L
L
X
L
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
L
L
L
L
X
L
L
L
L
H
L
L
L
L
L
X
H
H
H
H
H
L
L
L
L
L
L
L
L
L
X
L
L
X
L
H
H
L
L
H
H
L
L
H
H
L
X
X
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
X
X
L
L
L
H
H
H
L
L
L
L
L
X
L
L
H
L
L
L
H
L
L
H
L
X
L
L
H
L
L
L
H
L
L
H
L
X
L
L
H
L
L
L
H
L
L
H
L
X
L
L
H
H
H
H
H
H
H
L
L
L
L
L
X
L
H
X
L
H
H
L
L
H
H
L
L
H
H
L
X
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
X
X
L
L
H
L
H
H
L
L
L
L
L
X
L
L
H
H
L
L
H
L
L
L
L
X
L
L
L
L
L
L
H
L
L
L
L
X
L
L
H
H
L
L
H
L
L
L
L
X
L
L
H
L
H
H
L
L
L
L
L
X
L
L
L
L
X
H
H
X
L
H
H
L
L
H
H
L
L
H
H
H
X : Don't Care
22/45
¡ Semiconductor
MSM6222B-xx
Cursor/Blink Control Circuit
This is a circuit that generates the LCD cursor and blink.
This circuit is under the control of the CPU program.
The display of the cursor and blink on the LCD is made at a position corresponding to the
DD RAM address that is set in the ADC.
The figure below shows an example of the cursor/blink position when the value of ADC
is set to "07" (hex.).
DB6
L
DB0
H
ADC
L
0
L
L
H
H
7
First
digit
2
3
4
5
6
7
8
9
79 80
4E 4F
In 1-line display mode
00 01 02 05 04 05 06 07 08
Cursor and blink position
First
digit
2
3
4
5
6
7
8
9
39 40
26 27
First line
00 01 02 03 04 05 06 07 08
40 41 42 43 44 45 46 47 48
In 2-line display mode
Second line
66 67
Cursor and blink position
(Note) The cursor and blink are displayed even when the CG RAM address is set in the
ADC. For this reason, it is necessary to inhibit the cursor and blink display while
the CG RAM address is set in the ADC.
LCD Display Circuit (COM to COM , SEG to SEG , L, CP, DO, and DF)
1
16
1
40
As the MSM6222B-xx provides the COM signal outputs (16 outputs) and the SEG signal
outputs (40 outputs), it can display 8 characters (1-line display) or 16 characters (2-line
display) as a unit.
SEG to SEG are used to display 8-digit display on the LCD. To expand the display, an
1
40
MSM5259 is used.
The MSM5259, 40-dot segment driver, is used for expansion of the SEG signal output.
Interface with the MSM5259 is made through data output pin (DO), clock output pin (CP),
latch output pin (L), and display frequency pin (DF). The character pattern data is serially
transferred to MSM5259 through DO and CP. When the data of 72 characters 360-bit (= 5-
bit/ch. x 72 ch. = 1-line display) or 32 characters 160-bit (5-bit/ch. x 32 ch. = 2-line display)
is output, the latch pulse is also output through pin L. By this latch pulse, the data
transferred serially to MSM5259 is latched to be used as display data. The display
frequency signal (DF) required when LCD is displayed is also output from DF pin
synchronously with this latch pulse.
23/45
¡ Semiconductor
MSM6222B-xx
Built-in Reset Circuit
The MSM6222B-xx is automatically initialized when the power is turned on.
During initialization, the busy flag (BF) holds "H" and does not accept instructions (other
than the busy flag read).
The busy flag holds "H" for 15 ms after V reaches 4.5V or more.
DD
During initialization, the MSM6222B-xx executes the follwing instructions:
• Display clear
• Data length of interface with CPU: 8 bits (8B/4B = "H")
• LCD: 1-line display (N = "L")
• Character font: 5 x 7 dots (F = "L")
• ADC: Increment (I/D = "H")
• No display shift (SH = "L")
• Display: Off (DI = "L")
• Cursor: Off (C = "L")
• No blink (B = "L")
It is required to satisfy the following power supply conditions.
4.5V
0.2V
0.2V
0.2V
VDD
tON
tOFF
0.1ms £ tON £ 100ms
1ms £ tOFF
Fig. 1. Power ON/OFF Waveform
24/45
¡ Semiconductor
MSM6222B-xx
Data Bus Connected with CPU
The data bus connected with CPU is available either once for 8 bits or twice for 4 bits. This
allows the MSM6222B-xx to be interfaced with either an 8-bit or 4-bit CPU.
(1) When the interface data length is 8 bits
Data buses DB to DB (8 buses) are all used and data input/output is carried out in
0
7
one step.
(2) When the interface data length is 4 bits
The 8-bit data input/output is carried out in two steps by using only high-order 4 bits
of data buses DB to DB (4 buses)
4
7
The first time data input/output is made for 4-high order bits (DB to DB when the
4
7
interfaces data length is 8 bits) and the second time data input/output is made for low-
order 4 bits (DB to DB when the interface data length is 8 bits). Even when the data
0
3
input/output can be completely made through high-order 4 bits, be sure to make
another input/output of low-order 4 bits. (Example: Busy flag Read).
Since the data input/output is carried out in two steps but as one execution, no normal
data transfer is executed from the next input/output if accessed only once.
25/45
¡ Semiconductor
MSM6222B-xx
RS
R/W
E
Busy
(internal
operation)
No
Busy
IR7
Busy
DR7
DB7
ADC6
IR6
DR6
DB6
IR5
DR5
DR4
ADC5
ADC4
DB5
IR4
IR3
IR2
IR1
IR0
DB4
DB3
DB2
DB1
DB0
ADC3
ADC2
ADC1
ADC0
DR3
DR2
DR1
DR0
Instruction
register(IR)
write
Busy flag(BF)and address
counter(ADC)read
Data register
(DR)write
Fig. 2 8-Bit Data Transfer
26/45
RS
R/W
E
Busy(internal
operation)
No
Busy
ADC3
DR7
DR3
IR7
IR3
DB7
DB6
DB5
DB4
Busy
ADC6
ADC5
ADC4
ADC2
ADC1
ADC0
IR6
IR5
IR4
IR2
IR1
IR0
DR6
DR5
DR4
DR2
DR1
DR0
Instruction register
(IR)write
Busy flag(BF)and address
counter(ADC)read
Data register
(DR)write
Fig. 3 4-Bit Data Transfer
¡ Semiconductor
MSM6222B-xx
Instruction Code
The instruction code is defined as the signal through which the MSM6222B-xx is accessed
by the CPU.
The MSM6222B-xx begins operation upon receipt of the instruction code input.
As the internal processing operation of MSM6222B-xx starts in a timing that does not affect
the LCD display, the busy status continues for longer than the CPU cycle time.
Underthebusystatus(whenthebusyflagissetto"H"), theMSM6222B-xxdoesnotexecute
any instructions other than the busy flag read.
Therefore, the CPU has to verify that the busy flag is set to "L" prior to the input of the
instruction code.
(1) Display clear:
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
L
L
L
L
L
L
L
L
H
When this instruction is executed, the LCD display is cleared.
I/D in the entry mode setting is set to "H" (increment). SH does not change.
When the cursor and blink are in display, the blinking position moves to the left end of the
LCD (the left end of the first line in the 2-line display mode).
(Note) All DD RAM data goes to "20" (hex.), while the address counter (ADC) goes to "00"
(hex.). The execution time is 1.64 ms (max.), when the OSC oscillation frequency
is 250 kHz.
(2) Cursor home
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
L
L
L
L
L
L
L
H
X
X : Don't Care
When this instruction is executed, the blinking position moves to the left end of the LCD
(to the left end of the first line in the 2-line display mode) as the cursor and blink are being
displayed.
When the display is in shift, the display returns to its original position before shifting.
(Note) The address counter (ADC) goes to "00" (hex.). The execution time is 1.64 ms
(max.), when the OSC oscillation frequency is 250 kHz.
28/45
¡ Semiconductor
MSM6222B-xx
(3) Entry mode setting
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
I/D SH
Instruction code
L
L
L
L
L
L
L
H
1 When the I/D is set, the 8-bit character code is written or read to and from the DD
RAM, the cursor and blink shift to the right by 1 character position (I/D = "H";
increment) or to the left by 1 character position (I/D = "L"; decrement).
The address counter is incremented (I/D = "H") or decremented (I/D = "L") by 1 at
this time. Even after the character pattern code is written or read to and from the
CG RAM, the address counter (ADC) is incremented (I/D = "H") or decremented
(I/D = "L") by 1.
2 When SH = "H" is set, the character code is written to the DD RAM. Then the cursor
and blink stop and the entire display shifts to the left (I/D = "H") or to the right (I/
D = "L") by 1 character position.
When the character is read from the DD RAM during SH = "H", or when the
character pattern data is written or read to or from the CG RAM during SH = "H",
the entire display does not shift, but normal write/read is performed (the entire
display does not shift, but the cursor and blink shift to the right (I/D = "H") or to the
left (I/D = "L") by 1 character position.
WhenSH="L"isset,thedisplaydoesnotshift,butnormalwrite/readisperformed.
The execution time when the OSC oscillation frequency is 250 kHz is 40 ms.
(4) Display mode setting
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
L
L
L
L
L
H
DI
C
B
1 The DI bit controls whether the character pattern is displayed or not displayed.
When DI is "H", this bit makes the LCD display the character pattern.
When DI is "L", the LCD character pattern is not displayed. The cursor and blink
are also cancelled at this time.
(Note) Unlike the display clear, the character code is not rewritten at all.
2 The cursor is not displayed when C = "L" and is displayed when DI = "H" and C =
"H".
3 The blink is cancelled when B = "L" and is executed when DI = "H" and B = "H".
In the blink mode, all dots (including the cursor), displaying character pattern, and
cursor are displayed alternately at 409.6 ms (in 5 x 7 dots character font) or 563.2 ms
(in 5 x 10 dots character font) when the OSC oscillation frequency is 250 kHz. The
execution time when the OSC oscillation frequency is 250 kHz is 40 ms.
29/45
¡ Semiconductor
MSM6222B-xx
(5) Cursor and display shift
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D/C R/L
Instruction code
L
L
L
L
L
H
X
X
X : Don't Care
When D/C = "L" and R/L = "L", the cursor and blink positions are shifted to the left by
1 character position (ADC is decremented by 1).
When D/C = L and R/L = "H", the cursor and blink positions are shifted to the right by
1 character position (ADC is incremented by 1).
When D/C = "H" and R/L = "L", the entire display is shifted to the left by 1 character
position. The cursor and blink positions are also shifted with the display (ADC remains
unchanged).
When D/C = "H" and R/L = "H", the entire display is shifted to the right by 1 character
position. The cursor and blink positions are also shifted with the display (ADC remains
unchanged).
In the 2-line display mode, the cursor and blink positions are shifted from the first to
the second line when the cursor is shifted to the right next to the fortieth digit (27; hex.)
in the first line. No such shifting is made in other cases.
When shifting the entire display, the display pattern, cursor, and blink positions are in
no case shifted between lines (from the first to the second line or vice versa).
The execution time, when the OSC oscillation frequency is 250 kHz, is 40 ms.
(6) Initial setting
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
L
L
L
H
8B/4B
N
F
X
X
X : Don't Care
1 When 8B/4B = "H", the data input/output to and from the CPU is carried out
simultaneously by means of 8 bits DB to DB .
7
0
When 8B/4B = "L", the data input/output to and from the CPU is carried out in two
steps through 4 bits of DB to DB .
7
4
2 The 2-line display mode of the LCD is selected when N = "H", while the 1-line
display mode is selected when N = "L".
3 The 5 x 7 dots character font is selected when F = "L", while the 5 x 10 dots character
font is selected when F = "H" and N = "L".
This initial setting has to be accessed prior to other instructions except for the busy
flag read after the power is supplied to the MSM6222B-xx.
Number of
display lines
Character
font
Number of
COMMOM signals
Duty
ratio
Number
of biases
N
F
L
L
L
H
L
1 - line
1 - line
2 - line
2 - line
5 x 7 dots
5 x 10 dots
5 x 7 dots
5 x 7 dots
1/8
4
4
5
5
8
11
16
16
1/11
1/16
1/16
H
H
H
30/45
¡ Semiconductor
MSM6222B-xx
Generate biases externally and input them to the MSM6222B-xx (V , V , V , V , V ,
DD
1
2
3
4
and V ).
5
When the number of biases is 4, input the same potential to V and V . The execution
2
3
time, when the OSC oscillation frequency is 250 kHz, is 40 ms.
(7) CG RAM address setting
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
L
L
H
C5 C4 C3 C2 C1 C0
When CG RAM addresses, bits C to C (binary), are set, the CG RAM is specified, until
5
0
the DD RAM address is set.
Write/read of the character pattern to and from the CPU begins with addresses, bits C
5
to C , starting from CG RAM selection.
0
The execution time, when the OSC oscillation frequency is 250 kHz, is 40 ms.
(8) DD RAM address setting
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
L
H
D6 D5 D4 D3 D2 D1 D0
When the DD RAM addresses D to D (binary) are selected, the DD RAM is specified
6
0
until the DD RAM address is set.
Write/read of the character code to and from the CPU begins with addresses D to D
6
0
starting from DD RAM selection.
In the 1-line display mode (N = H), however, D to D (binary) must be set to one of the
6
0
values among "00" to "4F" (hex.).
Likewise, in the 2-line mode, D to D (binary) must be set to one of the values among
6
0
"00" to "27" (hex.) or "40" to "67" (hex.).
When any value other than the above is input, it is impossible to make a normal write/
read of character codes to and from the DD RAM.
The execution time, when the OSC oscillation frequency is 250 kHz, is 40 ms.
(9) DD RAM and CG RAM data write
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
H
E7 E6 E5 E4 E3 E2 E1 E0
When E to E (binary) codes are written to the DD RAM or CG RAM, the cursor and
7
0
display move as described in "(5) Cursor and display shift". The execution time, when
the OSC oscillation frequency is 250 kHz, is 40 ms.
31/45
¡ Semiconductor
MSM6222B-xx
(10) Busy flag and address counter read (Execution time is 1 ms.)
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
H
L
BF O6 O5 O4 O3 O2 O1 O0
The busy flag (BF) is output by this instruction to indicate whether the MSM6222B-xx
is engaged in internal operations (BF = "H") or not (BF = "L").
When BF = "H", no new instruction is accepted. It is therefore necessary to verify BF =
"L" before inputting a new instruction.
When BF = "L", a correct address counter value is output. The address counter value
must match the DD RAM address or CG RAM address. The decision of whether it is
a DD RAM address or CG RAM address is made by the address previously set.
SincetheaddresscountervaluewhenBF="H"issometimesincrementedordecremented
by 1 during internal operations, it is not always a correct value.
(11) DD RAM and CG RAM data read
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
H
H
P7 P6 P5 P4 P3 P2 P1 P0
Character codes (bits P to P ) are read from the DD RAM, while character patterns (P
7
7
0
to P ) from the CG RAM.
0
Selection of DD RAM or CG RAM is decided by the address previously set.
After reading those data, the address counter (ADC) is incremented or decremented by
1 as set by the shift mode mentioned in item "(3) shift mode set".
The execution time, when the OSC oscillation frequency is 250 kHz, is 40 ms.
(Note) Conditions for the reading of correct data:
1 When the DD RAM address set or CG RAM address set is input before
inputting this instruction.
2 When the cursor/display shift is input before inputting this instruction in
case the character code is read.
3 Data after the second reading from RAM when read more than 2 times.
Correct data is not output in any other case.
32/45
¡ Semiconductor
MSM6222B-xx
Interface with LCD and MSM5259
Displayexampleswhensettingthe5x7dotscharacterfont1-linemode, 5x10dotscharacterfont
1-line mode, and 5 x 7 dots character font 2-line mode through instructions are shown in Figures
4, 5, and 6, respectively.
When the 5 x 7 dots character font is set in the 1-line display mode, the COM signals COM to
9
COM are output for extinguishing.
16
Likewise, when the 5 x 10 dots character font (1-line is set), the COM signals COM to COM
12
16
are output for display-off.
The display example shows a combination of 16 characters (32 characters for the 2-line display
mode) and the LCD. When the number of MSM5259s are increased according to the increase in
the number of characters, it is possible to display a maximum of 80 characters.
Besides, it is necessary to generate bias voltage required for LCD operation by splitting resistors
outside the IC to input it to MSM6222B-xx and MSM5259.
Examples of these bias voltages are shown in Figures 7, 8, 9, and 10. Basically, this can be done
by dividing the voltage by the resistors as shown in Figures 7 and 8. If the value of resistor R is
made larger to reduce system power consumption, the LCD operating margin decreases and the
LCD driving waveform is distorted. To prevent this, a by-pass capacitor is serially connected to
the resistor to lower voltage division impedance caused by the splitting of resistors as shown in
Figures 9 and 10.
As the values of R, VR, and C vary according to the LCD size used and V
(LCD drive voltage),
LCD
these values have to be determined through actual experimentation in combination with the
LCD.
(Example set values: R = 3.3 to 10kW, V = 10 to 30kW, and C = 0.0022 mF to 0.047 mF)
R
Figure 17 shows an application circuit for the MSM6222B-xx and MSM5259 including a bias
circuit.
The bias voltage has to maintain the following potential relation:
V
DD
> V > V ≥ V > V > V
1 2 3 4 5
• In the case of 1-line 16 characters display (5 x 7 dots/font)
COM
COM
1
LCD
8
SEG
SEG
O
1
O
1
40
1
40
DO
CP
DI
MSM6222B-xx
MSM5259
DF DO
CP
DF
L
LOAD
DI
20
21
Figure 4
33/45
¡ Semiconductor
MSM6222B-xx
• In the case of 16-character (1 line) display (5 x 10 dots/font)
COM
1
LCD
COM
11
SEG
SEG
O
1
O
1
40
1
40
DO
CP
DI
MSM6222B-xx
MSM5259
DF DO
CP
DF
L
LOAD
DI
20
21
Figure 5
• In the case of 16-character (2 lines) display (5 x 7 dots/font)
COM
1
COM
COM
COM
7
8
9
LCD
COM
COM
15
16
SEG
SEG
O
1
O
1
40
1
40
DO
CP
DI
MSM6222B-xx
MSM5259
DF DO
CP
DF
L
LOAD
DI
20
21
Figure 6
34/45
¡ Semiconductor
MSM6222B-xx
• Bias voltage circuit (1-line display mode)
• Bias voltage circuit (2-line display mode)
VDD
VDD
R
R
V1
V1
R
R
V2
V2
VLCD
MSM6222B-xx
VLCD
MSM6222B-xx
R
R
R
R
V3
V4
V3
V4
V5
VR
VR
V5
Figure 8
Figure 7
• Bias voltage circuit (1-line display mode)
• Bias voltage circuit (2-line display mode)
VDD
VDD
R
C
R
C
V1
V1
R
C
R
V2
V2
C
MSM6222B-xx
VLCD
MSM6222B-xx
R
R
VLCD
C
C
C
R
V3
V3
V4
C
V4
R
C
VR
V5
VR
C
R
V5
C
Figure 10
Figure 9
(VLCD : LCD driving voltage)
35/45
¡ Semiconductor
MSM6222B-xx
• Application circuit
Figure 11
36/45
¡ Semiconductor
MSM6222B-xx
LCD Drive Waveforms
Figures 12, 13 and 14 show the LCD driving waveforms consisting of COM signal, SEG signal,
DF signal and L (latch pulse waveform) signal, in the duty of 1/8, 1/11 and 1/16 respectively.
The relation between duty and frame frequency is described in the table below.
Duty
1/8
Frame frequency
78.1 Hz
1/11
1/16
56.8 Hz
78.1 Hz
(Note) The OSC oscillation frequency is assumed to be 250 kHz.
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¡ Semiconductor
MSM6222B-xx
8
1
2
3
4
5
6
7
8
1
2
VDD
V1
COM1
COM2
COM8
COM9
COM16
V2,V3
V4
V5
1 frame
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
VDD
V1
V2,V3
V4
V5
Display-off
waveform
VDD
V1
SEG
V2,V3
V4
V5
(Output
example)
Display-on
waveform
DF
L
Figure 12. LCD Driving Waveform at 1/8 Duty
38/45
¡ Semiconductor
MSM6222B-xx
11
1
2
3
4
5
6
7
8
9
10 11
1
2
VDD
V1
V2,V3
V4
COM1
V5
1 frame
VDD
V1
V2,V3
COM2
V4
V5
VDD
V1
V2,V3
V4
COM11
V5
VDD
V1
V2,V3
V4
COM12
V5
VDD
V1
V2,V3
V4
COM16
V5
Display-off
waveform
VDD
V1
V2,V3
V4
SEG
(Output
example)
V5
Display-on
waveform
DF
L
Figure 13. LCD Driving Waveform at 1/11 Duty
39/45
¡ Semiconductor
MSM6222B-xx
16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
VDD
V1
V2
COM1
V3
V4
V5
1 frame
VDD
V1
V2
V3
V4
V5
COM2
VDD
V1
V2
V3
COM16
V4
V5
Display-off
waveform
VDD
V1
V2
V3
V4
V5
SEG
(Output
example)
Display-on
waveform
DF
L
Figure 14. LCD Driving Waveform at 1/16 Duty
40/45
¡ Semiconductor
MSM6222B-xx
Initial Setting of Instruction
(1) When data input/output to and from the CPU is carried out by 8 bits (DB to DB ):
0
7
q Turn on the power.
w Wait for 15 ms or more after V has reached 4.5V or more.
DD
e Set 8B/4B at "H" by initial setting of instruction.
r Wait for 4.1 ms or more.
t Set 8B/4B at "H" by initial setting of instruction.
y Wait for 100 ms or more.
u Set 8B/4B at "H" by initial setting of instruction.
i Check the busy flag as No Busy.
o Set 8B/4B at "H". Set LCD line number (N) and character font (F).
(After this, do not change the LCD line number and character font.)
! Check No Busy.
! Clear the display by setting the display mode.
! Check No Busy.
! Clear the display.
! Check No Busy.
! Set the shift mode.
! Check No Busy.
! Initial setting completed.
Example of Instruction Code for Steps e, t, and u.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
L
L
L
L
H
H
X
X
X
X
X : Don't Care
41/45
¡ Semiconductor
MSM6222B-xx
(2) When data input/output to and from the CPU is carried out by 4 bits (DB to DB ):
4
7
q Turn on the power.
w Wait for 15 ms or more after V has reached 4.5V or more.
DD
e Set 8B/4B at "H" by initial setting of instruction.
r Wait for 4.1 ms or more.
t Set 8B/4B at "H" by initial setting of instruction.
y Wait for 100 ms or more.
u Set 8B/4B at "H" by initial setting of instruction.
i Check the busy flag as No Busy.
o Set 8B/4B at "L". Set LCD line number (N) and character font (F).
! Wait for 100 ms or more.
! Set 8B/4B at "L". Set LCD line number (N) and character font (F).
! Check No Busy.
! Clear the display by setting the display mode.
! Check No Busy.
! Clear the display.
! Check No Busy.
! Set the shift mode.
! Check No Busy.
! Initialization completed.
Example of Instruction Code for Steps e, t, and u.
R/W RS DB7 DB6 DB5 DB4
L
L
L
L
H
H
Example of Instruction Code for Step i.
R/W RS DB7 DB6 DB5 DB4
H
L
BF O6 O5 Q4
Example of Instruction Code for Step o.
R/W RS DB7 DB6 DB5 DB4
L
L
L
L
H
L
Execute two-step accesses in 4 bits from Step ! to Step !.
42/45
¡ Semiconductor
MSM6222B-xx
Differences Between HD44780 and MSM6222B-xx
Item
MSM6222B - xx
HD44780
LCD driving voltage (VLCD
1/4 bias
)
3.0 to 11.0 (V)
4.6 to 11.0 (V)
3.0 to 8.0 (V)
3.0 to 8.0 (V)
1/5 bias
Bus interface speed with CPU
1 MHz (1000 ns)
1.5 MHz (667 ns)
Since signal rise/fall time is quite fast,
the electromagnetic induction between
lines of the PCB and the cable
assignment should be noted.
The increment and decrement
of the address counter in writing/ or decremented 6 msec
reading the data to/from the
CGRAM/DDRAM.
The address counter is incremented
The address counter is incremented
or decremented during the busy
condition.
So, data can be written into/read out
from the RAM immediately after the
busy condition was over.
(when ƒOSC = 250 KHz) after the
busy condition is released.
(Period of busy condition is 40 ms)
So, the data cannot be written into/
read out from the RAM for 6 msec
after the busy condition was over.
The repeated input frequency
(oscillation frequency=250kHz)
of display clear instruction
610 Hz or less (1.64 ms or more)
78 Hz or less in 5¥7 dots (12.8 ms or
more), 56Hz or less in 5¥10 dots (17.9
ms or more)
43/45
¡ Semiconductor
PACKAGE DIMENSIONS
QFP80-P-1420-0.80-L
MSM6222B-xx
(Unit : mm)
Spherical surface
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
44/45
¡ Semiconductor
MSM6222B-xx
(Unit : mm)
QFP80-P-1420-0.80-BL
Spherical surface
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
45/45
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