MSM5416258A-45TS-K [OKI]
EDO DRAM, 256KX16, 45ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40;
| 型号： | MSM5416258A-45TS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | EDO DRAM, 256KX16, 45ns, CMOS, PDSO40, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-44/40 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2L0047-28-Z2
This version: Dec. 1998
Previous version: Jan. 1998
¡ Semiconductor
MSM5416258A
262,144-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM5416258A is a 262,144-word ¥ 16-bit dynamic RAM fabricated in Oki's CMOS silicon gate
technology. The MSM5416258A achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer
metal CMOS process. The MSM5416258A is available in a 44/40-pin plastic TSOP.
FEATURES
• 262,144-word ¥ 16-bit configuration
• Single 5.0 V power supply, ±0.5 V tolerance
• Input:
TTL compatible
• Output: TTL compatible, 3-state
• Refresh: 512 cycles/8 ms
• Fast page mode with EDO, read modify write capability
• Byte wide control: 2 CAS control
• CAS before RAS refresh, hidden refresh, RAS only refresh capability
• Package :
44/40-pin 400 mil plastic TSOP (Type II) (TSOPII44/40-P-400-0.80-K) (Product : MSM5416258A-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Power Dissipation
(Max.)
Access Time (Max.)
tRAC tAA tCAC tOEA
40 ns 22 ns 10 ns 10 ns
45 ns 24 ns 12 ns 12 ns
Cycle Time (Min.)
Family
tRC
tHPC
15 ns
20 ns
MSM5416258A-40
MSM5416258A-45
80 ns
90 ns
825 mW
770 mW
1/21
¡ Semiconductor
MSM5416258A
PIN CONFIGURATION (TOP VIEW)
VCC
1
44 VSS
DQ0 2
DQ1 3
DQ2 4
DQ3 5
43 DQ15
42 DQ14
41 DQ13
40 DQ12
39 VSS
VCC
6
DQ4 7
DQ5 8
DQ6 9
DQ7 10
38 DQ11
37 DQ10
36 DQ9
35 DQ8
VSS* 13
32 VSS*
NC 14
31 LCAS
30 UCAS
29 OE
28 A8
WE 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
VCC 22
27 A7
26 A6
25 A5
24 A4
23 VSS
44/40-Pin Plastic TSOP (II)
(K Type)
Pin Name
A0 - A8
RAS
Function
Address Input
Row Address Strobe
LCAS, UCAS
DQ0 - DQ15
WE
Column Address Strobe
Data - Input / Data - Output
Write Enable
OE
Output Enable
VCC
Power Supply (5.0 V)
Ground (0 V)
VSS
NC
No Connection
VSS
*
Ground (0 V)*
Note: The same power supply voltage must be provided to every V pin, and the same GND
CC
voltage level must be provided to every V pin.
SS
*:
For improved signal integrity, it is recommended to connect the V * pins, pin 13 and pin 32,
to GND: the pins are electrically connected to internal GND.
SS
2/21
¡ Semiconductor
BLOCK DIAGRAM
OE
MSM5416258A
WE
Timing
RAS
Generator
I/O
Controller
LCAS
UCAS
I/O
Controller
Output
Buffers
8
8
8
DQ0 - DQ7
Column
Address
Buffers
Input
Buffers
9
Column Decoders
Sense Amplifiers
9
8
I/O
Selector
Internal
Address
Counter
16
16
Refresh
Control Clock
A0 - A8
Input
Buffers
8
8
8
Row
Address
Buffers
Row
Deco-
ders
9
9
Word
Drivers
Memory
Cells
DQ8 - DQ15
Output
Buffers
8
VCC
On-chip
BB Generator
V
VSS
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
LCAS
UCAS
WE
OE
*
DQ0 - DQ7
High-Z
High-Z
DOUT
DQ8 - DQ15
High-Z
High-Z
High-Z
DOUT
Standby
Refresh
H
L
L
L
L
L
L
L
L
*
H
L
H
L
L
H
L
L
*
H
H
L
L
H
L
L
L
*
*
*
Lower Byte Read
Upper Byte Read
Word Read
H
H
H
L
L
L
H
L
High-Z
DOUT
L
DOUT
L
H
H
H
H
DIN
Don't Care
DIN
Lower Byte Write
Upper Byte Write
Word Write
—
Don't Care
DIN
DIN
High-Z
High-Z
* : "H" or "L"
3/21
¡ Semiconductor
MSM5416258A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
—
Rating
–1.0 to 7.0
50
Unit
V
IOS
mA
W
PD
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
—
°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Symbol
VCC
Min.
4.5
0
Typ.
5.0
0
Max.
Unit
V
5.5
0
Power Supply Voltage
VSS
V
Input High Voltage
Input Low Voltage
VIH
2.4
–1.0
—
VCC + 1.0
0.8
V
V
VIL
—
Capacitance
(VCC = 5.0 V 0.5 V, Ta = 25°C, f = 1 MHꢀ)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A8)
CIN1
—
5
pF
Input Capacitance
(RAS, LCAS, UCAS, WE, OE)
CIN2
CI/O
—
—
7
7
pF
pF
Input / Output Capacitance
(DQ0 - DQ15)
4/21
¡ Semiconductor
MSM5416258A
DC Characteristics
(VCC = 5.0 V 0.5 V, Ta = 0°C to 70°C)
MSM5416258A
-40
MSM5416258A
-45
Parameter
Symbol
Condition
UnitNote
Min.
2.4
0
Max.
VCC
0.4
Min.
2.4
0
Max.
VCC
0.4
Output High Voltage
Output Low Voltage
Input Leakage Current
VOH
VOL
ILI
I
OH = –2.5 mA
V
V
IOL = 2.0 mA
0 V £ VI £ VCC
–10
10
–10
10
mA
DQi Disable
0 V £ VO £ 5.5 V
Output Leakage Current
ILO
–10
10
–10
10
mA
Average Power
Supply Current
(Operating)
RAS, CAS Cycling,
1, 2
1
ICC1
ICC2
ICC3
—
150
—
140
mA
mA
mA
tRC = Min.
Power Supply
Current (Standby)
RAS, CAS = VIH
—
—
3
—
—
3
Average Power
Supply Current
(RAS Only Refresh)
RAS = Cycling,
CAS = VIH,
1, 2
150
140
tRC = Min.
Average Power
Supply Current
(Fast Page Mode)
RAS = VIL,
1, 3
1, 2
ICC4
—
—
130
150
—
—
115
140
mA
mA
CAS Cycling,
t
HPC = Min.
Average Power
Supply Current
(CAS before RAS Refresh)
RAS = Cycling,
CAS before RAS
ICC5
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CAS = V
.
IH
5/21
¡ Semiconductor
AC Characteristics (1/2)
Parameter
MSM5416258A
(VCC = 5.0 V ±0.5 V, Ta = 0°C to 70°C)
MSM5416258A
-40
MSM5416258A
-45
Symbol
Unit Note
Min.
80
115
15
55
—
—
—
—
—
0
Max.
—
—
—
—
40
10
22
10
22
—
—
8
Min.
90
130
20
60
—
—
—
—
—
0
Max.
—
—
—
—
45
12
24
12
24
—
—
8
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
tRC
tRWC
tHPC
tPRWC
tRAC
tCAC
tAA
ns
ns
ns
Fast Page Mode Read Modify Write Cycle Time
Access Time from RAS
ns
ns 7, 12, 13
ns 7, 12
ns 7, 13
ns
Access Time from CAS
Access Time from Column Address
Access Time from OE
tOEA
tCPA
tCLZ
tCOH
tOFF
Access Time from CAS Precharge
Output Low Impedance Time from CAS
Data Hold After CAS Low
ns 7, 12
ns
3
3
ns
ns
17
8
Output Buffer Turn-off Delay Time
3
3
Output Buffer Turn-off
Delay Time from OE
tOEZ
tREZ
tWEZ
3
1.5
3
8
8
8
3
1.5
3
8
8
8
ns
ns
ns
8
8
8
Output Buffer Turn-off
Delay Time from RAS
Output Buffer Turn-off
Delay Time from WE
Transition Time
tT
2
—
30
40
40
8
35
8
2
—
35
45
45
10
8
35
8
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Refresh Period
tREF
tRP
RAS Precharge Time
—
—
RAS Pulse Width
tRAS
tRASP
tRSH
tROH
tCP
10,000
100,000
—
10,000
100,000
—
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RAS Hold Time Reference to OE
CAS Precharge Time
8
—
—
5
—
6
—
CAS Pulse Width
tCAS
tCSH
tCRP
tRHCP
tRCD
tRAD
tASR
tRAH
tASC
tCAH
tAR
6
10,000
—
7
10,000
—
CAS Hold Time
35
5
35
5
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time from RAS
Column Address to RAS Lead Time
—
—
22
18
13
0
—
24
18
13
0
—
30
30
12
13
18
18
—
—
8
—
8
—
0
—
0
—
6
—
6
—
30
22
—
30
24
—
tRAL
—
—
6/21
¡ Semiconductor
AC Characteristics (2/2)
Parameter
MSM5416258A
(VCC = 5.0 V ±0.5 V, Ta = 0°C to 70°C)
MSM5416258A
-40
MSM5416258A
-45
Symbol
Unit Note
Min.
Max.
—
Min.
Max.
—
Read Command Set-up Time
Read Command Hold Time
tRCS
tRCH
0
0
0
0
ns
—
—
ns
9
9
Read Command Hold Time
Reference to RAS
tRRH
0
—
0
—
ns
WE Pulse Width (DQ Disable)
Write Command Set-up Time
Write Command Hold Time
Write Command Pulse Width
Write Command Hold Time from RAS
OE Command Hold Time
tWEP
tWCS
tWCH
tWP
10
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
6
6
6
6
tWCR
tOEH
tCWL
tRWL
tDZC
tDZO
tDS
30
6
30
7
Write Command to CAS Lead Time
Write Command to RAS Lead Time
Data to CAS Delay Time
6
7
8
9
0
0
Data to OE Delay Time
0
0
Data-in Set-up Time
0
0
10
10
Data-in Hold Time
tDH
6
7
Data-in Hold Time referenced to RAS
OE to Data-in Delay Time
tDHR
tOED
tOCH
tCHO
tOEP
tCWD
tAWD
tRWD
30
8
30
8
OE "L" to CAS "H" Lead Time
CAS "H" to OE "L" Lead Time
Hi-Z Command Pulse Width
CAS to WE Delay Time
10
10
10
22
32
50
10
10
10
22
32
55
11
11
11
Column Address to WE Delay Time
RAS to WE Delay Time
CAS Active Delay Time
from RAS Precharge
tRPC
tCSR
tCHR
0
—
—
—
0
—
—
—
ns
ns
ns
RAS to CAS Set-up Time
(CAS before RAS)
10
10
10
10
RAS to CAS Hold Time
(CAS before RAS)
7/21
¡ Semiconductor
MSM5416258A
Notes: 1. All voltages are referenced to V .
SS
2. This parameter is dependent upon the cycle rate.
3. Thisparameterisdependentupontheoutputloading. Specifiedvaluesareobtained
with the output open.
4. An initial pause of 200 ms is required after power-up, followed by any 8RAScycles.
(Example : RAS-only-refresh) before proper device operation is achieved. In case of
usinginternalrefreshcounter,aminimumof8CASbeforeRAScyclesinsteadof8RAS
cycles are required.
5. The AC characteristics assume t = 5 ns.
T
6. V (Min.) and V (Max.) are reference levels for measuring timing of input signals.
IH
IL
Also, transition times are measured between V and V .
IH
IL
7. Data outputs are measured with a load of 50 pF. DOUT reference levels: V /V
=
OH
OL
2.0V/1.4V. NotethatV isdefinedas1.4VwhenV *pins, pin13andpin32, were
OL
SS
open. ThedataoutputmeasurementsunderV /V =2.0V/0.8Vareguaranteed
OH
OL
when V * pins, pin 13 and pin 32, were connected to GND.
SS
8. t
(Max.), t
(Max.), t
(Max.) and t
(Max.) define the time at which the
REZ
OFF
WEZ
OEZ
outputsachievetheopencircuitconditionandarenotreferencedtooutputvoltage
levels. This parameter is sampled and not 100% tested.
9. Either t
or t
must be satisfied for a read cycle.
RRH
RCH
10. TheseparametersarereferencedtoCASleadingedgeofearlywritecyclesandtoWE
leading edge in OE-controlled write cycles and read-modify-write cycles.
11. t
, t
, t
and t
are not restrictive operating parameters. They are included
WCS RWD CWD
AWD
in the data sheet as electrical characteristics only. If t
≥t
(Min.), the cycle is an
WCS WCS
earlywritecycleandthedataoutpinswillremainopencircuitthroughouttheentire
cycle. If t ≥t (Min.), t ≥t (Min.) and t ≥t (Min.), the cycle is
RWD RWD
CWD CWD
AWD AWD
aread-modify-writecycleandthedataoutwillcontaindatareadfromtheselectedcell.
If neither of the above sets of conditions is satisfied, the condition of the data out is
indeterminate.
12. Operation within the t
(Max.) limit insures that t
(Max.) can be met.
RCD
RAC
t
(Max.) is specified as a reference point only. If t
(Max.) limit, then access time is controlled by t
is greater than the specified
RCD
RCD
t
.
RCD
CAC
13. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
RAD
RAC
t
(Max.) is specified as a reference point only: If t
(Max.) limit, then access time is controlled by t
is greater than the specified
RAD
RAD
t
.
RAD
AA
14. Input levels at the AC testing are 3.0 V/0 V.
15. Addresses (A0 - A8) may be changed two times or less while RAS = V .
IL
16. Addresses (A0 - A8) may be changed once or less while CAS = V and RAS = V .
IH
IL
17. This is guaranteed by design. (t
not 100% tested.
= t
- output transition time). This parameter is
COH
CAC
18. Thisparameterisdependentuponthenumberofaddresstransitions.Specifiedvalues
aremeasuredwithamaximumoftwotransitionsperaddresscycleinFastPageMode.
8/21
¡ Semiconductor
MSM5416258A
TIMING WAVEFORM
Read Cycle (RAS Output Control)
tRC
tRP
tRAS
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
UCAS
LCAS
tAR
tASC
Column
tRAD
tASR tRAH
tRAL
tCAH
Row
A0 - A8
WE
tRCH
tRRH
tRCS
tROH
tOEZ
tOEA
OE
tCAC
tOFF
tAA
High-Z
DQ0 - 7
Valid Data
Valid Data
tRAC
tOFF
High-Z
DQ8 - 15
"H" or "L"
9/21
¡ Semiconductor
MSM5416258A
Read Cycle (CAS Output Control)
tRC
tRP
tRAS
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
UCAS
LCAS
tAR
tASC
Column
tRAD
tRAH
tRAL
tASR
tCAH
Row
A0 - A8
tRCS
tRRH
WE
tROH
tOEZ
tOEA
OE
tCAC
tOFF
tAA
High-Z
DQ0 - 7
Valid Data
Valid Data
tRAC
High-Z
DQ8 - 15
"H" or "L"
10/21
¡ Semiconductor
MSM5416258A
Early Write Cycle (LCAS and UCAS Active)
tRC
tRP
tRAS
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
UCAS
LCAS
tAR
tRAD
tRAL
tASR tRAH
tASC
tCAH
Row
Column
A0 - A8
WE
tCWL
tRWL
tWP
tWCR
tWCS
tWCH
OE
tDHR
tDS
tDH
Valid Data
DQ0 - 7
tDS
tDH
Valid Data
DQ8 - 15
"H" or "L"
11/21
¡ Semiconductor
MSM5416258A
Late Write Cycle (LCAS and UCAS Active)
tRC
tRP
tRAS
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
UCAS
LCAS
tAR
tRAD
tASR tRAH
tRAL
tASC
tCAH
Row
Column
A0 - A8
WE
tCWL
tRWL
tWP
tRCS
tWCR
tOEH
OE
tDS
tDH
Valid Data
DQ0 - 7
tDS
tDH
Valid Data
DQ8 - 15
"H" or "L"
12/21
¡ Semiconductor
MSM5416258A
Read Modify Write Cycle (LCAS and UCAS Active)
tRWC
tRP
tRAS
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
UCAS
LCAS
tAR
tASC
tRAD
tASR tRAH
tRAL
tCAH
Column
Row
A0 - A8
WE
tAWD
tCWL
tRWL
tWP
tRCS
tRWD
tCWD
tDZO
tOEH
tOEA
tOEZ
tOED
tDS
OE
tCAC
tDZC
tDH
Out
Out
In
In
DQ0 - 7
tRAC
tDS
tDH
DQ8 - 15
"H" or "L"
13/21
¡ Semiconductor
MSM5416258A
Fast Page Mode Read Cycle
tRASP
tAR
tRHCP
tRP
RAS
tCRP
tPC
tRSH
tCAS
tCRP
tCP
tRCD
tRAD
tCP
tCAS
tCAS
UCAS
LCAS
tRAL
tCAH
tCSH
tCAH
tASR
Row
tASC
tASC
tCAH
tASC
tRAH
Column
Column
tRCS
Column
tRCS
A0 - A8
tRCH
tRRH
tOFF
tRCS
tRCH
tRCH
WE
tAA
tAA
tAA
tCPA
tOEA
tCPA
tOEA
tOEA
tCAC
OE
tOFF
tCAC
tOFF
tCAC
tRAC
tOEZ
tOEZ
tOEZ
Valid
Data
Valid
Valid
High-Z
High-Z
DQ0 - 7
Data
Data
tCLZ
tCLZ
tCLZ
Valid
Data
Valid
Data
Valid
Data
DQ8 - 15
"H" or "L"
14/21
tRC
tRP
tRASP
tAR
tCSH
RAS
tHPC
tRSH
tCRP
tRCD
tCP
tCP
tCP
tCRP
tCAS
tCAS
tCAS
tCAS
tRAL
UCAS
LCAS
tRAD
tASR tRAH
Row
tASC
tCAH
tASC tCAH
Column
tASC tCAH
Column
tASC tCAH
Column
Column
A0 - A8
WE
tRRH
tRCS
tRCH
tRCS
tRCH
tRAC
tCHO
tOEP
tOCH
tWEP
tOEA
tCAC
tAA
tOEP
tCAC
OE
tCAC
tAA
tCPA
tDOH
tAA
tCAC
tAA
tOEZ
tOEA
tOEZ tOEA
tWEZ
tREZ
Valid
Valid
Valid
High-Z
High-Z
Valid Data
Valid Data
Valid Data
DQ0 - 7
Data
Data
Data
Valid
Data
Valid
Data
Valid
Data
Valid Data
DQ8 - 15
"H" or "L"
¡ Semiconductor
MSM5416258A
Fast Page Mode Early Write Cycle
tRC
tRASP
tRP
RAS
tCSH
tPC
tRSH
tCAS
tCRP
tCP
tRCD
tCP
tCAS
tCAH
tCAS
UCAS
LCAS
tAR
tRAD
tRAL
tCAH
tASR
Row
tASC
tASC
tCAH
tASC
tRAH
Column
tCWL
Column
tCWL
Column
tCWL
A0 - A8
tWCS
tWCS
tWCS
tWCH
tWCH
tWCH
tWP
tWP
tWP
WE
OE
tDH
tDS
Input Data
tDS
tDH
Input Data
tDH
tDS
tDH
tDS
Input Data
tDH
Input Data
tDS
tDH
Input Data
DQ0 - 7
tDS
DQ8 - 15
Input Data
"H" or "L"
16/21
¡ Semiconductor
MSM5416258A
Fast Page Mode Read Modify Write Cycle
tRC
tRASP
tRP
RAS
tCSH
tPRWC
tCAS
tRSH
tCAS
tCRP
tRCD
tCAS
tCP
tCP
UCAS
LCAS
tAR
tRAL
tCAH
tRAD
tCAH
tCAH
tASR tRAH tASC
tASC
tASC
A0 - A8
Row
Column
Column
Column
tCWL
tCWL
tCWL
tAWD
tAWD
tAWD
WE
tCWD
tWP
tCWD
tWP
tCWD
tWP
tRCS
tOEA
tOEA
tOEA
tOEZ
tOEZ
tOEZ
OE
tCAC
tAA
tCAC
tAA
tCAC
tAA
tDH
tDH
tDH
tDS
tDS
tDS
DQ0 - 7
Out
In
Out
In
Out
In
tDH
tDH
tDH
tCAC
tCAC
tCAC
tAA
tDS
tDS
tDS
tAA
tAA
Out
In
Out In
Out
In
DQ8 - 15
"H" or "L"
17/21
¡ Semiconductor
MSM5416258A
CAS before RAS Refresh Cycle
tRC
tRP
tRAS
tRP
RAS
tRPC
tRPC
tCSR
tCHR
UCAS
LCAS
Inhibit Falling Transition
A0 - A8
WE
OE
tOFF
High-Z
High-Z
DQ0 - 7
tOFF
DQ8 - 15
"H" or "L"
18/21
¡ Semiconductor
MSM5416258A
Hidden Refresh Cycle
tRC
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tRSH
tCHR
UCAS
LCAS
tAR
tASC
tRAD
tRAH
tRAL
tCAH
tASR
Row
Column
A0 - A8
tRRH
tRCS
WE
tROH
tOEA
tOEZ
OE
tRAC
tOFF
tCAC
tAA
High-Z
High-Z
DQ0 - 7
Valid Data
Valid Data
tRAC
tCAC
tAA
tOFF
DQ8 - 15
"H" or "L"
19/21
¡ Semiconductor
MSM5416258A
RAS Only Refresh Cycle
tRC
tRAS
tRP
RAS
tRPC
tCRP
UCAS
LCAS
tASR tRAH
Row
A0 - A8
WE
OE
High-Z
DQ0 - 7
High-Z
DQ8 - 15
"H" or "L"
20/21
¡ Semiconductor
PACKAGE DIMENSIONS
TSOPII44/40-P-400-0.80-K
MSM5416258A
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.49 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
21/21
E2Y0002-28-41
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan
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