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MSM51V17800F-70TS-K [OKI]

2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE; 2097152字】 8位动态RAM ：快速页面模式类型
MSM51V17800F-70TS-K
型号： MSM51V17800F-70TS-K
厂家： OKI ELECTRONIC COMPONETS    OKI ELECTRONIC COMPONETS
描述：

2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
2097152字】 8位动态RAM ：快速页面模式类型

存储 内存集成电路 光电二极管 动态存储器
文件： 总15页 (文件大小：210K)
中文：  中文翻译
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FEDD51V17800F-01  
This version: January. 2001  
Previous version :  
1
Semiconductor  
MSM51V17800F  
2,097,152-Word × 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE  
DESCRIPTION  
The MSM51V17800F is a 2,097,152-word × 8-bit dynamic RAM fabricated in Oki’s silicon-gate  
CMOS technology. The MSM51V17800F achieves high integration, high-speed operation, and low-  
power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer  
metal CMOS process. The MSM51V17800F is available in a 28-pin plastic SOJ or 28-pin plastic TSOP.  
FEATURES  
∙ 2,097,152-word × 8-bit configuration  
∙ Single 3.3V power supply, ±0.3V tolerance  
∙ Input : LVTTL compatible, low input capacitance  
∙ Output : LVTTL compatible, 3-state  
∙ Refresh : 2048 cycles/32ms  
∙ Fast page mode, read modify write capability  
∙ CAS before RAS refresh, hidden refresh, RAS-only refresh capability  
∙ Packages  
28-pin 400mil plastic SOJ  
28-pin 400mil plastic TSOP  
(SOJ28-P-400-1.27)  
(TSOPII28-P-400-1.27-K)  
(Product : MSM51V17800F-xxJS)  
(Product : MSM51V17800F-xxTS-K)  
xx indicates speed rank.  
PRODUCT FAMILY  
Access Time (Max.)  
Power Dissipation  
Cycle Time  
(Min.)  
Family  
Operating  
(Max.)  
Standby  
(Max.)  
t
t
t
t
OEA  
RAC  
AA  
CAC  
50ns  
25ns  
30ns  
35ns  
13ns  
15ns  
20ns  
13ns  
15ns  
20ns  
90ns  
110ns  
130ns  
360mW  
324mW  
288mW  
MSM51V17800F  
60ns  
70ns  
1.8mW  
1/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
PIN CONFIGURATION (TOP VIEW)  
VCC  
1
28 VSS  
27 DQ8  
26 DQ7  
25 DQ6  
24 DQ5  
23 CAS  
22 OE  
21 A9  
VCC  
1
28 VSS  
DQ1 2  
DQ2 3  
DQ3 4  
DQ4 5  
WE 6  
RAS 7  
NC 8  
DQ1 2  
DQ2 3  
DQ3 4  
DQ4 5  
WE 6  
RAS 7  
NC 8  
27 DQ8  
26 DQ7  
25 DQ6  
24 DQ5  
23 CAS  
22 OE  
21 A9  
A10R 9  
A0 10  
20 A8  
A10R 9  
A0 10  
20 A8  
19 A7  
19 A7  
A1 11  
18 A6  
A1 11  
18 A6  
A2 12  
17 A5  
A2 12  
17 A5  
A3 13  
16 A4  
A3 13  
16 A4  
VCC 14  
15 VSS  
VCC 14  
15 VSS  
28-Pin Plastic TSOP  
(K Type)  
28-Pin Plastic SOJ  
Pin Name  
Function  
A0–A9, A10R  
Address Input  
Row Address Strobe  
Column Address Strobe  
Data Input/Data Output  
Output Enable  
RAS  
CAS  
DQ1–DQ8  
OE  
WE  
Write Enable  
VCC  
Power Supply (3.3V)  
Ground (0V)  
VSS  
NC  
No Connection  
Note : The same power supply voltage must be provided to every V pin, and the same GND voltage level must  
CC  
be provided to every V pin.  
SS  
2/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
BLOCK DIAGRAM  
Timing  
Generator  
WE  
OE  
RAS  
CAS  
I/O  
Controller  
Output  
Buffers  
8
8
8
DQ1 – DQ8  
Column  
Address  
Buffers  
10  
Column Decoders  
Sense Amplifiers  
Input  
Buffers  
8
I/O  
Selector  
Internal  
Address  
Counter  
8
8
Refresh  
Control Clock  
A0– A9  
10  
1
Row  
Address  
Buffers  
Row  
Deco-  
ders  
11  
Word  
Drivers  
Memory  
Cells  
A10R  
VCC  
On Chip  
VBB Generator  
On Chip  
IVCC Generator  
VSS  
3/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
ELECTRICAL CHARACTERISTICS  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Voltage VCC Supply relative to VSS  
Short Circuit Output Current  
Power Dissipation  
Symbol  
VT  
Value  
–0.5 to 4.6  
50  
Unit  
V
IOS  
mA  
W
PD*  
1
Operating Temperature  
Storage Temperature  
Topr  
0 to 70  
–55 to 150  
°C  
°C  
Tstg  
*: Ta = 25°C  
RECOMMENDED OPERATING CONDITIONS  
(Ta = 0 to 70°C)  
Parameter  
Symbol  
VCC  
VSS  
Min.  
3.0  
Typ.  
3.3  
0
Max.  
Unit  
V
3.6  
0
Power Supply Voltage  
0
V
Input High Voltage  
Input Low Voltage  
VIH  
2.0  
VCC + 0.3*1  
0.8  
V
VIL  
− 0.3*2  
V
Notes: *1. The input voltage is V + 1.0V when the pulse width is less than 20ns (the pulse width is with respect  
CC  
to the point at which V is applied).  
CC  
*2. The input voltage is V − 1.0V when the pulse width is less than 20ns (the pulse width respect to the  
SS  
point at which V is applied).  
SS  
PIN CAPACITANCE  
(Vcc = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz)  
Parameter  
Symbol  
CIN1  
Min.  
—
Max.  
5
Unit  
pF  
Input Capacitance (A0 – A9, A10R)  
Input Capacitance  
CIN2  
CI/O  
—
—
7
7
pF  
pF  
(RAS, CAS, WE, OE)  
Output Capacitance (DQ1 – DQ8)  
4/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
DC CHARACTERISTICS  
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C)  
MSM51V17800 MSM51V17800 MSM51V17800  
F-50 F-60 F-70  
Parameter  
Symbol  
Condition  
Unit Note  
Min. Max. Min. Max. Min. Max.  
Output High Voltage  
Output Low Voltage  
V
I
I
= −2.0mA  
2.4  
0
V
2.4  
0
V
2.4  
0
V
CC  
V
V
OH  
OH  
OL  
CC  
CC  
V
= 2.0mA  
0.4  
0.4  
0.4  
OL  
0V ≤ V ≤ VCC + 0.3V;  
I
Input Leakage  
Current  
I
− 10  
− 10  
10  
− 10  
− 10  
10  
− 10  
− 10  
10  
µA  
µA  
All other pins not  
under test = 0V  
LI  
DQ disable  
Output Leakage  
Current  
I
10  
10  
90  
10  
80  
LO  
0V ≤ V ≤ V  
CC  
O
Average Power  
Supply Current  
RAS, CAS cycling,  
= Min.  
I
I
100  
mA 1,2  
mA  
CC1  
CC2  
t
RC  
(Operating)  
RAS, CAS = V  
RAS, CAS  
2
2
2
Power Supply  
Current  
IH  
1
0.5  
0.5  
0.5  
µA  
(Standby)  
≥ V  
− 0.2V  
CC  
RAS cycling,  
Average Power  
Supply Current  
I
I
100  
5
90  
5
80  
5
mA 1,2  
CAS = V  
,
,
CC3  
CC5  
IH  
(RAS-only Refresh)  
t
= Min.  
RC  
RAS = V  
Power Supply  
Current  
IH  
mA  
1
CAS = V ,  
IL  
(Standby)  
DQ = enable  
Average Power  
Supply Current  
RAS = cycling,  
CAS before RAS  
I
I
100  
75  
90  
70  
80  
65  
mA 1,2  
mA 1,3  
CC6  
CC7  
(CAS before RAS  
Refresh)  
RAS = V ,  
Average Power  
Supply Current  
IL  
CAS cycling,  
(Fast Page Mode)  
t
= Min.  
PC  
Notes: 1. I Max. is specified as I for output open condition.  
CC  
CC  
2. The address can be changed once or less while RAS = V .  
IL  
3. The address can be changed once or less while CAS = V .  
IH  
5/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
AC CHARACTERISTICS (1/2)  
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3  
MSM51V17800 MSM51V17800 MSM51V17800  
F-50 F-60 F-70  
Parameter  
Symbol  
Unit Note  
Min.  
90  
Max. Max. Max.  
Min.  
110  
155  
40  
Min.  
130  
185  
45  
Random Read or Write Cycle Time  
Read Modify Write Cycle Time  
Fast Page Mode Cycle Time  
t
ns  
ns  
ns  
RC  
t
131  
35  
RWC  
t
PC  
Fast Page Mode Read Modify Write  
Cycle Time  
t
76  
85  
100  
ns  
PRWC  
Access Time from RAS  
t
50  
13  
25  
30  
13  
60  
15  
30  
35  
15  
70  
20  
35  
40  
20  
ns 4, 5, 6  
RAC  
Access Time from CAS  
t
ns  
ns  
4, 5  
4, 6  
CAC  
Access Time from Column Address  
Access Time from CAS Precharge  
Access Time from OE  
t
AA  
t
t
ns 4, 12  
CPA  
ns  
ns  
4
4
OEA  
Output Low Impedance Time from  
CAS  
t
0
0
0
0
0
0
CLZ  
OFF  
OEZ  
CAS to Data Output Buffer Turn-  
off Delay Time  
t
13  
13  
15  
15  
20  
20  
ns  
ns  
7
OE to Data Output Buffer Turn-off  
Delay Time  
t
0
3
0
3
0
3
7
3
Transition Time  
t
50  
32  
50  
32  
50  
32  
ns  
ms  
ns  
T
Refresh Period  
t
t
REF  
RAS Precharge Time  
RAS Pulse Width  
t
30  
50  
50  
13  
13  
40  
60  
60  
15  
15  
50  
70  
70  
20  
20  
RP  
10,000  
10,000  
10,000 ns  
RAS  
RAS Pulse Width (Fast Page Mode)  
RAS Hold Time  
t
100,000  
100,000  
100,000 ns  
RASP  
t
ns  
ns  
RSH  
RAS Hold Time referenced to OE  
t
ROH  
CAS Precharge Time  
(Fast Page Mode)  
t
7
10  
10  
ns  
CP  
CAS Pulse Width  
t
t
13  
50  
5
10,000  
15  
60  
5
10,000  
20  
70  
5
10,000 ns  
CAS  
CAS Hold Time  
ns  
ns  
ns  
CSH  
CRP  
CAS to RAS Precharge Time  
t
RAS Hold Time from CAS Precharge t  
RAS to CAS Delay Time  
30  
17  
12  
0
35  
20  
15  
0
40  
20  
15  
0
RHCP  
t
37  
25  
45  
30  
50  
35  
ns  
ns  
ns  
5
6
RCD  
RAS to Column Address Delay Time  
Row Address Set-up Time  
t
RAD  
t
ASR  
6/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
AC CHARACTERISTICS (2/2)  
(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3  
MSM51V17800 MSM51V17800 MSM51V17800  
F-50 F-60 F-70  
Parameter  
Symbol  
Unit Note  
Min.  
7
Max. Max. Max.  
Min.  
10  
0
Min.  
10  
0
Row Address Hold Time  
t
ns  
ns  
ns  
ns  
ns  
RAH  
Column Address Set-up Time  
Column Address Hold Time  
Column Address to RAS Lead Time  
Read Command Set-up Time  
Read Command Hold Time  
t
0
ASC  
CAH  
t
7
10  
30  
0
15  
35  
0
t
25  
0
RAL  
RCS  
RCH  
t
t
0
0
0
ns  
ns  
8
8
9
Read Command Hold Time  
referenced to RAS  
t
0
0
0
RRH  
Write Command Set-up Time  
Write Command Hold Time  
Write Command Pulse Width  
OE Command Hold Time  
t
0
0
0
15  
10  
20  
20  
20  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WCS  
t
7
10  
10  
15  
15  
15  
0
WCH  
t
7
WP  
t
13  
13  
13  
0
OEH  
RWL  
CWL  
Write Command to RAS Lead Time  
Write Command to CAS Lead Time  
Data-in Set-up Time  
t
t
t
10  
10  
DS  
DH  
Data-in Hold Time  
t
7
10  
15  
40  
55  
85  
60  
15  
20  
50  
65  
100  
70  
OE to Data-in Delay Time  
CAS to WE Delay Time  
t
t
13  
36  
48  
73  
53  
OED  
9
9
9
9
CWD  
Column Address to WE Delay Time  
RAS to WE Delay Time  
t
AWD  
RWD  
t
CAS Precharge WE Delay Time  
t
CPWD  
CAS Active Delay Time from RAS  
t
t
t
5
5
5
ns  
ns  
ns  
ns  
ns  
RPC  
CSR  
CHR  
Precharge  
RAS to CAS Set-up Time  
(CAS before RAS)  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
RAS to CAS Hold Time  
(CAS before RAS)  
WE to RAS Precharge Time  
(CAS before RAS)  
t
WRP  
WRH  
WE Hold Time from RAS  
(CAS before RAS)  
t
RAS to WE Set-up Time  
RAS to WE Hold Time  
t
t
10  
10  
10  
10  
10  
10  
ns  
ns  
WTS  
WTH  
7/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization  
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.  
2. The AC characteristics assume tT = 5ns.  
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT)  
are measured between VIH and VIL.  
4. -50 is measured with a load circuit equivalent to 1 TTL load and 50pF, and -60/-70 is measured with a  
load circuit equivalent to 1 TTL load and 100pF.  
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.  
t
RCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit,  
then the access time is controlled by tCAC  
.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.  
t
RAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit,  
then the access time is controlled by tAA.  
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and  
are not referenced to output voltage levels.  
8. tRCH or tRRH must be satisfied for a read cycle.  
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data  
sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and  
the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD  
(Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify  
write cycle and data out will contain data read from the selected cell; if neither of the above sets of  
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.  
10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE  
leading edge in an OE control write cycle, or a read modify write cycle.  
8/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
TIMING CHART  
Read Cycle  
tRC  
tRAS  
VIH  
RAS  
tRP  
VIL  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH  
CAS  
tRAD  
tASR tRAH  
VIL  
tRAL  
tASC  
tCAH  
VIH  
Address  
VIL  
Row  
Column  
tRCS  
tRRH  
VIH  
WE  
tAA  
tRCH  
VIL  
tROH  
tOEA  
VIH  
OE  
VIL  
tCAC  
tOFF  
tRAC  
tOEZ  
tCLZ  
VOH  
DQ  
Valid Data-out  
Open  
VOL  
“H” or “L”  
Write Cycle (Early Write)  
tRC  
tRAS  
VIH  
RAS  
tRP  
tCRP  
VIL  
tCSH  
tCRP  
tRCD  
tRSH  
tCAS  
VIH  
CAS  
tRAD  
VIL  
tRAL  
tRAH  
tASR  
tASC  
tCAH  
VIH  
Address  
Row  
Column  
VIL  
tCWL  
tWCH  
tWCS  
tWP  
VIH  
VIL  
WE  
OE  
DQ  
tRWL  
VIH  
VIL  
tDS  
tDH  
VIH  
VIL  
Valid Data-in  
Open  
“H” or “L”  
9/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
Read Modify Write Cycle  
tRWC  
tRAS  
VIH  
RAS  
tRP  
VIL  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH  
CAS  
tRAD  
tASR tRAH  
VIL  
tCWL  
tRWL  
tASC  
tCAH  
VIH  
VIL  
Row  
Colum  
tRCS  
Address  
tCWD  
tWP  
tRWD  
VIH  
VIL  
WE  
OE  
tAWD  
tAA  
tOEH  
tOEA  
VIH  
VIL  
tOED  
tOEZ  
tCAC  
tDH  
tRAC  
tDS  
tCLZ  
VI/OH  
VI/OL  
Valid  
Data-out  
Valid  
Data-in  
DQ  
“H” or “L”  
10/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
Fast Page Mode Read Cycle  
tRASP  
tRP  
tPC  
tRHCP  
VIH  
RAS  
VIL  
tRCD  
tCP  
tCP  
tRSH  
tCAS  
tCRP  
tCRP  
tCAS  
tCAS  
VIH  
CAS  
tRAD  
tCSH  
tRAH  
VIL  
tRAL  
tASC  
tASR  
tASC  
tCAH  
tCAH  
tASC  
tCAH  
VIH  
Address  
WE  
Row  
Column  
Column  
tRCS  
Column  
tRCS  
VIL  
tRCS  
tRCH  
tRCH  
tRCH  
VIH  
VIL  
tAA  
tAA  
tAA  
tRRH  
tOEA  
tOEA  
tOEA  
VIH  
VIL  
OE  
tCPA  
tOFF  
tOEZ  
tCPA  
tOFF  
tRAC  
tOFF  
tCAC  
tCLZ  
tCAC  
tCLZ  
tCAC  
tOEZ  
tOEZ  
tCLZ  
VOH  
VOL  
Valid  
Data-out  
Valid  
Data-out  
Valid  
Data-out  
DQ  
“H” or “L”  
Fast Page Mode Write Cycle (Early Write)  
tRP  
tRASP  
tRHPC  
tPC  
VIH  
RAS  
VIL  
tCRP  
tCRP  
tCP  
tCP  
tRSH  
tCAS  
tRCD  
tCAS  
tCAS  
VIH  
CAS  
tRAD  
VIL  
tCSH  
tCAH  
tRAL  
tCAH  
tASR  
tASC  
tASC  
tCAH  
tRAH  
tASC  
VIH  
VIL  
Row  
Column  
Column  
Column  
tRWL  
tCWL  
Address  
tCWL  
tWCH  
tWP  
tCWL  
tWCH  
tWP  
tWCS  
tWCS  
tWCS  
tWCH  
tWP  
VIH  
VIL  
WE  
tDS  
tDH  
tDS  
tDH  
tDS  
tDH  
VIH  
VIL  
Valid *  
Data-in  
Valid *  
Data-in  
Valid *  
Data-in  
DQ  
Note: OE = “H” or “L”  
“H” or “L”  
11/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
Fast Page Mode Read Modify Write Cycle  
tRASP  
tRP  
tCSH  
tPRWC  
tRSH  
VIH  
RAS  
VIL  
tCP  
tCP  
tCRP  
tRCD  
tCAS  
tCAS  
tCAH  
tCAS  
tCAH  
VIH  
VIL  
CAS  
tRAD  
tASC  
tRAH  
tASR  
tCAH  
tCWL  
tASC  
tASC  
tRAL  
tCWL  
VIH  
VIL  
Row  
Column  
Column  
tRCS  
Column  
tRCS  
Address  
tCWL  
tPWD  
tCWD  
tCPWD  
tCPWD  
tCWD  
tRWL  
tCWD  
tRCS  
VIH  
VIL  
WE  
tAWD  
tAWD  
tAWD  
tWP  
tWP  
tWP  
tDH  
tCPA  
tAA  
tRAC  
tAA  
tROH  
tCPA  
tDH  
tDS  
tDH  
tDS  
tAA  
tOEA  
tOEA  
tOEA  
VIH  
VIL  
tOED  
tOEZ  
OE  
tOED  
tOEZ  
tOED  
tOEZ  
tCAC  
tCAC  
tCAC  
tDS  
VI/OH  
VI/OL  
DQ  
Out  
Out  
In  
Out  
In  
In  
tCLZ  
tCLZ  
tCLZ  
Note: In = Valid Data-in, Out = Valid Data-out  
“H” or “L”  
RAS-only Refresh Cycle  
tRC  
tRAS  
VIH  
RAS  
tRP  
VIL  
tCRP  
tRPC  
VIH  
VIL  
CAS  
Address  
DQ  
tASR tRAH  
VIH  
VIL  
Row  
tOFF  
VOH  
VOL  
Open  
Note: WE, OE = “H” or “L”  
“H” or “L”  
12/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
CAS before RAS Refresh Cycle  
tRP  
tRC  
tRAS  
VIH  
RAS  
tRPC  
tCP  
tRP  
VIL  
tCSR  
tRPC  
tCHR  
VIH  
CAS  
VIL  
tWRP  
tWRH  
tWRP  
VIH  
WE  
VIL  
tCEZ  
VOH  
VOL  
DQ  
Open  
“H” or “L”  
Note: OE, Address = “H” or “L”  
Hidden Refresh Read Cycle  
tRC  
tRC  
tRAS  
tRAS  
VIH  
RAS  
VIL  
tCRP  
tRCD  
tRSH  
tRP  
tRP  
tCHR  
VIH  
CAS  
tRAD  
tRAH  
VIL  
tASR  
tASC  
tCAH  
VIH  
Address  
Row  
Column  
VIL  
tRCS  
tCAC  
tRAL  
tRRH  
VIH  
VIL  
WE  
tREZ  
tAA  
tROH  
tOEA  
tWRP tWRH  
tCEZ  
VIH  
VIL  
OE  
tRAC  
tOEZ  
tCLZ  
VOH  
VOL  
DQ  
Open  
Valid Data-out  
“H” or “L”  
13/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
Hidden Refresh Write Cycle  
tRC  
tRC  
tRAS  
tRAS  
VIH  
RAS  
VIL  
tRP  
tCRP  
tRCD  
tRSH  
tRP  
tCHR  
VIH  
CAS  
tRAD  
tRAH  
VIL  
tCAH  
tASR  
tASC  
VIH  
VIL  
Address  
Row  
Column  
tRAL  
tRWL  
tWP  
VIH  
VIL  
WE  
OE  
DQ  
tWCH  
tWRP tWRH  
tWCS  
VIH  
VIL  
tDS  
tDH  
Valid Data-in  
VIH  
VIL  
“H” or “L”  
14/15  
FEDD51V17800F-01  
1
Semiconductor  
MSM51V17800F  
NOTICE  
1. The information contained herein can change without notice owing to product and/or technical improvements.  
Before using the product, please make sure that the information being referred to is up-to-date.  
2. The outline of action and examples for application circuits described herein have been chosen as an explanation  
for the standard action and performance of the product. When planning to use the product, please ensure that  
the external conditions are reflected in the actual circuit, assembly, and program designs.  
3. When designing your product, please use our product below the specified maximum ratings and within the  
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating  
temperature.  
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or  
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration  
or accident, improper handling, or unusual physical or electrical stress including, but not  
limited to, exposure to parameters beyond the specified maximum ratings or operation  
outside the specified operating range.  
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted  
by us in connection with the use of the product and/or the information and drawings contained herein. No  
responsibility is assumed by us for any infringement of a third party’s right which may result from the use  
thereof.  
6. The products listed in this document are intended for use in general electronics equipment for commercial  
applications (e.g., office automation, communication equipment, measurement equipment, consumer  
electronics, etc.). These products are not authorized for use in any system or application that requires special or  
enhanced quality and reliability characteristics nor in any system or application where the failure of such  
system or application may result in the loss or damage of property, or death or injury to humans.  
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace  
equipment, nuclear power control, medical equipment, and life-support systems.  
7. Certain products in this document may need government approval before they can be exported to particular  
countries. The purchaser assumes the responsibility of determining the legality of export of these products and  
will take appropriate and necessary steps at their own expense for these.  
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.  
Copyright 2000 Oki Electric Industry Co., Ltd.  
15/15  

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