MSM51V16800DSL-60 [OKI]
2,097,152-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE; 2,097,152字×8位动态RAM ：快速页面模式类型
| 型号： | MSM51V16800DSL-60 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 2,097,152-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| 文件： | 总17页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2G0126-17-61
Preliminary
This version: Mar. 1998
¡ Semiconductor
MSM51V16800D/DSL
2,097,152-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
TheMSM51V16800D/DSLisa2,097,152-word¥8-bitdynamicRAMfabricatedinOki'ssilicon-gate
CMOS technology. The MSM51V16800D/DSL achieves high integration, high-speed operation,
andlow-powerconsumptionbecauseOkimanufacturesthedeviceinaquadruple-layerpolysilicon/
double-layer metal CMOS process. The MSM51V16800D/DSL is available in a 28-pin plastic SOJ or
28-pin plastic TSOP. The MSM51V16800DSL (the self-refresh version) is specially designed for
lower-power applications.
FEATURES
• 2,097,152-word ¥ 8-bit configuration
• Single 3.3 V power supply, ±0.3 V tolerance
• Input
: LVTTL compatible, low input capacitance
• Output : LVTTL compatible, 3-state
• Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version)
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• CAS before RAS self-refresh capability (SL version)
• Multi-bit test mode capability
• Package options:
28-pin 400 mil plastic SOJ
28-pin 400 mil plastic TSOP
(SOJ28-P-400-1.27)
(TSOPII28-P-400-1.27-K) (Product : MSM51V16800D/DSL-xxTS-K)
(Product : MSM51V16800D/DSL-xxJS)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Cycle Time
(Min.)
Power Dissipation
Family
tRAC tAA tCAC tOEA
50 ns 25 ns 13 ns 13 ns
60 ns 30 ns 15 ns 15 ns
70 ns 35 ns 20 ns 20 ns
Standby (Max.)
Operating (Max.)
MSM51V16800D/DSL-50
MSM51V16800D/DSL-60
MSM51V16800D/DSL-70
90 ns
110 ns
130 ns
270 mW
252 mW
234 mW
1.8 mW/
0.72 mW (SL version)
1/17
¡ Semiconductor
MSM51V16800D/DSL
PIN CONFIGURATION (TOP VIEW)
VCC
1
28 VSS
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23 CAS
22 OE
VCC
1
28 VSS
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE 6
DQ1 2
DQ2 3
DQ3 4
DQ4 5
WE 6
27 DQ8
26 DQ7
25 DQ6
24 DQ5
23 CAS
22 OE
21 A9R
20 A8
RAS 7
A11R 8
A10R 9
A0 10
RAS 7
21 A9R A11R 8
20 A8
19 A7
18 A6
17 A5
16 A4
15 VSS
A10R 9
A0 10
A1 11
A2 12
A3 13
VCC 14
19 A7
A1 11
18 A6
A2 12
17 A5
A3 13
16 A4
VCC 14
15 VSS
28-Pin Plastic SOJ
28-Pin Plastic TSOP
(K Type)
Pin Name
A0 - A8,
A9R - A11R
RAS
Function
Address Input
Row Address Strobe
Column Address Strobe
Data Input/Data Output
Output Enable
CAS
DQ1 - DQ8
OE
WE
Write Enable
VCC
Power Supply (3.3 V)
Ground (0 V)
VSS
Note :
The same power supply voltage must be provided to every V pin, and the same GND
CC
voltage level must be provided to every V pin.
SS
2/17
¡ Semiconductor
MSM51V16800D/DSL
BLOCK DIAGRAM
WE
OE
Timing
Generator
RAS
I/O
Controller
Output
8
8
Buffers
CAS
DQ1 - DQ8
Input
Column
Address
Buffers
Column Decoders
9
9
8
8
Buffers
I/O
Selector
Internal
Address
Counter
Sense Amplifiers
8
8
Refresh
Control Clock
A0 - A8
9
3
Row
Address
Buffers
Row
Memory
Cells
12
Deco-
Word
Drivers
ders
A9R - A11R
VCC
On Chip
V
Generator
BB
VSS
3/17
¡ Semiconductor
MSM51V16800D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Rating
–0.5 to 4.6
50
Unit
V
IOS
mA
W
PD
*
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Symbol
VCC
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Unit
V
V
V
V
VSS
0
Input High Voltage
Input Low Voltage
VIH
2.0
–0.3
—
VCC + 0.3
0.8
VIL
—
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25°C, f = 1 MHꢀ)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance
(A0 - A8, A9R - A11R)
CIN1
—
5
pF
Input Capacitance (RAS, CAS, WE, OE)
CIN2
CI/O
—
—
7
7
pF
pF
Output Capacitance (DQ1 - DQ8)
4/17
¡ Semiconductor
MSM51V16800D/DSL
DC Characteristics
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C)
MSM51V16800MSM51V16800MSM51V16800
D/DSL-50 D/DSL-60 D/DSL-70
Parameter
Symbol
Condition
Unit Note
Min. Max. Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
VOH IOH = –2.0 mA
VOL IOL = 2.0 mA
0 V £ VI £ VCC + 0.3 V;
ILI All other pins not
under test = 0 V
2.4
0
VCC
0.4
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
Input Leakage Current
–10
–10
—
10
10
75
–10
–10
—
10
10
70
–10
–10
—
10
10
65
mA
DQ disable
Output Leakage Current ILO
Average Power
mA
0 V £ VO £ VCC
RAS, CAS cycling,
Supply Current
(Operating)
ICC1
mA 1, 2
tRC = Min.
RAS, CAS = VIH
—
—
—
2
—
—
—
2
—
—
—
2
Power Supply
mA
1
ICC2 RAS, CAS
≥ VCC –0.2 V
RAS cycling,
ICC3 CAS = VIH,
tRC = Min.
0.5
200
0.5
200
0.5
200
Current (Standby)
mA 1, 5
Average Power
Supply Current
—
—
—
—
—
75
5
—
—
—
—
—
70
5
—
—
—
—
—
65
5
mA 1, 2
(RAS-only Refresh)
RAS = VIH,
Power Supply
ICC5 CAS = VIL,
DQ = enable
mA
1
Current (Standby)
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
Supply Current
(Battery Backup)
Average Power
Supply Current
(CAS before RAS
Self-Refresh)
RAS cycling,
ICC6
75
70
400
70
65
400
65
60
400
mA 1, 2
mA 1, 3
CAS before RAS
RAS = VIL,
ICC7 CAS cycling,
tPC = Min.
tRC = 31.3 ms,
1, 4,
ICC10 CAS before RAS,
tRAS £ 1 ms
mA
5
RAS £ 0.2 V,
ICCS
—
300
—
300
—
300
mA 1, 5
CAS £ 0.2 V
Notes : 1. I Max. is specified as I for output open condition.
CC
CC
2. The address can be changed once or less while RAS = V .
IL
3. The address can be changed once or less while CAS = V
.
IH
4. V – 0.2 V £ V £ V + 0.3 V, –0.3 V £ V £ 0.2 V.
CC
IH
CC
IL
5. SL version.
5/17
¡ Semiconductor
MSM51V16800D/DSL
AC Characteristics (1/2)
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
MSM51V16800MSM51V16800MSM51V16800
D/DSL-50
D/DSL-60
D/DSL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
tRC
tRWC
tPC
90
131
35
—
—
—
110
155
40
—
—
—
130
185
45
—
—
—
ns
ns
ns
Fast Page Mode Read Modify Write
Cycle Time
tPRWC
76
—
85
—
100
—
ns
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
tRAC
tCAC
tAA
—
—
—
—
50
13
25
30
—
—
—
—
60
15
30
35
—
—
—
—
70
20
35
40
ns 4, 5, 6
ns
ns
ns
4, 5
4, 6
4
tCPA
Access Time from OE
Output Low Impedance Time from CAS
tOEA
tCLZ
—
0
13
—
13
13
50
64
128
—
—
0
15
—
15
15
50
64
128
—
—
0
20
—
20
20
50
64
128
—
ns
ns
ns
ns
ns
ms
ms
ns
4
4
7
7
3
CAS to Data Output Buffer Turn-off Delay Time tOFF
OE to Data Output Buffer Turn-off Delay Time
Transition Time
0
0
0
tOEZ
tT
tREF
tREF
tRP
0
3
—
—
30
0
3
—
—
40
0
3
—
—
50
Refresh Period
Refresh Period (SL version)
RAS Precharge Time
13
RAS Pulse Width
tRAS
50 10,000 60 10,000 70 10,000 ns
50 100,000 60 100,000 70 100,000 ns
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RAS Hold Time referenced to OE
CAS Precharge Time (Fast Page Mode)
CAS Pulse Width
tRASP
tRSH
tROH
tCP
13
13
7
—
—
—
15
15
10
—
—
—
20
20
10
—
—
—
ns
ns
ns
tCAS
tCSH
tCRP
tRHCP
tRCD
tRAD
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
13 10,000 15 10,000 20 10,000 ns
CAS Hold Time
50
5
—
—
—
37
25
—
—
—
—
—
—
—
—
60
5
—
—
—
45
30
—
—
—
—
—
—
—
—
70
5
—
—
—
50
35
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
30
17
12
0
35
20
15
0
40
20
15
0
5
6
7
10
0
10
0
Column Address Set-up Time
Column Address Hold Time
Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
0
7
10
30
0
15
35
0
25
0
0
0
0
8
8
Read Command Hold Time referenced to RAS tRRH
0
0
0
6/17
¡ Semiconductor
MSM51V16800D/DSL
AC Characteristics (2/2)
(VCC = 3.3 V 0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
MSM51V16800MSM51V16800MSM51V16800
D/DSL-50
D/DSL-60
D/DSL-70
Parameter
Symbol
Unit Note
Min. Max. Min. Max. Min. Max.
Write Command Set-up Time
Write Command Hold Time
tWCS
tWCH
0
7
—
—
0
—
—
0
—
—
ns
ns
9
10
15
Write Command Pulse Width
OE Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
tWP
tOEH
tRWL
tCWL
7
—
—
—
—
10
15
15
15
—
—
—
—
10
20
20
20
—
—
—
—
ns
ns
ns
ns
13
13
13
Data-in Set-up Time
tDS
tDH
tOED
tCWD
tAWD
tRWD
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
15
20
50
65
100
70
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
Data-in Hold Time
OE to Data-in Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to WE Delay Time
7
10
15
40
55
85
60
5
13
36
48
73
9
9
9
9
CAS Precharge WE Delay Time
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS) tCSR
RAS to CAS Hold Time (CAS before RAS) tCHR
WE to RAS Precharge Time (CAS before RAS) tWRP
WE Hold Time from RAS (CAS before RAS) tWRH
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
RAS Pulse Width
tCPWD 53
tRPC
5
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
tWTS
tWTH
tRASS 100
—
—
—
100
110
–50
—
—
—
100
130
–50
—
—
—
ms
ns
ns
13
13
13
(CAS before RAS Self-Refresh)
RAS Precharge Time
tRPS
tCHS
90
(CAS before RAS Self-Refresh)
CAS Hold Time
–50
(CAS before RAS Self-Refresh)
7/17
¡ Semiconductor
MSM51V16800D/DSL
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume t = 5 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.
IH
IL
Transition times (t ) are measured between V and V .
T
IH
IL
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.
The output timing reference levels are V = 2.0 V and V = 0.8 V.
OH
OL
5. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
is greater than the specified
RCD
RAC
t
(Max.) is specified as a reference point only. If t
RCD
RCD
t
(Max.) limit, then the access time is controlled by t
.
RCD
CAC
6. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
is greater than the specified
RAD
RAC
t
(Max.) is specified as a reference point only. If t
RAD
RAD
t
(Max.) limit, then the access time is controlled by t
.
RAD
AA
7. t
(Max.) and t
(Max.) define the time at which the output achieves the open
OFF
OEZ
circuit condition and are not referenced to output voltage levels.
8. t
9. t
or t
must be satisfied for a read cycle.
RCH
RRH
, t
, t
, t
and t
are not restrictive operating parameters. They are
WCS CWD RWD AWD
CPWD
included in the data sheet as electrical characteristics only. If t
≥t
(Min.), then
WCS WCS
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If t ≥ t (Min.) , t ≥ t (Min.),
CWD
CWD
RWD
RWD
t
≥ t
(Min.) and t
≥ t
(Min.), then the cycle is a read modify write
AWD
AWD
CPWD
CPWD
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is a 2-bit parallel test function. CA8 is not
used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high
level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specifiedvalue.Theseparametersshouldbespecifiedintestmodecyclebyaddingthe
above value to the specified value in this data sheet.
13. Only SL version.
8/17
E2G0101-17-41N
¡ Semiconductor
MSM51V16800D/DSL
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
tCRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
CAS
tRAD
tASC
tASR
Row
tRAH
tRAL
tCAH
Column
VIH
VIL
–
–
Address
tRCH
tRCS
tRRH
VIH
VIL
–
–
tAA
WE
OE
tROH
tOEA
VIH
VIL
–
–
tOFF
tCAC
tRAC
tOEZ
VOH
VOL
–
–
DQ
Open
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
VIH
VIL
–
–
tCRP
RAS
CAS
tCSH
tCRP
tRCD
tRAD
tRAH
tASC
tRSH
tCAS
VIH
VIL
–
–
tRAL
tASR
Row
tCAH
Column
tWCH
VIH
VIL
–
–
Address
tWCS
tCWL
VIH
VIL
–
–
tWP
WE
tRWL
VIH
VIL
–
–
OE
tDS
tDH
VIH
VIL
–
–
DQ
Open
Valid Data-in
"H" or "L"
9/17
¡ Semiconductor
MSM51V16800D/DSL
Read Modify Write Cycle
tRWC
tRAS
tRP
VIH
VIL
–
–
RAS
CAS
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
VIL
–
–
tRAH
tASC
tASR
tCAH
Column
VIH
VIL
–
–
Row
Address
tCWL
tRWL
tWP
tCWD
tAWD
tRAD
tRWD
tOEA
VIH
VIL
–
–
tAA
WE
OE
tRCS
VIH
VIL
–
–
tOED
tOEZ
tOEH
tDH
tCAC
tDS
tRAC
VI/OH
–
Valid
Data-out
Valid
Data-in
DQ
–
tCLZ
VI/OL
"H" or "L"
10/17
¡ Semiconductor
MSM51V16800D/DSL
Fast Page Mode Read Cycle
tRASP
tRP
tRHCP
VIH
VIL
–
–
RAS
CAS
tCRP
tPC
tRSH
tCAS
tCRP
tRCD
tRAD
tRAH tASC
tCP
tCP
tCAS
tCAS
VIH
VIL
–
–
tRAL
tASC tCAH
tCSH
tCAH
tASR
Row
tASC
tCAH
VIH
VIL
–
–
Column
Column
Column
tRCS
Address
tRCH
tRCS
tRCS
tRCH
tRCH
VIH
VIL
–
–
WE
tAA
tAA
tAA
tRRH
tCPA
tCPA
tOEA
tOEA
tOEA
VIH
VIL
–
–
OE
tOFF
tOEZ
tOFF
tOEZ
tCAC
tCLZ
tCAC
tCLZ
tOFF
tCAC
tRAC
tOEZ
VOH
VOL
–
–
Valid
Data-out
Valid
Data-out
Valid
Data-out
DQ
tCLZ
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP
tPC
tRP
tCRP
tRHCP
VIH
VIL
–
–
RAS
CAS
tRSH
tCAS
tRAL
tCRP
tRCD
tCP
tCP
tCAS
tCAS
tCAH
Column
VIH
VIL
–
–
tCSH
tCAH
tASR
Row
tASC
tASC
tASC
tRAH
tCAH
VIH
VIL
–
–
Column
tCWL
tWCH
tWP
Column
Address
tRAD
tWCS
tCWL
tWCH
tWP
tRWL
tCWL
tWCH
tWP
tWCS
tWCS
VIH
VIL
–
–
WE
tDS
tDS
tDS
tDH
tDH
tDH
VIH
VIL
–
–
Valid
Data-in
Valid
Data-in
Valid Data-in
DQ
Note: OE = "H" or "L"
"H" or "L"
11/17
¡ Semiconductor
MSM51V16800D/DSL
Fast Page Mode Read Modify Write Cycle
tRASP
VIH
VIL
–
–
RAS
CAS
tRP
tCSH
tPRWC
tCAS
tRSH
tCAS
tCRP
tCP
tCP
tRCD
tRAD
tRAH
tCAS
VIH
VIL
–
–
tASC
tCAH
tASC
tRAL
tCAH
tCAH
tASR
tASC
VIH
VIL
–
–
Column
tRWD
Column
tRCS
Column
Address
Row
tRCS
tCPWD
tCPWD
tCWD
tRWL
tCWL
tCWD
tCWD
tRCS
tCWL
tCWL
VIH
VIL
–
–
WE
tAWD
tAWD
tAWD
tROH
tWP
tWP
tDH
tWP
tDH
tDH
tDS
tDS
tDS
tRAC
tCPA
tAA
tCPA
tAA
tAA
tOEA
tOEA
tOEA
tOED
tOED
tOED
VIH
VIL
–
–
OE
tOEZ
tOEZ
tOEZ
tCAC
tCAC
tCAC
VI/OH
–
DQ
Out
In
Out
In
Out
In
–
VI/OL
tCLZ
tCLZ
tCLZ
"H" or "L"
RAS-Only Refresh Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tCRP
tRPC
VIH
VIL
–
–
tASR tRAH
VIH
VIL
–
–
Address
DQ
Row
tOFF
VOH
VOL
–
–
Open
Note: WE, OE = "H" or "L"
"H" or "L"
12/17
¡ Semiconductor
MSM51V16800D/DSL
CAS before RAS Refresh Cycle
tRC
tRP
tRP
tRAS
VIH
VIL
–
–
RAS
CAS
tRPC
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
tWRP
tWRP
tWRH
VIH
VIL
–
–
WE
tOFF
VOH
VOL
DQ
–
–
Open
Note: OE, Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
tRP
tRP
VIH
VIL
–
–
RAS
tCRP
tRSH
tRCD
tCHR
VIH
VIL
–
–
tRAD
tASC
tRAH
CAS
tCAH
tASR
VIH
VIL
–
–
Address
Row
Column
tRCS
tRRH
tRAL
VIH
VIL
–
–
tAA
WE
OE
tROH
tOEA
VIH
VIL
–
–
tCAC
tCLZ
tOFF
tRAC
tOEZ
VOH
VOL
–
–
DQ
Valid Data-out
"H" or "L"
13/17
¡ Semiconductor
MSM51V16800D/DSL
Hidden Refresh Write Cycle
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
–
–
RAS
tCRP
tRCD
tRSH
tCHR
VIH
VIL
–
–
tRAD
tASC
CAS
tCAH
Column
tASR
Row
tRAH
tRAL
VIH
VIL
–
–
Address
tWRP
tWRH
tWCS
tWCH
tWP
VIH
VIL
–
–
WE
OE
VIH
VIL
–
–
tDS
tDH
Valid Data-in
VIH
VIL
–
–
DQ
"H" or "L"
CAS before RAS Self-Refresh Cycle
tRASS
tRPS
tRP
VIH
VIL
–
–
RAS
CAS
tRPC
tCP
tRPC
tCHS
tCSR
VIH
VIL
–
–
tOFF
VOH
VOL
–
–
DQ
Open
Note: WE, OE, Address = "H" or "L"
"H" or "L"
Only SL version
14/17
¡ Semiconductor
MSM51V16800D/DSL
Test Mode Initiate Cycle
tRC
tRP
tRAS
VIH
VIL
–
–
RAS
tRPC
tCP
tCSR
tCHR
VIH
VIL
–
–
CAS
WE
tWTS
tWTH
VIH
VIL
–
–
tOFF
VOH
VOL
–
–
DQ
Open
Note: OE, Address = "H" or "L"
"H" or "L"
15/17
¡ Semiconductor
PACKAGE DIMENSIONS
SOJ28-P-400-1.27
MSM51V16800D/DSL
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.30 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/17
¡ Semiconductor
MSM51V16800D/DSL
(Unit : mm)
TSOPII28-P-400-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.51 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17
相关型号：
MSM51V16805B-50JS
EDO DRAM, 2MX8, 50ns, CMOS, PDSO28, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-28
OKI
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