MSM514400E-XXSJ [OKI]
1,048,576-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE; 1,048,576字×4位动态RAM ：快速页面模式类型
| 型号： | MSM514400E-XXSJ |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 1,048,576-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| 文件： | 总14页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PEDD514400EL-01
This version : Jan. 2001
Semiconductor
MSM514400E/EL
1,048,576-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
Preliminary
DESCRIPTION
The MSM514400E/EL is a 1,048,576-word × 4-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS
technology. The MSM514400E/EL achieves high integration, high-speed operation, and low-power consumption
because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The
MSM514400E/EL is available in a 26/20-pin plastic SOJ, 26/20-pin plastic TSOP. The MSM514400EL (the
low-power version) is specially designed for lower-power applications.
FEATURES
•
•
•
•
•
•
•
•
•
1,048,576-word × 4-bit configuration
Single 5V power supply, ± 10% tolerance
Input
: TTL compatible, low input capacitance
: TTL compatible, 3-state
Output
Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
Fast page mode, read modify write capability
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Multi-bit test mode capability
Package options:
26/20-pin 300mil plastic SOJ
26/20-pin 300mil plastic TSOP
(SOJ26/20-P-300-1.27)
(Product : MSM514400E/EL-xxSJ)
(TSOPII26/20-P-300-1.27-K) (Product : MSM514400E/EL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation
Cycle Time
(Min.)
Family
t
t
t
t
OEA
Operating (Max.) Standby (Max.)
RAC
AA
CAC
MSM514400E/EL-60
MSM514400E/EL-70
60ns
70ns
30ns
35ns
15ns
20ns
15ns
20ns
110ns
130ns
468mW
5.5mW/
1.1mW (L-version)
413mW
1/14
PEDD514400EL-01
MSM514400E/EL
PIN CONFIGRATION (TOP VIEW)
DQ1 1
DQ2 2
WE 3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
DQ1 1
DQ2 2
WE 3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
26/20-Pin Plastic SOJ
26/20-Pin Plastic TSOP
(K Type)
Pin Name
A0–A9
RAS
Function
Address Input
Row Address Strobe
Column Address Strobe
Data Input/Data Output
Output Enable
CAS
DQ1–DQ4
OE
Write Enable
WE
VCC
Power Supply (5 V)
Ground (0 V)
VSS
Note : The same power supply voltage must be provided to every VCC pin, and the
same GND voltage level must be provided to every VSS pin.
2/14
PEDD514400EL-01
MSM514400E/EL
BLOCK DIAGRAM
Timing
Generator
RAS
Timing
Generator
CAS
Column
Address
Buffers
WE
Write
Clock
Generator
Column
decoders
10
10
OE
Output
Buffers
4
4
4
I/O
Selector
Internal
Address
Counter
Refresh
Control Clock
4
DQ1-DQ4
Sense Amplifiers
4
4
A0-A9
Input
Buffers
4
Row
Address
Buffers
Row
De-
coders
10
10
Word
Drivers
Memory
Cells
VCC
On Chip
BB Generator
V
VSS
3/14
PEDD514400EL-01
MSM514400E/EL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VSS Supply Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
Rating
Unit
V
VIN, VOUT
VCC
− 0.5 to Vcc + 0.5
V
− 0.5 to 7.0
50
IOS
mA
W
PD*
1
Operating Temperature
Topr
0 to 70
− 55 to 150
°C
°C
Storage Temperature
Tstg
*: Ta = 25°C
Recommended Operating Conditions
(Ta = 0 °C to 70 °C)
Parameter
Symbol
VCC
VSS
Min.
4.5
Typ.
5.0
0
Max.
Unit
V
5.5
0
Vcc + 0.5*1
Power Supply Voltage
0
V
Input High Voltage
Input Low Voltage
2.4
− 0.5*2
V
VIH
0.8
V
VIL
Notes: *1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with
respect to the point at which VCC is applied).
*2. The input voltage is VSS − 2.0V when the pulse width is less than 20ns (the pulse width respect to
the point at which VSS is applied).
Capacitance
(Vcc = 5V ± 10%, Ta = 25°C, f=1MHz)
Parameter
Symbol
CIN1
Typ.
Max.
Unit
pF
Input Capacitance (A0 – A9)
6
7
7
pF
Input Capacitance (RAS, CAS, WE, OE)
Output Capacitance (DQ1 – DQ4)
CIN2
pF
CI/O
4/14
PEDD514400EL-01
MSM514400E/EL
DC Characteristics
(Vcc = 5V ± 10%, Ta = 0°C to 70°C)
MSM514400
E/EL-60
Min. Max.
MSM514400
E/EL-70
Parameter
Symbol
Condition
Unit Note
Min.
2.4
0
Max.
V
OH
V
CC
V
CC
I
I
= −5.0mA
Output High Voltage
Output Low Voltage
2.4
0
V
V
OH
V
OL
= 4.2mA
0.4
0.4
OL
0V ≤ V ≤ V +0.5V;
I
CC
I
Input Leakage Current
Output Leakage Current
10
10
−10
−10
−10
−10
µA
µA
LI
All other pins not
under test = 0V
DQ disable
I
LO
10
85
10
75
0V ≤ V ≤ 5.5V
O
Average Power Supply
Current
RAS, CAS cycling,
I
mA
1, 2
CC1
t
= Min.
RC
(Operating)
RAS, CAS = V
RAS, CAS
2
1
2
1
IH
mA
1
Power Supply Current
(Standby)
I
CC2
≥ V −0.2V
CC
200
200
1,5
µA
RAS cycling,
Average Power Supply
Current
I
CAS = V ,
85
5
75
5
mA
mA
mA
mA
µA
1, 2
1
CC3
IH
(RAS-only Refresh)
t
= Min.
RC
RAS = V ,
IH
Power Supply Current
(Standby)
I
CC5
CAS = V ,
IL
DQ = enable
Average Power Supply
Current
RAS = cycling,
CAS before RAS
I
85
70
300
75
60
300
1, 2
1, 3
1,4,5
CC6
(CAS before RAS Refresh)
RAS = V ,
IL
Average Power Supply
Current
I
CC7
CAS cycling,
(Fast Page Mode)
t
= Min.
PC
t
= 125µs
Average Power Supply
Current
RC
I
CAS before RAS
≤ 1µs
CC10
t
(Battery Backup)
RAS
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
4. VCC − 0.2V ≤ VIH ≤ VCC + 0.5V, − 0.5V ≤ VIL ≤ 0.2V.
5. L-version.
5/14
PEDD514400EL-01
MSM514400E/EL
AC Characteristic (1/2)
(Vcc = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
MSM514400
E/EL-60
MSM514400
E/EL-70
Parameter
Symbol
unit
Note
Min.
110
155
40
Max.
Min.
130
185
45
Max.
t
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
ns
ns
ns
RC
t
RWC
t
PC
Fast Page Mode Read Modify Write
Cycle Time
t
85
100
ns
PRWC
t
60
15
30
35
15
70
20
35
40
20
ns
ns
ns
ns
ns
ns
4, 5, 6
4, 5
4, 6
4
Access Time from RAS
RAC
t
Access Time from CAS
CAC
t
AA
Access Time from Column Address
Access Time from CAS Precharge
Access Time from OE
t
CPA
t
4
OEA
t
0
0
0
0
4
Output Low Impedance Time from CAS
CLZ
CAS to Data Output Buffer Turn-off
t
15
15
20
20
ns
ns
7
OFF
Delay Time
OE to Data Output Buffer Turn-off Delay
t
0
3
0
3
7
3
OEZ
Time
t
T
Transition Time
50
16
50
16
ns
ns
ms
ns
ns
ns
ns
ns
t
Refresh Period
REF
t
Refresh Period (L-version)
RAS Precharge Time
RAS Pulse Width
128
128
REF
t
40
60
60
15
15
50
70
70
20
20
RP
t
10,000
10,000
RAS
t
100,000
100,000
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
RASP
t
RSH
t
RAS Hold Time referenced to OE
ROH
CAS Precharge Time
t
10
10
ns
CP
(Fast Page Mode)
t
15
60
5
10,000
20
70
5
10,000
ns
ns
ns
ns
ns
ns
ns
ns
CAS Pulse Width
CAS
t
CAS Hold Time
CSH
t
CAS to RAS Precharge Time
RAS Hold Time from CAS Precharge
RAS to CAS Delay Time
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
CRP
t
35
20
15
0
40
20
15
0
RHCP
t
45
30
50
35
5
6
RCD
t
RAD
t
ASR
t
10
10
RAH
6/14
PEDD514400EL-01
MSM514400E/EL
AC Characteristic (2/2)
(Vcc = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
MSM514400
E/EL-60
MSM514400
E/EL-70
Parameter
Symbol
unit
Note
Min.
0
Max.
Min.
0
Max.
t
Column Address Set-up Time
Column Address Hold Time
Column Address to RAS Lead Time
Read Command Set-up Time
Read Command Hold Time
ns
ns
ns
ns
ns
ASC
t
10
30
0
15
35
0
CAH
t
RAL
t
RCS
t
0
0
8
8
9
RCH
Read Command Hold Time referenced
to RAS
t
0
0
ns
RRH
t
Write Command Set-up Time
Write Command Hold Time
Write Command Pulse Width
OE Command Hold Time
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
0
0
10
10
20
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCS
t
10
10
15
15
15
0
WCH
t
WP
t
OEH
t
RWL
t
CWL
t
10
10
DS
t
Data-in Hold Time
10
15
40
55
85
60
15
20
50
65
100
70
DH
t
OE to Data-in Delay Time
CAS to WE Delay Time
OED
t
9
9
9
9
CWD
t
Column Address to WE Delay Time
RAS to WE Delay Time
AWD
t
RWD
t
CAS Precharge WE Delay Time
CPWD
CAS Active Delay Time from RAS
t
5
5
5
5
ns
ns
ns
ns
RPC
Precharge
RAS to CAS Set-up Time
(CAS before RAS)
t
CSR
RAS to CAS Hold Time
(CAS before RAS)
t
10
10
10
10
CHR
WE to RAS Precharge time
(CAS before RAS)
t
WRP
t
10
10
10
10
10
10
ns
ns
ns
WE Hold Time (CAS before RAS)
WE Set-up Time (Test mode)
WE Hold Time (Test mode)
WRH
t
WTS
t
WRH
7/14
PEDD514400EL-01
MSM514400E/EL
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5ns.
3.
V
IH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition
times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
t
RCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD
(Max.) limit, then the access time is controlled by tCAC
.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
RAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD
(Max.) limit, then the access time is controlled by tAA.
t
7.
t
OFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit
condition and are not referenced to output voltage levels.
8.
t
RCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early
write cycle and the data out will remain open circuit (high impedance) throughout the entire
cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.),
then the cycle is a read modify write cycle and data out will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at
access time) is indeterminate.
10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data
sheet in a 2-bit parallel test function. CA0 is not used. In read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a
low level. The test mode is cleared and the memory device returned to its normal operating state
by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
8/14
PEDD514400EL-01
MSM514400E/EL
Timing Chart
•
Read Cycle
tRC
tRAS
VIH
RAS
tRP
tCRP
VIL
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
VIL
tRAL
tASR tRAH
tASC
tCAH
VIH
Address
VIL
Row
Column
tRCS
tRRH
tRCH
VIH
WE
tAA
VIL
tROH
tOEA
tCAC
VIH
OE
VIL
tOFF
tRAC
tOEZ
tCLZ
VOH
DQ
Valid Data-out
Open
VOL
“H” or “L”
•
Write Cycle (Early Write)
tRC
tRAS
VIH
RAS
tRP
tCRP
VIL
tCSH
tCRP
tRCD
tRSH
tCAS
VIH
CAS
tRAD
VIL
tRAL
tASR tRAH
tASC
tCAH
VIH
VIL
Row
Column
Address
tCWL
tWCH
tWCS
tWP
VIH
VIL
WE
OE
DQ
tRWL
VIH
VIL
tDS
tD
VIH
VIL
Valid Data-in
Open
“H” or “L”
9/14
PEDD514400EL-01
MSM514400E/EL
•
Read Modify Write Cycle
tRWC
tRAS
tCSH
VIH
RAS
tRP
VIL
tCRP
tRCD
tRSH
tCAS
tCRP
VIH
CAS
tRAD
tRAH
VIL
tCWL
tRWL
tASR
tASC
tCAH
VIH
Row
Column
Address
VIL
tRCS
tCWD
tRWD
tWP
VIH
VIL
WE
OE
tAWD
tAA
tOEH
tOEA
VIH
VIL
tOED
tOEZ
tCAC
tD
tDS
tRAC
tCLZ
VI/OH
VI/OL
Valid
Data-out
Valid
Data-in
DQ
“H” or “L”
10/14
PEDD514400EL-01
MSM514400E/EL
•
Fast Page Mode Cycle
tRASP
tRP
tPC
tRHCP
VIH
RAS
VIL
tRCD
tCP
tCP
tRSH
tCAS
tCRP
tCRP
tCAS
tCAS
VIH
CAS
tRAD
tCSH
tRAH
VIL
tRAL
tCAH
tASR
tASC
tCAH
tASC tCAH
tASC
VIH
Row
Column
Column
Column
Address
WE
VIL
tRCS
tRCH
tRCS
tRCH
tRCS
tRCH
VIH
VIL
tAA
tAA
tAA
tRRH
tOEA
tOEA
tOEA
VIH
VIL
OE
tRAC
tCPA
tOFF
tOEZ
tCPA
tOFF
tOFF
tCAC
tCLZ
tCAC
tCLZ
tCAC
tOEZ
tOEZ
tCLZ
VOH
VOL
Valid
Data-out
Valid
Data-out
Valid
Data-out
DQ
“H” or “L”
•
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
tPC
tRHPC
VIH
RAS
VIL
tCRP
tCRP
tRCD
tRAD
tRAH
tCP
tCP
tRSH
tCAS
tCAS
tCAS
VIH
VIL
CAS
tCSH
tCAH
tRAL
tCAH
tASR
tASC
tASC
tCAH
tASC
VIH
VIL
Row
Column
Column
Column
Address
tCWL
tCWL
tCWL
tRWL
tWCH
tWP
tWCH
tWP
tWCS
tWCS
tWCS
tWCH
tWP
VIH
VIL
WE
DQ
tDS
tD
tDS
tD
tDS
tD
VIH
VIL
Valid
Data-in
Valid
Data-in
Valid
Data-in
Note: OE = “H” or “L”
“H” or “L”
11/14
PEDD514400EL-01
MSM514400E/EL
•
Fast Page Mode Read Modify Write Cycle
tRASP
tRP
tCSH
tPRWC
tRSH
VIH
RAS
VIL
tCP
tCP
tRCD
tCAS
tCAS
tCAH
tCAS
tCAH
tCRP
VIH
VIL
CAS
tRAD
tASC
tRAH
tASR
tCAH
tCWL
tASC
tASC
tRAL
tCWL
VIH
VIL
Row
Column
Column
Column
Address
tRCS
tRCS
tCWL
tRWD
tCWD
tCPWD
tCPWD
tRWL
tRCS
tCWD
tCWD
VIH
VIL
WE
tAWD
tAWD
tAWD
tWP
tWP
tWP
tCPA
tAA
tRAC
tAA
tROH
tCPA
tDS
tD
tDH
tDS
tOEA
tD
tAA
tDS
tOEA
tOEA
VIH
VIL
OE
DQ
tOED
tOEZ tCAC
tOED
tOEZ
tOED
tOEZ
tCAC
tCAC
VI/OH
VI/OL
Out
In
Out
In
Out
In
tCLZ
tCLZ
tCLZ
Note: In = Valid Data-in, Out = Valid Data-out
“H” or “L”
•
RAS-only Refresh Cycle
tRC
tRAS
VIH
RAS
tRP
VIL
tCRP
tRPC
VIH
CAS
VIL
tAS tRA
VIH
Row
Address
VIL
tOFF
VOH
VOL
Open
DQ
Note: WE, OE = “H” or “L”
“H” or “L”
12/14
PEDD514400EL-01
MSM514400E/EL
•
CAS before RAS Refresh Cycle
tRP
tRC
tRAS
VIH
RAS
VIL
tRPC
tRP
tCSR
tCP
tRPC
tCHR
tWR
VIH
VIL
CAS
WE
DQ
tWR
tWR
VIH
VIL
tOFF
VOH
VOL
Open
Note: WE, OE, Address = “H” or “L”
“H” or “L”
•
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRAS
VIH
RAS
VIL
tCRP
tRP
tRCD
tRSH
tRP
tCHR
VIH
CAS
tRAD
tRAH
VIL
tASR
tASC
tCAH
VIH
VIL
Row
Column
Address
WE
tRCS
tCAC
tRAL
tRRH
VIH
VIL
tAA
tROH
tOEA
tOFF
VIH
VIL
OE
DQ
tRAC
tOEZ
tCLZ
VOH
VOL
Open
Valid Data-out
“H” or “L”
13/14
PEDD514400EL-01
MSM514400E/EL
•
Hidden Refresh Write Cycle
tRC
tRC
tRAS
tRAS
VIH
RAS
VIL
tCRP
tRCD
tRSH
tRP
tRP
tCHR
VIH
CAS
tRAD
tRAH
VIL
tRAL
tCAH
tASR
tASC
VIH
VIL
Row
Column
Address
WE
tWR
tWR
tWCS
tWCH
tWP
VIH
VIL
VIH
VIL
OE
tDS
tD
VIH
VIL
DQ
Valid Data-in
“H” or “L”
•
Test Mode Initiate Cycle
tRC
tRP
tRAS
VIH
RAS
tRPC
VIL
tCP
tCSR
tCHR
VIH
CAS
VIL
tWTS
tWTH
VIH
WE
VIL
tOFF
VIH
DQ
Open
VIL
Note: OE, Address = “H” or “L”
“H” or “L”
14/14
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