MSM511664C [OKI]

65,536-Word X 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE (BYTE WRITE); 65536字×16位动态RAM :快速页面模式类型(字节写入)
MSM511664C
型号: MSM511664C
厂家: OKI ELECTRONIC COMPONETS    OKI ELECTRONIC COMPONETS
描述:

65,536-Word X 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE (BYTE WRITE)
65536字×16位动态RAM :快速页面模式类型(字节写入)

文件: 总16页 (文件大小:238K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
E2G0014-17-41  
This version: Jan. 1998  
Previous version: May 1997  
¡ Semiconductor  
MSM511664C/CL  
65,536-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE (BYTE WRITE)  
DESCRIPTION  
The MSM511664C/CL is a 65,536-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS  
technology. The MSM511664C/CL achieves high integration, high-speed operation, and low-power  
consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer  
metal CMOS process. The MSM511664C/CL is available in a 40-pin plastic SOJ or 44/40-pin plastic  
TSOP.TheMSM511664CL(thelow-powerversion)isspeciallydesignedforlower-powerapplications.  
FEATURES  
• 65,536-word ¥ 16-bit configuration  
• Single 5 V power supply, ±10% tolerance  
• Input  
: TTL compatible, low input capacitance  
• Output : TTL compatible, 3-state  
• Refresh : 256 cycles/4 ms, 256 cycles/32 ms (L-version)  
• Byte write and fast page mode, read modify write capability  
CAS before RAS refresh, hidden refresh, RAS-only refresh capability  
• Package options:  
40-pin 400 mil plastic SOJ  
(SOJ40-P-400-1.27)  
(Product : MSM511664C/CL-xxJS)  
44/40-pin 400 mil plastic TSOP  
(TSOPII44/40-P-400-0.80-K) (Product : MSM511664C/CL-xxTS-K)  
xx indicates speed rank.  
PRODUCT FAMILY  
Access Time (Max.)  
Cycle Time  
(Min.)  
Power Dissipation  
Family  
tRAC tAA tCAC tOEA  
60 ns 30 ns 20 ns 20 ns  
70 ns 40 ns 25 ns 25 ns  
80 ns 45 ns 30 ns 30 ns  
Standby (Max.)  
Operating (Max.)  
MSM511664C/CL-60  
MSM511664C/CL-70  
MSM511664C/CL-80  
110 ns  
120 ns  
135 ns  
550 mW  
495 mW  
440 mW  
5.5 mW/  
1.1 mW (L-version)  
1/16  
¡ Semiconductor  
MSM511664C/CL  
PIN CONFIGURATION (TOP VIEW)  
VCC  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
1
2
3
4
5
6
7
8
9
44 VSS  
VCC  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
1
2
3
4
5
6
7
8
9
40 VSS  
39 DQ16  
38 DQ15  
37 DQ14  
36 DQ13  
35 DQ12  
34 DQ11  
33 DQ10  
32 DQ9  
31 NC  
43 DQ16  
42 DQ15  
41 DQ14  
40 DQ13  
39 DQ12  
38 DQ11  
37 DQ10  
36 DQ9  
35 NC  
NC 10  
NC 10  
VCC 11  
UWE 12  
LWE 13  
RAS 14  
A0 15  
VCC 13  
UWE 14  
LWE 15  
RAS 16  
A0 17  
A1 18  
A2 19  
A3 20  
A4 21  
32 VSS  
31 CAS  
30 OE  
29 NC  
28 NC  
27 NC  
26 A7  
25 A6  
24 A5  
23 VSS  
30 VSS  
29 CAS  
28 OE  
27 NC  
26 NC  
A1 16  
25 NC  
A2 17  
24 A7  
VCC 22  
A3 18  
23 A6  
44/40-Pin Plastic TSOP  
(K Type)  
A4 19  
22 A5  
VCC 20  
21 VSS  
40-Pin Plastic SOJ  
Pin Name  
Function  
A0 - A7  
RAS  
Address Input  
Row Address Strobe  
Column Address Strobe  
Data Input/Data Output  
Output Enable  
CAS  
DQ1 - DQ16  
OE  
LWE  
Lower Byte Write Enable  
Upper Byte Write Enable  
Power Supply (5 V)  
Ground (0 V)  
UWE  
VCC  
VSS  
NC  
No Connection  
Note :  
The same power supply voltage must be provided to every V pin, and the same GND  
CC  
voltage level must be provided to every V pin.  
SS  
2/16  
¡ Semiconductor  
MSM511664C/CL  
BLOCK DIAGRAM  
Timing  
Generator  
RAS  
Timing  
Generator  
CAS  
Write  
Clock  
Generator  
UWE  
LWE  
Column  
Address  
Buffers  
Column  
Decoders  
8
8
OE  
Output  
Buffers  
16  
16  
16  
Internal  
Address  
Counter  
I/O  
Selector  
Refresh  
Control Clock  
Sense  
Amplifiers  
A0 - A7  
16  
16  
16  
DQ1 - DQ16  
Input  
Buffers  
16  
Row  
Address  
Buffers  
Row  
De-  
8
8
Word  
Drivers  
Memory  
Cells  
coders  
VCC  
On Chip  
BB Generator  
V
VSS  
FUNCTION TABLE  
Input Pin  
DQ Pin  
DQ1 - DQ8  
Function Mode  
RAS  
CAS  
LWE  
UWE  
OE  
DQ9 - DQ16  
High-Z  
High-Z  
DOUT  
Standby  
Refresh  
H
L
L
L
L
L
L
High-Z  
High-Z  
DOUT  
*
H
*
*
*
*
H
*
H
*
L
Word Read  
Lower Byte Write  
Upper Byte Write  
Word Write  
L
L
L
L
L
DIN  
L
H
L
H
L
H
H
H
H
Don't Care  
DIN  
Don't Care  
DIN  
DIN  
L
High-Z  
High-Z  
H
H
*: "H" or "L"  
3/16  
¡ Semiconductor  
MSM511664C/CL  
ELECTRICAL CHARACTERISTICS  
Absolute Maximum Ratings  
Parameter  
Voltage on Any Pin Relative to VSS  
Short Circuit Output Current  
Power Dissipation  
Symbol  
VT  
Rating  
–1.0 to 7.0  
50  
Unit  
V
IOS  
mA  
W
PD  
*
1
Operating Temperature  
Storage Temperature  
Topr  
Tstg  
0 to 70  
–55 to 150  
°C  
°C  
*: Ta = 25°C  
Recommended Operating Conditions  
(Ta = 0°C to 70°C)  
Parameter  
Power Supply Voltage  
Symbol  
VCC  
Min.  
4.5  
0
Typ.  
5.0  
0
Max.  
Unit  
5.5  
0
V
V
V
V
VSS  
Input High Voltage  
Input Low Voltage  
VIH  
2.4  
–1.0  
6.5  
0.8  
VIL  
Capacitance  
(VCC = 5 V 10ꢀ% Ta = 25°C% f = 1 MHꢁ)  
Parameter  
Symbol  
Typ.  
Max.  
Unit  
Input Capacitance (A0 - A7)  
Input Capacitance  
CIN1  
7
pF  
CIN2  
CI/O  
7
7
pF  
pF  
(RAS% CAS% UWE% LWE% OE)  
Output Capacitance (DQ1 - DQ16)  
4/16  
¡ Semiconductor  
MSM511664C/CL  
DC Characteristics  
(VCC = 5 V 10ꢀ% Ta = 0°C to 70°C)  
MSM511664 MSM511664 MSM511664  
C/CL-60 C/CL-70 C/CL-80  
Parameter  
Symbol  
Condition  
Unit Note  
Min. Max. Min. Max. Min. Max.  
Output High Voltage  
Output Low Voltage  
VOH IOH = –2.5 mA  
VOL IOL = 2.1 mA  
0 V £ VI £ 6.5 V;  
ILI All other pins not  
under test = 0 V  
DQ disable  
2.4  
0
VCC  
0.4  
2.4  
0
VCC  
0.4  
2.4  
0
VCC  
0.4  
V
V
Input Leakage Current  
–10  
–10  
10  
10  
–10  
–10  
10  
10  
90  
–10  
–10  
10  
10  
80  
mA  
Output Leakage Current ILO  
mA  
0 V £ VO £ 5.5 V  
Average Power  
RAS% CAS cycling%  
Supply Current  
(Operating)  
ICC1  
100  
mA 1% 2  
tRC = Min.  
RAS% CAS = VIH  
2
1
2
1
2
1
Power Supply  
mA  
1
ICC2 RAS% CAS  
VCC –0.2 V  
RAS cycling%  
ICC3 CAS = VIH%  
tRC = Min.  
Current (Standby)  
200  
200  
200  
mA 1% 5  
Average Power  
Supply Current  
100  
5
90  
5
80  
5
mA 1% 2  
(RAS-only Refresh)  
RAS = VIH%  
Power Supply  
ICC5 CAS = VIL%  
DQ = enable  
mA  
1
Current (Standby)  
Average Power  
Supply Current  
(CAS before RAS Refresh)  
Average Power  
Supply Current  
(Fast Page Mode)  
Average Power  
Supply Current  
(Battery Backup)  
RAS cycling%  
ICC6  
100  
95  
90  
85  
300  
80  
75  
300  
mA 1% 2  
mA 1% 3  
CAS before RAS  
RAS = VIL%  
ICC7 CAS cycling%  
tPC = Min.  
tRC = 125 ms%  
1% 4%  
ICC10  
300  
mA  
CAS before RAS%  
tRAS £ 1 ms  
5
Notes : 1. I Max. is specified as I for output open condition.  
CC  
CC  
2. The address can be changed once or less while RAS = V .  
IL  
3. The address can be changed once or less while CAS = V  
.
IH  
4. V – 0.2 V £ V £ 6.5 V, –1.0 V £ V £ 0.2 V.  
CC  
IH  
IL  
5. L-version.  
5/16  
¡ Semiconductor  
MSM511664C/CL  
AC Characteristics (1/2)  
(VCC = 5 V 10ꢀ% Ta = 0°C to 70°C) Note 1% 2% 3  
MSM511664 MSM511664 MSM511664  
C/CL-60 C/CL-70 C/CL-80  
Parameter  
Symbol  
Unit Note  
Min. Max. Min. Max. Min. Max.  
Random Read or Write Cycle Time  
Read Modify Write Cycle Time  
Fast Page Mode Cycle Time  
tRC  
110  
120  
170  
50  
135  
185  
55  
ns  
ns  
ns  
tRWC 155  
tPC  
40  
Fast Page Mode Read Modify Write  
Cycle Time  
85  
95  
100  
ns  
tPRWC  
Access Time from RAS  
Access Time from CAS  
Access Time from Column Address  
Access Time from CAS Precharge  
tRAC  
tCAC  
tAA  
60  
20  
30  
35  
70  
25  
40  
45  
80  
30  
45  
50  
ns 4% 5% 6  
ns  
ns  
ns  
4% 5  
4% 6  
4
tCPA  
Access Time from OE  
Output Low Impedance Time from CAS  
tOEA  
tCLZ  
0
20  
20  
15  
50  
4
0
25  
20  
15  
50  
4
0
30  
20  
15  
50  
4
ns  
ns  
ns  
ns  
ns  
ms  
ms  
ns  
4
4
7
7
3
0
0
0
CAS to Data Output Buffer Turn-off Delay Time tOFF  
OE to Data Output Buffer Turn-off Delay Time  
Transition Time  
0
0
0
tOEZ  
tT  
tREF  
tREF  
tRP  
3
3
3
Refresh Period  
40  
40  
45  
32  
32  
32  
Refresh Period (L-version)  
RAS Precharge Time  
60 10%000 70 10%000 80 10%000 ns  
60 100%000 70 100%000 80 100%000 ns  
RAS Pulse Width  
tRAS  
RAS Pulse Width (Fast Page Mode)  
RAS Hold Time  
RAS Hold Time referenced to OE  
CAS Precharge Time (Fast Page Mode)  
CAS Pulse Width  
tRASP  
tRSH  
tROH  
tCP  
20  
15  
10  
25  
15  
10  
30  
15  
10  
ns  
ns  
ns  
tCAS  
tCSH  
tCRP  
tRHCP  
tRCD  
tRAD  
tASR  
tRAH  
tASC  
tCAH  
tAR  
20 10%000 25 10%000 30 10%000 ns  
CAS Hold Time  
60  
5
40  
30  
70  
5
45  
30  
80  
5
50  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CAS to RAS Precharge Time  
RAS Hold Time from CAS Precharge  
RAS to CAS Delay Time  
RAS to Column Address Delay Time  
Row Address Set-up Time  
Row Address Hold Time  
35  
20  
15  
0
45  
20  
15  
0
50  
22  
17  
0
5
6
10  
0
10  
0
12  
0
Column Address Set-up Time  
Column Address Hold Time  
Column Address Hold Time from RAS  
Column Address to RAS Lead Time  
Read Command Set-up Time  
Read Command Hold Time  
10  
45  
30  
0
10  
45  
40  
0
15  
55  
45  
0
ns  
ns  
ns  
ns  
ns  
ns  
tRAL  
tRCS  
tRCH  
0
0
0
8
8
Read Command Hold Time referenced to RAS tRRH  
0
0
0
6/16  
¡ Semiconductor  
MSM511664C/CL  
AC Characteristics (2/2)  
(VCC = 5 V 10ꢀ% Ta = 0°C to 70°C) Note 1% 2% 3  
MSM511664 MSM511664 MSM511664  
C/CL-60 C/CL-70 C/CL-80  
Unit Note  
Parameter  
Symbol  
Min. Max. Min. Max. Min. Max.  
Write Command Set-up Time  
tWCS  
0
0
0
ns  
9
Write Command Hold Time  
Write Command Hold Time from RAS  
tWCH  
tWCR  
10  
40  
10  
45  
15  
55  
ns  
ns  
Write Command Pulse Width  
OE Command Hold Time  
Write Command to RAS Lead Time  
Write Command to CAS Lead Time  
tWP  
tOEH  
tRWL  
tCWL  
10  
10  
20  
20  
10  
10  
20  
20  
15  
10  
20  
20  
ns  
ns  
ns  
ns  
Data-in Set-up Time  
tDS  
tDH  
0
0
0
15  
55  
15  
55  
70  
105  
75  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10  
10  
Data-in Hold Time  
10  
40  
15  
40  
50  
80  
10  
45  
15  
50  
60  
95  
70  
0
Data-in Hold Time from RAS  
OE to Data-in Delay Time  
CAS to WE Delay Time  
Column Address to WE Delay Time  
RAS to WE Delay Time  
tDHR  
tOED  
tCWD  
tAWD  
tRWD  
9
9
9
9
CAS Precharge WE Delay Time  
CAS Active Delay Time from RAS Precharge  
RAS to CAS Set-up Time (CAS before RAS) tCSR  
RAS to CAS Hold Time (CAS before RAS) tCHR  
tCPWD 55  
tRPC  
0
5
10  
5
10  
5
10  
7/16  
¡ Semiconductor  
MSM511664C/CL  
Notes: 1. A start-up delay of 100 µs is required after power-up, followed by a minimum of eight  
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device  
operation is achieved.  
2. The AC characteristics assume t = 5 ns.  
T
3. V (Min.) and V (Max.) are reference levels for measuring input timing signals.  
IH  
IL  
Transition times (t ) are measured between V and V .  
T
IH  
IL  
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF.  
5. Operation within the t (Max.) limit ensures that t (Max.) can be met.  
RCD  
RAC  
t
(Max.) is specified as a reference point only. If t  
(Max.) limit, then the access time is controlled by t  
is greater than the specified  
RCD  
RCD  
t
.
RCD  
CAC  
6. Operation within the t  
(Max.) limit ensures that t  
(Max.) can be met.  
is greater than the specified  
RAD  
RAC  
t
(Max.) is specified as a reference point only. If t  
RAD  
RAD  
t
(Max.) limit, then the access time is controlled by t  
.
RAD  
AA  
7. t  
(Max.) and t  
(Max.) define the time at which the output achieves the open  
OFF  
OEZ  
circuit condition and are not referenced to output voltage levels.  
8. t  
9. t  
or t  
must be satisfied for a read cycle.  
RCH  
RRH  
, t  
, t  
, t  
and t  
are not restrictive operating parameters. They are  
WCS CWD RWD AWD  
CPWD  
included in the data sheet as electrical characteristics only. If t  
t  
(Min.), then  
WCS WCS  
the cycle is an early write cycle and the data out will remain open circuit (high  
impedance) throughout the entire cycle. If t t (Min.) , t t (Min.),  
CWD  
CWD  
RWD  
RWD  
t
t  
(Min.) and t  
t  
(Min.), then the cycle is a read modify write  
AWD  
AWD  
CPWD  
CPWD  
cycle and data out will contain data read from the selected cell; if neither of the above  
sets of conditions is satisfied, then the condition of the data out (at access time) is  
indeterminate.  
10. These parameters are referenced to the CAS leading edge in an early write cycle, and  
to the WE leading edge in an OE control write cycle, or a read modify write cycle.  
8/16  
E2G0092-17-41E  
¡ Semiconductor  
MSM511664C/CL  
TIMING WAVEFORM  
Read Cycle  
tRC  
tRP  
tCRP  
tRAS  
VIH  
VIL  
tAR  
RAS  
tCSH  
tCRP  
tRCD  
tRSH  
tCAS  
VIH  
VIL  
CAS  
tRAD  
tASC  
tASR  
Row  
tRAH  
tRAL  
tCAH  
Column  
VIH  
VIL  
Address  
tRCH  
tRCS  
tRRH  
VIH  
VIL  
tAA  
WE  
OE  
tROH  
tOEA  
VIH  
VIL  
tOFF  
tCAC  
tRAC  
tOEZ  
VOH  
VOL  
DQ  
Open  
Valid Data-out  
tCLZ  
"H" or "L"  
Write Cycle (Early Write)  
tRC  
tRP  
tRAS  
VIH  
VIL  
tAR  
tCRP  
RAS  
CAS  
tCSH  
tCRP  
tRCD  
tRAD  
tRAH  
tASC  
tRSH  
tCAS  
VIH  
VIL  
tRAL  
tASR  
Row  
tCAH  
Column  
tWCH  
VIH  
VIL  
Address  
tWCS  
tCWL  
VIH  
VIL  
tWP  
WE  
tRWL  
tWCR  
VIH  
VIL  
OE  
tDHR  
tDS  
tDH  
VIH  
VIL  
DQ  
Open  
Valid Data-in  
"H" or "L"  
9/16  
¡ Semiconductor  
MSM511664C/CL  
Read Modify Write Cycle  
tRWC  
tRAS  
tRP  
VIH  
VIL  
tAR  
RAS  
CAS  
tCRP  
tCSH  
tCRP  
tRCD  
tRSH  
tCAS  
VIH  
VIL  
tRAH  
tASC  
tASR  
tCAH  
Column  
VIH  
VIL  
Row  
Address  
tCWL  
tRWL  
tWP  
tCWD  
tAWD  
tRAD  
tRWD  
tOEA  
VIH  
VIL  
tAA  
WE  
OE  
tRCS  
VIH  
VIL  
tOED  
tOEZ  
tOEH  
tDH  
tCAC  
tDS  
tRAC  
VI/OH  
Valid  
Data-out  
Valid  
Data-in  
DQ  
tCLZ  
VI/OL  
"H" or "L"  
10/16  
¡ Semiconductor  
MSM511664C/CL  
Fast Page Mode Read Cycle  
tRASP  
tRP  
tAR  
tRCD  
tRAD  
tRAH tASC  
tRHCP  
VIH  
VIL  
RAS  
CAS  
tCRP  
tPC  
tRSH  
tCRP  
tCP  
tCP  
tCAS  
tCAS  
tCAS  
tRAL  
VIH  
VIL  
tCSH  
tCAH  
tASR  
Row  
tASC  
tCAH  
tASC tCAH  
VIH  
VIL  
Column  
Column  
Column  
tRCS  
Address  
tRCH  
tRCS  
tRCS  
tRCH  
tRCH  
VIH  
VIL  
WE  
tAA  
tAA  
tAA  
tRRH  
tCPA  
tCPA  
tOEA  
tOEA  
tOEA  
VIH  
VIL  
OE  
tOFF  
tOEZ  
tOFF  
tOEZ  
tCAC  
tCLZ  
tCAC  
tCLZ  
tOFF  
tCAC  
tRAC  
tOEZ  
VOH  
VOL  
Valid  
Data-out  
Valid  
Data-out  
Valid  
Data-out  
DQ  
tCLZ  
"H" or "L"  
Fast Page Mode Write Cycle (Early Write)  
tRASP  
tPC  
tRP  
tCRP  
tAR  
tRHCP  
VIH  
VIL  
RAS  
CAS  
tRSH  
tCAS  
tRAL  
tCRP  
tRCD  
tCP  
tCP  
tCAS  
tCAS  
tCAH  
Column  
VIH  
VIL  
tCSH  
tCAH  
tASR  
Row  
tASC  
tASC  
tASC  
tRAH  
tCAH  
VIH  
VIL  
Column  
tCWL  
tWCH  
tWP  
Column  
Address  
tRAD  
tWCS  
tCWL  
tWCH  
tWP  
tRWL  
tCWL  
tWCH  
tWP  
tWCS  
tWCS  
VIH  
VIL  
WE  
tWCR  
tDS  
tDS  
tDS  
tDH  
tDH  
tDH  
VIH  
VIL  
Valid  
Data-in  
Valid  
Data-in  
Valid Data-in  
tDHR  
DQ  
Note: OE = "H" or "L"  
"H" or "L"  
11/16  
¡ Semiconductor  
MSM511664C/CL  
Fast Page Mode Read Modify Write Cycle  
tRASP  
VIH  
VIL  
tAR  
RAS  
CAS  
tRP  
tCSH  
tPRWC  
tCAS  
tRSH  
tCAS  
tCRP  
tCP  
tCP  
tRCD  
tCAS  
VIH  
VIL  
tRAD  
tRAH  
tASC  
tCAH  
tASC  
tRAL  
tCAH  
tCAH  
tASR  
tASC  
VIH  
VIL  
Column  
tRWD  
Column  
tRCS  
Column  
Address  
Row  
tRCS  
tCPWD  
tCPWD  
tCWD  
tRWL  
tCWL  
tCWD  
tCWD  
tRCS  
tCWL  
tCWL  
VIH  
VIL  
WE  
tAWD  
tAWD  
tAWD  
tROH  
tWP  
tWP  
tDH  
tWP  
tDH  
tDH  
tDS  
tDS  
tDS  
tRAC  
tCPA  
tAA  
tCPA  
tAA  
tAA  
tOEA  
tOEA  
tOEA  
tOED  
tOED  
tOED  
VIH  
VIL  
OE  
tOEZ  
tOEZ  
tOEZ  
tCAC  
tCAC  
tCAC  
VI/OH  
DQ  
Out  
In  
Out  
In  
Out  
In  
VI/OL  
tCLZ  
tCLZ  
tCLZ  
"H" or "L"  
RAS-Only Refresh Cycle  
tRC  
tRP  
tRAS  
VIH  
VIL  
RAS  
CAS  
tCRP  
tRPC  
VIH  
VIL  
tASR tRAH  
VIH  
VIL  
Address  
DQ  
Row  
tOFF  
VOH  
VOL  
Open  
Note: WE% OE = "H" or "L"  
"H" or "L"  
12/16  
¡ Semiconductor  
MSM511664C/CL  
CAS before RAS Refresh Cycle  
tRC  
tRP  
tRAS  
tRP  
VIH  
VIL  
RAS  
tRPC  
tRPC  
tCP  
tCSR  
tCHR  
VIH  
VIL  
CAS  
tOFF  
VOH  
VOL  
DQ  
Open  
Note: WE% OE% Address = "H" or "L"  
"H" or "L"  
Hidden Refresh Read Cycle  
tRC  
tRC  
tRAS  
tRAS  
tRP  
tRP  
VIH  
VIL  
tAR  
tRCD  
RAS  
tCRP  
tRSH  
tCHR  
VIH  
VIL  
tRAD  
tASC  
tRAH  
CAS  
tCAH  
tASR  
VIH  
VIL  
Address  
Row  
Column  
tRCS  
tRRH  
tRAL  
VIH  
VIL  
tAA  
WE  
OE  
tROH  
tOEA  
VIH  
VIL  
tCAC  
tCLZ  
tOFF  
tRAC  
tOEZ  
VOH  
VOL  
DQ  
Valid Data-out  
"H" or "L"  
13/16  
¡ Semiconductor  
MSM511664C/CL  
Hidden Refresh Write Cycle  
tRC  
tRC  
tRP  
tRAS  
tRAS  
tRP  
VIH  
VIL  
tAR  
tRCD  
RAS  
tCRP  
tRSH  
tCHR  
VIH  
VIL  
tRAD  
tASC  
tRAH  
CAS  
tCAH  
tASR  
tRAL  
VIH  
VIL  
Address  
Column  
Row  
tWCS  
tWCH  
tWP  
VIH  
VIL  
WE  
tWCR  
VIH  
VIL  
OE  
tDS  
tDH  
VIH  
VIL  
DQ  
Valid Data-in  
tDHR  
"H" or "L"  
14/16  
¡ Semiconductor  
MSM511664C/CL  
PACKAGE DIMENSIONS  
(Unit : mm)  
SOJ40-P-400-1.27  
Mirror finish  
Package material  
Epoxy resin  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
42 alloy  
Solder plating  
5 mm or more  
1.70 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
15/16  
¡ Semiconductor  
MSM511664C/CL  
(Unit : mm)  
TSOPII44/40-P-400-0.80-K  
Mirror finish  
Package material  
Epoxy resin  
Lead frame material  
Pin treatment  
Solder plate thickness  
Package weight (g)  
42 alloy  
Solder plating  
5 mm or more  
0.49 TYP.  
Notes for Mounting the Surface Mount Type Package  
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which  
are very susceptible to heat in reflow mounting and humidity absorbed in storage.  
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions  
(reflow method, temperature and times).  
16/16  

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