MSC23V26457TD-60 [OKI]
2,097,152-Word x 64-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO; 2,097,152字×64位的动态RAM模块：快速页模式输入与EDO
| 型号： | MSC23V26457TD-60 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 2,097,152-Word x 64-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO |
| 文件： | 总10页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
This version: Apr.22. 1999
Semiconductor
MSC23V26457TD-xxBS8
2,097,152-Word x 64-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSC23V26457TD-xxBS8 is a 2,097,152-word x 64-bit CMOS dynamic random access memory module which
is composed of eight 16Mb(2Mx8) DRAMs in TSOP packages mounted with eight decoupling capacitors. This is an
168-pin dual in-line memory module. This module supports any application where high density and large capacity of
storage memory are required.
FEATURES
· 2,097,152-word x 64-bit organization
· 168-pin Dual In-line Memory Module
· Gold tab
· Single 3.3V power supply, ±0.3V tolerance
· Input
: LVTTL compatible
· Output
: LVTTL compatible, 3-state
· Refresh : 2048cycles/ 32ms
· /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability
· Fast page mode with EDO, read modify write capability
· Multi-bit test mode capability
· Serial Presence Detect
PRODUCT FAMILY
Cycle
Time
(Min.)
Access Time (Max.)
Power Dissipation (Max.)
Family
tRAC
50ns
60ns
70ns
tAA
tCAC
13ns
15ns
20ns
tOEA
13ns
15ns
20ns
Operating
2880mW
2592mW
2304mW
Standby
MSC23V26457TD-50BS8
MSC23V26457TD-60BS8
MSC23V26457TD-70BS8
25ns
30ns
35ns
84ns
104ns
124ns
14.4mW
Semiconductor
MSC23V26457TD
MODULE OUTLINE
MSC23V26457TD-xxBS8
(Unit : mm)
2.70Max.
133.35±0.7 *1
131.35 TYP
2 - R2.0
2 - 3.0±0.1
φ
A
B
C
4.0Min.
1
84
11.43±0.05
36.83±0.05
54.61±0.05
127.35±0.05
133.35±0.12
1.27±0.1
R1.0
R1.0
1.0±0.03
4.175±0.13
3.175±0.13
2.0±0.1
2.0±0.1
1.27±0.03
6.35±0.05
6.35±0.05
Detail A
Detail B
Detail C
Note:
1. Tolerance over 19.78mm from bottom edge is ±0.7.
Semiconductor
PIN CONFIGURATION
Front Side
MSC23V26457TD
Back Side
Front Side
Back Side
Pin No. Pin Name
Pin No.
1
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
V
SS
85
86
V
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
V
SS
SS
2
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
/OE2
/RAS2
/CAS2
/CAS3
/WE2
NC
NC
3
87
4
88
/CAS6
/CAS7
NC
5
89
6
V
CC
90
V
CC
7
DQ4
DQ5
DQ6
DQ7
DQ8
91
DQ36
DQ37
DQ38
DQ39
DQ40
V
V
CC
CC
8
92
NC
NC
NC
NC
NC
NC
NC
NC
9
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
94
95
V
96
V
V
V
SS
SS
SS
SS
DQ9
DQ10
DQ11
DQ12
DQ13
97
DQ41
DQ42
DQ43
DQ44
DQ45
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
V
CC
V
CC
V
CC
V
CC
DQ20
NC
DQ52
NC
DQ14
DQ15
NC
DQ46
DQ47
NC
NC
NC
NC
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
DQ21
DQ22
DQ23
DQ53
DQ54
DQ55
NC
NC
NC
NC
V
CC
V
CC
V
SS
V
SS
/WE0
/CAS0
/CAS1
/RAS0
/OE0
NC
/CAS4
/CAS5
NC
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
NC
V
CC
V
CC
V
SS
V
SS
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
A0
A2
A1
A3
A5
A7
A9
NC
NC
A4
A6
V
SS
V
SS
A8
NC
NC
NC
NC
A10
NC
NC
SA0
SA1
SA2
V
CC
V
CC
SDA
SCL
V
CC
NC
NC
NC
V
CC
V
CC
Semiconductor
MSC23V26457TD
Serial PD Matrix
SPD Value
(Hex)
Byte No.
Function described
Number of Byte used
Note
0
80
08
02
0B
0A
01
40
00
01
32
3C
46
0D
0F
14
00
00
08
00
00
01
29
35
44
00
FF
128 Bytes
1
Total SPD Memory size
Memory type
256 Bytes
2
EDO
3
Number of Rows
11
4
Number of Columns
Number of Banks
10
5
1
6
Module Data Width
Module Data Width Continued
Supply Voltage
64
7
0
8
LVTTL
50ns
-50
9
-60
-70
-50
-60
-70
/RAS Access Time
/CAS Access Time
60ns
70ns
13ns
10
15ns
20ns
11
12
DIMM Configuration type
Refresh Rate/Type
Non-Parity
Normal Refresh
x8
13
Primary DRAM Width
Error Checking DRAM Width
Superset Information
14
15-61
62
Reserved
1
SPD Data Revision Code
-50
-60
-70
63
Checksum for Byte 0-62
64-127
Reserved
128-255
Unused Storage Location (Reserved)
Semiconductor
MSC23V26457TD
BLOCK DIAGRAM
/OE0
/WE0
/OE2
/WE2
/RAS0
/CAS0
/RAS2
/CAS4
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
DQ32 DQ
DQ0
DQ
DQ
DQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33 DQ
DQ34 DQ
DQ35 DQ
DQ36 DQ
DQ37 DQ
DQ38 DQ
DQ39 DQ
DQ
DQ
D0
D4
DQ
DQ
DQ
/CAS1
/CAS5
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
DQ40 DQ
DQ8
DQ9
DQ
DQ
DQ41 DQ
DQ42 DQ
DQ43 DQ
DQ44 DQ
DQ45 DQ
DQ46 DQ
DQ47 DQ
DQ10 DQ
DQ11 DQ
DQ12 DQ
DQ13 DQ
DQ14 DQ
DQ15 DQ
D1
D5
/CAS2
/CAS6
/CAS /RAS /WE /OE
DQ16 DQ
/CAS /RAS /WE /OE
DQ48 DQ
DQ17 DQ
DQ18 DQ
DQ19 DQ
DQ20 DQ
DQ21 DQ
DQ22 DQ
DQ23 DQ
DQ49 DQ
DQ50 DQ
DQ51 DQ
DQ52 DQ
DQ53 DQ
DQ54 DQ
DQ55 DQ
D2
D6
/CAS3
/CAS7
/CAS /RAS /WE /OE
DQ24 DQ
/CAS /RAS /WE /OE
DQ56 DQ
DQ25 DQ
DQ26 DQ
DQ27 DQ
DQ28 DQ
DQ29 DQ
DQ30 DQ
DQ31 DQ
DQ57 DQ
DQ58 DQ
DQ59 DQ
DQ60 DQ
DQ61 DQ
DQ62 DQ
DQ63 DQ
D3
D7
A0-A9
A10
A0-A9 : D0-D7
A10R
Serial PD
SCL SCL
SDA SDA
A0 A1 A2
SA0 SA1 SA2
V
D0-D7
D0-D7
CC
C1-C8
V
SS
Semiconductor
MSC23V26457TD
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
-0.5 to 4.6
-0.5 to 4.6
50
Unit
V
Voltage on Any Pin Relative to V
V , V
IN OUT
SS
Voltage on V Supply Relative to V
V
CC
V
CC
SS
Short Circuit Output Current
Power Dissipation
IOS
mA
W
PD *
TOPR
8
Operating Temperature
Storage Temperature
0 to 70
-40 to 125
°C
°C
T
STG
* Ta = 25°C
Recommended Operating Conditions
( Ta = 0°C to 70°C )
Parameter
Symbol
Min.
3.0
0
Typ.
Max.
Unit
V
V
CC
3.3
0
3.6
0
Power Supply Voltage
V
SS
V
Input High Voltage
Input Low Voltage
V
2.0
-0.3
-
V +0.3
V
V
IH
CC
V
IL
-
0.8
Capacitance
( V = 3.3V ±0.3V, Ta = 25°C, f = 1 MHz )
CC
Parameter
Symbol
Typ.
Max.
49
Unit
pF
Input Capacitance (A0 - A10)
C
IN1
-
-
-
-
Input Capacitance (/RAS0, /RAS2, /WE0, /WE2, /OE0, /OE2)
Input Capacitance (/CAS0 - /CAS7)
CIN2
35
pF
C
IN3
13
pF
I/O Capacitance (DQ0 - DQ63)
C
I/O
13
pF
Semiconductor
MSC23V26457TD
DC Characteristics
(V = 3.3V ±0.3V, Ta = 0°C to 70°C )
CC
-50
-60
-70
Parameter
Symbol
Condition
Unit Note
Min. Max. Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
V
IOH = -2.0mA
IOL = 2.0mA
0V V V +0.3V;
All other pins not
under test = 0V
2.4
0
V
2.4
0
V
2.4
0
V
V
V
OH
CC
CC
CC
V
OL
0.4
80
0.4
80
0.4
80
≤
≤
IN
CC
Input Leakage Current
Output Leakage Current
ILI
-80
-10
-
-80
-10
-
-80
-10
-
A
A
µ
DQ disable
ILO
10
10
10
µ
0V V
V
≤
≤
OUT
CC
Average Power
Supply Current
(Operating)
/RAS, /CAS cycling,
RC = Min.
ICC1
800
720
640
mA 1, 2
mA
t
/RAS, /CAS = V
-
-
16
4
-
-
16
4
-
-
16
4
IH
Power Supply Current
(Standby)
ICC2
1
/RAS, /CAS
V -0.2V
mA
≥
CC
Average Power
Supply Current
(/RAS only refresh)
/RAS cycling,
ICC3
ICC6
ICC7
/CAS = V ,
-
-
-
800
800
800
-
-
-
720
720
720
-
-
-
640
640
640
mA 1, 2
mA 1, 2
mA 1, 3
IH
tRC = Min.
Average Power
Supply Current
(/CAS before /RAS refresh)
/RAS cycling,
/CAS before /RAS
Average Power
Supply Current
(Fast Page Mode)
/RAS = V ,
IL
/CAS cycling,
tHPC = Min.
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while /RAS = VIL.
3. The address can be changed once or less while /CAS = VIH.
Semiconductor
MSC23V26457TD
AC Characteristics (1/2)
(V = 3.3V ±0.3V, Ta = 0°C to 70°C ) Note: 1, 2, 3, 12, 13
CC
-50
-60
-70
Parameter
Symbol
Unit
Note
Min. Max. Min. Max. Min. Max.
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
tRC
tRWC
tHPC
tHPRWC
tRAC
tCAC
tAA
84
110
20
58
-
-
-
104
135
25
68
-
-
-
124
160
30
78
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
Fast Page Mode Read Modify Write Cycle Time
Access Time from /RAS
-
-
-
50
13
25
30
13
-
60
15
30
35
15
-
70
20
35
40
20
-
4, 5, 6
4, 5
4, 6
4
Access Time from /CAS
-
-
-
Access Time from Column Address
Access Time from /CAS Precharge
Access Time from /OE
-
-
-
tCPA
tOEA
tCLZ
tDOH
tCEZ
tREZ
tOEZ
tWEZ
tT
-
-
-
-
-
-
4
Output Low Impedance Time from /CAS
Data Output Hold After /CAS Low
/CAS to Data Output Buffer Turn-off Delay Time
/RAS to Data Output Buffer Turn-off Delay Time
/OE to Data Output Buffer Turn-off Delay Time
/WE to Data Output Buffer Turn-off Delay Time
Transition Time
0
0
0
4
5
-
5
-
5
-
0
13
13
13
13
50
32
-
0
15
15
15
15
50
32
-
0
20
20
20
20
50
32
-
7, 8
7, 8
7
0
0
0
0
0
0
0
0
0
7
1
1
1
3
Refresh Period
tREF
tRP
-
-
-
/RAS Precharge Time
30
50
50
7
40
60
50
70
/RAS Pulse Width
tRAS
tRASP
tRSH
tROH
tCP
10K
10K
10K
100K
-
/RAS Pulse Width (Fast Page Mode with EDO)
/RAS Hold Time
100K 60
100K 70
-
10
10
10
10
40
5
-
13
13
10
13
45
5
/RAS Hold Time referenced to /OE
/CAS Precharge Time (Fast Page Mode with EDO)
/CAS Pulse Width
7
-
-
-
7
-
-
-
tCAS
tCSH
tCRP
tRHCP
tCHO
tRCD
tRAD
tASR
tRAH
tASC
tCAH
tRAL
7
10K
10K
10K
-
/CAS Hold Time
35
5
-
-
-
-
/CAS to /RAS Precharge Time
/RAS Hold Time from /CAS Precharge
/OE Hold Time from /CAS (DQ Disable)
/RAS to /CAS Delay Time
-
30
5
-
35
5
-
40
5
-
-
-
-
11
9
37
25
-
14
12
0
45
30
-
14
12
0
50
35
-
5
6
/RAS to Column Address Delay Time
Row Address Set-up Time
0
Row Address Hold Time
7
-
10
0
-
10
0
-
Column Address Set-up Time
Column Address Hold Time
0
-
-
-
7
-
10
30
-
13
35
-
Column Address to /RAS Lead Time
25
-
-
-
Semiconductor
MSC23V26457TD
AC Characteristics (2/2)
(V = 3.3V ±0.3V, Ta = 0°C to 70°C ) Note: 1, 2, 3, 12, 13
CC
-50
-60
-70
Parameter
Symbol
Unit
Note
Min. Max. Min. Max. Min. Max.
Read Command Set-up Time
tRCS
tRCH
tRRH
tWCS
tWCH
tWP
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Command Hold Time
0
0
9
Read Command Hold Time referenced to /RAS
Write Command Set-up Time
0
0
0
9
0
0
0
10
Write Command Hold Time
7
10
10
10
10
10
10
10
10
0
13
10
10
13
10
10
13
13
0
Write Command Pulse Width
7
/WE Pulse Width (DQ Disable)
/OE Command Hold Time
tWPE
tOEH
tOEP
tOCH
tRWL
tCWL
tDS
7
7
/OE Precharge Time
7
/OE Command Hold Time
7
Write Command to /RAS Lead Time
Write Command to /CAS Lead Time
Data-in Set-up Time
7
7
0
11
11
Data-in Hold Time
tDH
7
10
15
34
49
79
54
5
13
20
44
59
94
64
5
/OE to Data-in Delay Time
tOED
tCWD
tAWD
tRWD
tCPWD
tRPC
tCSR
tCHR
tWRP
tWRH
tWTS
tWTH
13
30
42
67
47
5
/CAS to /WE Delay Time
10
10
10
10
Column Address to /WE Delay Time
/RAS to /WE Delay Time
/CAS Precharge /WE Delay Time
/CAS Active Delay Time from /RAS Precharge
/RAS to /CAS Set-up Time (/CAS before /RAS)
/RAS to /CAS Hold Time (/CAS before /RAS)
/WE to /RAS Precharge Time (/CAS before /RAS)
/WE Hold Time from /RAS (/CAS before /RAS)
/RAS to /WE Set-up Time (Test Mode)
/RAS to /WE Hold Time (Test Mode)
5
5
5
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
Semiconductor
MSC23V26457TD
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles
(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 2ns.
3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are
measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF.
The output timing reference levels are VOH = 2.0V and VOL = 0.8V.
5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met.
tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then
the access time is controlled by tCAC
.
6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the access time is controlled by tAA.
7. tCEZ(Max.), tREZ(Max.), tWEZ(Max.) and tOEZ(Max.) define the time at which the output achieves the open
circuit condition and are not referenced to output voltage levels.
8. tCEZ or tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS ≥ tWCS(Min.), then the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD(Min.), tRWD
≥ tRWD(Min.), tAWD ≥ tAWD(Min.) and tCPWD ≥ tCPWD(Min.), then the cycle is a read modify write cycle and
data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the /CAS leading edge in an early write cycle, and to the /WE
leading edge in an /OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin
will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low levels. The test
mode is cleared and the memory device returned to its normal operating state by performing a /RAS
only refresh cycle or a /CAS before /RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specified in test mode cycle by adding the above value to the specified
value in this data sheet.
相关型号：
©2020 ICPDF网 联系我们和版权申明