ML63295A-XXXGA [OKI]
4-Bit Microcontroller with Built-in 3072-Dot Matrix LCD Driver and Melody Circuit; 4 -bit微控制器内置3072点阵LCD驱动器和电路的旋律
| 型号： | ML63295A-XXXGA |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 4-Bit Microcontroller with Built-in 3072-Dot Matrix LCD Driver and Melody Circuit |
| 文件： | 总38页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL63295A-02
This version:
Previous version: Nov. 2000
Jul. 2001
1
Semiconductor
ML63295A
4-Bit Microcontroller with Built-in 3072-Dot Matrix LCD Driver and Melody Circuit
GENERAL DESCRIPTION
The ML63295A is a CMOS 4-bit microcontroller that employs Oki’s original CPU core nX-4/250.
The ML63295A operates on a power supply voltage of 6 V.
With built-in 3072-dot matrix LCD drivers (96 SEG. × 32 COM.), the ML63295A is suited for applications such as
electronic dictionaries with an LCD.
FEATURES
• Extensive instruction set
439 instructions:
Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations,
bit operations, ROM table reference, external memory transfer, stack operations, flag operations, jump,
conditional branch, call/return, control
• Wide variety of addressing modes
Indirect addressing mode for 4 types of data memory with current bank register, extra bank register,
HL register and XY register
Data memory bank internal direct addressing mode
• Processing speed
2 clocks per machine cycle, with most instructions executed in 1 machine cycle
Minimum instruction execution time : 61 µs (@ 32.768 kHz system clock)
: 1 µs (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock : Crystal oscillation or RC oscillation selected with mask option
(30 kHz to 80 kHz)
High-speed clock: Ceramic oscillation or RC oscillation selected with software
(2 MHz max)
• Program memory space
32 K words
Basic instruction length is 16 bits/1word.
• Data memory space
2048 nibbles
• External data memory space
64 Kbytes (expandable furthermore by using the I/O ports)
• Stack level
Call stack level
Register stack level
: 16 levels
: 16 levels
1/38
FEDL63295A-02
1Semiconductor
ML63295A
• Ports
Input ports:
Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
Output ports:
Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/CMOS
output.
I/O ports:
Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/
CMOS output.
Can be interfaced with external peripherals that use a different power supply than this device uses.
Number of ports:
Input port
Output port
Input-output port
: 2 ports × 4 bits
: 6 ports × 4 bits
: 6 ports × 4 bits
• Melody output
Melody frequency
Tone length
: 529 Hz to 2979 Hz
: 63 varieties
Tempo
: 15 varieties
Melody data
Buzzer driver signal output
: Stored in program memory
: 4 kHz
• LCD driver
Number of segments
Duty
: 3072 Max. (96 SEG. × 32 COM.)
: Selectable as 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14, 1/16, 1/18, 1/20,
1/22, 1/24, 1/26, 1/28, 1/30, or 1/32 duty
Bias
Frame frequency
: Selectable as 1/5 or 1/6 bias (regulator built-in)
: ex. 64 Hz (at 1/32 duty), 128 Hz (at 1/16 duty), 256 Hz (at 1/8
duty), 512 Hz (at 1/4 duty), 1024 Hz (at 1/2 duty)
: 16 levels adjustable
Contrast
Display modes
: Selectable as all-ON mode/all-OFF mode/power down
mode/normal display mode
• Multiplier/divider circuit
Multiplier
: (8 bits) × (8 bits) → Product (16 bits)
Divider
: (16 bits)/(8 bits) → Quotient (16 bits), Remainder (8 bits)
• System reset function
System reset through RESET pin
System reset by power-on detection
System reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
The value of the judgment voltage is selected by the software (by setting the LD1 and LD0 bits of
BLDCON).
LD1
1
LD0
0
Judgment voltage (V)
4.5 ±0.1
Remarks
Ta = 25°C
Ta = 25°C
1
1
5.1 ±0.1
2/38
FEDL63295A-02
1Semiconductor
ML63295A
• Timers and Counter
8-bit timer
: 2
Selectable as auto-reload mode/clock frequency measurement
mode
Watchdog timer
100 Hz timer
: 1
: 1
Measurable in steps of 1/100 sec.
: 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
15-bit time-base counter
• Serial port
Mode
: Selectable as UART mode, synchronous mode
: 1200 bps, 2400 bps, 4800 bps, 9600 bps
UART communication speed
Clock frequency in synchronous mode : Internal clock mode (32.768 kHz), External clock frequency
Data length
: 5 to 8 bits
• Shift register
Shift clock
Data length
: 1 × or 1/2 × system clock, external clock
: 8 bits
• Interrupt factors
External interrupt
: 5
Internal interrupt
• Operating temperature
• Power supply voltage
: 12
: –20 to +70°C
: 3.5 to 7.2 V
• Package:
Chip (212 pads)
: (Product name: ML63295A-xxxWA)
240-pin plastic QFP (QFP240-P-3232-0.50-BK4) : (Product name: ML63295A-xxxGA)
….under consideration
xxx indicates a code number.
3/38
FEDL63295A-02
1Semiconductor
ML63295A
BLOCK DIAGRAM
Asterisks (*) indicate the port secondary functions. Signal names enclosed by chain lines (
) indicate interface
signals of the VDDI power supply system. Signal names enclosed by
supply system.
indicates signals of the VDDE power
CPU core
CBR
nX-4/250
H
X
L
RA
PC
TIMING
CONT.
ROM
32 KW
EBR
Y
A
G
SP
C
Z
BUS
CONT.
ALU
D0-7*
EXTMEM
64 KB
RSP
MIE
A0-15*
INSTRUCTION
DECODER
STACK
CAL.S:16-level
REG.S:16-level
IR
R D *
W R *
INT
T2CK*
T3CK*
2
RAM
2048N
TIMER
8 bit (2ch)
INT
2
RXC*
TXC*
RXD*
TXD*
INT
SIO
INT
1
MULDIV
TBC
SCLK*
SIN*
RESET
RST
SFT
SOUT*
INT
4
INT
1
TST1
TST2
MD
TST
MELODY
MDB
INT
1
P0.0-P0.3
P1.0-P1.3
BLD
INPUT
PORT
XT0
XT1
OSC
OSC0
INT
1
P2.0-P2.3
P3.0-P3.3
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
P7.0-P7.3
100HzTC
W DT
OSC1
INT
1
OUTPUT
VDDX1
VDDX2
VDDX3
VDDX4
C1
INT
4
P8.0-P8.3
P9.0-P9.3
PA.0-PA.3
PB.0-PB.3
PC.0-PC.3
PE.0-PE.3
C2
BIAS
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
I/O
PORT
LCD
&
DSPR
COM1-COM32
SEG0-SEG95
VDD
VDDL
VDDE
VR
VDDI
VSS
4/38
FEDL63295A-02
1Semiconductor
ML63295A
PIN CONFIGURATION (TOP VIEW)
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
(NC)
(NC)
(NC)
(NC)
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
(NC)
(NC)
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
(NC)
(NC)
PE.3
PE.2
PE.1
PE.0
PC.3
PC.2
PC.1
PC.0
PB.3
PB.2
PB.1
PB.0
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P8.3
P8.2
P8.1
P8.0
P7.3
P7.2
P7.1
P7.0
P6.3
P6.2
P6.1
P6.0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
P1.3
P1.2
P1.1
P1.0
P0.3
(NC)
(NC)
(NC)
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
(NC)
(NC)
61
240-Pin Plastic QFP
(GA:QFP240-P-3232-0.50-BK4)
Note: Pins marked as (NC) are no-connection pins which are left open.
5/38
FEDL63295A-02
1Semiconductor
ML63295A
PAD CONFIGURATION
Pad Layout
109 SEG35
108 SEG34
107 SEG33
106 SEG32
SEG90
SEG91
SEG92
SEG93
SEG94
164
165
166
167
168
105
SEG31
104 SEG30
SEG29
SEG28
103
102
SEG95169
COM17
COM18
COM19
COM20
COM21
170
171
172
173
174
101 SEG27
100 SEG26
99
SEG25
98 SEG24
97 SEG23
96 SEG22
95 SEG21
94 SEG20
93 SEG19
92 SEG18
91 SEG17
90 SEG16
89 SEG15
88 SEG14
COM22175
COM23
COM24
COM25
COM26
COM27
176
177
178
179
180
COM28181
COM29
COM30
182
183
87
SEG13
Y
COM31184
86 SEG12
85 SEG11
COM32
185
186
187
188
V
SS
84
SEG10
V
V
V
V
V
V
DD1
DD2
83 SEG9
82 SEG8
81 SEG7
80 SEG6
79 SEG5
78 SEG4
77 SEG3
76 SEG2
75 SEG1
74 SEG0
73 COM16
72 COM15
71 COM14
70 COM13
69 COM12
68 COM11
67 COM10
66 COM9
65 COM8
64 COM7
63 COM6
62 COM5
61 COM4
60 COM3
59 COM2
58 COM1
X
DD3 189
( 0,0 )
DD4
DD5
DD6
190
191
192
V
DDX1 193
V
DDX2 194
V
DDX3 195
V
DDX4 196
C1 197
C2 198
V
DD 199
V
DDL 200
DD 201
V
V
DDE 202
OSC1 203
OSC0 204
TST1 205
TST2 206
XT1
207
XT0 208
RESET
209
MD 210
MDB
211
57
V
SS
V
DDI 212
56 P0.0
55 P0.1
54 P0.2
Chip size
: 8.25 mm × 8.20 mm
Chip thickness
Coordinate origin
Pad hole size
Pad size
: 350 µm (280 µm: available as required)
: center of chip
: 100 µm × 100 µm
: 110 µm × 110 µm
: 120 µm
Minimum pad pitch
Note: The chip substrate voltage is VSS.
6/38
FEDL63295A-02
1Semiconductor
ML63295A
Pad Coordinates
Center of chip: X = 0, Y = 0
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
1
PE.3
PE.2
PE.1
PE.0
PC.3
PC.2
PC.1
PC.0
PB.3
PB.2
PB.1
PB.0
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P8.3
P8.2
P8.1
P8.0
P7.3
P7.2
P7.1
P7.0
P6.3
P6.2
P6.1
P6.0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
–3138
–3018
–2898
–2778
–2658
–2538
–2418
–2298
–2178
–2058
–1938
–1818
–1698
–1578
–1458
–1338
–1218
–1098
–978
–858
–738
–618
–498
–378
–258
–138
–18
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
P4.0
P3.3
1542
1662
1782
1902
2022
2142
2262
2382
2502
2622
2742
2862
2982
3102
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3905
–3281
–3161
–3041
–2907
–2766
–2646
–2526
–2406
–2286
–2166
–2046
–1926
–1806
–1686
–1566
–1446
–1326
–1206
–1086
–966
2
3
P3.2
4
P3.1
5
P3.0
6
P2.3
7
P2.2
8
P2.1
9
P2.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
VSS
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG0
SEG1
SEG2
SEG3
SEG4
102
222
342
462
582
702
822
942
–846
1062
1182
1302
1422
–726
–606
–486
–366
7/38
FEDL63295A-02
1Semiconductor
ML63295A
Center of chip: X = 0, Y = 0
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
79
80
SEG5
SEG6
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3965
3185
3065
2945
2825
2705
2585
2465
2345
–246
–126
–6
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
2225
2105
1985
1865
1745
1625
1505
1385
1265
1145
1025
905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
3905
81
SEG7
82
SEG8
114
83
SEG9
234
84
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
354
85
474
86
594
87
714
88
834
89
954
90
1074
1194
1314
1434
1554
1674
1794
1914
2034
2154
2274
2394
2514
2634
2754
2874
2994
3114
3234
3354
3905
3905
3905
3905
3905
3905
3905
3905
91
785
92
665
93
545
94
425
95
305
96
185
97
65
98
–55
99
–175
–295
–415
–535
–655
–775
–895
–1015
–1135
–1255
–1375
–1495
–1615
–1735
–1855
–1975
–2095
–2215
–2335
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
8/38
FEDL63295A-02
1Semiconductor
ML63295A
Center of chip: X = 0, Y = 0
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
–2455
–2575
–2695
–2815
–2935
–3055
–3175
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
3905
3905
3905
3905
3905
3905
3905
3432
3312
3192
3072
2952
2832
2712
2592
2472
2352
2232
2112
1992
1872
1752
1632
1512
1392
1272
1152
1032
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
COM32
VSS
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
–3965
912
730
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDDX1
VDDX2
VDDX3
VDDX4
C1
580
430
280
130
–20
–170
–320
–470
–620
–770
–920
–1070
–1220
–1370
–1520
–1670
–1924
–2074
–2268
–2388
–2593
–2743
–2912
–3120
–3240
–3392
C2
VDD
VDDL
VDD
VDDE
OSC1
OSC0
TST1
TST2
XT1
XT0
RESET
MD
MDB
VDDI
9/38
FEDL63295A-02
1Semiconductor
ML63295A
PIN DESCRIPTIONS
The basic functions of each pin of the ML63295A are described in Table 1.
A symbol with a slash “/” denotes a pin that has a secondary function. Refer to Table 2 for secondary functions.
For type, “—” denotes a power supply pin, “I” an input pin, “O” an output pin, and “I/O” an input-output pin.
Table 1 Pin Descriptions (Basic Functions)
Function
Symbol
Pin No.
Pad No.
Type
Description
Positive power supply pin
VDD
VSS
164, 166
6, 144
145
199, 201
57, 186
187
—
—
Negative power supply pin
VDD1
VDD2
VDD4
VDD5
VDD6
VDDX1
Power supply pins for LCD bias voltage (internally
generated):
146
188
Capacitors (1.0 µF) should be connected between
these pins and VSS.
149
190
—
150
191
151
192
153
193
—
—
Positive power supply for low-speed oscillation.
Power supply pins for LCD bias voltage generation:
Capacitors (1.0 µF) should be connected between
these pins and VSS.
VDD3
147
157
189
196
VDDX4
C1
C2
158
159
154
155
197
198
194
195
Capacitor connection pins for LCD bias voltage
generation:
A capacitor (1.0 µF) should be connected between
Power
Supply
—
—
VDDX2
VDDX3
C1 and C2, and between VDDX2 and VDDX3
.
Positive power supply pin for external interface
(Power supply for input, output, and input-output
VDDI
VDDL
VDDE
179
165
167
212
200
202
—
—
—
ports)
Positive power supply pin for internal logic
(internally generated):
A capacitor (0.1 µF) should be connected between
this pin and VSS.
Constant voltage output pin:
A capacitor (1.0 µF) should be connected between
this pin and VSS.
Low-speed clock oscillation pins:
An option for using crystal oscillation or RC
oscillation is chosen by the mask option.
If the crystal oscillation is chosen, a crystal should
be connected between XT0 and XT1, and capacitor
(CG) should be connected between XT0 and VSS.
If the RC oscillation is chosen, external oscillation
resistor (ROSL) should be connected between XT0
and XT1.
XT0
XT1
174
173
208
207
I
Oscillation
O
10/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No. Pad No. Type
Description
High-speed clock oscillation pins:
OSC0
OSC1
TST1
TST2
169
168
171
172
204
203
205
206
I
O
I
A ceramic resonator and capacitors (CL0, CL1) or
external oscillation resistor (ROSH) should be
connected to these pins.
Oscillation
Input pins for testing.
A pull-down resistor is internally connected to these
pins.
Test
I
System reset input pin.
Setting this pin to “H” level puts this device into a
reset state. Then, setting this pin to “L” level starts
executing an instruction from address 0000H.
A pull-down resistor is internally connected to this
pin.
Reset
RESET
175
209
I
Melody output pin (non-inverted output)
Melody output pin (inverted output)
MD
177
178
210
211
O
O
Melody
MDB
11/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
5
Pad No.
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Type
I
Description
P0.0/INT5
P0.1/INT5
P0.2/INT5
P0.3/INT5
P1.0/INT5
P1.1/INT5
P1.2/INT5
P1.3/INT5
P2.0
4-bit input ports:
Pull-up resistor input, pull-down resistor input,
or high-impedance input is selectable for each
bit.
4
3
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
I
4-bit output ports:
P-channel open drain output, N-channel open
drain output, CMOS output, or high-impedance
output is selectable for each bit.
P2.1
O
P2.2
P2.3
P3.0
P3.1
O
P3.2
P3.3
P4.0/A0
P4.1/A1
P4.2/A2
P4.3/A3
P5.0/A4
P5.1/A5
P5.2/A6
P5.3/A7
P6.0/A8
P6.1/A9
P6.2/A10
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15
P8.0/RD
P8.1/WR
P8.2
O
Port
O
O
O
4-bit input-output ports:
In input mode, pull-up resistor input, pull-down
resistor input, or high-impedance input is
selectable for each bit.
I/O
I/O
P8.3/INT4
P9.0/D0
P9.1/D1
P9.2/D2
P9.3/D3
In output mode, P-channel open drain output,
N-channel open drain output, CMOS output, or
high-impedance output is selectable for each
bit.
12/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
200
Pad No.
16
Type
I/O
Description
4-bit input-output ports:
PA.0/D4
PA.1/D5
PA.2/D6
PA.3/D7
PB.0/INT0
PB.1/INT0
PB.2/INT0/
T2CK
In input mode, pull-up resistor input, pull-
down resistor input, or high-impedance
input is selectable for each bit.
199
15
198
14
197
13
In output mode, P-channel open drain
output, N-channel open drain output, CMOS
output, or high-impedance output is
selectable for each bit.
196
12
195
11
194
193
10
9
I/O
PB.3/INT0/
T3CK
PC.0/INT1/
RXD
192
191
190
189
188
187
186
185
8
7
6
5
4
3
2
1
Port
PC.1/INT1/
TXC
I/O
PC.2/INT1/
RXC
PC.3/INT1/
TXD
PE.0/SIN
PE.1/SOUT
PE.2/SCLK
PE.3/INT2
I/O
13/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
7
Pad No.
58
Type
Description
LCD common signal output pins
COM1
COM2
8
59
COM3
9
60
COM4
10
61
COM5
11
62
COM6
12
63
COM7
13
64
COM8
14
65
COM9
15
66
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
16
67
17
68
18
69
19
70
20
71
21
72
22
73
LCD
O
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
14/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
64
65
66
67
68
69
70
71
72
73
74
Pad No.
74
Type
Description
LCD segment signal output pins
SEG0
SEG1
75
SEG2
76
SEG3
77
SEG4
78
SEG5
79
SEG6
80
SEG7
81
SEG8
82
SEG9
83
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
84
85
86
87
88
89
90
91
92
93
94
95
96
LCD
97
O
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
15/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Pad No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
Type
Description
LCD segment signal output pins
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
LCD
99
O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
122
123
124
125
126
127
16/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 2 shows the secondary functions of each pin of the ML63295A.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin No.
196
Pad No.
12
Type
Description
External 0 interrupt input pins
PB.0/INT0
PB.1/INT0
PB.2/INT0
The change of input signal level causes an
interrupt to occur.
195
11
I
194
10
The Port B Interrupt Enable register (PBIE)
enables or disables an interrupt for each bit.
PB.3/INT0
193
9
External 1 interrupt input pins
PC.0/INT1
PC.1/INT1
PC.2/INT1
192
191
190
8
7
6
The change of input signal level causes an
interrupt to occur.
I
The Port C Interrupt Enable register (PCIE)
enables or disables an interrupt for each bit.
PC.3/INT1
189
5
External 2 interrupt input pin
PE.3/INT2
185
1
I
I
The change of input signal level causes an
interrupt to occur.
External
Interrupt
External 4 interrupt input pin
P8.3/INT4
205
21
The change of input signal level causes an
interrupt to occur.
P0.0/INT5
P0.1/INT5
P0.2/INT5
P0.3/INT5
P1.0/INT5
P1.1/INT5
P1.2/INT5
P1.3/INT5
PB.2/T2CK
PB.3/T3CK
5
56
55
54
53
52
51
50
49
10
9
External 5 interrupt input pins
The change of input signal level causes an
interrupt to occur.
4
3
The Port 0 Interrupt Enable register (P0IE)
and Port 1 Interrupt Enable register (P1IE)
enable or disable an interrupt for each bit.
237
236
235
234
233
194
193
I
I
I
External clock input pin for timer 2
External clock input pin for timer 3
Timer
17/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
Symbol
Pin No. Pad No.
Type
I
Description
PC.0/RXD
192
191
8
7
Serial port receive data input pin
Sync serial port clock input-output pin
Transmit clock output when this device is used as a
master processor.
Transmit clock input when this device is used as a
slave processor.
PC.1/TXC
PC.2/RXC
I/O
I/O
Serial
Port
Sync serial port clock input-output pin
Receive clock output when this device is used as a
master processor.
190
6
Receive clock input when this device is used as a
slave processor.
PC.3/TXD
PE.0/SIN
189
188
187
5
4
3
O
I
Serial port transmit data output pin
Shift register receive data input pin
Shift register transmit data output pin
Shift register clock input-output pin.
Clock output when this device is used as a master
processor.
PE.1/SOUT
O
Shift
Register
PE.2/SCLK
186
2
I/O
Clock input when this device is used as a slave
processor.
P4.0/A0
P4.1/A1
P4.2/A2
P4.3/A3
P5.0/A4
P5.1/A5
P5.2/A6
P5.3/A7
P6.0/A8
P6.1/A9
P6.2/A10
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15
P9.0/D0
P9.1/D1
P9.2/D2
P9.3/D3
PA.0/D4
PA.1/D5
PA.2/D6
PA.3/D7
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
204
203
202
201
200
199
198
197
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
20
19
18
17
16
15
14
13
Address output bus for external memory
O
External
Memory
Data bus for external memory
I/O
Read signal output pin for external memory
(negative logic)
P8.0/RD
P8.1/WR
208
207
24
23
O
O
Write signal output pin for external memory
(negative logic)
18/38
FEDL63295A-02
1Semiconductor
ML63295A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
VDD1
Condition
Ta = 25°C
Rating
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
Power Supply Voltage 1
Power Supply Voltage 2
Power Supply Voltage 3
Power Supply Voltage 4
Power Supply Voltage 5
Power Supply Voltage 6
Power Supply Voltage 7
Power Supply Voltage 8
Power Supply Voltage 9
Power Supply Voltage 10
Power Supply Voltage 11
Power Supply Voltage 12
Input Voltage 1
–0.3 to +1.5
VDD2
Ta = 25°C
–0.3 to +2.5
VDD3
Ta = 25°C
–0.3 to +6.5
VDD4
Ta = 25°C
–0.3 to +4.5
VDD5
Ta = 25°C
–0.3 to +5.5
VDD6
Ta = 25°C
–0.3 to +6.5
VDDX1
VDDX4
VDD
Ta = 25°C
–0.3 to +2.0
Ta = 25°C
–0.3 to +6.5
Ta = 25°C
–0.3 to +7.5
VDDI
Ta = 25°C
–0.3 to +6.0
VDDL
Ta = 25°C
–0.3 to +6.0
VDDE
VIN1
Ta = 25°C
–0.3 to +6.0
VDD input, Ta = 25°C
VDDI input, Ta = 25°C
VDD1 output, Ta = 25°C
VDD2 output, Ta = 25°C
VDD3 output, Ta = 25°C
VDD4 output, Ta = 25°C
VDD5 output, Ta = 25°C
VDD6 output, Ta = 25°C
VDDX1 output, Ta = 25°C
VDDX4 output, Ta = 25°C
VDD output, Ta = 25°C
VDDI output, Ta = 25°C
VDDE output, Ta = 25°C
—
–0.3 to VDD + 0.3
–0.3 to VDDI + 0.3
–0.3 to VDD1 + 0.3
–0.3 to VDD2 + 0.3
–0.3 to VDD3 + 0.3
–0.3 to VDD4 + 0.3
–0.3 to VDD5 + 0.3
–0.3 to VDD6 + 0.3
–0.3 to VDDX1 + 0.3
–0.3 to VDDX4 + 0.3
–0.3 to VDD + 0.3
–0.3 to VDDI + 0.3
–0.3 to VDDE + 0.3
–55 to +150
Input Voltage 2
VIN2
Output Voltage 1
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT11
VOUT12
VOUT13
TSTG
Output Voltage 2
Output Voltage 3
Output Voltage 4
Output Voltage 5
Output Voltage 6
Output Voltage 7
Output Voltage 8
Output Voltage 9
Output Voltage 10
Output Voltage 11
Storage Temperature
19/38
FEDL63295A-02
1Semiconductor
ML63295A
RECOMMENDED OPERATING CONDITIONS
(VSS = 0 V)
Parameter
Symbol
TOP
Condition
—
Range
–20 to +70
3.5 to 7.2
1.8 to 5.5
Unit
°C
V
Operating Temperature
VDD
—
Operating Voltage
VDDI
fXT
—
V
Crystal Oscillation Frequency
CG = 5 to 25 pF
ROSL = 1.5 MΩ
ROSL = 700 kΩ
ROSL = 500 kΩ
32.768 to 76.8
32 k ±30%
60 k ±30%
80 k ±30%
kHz
Hz
Low-speed RC Oscillation
Frequency
fROSL
Ceramic Oscillation
Frequency
fCM
VDD = 3.5 to 7.2 V
200 k to 2 M
Hz
Hz
ROSH = 100 kΩ
700 k ±30%
1 M ±30%
ROSH = 75 kΩ
ROSH = 51 kΩ
ROSH = 30 kΩ
High-speed RC Oscillation
Frequency
fROSH
VDD = 3.5 to 7.2 V
1.35 M ±30%
2 M ±30%
20/38
FEDL63295A-02
1Semiconductor
ML63295A
Typical characteristics of low-speed RC oscillation
(VDD = 6.0 V, VDDI = 3.0 V)
Reference data
1000
100
10
100
1000
10000
ROSL [k ]
Ω
Typical characteristics of high-speed RC oscillation
(VDD = 6.0 V, VDDI = 3.0 V)
Reference data
10000
1000
100
10
100
1000
Ω
ROSH[k ]
21/38
FEDL63295A-02
1Semiconductor
ML63295A
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD = 3.5 to 7.2 V, VDDI = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Meas-
Parameter
Symbol
VDDE
Condition
Min.
2.7
—
Typ.
3.0
Max.
3.3
—
Unit
V
uring
Circuit
VDDE Voltage
IOUT = 0 to 15 mA, Ta = 25°C
—
VDDE Voltage
Temperature
Deviation
∆VDDE
–4.0
mV/°C
High-speed clock oscillation
stopped
1.0
1.2
1.5
—
2.0
3.3
VDDL Voltage
VDDL
During operation at high-speed
clock oscillation
(VDD = 3.5 to 7.2 V)
V
Crystal Oscillation
Start Voltage
Oscillation start time:
within 5 seconds
VSTA
VHOLD
TSTOP
3.5
3.5
0.1
—
—
—
—
—
Crystal Oscillation
Hold Voltage
—
—
Crystal Oscillation
Stop Detect Time
5.0
ms
1
External RC
Oscillator
Capacitance
CG
CD
—
—
5
20
—
8
—
25
30
12
25
30
—
16
Internal RC
Oscillator
Capacitance
pF
External Ceramic
Oscillator
Capacitance
CSA2.00MG
(Murata MFG.-make) used
CL0, CL1
V
DDE = 3.0 V
Internal RC
Oscillator
COS
—
Capacitance
POR Voltage
VPOR1
VPOR2
VDD = 6.0 V
VDD = 6.0 V
0
—
—
0.7
6.0
V
V
Non-POR Voltage
2.0
LD1 = 1, LD0 = 1, Ta = 25°C
LD1 = 1, LD0 = 0, Ta = 25°C
VBLDC = 5.10 V
5.00
4.40
5.10
4.50
5.20
4.60
BLD Judgment
Voltage
VBLDC
BLD Judgment
Voltage
Temperature
Deviation
—
—
–3.5
–2.3
—
—
—
(LD1 = 1, LD0 = 1)
VBLDC = 4.50 V
∆VBLDC
mV/°C
(LD1 = 1, LD0 = 0)
Notes: 1. “TSTOP” indicates that if the crystal oscillator stops over the value of TSTOP, the system reset
occurs.
2. “POR” denotes Power On Reset.
3. “VPOR1” indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises up to VDD
4. “VPOR2” indicates that POR does not occur when VDD falls from VDD to VPOR2 and again rises
up to VDD.
22/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (2)
(VDD = 6.0 V, VDDI = 3.0 V, VSS = 0 V, 1/6 bias, DSPCNT = 0H, Ta = –20 to +70°C unless otherwise specified)
Meas-
Parameter Symbol
Condition
Min. Typ. Max. Unit
uring
Circuit
CPU in HALT state,
LCD is being driven,
no panel load
(Crystal oscillation: 32.768 kHz)
(High-speed clock oscillation
stopped)
Ta = –20 to +50°C
Ta = –20 to +70°C
Ta = –20 to +50°C
Ta = –20 to +70°C
—
—
—
—
11.0 14.5
11.0 19.5
14.5 18.0
14.5 23.0
Supply
IDD1
Current 1
CPU in HALT state,
LCD is being driven,
no panel load
(RC oscillation: ROSL = 1.5 MΩ)
(High-speed clock oscillation
stopped)
CPU in HALT state,
Ta = –20 to +50°C
Ta = –20 to +70°C
Ta = –20 to +50°C
Ta = –20 to +70°C
—
—
—
—
4.0 5.0
4.0 6.5
7.0 8.0
7.0 9.5
LCD in Power Down mode
(Crystal oscillation: 32.768 kHz)
(High-speed clock oscillation
stopped)
Supply
IDD2
Current 2
CPU in HALT state,
LCD in Power Down mode
(RC oscillation: ROSL = 1.5 MΩ)
(High-speed clock oscillation
stopped)
µA
1
CPU operating at low speed,
LCD is being driven,
no panel load
(Crystal oscillation: 32.768 kHz)
(High-speed clock oscillation
stopped)
Ta = –20 to +50°C
Ta = –20 to +70°C
Ta = –20 to +50°C
Ta = –20 to +70°C
—
—
—
20.5 29.0
20.5 34.0
24.5 33.0
Supply
IDD3
Current 3
CPU operating at low speed,
LCD is being driven,
no panel load
(RC oscillation: ROSL = 1.5 MΩ)
(High-speed clock oscillation
stopped)
—
—
—
24.5 38.0
1100 1700
1500 2000
CPU operating at high-speed oscillation
(1 MHz RC oscillation, ROSH = 75 kΩ)
CPU operating at high-speed oscillation
(2 MHz ceramic oscillation)
Supply
IDD4
Current 4
Supply
IDD5
Current 5
23/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (3)
(VDD = 3.5 to 7.2 V, VDDI = 1.8 to 5.5 V, VSS = 0 V, Ta = 25°C unless otherwise specified)
Meas-
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
uring
Circuit
VDD6 Voltage
VDD5 Voltage
VDD6
VDD5
1/6 bias, 1/5 bias
1/6 bias
4.0
4.1
4.2
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
5/6 × VDD6
4/5 × VDD6
4/6 × VDD6
3/5 × VDD6
2/6 × VDD6
2/5 × VDD6
1/6 × VDD6
1/5 × VDD6
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
1/5 bias
1/6 bias
VDD4 Voltage
VDD2 Voltage
VDD1 Voltage
VDD4
VDD2
VDD1
1/5 bias
V
1
1/6 bias
1/5 bias
1/6 bias
1/5 bias
Note: “VDD6” changes in the range from 4.10 to 6.14 V (Typ. value) according to the value of Display
Contrast register (DSPCNT).
(VDD = 3.5 to 7.2 V, VDDI = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Meas-
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
uring
Circuit
VDDE Voltage
Temperature Deviation
VDD6 Voltage
∆VDDE
VDD6
—
—
–4.0
4.1
—
mV/°C
1/6 bias, 1/5 bias
1/6 bias
3.6
4.6
Typ.–0.5 5/6 × VDD6 Typ.+0.5
Typ.–0.5 4/5 × VDD6 Typ.+0.5
Typ.–0.5 4/6 × VDD6 Typ.+0.5
Typ.–0.5 3/5 × VDD6 Typ.+0.5
Typ.–0.5 2/6 × VDD6 Typ.+0.5
Typ.–0.5 2/5 × VDD6 Typ.+0.5
Typ.–0.5 1/6 × VDD6 Typ.+0.5
Typ.–0.5 1/5 × VDD6 Typ.+0.5
VDD5 Voltage
VDD4 Voltage
VDD2 Voltage
VDD1 Voltage
VDD5
1/5 bias
1/6 bias
1
VDD4
VDD2
VDD1
1/5 bias
V
1/6 bias
1/5 bias
1/6 bias
1/5 bias
Note: “VDD6” changes in the range from 4.10 to 6.14 V (Typ. value) according to the value of Display
Contrast register (DSPCNT).
24/38
FEDL63295A-02
1Semiconductor
ML63295A
• Contrast voltage (VDD6 voltage)
Ta = 25°C, VDD6 = 4.1 V (Typ.)
Display Contrast
DSPCNT
VDD6 Voltage (V)
CN0 to CN3
0H
CN3
0
CN2
0
CN1
0
CN0
0
Min.
—
Typ.
4.1
Max.
—
Light
1H
0
0
0
1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
4.2
4.3
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
2H
0
0
1
0
3H
0
0
1
1
4.4
4H
0
1
0
0
4.5
5H
0
1
0
1
4.62
4.74
4.86
5.00
5.14
5.29
5.44
5.60
5.77
5.95
6.14
6H
0
1
1
0
7H
0
1
1
1
8H
1
0
0
0
9H
1
0
0
1
0AH
0BH
0CH
0DH
0EH
0FH
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Dark
Ta = 25°C, VDD6 = 4.0 V (Min.)
Display Contrast
DSPCNT
VDD6 Voltage (V)
CN0 to CN3
0H
CN3
0
CN2
0
CN1
0
CN0
0
Min.
—
Typ.
4.0
Max.
—
Light
1H
0
0
0
1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
4.1
4.2
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
2H
0
0
1
0
3H
0
0
1
1
4.3
4H
0
1
0
0
4.4
5H
0
1
0
1
4.52
4.64
4.76
4.90
5.04
5.19
5.34
5.50
5.67
5.85
6.04
6H
0
1
1
0
7H
0
1
1
1
8H
1
0
0
0
9H
1
0
0
1
0AH
0BH
0CH
0DH
0EH
0FH
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Dark
25/38
FEDL63295A-02
1Semiconductor
ML63295A
• Contrast voltage (VDD6 voltage)
Ta = 25°C, VDD6 = 4.2 V (Max.)
DSPCNT
VDD6 Voltage (V)
Display Contrast
Max.
CN0 to CN3
0H
CN3
0
CN2
0
CN1
0
CN0
0
Min.
—
Typ.
4.2
—
Light
1H
0
0
0
1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
Typ.–0.1
4.3
4.4
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
Typ.+0.1
2H
0
0
1
0
3H
0
0
1
1
4.5
4H
0
1
0
0
4.6
5H
0
1
0
1
4.72
4.84
4.96
5.10
5.24
5.39
5.54
5.70
5.87
6.05
6.24
6H
0
1
1
0
7H
0
1
1
1
8H
1
0
0
0
9H
1
0
0
1
0AH
0BH
0CH
0DH
0EH
0FH
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Dark
26/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (4)
(VDD = 6.0 V, VDDI = VDDE = 3.0 V, VDD1 = 1.0 V, VDD2 = 2.0 V, VDD3 = 3.0 V, VDD4 = 4.0 V,
VDD5 = 5.0 V, VDD6 = 6.0 V, Ta = –20 to +70°C unless otherwise specified)
Meas-
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
uring
Circuit
Output Current 1
(P2.0 to P2.3)
VDDI = 3.0 V
DDI = 5.0 V
–6.0
–8.5
–3.5
–5.0
–1.0
–1.5
IOH1
VOH1 = VDDI – 0.5 V
V
VDDI = 3.0 V
VDDI = 5.0 V
1.0
1.5
3.0
3.7
6.0
8.5
(PC.0 to PC.3)
(PE.0 to PE.3)
IOL1
VOL1 = 0.5 V
mA
IOH2
IOL2
VOH2 = VDDE – 0.7 V
VOL2 = 0.7 V
VDDE = 3.0 V –11.0
–6.0
5.5
—
–2.0
11.0
–4
—
Output Current 2
(MD, MDB)
VDDE = 3.0 V
2.0
—
4
IOH3
VOH3 = VDD6 – 0.2 V (VDD6 level)
VOHM3 = VDD5 + 0.2 V (VDD5 level)
VOHM3S = VDD5 – 0.2 V (VDD5 level)
VOMH3 = VDD4 + 0.2 V (VDD4 level)
VOMH3S = VDD4 – 0.2 V (VDD4 level)
VOML3 = VDD2 + 0.2 V (VDD2 level)
VOML3S = VDD2 – 0.2 V (VDD2 level)
VOLM3 = VDD1 + 0.2 V (VDD1 level)
VOLM3S = VDD1 – 0.2 V (VDD1 level)
VOL3 = VSS + 0.2 V (VSS level)
VOH4R = VDDE – 0.5 V
IOHM3
IOHM3S
IOMH3
IOMH3S
IOML3
IOML3S
IOLM3
IOLM3S
IOL3
—
—
4
—
–4
—
—
Output Current 3
(SEG0 to SEG95)
(COM1 to COM32)
—
4
—
–4
—
µA
—
—
4
—
–4
—
—
2
—
4
—
–4
—
—
IOH4R
IOL4R
IOH4C
IOL4C
V
V
V
DDE = 3.0 V –2.50 –1.30 –0.25
(RC oscillation)
mA
VOL4R = 0.5 V
(RC oscillation)
DDE = 3.0 V
DDE = 3.0 V
0.25
–300
60
1.50
–120
120
2.50
–60
300
Output Current 4
(OSC1)
VOH4C = VDDE – 0.5 V
(ceramic oscillation)
VOL4C = 0.5 V
(ceramic oscillation)
VDDE = 3.0 V
Output Leakage
Current
(P2.0 to P2.3)
µA
IOOH
VOH = VDDI
—
—
—
0.3
—
IOOL
VOL = VSS
–0.3
(PC.0 to PC.3)
(PE.0 to PE.3)
27/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (5)
(VDD = 6.0 V, VDDI = VDDE = 3.0 V, VDD1 = 1.0 V, VDD2 = 2.0 V, VDD3 = 3.0 V, VDD4 = 4.0 V,
VDD5 = 5.0 V, VDD6 = 6.0 V, Ta = –20 to +70°C unless otherwise specified)
Meas-
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
uring
Circuit
Input Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
VDDI = 3.0 V
VDDI = 5.0 V
VDDI = 3.0 V
VDDI = 5.0 V
10
20
20
60
40
VIH1 = VDDI
(when pulled down)
IIH1
120
–10
–20
1.0
–40
–120
0
–20
–60
—
VIL1 = VSS
(when pulled up)
IIL1
IIH1Z
IIL1Z
VIH1 = VDDI (in a high impedance state)
VIL1 = VSS (in a high impedance state)
VIL2 = VSS
(PC.0 to PC.3)
(PE.0 to PE.3)
–1.0
—
0
IIL2
VDDE = 3.0 V
–350 –170
–30
µA
(when pulled up)
3
IIH2R
IIL2R
IIH2C
IIL2C
IIH3
VIH2R = VDDE (RC oscillation)
VIL2R = VSS (RC oscillation)
0
—
—
1.0
0
Input Current 2
(OSC0)
–1.0
0.1
VIH2R = VDDE (ceramic oscillation)
VIL2R = VSS (ceramic oscillation)
0.5
–0.5
60
1.0
–0.1
150
0
–1.0
40
VIH3 = VDD
VIL3 = VSS
VIH4 = VDD
VIL4 = VSS
VDD = 6.0 V
Input Current 3
(RESET)
IIL3
–1.0
4.0
—
IIH4
VDD = 6.0 V
12.0
—
16.0
0
mA
Input Current 4
(TST1, TST2)
IIL4
–1.0
µA
28/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (6)
(VDD = 6.0 V, VDDI = VDDE = 3.0 V, VDD1 = 1.0 V, VDD2 = 2.0 V, VDD3 = 3.0 V, VDD4 = 4.0 V,
VDD5 = 5.0 V, VDD6 = 6.0 V, Ta = –20 to +70°C unless otherwise specified)
Meas-
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
uring
Circuit
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
VDDI = 3.0 V
VDDI = 5.0 V
VDDI = 3.0 V
VDDI = 5.0 V
2.3
3.8
0
—
—
—
—
3.0
5.0
0.7
1.2
VIH1
VIL1
(PC.0 to PC.3)
(PE.0 to PE.3)
0
VIH2
VIL2
VIH3
VIL3
2.4
0
—
—
—
—
3.0
0.6
Input Voltage 2
(OSC0)
VDDE = 3.0 V
VDD = 6.0 V
4.8
0
6.0
1.2
Input Voltage 3
(RESET, TST1, TST2)
V
4
Hysteresis Width 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
VDDI = 3.0 V
0.2
0.5
1.0
∆VT1
∆VT2
CIN
VDDI = 5.0 V
VDD = 5.0 V
0.25
0.25
1.00
1.00
1.50
1.50
(PC.0 to PC.3)
(PE.0 to PE.3)
Hysteresis Width 2
(RESET, TST1, TST2)
Input Pin Capacitance
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
—
—
—
5
pF
—
(PC.0 to PC.3)
(PE.0 to PE.3)
29/38
FEDL63295A-02
1Semiconductor
ML63295A
Measuring circuit 1
3
XT0
XT1
(*2)
C1
4
C12
C2
CX1
OSC0
1
2
VDDX1
VDDX2
VDDX3
VDDX4
CX23
(*1)
OSC1
CX4
VSS VDD VDDE VDDI VDD1
CXE Ca
VDD2
Cb
VDD3
Cc
VDD4
Cd
VDD5
Ce
VDD6
Cf
VDDL
CI
A
V
V
V
V
V
V
V
*2 RC Oscillator
3
*1 RC Oscillator
ROSH
CX1, CX23, CX4, CXE
Ca, Cb, Cc, Cd, Ce, Cf, C12
Cl
CG
CL0
CL1
: 1.0 µF
: 1.0 µF
: 0.1 µF
: 15 pF
: 30 pF
: 30 pF
1
ROSL
4
2
Ceramic resonator
: CSA2.00MG (2 MHz)
: CSB1000J (1 MHz)
(Murata MFG-.make)
Crystal Oscillator
Ceramic Oscillator
CG
CL0
3
1
Ceramic resonator
4
2
CL1
32.768 kHz
crystal
30/38
FEDL63295A-02
1Semiconductor
ML63295A
Measuring circuit 2
*4
VIH
A
INPUT
OUTPUT
*3
VIL
VSS VDD VDDE VDDI VDD1 VDD2 VDD4 VDD5 VDD6 VDDL
*3 Input logic circuit to determine the specified measuring conditions.
*4 Measured at the specified output pins.
Measuring circuit 3
*5
INPUT
OUTPUT
A
VSS VDD VDDE VDDI VDD1 VDD2 VDD4 VDD5 VDD6 VDDL
Measuring circuit 4
VIH
Waveform
Monitoring
INPUT
OUTPUT
*5
VIL
VSS VDD VDDE VDDI VDD1 VDD2 VDD4 VDD5 VDD6 VDDL
*5 Measured at the specified input pins.
31/38
FEDL63295A-02
1Semiconductor
ML63295A
AC Characteristics (Serial Interface, Serial Port)
(1) Synchronous Communication
(VDD = 3.5 to 7.2 V,VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Symbol
tf
Condition
Min. Typ. Max. Unit
TXC/RXC Input Fall Time
—
—
—
—
—
—
—
—
—
1.0
1.0
—
TXC/RXC Input Rise Time
tr
TXC/RXC Input “L” Level Pulse Width
TXC/RXC Input “H” Level Pulse Width
TXC/RXC Input Cycle Time
tCWL
tCWH
tCYC
0.8
0.8
2.0
—
—
—
—
—
—
µs
tCYC1 (O) CPU operating at 32.768 kHz
30.5
0.5
—
TXC/RXC Output Cycle Time
TXD Output Delay Time
tCYC2 (O)
CPU operating at 2 MHz
—
—
Output load capacitance
10 pF
tDDR
—
—
0.4
RXD Input Setup Time
RXD Input Hold Time
tDS
tDH
—
—
0.5
0.8
—
—
—
—
Synchronous communication timing
(“H” level = 4.0 V, “L” level = 1.0 V)
tCYC
VDDI
VSS
TXC (PC.1)/
RXC (PC.2)
tr
tf
tCWH
tCWL
tDDR
tDDR
VDDI
VSS
TXD (PC.3)
tDS
tDH
tDS
VDDI
VSS
RXD (PC.0)
32/38
FEDL63295A-02
1Semiconductor
ML63295A
(2) UART Communication
Parameter
Transmit Baud Rate
Receive Baud Rate
Symbol
TBRT
Condition
Min.
Typ.
TBRT
RBRT
Max.
TBRT + TCR
BRT × 1.03
Unit
s
TBRT = 1/fBRT
TCR = 1/fOSC
TBRT – TCR
RBRT
RBRT = 1/fBRT
R
BRT × 0.97
R
fBRT: Baud rates (1200, 2400, 4800, 9600 bps)
UART communication timing
(“H” level = 4.0 V, “L” level = 1.0 V)
TBRT
VDDI
TXD (PC.3)
RXD (PC.0)
VSS
RBRT
VDDI
VSS
33/38
FEDL63295A-02
1Semiconductor
ML63295A
AC Characteristics (Serial Interface, Shift Register)
(VDD = 3.5 to 7.2 V, VDDI = 5.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Symbol
tf
Condition
Min.
—
Typ. Max.
Unit
SCLK Input Fall Time
—
—
—
1.0
1.0
—
SCLK Input Rise Time
tr
—
—
SCLK Input “L” Level Pulse Width
SCLK Input “H” Level Pulse Width
SCLK Input Cycle Time
tCWL
tCWH
tCYC
tCYC1(O)
tCYC2(O)
tDDR
tDS
—
0.8
0.8
1.8
—
—
—
VDDI = VDDE to 5.5 V
CPU operating at 32.768 kHz
CPU operating at 2 MHz
Output load capacitance 10 pF
—
—
—
—
—
µs
30.5
0.5
—
—
SCLK Output Cycle Time
—
—
SOUT Output Delay Time
SIN Input Setup Time
SIN Input Hold Time
—
0.4
—
0.5
0.8
—
tDH
—
—
—
AC characteristics timing
(“H” level = 4.0 V, “L” level = 1.0 V)
tCYC
VDDI
VSS
SCLK (PE.2)
tr
tf
tCWH
tCWL
tDDR
tDDR
VDDI
VSS
SOUT (PE.1)
tDS
tDH
tDS
VDDI
VSS
SIN (PE.0)
34/38
FEDL63295A-02
1Semiconductor
ML63295A
AC Characteristics (External Memory Interface)
(VDD = 3.5 to 7.2 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise specified)
(1)
For Reading from External Memory
(a) When the CPU operates at 32.768 kHz
Parameter
Read Cycle Time
Symbol
tRC
Condition
Min.
—
Typ.
61.0
—
Max.
—
Unit
—
—
—
—
RD Output Delay Time
Output Enable Time
tOE
—
5.0
5.0
5.0
µs
tOHA
tDO
—
—
External Memory Output Delay Time
—
—
(b) When the CPU operates at 2 MHz (VDD = 3.5 to 7.2 V)
Parameter
Read Cycle Time
Symbol
tRC
Condition
Min.
1.0
—
Typ.
—
Max.
—
Unit
—
—
—
—
µs
RD Output Delay Time
Output Enable Time
tOE
—
100
100
150
tOHA
tDO
—
—
ns
External Memory Output Delay Time
—
—
AC characteristics timing
(“H” level = 4.0 V, “L” level = 1.0 V)
MOVXB obj, xadr16
MOVXB obj, [RA]
S1
S2
S1
S2
S1
S2
System clock
tRC
VDDI
VSS
P7 to P4
(A15 to A0)
Port set value
Address output
Port set value
P8.0
(RD)
VDDI
VSS
tOHA
tOE
VDDI
VSS
PA, P9
(D7 to D0)
Port set value
Input data
tDO
Port set value
35/38
FEDL63295A-02
1Semiconductor
ML63295A
(2)
For Writing to External Memory
(a) When the CPU operates at 32.768 kHz
Parameter
Write Cycle Time
Symbol
tWC
Condition
Min.
—
Typ.
61.0
30.5
15.3
15.3
45.8
15.3
Max.
—
Unit
—
—
—
—
—
—
Address Setup Time
Write Time
tAS
—
—
tW
—
—
µs
Write Recovery Time
Data Setup Time
Data Hold Time
tWR
—
—
tDS
—
—
tDH
—
—
(b) When the CPU operates at 2 MHz (VDD = 3.5 to 7.2 V)
Parameter
Write Cycle Time
Symbol
tWC
Condition
Min.
1.0
0.4
0.2
0.2
0.7
0.2
Typ.
—
Max.
—
Unit
—
—
—
—
—
—
Address Setup Time
Write Time
tAS
—
—
tW
—
—
µs
Write Recovery Time
Data Setup Time
Data Hold Time
tWR
—
—
tDS
—
—
tDH
—
—
AC characteristics timing
(“H” level = 4.0 V, “L” level = 1.0 V)
MOVXB [RA], obj
MOVXB xadr16, obj
S1
S2
S1
S2
S1
S2
System clock
tWC
VDDI
P7 to P4
(A15 to A0)
Port set value
Port set value
Address output
Port set value
VSS
VDDI
VSS
PA, P9
(D7 to D0)
Output data
tDS
Port set value
tDH
VDDI
VSS
P8.1
(WR)
tWR
tAS
tW
36/38
FEDL63295A-02
1Semiconductor
ML63295A
PACKAGE DIMENSIONS
(Unit: mm)
QFP240-P-3232-0.50-BK4
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
Cu alloy
Solder plating (≥5µm)
7.82 TYP.
2/Nov. 28, 1996
5
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
37/38
FEDL63295A-02
1Semiconductor
ML63295A
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
38/38
相关型号：
ML63295A-XXXWA
4-Bit Microcontroller with Built-in 3072-Dot Matrix LCD Driver and Melody Circuit
OKI
ML632PTA102MLH
General Purpose Inductor, 1uH, 20%, 1 Element, Ferrite-Core, SMD, 7674, CHIP, 7674, ROHS COMPLIANT
COILCRAFT
ML632PTA102MLN
General Purpose Inductor, 1uH, 20%, 1 Element, Ferrite-Core, SMD, 7674, CHIP, 7674, ROHS COMPLIANT
COILCRAFT
ML632PTA122MLC
General Purpose Inductor, 1.2uH, 20%, 1 Element, Ferrite-Core, SMD, 7674, ROHS COMPLIANT
COILCRAFT
ML632PTA122MLN
General Purpose Inductor, 1.2uH, 20%, 1 Element, Ferrite-Core, SMD, 7674, CHIP, 7674, ROHS COMPLIANT
COILCRAFT
ML632PTA202MLC
General Purpose Inductor, 2uH, 20%, 1 Element, Ferrite-Core, SMD, 7674, ROHS COMPLIANT
COILCRAFT
ML632PTA202MLH
General Purpose Inductor, 2uH, 20%, 1 Element, Ferrite-Core, SMD, 7674, CHIP, 7674, ROHS COMPLIANT
COILCRAFT
©2020 ICPDF网 联系我们和版权申明