82C37 [OKI]
PROGRAMMABLE DMA CONTROLLER; 可编程DMA控制器
| 型号： | 82C37 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | PROGRAMMABLE DMA CONTROLLER |
| 文件： | 总34页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2O0016-39-81
This version: Aug. 1999
Previous version: Jan. 1998
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
PROGRAMMABLE DMA CONTROLLER
GENERAL DESCRIPTION
The MSM82C37B-5RS/GS/VJS, DMA (Direct Memory Access) controller is capable of high-
speeddatatransferwithoutCPUinterventionandisusedasaperipheraldeviceinmicrocomputer
systems. The device features four independent programmable DMA channels.
Due to the use of silicon gate CMOS technology, standby current is 10 mA (max.), and power
consumption is as low as 10 mA (max.) when a 5 MHz clock is generated.
All items of AC characteristics are compatible with intel 8237A-5.
FEATURES
• Maximum operating frequency of 5 MHz (Vcc = 5 V ±10%)
• High-speed operation at very low power consumption due to silicon gate CMOS technology
• Wide operating temperature range from –40°C to +85°C
• 4-channels independent DMA control
• DMA request masking and programming
• DMA request priority function
• DREQ and DACK input/output logic inversion
• DMA address increment/decrement selection
• Memory-to-Memory Transfers
• Channel extension by cascade connection
• DMA transfer termination by EOP input
• Intel 8237A-5 compatibility
• TTL Compatible
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C37B-5RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C37B-5VJS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C37B-5GS-2K)
1/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
PIN CONFIGURATION (TOP VIEW)
40 pin Plastic DIP
1
2
3
4
5
40
A7
IOR
IOW
MEMR
MEMW
NC
39
38
37
A6
A5
A4
36 EOP
6
7
8
9
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
READY
HLDA
ADSTB
AEN
A3
A2
A1
A0
V
CC (+5 V)
10
11
12
13
14
15
16
17
18
19
HRQ
DB0
DB1
DB2
DB3
DB4
DACK0
DACK1
DB5
DB6
DB7
CS
CLK
RESET
DACK2
DACK3
DREQ3
DREQ2
DREQ1
DREQ0
44 pin Plastic QFP
GND 20
READY
HLDA
ADSTB
AEN
1
2
3
4
5
6
7
8
9
33 A3
32 A2
31 A1
30 A0
HRQ
NC
29
VCC
28 NC
27 DB0
26 DB1
25 DB2
24 DB3
23 DB4
CS
CLK
RESET
DACK2 10
DACK3 11
44 pin Plastic QFJ
NC
READY
HLDA
ADSTB
AEN
7
39 NC
8
38 A3
9
37 A2
10
11
12
13
14
15
36 A1
35 A0
HRQ
34 VCC
33 DB0
32 DB1
31 DB2
30 DB3
CS
CLK
RESET
DACK2 16
NC 17
29
DB4
2/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
BLOCK DIAGRAM
IOR
IOW
Incrementer/Decrementer
Decrementer
Temporary Word
Count Register (16)
TC
8
4
Output
Buffer
MEMR
MEMW
READY
ADSTB
AEN
(Terminal Count)
A4 - A7
Temporary Address
Register (16)
Timing
Control
Circuit
4
Input/Output
Buffer
A0 - A3
16 Bit Bus
16 Bit Bus
CS
Current
Word
Count
Register
(4 ¥ 16)
Base
Current
Address
Register
(4 ¥ 16)
CLK
Base Word
Count
Register
(4 ¥ 16)
Address
Register
(4 ¥ 16)
Command
Control
Circuit
RESET
EOP
2
D0 - 1
HLDA
HRQ
Mode
Input/Output
Buffer
Internal Data Bus
DB0 - DB7
Register
Priority
Judgment
Circuit
(4 ¥ 16)
4
4
Command
Register (8)
DREQ0 - 3
DACK0 - 3
Mark
Register (4)
Status
Register (8)
Temporary
Register (8)
Request
Register (4)
3/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
ABSOLUTE MAXIMUM RATINGS
Rating
Conditions
Parameter
Symbol
Unit
MSM82C37B-5RS MSM82C37B-5GS MSM82C37B-5VJS
Power Supply Voltage
Input Voltage
VCC
VIN
V
V
–0.5 to +7
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–55 to +150
with respect
to GND
Output Voltage
VOUT
TSTG
V
—
Storage Temperature
Power Dissipation
°C
W
1.0
0.7
1.0
PD
Ta = 25°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
"L" Input Voltage
Symbol
VCC
Min.
4.5
Typ.
5.0
+25
—
Max.
5.5
Unit
V
°C
V
Top
–40
–0.5
2.2
+85
VIL
+0.8
"H" Input Voltage
V
TIH
—
VCC + 0.5
DC CHARACTERISTICS
Parameter
"L" Output Voltage
"H" Output Voltage
Input Leak Current
Output Leak Current
Symbol
Conditions
OL = 3.2 mA
Min. Typ. Max. Unit
I
VOL
VOH
—
3.7
—
—
—
—
0.4
—
10
10
V
V
I
OH = –1.0 mA
V
CC = 4.5 V
to 5.5 V
–10
–10
mA
mA
ILI
0V £ VIN £ VCC
Ta = –40°C
to +85°C
ILO
0V £ VOUT £ VCC
Input frequency
5 MHz, when RESET
Average Power Supply
Current during Operations
ICC
—
—
—
—
10
10
mA
VIN = 0 V/VCC,
CL = 0 pF
HLDA = 0 V,
Power Supply Current
in Standby Mode
ICCS
V
V
IL = 0 V,
IH = VCC
mA
4/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
AC CHARACTERISTICS
DMA (Master) Mode
(Ta = –40 to +85°C, VCC = 4.5 to 5.5 V)
Comments
Symbol
Item
Min.
Max.
Unit
Delay Time from CLK Falling Edge
up to AEN Leading Edge
ns
—
200
130
90
—
—
tAEL
Delay Time from CLK Rising Edge
up to AEN Trailing Edge
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
tAET
tAFAB
tAFC
Delay Time from CLK Rising Edge
up to Address Floating Status
—
Delay Time from CLK Rising Edge
up to Read/Write Signal Floating Status
—
120
170
—
—
Delay Time from CLK Rising Edge
up to Data Bus Floating Status
—
—
tAFDB
tAHR
tAHS
tAHW
Address Valid Hold Time
to Read Signal Trailing Edge
tCY – 100
30
—
Data Valid Hold Time
to ADSTB Trailing Edge
—
—
Address Valid Hold Time
to Write Signal Trailing Edge
tCY – 50
—
—
—
Delay Time from CLK Falling Edge
up to Active DACK
170
170
170
170
(Note 3)
(Note 5)
—
Delay Time from CLK Rising Edge
up to EOP Leading Edge
—
tAK
Delay Time from CLK Rising Edge
up to EOP Trailing Edge
—
Time from CLK Rising Edge
up to Address Valid
—
—
tASM
ns
ns
ns
ns
tASS
tCH
tCL
Data Set-up Time to ADSTB Trailing Edge
Clock High-level Time
100
68
—
—
—
—
—
(Note 6)
(Note 6)
—
Clock Low-level Time
68
tCY
200
CLK Cycle Time
5/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
DMA (Master) Mode (continued)
Comments
Unit
Symbol
Item
Min.
Max.
Delay Time from CLK Rising Edge
to Read/Write Signal Leading Edge
ns
ns
ns
ns
ns
—
190
(Note 2)
(Note 2)
(Note 2)
—
tDCL
Delay Time from CLK Rising Edge
to Read Signal Trailing Edge
—
—
—
190
130
120
tDCTR
tDCTW
tDQ
Delay Time from CLK Rising Edge
to Write Signal Trailing Edge
Delay Time from CLK Rising Edge
to HRQ Valid
EOP Leading Edge Set-up Time to
CLK Falling Edge
40
220
—
—
—
—
—
tEPS
tEPW
ns
ns
EOP Pulse Width
Delay Time from CLK Rising Edge
to Address Valid
170
150
200
—
—
—
tFAAB
tFAC
tFADB
tHS
Time from CLK Rising Edge
up to Active Read/Write Signal
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
75
0
Delay Time from CLK Rising Edge
to Data Valid
—
HLDA Valid Set-up Time
to CLK Rising Edge
—
Input Data Hold Time
to MEMR Trailing Edge
—
—
tIDH
tIDS
tODH
tODV
tQS
Input Data Set-up
to MEMR Trailing Edge
170
10
125
0
—
—
Output Data Hold Time
to MEMW Trailing Edge
—
—
Time from Output Data Valid
to MEMW Trailing Edge
—
—
DREQ Set-up Time
to CLK Falling Edge
—
(Note 3)
—
READY Hold Time
to CLK Falling Edge
20
60
—
—
—
tRH
READY Set-up Time
to CLK Falling Edge
—
—
tRS
Delay Time from CLK Rising Edge
to ADSTB Leading Edge
130
90
—
tSTL
tSTT
Delay Time from CLK Rising Edge
to ADSTB Trailing Edge
—
6/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Slave Mode
(Ta = –40 to +85°C, VCC = 4.5 to 5.5 V)
Comments
Symbol
Item
Min.
Max.
Unit
Time from Address Valid or
CS Leading Edge to IOR Leading Edge
ns
50
—
—
—
—
—
140
70
—
—
—
—
—
—
—
—
—
—
—
tAR
Address Valid Set-up Time
to IOW Trailing Edge
ns
ns
ns
ns
ns
ns
ns
ns
130
130
130
0
tAW
tCW
CS Leading Edge Set-up Time
to IOW trailing edge
Data Valid Set-up Time
to IOW Trailing Edge
tDW
Address or CS Hold Time
to IOR Trailing Edge
tRA
Data Access Time
to IOR Leading Edge
—
tRDE
tRDF
tRSTD
tRSTS
Delay Time to Data Floating Status
from IOR Trailing Edge
0
Supply Power Leading Edge Set-up
time to RESET Trailing Edge
500
2tCY
Time to First Active IOR or IOW
from RESET Trailing Edge
ns
ns
300
200
—
—
—
—
tRSTW
tRW
RESET Pulse Width
IOR Pulse Width
Address Hold Time
to IOW Trailing Edge
ns
ns
20
20
—
—
—
—
tWA
tWC
CS Trailing Edge Hold Time
to IOW Trailing Edge
ns
ns
30
—
—
—
—
tWD
Data Hold Time to IOW Trailing Edge
IOW Pulse Width
160
tWWS
Notes: 1. Output load capacitance of 150 (pF).
2. IOW and MEMW pulse widths of t – 100 (ns) for normal writing, and 2t – 100
CY
CY
(ns) for extended writing. IOR and MEMR pulse widths of 2t – 50 (ns) for normal
CY
timing, and t – 50 (ns) for compressed timing.
CY
3. DREQ and DACK signal active level can be set to either low or high. In the timing
chart, the DREQ signal has been set to active-high, and the DACK signal to active-
low.
4. When the CPU executes continuous read or write in programming mode, the
interval during which the read or write pulse becomes active must be set to at least
400 ns.
5. EOP is an open drain output. The value given is obtained when a 2.2 kW pull-up
resistance is connected to V
.
CC
6. Rise time and fall time are less than 10 ns.
7. Waveform measurement points for both input and output signals are 2.2 V for HIGH
and 0.8 V for LOW, unless otherwise noted.
7/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
TIMING CHART
Reset Timing
VCC
tRSTD
tRSTW
RESET
tRSTS
IOR, IOW
Slave Mode Write Timing
tCW
CS
tWC
tWWS
tAW
IOW
tWA
A0 - A3
Input Valid Address
tWD
tDW
DB0 - DB7
Input Valid Data
Slave Mode Read Timing
CS
A0 - A3
Input Valid Address
tAR
tRA
tRW
IOR
tRDE
tRDF
DB0 - DB7
Output Valid Data
8/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
DMA Transfer Timing
SI SI
S0 S0 S1 S2 S3 S4 S2 S3 S4
SI
SI
CLK
tCH
tCY
tCL
tQS
tQS
DREQ
HRQ
tDQ
tDQ
tHS
HLDA
AEN
tAET
tAEL
tSTT
tSTL
ADSTB
tASS
tAHS
tFADB
A8 - A15
tAFDB
DB0 - DB7
A0 - A7
tASM
tFAAB
tAFAB
tAHW
A0 - A7
A0 - A7
tAHR
tAK
tAK
DACK
tDCL
tDCTR
tFAC
tAFC
IOR, MEMR
tDCL
tDCTW
IOW, MEMW
tAK
tAK
(Extended Write)
Internal EOP
tEPS
(Output)
tEPW
External EOP
(Input)
9/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Memory to Memory Transfer Timing
S11
S12
S0
S13
S14
S21
S22
S23
S24
SI
CLK
tSTL
tSTT
tSTL
tSTT
ADSTB
A0 - A7
tASM
tAHS
tAHS
tAFAB
tFAAB
Valid Address A
Valid Address A
0 - 7
0 - 7
tAFDB
tAFDB
tFADB
Data Input
tDCTR
Data Output
tODV tODH
DB0 - DB7
MEMR
A8 - A15
tDCL
A8 - A15
tFADB
tFAC
tIDH
tAFC
tIDS
tDCTW
tDCL
tFAC
tAFC
MEMW
tAK
tAK
Internal EOP
tEPS
tEPS
(Output)
tEPW
tEPW
External EOP
(Input)
Ready Timing
S2
S3
SW
SW
S4
CLK
tDCTR
tDCL
IOR, MEMR
IOW, MEMW
READY
tDCL
tDCL
tDCTW
(Extended Write)
tRH
tRH
tRS
tRS
10/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Compressed Transfer Timing
S2
S4
S2
S4
CLK
tASM
tASM
A0 - A7
Valid Address
tDCL
tDCTR
tDCL
tDCTR
IOR, MEMR
IOW, MEMW
READY
tDCTW
tDCTW
tDCL
tRH
tRH
tRS
tRS
tAK
tAK
Internal EOP
(Output)
tEPS
tEPW
External EOP
(Input)
11/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
PIN FUNCTIONS
Symbol
VCC
Input/Output
Function
Pin Name
Power
+5 V power supply
—
—
Ground
Clock
Ground (0 V) connection.
GND
Control of MSM82C37B-5 internal operations and data transfer
speed.
CLK
Input
Chip Select
Reset
Input
Input
CS is active-low input signal used for the CPU to select
CS
the MSM82C37B-5 as an I/O device in an idle cycle.
RESET is active-high asynchrounous input signal used to clear
command, status, request, temporary registers, and first/last F/F,
and to set mask register. The MSM82C37B-5 enters an idle cycle
following a RESET.
RESET
The read or write pulse width can be extended to accomodate
slow access memories and I/O devices when this input is
switched to low level. Note this input must not change within
the prescribed set-up/hold time.
READY
HLDA
Ready
Input
Hold Acknowledge
Input
Input
HLDA is active-high input signal used to indicate that system bus
control has been released when a hold request is recieved by
the CPU.
DREQ is asynchronous DMA transfer request input signals.
Although these pins are switched to active-high by reset, they can
be programmed to become active-low. DMA requests are
received in accordance with a prescribed order of priority. DREQ
must be held until DACK becomes active.
DREQ0 - DMA Request
DREQ3
0 - 3 Channels
DB is bidirectional three-state signals connected to the system
data bus, and which is used as an input/output of MSM82C37B-5
internal registers during idle cycles, and as an output of the eight
higher order bits of transfer addresses during active cycles.
Also used as input and output of transfer data during memory-
memory transfers.
DB0 - DB7 Data Bus 0 - 7
Input/Output
I/O Read
I/O Write
Input/Output
Input/Output
IOR is active-low bidirectional three-state signal used as an input
control signal for CPU reading of MSM82C37B-5 internal
registers during idle cycles, and as an output control signal for
reading I/O device transfer data in writing transfers during active
cycles.
IOR
IOW is active-low bidirectional three-state signal used as an input
control signal for CPU writing of MSM82C37B-5 internal registers
during idle cycles, and as an output control signal for writing I/O
device transfer data in writing transfers during active cycles.
IOW
12/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
PIN FUNCTIONS (continued)
Symbol
Pin Name
Input/Output
Function
EOP
End of Process
Input/Output
EOP is active-low bidirectional three-state signal. Unlike other
pins, this pin is an N-channel open drain. During DMA operations,
a low-level output pulse is obtained from this pin if the channel
word count changes from 0000H to FFFFH.
And DMA transfers can be terminated by pulling the EOP input to
low level. Both of these actions are called terminal count (TC).
When internal or external EOP is generated, the MSM82C37B-5
terminates the transfer and resets the DMA request.
When the EOP pin is not used, it is necessary to hold the pin at
high level by pull-up resistor to prevent the input of an EOP
by error. Also note that the EOP function cannot be satisfied in
cascade mode.
A0 - A3
Address 0 - 3
Input/Output
A0 - A3 is bidirectional three-state signals used as input signals
for specifying the MSM82C37B-5 internal register to be accessed
by the CPU during idle cycles, and as an output the four lower
order bits of the transfer address during active cycles.
A4 - A7
HRQ
Address 4 - 7
Hold Request
Output
Output
A4 - A7 is three-state signals used as an output the four higher
order bits of the transfer address during active cycles.
HRQ is active-high signal used as an output of hold request to
the CPU for system data bus control purposes. After HRQ has
become active, at least one clock cycle is required before HLDA
becomes active.
DACK is output signals used to indicate that DMA transfer to
DACK0 - DMA Acknowledge
Output
Output
DACK3
0 - 3 Channels
peripheral devices has been permitted. (Available in each channel.)
Although these pins are switched to active-low when reset, they
can be programmed to become active-high.
Note that there is no DACK output signal during memory-memory
transfers.
AEN
Address Enable
AEN is active-high ouput signal used to indicate that output
signals sent from the MSM82C37B-5 to the system are valid.
And in addition to enabling external latch to hold the eight higher
order bits of the transfer address, this signal is also used to
disable other system bus buffers.
Address Strobe
Memory Read
Output
Output
ADSTB is active-high signal used to strobe the eight higher order
bits of the transfer address by external latch.
ADSTB
MEMR is active-low three-state output signal used as a control
signal in reading data from memory during read transfers and
memory-memory transfers.
MEMR
MEMW
Memory Write
Output
MEMW is active-low three-state output signal used as a control
signal in writing data into memory during write transfers and
memory-memory transfers.
13/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
RESET
SI
Internal/
external DMA
Request
N
Y
S0
N
HLDA
Y
Y
Memory-Memory
Transfer
S11
S12
N
S1
Y
S2
External EOP
N
Y
External EOP
EOP F/F Setting
N
S13
EOP F/F Setting
Y
Compressed
Timing
N
SW
READY
N
Y
S3
S14
Y
Verify
N
S21
S22
N
SW
READY
Y
Y
External EOP
N
S4
EOP F/F Setting
S23
Y
Y
Internal/
External EOP
N
Single Transfer
N
N
SW
READY
Y
S24
N
Y
HLDA
Y
Y
Internal/
External EOP
N
Demand Transfer
N
Y
Y
N
HLDA
N
External DMA
Request
N
Carry or Borrow
Y
Note:
Y º Yes (Active)
N º No (Inactive)
Figure 1 DMA Operation State Transition Diagram
14/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
OUTLINE OF FUNCTIONS
The MSM82C37B-5 consists of five blocks = three logic sections, an internal register section, and
a counter section.
The logic sections include a timing control block where the internal timing and external control
signals are generated, a command control block where each instruction from the CPU is
decoded, and a priority decision block where the order of DMA channel priority is determined.
The purpose of the internal register section is to hold internal states and instructions from the
CPU, while the counter section computes addresses and word counts.
DESCRIPTION OF OPERATIONS
The MSM82C37B-5 operates in two cycles (called the idle and active cycles) which are divided
into independent states. Each state is commenced by a clock falling edge and continues for a
single clock cycle. The transition from one state to the next in DMA operations is outlined in
Figure 1.
Idle Cycle
The idle cycle is entered from the Sl state when there is no valid DMA request on any
MSM82C37B-5 channel. During this cycle, DREQ and CS inputs are monitored during each
cycle. When a valid DMA request is then received, an active cycle is commenced. And if the
HLDA and CS inputs are at low level, a programming state is started with MSM82C37B-5
reading or writing executed by IOR or IOW. Programming details are described later.
Active Cycle
If a DMA request is received in an unmasked channel while the MSM82C37B-5 is in idle cycle,
or if a software DREQ is generated, the HRQ is changed to high level to commence an active
cycle. The initial state of an active cycle is the S state which is repeated until the HLDA input
0
from the CPU is changed to high level. (But because of internal operational reasons, a minimum
of one clock cycle is required for the HLDA is be changed to high level by the CPU after the HRQ
has become high level. That is, the S state must be repeated at least twice.)
0
After the HLDA has been changed to high level, the S state proceeds to operational states S1
0
thru S during I/O-memory transfers, or to operational states S thru S and S thru S
4
11
14
21
24
during memory-memory transfers.
If the memory or I/O device cannot be accessed within the normal timing, an SW state (wait
state) can be inserted by a READY input to extend the timing.
15/33
¡ Semiconductor
MSM82C37B-5RS/GS/VJS
DESCRIPTION OF TRANSFER TYPES
MSM82C37B-5 transfers between an I/O and memory devices, or transfers between memory
devices. The three types of transfers between I/O and memory devices are read, write, and
verify.
I/O-Memory Transfers
The operational states during an I/O-memory transfer are S , S , S , and S .
1
2
3
4
In the S state, an AEN output is changed to high level to indicate that the control signal from
1
the MSM82C37B-5 is valid. The eight lower order bits of the transfer address are obtained from
A thru A , and the eight higher order bits are obtained from DB thru DB . The ADSTB output
0
7
0
7
is changed to high level at this time to set the eight higher order bits in an external address latch,
and the DACK output is made active for the channel where the DMA request is acknowledged.
Wherethereisnochangeintheeighthigherbittransferaddressduringdemandandblockmode
transfers, however, the S state is omitted.
1
In the S state, the IOR or MEMR output is changed to low level.
2
In the S state, IOW or MEMW is changed to low level. Where compressed timing is used,
3
however, the S state is omitted.
3
The S and S states are I/O or memory input/output timing control states. In the S state, IOR,
2
3
4
IOW,MEMR,andMEMWarechangedtohighlevel,andthewordcountregisterisdecremented
by 1 while the address register is incremented (or decremented) by 1. This completes the DMA
transfer of one word.
Note that in I/O-memory transfers, data is transferred directly without being taken in by the
MSM82C37B-5. ThedifferencesinthethreetypesofI/O-memorytransfersareindicatedbelow.
Read Transfer
Data is transferd from memory to the I/O device by changing MEMR and lOW to low level.
MEMW and IOR are kept at high level during this time.
Write Transfer
Data is transferred from the I/O device to memory by changing MEMW and IOR to low level.
MEMR and IOW are kept at high level during this time.
Note that writing and reading in these write and read transfers are with respect to the memory.
Verify Transfer
Although verify transfers involve the same operations as write and read transfers (such as
transfer address generation and EOP input responses),they are in fact pseudo transfers where
all I/O and memory reading/writing control signals are kept inactive. READY inputs are
disregarded in verify transfers.
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Memory-memory Transfer
Memory-memory transfers are used to transfer data blocks from one memory area to another.
Memory-memory transfers require a total of eight states to complete a single transfer four states
(S thru S ) for reading from memory, and four states (S thru S ) for writing into memory.
11
14
21
24
ThesestatesaresimilartoI/O-memorytransferstates, andaredistinguishedbyusingtwo-digit
numbers. Inmemory-memorytransfers, channel0isusedforreadingdatafromthesourcearea,
and channel 1 is used for writing data into the destination area. During the initial four states,
data specified by the channel 0 address is read from the memory when MEMR is made active,
andistakenintheMSM82C37B-5temporaryregister. Thenduringthelatterfourstates,thedata
in the temporary register is written in the address specified by channel 1. This completes the
transfer of one byte of data. With channel 0 and channel 1 addresses subsequently incremented
(ordecremented)by1,andchannel0,1wordcountdecrementedby1,thisoperationisrepeated.
ThetransferisterminatedwhenthewordcountreachesFFFF(H)from0000(H), orwhenanEOP
input is applied from an external source. Note that there is no DACK output signal during this
transfer.
Thefollowingpreparationsinprogrammingarerequiringtoenablememory-memorytransfers
to be started.
Command Register Setting
Memory-memory transfers are enabled by setting bit 0. Channel 0 address can be held for all
transfers by setting bit 1. This setting can be used to enable 1-word contents of the source area
to be written into the entire destination area.
Mode Register Setting
The transfer type destination is disregarded in channels 0 and 1. Memory-memory transfers are
always executed in block transfer mode.
Request Register Setting
Memory-memory transfers are started by setting the channel 0 request bit.
Mask Register Setting
Mask bits for all channels are set to prevent selection of any other channel apart from channel
0.
Word Count Register Setting
The channel 1 word count is validated, while the channel 0 word count is disregarded.
In order to autoinitialize both channels, it is necessary to write the same values into both word
count registers.
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
DESCRIPTION OF OPERATION MODES
Single Transfer Mode
In single transfer mode, only one word is transferred, and the addresses are incremented (or
decremented) by 1 while the word count is decremented by 1. The HRQ is then changed to low
level to return the bus control to the CPU. If DREQ remains active after completion of a transfer,
the HRQ is changed to low level. After the HLDA is changed to low level by the CPU, and then
changes the HRQ back to high level to commence a fresh DMA cycle. For this reason, a machine
cycle can be inserted between DMA cycles by the CPU.
Block Transfer Mode
OnceaDMAtransferisstartedinblockmode, thetransferiscontinueduntilterminalcount(TC)
status is reached.
If DREQ remains active until DACK becomes active, the DMA transfer is continued even if
DREQ becomes inactive.
Demand Transfer Mode
TheDMAtransferiscontinuedindemandtransfermodeuntilDREQisnolongeractive, oruntil
TC status is reached.
During a DMA transfer, intermediate address and word count values are held in the current
address and current word count registers. Consequently, if the DMA transfer is suspended as
a result of DREQ becoming inactive before TC status is reached, and the DREQ for that channel
is then made active again, the suspended DMA transfer is resumed.
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Cascade Transfer Mode
When DMA transfers involving more than four channels are required, connecting a multiple
number of MSM82C37A-5 devices in a cascade connection (see Figure 2 ) enables a simple
system extension. This mode is set by setting the first stage MSM82C37B-5 channel to cascade
mode. TheDREQandDACKlinesforthefirststageMSM82C37B-5channelsettocascademode
are connected to the HRQ and HLDA lines of the respective MSM82C37B-5 devices in the
second stage. The first stage MSM82C37B-5 DACK signal must be set to active-high, and the
DREQ signal to active-low.
Since the first stage MSM82C37B-5 is only used functionally in determining the order of priority
of each channel when cascade mode is set, only DREQ and DACK are used–all other inputs are
disregarded. And since the system may be hung up if the DMA transfer is activated by software
DREQ, do not set a software DREQ for channels where cascade mode has been set.
In addition to the dual stage cascade connection shown in Figure 2, triple stage cascade
connections are possible with the second stage also set to cascade mode.
4
DREQ
0 - 3
I/O
CPU
4
DACK
0 - 3
DREQ
DACK
HRQ
HLDA
HRQ
HLDA
HRQ
HLDA
DREQ
DACK
4
4
DREQ
0 - 3
Stage 1
MSM82C37B-5
I/O
DACK
0 - 3
Stage 2
MSM82C37B-5
Figure 2 MSM82C37B-5 Cascade Connection System
Autoinitialize Mode
Setting bit 4 of the mode register enables autoinitialization of that channel. Following TC
generation, autoinitialize involves writing of the base address and the base word count register
values in the respective current address and current word count registers. The same values as
in the current registers are written in the base registers by the CPU, and are not changed during
DMA transfers. When a channel has been set to autoinitialize, that channel may be used in a
second transfer without involving the CPU and without the mask bit being reset after the TC
generation.
Priority Modes
The MSM82C37B-5 makes use of two priority decision modes, and acknowledges the DMA
channel of highest priority among the DMA requesting channels.
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MSM82C37B-5RS/GS/VJS
Fixed Priority Mode
In fixed priority mode, channel 0 has the highest priority, followed by channels 1, 2, and 3 in that
order.
Rotating Priority Mode
In rotating priority mode, the order of priority is changed so that the channel where the current
DMA transfer has been completed is given lowest priority. This is to prevent any one channel
from monopolizing the system.
The fixed priority is regained immediately after resetting.
Table 1 MSM82C37B-5 Priority Decision Modes
Priority Mode
Service Terminated Channel
Highest
Fixed
—
Rotating
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
Order of Priority
for Next DMA
Lowest
Compressed Timing
Setting the MSM82C37B-5 to compressed timing mode enables the S state used in extension of
3
the read pulse access time to be omitted (if permitted by system structure) for two or three clock
cycle DMA transfers. If the S state is omitted, the read pulse width becomes the same as the
3
write pulse width with the address updated in S and the read or write operation executed in
2
S . This mode is disregarded if the transfer is a memory-memory transfer, transfer.
4
Extended Writing
When this mode is set, the IOW or MEMW signal which normally appears during the S state
3
is obtained during the S state, thereby extending the write pulse width. The purpose of this
2
extended write pulse is to enable the system to accomodate memories and I/O devices where
the access time is slower. Although the pulse width can also be extended by using READY, that
involves the insertion of a SW state to increase the number of states.
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
DESCRIPTION OF INTERNAL REGISTERS
Current Address Register
Each channel is equipped with a 16-bit long current address register where the transfer address
is held during DMA transfers. The register value is incremented (or decremented) in each DMA
cycle. Although this register is 16 bits long, the CPU is accessed by the MSM82C37B-5 eight bits
at a time, therefore necessitating two successive 8-bit (lower and higher order bits) reading or
writing operations using internal first/last flip-flops.
When autoinitialize has been set, the register is automatically initialized to the original value
after TC.
Current Word Count Register
Each channel is also equipped with a 16 bit-long current word count register where the transfer
count is held during DMA transfers. The register value is decremented in each DMA cycle.
WhenthewordcountvaluereachesFFFF(H)from0000(H),aTCisgenerated. Therefore,aword
count value which is one less than the actual number of transfers must be set.
Since thisregisteris also 16bits long, it is accessedbyfirst/lastflip-flops control in the same way
astheaddressregister. Andifautoinitializehasbeenset, theregisterisautomaticallyinitialized
to the original value after TC.
Base Address Register and Base Word Count Register
Each channel is equipped with a 16-bit long base address register and base word count register
where the initial value of each current register is held. The same values are written in each base
register and the current register by the CPU. The contents of the current register can be made
ready by the CPU, but the content of the base register cannot be read.
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MSM82C37B-5RS/GS/VJS
Command Register
This 8-bit write-only register prescribes DMA operations for all MSM82C37B-5 channels. An
outline of all bits is given in Figure 3. When the controller is disabled by setting D B , there is
2
no HRQ output even if DMA request is active.
DREQ and DACK signals may be active high or active low by setting D B and DB .
6
7
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0: Memory-Memory Transfer Disabled
1: Memory-Memory Transfer Enabled
0: Channel 0 Address Hold Disabled
1: Channel 0 Address Hold Enabled
(Invalid when DB0 = "0")
0: Controller Enabled
1: Controller Disabled
0: Normal Timing
1: Compressed Timing
(Invalid when DB0 = "1")
0: Fixed Priority
1: Rotating Priority
0: Normal Write Pulse Width
1: Extended Write Pulse Width
0: DREQ Sense Active "H"
1: DREQ Sense Active "L"
0: DACK Sense Active "L"
1: DACK Sense Active "H"
Figure 3 Command Register
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Mode Register
Eachchannelisequippedwitha6-bitwrite-onlymoderegister, whichisdecidedbysettingDB ,
0
DB which channel is to be written when writing from CPU is programming status. The bit
1
description is outlined in Figure 4.
This register is not cleared by Reset or Master Clear instruction.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00: Channel 0 Selected
01: Channle 1 Selected
10: Channel 2 Selected
11: Channle 3 Selected
00: Verify Transfer
01: Write Transfer
10: Read Transfer
11: Disabled
(Invalid When DB6·DB7 = "11")
0: Auto Initialize Disabled
1: Auto Initialize Enabled
0: Address Increment (+1) Selected
1: Address Decrement (–1) Selected
00: Demand Transfer Mode Selected
01: Single Transfer Mode Selected
10: Block Transfer Mode Selected
11: Cascade Mode Selected
Figure 4 Mode Register
Request Register
InadditiontousingtheDREQsignal,theMSM82C37B-5canrequestDMAtransfersbysoftware
means. Thisinvolvessettingtherequestbitofrequestregister. Eachchannelhasacorresponding
request bit in the request register, and the order of priority of these bits is determined by the
priority decision circuit irrespective of the mask register. DMA transfers are acknowledged in
accordance with the decided order of priority.
All request bits are reset when the TC is reached, and when the request bit of a certain channel
has been received, all other request bits are cleared. When a memory-memory transfer is
commenced, the channel 0 request bit is set. The bit description is outlined in Figure 5.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00: Channel 0 Selected
01: Channel 1 Selected
10: Channel 2 Selected
11: Channel 3 Selected
0: Request Bit Cleared
1: Request Bit Set
Not Used
Figure 5 Request Register
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MSM82C37B-5RS/GS/VJS
Mask Register
This register is used in disabling and enabling of DMA transfers in each channel. Each channel
includesacorrespondingmaskbitinthemaskregister,andeachbitissetwhentheTCisreached
if not in autoinitialize mode. This mask register can be set in two different ways.
The method for setting/resetting the register for each channel is outlined in Figure 6(a), while
the method for setting/resetting the register for all channels at once is outlined in Figure 6(b).
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00: Channel 0 Selected
01: Channel 1 Selected
10: Channel 2 Selected
11: Channel 3 Selected
0: Mask Bit Cleared
1: Mask Bit Set
Not Used
(a) Single Mask Register (Setting/Resetting for Each Channel)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0: Channel 0 Mask Bit Cleared
1: Channel 0 Mask Bit Set
0: Channel 1 Mask Bit Cleared
1: Channel 1 Mask Bit Set
0: Channel 2 Mask Bit Cleared
1: Channel 2 Mask Bit Set
0: Channel 3 Mask Bit Cleared
1: Channel 3 Mask Bit Set
Not Used
(b) All Mask Register (Setting/Resetting of All Channels at Once)
Figure 6 Mask Register
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Status Register
This register is a read-only register used in CPU reading of the MSM82C37B-5 status. The four
higher order bits indicate the DMA transfer request status for each channel, ‘1’ being set when
the DREQ input signal is active.
ThefourlowerorderbitsindicatewhetherthecorrespondingchannelhasreachedtheTCornot,
‘1’ being set when the TC status is reached. These four lower order bits are reset by status
register reading, or RESET input and master clearing. A description of each bit is outlined in
Figure 7
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0: Channel 0 Has Not Reached TC
1: Channel 0 Has Reached TC
0: Channel 1 Has Not Reached TC
1: Channel 1 Has Reached TC
0: Channel 2 Has Not Reached TC
1: Channel 2 Has Reached TC
0: Channel 3 Has Not Reached TC
1: Channel 3 Has Reached TC
0: Channel 0 Is Not Requesting
1: Channel 0 Is Requesting
0: Channel 1 Is Not Requesting
1: Channel 1 Is Requesting
0: Channel 2 Is Not Requesting
1: Channel 2 Is Requesting
0: Channel 3 Is Not Requesting
1: Channel 3 Is Requesting
Figure 7 Status Register
Temporary Register
The temporary register is a register where transfer data is held temporarily during memory-
memory transfers. Since the last item of data to be transferred is held after completion of the
transfer, this item can be read by the CPU.
Software Command
The MSM82C37B-5 is equipped with software commands for executing special operations to
ensure proper programming. Software command is irrespective of data bus contents.
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MSM82C37B-5RS/GS/VJS
Clear First/Last Flip-Flop
16-bit address and word count registers are read or written in two consecutive operations
involving eight bits each (higher and lower order bits) under data bus port control. The fact that
the lower order bits are accessed first by the MSM82C37B-5, followed by accessing of the higher
order bits, is discerned by the internal first/last flip-flop. This command resets the first/last
flip-flop with the eight lower order bits being accessed immediately after execution.
Master Clear
The same operation as when the hardware RESET input is applied. Thus command clears the
contents of the command, status (four lower order bits), request, and temporary registers, also
clears the first/last flip-flop, and sets the mask register. This command is followed by an idle
cycle.
Clear Mask Register
When this command is executed, the mask bits for all channels are cleared to enable reception
of DMA transfers.
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MSM82C37B-5RS/GS/VJS
PROGRAMMING
The MSM82C37B-5 is switched to programming status when the HLDA input and CS are both
at low level. In this state, IOR is changed to low level with IOW held at high level to enable
reading by the CPU, or else IOW is changed to low level while IOR is held at high level to enable
writing by the CPU. A list of command codes for reading from the MSM82C37B-5 is given in
Table 2, and a list of command codes for writing in the MSM82C37B-5 is given Table 3.
Note: If a DMA transfer request is received from an I/O device during MSM82C37B-
5programming,thatDMAtransfermaybecommencedtopreventproperprogramming.
To prevent this interference, the DMA channel must be masked, or the controller
disabled by the command register, or the system set to as to prevent DREQ becoming
active during the programming.
Table 2 List of MSM82C37B-5 Read Commands
Internal
CS IOR A3 A2 A1 A0 First/Last
Read Out Data
Flip/Flop
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
¥
¥
¥
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
Current Address
Register
Channel 0
Channel 1
Channel 2
Current Word Count
Register
Current Address
Register
Current Word Count
Register
Current Address
Register
Current Word Count
Register
Current Address
Register
Channel 3
Current Word Count
Register
Status Register
Temporary Register
Output Data Invalid
Other Combinations
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Table 3 List of MSM82C37B-5 Write Commands
Internal
CS IOW A3 A2 A1 A0 First/Last
Written Data
Flip-Flop
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
¥
¥
¥
¥
¥
¥
¥
¥
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
8 Lower Order Bits
8 Higher Order Bits
Current and Base
Address Registers
Channel 0
Channel 1
Channel 2
Channel 3
Current and Base
Word Count Registers
Current and Base
Address Registers
Current and Base
Word Count Registers
Current and Base
Address Registers
Current and Base
Word Count Registers
Current and Base
Address Registers
Current and Base
Word Count Registers
Command Register
Request Register
Single Mask Register
Mode Register
Clear First/Last Flip-Flop (Software Command)
Master Clear (Software Command)
Clear Mask Register (Software Command)
All Mask Register
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES
The conventional low speed devices are replaced by high-speed devices as shown below.
When you want to replace your low speed devices with high-speed devices, read the replacement
notice given on the next pages.
High-speed device (New)
M80C85AH
Remarks
Low-speed device (Old)
M80C85A/M80C85A-2
M80C86A/M80C86A-2
M80C88A/M80C88A-2
M82C84A/M82C84A-5
M81C55
8-bit MPU
M80C86A-10
16-bit MPU
M80C88A-10
8-bit MPU
M82C84A-2
Clock generator
RAM, I/O, timer
DMA controller
M81C55-5
M82C37B-5
M82C37A/M82C37A-5
M82C51A-2
USART
M82C51A
M82C53-2
Timer
PPI
M82C53-5
M82C55A-2
M82C55A-5
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Differences between MSM82C37A-5 and MSM82C37B-5
1) Manufacturing Process
These devices use a 3 m Si-CMOS process technology and have the same chip size.
2) Function
These devices have the same logics except for changes in AC characteristics listed in (3-2).
3) Electrical Characteristics
3-1) DC Characteristics
These devices have the same DC characteristics.
3-2) AC Characteristics
Parameter
Clock Low Time
Symbol
MSM82C37A-5
MSM82C37B-5
t
t
CL
100 ns minimum
68 ns minimum
(at automatic initialization)
Clock Low Time
(Other than the above)
CL
68 ns minimum
68 ns minimum
As shown above, the MSM82C37A-5 cannot satisfy the clock low time of 68 ns (at automatic
initialization). On the other hand, the MSM82C37B-5 can satisfy the clock low time of 68 ns in any
operation status. As for the other characteristics, both the MSM82C37A-5 and the MSM82C37B-5 are
identical.
4) Package
The MSM82C37A-5 employed a PLCC package having OKI's original pin layout, which is not
compatible to AMD's PLCC products which has been commercialized before OKI's products.
To meet overseas customers needs, OKI has developed AMD-compatible PLCC
productsMSM82C37B-VJS. The OKI's DIP and FLAT package are identical to those of AMD.
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¡ Semiconductor
PACKAGE DIMENSIONS
DIP40-P-600-2.54
MSM82C37B-5RS/GS/VJS
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
6.10 TYP.
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
2.00 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.41 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
33/33
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
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9.
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MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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