TJA1442ATK [NXP]
High-speed CAN transceiver with Standby mode;型号: | TJA1442ATK |
厂家: | NXP |
描述: | High-speed CAN transceiver with Standby mode |
文件: | 总30页 (文件大小:356K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TJA1442
High-speed CAN transceiver with Standby mode
Rev. 1 — 12 August 2020
Product data sheet
1 General description
The TJA1442 is a member of the TJA144x family of transceivers that provide an interface
between a Controller Area Network (CAN) or CAN FD (Flexible Data rate) protocol
controller and the physical two-wire CAN bus. TJA144x transceivers implement the CAN
physical layer as defined in ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5, and
are fully interoperable with high-speed Classical CAN and CAN FD transceivers. All
TJA144x variants enable reliable communication in the CAN FD fast phase at data rates
up to 5 Mbit/s.
The TJA1442 is intended as a simple replacement for high-speed Classical CAN and
CAN FD transceivers, such as the TJA1042 or TJA1044GT from NXP. It offers pin
compatibility and is designed to avoid changes to hardware and software design,
allowing the TJA1442 to be easily retrofitted to existing applications.
An AEC-Q100 Grade 0 variant, the TJR1442, is available for high temperature
applications, supporting operation at 150 °C ambient temperature.
1.1 TJA1442 variants
The TJA1442 comes in two variants, each available in an SO8 or HVSON8 package:
• The TJA1442A is a high-speed CAN transceiver with Normal and Standby modes and
a VIO supply pin. The VIO pin allows for direct interfacing with 3.3 V- and 5 V-supplied
microcontrollers.
• The TJA1442B is a high-speed CAN transceiver with Normal and Standby modes.
2 Features and benefits
2.1 General
• ISO 11898-2:2016, SAE J2284-1 to SAE J2284-5 and SAE J1939-14 compliant
• Standard CAN and CAN FD data bit rates up to 5 Mbit/s
• Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI)
• Qualified according to AEC-Q100 Grade 1
• TJA1442A only: VIO input for interfacing with 3.3 V to 5 V microcontrollers
• All variants are available in SO8 and leadless HVSON8 (3.0 mm x 3.0 mm) packages;
HVSON8 with improved Automated Optical Inspection (AOI) capability.
• Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.2 Predictable and fail-safe behavior
• Undervoltage detection with defined handling on all supply pins
NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
• Full functionality guaranteed from the undervoltage detection thresholds up to the
maximum limiting voltage values
• Defined behavior below the undervoltage detection thresholds
• Transceiver disengages from the bus (high-ohmic) when the supply voltage drops
below the Off mode threshold
• Internal biasing of TXD and mode selection input pins, to enable defined fail-safe
behavior
2.3 Low-power management
• Very low-current Standby mode with host and bus wake-up capability
• TJA1442A only: CAN wake-up receiver powered by VIO allowing VCC to be shut down
• CAN wake-up pattern filter time of 0.5 μs to 1.8 μs, meeting Classical CAN and CAN
FD requirements
2.4 Protection
• High ESD handling capability on the bus pins (8 kV IEC and HBM)
• Bus pins protected against transients in automotive environments
• Transmit Data (TXD) dominant time-out function
• Thermally protected
TJA1442
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1 — 12 August 2020
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
3 Quick reference data
Table 1.ꢀQuick reference data
Symbol
VCC
Parameter
Conditions
Min
Typ
Max Unit
supply voltage
supply current
4.5
-
5.5
60
7
V
ICC
Normal mode, dominant
Normal mode, recessive
Standby mode; TJA1442A
Standby mode; TJA1442B
-
38
4
-
mA
mA
μA
μA
V
-
-
2
-
8
-
12
4.5
Vuvd(stb)(VCC)
standby undervoltage detection
voltage on pin VCC
4
Vuvhys(stb)(VCC) standby undervoltage hysteresis
voltage on pin VCC
50
-
-
-
mV
V
Vuvd(swoff)(VCC) switch-off undervoltage detection TJA1442B
voltage on pin VCC
2.65
2.95
VIO
IIO
supply voltage on pin VIO
supply current on pin VIO
2.95
-
5.5
V
Normal mode, dominant; VTXD = 0 V
Normal mode, recessive; VTXD = VIO
Standby mode
-
250
150
8
760
460
11
µA
µA
µA
V
-
-
Vuvd(swoff)(VIO) switch-off undervoltage detection
voltage on pin VIO
2.65
-
2.95
VESD
VCANH
VCANL
Tvj
electrostatic discharge voltage
voltage on pin CANH
IEC 61000-4-2 on pins CANH and CANL -8
-
-
-
-
+8
kV
V
limiting value according to IEC 60134
limiting value according to IEC 60134
-36
+40
+40
voltage on pin CANL
-36
-40
V
virtual junction temperature
+150 °C
4 Ordering information
Table 2.ꢀOrdering information
Type number
Package
Name
SO8
Description
Version
TJA1442AT
TJA1442BT
TJA1442ATK
TJA1442BTK
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
HVSON8
plastic thermal enhanced very thin small outline package; no
leads; 8 terminals; body 3 × 3 × 0.85 mm
SOT782-1
TJA1442
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Product data sheet
Rev. 1 — 12 August 2020
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
5 Block diagram
(1)
5
VIO
VCC
3
TEMPERATURE
PROTECTION
(2)
IO CC
V
/V
7
CANH
TRANSMITTER
1
6
TXD
TIME-OUT
CANL
(2)
IO CC
V
/V
MODE
CONTROL
8
STB
(2)
V
/V
IO CC
normal
receiver
MUX
AND
DRIVER
4
RXD
low-power
receiver
WAKE-UP
FILTER
2
aaa-038094
GND
(1) VIO is only available in the TJA1442A (pin 5 is not connected in the TJA1442B).
(2) VIO in TJA1442A; VCC in TJA1442B.
Figure 1.ꢀBlock diagram
TJA1442
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Product data sheet
Rev. 1 — 12 August 2020
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
6 Pinning information
6.1 Pinning
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
TXD
GND
VCC
RXD
STB
TXD
GND
VCC
RXD
STB
CANH
CANL
VIO
CANH
CANL
n.c.
aaa-030475
aaa-030476
TJA1442AT: SO8
TJA1442BT: SO8
terminal 1
index area
terminal 1
index area
TXD
GND
VCC
RXD
1
2
3
4
8
STB
TXD
GND
VCC
RXD
1
2
3
4
8
STB
7
6
5
CANH
CANL
VIO
7
6
5
CANH
CANL
n.c.
aaa-030477
aaa-030478
Transparent top view
Transparent top view
TJA1442ATK: HVSON8
TJA1442BTK: HVSON8
Figure 2.ꢀPin configuration diagrams
6.2 Pin description
Table 3.ꢀPin description
Symbol
Pin
1
Type[1] Description
TXD
I
transmit data input; inputs data (from the CAN controller) to be written to the bus lines
ground
GND[2]
VCC
2
G
3
P
5 V supply voltage input
RXD
4
O
receive data output; outputs data read from the bus lines (to the CAN controller)
supply voltage input for I/O level adapter in TJA1442A
not connected in TJA1442B
VIO
5
P
n.c.
-
CANL
CANH
STB
6
7
8
AIO
AIO
I
LOW-level CAN bus line
HIGH-level CAN bus line
Standby mode control input; active-HIGH
[1] I: digital input; O: digital output; AIO: analog input/output; P: power supply; G: ground.
[2] HVSON package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground. For
enhanced thermal and electrical performance, it is also recommended to solder the exposed center pad to board ground.
TJA1442
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Product data sheet
Rev. 1 — 12 August 2020
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
7 Functional description
7.1 Operating modes
The TJA1442 supports three operating modes, Normal, Standby and Off. The operating
mode is selected via pin STB. See Table 4 for a description of the operating modes
under normal supply conditions. Mode changes are completed after transition time
tt(moch)
.
Table 4.ꢀOperating modes
Mode
Inputs
Pin STB
LOW
Outputs
Pin TXD
LOW
CAN driver
dominant
recessive
Pin RXD
Normal
LOW
HIGH
LOW when bus dominant
HIGH when bus recessive
follows BUS when wake-up detected
HIGH when no wake-up detected
high-ohmic state
Standby
Off[1]
HIGH
X
X
X
biased to ground
high-ohmic state
[1] Off mode is entered when the voltage on pin VIO (TJA1442A) or pin VCC (TJA1442B) is below the switch-off undervoltage detection threshold.
from any mode when
V
< V
for t > t
IO
uvd(swoff)(VIO) uvd(swoff)
OFF
(CAN BIAS =
high-ohmic)
V
> V for t > t
uvd(swoff)(VIO) startup
IO
STANDBY
(CAN BIAS =
0 V)
STB = HIGH
for t > t
STB = LOW
uvd(stb)(VCC)
OR (V
< V
)
det(uv)
AND (V
> V
for t > t
)
rec(uv)
CC
uvd(stb)(VCC)
CC
NORMAL
(CAN BIAS =
/2)
V
CC
aaa-038640
Figure 3.ꢀ TJA1442A state diagram
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
from any mode when
for t > t
V
CC
< V
uvd(swoff)(VCC)
uvd(swoff)
OFF
(CAN BIAS =
high-ohmic)
V
> V
for t > t
CC
uvd(swoff)(VCC) startup
STANDBY
(CAN BIAS =
0 V)
STB = HIGH
for t > t
STB = LOW
uvd(stb)(VCC)
OR (V
< V
uvd(stb)(VCC)
)
det(uv)
AND (V
> V
CC
for t > t
)
rec(uv)
CC
NORMAL
(CAN BIAS
= V /2)
CC
aaa-038642
Figure 4.ꢀ TJA1442B state diagram
7.1.1 Off mode
The TJA1442 switches to Off mode from any mode when the supply voltage (on pin
VIO in the TJA1442A and VCC in the TJA1442B) falls below the switch-off undervoltage
threshold (Vuvd(swoff)(VCC) or Vuvd(swoff)(VIO)). This is the default mode when the supply is
first connected.
In Off mode, the CAN pins and pin RXD are in a high-ohmic state.
7.1.2 Standby mode
When the supply voltage (VIO for TJA1442A or VCC for TJA1442B) rises above the
switch-off undervoltage detection threshold, the TJA1442 starts to boot up, triggering an
initialization procedure. The TJA1442 switches to the selected mode after tstartup
.
Standby mode is selected when pin STB goes HIGH. In this mode, the transceiver is
unable to transmit or receive data and a low-power receiver is activated to monitor
the bus for a wake-up pattern. The transmitter and Normal-mode receiver blocks are
switched off and the bus pins are biased to ground to minimize system supply current.
Pin RXD follows the bus after a wake-up request has been detected.
A transition to Normal mode is triggered when STB is forced LOW (provided VCC
Vuvd(stb)(VCC) and VIO > Vuvd(swoff)(VIO) in the TJA1442A).
>
If VCC is below Vuvd(stb)(VCC) when STB goes LOW (with VIO > Vuvd(swoff)(VIO) in TJA1442A
and VCC > Vuvd(swoff)(VCC) in TJA1442B), the TJA1442 will remain in Standby mode.
TJA1442
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Product data sheet
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
Pending wake-up events will be cleared and differential data on the bus pins converted to
digital data via the low-power receiver and output on pin RXD.
In the TJA1442A, the low-power receiver is supplied from VIO and can detect CAN bus
activity when VIO is above Vuvd(swoff)(VIO) (even if VIO is the only available supply voltage).
7.1.3 Normal mode
A LOW level on pin STB selects Normal mode, provided the supply voltage on pin VCC
is above the standby undervoltage detection threshold, Vuvd(stb)(VCC)
.
In this mode, the transceiver can transmit and receive data via bus lines CANH and
CANL. Pin TXD must be HIGH at least once in Normal Mode before transmission can
begin. The differential receiver converts the analog data on the bus lines into digital data
on pin RXD. The slopes of the output signals on the bus lines are controlled internally
and are optimized in a way that guarantees the lowest possible EME. In recessive state,
the output voltage on the bus pins is VCC/2.
7.1.4 Operating modes and gap-free operation
Gap-free operation guarantees defined behavior at all voltage levels. Supply voltage-to-
operating mode mapping is detailed in Figure 5 and in the state diagrams ( Figure 3 and
Figure 4).
TJA1442
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
TJA1442A
TJA1442B
[1]
[2][3]
[1]
[2][3]
5.5 V - 6 V
Fully functional
5.5 V - 6 V
Fully functional
[2][3]
Fully functional
or
[2]
[2]
Fully functional and
Fully functional and
characteristics
[4]
Off
V
operating range
CC
(4.5 V - 5.5 V)
V
operating range
CC
(4.5 V - 5.5 V)
characteristics
[5]
[5]
guaranteed
guaranteed
Off
[2]
[2]
[2]
Fully functional or
Fully functional or
Fully functional or
[6]
V
range
V
range
uvd(stb)(VCC)
uvd(stb)(VCC)
[4]
[4]
[4]
Standby or Off
Standby
Standby
2.95 V - 4 V
Standby
[4]
[4]
-0.3 V - 4 V
V
range
Standby or Off
Standby
Standby or Off
uvd(swoff)(VCC)
-0.3 V - 2.65 V
Off
Voltage range on VIO
[1] 6 V is the IEC 60134 Absolute Maximum Rating (AMR) for VCC and VIO (see Limiting values table). Above the AMR, irreversible changes in
characteristics, functionality or performance may occur. Returning from above AMR to the operating range, datasheet characteristics and
functionality cannot be guaranteed.
[2] Target transceiver functionality as described in this datasheet is applicable.
[3] Prolonged operation of the device outside the operating range may impact reliability over lifetime. Returning to the operating range, datasheet
characteristics are guaranteed provided the AMR has not been exceeded.
[4] For a given value of V
(and V in TJA1442A), a specific device will be in a single defined state determined by its undervoltage detection
CC
IO
thresholds (V
, V
and V ). The actual thresholds can vary between devices (within the ranges specified
uvd(swoff)(VCC)
uvd(stb)(VCC) uvd(swoff)(VIO)
in this data sheet). To guarantee the device will be in a specific state, V and V
must be either above the maximum or below the
IO
CC
minimum thresholds specified for these undervoltage detection ranges.
[5] Datasheet characteristics are guaranteed within the V
characteristics tables.
and V operating ranges. Exceptions are described in the Static and Dynamic
CC
IO
[6] The following applies to TJA1442A:
- If both V
and V are above the undervoltage threshold, the device is fully functional.
CC
IO
- If V
is below and V above the undervoltage threshold, the device is in Standby mode.
CC
IO
- If V is below the undervoltage threshold, the device is in Off mode, regardless of V
.
IO
CC
aaa-038067
Figure 5.ꢀSupply voltage ranges and gap-free operation
7.2 Remote wake-up (via the CAN bus)
The TJA1442 wakes up from Standby mode when a dedicated wake-up pattern
(specified in ISO 11898-2: 2016) is detected on the bus.
The wake-up pattern consists of:
• a dominant phase of at least twake(busdom) followed by
• a recessive phase of at least twake(busrec) followed by
• a dominant phase of at least twake(busdom)
Dominant or recessive bits between the above mentioned phases that are shorter than
twake(busdom) and twake(busrec) respectively are ignored.
The complete dominant-recessive-dominant pattern must be received within tto(wake)bus to
be recognized as a valid wake-up pattern (see Figure 6). Otherwise, the internal wake-up
TJA1442
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Product data sheet
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
logic is reset. The complete wake-up pattern then needs to be retransmitted to trigger a
wake-up event. Pin RXD remains HIGH until the wake-up event has been triggered.
After a wake-up sequence has been detected, the TJA1442 remains in Standby mode
with the bus signals reflected on RXD after tstartup(RXD). Note that dominant or recessive
phases lasting less than tfltr(wake)bus will not be detected by the low-power differential
receiver and will not be reflected on RXD in Standby mode.
A wake-up event is not flagged on RXD if any of the following events occurs while a valid
wake-up pattern is being received:
• The device switches to Normal mode
• The complete wake-up pattern was not received within tto(wake)bus
• A VCC or VIO switch-off undervoltage is detected (VCC < Vuvd(swoff)(VCC) or VIO
<
Vuvd(swoff)(VIO); see Section 7.3.3)
CANH
CANL
V
O(dif)
t
t
t
t
t
t < t
t < t
fltr(wake)bus
wake(busrec)
fltr(wake)bus fltr(wake)bus
fltr(wake)bus fltr(wake)bus
fltr(wake)bus
t
t
t
t
fltr(wake)bus
wake(busdom)
wake(busdom)
fltr(wake)bus
(1)
t
startup(RXD)
RXD
wake-up
pattern detected
t ≤ t
to(wake)bus
aaa-031221
(1) During tstartup(RXD), the low-power receiver is on but pin RXD is not active (i.e. HIGH/recessive). The first dominant
pulse of width ≥ tfltr(wake)bus that ends after tstartup(RXD) will trigger RXD to go LOW/dominant.
Figure 6.ꢀWake-up timing
7.3 Fail-safe features
7.3.1 TXD dominant time-out function
A 'TXD dominant time-out' timer is started when pin TXD is set LOW. If the LOW state on
this pin persists for longer than tto(dom)TXD, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.
7.3.2 Internal biasing of TXD and STB input pins
Pins TXD and STB have internal pull-ups to VCC/VIO to ensure a safe, defined state in
case one, or both, of these pins is left or becomes floating. Pull-up resistors are active
on these pins in all states; they should be held at the VCC/VIO level in Standby mode to
minimize supply current.
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
7.3.3 Undervoltage detection on pins VCC and VIO
If VCC drops below the standby undervoltage detection threshold (Vuvd(stb)(VCC)) for tdet(uv)
,
the transceiver switches to Standby mode. The logic state of pin STB is ignored until VCC
has recovered.
In the TJA1442A, if VIO drops below the switch-off undervoltage detection threshold
(Vuvd(swoff)(VIO)) for tuvd(swoff), the transceiver switches to Off mode and disengages from
the bus (high-ohmic) until VIO has recovered.
In the TJA1442B, if VCC drops below the switch-off undervoltage detection threshold
(Vuvd(swoff)(VCC)) for tuvd(swoff), the transceiver switches to Off mode and disengages from
the bus (high-ohmic) until VCC has recovered.
7.3.4 Overtemperature protection
The device is protected against overtemperature conditions. If the junction temperature
exceeds the shutdown junction temperature, Tj(sd), the CAN bus drivers are disabled.
When the junction temperature drops below Tj(sd)rel, the CAN bus drivers recover once
TXD has been reset to HIGH and Normal mode is selected (waiting for TXD to go HIGH
prevents output driver oscillation due to small variations in temperature).
7.3.5 I/O levels
Pin VIO on the TJA1442A should be connected to the microcontroller supply voltage
(see Figure 10). This adjusts the signal levels on pins TXD, RXD and STB to the I/O
levels of the microcontroller, allowing for direct interfacing without additional glue logic.
Pin VIO also provides the internal supply voltage for the low-power differential receiver.
For applications running in low-power mode, this allows the bus lines to be monitored for
activity even if there is no supply voltage on pin VCC.
All I/O levels are related to VCC in the TJA1442B and are, therefore, compatible with 5 V
microcontrollers. Spurious signals from the microcontroller on pin STB are filtered out
with a filter time of tfltr(IO)
.
TJA1442
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Product data sheet
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
8 Limiting values
Table 5.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND, unless
otherwise specified.
Symbol
Parameter
voltage on pin x[1]
Conditions
Min Max
Unit
V
Vx
pins VCC, VIO (TJA1442A), TXD, STB
-0.3 +6
-
+7[2]
V
pins CANH, CANL
pin RXD
-36
+40
V
TJA1442A
-0.3 VIO+0.3[3]
-0.3 VCC+0.3[3]
V
V
V
TJA1442B
V(CANH-CANL) voltage between pin CANH
and pin CANL
-40
+40
[4]
Vtrt
transient voltage
on pins CANH, CANL
pulse 1
-100
-
V
V
V
V
pulse 2a
-
+75
-
pulse 3a
-150
-
pulse 3b
+100
[5]
VESD
electrostatic discharge
voltage
IEC 61000-4-2 (150 pF, 330 Ω discharge circuit)
on pins CANH, CANL
Human Body Model (HBM)
on any pin
-8
+8
kV
[6]
[7]
[8]
-4
-8
+4
+8
kV
kV
on pins CANH, CANL
Charged Device Model (CDM)
on corner pins
-750 +750
-500 +500
V
on any other pin
V
[9]
Tvj
virtual junction temperature
storage temperature
-40
-55
+150
+150
°C
°C
Tstg
[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these
values.
[2] The device can withstand voltages between 6 V and 7 V for a total of 20 s over the product lifetime.
[3] Subject to the qualifications detailed in Table notes 1 and 2 above for pins VCC, VIO, TXD and STB.
[4] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637.
[5] Verified by an external test house according to IEC TS 62228, Section 4.3.
[6] According to AEC-Q100-002.
[7] Pins stressed to reference group containing all ground and supply pins, emulating the application circuits (Figure 10 and Figure 11). HBM pulse as
specified in AEC-Q100-002 used.
[8] According to AEC-Q100-011.
[9] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P × Rth(j-a), where Rth(j-a) is a fixed value used in
the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
TJA1442
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Product data sheet
Rev. 1 — 12 August 2020
12 / 30
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TJA1442
High-speed CAN transceiver with Standby mode
9 Thermal characteristics
Table 6.ꢀThermal characteristics
Value determined for free convection conditions on a JEDEC 2S2P board.
Symbol
Parameter
Conditions[1]
SO8
Typ
96
57
19
9
Unit
K/W
K/W
K/W
K/W
K/W
Rth(j-a)
thermal resistance from junction to ambient
HVSON8
HVSON8
SO8
Rth(j-c)
Ѱj-top
thermal resistance from junction to case[2]
thermal characterization parameter from junction to top of package
HVSON8
9
[1] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm)
and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 μm).
[2] Case temperature refers to the center of the heatsink at the bottom of the package.
10 Static characteristics
Table 7.ꢀStatic characteristics
Tvj = -40 °C to +150 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJA1442A); RL = 60 Ω unless specified otherwise; all
voltages are defined with respect to ground; positive currents flow into the IC.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin VCC
VCC
supply voltage
4.5
4
-
-
5.5
4.5
V
V
[2]
[2]
Vuvd(stb)
standby undervoltage
detection voltage
Vuvhys(stb)
Vuvd(swoff)
ICC
standby undervoltage
hysteresis voltage
50
-
-
-
mV
V
switch-off undervoltage
detection voltage
TJA1442B
2.65
2.95
supply current
Normal mode
dominant; VTXD = 0 V; t < tto(dom)TXD
-
-
38
-
60
mA
mA
dominant; VTXD = 0 V;
125
short circuit on bus lines;
-3 V < (VCANH = VCANL) < +40 V
[3]
recessive; VTXD = VIO
-
4
7
mA
Standby mode
TJA1442A; Tvj < 85 °C
TJA1442B; Tvj < 85 °C
-
-
-
2
µA
µA
8
12
I/O level adapter supply; pin VIO (TJA1442A)
VIO
supply voltage
2.95
2.65
-
-
5.5
V
V
[2]
Vuvd(swoff)
switch-off undervoltage
detection voltage
2.95
IIO
supply current
Normal mode, dominant; VTXD = 0 V
Normal mode, recessive; VTXD = VIO
-
-
250
150
760
460
µA
µA
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standby mode; Tvj < 85 °C
-
8
11
µA
CAN transmit data input; pin TXD
[3]
VIH
HIGH-level input voltage
0.7VIO
-
-
-
-
V
[3]
VIL
LOW-level input voltage
-
0.3VIO
-
V
Vhys(TXD)
hysteresis voltage on pin
TXD
50
mV
Rpu
Ci
pull-up resistance
input capacitance
20
-
-
-
80
10
kΩ
pF
[4]
CAN receive data output; pin RXD
IOH HIGH-level output current
IOL LOW-level output current
Standby control input; pin STB
VRXD = VIO[3] - 0.4 V
-10
1
-
-
-1
mA
mA
VRXD = 0.4 V; bus dominant
10
[3]
VIH
VIL
Vhys
Rpu
Ci
HIGH-level input voltage
0.7VIO
-
-
-
-
-
-
V
[3]
LOW-level input voltage
hysteresis voltage
pull-up resistance
input capacitance
-
0.3VIO
V
50
20
-
-
mV
kΩ
pF
80
10
[4]
Bus lines; pins CANH and CANL
VO(dom)
dominant output voltage
VTXD = 0 V; t < tto(dom)TXD; VCC ≥ 4.75 V
pin CANH; RL = 50 Ω to 65 Ω
2.75
0.5
3.5
1.5
-
4.5
V
V
V
pin CANL; RL = 50 Ω to 65 Ω
2.25
[4]
[5]
VTXsym
Vcm(step)
Vcm(p-p)
VO(dif)
transmitter voltage
symmetry
VTXsym = VCANH + VCANL
;
0.9VCC
1.1VCC
+150
CSPLIT = 4.7 nF;
fTXD = 250 kHz, 1 MHz or 2.5 MHz
[4]
[5]
[6]
common mode voltage step
-150
-
-
mV
mV
[4]
[5]
[6]
peak-to-peak common mode
voltage
-300
+300
differential output voltage
dominant; Normal mode; VTXD = 0 V;
t < tto(dom)TXD; VCC ≥ 4.75 V
RL = 50 Ω to 65 Ω
RL = 45 Ω to 70 Ω
RL = 2240 Ω
1.5
1.4
1.5
-
-
-
3
V
V
V
3.3
5
[4]
recessive; no load
[3]
Normal mode; VTXD = VIO
-50
-0.2
2
-
+50
+0.2
3
mV
V
Standby mode
-
VO(rec)
recessive output voltage
Normal mode; VTXD = VIO[3]; no load
2.5
-
V
Standby mode; no load
-0.1
+0.1
V
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth(RX)dif
differential receiver
threshold voltage
-12 V ≤ VCANH ≤ +12 V;
-12 V ≤ VCANL ≤ +12 V
Normal mode
Standby mode
0.5
0.4
-
-
0.9
1.1
V
V
Vrec(RX)
receiver recessive voltage
receiver dominant voltage
-12 V ≤ VCANH ≤ +12 V;
-12 V ≤ VCANL ≤ +12 V
Normal mode
Standby mode
-4
-4
-
-
+0.5
+0.4
V
V
Vdom(RX)
-12 V ≤ VCANH ≤ +12 V;
-12 V ≤ VCANL ≤ +12 V
Normal mode
Standby mode
0.9
1.1
50
-
-
-
9
9
-
V
V
Vhys(RX)dif
IO(sc)
differential receiver
hysteresis voltage
-12 V ≤ VCANH ≤ +12 V;
mV
-12 V ≤ VCANL ≤ +12 V; Normal mode
short-circuit output current
-15 V ≤ VCANH ≤ +40 V;
-15 V ≤ VCANL ≤ +40 V
-
-
-
115
+3
mA
mA
IO(sc)rec
recessive short-circuit output -27 V ≤ VCANH ≤ +32 V;
-3
current
-27 V ≤ VCA[3N] L ≤ +32 V; Normal mode;
VTXD = VIO
IL
leakage current
input resistance
input resistance deviation
VCC = VIO = 0 V or pins shorted to GND
via 47 KΩ; VCANH = VCANL = 5 V
-10
25
-
+10
50
µA
kΩ
Ri
-2 V ≤ VCANL ≤ +7 V;
-2 V ≤ VCANH ≤ +7 V
40
ΔRi
0 V ≤ VCANL ≤ +5 V; 0 V ≤ VCANH ≤ +5 V
-3
-
+3
%
Ri(dif)
differential input resistance -2 V ≤ VCANL ≤ +7 V;
-2 V ≤ VCANH ≤ +7 V
50
80
100
kΩ
[4]
[4]
Ci(cm)
Ci(dif)
common-mode input
capacitance
-
-
-
-
20
10
pF
pF
differential input capacitance
Temperature detection
[4]
[4]
Tj(sd)
shutdown junction
temperature
180
175
-
-
200
195
°C
°C
Tj(sd)rel
release shutdown junction
temperature
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage ranges.
[2] Undervoltage is detected between min and max values. Undervoltage is guaranteed to be detected below min value and guaranteed not to be detected
above max value.
[3] VCC in TJA1442B
[4] Not tested in production; guaranteed by design.
[5] The test circuit used to measure the bus output voltage symmetry and the common-mode voltages (which includes CSPLIT) is shown in Figure 13.
[6] See Figure 9
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
11 Dynamic characteristics
Table 8.ꢀDynamic characteristics
Tvj = -40 °C to +150 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJA1442A); RL = 60 Ω unless specified otherwise; all
voltages are defined with respect to ground.[1]
Symbol
Parameter
Conditions
Min
Typ
Max Unit
CAN timing characteristics; tbit(TXD) ≥ 200 ns; see Figure 7, Figure 8 and Figure 12
td(TXD-busdom) delay time from TXD to bus dominant
td(TXD-busrec) delay time from TXD to bus recessive
td(busdom-RXD) delay time from bus dominant to RXD
td(busrec-RXD) delay time from bus recessive to RXD
td(TXDL-RXDL) delay time from TXD LOW to RXD LOW
td(TXDH-RXDH) delay time from TXD HIGH to RXD HIGH
Normal mode
Normal mode
Normal mode
Normal mode
Normal mode
Normal mode
-
-
-
-
-
-
-
-
-
-
-
-
102.5 ns
102.5 ns
127.5 ns
127.5 ns
230
230
ns
ns
CAN FD timing characteristics according to ISO 11898-2:2016; see Figure 8 and Figure 12
tbit(bus)
transmitted recessive bit width
receiver timing symmetry
bit time on pin RXD
tbit(TXD) = 500 ns
tbit(TXD) = 200 ns
tbit(TXD) = 500 ns
tbit(TXD) = 200 ns
tbit(TXD) = 500 ns
tbit(TXD) = 200 ns
435
155
-65
-
-
-
-
-
-
530
210
+40
+15
550
220
ns
ns
ns
ns
ns
ns
Δtrec
-45
tbit(RXD)
400
120
Dominant time-out time; pin TXD
[2]
[3]
tto(dom)TXD
TXD dominant time-out time
VTXD = 0 V; Normal mode
0.8
-
9
ms
Bus wake-up times; pins CANH and CANL; Figure 6
twake(busdom) bus dominant wake-up time
[2]
[4]
Standby mode
Standby mode
Standby mode
Standby mode
0.5
0.5
0.8
-
-
-
-
-
1.8
1.8
9
µs
µs
ms
µs
[2]
[4]
twake(busrec)
tto(wake)bus
tfltr(wake)bus
bus recessive wake-up time
bus wake-up time-out time
bus wake-up filter time
[2]
[3]
[2]
1.8
Mode transitions
[2]
[2]
tt(moch)
mode change transition time
-
-
-
-
50
1
µs
ms
µs
tstartup
start-up time
-
[2]
[5]
tstartup(RXD)
RXD start-up time
to Standby mode after wake-
up
4
20
IO filter; pin STB
[6]
tfltr(IO)
IO filter time
1
-
5
µs
Undervoltage detection; Figure 3 and Figure 4
[2]
[2]
tdet(uv)
undervoltage detection time
on pin VCC
-
-
-
-
30
30
µs
µs
tuvd(swoff)
switch-off undervoltage detection time
on pin VCC; TJA1442B
TJA1442
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Product data sheet
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
Symbol
Parameter
Conditions
Min
Typ
Max Unit
[2]
[2]
on pin VIO; TJA1442A
on pin VCC
30
50
µs
µs
trec(uv)
undervoltage recovery time
-
-
[1] All parameters are guaranteed over the junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage ranges.
[2] Not tested in production; guaranteed by design.
[3] Time-out occurs between the min and max values. Time-out is guaranteed not to occur below the min value; time-out is guaranteed to occur above the
max value.
[4] A dominant/recessive phase shorter than the min value is guaranteed not be seen as a dominant/recessive bit; a dominant/recessive phase longer than
the max value is guaranteed to be seen as a dominant/recessive bit.
[5] When a wake-up is detected, RXD start-up time is between the min and max values. RXD cannot be relied on below the min value; RXD can be relied on
above the max value; see Figure 6.
[6] Pulses shorter than the min value are guaranteed to be filtered out; pulses longer than the max value are guaranteed to be processed.
HIGH
70 %
TXD
30 %
LOW
CANH
CANL
dominant
0.9 V
V
O(dif)
0.5 V
recessive
HIGH
70 %
RXD
30 %
LOW
t
t
d(TXD-busrec)
d(TXD-busdom)
t
d(busdom-RXD)
t
d(busrec-RXD)
aaa-029311
Figure 7.ꢀCAN transceiver timing diagram
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
70 %
TXD
30 %
30 %
t
5 x t
bit(TXD)
d(TXDL-RXDL)
t
bit(TXD)
0.9 V
V
O(dif)
0.5 V
t
bit(bus)
70 %
RXD
30 %
t
d(TXDH-RXDH)
t
bit(RXD)
aaa-029312
Figure 8.ꢀCAN FD timing definitions according to ISO 11898-2:2016
CANH
CANL
V
cm(step)
V
CANH
+ V
CANL
V
cm(p-p)
aaa-037830
Figure 9.ꢀCAN bus common-mode voltage
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
12 Application information
12.1 Application diagrams
BAT
3.3 V
(1)
on/off control
(1)
5 V
VCC
VIO
VDD
Pxx
CANH
CANH
STB
Pyy
MICRO-
CONTROLLER
TXD
RXD
TX0
RX0
CANL
CANL
GND
GND
aaa-038119
(1) Optional, depends on regulator.
Figure 10.ꢀTypical TJA1442A application with a 3.3 V microcontroller
5 V
BAT
(1)
VCC
VDD
CANH
CANH
Pxx
Pyy
TX0
RX0
STB
TXD
RXD
MICRO-
CONTROLLER
CANL
CANL
GND
GND
aaa-038118
(1) Optional, depends on regulator.
Figure 11.ꢀTypical TJA1442B application with a 5 V microcontroller
12.2 Application hints
Further information on the application of the TJA1442 can be found in NXP application
hints AH2002 'TJx144x/TJx146x Application Hints', available on request from NXP
Semiconductors.
TJA1442
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Product data sheet
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
13 Test information
TXD
RXD
CANH
CANL
R
60 Ω
C
L
100 pF
L
15 pF
aaa-030850
Figure 12.ꢀCAN transceiver timing test circuit
TXD
RXD
CANH
CANL
30 Ω
30 Ω
f
TXD
C
4.7 nF
SPLIT
aaa-030851
Figure 13.ꢀTest circuit for measuring transceiver driver symmetry
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-H - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
TJA1442
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Product data sheet
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
14 Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
detail X
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
0.25
0.01
0.25
0.1
1.75
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Figure 14.ꢀPackage outline SOT96-1 (SO8)
TJA1442
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NXP Semiconductors
TJA1442
High-speed CAN transceiver with Standby mode
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 x 3 x 0.85 mm
SOT782-1
X
B
A
D
E
A
A
1
c
detail X
terminal 1
index area
e
1
C
terminal 1
index area
B
A
v
w
C
C
e
b
y
y
C
1
1
4
L
K
E
h
8
5
D
h
0
1
2 mm
L
scale
Dimensions
(1)
Unit
A
A
b
c
D
D
h
E
E
e
e
1
K
v
w
y
y
1
1
h
max 1.00 0.05 0.35
mm nom 0.85 0.03 0.30 0.2 3.00 2.40 3.00 1.60 0.65 1.95 0.30 0.40 0.1 0.05 0.05 0.1
min 0.80 0.00 0.25 2.90 2.35 2.90 1.55 0.25 0.35
3.10 2.45 3.10 1.65
0.35 0.45
Note
1. Plastic or metal protrusions of 0.075 maximum per side are not included.
sot782-1_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
09-08-25
09-08-28
SOT782-1
MO-229
Figure 15.ꢀPackage outline SOT782-1 (HVSON8)
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
15 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
TJA1442
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TJA1442
High-speed CAN transceiver with Standby mode
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 16) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with Table 9
and Table 10
Table 9.ꢀSnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
235
≥ 350
< 2.5
≥ 2.5
220
220
220
Table 10.ꢀLead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 16.
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High-speed CAN transceiver with Standby mode
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 16.ꢀTemperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17 Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can be found in the following application note:
• AN10365 “Surface mount reflow soldering description”
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18 Appendix: ISO 11898-2:2016 parameter cross-reference list
Table 11.ꢀISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016
NXP data sheet
Notation Symbol Parameter
Parameter
HS-PMA dominant output characteristics
Single ended voltage on CAN_H
Single ended voltage on CAN_L
Differential voltage on normal bus load
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
VCAN_H
VCAN_L
VDiff
VO(dom)
dominant output voltage
differential output voltage
VO(dif)
Driver symmetry
VSYM
VTXsym
transmitter voltage symmetry
short-circuit output current
Maximum HS-PMA driver output current
Absolute current on CAN_H
ICAN_H
ICAN_L
IO(sc)
Absolute current on CAN_L
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H
Single ended output voltage on CAN_L
Differential output voltage
VCAN_H
VCAN_L
VDiff
VO(rec)
recessive output voltage
differential output voltage
TXD dominant time-out time
VO(dif)
Optional HS-PMA transmit dominant time-out
Transmit dominant time-out, long
tdom
tto(dom)TXD
Transmit dominant time-out, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
Dominant state differential input voltage range
VDiff
Vth(RX)dif
differential receiver threshold
voltage
Vrec(RX)
receiver recessive voltage
receiver dominant voltage
Vdom(RX)
HS-PMA receiver input resistance (matching)
Differential internal resistance
RDiff
RCAN_H
RCAN_L
Ri(dif)
Ri
differential input resistance
input resistance
Single ended internal resistance
Matching of internal resistance
HS-PMA implementation loop delay requirement
Loop delay
MR
ΔRi
input resistance deviation
tLoop
td(TXDH-RXDH) delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL)
delay time from TXD LOW to
RXD LOW
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ISO 11898-2:2016
Parameter
NXP data sheet
Notation Symbol
Parameter
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to 2
Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
tBit(Bus)
tbit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff
tBit(RXD)
ΔtRec
tbit(RXD)
Δtrec
bit time on pin RXD
receiver timing symmetry
VDiff
V(CANH-CANL) voltage between pin CANH and
pin CANL
General maximum rating VCAN_H and VCAN_L
VCAN_H
VCAN_L
Vx
voltage on pin x
Optional: Extended maximum rating VCAN_H and VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
ICAN_H
ICAN_L
IL
leakage current
HS-PMA bus biasing control timings
CAN activity filter time, long
CAN activity filter time, short
Wake-up time-out, short
[1]
tFilter
twake(busdom)
twake(busrec)
bus dominant wake-up time
bus recessive wake-up time
tWake
tto(wake)bus
bus wake-up time-out time
Wake-up time-out, long
[1] tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality
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19 Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
19.2 Definitions
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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High-speed CAN transceiver with Standby mode
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Security — While NXP Semiconductors has implemented advanced
security features, all products may be subject to unidentified vulnerabilities.
Customers are responsible for the design and operation of their applications
and products to reduce the effect of these vulnerabilities on customer’s
applications and products, and NXP Semiconductors accepts no liability for
any vulnerability that is discovered. Customers should implement appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
19.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
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Contents
1
General description ............................................ 1
1.1
2
TJA1442 variants ...............................................1
Features and benefits .........................................1
General .............................................................. 1
Predictable and fail-safe behavior ..................... 1
Low-power management ................................... 2
Protection ...........................................................2
Quick reference data .......................................... 3
Ordering information .......................................... 3
Block diagram ..................................................... 4
Pinning information ............................................ 5
Pinning ...............................................................5
Pin description ...................................................5
Functional description ........................................6
Operating modes ............................................... 6
Off mode ............................................................7
Standby mode ................................................... 7
Normal mode .....................................................8
Operating modes and gap-free operation ..........8
Remote wake-up (via the CAN bus) ..................9
Fail-safe features .............................................10
TXD dominant time-out function ...................... 10
Internal biasing of TXD and STB input pins ..... 10
Undervoltage detection on pins VCC and
2.1
2.2
2.3
2.4
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.3.1
7.3.2
7.3.3
VIO ...................................................................11
Overtemperature protection .............................11
I/O levels ..........................................................11
Limiting values ..................................................12
Thermal characteristics ....................................13
Static characteristics ........................................13
Dynamic characteristics ...................................16
Application information ....................................19
Application diagrams ....................................... 19
Application hints .............................................. 19
Test information ................................................20
Quality information ...........................................20
Package outline .................................................21
Handling information ........................................23
Soldering of SMD packages .............................23
Introduction to soldering .............................
Wave and reflow soldering .........................
Wave soldering ...........................................
Reflow soldering .........................................
Soldering of HVSON packages ........................25
Appendix: ISO 11898-2:2016 parameter
cross-reference list ...........................................26
Legal information ..............................................28
7.3.4
7.3.5
8
9
10
11
12
12.1
12.2
13
13.1
14
15
16
16.1
16.2
16.3
16.4
17
18
19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2020.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 August 2020
Document identifier: TJA1442
相关型号:
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