TDA9802T-T [NXP]
IC AUDIO/VIDEO DEMODULATOR, PDSO20, Receiver IC;
| 型号： | TDA9802T-T |
| 厂家： | 
NXP |
| 描述： | IC AUDIO/VIDEO DEMODULATOR, PDSO20, Receiver IC 光电二极管 |
| 文件： | 总23页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9802
Multistandard VIF-PLL
demodulator and FM-PLL detector
November 1992
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator
and FM-PLL detector
TDA9802
• AGC output voltage for tuner; adjustable take-over point
FEATURES
(TOP)
• Suitable for negative and positive vision modulation
• AFC detector without extra reference circuit
• Gain controlled 3-stage IF amplifier; suitable for VIF
frequencies up to 60 MHz
• Alignment-free FM-PLL detector with high linearity
• Stabilizer circuit for ripple rejection and to achieve
constant output signals
• True synchronous demodulation with active carrier
regeneration (ultra-linear demodulation, good
intermodulation figures, reduced harmonics and
excellent pulse response)
• 5 to 8 V positive supply voltage range, low power
consumption (300 mW at +5 V supply voltage)
• Peak sync AGC for negative modulation, e.g. B/G
standard
GENERAL DESCRIPTION
• Peak white AGC for positive modulation, e.g. L standard
• Video amplifier to match sound trap and sound filter
The TDA9802 is a monolithic integrated circuit for vision
and sound IF signal processing in multistandard TV and
VTR sets.
QUICK REFERENCE DATA
SYMBOL
VP
PARAMETER
positive supply voltage (pin 20)
supply current
MIN.
4.5
51
TYP.
MAX.
8.8
UNIT
5
V
IP
60
50
150
70
2.0
8
69
90
−
mA
µV
mV
dB
V
Vi IF
vision IF input signal sensitivity (RMS value, pins 1 and 2) −
maximum vision IF input signal (RMS value, pins 1 and 2) 70
Gv
IF gain control range
64
1.7
6
73
2.3
−
Vo CVBS
B
CVBS output signal on pin 7 (peak-to-peak value)
−3 dB video bandwidth on pin 7
signal-to-noise ratio weighted; for video
intermodulation attenuation
MHz
dB
dB
dB
dB
V
S/N (W)
α1.1
56
56
56
35
0.8
59
62
62
40
−
−
−
α3.3
−
αH
suppression of harmonics in video signal
−
Vo AF
maximum AF output signal for THD < 1.5% (RMS value,
−
pin 9)
Tamb
operating ambient temperature range
0
−
+70
°C
ORDERING INFORMATION
PACKAGE
EXTENDED
TYPE NUMBER
PINS
20
PIN POSITION
DIL
MATERIAL
CODE
SOT146(1)
SOT163A(2)
TDA9802
plastic
plastic
TDA9802T
20
mini-pack
Note
1. SOT146-1; 1996 November 19.
2. SOT163-1; 1996 November 19.
November 1992
2
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
Fig.1 Block diagram.
November 1992
3
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
PINNING
SYMBOL
Vi IF
PIN
DESCRIPTION
1
2
3
4
5
6
7
8
vision IF differential input signal
TADJ
φADJ
CBL
tuner AGC take-over adjust (TOP)
phase detector adjust
black level capacitor, mute switch input
PLL time constant of phase detector
CVBS (positive) output signal
TPLL
Vo CVBS
STD
standard switch (negative = HIGH,
positive = LOW)
Vo AF
CAF
9
audio frequency output signal
10
11
12
13
14
15
16
17
18
19
20
decoupling capacitor of audio frequency amplifier
sound intercarrier input signal
Vi IC
TAGC
Vo VID
Vi VID
AFC
tuner AGC output
video and sound intercarrier output signal
video input signal to buffer amplifier
automatic frequency control output
VCO reference circuit for 2 fPC
VCO1
VCO2
GND
CAGC
VP
ground (0 V)
AGC capacitor
Fig.2 Pin configuration.
positive supply voltage
November 1992
4
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
FUNCTIONAL DESCRIPTION
Vision IF input
VCO and travelling wave divider
The VCO operates with a symmetrically-connected
reference LC-circuit, operating at double vision carrier
frequency. Frequency control is performed by an internal
varicap diode. The voltage to set the VCO frequency to the
actual frequency of double vision carrier frequency, is also
amplified and converted for the AFC output current.
The VCO signal is divided-by-two in a travelling wave
divider, which generates two differential output signals
with 90 degree phase difference independent of
frequency.
The vision IF amplifier consists of three AC-coupled
differential amplifier stages; each stage comprises a
controlled feedback network by means of emitter
degeneration.
IF and tuner AGC
The automatic control voltage to maintain the video output
signal at a constant level is generated according to the
transmission standard. For negative modulation the
peak-sync level is detected, for positive modulation the
peak white level is detected. The AGC detector charges
and discharges the capacitor on pin 19 to set the IF gain
and the tuner gain. The standard is switched by the voltage
on pin 8. To reduce the response time for positive
modulation (which needs a very long time constant) a
black level detector (CBL) increases the AGC capacitor
discharge current for low-level video signals.
Video amplifier, buffer and noise clipping
The video amplifier is a wide bandwidth operational
amplifier with internal feedback. Dependent on
transmission standard, a level shifter provides the same
sync level for positive as for negative modulation. A
nominal positive modulated video signal of 1 V (p-p) is
present on the composite video output (pin 13).
The input impedance of the 7 dB wideband buffer amplifier
(with internal feedback) is suitable for ceramic sound trap
filters.
The CVBS output (pin 7) provides a positive video signal
of 2 V (p-p). Noise clipping is provided internally.
The AGC capacitor voltage is transferred to an internal IF
control signal, and is fed to the tuner AGC to generate the
tuner AGC output current on pin 12 (open-collector
output). The tuner AGC voltage take over point is adjusted
on pin 3. This allows the tuner and the IF SAW filter to be
matched to achieve the optimum IF input level.
Sound demodulation
Frequency detector, phase detector and video
demodulator
The FM sound intercarrier signal is fed to pin 11 and
through a limiter amplifier before it is demodulated. This
achieves high sensitivity and high AM suppression. The
limiter amplifier consists of seven internal AC-coupled
stages, minimizing the DC offset.
The FM-PLL demodulator consists of an RC-oscillator,
loop filter and phase detector. The oscillator frequency is
locked on the FM intercarrier signal from the limiter
amplifier.
As a result of this locking, the RC-oscillator is
frequency-modulated. The modulating signal voltage (AF
signal) is used to control the oscillator frequency. By this,
the FM-PLL operates as an FM demodulator.
The audio frequency amplifier with internal feedback is
designed for high gain and high common mode rejection.
The low-level AF signal output from the FM-PLL
demodulator is amplified and buffered in a low-ohmic
audio signal output stage (pin 9). An external decoupling
capacitor on pin 10 removes the DC voltage from the audio
amplifier input.
The IF amplifier output signal is fed to a frequency detector
and to a phase detector. The frequency detector is
operational before lock-in. A DC current is generated
which is proportional to the frequency difference between
the input frequency and the VCO frequency. After lock-in,
the frequency detector and the phase detector generate a
DC current proportional to the phase difference between
VCO and input signals. The control signal for the VCO is
provided by the phase detector. The video demodulator is
a linear multiplier, designed for low distortion and wide
bandwidth. The vision IF input signal is multiplied by the
in-phase component of the VCO output. The demodulated
output signal is fed via an integrated low-pass filter
(fg = 12 MHz) to the video amplifier for suppression of the
carrier harmonics. The polarity of the video signal is
switched in the demodulator stage according to the TV
standard.
November 1992
5
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134)
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VP
supply voltage (pin 20) for a maximum chip temperature (note 1)
SOT146 at + 120 °C
0
0
0
−
−
8.8
V
V
V
s
SO163A at + 100 °C
5.5
VI
voltage on pins 1, 2, 7, 8, 11, 13, 14, 15 and 19
short-circuit time
VP
ts max
V12
10
tuner AGC output voltage
13.2
+150
±300
V
Tstg
storage temperature range
−25
°C
VESD
electrostatic handling for all pins (note 2)
−
V
Notes to the Limiting Values
1. Supply current IP = 69 mA at Tamb = +70 °C.
2. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (negative and positive voltage).
THERMAL RESISTANCE
SYMBOL
PARAMETER
THERMAL RESISTANCE
Rth j-a
from junction to ambient in free air
SOT146
73 K/W
85 K/W
SOT163A
November 1992
6
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
CHARACTERISTICS
VP = 5 V; Tamb = +25 °C; fPC = 38.9 MHz; fSC = 33.4 MHz with VPC/VSC = 13 dB (B/G); ViIF = 10 mV RMS value
(sync level at B/G; peak-white level at L); video modulation DSB; residual carrier: B/G = 10%, L = 3%; video signal in
accordance with CCIR line 17; measurements taken in Fig.3 unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
see note 1
MIN. TYP. MAX.
UNIT
VP
IP
supply voltage range (pin 20)
supply current
4.5
51
5
8.8
69
V
60
mA
Standard switch input (pin 8)
VIH
VIL
IIL
input voltage for negative modulation
see note 2
1.5
0
−
−
VP
V
input voltage for positive modulation
LOW level input current
0.8
V
V8 = 0 V
−
−300 −360
µA
B/G standard
Vision IF input (pins 1 and 2)
Vi
input signal sensitivity (RMS value)
maximum input signal (RMS value)
−1 dB video at output
−
50
90
−
µV
mV
dB
+1 dB video at output
70
−
150
0.7
∆Vi
IF amplitude difference between picture and within AGC range
sound carrier
1
GIF
B
IF gain control range
−3 dB IF bandwidth
input resistance
see Fig.4
64
70
73
−
dB
MHz
kΩ
pF
V
upper cut-off frequency 70
100
2.2
1.7
3.4
Ri
1.7
2.7
2.5
3.8
Ci
input capacitance
DC input voltage
1.2
V1, 2
3.0
see note 3
True synchronous video demodulator
fVCO
maximum oscillator frequency for carrier
regeneration
oscillator drift (free running) as a function of see note 4;
f = 2fPC
125
−
130
−
MHz
10−6
mV
∆fVCO
Vo ref
∆fPC
−
±1300
temperature
∆T = 0 to+70 °C
oscillator swing at pins 16 and 17
(RMS value)
tbn
120 tbn
vision carrier capture range (negative)
vision carrier capture range (positive)
acquisition time
1.5
1.5
−
2
2
−
−
MHz
MHz
ms
−
tacqu
Vi IF
see note 5; BL = 60 kHz
30
IF input signal sensitivity (RMS value, pins 1
and 2)
for PLL still locked
see note 6;
−
70
100
µV
maximum IF gain
for C/N = 10 dB
see note 7
see note 8
−
−
100 140
− ±4.5
µV
µA
Iloop
FPLL loop offset current at pin 6
November 1992
7
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX.
UNIT
sound carrier off
Composite video amplifier (pin 13)
V0 vid
V13
output signal (peak-to-peak value)
see Fig.7
B/G and L
B/G
0.9
1.4
2.5
1.0
1.5
2.6
1.1
1.6
2.7
V
V
V
V
V
sync level
zero carrier level
L
1.37 1.47 1.57
upper video clipping level
VP − VP −
−
1.1
1.0
lower video clipping level
−
0.3
0.4
V
V0 FM
IF intercarrier level (RMS value)
sound carrier on;
see note 9
tbn
140 tbn
mV
R13
Iint13
I13
output resistance
−
−
10
−
Ω
internal bias current for emitter follower
maximum output sink current
maximum output source current
−3 dB video bandwidth
DC
1.8
1.4
2.0
7
2.5
tbn
tbn
10
40
mA
mA
mA
MHz
dB
DC and AC
−
−
B
C
13 < 50 pF; RL > 1 kΩ
see note 10;
13 < 50 pF; RL > 1 kΩ
see Fig.9
−
αH
suppression of video signal harmonics
35
−
C
RR
ripple rejection on pin 13
32
35
−
dB
CVBS buffer amplifier and noise clipper (pins 7 and 14)
R14
input resistance
input capacitance
DC voltage at input
voltage gain
2.6
1.4
1.5
6
3.3
2
4.0
3.0
2.1
7.5
2.3
kΩ
pF
V
C14
V14
pin 14 not connected
see note 11
1.8
7
Gv
dB
V
Vo CVBS
CVBS output signal on pin 7 (peak-to-peak sound carrier off;
1.7
2.0
value)
see Fig.3
CVBS output level
upper video clipping
lower video clipping
sync level
tbn
4.0
1.0
−
V
−
tbn
V
1.25 1.35 1.45
V
R7
Iint7
I7
output resistance
−
−
10
−
Ω
internal bias current for emitter follower
maximum output sink current
maximum output source current
−3 dB video bandwidth
DC
1.8
1.4
2.4
8
2.5
tbn
tbn
11
mA
mA
mA
MHz
DC and AC
−
−
B
C7 < 20 pF; RL > 1 kΩ
−
November 1992
8
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX.
UNIT
Measurements from IF input to CVBS output (pin 7) 330 Ω between pins 13 and 14, sound carrier off
Vo CVBS
CVBS output signal on pin 7 (peak-to-peak
value)
1.7
2.0
2.3
V
∆Vo
deviation of CVBS output signal at B/G
50 dB gain control
30 dB gain control
−
−
−
−
−
−
0.5
0.1
1
dB
dB
%
black level tilt
B/G standard;
see note 12
vertical tilt for worst case in L standard
vision carrier modulated
by test line (VITS) only;
see note 12
−
−
1.5
%
∆G
differential gain
−
2
5
%
∆ϕ
differential phase
−
1
3
deg
MHz
dB
B
−3 dB video bandwidth
signal-to-noise ratio; weighted
intermodulation at ‘blue’
intermodulation at ‘yellow’
intermodulation at ‘blue’
intermodulation at ‘yellow’
residual vision carrier (RMS value)
CL < 20 pF; RL > 1 kΩ
6
8
−
S/N(W)
α1.1
see Fig.5 and note 13
56
56
58
56
57
−
59
62
64
62
63
1
−
see Fig.6 and note 14;
f = 1.1 MHz
−
dB
−
dB
α3.3
see Fig.6 and note 14;
f = 3.3 MHz
−
dB
−
dB
αC
fundamental wave
harmonics
10
10
−
mV
mV
dB
−
1
αH
suppression of video signal harmonics
ripple rejection on pin 7
see note 10
see Fig.9
35
25
40
28
RR
−
dB
AGC detector (pin 19)
tresp response to an increasing amplitude step of B/G and L
50 dB in input signal
−
1
10
ms
response to a decreasing amplitude step of B/G
−
−
50
100
ms
ms
mA
µA
50 dB in input signal
L
100 150
I19
charging current
B/G and L; see note 12 0.85 1.1
1.35
3.5
additional charging current
L in case of missing
VITS pulses and no
white video content
2.0
2.7
discharging current
AGC voltage
B/G
17
22
27
µA
µA
µA
normal mode L
fast mode L
see Fig.4
maximum gain
minimum gain
see Fig.7
L
0.24 0.33 0.42
31
44
57
V19
0
tbn
tbn
−
V
V
−
VP − 0.7
V13
threshold voltage level
for additional charging current
for fast L mode
1.9
1.6
1.95 2.0
1.65 1.7
V
V
L
November 1992
9
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX.
UNIT
Tuner AGC (pin 12)
Vi
IF input signal for minimum starting point of input at pins 1 and 2;
tuner take over (RMS value) RTOP = 22 kΩ
IF input signal for maximum starting point of input at pins 1 and 2;
−
−
−
5
mV
50
−
mV
tuner take over (RMS value)
R
TOP = 0 Ω
from external source
12 = 1.7 mA
V12
allowable voltage
−
−
−
−
−
1
13.2
0.2
3
V
saturation voltage
I
V
∆V12
variation of take over point by temperature
sink current
∆T = 0 to +50 °C
see Fig.4
dB
I12
no tuner gain reduction
−
0.1
2.0
0.3
2.6
µA
maximum tuner gain
reduction
1.7
mA
∆GIF
IF slip by automatic gain control
tuner gain current from
20 to 80%
−
6
8
dB
see Fig.8 and note 15
see note 16
AFC circuit (pin 15)
S
control steepness ∆I15/∆f
0.6
0.72 0.84
±1300
µA/kHz
10−6
∆fIF
frequency variation by temperature
∆T = 0 to +70 °C;
−
−
see note 4
V15
output voltage upper limit
see Fig.8
VP − VP −
−
V
0.5
0.3
output voltage lower limit
output current source
output current sink
−
0.3
0.5
V
I15
160
160
−
200 240
200 240
µA
µA
µA
∆I15
residual video modulation current
(peak-to-peak value)
B/G and L
20
30
see note 17
Sound mute switch (pin 5)
VIL
input voltage for MUTE-ON
0
−
−
0.8
VP
V
VIH
IIL
input voltage for MUTE-OFF
LOW level input current
1.5
−
V
V5 = 0 V
−300 −360
80
µA
dB
mV
αmute
∆V5
audio attenuation
V5 = 0 V
70
−
−
DC offset voltage at switching (plop)
switching to MUTE-ON
FM 5.5 MHz
100 500
FM sound limiter amplifier (pin 11)
Vi FM
input signal (RMS value, pin 11)
for S/N = 40 dB
CCIR468-4
see Fig.11
−
200 300
µV
for AM suppression αAM = 40 dB
maximum input signal handling (RMS value)
input resistance
AM: f = 1 kHz; m = 0.3
−
1
−
−
mV
mV
Ω
200
480
3.5
−
R11
B
600 720
−3 dB IF frequency response of sound IF
lower and upper
cut-off frequency
−
10
MHz
V11
DC voltage
2.3
2.6
2.9
V
November 1992
10
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
SYMBOL
PARAMETER
CONDITIONS
see note 18
MIN. TYP. MAX.
UNIT
FM−PLL sound demodulator and AF output (pin 9)
fi FM
catching range of PLL
holding range of PLL
acquisition time
4
−
−
−
−
7
MHz
3.5
−
8
MHz
µs
tacqu
4
∆fAF
frequency deviation
THD < 1.5%;
−
±50
kHz
see note 19
V10
DC voltage at decoupling capacitor
AF output signal (RMS value, pin 9)
voltage dependent on
VCO frequency;
see note 20
1.2
−
2.2
V
Vo AF
∆fAF = ±27 kHz;
280
350 420
mV
see Fig.11
maximum output signal handling
temperature drift of AF output signal
output resistance
THD < 1.5%
0.8
−
−
−
V
∆Vo
R9
∆T = 0 to+70 °C
0.2
100
−
0.5
−
dB
Ω
−
RL
load resistance (pin 9)
2.2
1.6
95
−
−
kΩ
V
V9
DC voltage
2.0
120
0.1
55
−
2.4
−
B
−3 dB audio frequency bandwidth
total harmonic distortion
signal-to-noise ratio, weighted
kHz
%
THD
S/N (W)
VSC
0.5
−
CCIR468-4; see Fig.11
50
−
dB
mV
residual sound carrier and harmonics (RMS
value)
75
αAM
AM suppression
see Fig.10;
AM: f = 1 kHz; m = 0.3
46
26
50
30
−
−
dB
dB
RR
ripple rejection on pin 9
see Fig.9
Measurements from IF input to audio output (pin 9)
560 Ω between pins 13 and 11
CCIR468-4; with offset alignment on pin 4
S/N (W)
weighted signal-to-noise ratio referred to
54% FM modulation
6 kHz sinusoidal waveform
black level
black-to-white
sync only
39
39
39
46
48
46
−
−
−
dB
dB
dB
white picture
November 1992
11
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
Notes to the characteristics
1. Typical values of video and sound parameters are decreased at VP = 4.5 V.
2. The input voltage for negative modulation has to be V8 > 1.5 V, or pin 8 open-circuit.
3. Loop bandwidth BL = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2 calculated with grey level and
FPLL input signal level).
Resonance circuit of VCO: Qo > 50; Cext = 8.2 pF; Cint ≈ 8.5 pF (loop voltage about 2.7 V).
4. The oscillator drift is related to the picture carrier frequency (at external temperature-compensated LC-circuit).
5. Vi IF = 10 mV (RMS value); ∆f = 1 MHz (VCO frequency offset related to picture carrier frequency); white picture
video modulation.
6. Vi IF for 0.9 V CVBS (peak-to-peak value) at composite video output pin 13; PLL is still locked.
7. Transformer at IF input (Fig.3). The C/N ratio at IF input for ‘lock-in’ is defined as the vision IF input signal (sync level,
RMS value) in relation to a superimposed, 5 MHz band-limited white noise signal (RMS value); video modulation:
white picture.
8. Offset current measured between pin 6 and half of supply voltage (V = 2.5 V) under the following conditions: no input
signal at IF input (pins 1 and 2) and IF-amplifier gain at minimum (V19 = VP), pin 4 (phase adjust) open-circuit.
9. The intercarrier output signal is superimposed to the video signal at pin 13 and can be calculated by the following
formula:
V13 interc. (p – p)
------------------------------------------
1V (p – p)
ViSC
20log
=
dB + 6.9 dB ± 2 dB
-----------
ViPC
with
ViSC
dB = sound to picture carrier ratio at IF input (pins 1 and 2) in dB
-----------
ViPC
and
±2 dB = tolerance of intercarrier output amplitude Vo FM.
10. Measurements taken with SAW filter G1956; modulation: VSB, fvideo > 0.5 MHz, loop bandwidth BL = 60 kHz.
11. The 7 dB buffer gain accounts for 1 dB loss in the sound trap. Buffer output signal is typical 2 V (p-p). If no sound
trap is applied a 330 Ω resistor must be connected from output to input (from pin 13 to pin 14).
12. The leakage current of the AGC capacitor has to be < 1 µA in B/G mode (< 30 nA in L mode) to avoid larger tilt.
13. S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value, pin 7). B = 5 MHz weighted
in accordance with CCIR-567 at a source impedance of 50 Ω.
14. α1.1 = 20 log (Vo at 4.4 MHz / Vo at 1.1 MHz) + 3.6 dB; α1.1 value at 1.1 MHz related to black/white signal
α3.3 = 20 log (Vo at 4.4 MHz / Vo at 3.3 MHz); α3.3 value at 3.3 MHz related to colour carrier.
15. To match the AFC output signal to different tuning systems a current source output is provided (Fig.8).
16. Depending on the radio ∆C/Co of the LC resonance circuit of VCO
(Qo > 50; Co = Cint+Cext; Cext = 8.2 pF; Cint ≈ 8.5 pF).
17. No mute state is also valid for pin not connected. For switching on the L-standard no external load is allowed at pin
5 except capacitor CBL
.
18. A 5.5 MHz signal for second IF with 10 mV (RMS value) input level, fmod = 1 kHz and frequency deviation with 54%
FM modulation of audio reference is fed directly to pin 11. Audio measurements are taken at 50 µs de-emphasis.
19. To allow higher frequency deviation, the resistor Rx on pin 10 (see Fig.12) has to be increased to a value which does
not exceed the AF output signal of nominally 0.35 V for THD = 0.1% (Rx = 4.7 kΩ provides −6 dB amplification).
20. The leakage current of the 2.2 µF capacitor is < 100 nA.
November 1992
12
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
Fig.3 Test circuit.
November 1992
13
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
MED332
70
60
G
IF
I
12
(dB)
50
(mA)
0
40
0.2
(2) (3)
(4)
(1)
30
20
10
0
0.6
1.0
1.4
1.8
2.0
−10
0
1
2
3
4
5
V
(V)
19
Fig.4 IF AGC (dashed) and tuner AGC as a function of take over point adjustment.
MED333
80
−3.2 dB
handbook, halfpage
handbook, halfpage
S/N
(dB)
−10 dB
−13.2 dB
−24 dB
−13.2 dB
−24 dB
60
40
20
SC CC
PC
SC CC
YELLOW
PC
BLUE
MED334
SC = sound carrier level
; with respect to TOP sync level.
CC = chrominance carrier level ; with respect to TOP sync level.
0
−60
−40
−20
0
20
PC = picture carrier level
; with respect to TOP sync level.
V
(dB)
i IF(rms)
0.06
0.6
6
60
V
600
(mV)
Sound shelf attenuation: 17 dB.
10
i IF(rms)
Fig.5 Typical signal-to-noise ratio as a function of
IF input signal.
Fig.6 Input conditions for intermodulation
measurements.
November 1992
14
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
Fig.7 Video signal levels on output pin 13.
Fig.8 Measurement conditions and typical AFC characteristic.
Fig.9 Ripple rejection condition.
15
November 1992
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
MED338
0
α
AM
(dB)
−20
−40
−60
−80
−100
−1
2
3
10
1
10
10
10
V
(mV)
i IC
Fig.10 Typical AM suppression of FM sound demodulator.
MED339
370
60
V
(1)
(2)
o AF
S/N (W)
(dB)
(mV RMS)
360
50
40
30
350
340
330
20
3
−1
2
10
1
10
10
10
V
(mV)
i FM
Fig.11 Typical AF output signal and signal-to-noise ratio.
November 1992
16
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
(1) depends on tuner
Fig.12 Application circuit.
November 1992
17
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
(1) depends on TOP
Fig.13 Front end level diagram.
November 1992
18
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
November 1992
19
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
PACKAGE OUTLINE
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
2.0
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-05-24
SOT146-1
SC603
November 1992
20
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT163-1
075E04
MS-013AC
November 1992
21
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
Several techniques exist for reflowing; for example,
SOLDERING
Introduction
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
November 1992
22
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL demodulator and
FM-PLL detector
TDA9802
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
November 1992
23
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