TDA9381PS/N2 [NXP]
TV signal processor-Teletext decoder with embedded m-Controller;
| 型号： | TDA9381PS/N2 |
| 厂家： | 
NXP |
| 描述： | TV signal processor-Teletext decoder with embedded m-Controller 电视 |
| 文件： | 总118页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DEVICE SPECIFICATION
TDA935X/6X/8X PS/N2 series
TV signal processor-Teletext
decoder with embedded µ-Controller
Tentative Device Specification
2001 Jan 18
Version: 2.8
Previous date: 2000 Nov 29
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder
with embedded µ-Controller
TDA935X/6X/8X PS/N2 series
GENERAL DESCRIPTION
The various versions of theTDA935X/6X/8X PS/N2 series
combine the functions of a TV signal processor together
with a µ-Controller and US Closed Caption decoder. Most
versions have a Teletext decoder on board. The Teletext
decoder has an internal RAM memory for 1or 10 page text.
The ICs are intended to be used in economy television
receivers with 90° and 110° picture tubes.
The ICs have supply voltages of 8 V and 3.3 V and they
are mounted in S-DIP envelope with 64 pins.
The features are given in the following feature list. The
differences between the various ICs are given in the table
on page 4.
FEATURES
• RGB control circuit with ‘Continuous Cathode
Calibration’, white point and black level offset
adjustment so that the colour temperature of the dark
and the light parts of the screen can be chosen
independently.
TV-signal processor
• Multi-standard vision IF circuit with alignment-free PLL
demodulator
• Internal (switchable) time-constant for the IF-AGC circuit • Linear RGB or YUV input with fast blanking for external
RGB/YUV sources. The Text/OSD signals are internally
supplied from the µ-Controller/Teletext decoder
• A choice can be made between versions with mono
intercarrier sound FM demodulator and versions with
QSS IF amplifier.
• Contrast reduction possibility during mixed-mode of
OSD and Text signals
• The mono intercarrier sound versions have a selective
FM-PLL demodulator which can be switched to the
different FM sound frequencies (4.5/5.5/6.0/6.5 MHz).
The quality of this system is such that the external
band-pass filters can be omitted.
• Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
• Vertical count-down circuit
• Vertical driver optimized for DC-coupled vertical output
stages
• Source selection between ‘internal’ CVBS and external
CVBS or Y/C signals
• Horizontal and vertical geometry processing
• Integrated chrominance trap circuit
• Horizontal and vertical zoom function for 16 : 9
applications
• Integrated luminance delay line with adjustable delay
time
• Horizontal parallelogram and bow correction for large
screen picture tubes
• Picture improvement features with peaking (with
variable centre frequency and positive/negative
overshoot ratio) and black stretching
• Low-power start-up of the horizontal drive circuit
• Integrated chroma band-pass filter with switchable
centre frequency
• Only one reference (12 MHz) crystal required for the
µ-Controller, Teletext- and the colour decoder
• PAL/NTSC or multi-standard colour decoder with
automatic search system
• Internal base-band delay line
2001 Jan 18
2
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
µ-Controller
Display
• 80C51 µ-controller core standard instruction set and
• Teletext and Enhanced OSD modes
timing
• Features of level 1.5 WST and US Close Caption
• Serial and Parallel Display Attributes
• 1 µs machine cycle
• 32 - 128Kx8-bit late programmed ROM
• Single/Double/Quadruple Width and Height for
• 3 - 12Kx8-bit Auxiliary RAM (shared with Display and
characters
Acquisition)
• Scrolling of display region
• Interrupt controller for individual enable/disable with two
level priority
• Variable flash rate controlled by software
• Enhanced display features including overlining,
underlining and italics
• Two 16-bit Timer/Counter registers
• One 16 bit Timer with 8-bit Pre-scaler
• WatchDog timer
• Soft colours using CLUT with 4096 colour palette
• Globally selectable scan lines per row (9/10/13/16) and
• Auxiliary RAM page pointer
• 16-bit Data pointer
character matrix [12x10, 12x13, 12x16 (VxH)]
• Fringing (Shadow) selectable from N-S-E-W direction
• Fringe colour selectable
• Stand-by, Idle and Power Down (PD) mode
• 14 bits PWM for Voltage Synthesis Tuning
• 8-bit A/D converter
• Meshing of defined area
• Contrast reduction of defined area
• Cursor
• 4 pins which can be programmed as general I/O pin,
ADC input or PWM (6-bit) output
• Special Graphics Characters with two planes, allowing
four colours per character
Data Capture
• 32 software redefinable On-Screen display characters
• Text memory for 0, 1 or 10 pages
• 4 WST Character sets (G0/G2) in single device (e.g.
• In the 10 page versions inventory of transmitted Teletext
pages stored in the Transmitted Page Table (TPT) and
Subtitle Page Table (SPT)
Latin, Cyrillic, Greek, Arabic)
• G1 Mosaic graphics, Limited G3 Line drawing
characters
• Data Capture for US Closed Caption
• WST Character sets and Closed Caption Character set
• Data Capture for 525/625 line WST, VPS (PDC system
in single device
A) and Wide Screen Signalling (WSS) bit decoding
• Automatic selection between 525 WST/625 WST
• Automatic selection between 625 WST/VPS on line 16
of VBI
• Real-time capture and decoding for WST Teletext in
Hardware, to enable optimized µ-processor throughput
• Automatic detection of FASTEXT transmission
• Real-time packet 26 engine in Hardware for processing
accented, G2 and G3 characters
• Signal quality detector for video and WST/VPS data
types
• Comprehensive teletext language coverage
• Full Field and Vertical Blanking Interval (VBI) data
capture of WST data
2001 Jan 18
3
FUNCTIONAL DIFFERENCE BETWEEN THE VARIOUS IC VERSIONS
IC VERSION (TDA)
TV range
9350935193529353936093619362936393649365936693679380938193829383938493859386938793889389
90° 90° 90° 110° 90° 90° 110° 110° 110° 110° 90° 90° 90° 90° 90° 110° 110° 110° 110° 90° 110° 110°
Mono intercarrier multi-standard
sound demodulator (4.5 - 6.5 MHz)
with switchable centre frequency
√
√
√
√
√
√
√
√
√
√
√
√
√
Audio switch
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Automatic Volume Levelling
√
√
√
√
√
√
√
√
Automatic Volume Levelling or
subcarrier output (for comb filter
applications)
√
√
√
√
√
√
√
√
QSS sound IF amplifier with
separate input and AGC circuit
√
√
√
√
AM sound demodulator without
extra reference circuit
PAL decoder
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
SECAM decoder
NTSC decoder
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Horizontal geometry (E-W)
Horizontal and Vertical Zoom
ROM size
32- 32- 32- 32- 64- 64- 64- 64- 64- 64- 64- 64- 16- 16- 16- 16- 16- 16- 16- 16- 16- 16-
64 k 64 k 64 k 64 k 128k 128k 128k 128k 128k 128k 128k 128k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 64 k 64 k
User RAM size
Teletext
1 k 1 k 1 k 1 k 2 k 2 k 2 k 2 k 2 k 2 k 2 k 2 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k
1
1
1
1
10 10 10 10 10 10 10 10
pagepagepagepagepagepagepagepagepagepagepagepage
Closed captioning
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
QUICK REFERENCE DATA
SYMBOL
Supply
PARAMETER
MIN.
TYP.
MAX.
UNIT
VP
IP
supply voltages
supply current
−
−
8.0/3.3
tbf
−
−
V
mA
Input voltages
ViVIFrms)
video IF amplifier sensitivity (RMS value)
QSS sound IF amplifier sensitivity (RMS value)
external audio input (RMS value)
−
−
−
−
−
75
−
−
−
−
−
µV
µV
mV
V
ViSIF(rms)
60
ViAUDIO(rms)
ViCVBS(p-p)
500
1.0
0.3
external CVBS/Y input (peak-to-peak value)
ViCHROMA(p-p) external chroma input voltage (burst amplitude)
(peak-to-peak value)
V
ViRGB(p-p)
ViYIN(p-p)
ViUVIN(p-p)
RGB inputs (peak-to-peak value)
−
−
−
0.7
1.4
−
−
V
V
V
luminance input signal (peak-to-peak value)
U/V input signal (peak-to-peak value)
1.33/1.05 −
Output signals
Vo(IFVO)(p-p)
demodulated CVBS output (peak-to-peak value)
−
−
−
2.5
−
−
−
V
Vo(QSSO)(rms) sound IF intercarrier output in QSS versions (RMS value)
100
500
mV
mV
Vo(AMOUT)(rms) demodulated AM sound output in QSS versions (RMS
value)
Io(AGCOUT)
VoRGB(p-p)
IoHOUT
tuner AGC output current range
0
−
5
−
−
−
−
mA
V
RGB output signal amplitudes (peak-to-peak value)
horizontal output current
−
2.0
−
10
1
mA
mA
mA
IoVERT
vertical output current (peak-to-peak value)
EW drive output current
−
IoEWD
1.2
−
2001 Jan 18
5
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
BLOCK DIAGRAM
1 + 6 2 - 6 4
I / O P O R T S ( 4 x )
5 - 8
A D C I N ( 4 x )
V S T O U T
1 0 / 1 1
L E D O U T ( 2 x )
V P E
R E S E T
U A D O U T
A U D E X T
S N D I F
2001 Jan 18
6
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
1 + 6 2 - 6 4
I / O P O R T S ( 4 x )
5 - 8
A D C I N ( 4 x )
V S T O U T
1 0 / 1 1
L E D O U T ( 2 x )
V P E
R E S E T
A M O U T
Q S S O U T / A M O U T
S I F I N
( 2 0 )
A U D E X T
2001 Jan 18
7
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
PINNING
SYMBOL
P1.3/T1
PIN
DESCRIPTION
1
port 1.3 or Counter/Timer 1 input
port 1.6 or I2C-bus clock line
port 1.7 or I2C-bus data line
port 2.0 or Tuning PWM output
port 3.0 or ADC0 input
P1.6/SCL
P1.7/SDA
P2.0/TPWM
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
VSSC/P
2
3
4
5
6
port 3.1 or ADC1 input
7
port 3.2 or ADC2 input
8
port 3.3 or ADC3 input
9
digital ground for µ-Controller core and periphery
port 0.5 (8 mA current sinking capability for direct drive of LEDs)
port 0.6 (8 mA current sinking capability for direct drive of LEDs)
analog ground of Teletext decoder and digital ground of TV-processor
SECAM PLL decoupling
2nd supply voltage TV-processor (+8V)
decoupling digital supply of TV-processor
phase-2 filter
P0.5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P0.6
VSSA
SECPLL
VP2
DECDIG
PH2LF
PH1LF
phase-1 filter
GND3
ground 3 for TV-processor
DECBG
AVL/EWD (1)
bandgap decoupling
Automatic Volume Levelling /East-West drive output
vertical drive B output
VDRB
VDRA
vertical drive A output
IFIN1
IF input 1
IFIN2
IF input 2
IREF
reference current input
VSC
vertical sawtooth capacitor
TUNERAGC
AUDEEM/SIFIN1(1)
DECSDEM/SIFIN2(1)
GND2
SNDPLL/SIFAGC(1)
AVL/SNDIF/REF0/
AMOUT(1)
HOUT
tuner AGC output
audio deemphasis or SIF input 1
decoupling sound demodulator or SIF input 2
ground 2 for TV processor
narrow band PLL filter /AGC sound IF
Automatic Volume Levelling / sound IF input / subcarrier reference output /AM output
(non controlled)
33
34
35
horizontal output
FBISO
flyback input/sandcastle output
AUDEXT/
QSSO/AMOUT(1)
EHTO
external audio input /QSS intercarrier out /AM audio output (non controlled)
36
37
38
39
40
41
42
43
44
EHT/overvoltage protection input
IF-PLL loop filter
PLLIF
IFVO/SVO
VP1
IF video output / selected CVBS output
main supply voltage TV-processor (+8 V)
internal CVBS input
CVBSINT
GND1
ground 1 for TV-processor
CVBS/Y
external CVBS/Y input
CHROMA
AUDOUT /AMOUT(1)
chrominance input (SVHS)
audio output /AM audio output (volume controlled)
2001 Jan 18
8
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
SYMBOL
INSSW2
PIN
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DESCRIPTION
2nd RGB / YUV insertion input
2nd R input / V (R-Y) input
2nd G input / Y input
R2/VIN
G2/YIN
B2/UIN
BCLIN
BLKIN
RO
2nd B input / U (B-Y) input
beam current limiter input / (V-guard input, note 2)
black current input / (V-guard input, note 2)
Red output
GO
Green output
BO
Blue output
VDDA
analog supply of Teletext decoder and digital supply of TV-processor (3.3 V)
OTP Programming Voltage
digital supply to core (3.3 V)
oscillator ground supply
VPE
VDDC
OSCGND
XTALIN
XTALOUT
RESET
VDDP
crystal oscillator input
crystal oscillator output
reset
digital supply to periphery (+3.3 V)
port 1.0 or external interrupt 1 input
port 1.1 or Counter/Timer 0 input
port 1.2 or external interrupt 0 input
P1.0/INT1
P1.1/T0
P1.2/INT0
Note
1. The function of pin 20, 28, 29, 31, 32, 35 and 44 is dependent on the IC version (mono intercarrier FM demodulator
/ QSS IF amplifier and East-West output or not) and on some software control bits. The valid combinations are given
in table 1.
2. The vertical guard function can be controlled via pin 49 or pin 50. The selction is made by means of the IVG bit in
subaddress 2BH.
Table 1
Pin functions for various versions
FM-PLL version
IC version
QSS version
East-West Y/N
CMB1/CMB0 bits
AM bit
N
Y
N
Y
00
01/10/11
00
01/10/11
00
01/10/11
00
01/10/11
−
−
−
−
−
0
1
−
0
1
Pin 20
AVL
EWD
AVL
EWD
Pin 28
AUDEEM
SIFIN1
SIFIN2
Pin 29
DECSDEM
Pin 31
SNDPLL
SIFAGC
AMOUT
Pin 32
SNDIF(1) REFO(2) AVL/SNDIF(1) REFO(2) AMOUT
REFO(2)
REFO(2)
Pin 35
AUDEXT
AUDOUT
AUDEXT QSSO AMOUT AUDEXT QSSO AMOUT
controlled AM or audio out
Pin 44
Note
1. When additional (external) selectivity is required for FM-PLL system pin 32 can be used as sound IF input. This
function is selected by means of SIF bit in subaddress 28H.
2. The reference output signal is only available for the CMB1/CMB0 setting of 0/1. For the other settings this pin is a
switch output (see also table 67).
2001 Jan 18
9
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
handbook, halfpage
P1.3/T1
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.2/INT0
P1.1/T0
P1.0/INT1
VDDP
2
P1.6/SCL
P1.7/SDA
P2.0/TPMW
3
4
5
P3.0/ADC0
P3.1/ADC1
RESET
6
XTALOUT
7
P3.2/ADC2
P3.3/ADC3
XTALIN
OSCGND
8
VSSC/P
P0.5
9
VDDC
VPE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P0.6
VDDA
VSSA
BO
GO
SECPLL
RO
VP2
DECDIG
BLKIN
BCLIN
B2/UIN
PH2LF
PH1LF
GND3
G2/YIN
R2/VIN
INSSW2
DECBG
AVL/EWD
AUDOUT/AMOUT
CHROMA
VDRB
VDRA
CVBS/Y
IFIN1
IFIN2
IREF
GND1
CVBSINT
VP1
VSC
IFVO/SVO
TUNERAGC
PLLIF
EHTO
AUDEEM/SIFIN1
DECSDEM/SIFIN2
AUDEXT/QSSO/
AMOUT
GND2
SNDPLL/SIFAGC
FBISO
HOUT
AVL/SNDIF/
REFO/AMOUT
MXXxxx
Fig. 3 Pin configuration (SDIP 64)
10
2001 Jan 18
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
FUNCTIONAL DESCRIPTION OF THE 80C51
the 32K banks is common and is always addressable. The
other three banks (Bank0, Bank1, Bank2) can be
accessed by selecting the right bank via the SFR ROMBK
bits 1/0.
The functionality of the micro-controller used on this
device is described here with reference to the industry
standard 80C51 micro-controller. A full description of its
functionality can be found in the 80C51 based 8-bit
micro-controllers - Philips Semiconductors (ref. IC20).
FFFFH
FFFFH
FFFFH
Features of the 80c51
• 80C51 micro-controller core standard instruction set and
Bank1
32K
Bank0
32K
Bank2
32K
timing.
• 1µs machine cycle.
8000H
8000H
8000H
• Maximum 128K x 8-bit Program ROM.
• Maximum of 12K x 8-bit Auxiliary RAM.
• 2K (OSD only version) Auxiliary RAM, maximum
of 1.25K required for Display
7FFFH
• 3K (1 page teletext version) Auxiliary RAM,
maximum of 2K required for Display
Common
32K
• 12K (10 page teletext version) Auxiliary RAM,
maximum of 10K required for Display
0000H
• 8-Level Interrupt Controller for individual enable/disable
Fig.4 ROM Bank Switching memory map
with two level priority.
• Two 16-bit Timer/Counters.
• Additional 16-bit Timer with 8-bit Pre-scaler.
• WatchDog Timer.
RAM Organisation
The Internal Data RAM is organised into two areas, Data
Memory and Special Function Registers (SFRs) as shown
in Fig.5.
• Auxiliary RAM Page Pointer.
• 16-bit Data pointer
• Idle, Stand-by and Power-Down modes.
• 13 General I/O.
FFH
Accessible
by Indirect
Addressing
only
Accessible
by Direct
Addressing
only
Upper
128
• Four 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analogue signals.
• One 14-bit PWM for Voltage Synthesis tuner control.
• 8-bit ADC with 4 multiplexed inputs.
80H
7FH
Accessible
by Direct
and Indirect
Addressing
Lower
128
• 2 high current outputs for directly driving LED’s etc.
• I2C Byte Level bus interface.
00H
Memory Organisation
Data Memory
Special Function Registers
The device has the capability of a maximum of 128K Bytes
of PROGRAM ROM and 12K Bytes of DATA RAM. The
OSD (& Closed Caption) only version has a 2K RAM and
a maximum of 64K ROM, the 1 page teletext version has
a 3K RAM and also a maximum of 64K ROM whilst the 10
page teletext version has a 12K RAM and a maximum of
128K ROM.
Fig.5 Internal Data Memory
DATA MEMORY
The Data memory is 256 x 8-bits and occupies the address
range 00 to FF Hex when using Indirect addressing and 00
to 7F Hex when using direct addressing. The SFRs occupy
the address range 80 Hex to FF Hex and are accessible
using Direct addressing only. The lower 128 Bytes of Data
memory are mapped as shown in Fig.6. The lowest 32
ROM Organisation
The 64K device has a continuous address space from 0 to
64K. The 128K is arranged in four banks of 32K. One of
2001 Jan 18
11
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable
memory space. The upper 128 bytes are not allocated for any special area or functions.
7FH
2FH
Bank Select
Bits in PSW
20H
1FH
11 = BANK3
18H
17H
10 = BANK2
10H
0FH
01 = BANK1
08H
07H
00 = BANK0
00H
Fig.6 Lower 128 Bytes of Internal RAM
SFR MEMORY
The Special Function Register (SFR) space is used for port latches, counters/timers, peripheral control, data capture and
display. These registers can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both
bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR
map in address order is shown in Table 2.
ADD
80H
81H
82H
83H
84H
85H
87H
88H
89H
8AH
8BH
8CH
8DH
90H
91H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Names
P0
BIT7
Reserved
SP<7>
DPL<7>
DPH<7>
-
BIT6
P0<6>
SP<6>
DPL<6>
DPH<6>
-
BIT5
P0<5>
SP<5>
DPL<5>
DPH<5>
-
BIT4
Reserved
SP<4>
DPL<4>
DPH<4>
-
BIT3
Reserved
SP<3>
DPL<3>
DPH<3>
-
BIT2
Reserved
SP<2>
DPL<2>
DPH<2>
-
BIT1
Reserved
SP<1>
DPL<1>
DPH<1>
-
BIT0
Reserved
SP<0>
DPL<0>
DPH<0>
ET2
SP
DPL
DPH
IEN1
IP1
-
-
-
-
-
-
-
PT2
PCON
TCON
TMOD
TL0
0
ARD
RFI
WLE
GF1
GF0
PD
IDL
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
GATE
TL0<7>
TL1<7>
TH0<7>
TH1<7>
P1<7>
TP2L<7>
C/T
M1
M0
GATE
TL0<3>
TL1<3>
TH0<3>
TH1<3>
P1<3>
TP2L<3>
C/T
M1
M0
TL0<6>
TL1<6>
TH0<6>
TH1<6>
P1<6>
TP2L<6>
TL0<5>
TL1<5>
TH0<5>
TH1<5>
Reserved
TP2L<5>
TL0<4>
TL1<4>
TH0<4>
TH1<4>
Reserved
TP2L<4>
TL0<2>
TL1<2>
TH0<2>
TH1<2>
P1<2>
TP2L<2>
TL0<1>
TL1<1>
TH0<1>
TH1<1>
P1<1>
TP2L<1>
TL0<0>
TL1<0>
TH0<0>
TH1<0>
P1<0>
TP2L<0>
TL1
TH0
TH1
P1
TP2L
Table 2 SFR Map
2001 Jan 18
12
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
ADD
92H
93H
94H
96H
97H
98H
9CH
9DH
9EH
9FH
A0H
A6H
A7H
A8H
B0H
B2H
B3H
B4H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Names
TP2H
BIT7
TP2H<15>
TP2PR<7>
-
BIT6
TP2H<14>
TP2PR<6>
-
BIT5
TP2H<13>
TP2PR<5>
-
BIT4
TP2H<12>
TP2PR<4>
-
BIT3
TP2H<11>
TP2PR<3>
-
BIT2
TP2H<10>
TP2PR<2>
-
BIT1
BIT0
TP2H<9>
TP2PR<1>
TP2CRL<1>
Reserved
TP2H<8>
TP2PR<0>
TP2CRL<0>
Reserved
TP2PR
TP2CRL
P0CFGA
P0CFGB
SADB
P0CFGA<6>
P0CFGA<5>
Reserved
Reserved
-
Reserved
Reserved
DC_COMP
TP2CL<4>
TP2CH<4>
Reserved
Reserved
-
Reserved
Reserved
SAD<3>
TP2CL<3>
TP2CH<3>
P1CFGA<3>
Reserved
Reserved
SAD<2>
TP2CL<2>
TP2CH<2>
P1CFGA<2>
P0CFGB<6>
-
P0CFGB<5>
-
Reserved
Reserved
SAD<1>
SAD<0>
TP2CL
TP2CH
P1CFGA
P1CFGB
P2
TP2CL<7>
TP2CH<7>
P1CFGA<7>
TP2CL<6>
TP2CH<6>
P1CFGA<6>
TP2CL<5>
TP2CH<5>
Reserved
Reserved
-
TP2CL<1>
TP2CH<1>
P1CFGA<1>
TP2CL<0>
TP2CH<0>
P1CFGA<0>
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1CFGB<7>
Reserved
Reserved
Reserved
EA
P1CFGB<6>
-
P1CFGB<3>
-
P1CFGB<2>
-
P1CFGB<1>
-
P1CFGB<0>
P2<0>
P2CFGA<6>
P2CFGA<5>
P2CFGA<4>
P2CFGA<3>
P2CFGA<2>
P2CFGA<1>
P2CFGA<0>
P2CFGA
P2CFGB
IE
P2CFGB<6>
EBUSY
P2CFGB<5>
ES2
P2CFGB<4>
ECC
P2CFGB<3>
P2CFGB<2>
P2CFGB<1>
ET0
P2CFGB<0>
EX0
ET1
EX1
P3
Reserved
NOT<3>
TEN
Reserved
NOT<2>
TC<2>
Reserved
NOT<1>
TC<1>
0
Reserved
NOT<0>
TC<0>
0
P3<3>
P3<2>
P3<1>
P3<0>
TXT18
TXT19
TXT20
0
0
0
0
BS<1>
TS<1>
BS<0>
TS<0>
DRCS
ENABLE
OSD
PLANES
OSD LANG
ENABLE
OSD
LAN<2>
OSD
LAN<1>
OSD
LAN<0>
B5H
R/W
TXT21
DISP
DISP
CHAR
CHAR
Reserved
CC ON
I2C PORT0
CC/TXT
LINE<1>
LINES<0>
SIZE<1>
SIZE<0>
B6H
B7H
B8H
B9H
R
TXT22
CCLIN
IP
GPF1<7>
GPF1<6>
0
GPF1<5>
0
GPF1<4>
CS<4>
PCC
GPF1<3>
CS<3>
PT1
GPF1<2>
CS<2>
PX1
GPF1<1>
CS<1>
PT0
GPF1<0>
CS<0>
PX0
R/W
R/W
R/W
0
0
0
PBUSY
PES2
TXT17
FORCE
ACQ<1>
FORCE
ACQ<0>
FORCE
DISP<1>
FORCE
DISP<0>
SCREEN
COL<2>
SCREEN
COL<1>
SCREEN
COL<0>
BAH
BBH
BCH
R
R
R
WSS1
WSS2
WSS3
0
0
0
0
0
0
WSS<3:0>
ERROR
WSS<3>
WSS<7>
WSS<2>
WSS<6>
WSS<10>
WSS<1>
WSS<5>
WSS<9>
WSS<0>
WSS<4>
WSS<8>
WSS<7:4>
ERROR
WSS<13:11>
ERROR
WSS<13>
WSS<12>
WSS<11>
WSS<10:8>
ERROR
P3CFGA<3>
P3CFGA<2>
P3CFGA<1>
P3CFGB<1>
VPS ON
P3CFGA<0>
P3CFGB<0>
INV ON
BEH
BFH
C0H
R/W
R/W
R/W
P3CFGA
P3CFGB
TXT0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P3CFGB<3>
P3CFGB<2>
X24 POSN
DISPLAY
X24
AUTO
FRAME
DISABLE
HEADER
ROLL
DISPLAY
STATUS
ROW ONLY
DISABLE
FRAME
Table 2 SFR Map
2001 Jan 18
13
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
ADD
R/W
Names
TXT1
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
C1H
R/W
EXT PKT
OFF
8 BIT
ACQ OFF
X26 OFF
FULL
FIELD
FIELD
POLARITY
H
V
POLARITY
POLARITY
C2H
C3H
C4H
R/W
W
TXT2
TXT3
TXT4
ACQ BANK
-
REQ<3>
-
REQ<2>
-
REQ<1>
PRD<4>
REQ<0>
PRD<3>
SC<2>
SC<1>
SC<0>
PRD<2>
PRD<1>
PRD<0>
R/W
OSD BANK
ENABLE
QUAD
WIDTH
ENABLE
EAST/WES
T
DISABLE
DOUBLE
HEIGHT
B MESH
ENABLE
C MESH
ENABLE
TRANS
ENABLE
SHADOW
ENABLE
C5H
C6H
C7H
R/W
R/W
R/W
TXT5
TXT6
TXT7
BKGND
OUT
BKGND IN
BKGND IN
CORB OUT
CORB OUT
REVEAL
CORB IN
CORB IN
TEXT OUT
TEXT OUT
TEXT IN
TEXT IN
PICTURE
ON OUT
PICTURE
ON IN
BKGND
OUT
PICTURE
ON OUT
PICTURE
ON IN
STATUS
ROW TOP
CURSOR
ON
BOTTOM/
TOP
DOUBLE
HEIGHT
BOX ON 24
BOX ON
1-23
BOX ON 0
C8H
C9H
R/W
R/W
TXT8
TXT9
(Reserved)
0
FLICKER
STOP ON
HUNT
A0
DISABLE
SPANISH
PKT 26
RECEIVED
WSS
RECEIVED
WSS ON
R<1>
CVBS1/
CVBS0
CURSOR
FREEZE
CLEAR
MEMORY
R<4>
R<3>
R<2>
R<0>
CAH
CBH
CCH
R/W
R/W
R
TXT10
TXT11
TXT12
0
0
C<5>
D<5>
C<4>
D<4>
C<3>
D<3>
C<2>
D<2>
C<1>
D<1>
1
C<0>
D<0>
D<7>
D<6>
525/625
SYNC
ROM
VER<4>
ROM
VER<3>
ROM
VER<2>
ROM
VER<1>
ROM
VER<0>
VIDEO
SIGNAL
QUALITY
CDH
CEH
R/W
R/W
TXT14
TXT15
0
0
0
0
0
0
DISPLAY
BANK
PAGE<3>
PAGE<2>
PAGE<1>
PAGE<0>
MICRO
BANK
BLOCK<3>
BLOCK<2>
BLOCK<1>
BLOCK<0>
D0H
D2H
D3H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
E0H
E4H
R/W
R/W
R/W
R/W
R/W
R
PSW
C
AC
F0
RS1
RS0
OV
-
P
TDACL
TDACH
PWM0
PWM1
CCDAT1
S1CON
S1STA
S1DAT
S1ADR
PWM3
ACC
TD<7>
TPWE
TD<6>
TD<5>
TD<4>
TD<3>
TD<2>
TD<1>
TD<0>
TD<8>
PW0V<0>
PW1V<0>
CCD1<0>
CR<0>
0
1
1
TD<13>
PW0V<5>
PW1V<5>
CCD1<5>
STA
TD<12>
PW0V<4>
PW1V<4>
CCD1<4>
STO
TD<11>
PW0V<3>
PW1V<3>
CCD1<3>
SI
TD<10>
PW0V<2>
PW1V<2>
CCD1<2>
AA
TD<9>
PW0E
PW0V<1>
PW1V<1>
CCD1<1>
CR<1>
PW1E
1
CCD1<7>
CR<2>
STAT<4>
DAT<7>
ADR<6>
PW3E
CCD1<6>
ENSI
STAT<3>
DAT<6>
ADR<5>
1
R/W
R
STAT<2>
DAT<5>
ADR<4>
PW3V<5>
ACC<5>
PW2V<5>
STAT<1>
DAT<4>
ADR<3>
PW3V<4>
ACC<4>
PW2V<4>
STAT<0>
DAT<3>
ADR<2>
PW3V<3>
ACC<3>
PW2V<3>
0
0
R/W
R/W
R/W
R/W
R/W
DAT<2>
ADR<1>
PW3V<2>
ACC<2>
PW2V<2>
DAT<1>
ADR<0>
PW3V<1>
ACC<1>
PW2V<1>
DAT<0>
GC
PW3V<0>
ACC<0>
PW2V<0>
ACC<7>
PW2E
ACC<6>
1
PWM2
Table 2 SFR Map
2001 Jan 18
14
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
ADD
E7H
E8H
F0H
F8H
R/W
R
Names
CCDAT2
SAD
BIT7
CCD2<7>
VHI
BIT6
CCD2<6>
CH<1>
B<6>
BIT5
CCD2<5>
CH<0>
B<5>
BIT4
CCD2<4>
ST
BIT3
CCD2<3>
SAD<7>
B<3>
BIT2
CCD2<2>
SAD<6>
B<2>
BIT1
CCD2<1>
SAD<5>
B<1>
BIT0
CCD2<0>
SAD<4>
B<0>
R/W
R/W
R/W
B
B<7>
B<4>
TXT13
VPS
PAGE
525
525 TEXT
625 TEXT
PKT 8/30
FASTEXT
0
RECEIVED
CLEARING
DISPLAY
FAH
FBH
FDH
FEH
FFH
R/W
R/W
R
XRAMP
ROMBK
TEST
XRAMP<7>
STANDBY
TEST<7>
XRAMP<6>
IIC_LUT<1>
XRAMP<5>
IIC_LUT<0>
XRAMP<4>
0
XRAMP<3>
0
XRAMP<2>
0
XRAMP<1>
ROMBK<1>
TEST<1>
XRAMP<0>
ROMBK<0>
TEST<0>
TEST<6>
WKEY<6>
WDV<6>
TEST<5>
WKEY<5>
WDV<5>
TEST<4>
WKEY<4>
WDV<4>
TEST<3>
WKEY<3>
WDV<3>
TEST<2>
WKEY<2>
WDV<2>
W
WDTKEY
WDT
WKEY<7>
WDV<7>
WKEY<1>
WDV<1>
WKEY<0>
WDV<0>
R/W
Table 2 SFR Map
A description of each of the SFR bits is shown in Table 3, The SFRs are in alphabetical order.
Names
ACC
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
00H
E0H
ACC<7>
ACC<6>
ACC<5>
ACC<4>
ACC<3>
ACC<2>
ACC<1>
ACC<0>
ACC<7:0>
Accumulator value.
F0H B<7>
B Register value.
D7H CCD1<7>
B
B<6>
B<5>
CCD1<5>
CCD2<5>
0
B<4>
B<3>
B<2>
CCD1<2>
CCD2<2>
CS<2>
B<1>
CCD1<1>
CCD2<1>
CS<1>
B<0>
00H
00H
00H
15H
00H
00H
00H
B<7:0>
CCDAT1
CCD1<7:0>
CCDAT2
CCD2<7:0>
CCLIN
CS<4:0>
CCD1<6>
CCD1<4>
CCD2<4>
CS<4>
CCD1<3>
CCD2<3>
CS<3>
CCD1<0>
CCD2<0>
CS<0>
Closed Caption first data byte.
E7H CCD2<7> CCD2<6>
Closed Caption second data byte.
B7H
Closed Caption Slice line using 525 line number.
83H DPH<7> DPH<6> DPH<5>
0
0
DPH
DPH<7:0>
DPL
DPL<7:0>
DPH<4>
DPH<3>
DPH<2>
DPL<2>
EX1
DPH<1>
DPL<1>
ET0
DPH<0>
DPL<0>
EX0
Data Pointer High byte, used with DPL to address display and auxiliary memory.
82H DPL<7> DPL<6> DPL<5> DPL<4> DPL<3>
Data pointer low byte, used with DPH to address display and auxiliary memory.
A8H EA EBUSY ES2 ECC
IE
ET1
EA
EBUSY
ES2
Disable all interrupts (0), or use individual interrupt enable bits (1).
Enable BUSY Interrupt.
Enable I2C Interrupt.
ECC
Enable Closed Caption Interrupt.
Table 3 SFR Bit description
2001 Jan 18
15
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
ET1
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Enable Timer 1 Interrupt.
Enable External Interrupt 1.
Enable Timer 0 Interrupt.
Enable External Interrupt 0.
EX1
ET0
EX0
IEN1
IP
84H
Enable Timer 2 Interrupt.
B8H
-
-
-
-
-
-
-
ET2
PX0
00H
00H
ET2
0
PBUSY
PES2
PCC
PT1
PX1
PT0
PBUSY
PES2
PCC
PT1
Priority EBUSY Interrupt.
Priority ES2 Interrupt.
Priority ECC Interrupt.
Priority Timer 1 Interrupt.
Priority External Interrupt 1.
Priority Timer 0 Interrupt.
Priority External Interrupt 0.
PX1
PT0
PX0
IP1
P0
85H
Priority Timer 2 Interrupt.
80H Reserved
-
-
-
-
-
-
-
PT2
00H
FFH
FFH
PT2
P0<6>
P0<5>
Reserved
Reserved
Reserved
P1<3>
Reserved
P1<2>
Reserved
P1<1>
Reserved
P1<0>
P0<6:5>
Port 0 I/O register connected to external pins.
90H P1<7> P1<6> Reserved
P1
P1<7:6>
P1<3:0>
Port 1 I/O register connected to external pins.
Port 1 I/O register connected to external pins.
P2
P3
A0H
Port 2 I/O register connected to external pins.
B0H Reserved Reserved Reserved
Port 3 I/O register connected to external pins.
Reserved
P2<6>
P2<5>
P2<4>
P2<3>
P3<3>
P2<2>
P3<2>
P2<1>
P3<1>
P2<0>
P3<0>
FFH
FFH
P2<6:0>
P3<3:0>
Reserved
P0CFGA<6>
P0CFGB<6>
P0CFGA<5>
P0CFGB<5>
P0CFGA
P0CFGB
96H
97H
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FFH
00H
P0CFGB<x>/P0CFGA<x> = 00
P0CFGB<x>/P0CFGA<x> = 01
P0CFGB<x>/P0CFGA<x> = 10
P0CFGB<x>/P0CFGA<x> = 11
MODE 0 Open Drain.
MODE 1 Quasi Bi-Directional.
MODE2 High Impedance.
MODE3 Push Pull.
9EH
9FH
P1CFGA<7>
P1CFGB<7>
P1CFGA<6>
Reserved
P1CFGA<3>
P1CFGB<3>
P1CFGA<2>
P1CFGB<2>
P1CFGA<1>
P1CFGB<1>
P1CFGA<0>
P1CFGB<0>
P1CFGA
P1CFGB
Reserved
Reserved
FFH
00H
P1CFGB<6>
Reserved
Table 3 SFR Bit description
2001 Jan 18
16
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
P1CFGB<x>/P1CFGA<x> = 00
P1CFGB<x>/P1CFGA<x> = 01
P1CFGB<x>/P1CFGA<x> = 10
P1CFGB<x>/P1CFGA<x> = 11
MODE 0 Open Drain.
MODE 1 Quasi Bi-Directional.
MODE2 High Impedance.
MODE3 Push Pull.
P2CFGA<6>
P2CFGB<6>
P2CFGA<5>
P2CFGB<5>
P2CFGA<4>
P2CFGB<4>
P2CFGA<3>
P2CFGB<3>
P2CFGA<2>
P2CFGB<2>
P2CFGA<1>
P2CFGB<1>
P2CFGA<0>
P2CFGB<0>
P2CFGA
P2CFGB
A6H
A7H
Reserved
Reserved
FFH
00H
P2CFGB<x>/P2CFGA<x> = 00
P2CFGB<x>/P2CFGA<x> = 01
P2CFGB<x>/P2CFGA<x> = 10
P2CFGB<x>/P2CFGA<x> = 11
MODE 0 Open Drain.
MODE 1 Quasi Bi-Directional.
MODE2 High Impedance.
MODE3 Push Pull.
P3CFGA<3>
P3CFGB<3>
P3CFGA<2>
P3CFGB<2>
P3CFGA<1>
P3CFGB<1>
P3CFGA<0>
P3CFGB<0>
P3CFGA
P3CFGB
BEH
BFH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FFH
00H
P3CFGB<x>/P3CFGA<x> = 00
P3CFGB<x>/P3CFGA<x> = 01
P3CFGB<x>/P3CFGA<x> = 10
P3CFGB<x>/P3CFGA<x> = 11
MODE 0 Open Drain.
MODE 1 Quasi Bi-directional.
MODE2 High Impedance.
MODE3 Push Pull.
PCON
87H
SMOD
ARD
RFI
WLE
GF1
GF0
PD
IDL
00H
SMOD
ARD
RFI
UART Baud Rate Double Control.
Auxiliary RAM Disable, All MOVX instructions access the external data memory.
Disable ALE during internal access to reduce Radio Frequency Interference.
Watch Dog Timer enable.
WLE
GF1
GF0
PD
General purpose flag.
General purpose flag.
Power-down activation bit.
IDL
Idle mode activation bit.
PSW
D0H
C
AC
F0
RS<1>
RS<0>
OV
-
P
00H
C
AC
F0
Carry Bit.
Auxiliary Carry bit.
Flag 0, General purpose flag.
RS<1:0>
Register Bank selector bits.
RS<1:0> = 00, Bank0 (00H - 07H).
RS<1:0> = 01, Bank1 (08H - 0FH).
RS<1:0> = 10, Bank2 (10H - 17H).
RS<1:0> = 11, Bank3 (18H - 1FH).
OV
Overflow flag.
Table 3 SFR Bit description
2001 Jan 18
17
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
ADD
Parity bit.
D5H
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
40H
P
PWM0
PW0E
1
PW0V<5>
PW0V<4>
PW0V<3>
PW0V<2>
PW0V<1>
PW0V<0>
PW0E 0 - Disable Pulse Width Modulator 0.
1 - Enable Pulse Width Modulator 0.
PW0V<5:0>
PWM1
Pulse Width Modulator high time.
D6H PW1E
1
PW1V<5>
PW2V<5>
PW3V<5>
IIC_LUT<0>
PW1V<4>
PW2V<4>
PW3V<4>
0
PW1V<3>
PW2V<3>
PW3V<3>
0
PW1V<2>
PW2V<2>
PW3V<2>
0
PW1V<1>
PW2V<1>
PW3V<1>
ROMBK<1>
PW1V<0>
PW2V<0>
PW3V<0>
ROMBK<0>
40H
40H
40H
00H
PW1E
0 - Disable Pulse Width Modulator 1.
1 - Enable Pulse Width Modulator 1.
PW1V<5:0>
PWM2
Pulse Width Modulator high time.
E4H
PW2E
1
PW2E
0 - Disable Pulse Width Modulator 2.
1 - Enable Pulse Width Modulator 2.
PW2V<5:0>
Pulse Width Modulator high time.
PWM3
DCH
PW3E
1
PW3E
0 - Disable Pulse Width Modulator 3.
1 - Enable Pulse Width Modulator 3.
PW3V<5:0>
ROMBK
Pulse Width Modulator high time.
IIC_LUT<1>
FBH
STANDBY
STANDBY
0 - Disable Stand-by Mode
1 - Enable Stand-by Mode
IIC_LUT<1:0
>
IIC Lookup table selection:
IIC_LUT<1:0>=00, 558 Normal Mode.
IIC_LUT<1:0>=01, 558 Fast Mode.
IIC_LUT<1:0>=10, 558 Slow Mode.
IIC_LUT<1:0>=11, Reserved.
ROMBK<1:0
>
ROM Bank selection
ROMBK<1:0>=00, Bank0
ROMBK<1:0>=01, Bank1
ROMBK<1:0>=10, Bank2
ROMBK<1:0>=11, Reserved
S1ADR
ADR<6:0>
GC
DBH
ADR<6>
ADR<5>
ADR<4>
ADR<3>
ADR<2>
ADR<1>
ADR<0>
GC
00H
00H
I2C Slave Address.
0 - Disable I2C general call address.
1 - Enable I2C general call address.
S1CON
D8H
CR<2>
ENSI
STA
STO
SI
AA
CR<1>
CR<0>
CR<2:0>
Clock rate bits.
IIC rates are selectable (three tables)
ENSI
0 - Disable I2C interface.
1 - Enable I2C interface.
Table 3 SFR Bit description
2001 Jan 18
18
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
STA
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus
becomes free. If the device operates in master mode it will generate a repeated START condition.
STO
SI
STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also
be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases
the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware.
Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur:
-A START condition is generated in master mode.
-The own slave address has been received during AA=1.
-The general call address has been received while S1ADR.GC and AA=1.
-A data byte has been received or transmitted in master mode (even if arbitration is lost).
-A data byte has been received or transmitted as selected slave.
A STOP or START condition is received as selected slave receiver or transmitter
While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.
AA
Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions
-Own slave address is received.
-General call address is received(S1ADR.GC=1).
-A data byte is received, while the device is programmed to be a master receiver.
-A data byte is received, while the device is selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received.
S1DAT
DAT<7:0>
S1STA
STAT<4:0>
SAD
DAH
DAT<7>
DAT<6>
STAT<3>
CH<1>
DAT<5>
STAT<2>
CH<0>
DAT<4>
STAT<1>
ST
DAT<3>
STAT<0>
SAD<7>
DAT<2>
DAT<1>
DAT<0>
00H
F8H
00H
I2C Data.
D9H
STAT<4>
0
0
0
I2C Interface Status.
E8H VHI
SAD<6>
SAD<5>
SAD<4>
VHI
0 - Analogue input voltage less than or equal to DAC voltage.
1 - Analogue input voltage greater then DAC voltage.
CH<1:0>
ADC Input channel select.
CH<1:0> = 00,ADC3.
CH<1:0> = 01,ADC0.
CH<1:0> = 10,ADC1.
CH<1:0> = 11,ADC2.
ST
Initiate voltage comparison between ADC input Channel and SADB<3:0> value.
Note: Set by Software and reset by Hardware.
SAD<7:4>
Most Significant nibble of DAC input word
SADB
98H
0
0
0
DC_COMP
SAD<3>
SAD<2>
SAD<1>
SAD<0>
00H
DC_COMP
0 - Disable DC Comparator mode.
1 - Enable DC Comparator mode.
SAD<3:0>
4-bit SAD value.
SP
81H
Stack Pointer.
88H TF1
SP<7>
SP<6>
SP<5>
SP<4>
TR0
SP<3>
SP<2>
SP<1>
SP<0>
07H
00H
SP<7>
TCON
TR1
TF0
IE1
IT1
IE0
IT0
TF1
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine.
Table 3 SFR Bit description
2001 Jan 18
19
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
TR1
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off.
TF0
TR0
IE1
IT1
IE0
IT0
Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine.
Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off.
Interrupt 1 Edge flag (both edges generate flag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts.
Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
Interrupt 0 Type flag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts.
TDACH
D3H
TPWE
1
TD<13>
TD<12>
TD<11>
TD<10>
TD<9>
TD<8>
40H
TPWE
0 - Disable Tuning Pulse Width Modulator.
1 - Enable Tuning Pulse Width Modulator.
TD<13:8>
Tuning Pulse Width Modulator High Byte.
TDACL
TD<7:0>
D2H
TD<7>
TD<6>
TD<5>
TH0<5>
TH1<5>
TL0<5>
TL1<5>
TD<4>
TH0<4>
TH1<4>
TL0<4>
TL1<4>
TD<3>
TH0<3>
TH1<3>
TL0<3>
TL1<3>
TD<2>
TH0<2>
TH1<2>
TL0<2>
TL1<2>
TD<1>
TH0<1>
TH1<1>
TL0<1>
TL1<1>
TD<0>
TH0<0>
TH1<0>
TL0<0>
TL1<0>
00H
00H
00H
00H
00H
00H
Tuning Pulse Width Modulator Low Byte.
TH0
TH0<7:0>
TH1
8CH
Timer 0 high byte.
8DH TH1<7>
Timer 1 high byte.
8AH TL0<7>
Timer 0 low byte.
TH0<7>
TH0<6>
TH1<6>
TL0<6>
TL1<6>
TH1<7:0>
TL0<7:0>
TL1<7:0>
TL0
TL1
8BH
TL1<7>
Timer 1 low byte.
TMOD
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
Timer / Counter 1
Timer / Counter 0
GATE
C/T
Gating Control Timer /Counter 1.
Counter/Timer 1 selector.
M1,M0
Mode control bits Timer/Counter 1.
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler.
M1,M0 = 01, 16 bit time interval or event counter.
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1.
M1,M0 = 11, stopped.
GATE
C/T
Gating control Timer/Counter 0.
Counter/Timer 0 selector.
Table 3 SFR Bit description
2001 Jan 18
20
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
M1,M0
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Mode Control bits Timer/Counter 0.
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler.
M1,M0 = 01, 16 bit time interval or event counter.
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0.
M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter.
TP2CL
9CH
Indicate the low byte of the Time 2 current value.
9DH TP2CH<7> TP2CH<6> TP2CH<5>
Indicate the high byte of the Time 2 current value.
92H TP2H<7> TP2H<6> TP2H<5>
Timer 2 high byte, never change unless updated by the software.
91H TP2L<7> TP2L<6> TP2L<5> TP2L<4>
Timer 2 low byte, never change unless updated by the software.
93H TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4>
Timer 2 Pre-scaler, never change unless updated by the software.
TP2CL<7>
TP2CL<6>
TP2CL<5>
TP2CL<4>
TP2CH<4>
TP2H<4>
TP2CL<3>
TP2CH<3>
TP2H<3>
TP2L<3>
TP2PR<3>
-
TP2CL<2>
TP2CH<2>
TP2H<2>
TP2L<2>
TP2PR<2>
-
TP2CL<1>
TP2CH<1>
TP2H<1>
TP2L<1>
TP2CL<0>
TP2CH<0>
TP2H<0>
TP2L<0>
00H
00H
00H
00H
00H
00H
TP2CL<7:0>
TP2CH
TP2CH<7:0>
TP2H
TP2H<7:0>
TP2L
TP2L<7:0>
TP2PR
TP2PR<1>
TP2CRL<1>
TP2PR<0>
TP2CRL<0>
TP2H<7:0>
TP2CRL
TP2CRL<0>
94H
-
-
-
-
Timer 2 Control.
0 - Timer 2 disabled.
1 - Timer 2 enabled.
TP2CRL<1>
Timer 2 Status.
0 - No Overflow.
1 - Overflow.
TEST
FDH
TEST<7>
TEST<6>
TEST<5>
TEST<4>
TEST<3>
TEST<2>
TEST<1>
TEST<0>
00H
TEST<2:0>
Program Type bit SEL<2:0>.
011 - Display Dram test.
001 - Acquisition1 test.
010 - Acquisition2 test
TEST<4:3>
TEST<7:5>
Functional test mode bits, set via mode select logic.
Dram Size.
000 - 1.5K x 16.
001 - 2K x 16.
010 - 6K x 16.
011 - 7K x 16.
100 - 12K x 16.
101 - 14K x 16.
110 - 1K x 16.
111 - 11K x 16.
TXT0
C0H
X24 POSN
DISPLAY
X24
AUTO
FRAME
DISABLE
HEADER
ROLL
DISPLAY
STATUS
ROW
DISABLE
FRAME
VPS ON
INV ON
00H
ONLY
X24 POSN
0 - Store X/24 in extension memory
1 - Store X/24 in basic page memory with packets 0 to 23
Table 3 SFR Bit description
2001 Jan 18
21
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
DISLAY X24
0 - Display row 24 from basic page memory
1 - Display row 24 from appropriate location in extension memory
AUTO
0 - Normal Frame output
FRAME
1 - Frame output is switched off automatically if any video displayed
DISABLE
HEADER
ROLL
0 - Write rolling headers and time to current display page
1 - Disable writing of rolling headers and time to into memory
DISPLAY
STATUS
ROW ONLY
0 - Display normal page rows 0 to 24
1- Display only row 24
DISABLE
FRAME
0 - Normal Frame output
1 - Force Frame output to be low (0)
VPS ON
INV ON
0 - VPS acquisition off
1 - VPS acquisition on
0 - Inventory page off
1 - Inventory page on
TXT1
C1H
EXT PKT
OFF
8 BIT
ACQ OFF
ACQ OFF
FULL
FIELD
FIELD
POLARITY
H
V
00H
POLARITY
POLARITY
EXT PKT
OFF
0 - Acquire extension packets X/24,X/27,8/30/X
1 - Disable acquisition of extension packets
8 BIT
ACQ OFF
0 - Error check and/or correct packets 0 to 24
1 - Disable checking of packets 0 to 24 written into memory
0 - Write requested data into display memory
1 - Disable writing of data into Display memory
X26 OFF
0 - Enable automatic processing of X/26 data
1 - Disable automatic processing of X/26 data
FULL FIELD
0 - Acquire CC data only on selected line.
1 - Acquire CC data on any TV line (for test purposes).
FIELD
POLARIY
0 - Vsync pulse in first half of line during even field.
1 - Vsync pulse in second half of line during even field.
H POLARITY
V POLARITY
0 - Hsync reference edge is positive going
1 - Hsync reference edge is negative going
0 - Vsync reference edge is positive going
1 - Vsync reference edge is negative going
TXT2
C2H
ACQ
REQ<3>
REQ<2>
REQ<1>
REQ<0>
SC<2>
SC<1>
SC<0>
00H
BANK
ACQ_BANK
0 - Select Acquisition bank 0
1 - Select Acquisition bank 1
REQ<3:0>
SC<2:0>
Page request
Start column of page request
C3H
TXT3
PRD<4>
PRD<3>
PRD<2>
PRD<1>
PRD<0>
00H
PRD<4:0>
Page Request data
Table 3 SFR Bit description
2001 Jan 18
22
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
TXT4
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
00H
EAST/WEST
C4H
OSD
BANK
ENABLE
QUAD
WIDTH
ENABLE
DISABLE
DBL
HEIGHT
B MESH
ENABLE
C MESH
ENABLE
TRANS
ENABLE
SHADOW
ENABLE
OSD BANK
ENABLE
0 - Only alpha numeric OSD characters available, 32 locations
1 - Alternate OSD location available via graphic attribute, additional 32 location
QUAD
WIDTH
ENABLE
0 - Disable display of Quadruple width characters
1 - Enable display of Quadruple width characters
EAST/WEST
0 - Western language selection of character codes A0 to FF
1 - Eastern character selection of character codes A0 to FF
DISABLE
DOUBLE
HEIGHT
0 - Allow normal decoding of double height characters
1 - Disable normal decoding of double height characters
B MESH
ENABLE
0 - Normal display of black background
1 - Enable meshing of black background
C MESH
ENABLE
0 - normal display of coloured background
1 - Enable meshing of coloured background
TRANS
ENABLE
0 - Display black background as normal
1 - Display black background as video
SHADOW
ENABLE
0 - Disable display of shadow/fringing
1 - Display shadow/ fringe (default SE black)
TXT5
C5H
BKGND
OUT
BKGND IN
COR OUT
COR IN
TEXT OUT
TEXT IN
PICTURE
ON OUT
PICTURE
ON IN
03H
BKGND OUT
0 - Background colour not displayed outside teletext boxes
1 - Background colour displayed outside teletext boxes
BKGND IN
COR OUT
COR IN
0 - Background colour not displayed inside teletext boxes
1 - Background colour displayed inside teletext boxes
0 - COR not active outside teletext and OSD boxes
1 - COR active outside teletext and OSD boxes
0 - COR not active inside teletext and OSD boxes
1 - COR active inside teletext and OSD boxes
TEXT OUT
TEXT IN
0 - TEXT not displayed outside teletext boxes
1 - TEXT displayed outside teletext boxes
0 - TEXT not displayed inside teletext boxes
1 - TEXT displayed inside teletext boxes
PICTURE ON
OUT
0 - VIDEO not displayed outside teletext boxes
1 - VIDEO displayed outside teletext boxes
PICTURE ON
IN
0 - VIDEO not displayed inside teletext boxes
1 - VIDEO displayed inside teletext boxes
TXT6
C6H
BKGND
OUT
BKGND IN
COR OUT
COR IN
TEXT OUT
TEXT IN
PICTURE
ON OUT
PICTURE
ON IN
03H
BKGND OUT
0 - Background colour not displayed outside teletext boxes
1 - Background colour displayed outside teletext boxes
Table 3 SFR Bit description
2001 Jan 18
23
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
BKGND IN
0 - Background colour not displayed inside teletext boxes
1 - Background colour displayed inside teletext boxes
COR OUT
COR IN
0 - COR not active outside teletext and OSD boxes
1 - COR active outside teletext and OSD boxes
0 - COR not active inside teletext and OSD boxes
1 - COR active inside teletext and OSD boxes
TEXT OUT
TEXT IN
0 - TEXT not displayed outside teletext boxes
1 - TEXT displayed outside teletext boxes
0 - TEXT not displayed inside teletext boxes
1 - TEXT displayed inside teletext boxes
PICTURE ON
OUT
0 - VIDEO not displayed outside teletext boxes
1 - VIDEO displayed outside teletext boxes
PICTURE ON
IN
0 - VIDEO not displayed inside teletext boxes
1 - VIDEO displayed inside teletext boxes
TXT7
C7H
STATUS
ROW TOP
CURSOR
ON
REVEAL
BOTTOM/
TOP
DOUBLE
HEIGHT
BOX ON 24
BOX ON
1-23
BOX ON 0
00H
STATUS
ROW TOP
0 - Display memory row 24 information below teletext page (on display row 24)
1 - Display memory row 24 information above teletext page (on display row 0)
CURSOR ON
REVEAL
0 - Disable display of cursor
1 - Display cursor at position given by TXT9 and TXT10
0 - Display as spaces characters in area with conceal attribute set
1 - Display characters in area with conceal attribute set
BOTTOM/TO
P
0 - Display memory rows 0 to 11 when double height bit is set
1 - Display memory rows 12 to 23 when double height bit is set
DOUBLE
HEIGHT
0 - Display each characters with normal height
1 - Display each character as twice normal height.
BOX ON 24
BOX ON 1-23
BOX ON 0
TXT8
0 - Disable display of teletext boxes in memory row 24
1 - Enable display of teletext boxes in memory row 24
0 - Disable display of teletext boxes in memory row 1 to 23
1 - Enable display of teletext boxes in memory row 1 to 23
0 - Disable display of teletext boxes in memory row 0
1 - Enable display of teletext boxes in memory row 0
C8H
(Reserved)
0
FLICKER
STOP ON
HUNT
DISABLE
SPANISH
PKT 26
RECEIVED
WSS
RECEIVED
WSS ON
(Reserved)
0
00H
FLICKER
STOP ON
0 - Enable ‘Flicker Stopper’ circuitry
1 - Disable ‘Flicker Stopper’ circuitry
HUNT
0 - Allow automatic hunting for amplitude of data to be acquired
1 - Disable automatic hunting for amplitude
DISABLE
SPANISH
0 - Enable special treatment of Spanish packet 26 characters
1 - Disable special treatment of Spanish packet 26 characters
Table 3 SFR Bit description
2001 Jan 18
24
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
PKT 26
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
0 - No packet 26 data has been processed
1 - Packet 26 data has been processed.
RECEIVED
Note: This flag is set by Hardware and must be reset by Software
WSS
RECEIVED
0 - No Wide Screen Signalling data has been processed
1 - Wide Screen signalling data has been processed
Note: This flag is set by Hardware and must be reset by Software.
WSS ON
0 - Disable acquisition of WSS data.
1 - Enable acquisition of WSS data.
TXT9
C9H
CURSOR
FREEZE
CLEAR
MEMORY
A0
R<4>
R<3>
R<2>
R<1>
R<0>
00H
CURSOR
FREEZE
0 - Use current TXT9 and TXT10 values for cursor position.
1 - Lock cursor at current position
CLEAR
0 -
MEMORY
1 - Clear memory block pointed to by TXT15
Note: This flag is set by Software and reset by Hardware
A0
0 - Access memory block pointed to by TXT15
1 - Access extension packet memory
R<4:0>
Current memory ROW value.
Note: Valid range TXT mode 0 to 24, CC mode 0 to 15
TXT10
CAH
0
0
C<5>
C<4>
D<4>
C<3>
D<3>
C<2>
D<2>
C<1>
C<0>
D<0>
00H
00H
C<5:0>
Current memory COLUMN value.
Note: Valid range TXT mode 0 to 39, CC mode 0 to 47
TXT11
D<7:0>
TXT12
CBH
D<7>
D<6>
D<5>
D<1>
1
Data value written or read from memory location defined by TXT9, TXT10 and TXT15
CCH
625/525
SYNC
ROM
VER<4>
ROM
VER<3>
ROM
VER<2>
ROM
VER<1>
ROM
VER<0>
VIDEO
SIGNAL
QUALITY
xxxxx
x1xB
625/525
SYNC
0 - 625 line CVBS signal is being received
1 - 525 line CVBS signal is being received
ROM
VER<4:0>
Mask programmable identification for character set
Rom Version <4> :
0 - Spanish Flicker Stopper Disabled.
1 - Spanish Flicker Stopper Enabled (Controlled by TXT8 Bit-6).
1
Reserved
VIDEO
SIGNAL
QUALITY
0 - Acquisition can not be synchronised to CVBS input.
1 - Acquisition can be synchronised to CVBS
PAGE
CLEARING
TXT13
F8H
VPS
RECEIVED
525
DISPLAY
525 TEXT
625 TEXT
PKT 8/30
FASTEXT
0
xxxxx
xx0B
VPS
0 -
RECEIVED
1 - VPS data
PAGE
0 - No page clearing active
CLEARING
1 - Software or Power On page clear in progress
Table 3 SFR Bit description
2001 Jan 18
25
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
525 DISPLAY
0 - 625 Line synchronisation for Display.
1 - 525 Line synchronisation for Display.
525 TEXT
625 TEXT
PKT 8/30
FASTEXT
0 - 525 Line WST not being received
1 - 525 line WST being received
0 - 625 Line WST not being received
1 - 625 line WST being received
0 - No Packet 8/30/x(625) or Packet 4/30/x(525) data detected
1 - Packet 8/30/x(625) or Packet 4/30/x(525) data detected
0 - No Packet x/27 data detected
1 - Packet x/27 data detected
0
Reserved
TXT14
CDH
0
0
0
DISPLAY
BANK
PAGE<3>
PAGE<2>
PAGE<1>
PAGE<0>
00H
00H
00H
DISPLAY
BANK
0 - Select lower bank for Display
1 - Select upper bank for Display
PAGE<3:0>
Current Display page
TXT15
CEH
0
0
0
MICRO
BANK
BLOCK<3
>
BLOCK<2
>
BLOCK<1
>
BLOCK<0
>
MICRO
BANK
0 - Select lower bank for Micro
1 - Select upper bank for Micro
BLOCK<3:0>
Current Micro block to be accessed by TXT9, TXT10 and TXT11
TXT17
B9H
0
FORCE
ACQ<1>
FORCE
ACQ<0>
FORCE
DISP<1>
FORCE
DISP<0>
SCREEN
COL2
SCREEN
COL1
SCREEN
COL0
FORCE
00 - Automatic Selection
ACQ<1:0>
01 - Force 525 timing, Force 525 Teletext Standard
10 - Force 625 timing, Force 625 Teletext Standard
11 - Force 625 timing, Force 525 Teletext Standard
FORCE
00 - Automatic Selection
DISP<1:0>
01 - Force Display to 525 mode (9 lines per row)
10 - Force Display to 625 mode (10 lines per row)
11 - Not Valid (default to 625)
SCREEN
Defines colour to be displayed instead of TV picture and black background. The bits <2:0> are equivalent to the RGB components
COL<2:0>
000 - Transparent
001 - CLUT entry 9
010 - CLUT entry 10
011- CLUT entry 11
100 - CLUT entry 12
101 - CLUT entry 13
110- CLUT entry 14
111 - CLUT entry 15
TXT18
B2H
NOT<3>
NOT<2>
NOT<1>
NOT<0>
0
0
BS<1>
BS<0>
00H
NOT<3:0>
BS<1:0>
National Option table selection, maximum of 32 when used with East/West bit
Basic Character set selection
Table 3 SFR Bit description
2001 Jan 18
26
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
TXT19
ADD
BIT7
TEN
BIT6
TC<2>
BIT5
TC<1>
BIT4
TC<0>
BIT3
BIT2
BIT1
TS<1>
BIT0
TS<0>
RESET
00H
B3H
0
0
TEN
0 - Disable Twist function
1- Enable Twist character set
TC<2:0>
TS<1:0>
Language control bits (C12/C13/C14) that has Twisted character set
Twist Character set selection
TXT20
B4H
DRCS
ENABLE
OSD
PLANES
0
0
OSD
LANG
OSD
LAN<2>
OSD
LAN<1>
OSD
LAN<0>
00H
ENABLE
DRCS
ENABLE
0 - Normal OSD characters used
1 - Re-map column 9 to DRCS (TXT and CC modes),
OSD
PLANES
0 - Character code columns 8 and 9 defined as single plane characters
1- Character code columns 8 and 9 defined as double plane characters
OSD LANG
ENABLE
Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14
Alternative C12/C13/C14 bits for use with OSD menus
OSD
LAN<2:0>
TXT21
B5H
DISP
DISP
CHAR
CHAR
Reserved
CC ON
I2C PORT0
CC/TXT
02H
LINES<1>
LINES<0>
SIZE<1>
SIZE<0>
DISP
LINES<1:0>
The number of display lines per character row.
00 - 10 lines per character (defaults to 9 lines in 525 mode)
01 - 13 lines per character
10 - 16 lines per character
11 - reserved
CHAR
Character matrix size.
SIZE<1:0>
00 - 10 lines per character (matrix 12x10)
01 - 13 lines per character (matrix 12x13)
10 - 16lines per character (matrix 12x16)
11 - reserved
CCON
I2C PORT0
CC/TXT
0 - Closed Caption acquisition off
1 - Closed Caption acquisition on
0 - Disable I2C PORT0
1 - Enable I2C PORT0 selection (P1.7/SDA0, P1.6/SCL0)
0 - Display configured for TXT mode
1 - Display configured for CC mode
TXT22
B6H
GPF<7>
GPF<6>
GPF<5>
GPF<4>
GPF<3>
GPF<2>
GPF<1>
GPF<0>
XXH
GPF<7:6>
GPF<5>
General purpose register, bits defined by mask programmable bits
0 - Standard Painter device
1 - Enhanced Painter device
GPF<4>
(Used for
software only)
0 - Choose 6 page teletext device
1 - Choose 10 page teletext device
GPF<3>
0 - PWM0, PWM1, PWM2 & PWM3 output on Port 3.0 to Port 3.3 respectively
1 - PWM0, PWM1, PWM2 & PWM3 output on Port 2.1 to Port 2.4 respectively
Table 3 SFR Bit description
2001 Jan 18
27
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Names
GPF<2>
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
0 - Disable Closed Caption acquisition
1 - Enable Closed Caption acquisition
GPF<1>
0 - Disable Text acquisition
1 - Enable Text acquisition
GPF<0>
(Polarity
reversed in
Painter1_Plus
standalone)
0 - Standalone (Painter1_Plus) mode
1 - UOC mode
WDT
FFH
Watch Dog Timer period
FEH WKEY<7>
WDV<7>
WDV<6>
WDV<5>
WDV<4>
WDV<3>
WDV<2>
WDV<1>
WDV<0>
00H
00H
WDv<7:0>
WDTKEY
WKEY<7:0>
WKEY<6>
WKEY<5>
WKEY<4>
WKEY<3>
WKEY<2>
WKEY<1>
WKEY<0>
Watch Dog Timer Key.
Note: Must be set to 55H to disable Watch dog timer when active.
WSS1
BAH
0
0
0
WSS<3:0>
ERROR
WSS<3>
WSS<2>
WSS<6>
WSS<10>
WSS<1>
WSS<5>
WSS<9>
WSS<0>
WSS<4>
WSS<8>
00H
00H
00H
WSS<3:0>
ERROR
0 - No error in WSS<3:0>
1 - Error in WSS<3:0>
WSS<3:0>
Signalling bits to define aspect ratio (group 1)
BBH
WSS2
0
0
0
WSS<7:4>
ERROR
WSS<7>
WSS<7:4>
ERROR
0 - No errors in WSS<7:4>
1 - Error in WSS<7:4>
WSS<7:4>
Signalling bits to define enhanced services (group 2)
WSS3
BCH
WSS<13:11
< ERROR
WSS<13>
WSS<12>
WSS<11>
WSS<10:8>
ERROR
WSS<13:11>
ERROR
0 - No error in WSS<13:11>
1 - Error in WSS<13:11>
WSS<13:11>
Signalling bits to define reserved elements (group 4)
WSS<10:8>
ERROR
0 - No error in WSS<10:8>
1 - Error in WS<10:8>
WSS<10:8>
XRAMP
Signalling bits to define subtitles (group 3)
FAH
XRAMP<7>
XRAMP<6>
XRAMP<5>
XRAMP<4>
XRAMP<3>
XRAMP<2>
XRAMP<1>
XRAMP<0>
00H
XRAMP<7:0>
Internal RAM access upper byte address.
Table 3 SFR Bit description
2001 Jan 18
28
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
External (Auxiliary + Display) Memory
consecutive bytes. XRAMP only works on internal MOVX
memory.
The normal 80C51 external memory area has been
mapped internally to the device, this means that the MOVX
instruction accesses data memory internal to the device.
The movx memory map is shown in Fig.7.
FFH
FFFFH
(XRAMP)=FFH
(XRAMP)=FEH
00H
FFH
FF00H
FEFFH
7FFFH
FFFFH
00H
FFH
FE00H
01FFH
MOVX @Ri, A
MOVX A, @Ri
MOVX @DPTR,A
MOVX A,@DPTR
(XRAMP)=01H
(XRAMP)=00H
4800H
47FFH
00H
FFH
0100H
00FFH
8C00H
8BFFH
00H
0000H
Dynamically
Re-definable
Characters
Fig.8 Indirect addressing
(Movx address space)
Display RAM
for
TEXT PAGES(2)
8800H
87FFH
Display Registers
Power-on Reset
87F0H
Power on reset is generated internally to the
TDA935X/6x/8x device, hence no external reset circuitry is
required. The TV processor die shall generate the master
reset in the system, which in turn will reset the
microcontroller die
871FH
8700H
CLUT
2000H
07FFH
845FH
Display RAM
for
Data RAM(1)
Closed Caption(3)
8000H
A external reset pin is still present and is logically ORed
with the internal Power on reset. This pin will only be used
for test modes and OTP/ISP programming. The active high
reset pin incorporates an internal pull-down, thus it can be
left unconnected in application.
0000H
Lower 32K bytes
Upper 32K bytes
(1) Amount of Data RAM depends on device, PainterOSD 64K has 0.75K,
Painter1.1 has 1K and Painter1.10 has 2K
(2) Amount of Display RAM depends on the device, PainterOSD 64K has
1.25K, Painter1.1 has 2K and Painter1.10 has 10K
Power Saving modes of Operation
(3) Display RAM for Closed Caption and Text is shared
There are three Power Saving modes, Idle, Stand-by and
Power Down, incorporated into the Painter1_Plus die.
When utilizing either mode, the 3.3v power to the device
(Vddp, Vddc & Vdda) should be maintained, since Power
Saving is achieved by clock gating on a section by section
basis.
Fig.7 Movx Address Map
Auxiliary RAM Page Selection
The Auxiliary RAM page pointer is used to select one of
the 256 pages within the auxiliary RAM, not all pages are
allocated, refer to Fig.8. A page consists of 256
STAND-BY MODE
During Stand-by mode, the Acquisition and Display
sections of the device are disabled. The following
functions remain active:-
• 80c51 CPU Core
• Memory Interface
• I2C
• Timer/Counters
• WatchDog Timer
• SAD and PWMs
2001 Jan 18
29
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
To enter Stand-by mode, the STAND-BY bit in the
ROMBANK register must be set. Once in Stand-By, the
XTAL oscillator continues to run, but the internal clock to
Acquisition and Display are gated out. However, the clocks
to the 80c51 CPU Core, Memory Interface, I2C,
Timer/Counters, WatchDog Timer and Pulse Width
Modulators are maintained. Since the output values on
RGB and VDS are maintained the display output must be
disabled before entering this mode.
This mode may be used in conjunction with both Idle and
Power-Down modes. Hence, prior to entering either Idle or
Power-Down, the STAND-BY bit may be set, thus allowing
wake-up of the 80c51 CPU core without fully waking the
entire device (This enables detection of a Remote Control
source in a power saving mode).
executed will be the one following the instruction that put
the device into Idle.
• The third method of terminating Idle mode is with an
external hardware reset. Since the oscillator is running,
the hardware reset need only be active for two machine
cycles (24 clocks at 12MHz) to complete the reset
operation. Reset defines all SFRs and Display memory
to a pre-defined state, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ’0000’.
POWER DOWN MODE
In Power Down mode the XTAL oscillator still runs, and
differential clock transmitter is active. The contents of all
SFRs and Data memory are maintained, however, the
contents of the Auxiliary/Display memory are lost. The port
pins maintain the values defined by their associated SFRs.
Since the output values on RGB and VDS are maintained
the Display output must be made inactive before entering
Power Down mode.
The power down mode is activated by setting the PD bit in
the PCON register. It is advised to disable the WatchDog
timer prior to entering Power down. Recovery from
Power-Down takes several milli-seconds as the oscillator
must be given time to stabilise.
There are three methods of exiting power down:-
• An External interrupt provides the first mechanism for
waking from Power-Down. Since the clock is stopped,
external interrupts needs to be set level sensitive prior to
entering Power-Down. The interrupt is serviced, and
following the instruction RETI, the next instruction to be
executed will be the one after the instruction that put the
device into Power-Down mode.
IDLE MODE
During Idle mode, Acquisition, Display and the CPU
sections of the device are disabled. The following
functions remain active:-
• Memory Interface
• I2C
• Timer/Counters
• WatchDog Timer
• SAD & PWMs
To enter Idle mode the IDL bit in the PCON register must
be set. The WatchDog timer must be disabled prior to
entering Idle to prevent the device being reset. Once in Idle
mode, the XTAL oscillator continues to run, but the internal
clock to the CPU, Acquisition and Display are gated out.
However, the clocks to the Memory Interface, I2C,
Timer/Counters, WatchDog Timer and Pulse Width
Modulators are maintained. The CPU state is frozen along
with the status of all SFRs, internal RAM contents are
maintained, as are the device output pin values. Since the
output values on RGB and VDS are maintained the
Display output must be disabled before entering this
mode.
There are three methods available to recover from Idle:-
• Assertion of an enabled interrupt will cause the IDL bit to
be cleared by hardware, thus terminating Idle mode.
The interrupt is serviced, and following the instruction
RETI, the next instruction to be executed will be the one
after the instruction that put the device into Idle mode.
• A second method of exiting Power-Down is via an
Interrupt generated by the SAD DC Compare circuit.
When Painter is configured in this mode, detection of a
certain analogue threshold at the input to the SAD may
be used to trigger wake-up of the device i.e. TV Front
Panel Key-press. As above, the interrupt is serviced,
and following the instruction RETI, the next instruction to
be executed will be the one following the instruction that
put the device into Power-Down.
• The third method of terminating the Power-Down mode
is with an external hardware reset. Reset defines all
SFRs and Display memory, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ’0000’.
• A second method of exiting Idle is via an Interrupt
generated by the SAD DC Compare circuit. When
Painter is configured in this mode, detection of an
analogue threshold at the input to the SAD may be used
to trigger wake-up of the device i.e. TV Front Panel
Key-press. As above, the interrupt is serviced, and
following the instruction RETI, the next instruction to be
2001 Jan 18
30
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
I/O Facility
In addition to the conventional 80c51, two application
specific interrupts are incorporated internal to the device
which have the following functionality:-
I/O PORTS
The IC has 13 I/O lines, each is individually addressable,
or form part of 4 parallel addressable ports which are
port0, port1, port2 and port3.
CC (Closed Caption Data Ready Interrupt) - This
interrupt is generated when the device is configured for
Closed Caption acquisition. The interrupt is activated at
the end of the currently selected Slice Line as defined in
the CCLIN SFR.
PORT TYPE
All individual ports can be programmed to function in one
of four modes, the mode is defined by two Port
Configuration SFRs. The modes available are Open Drain,
Quasi-bidirectional, High Impedance and Push-Pull.
BUSY (Display Busy Interrupt) - An interrupt is
generated when the Display enters either a Horizontal or
Vertical Blanking Period. i.e. Indicates when the
micro-controller can update the Display RAM without
causing undesired effects on the screen. This interrupt can
be configured in one of two modes using the MMR
Configuration Register (Address 87FF, Bit-3 [TXT/V]):-
• TeXT Display Busy: An interrupt is generated on each
active horizontal display line when the Horizontal
Blanking Period is entered.
Open Drain
The Open drain mode can be used for bi-directional
operation of a port. It requires an external pull-up resistor,
the pull-up voltage has a maximum value of 5.5V, to allow
connection of the device into a 5V environment.
• Vertical Display Busy: An interrupt is generated on each
vertical display field when the Vertical Blanking Period is
entered.
Quasi bi-directional
The quasi-bidirectional mode is a combination of open
drain and push pull. It requires an external pull-up resistor
to VDDp (nominally 3.3V). When a signal transition from
0->1 is output from the device, the pad is put into push-pull
mode for one clock cycle (166ns) after which the pad goes
into open drain mode. This mode is used to speed up the
edges of signal transitions. This is the default mode of
operation of the pads after reset.
INTERRUPT ENABLE STRUCTURE
Each of the individual interrupts can be enabled or
disabled by setting or clearing the relevant bit in the
interrupt enable SFRs (IE and IEN1). All interrupt sources
can also be globally disabled by clearing the EA bit (IE.7).
High Impedance
H1 Highest Priority Level1
EX0
L1
The high impedance mode can be used for Input only
operation of the port. When using this configuration the two
output transistors are turned off.
Highest Priority Level0
H2
ET0
L2
H3
EX1
ET1
ECC
L3
H4
Push-Pull
L4
H5
The push pull mode can be used for output only. In this
mode the signal is driven to either 0V or VDDp, which is
nominally 3.3V.
L5
H6
ES2
L6
H7
EBUSY
L7
IE.0:6
IE1.0
IP.0:6
IP1.0
Interrupt System
Lowest Priority Level1
Lowest Priority Level0
H8
L8
The device has 8 interrupt sources, each of which can be
enabled or disabled. When enabled, each interrupt can be
assigned one of two priority levels. There are four
interrupts that are common to the 80C51, two of these are
external interrupts (EX0 and EX1) and the other two are
timer interrupts (ET0 and ET1). There is also one interrupt
(ES2) connected to the 80c51 micro-controller IIC
peripheral for Transmit and Receive operation.
The TDA935X/6x/8x family of devices have an additional
16-bit Timer (with 8-bit Pre-scaler). To accommodate this,
another interrupt ET2PR has been added to indicate timer
overflow.
ET2PR
IE.7
Interrupt
Source
Source
Enable
Global
Enable
Priority
Control
Fig.9 Interrupt Structure
INTERRUPT ENABLE PRIORITY
Each interrupt source can be assigned one of two priority
levels. The interrupt priorities are defined by the interrupt
priority SFRs (IP and IP1). A low priority interrupt can be
interrupted by a high priority interrupt, but not by another
low priority interrupt. A high priority interrupt can not be
interrupted by any other interrupt source. If two requests of
2001 Jan 18
31
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
different priority level are received simultaneously, the
request with the highest priority level is serviced. If
requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence as defined in Table 4.
In Counter mode, the register is incremented in response
to a negative transition at its corresponding external pin
T0/1. Since the pins T0/1 are sampled once per machine
cycle it takes two machine cycles to recognise a transition,
this gives a maximum count rate of 1/24 Fosc = 0.5MHz.
There are six special function registers used to control the
timers/counters as defined in Table 6.
Source
EX0
Priority within level
Interrupt Vector
0003H
SFR
TCON
TMOD
TL0
Address
88H
Highest
ET0
000BH
89H
EX1
0013H
8AH
8BH
ET1
001BH
TH0
ECC
0023H
TL1
8CH
ES2
002BH
TH1
8DH
EBUSY
ET2PR
0033H
Table 6 Timer/Counter Registers
Lowest
003BH
Table 4 Interrupt Priority (within same level)
TF1 TR TF0 TR IE1 IT1 IE0 IT0
Symbol
TF1
Position
TCON.7
Name and Significance
INTERRUPT VECTOR ADDRESS
Timer 1 overflow flag. Set by hard-
ware on timer/counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
Timer 1 Run control bit. Set/cleared
by software to turn timer.counter
on/off.
Timer 0 overflow flag. Set by hard-
ware on timer/counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
Timer 0 Run control bit. Set/cleared
by software to turn timer.counter
on/off.
The processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate
servicing routine. The interrupt vector addresses are
shown in Table 4.
TR1
TF0
TCON.6
TCON.5
LEVEL/EDGE INTERRUPT
TR0
TCON.4
The external interrupt can be programmed to be either
level-activated or transition activated by setting or clearing
the IT0/1 bits in the Timer Control SFR(TCON).
Symbol
IE1
Position
TCON.3
Name and Significance
Interrupt 1 Edge flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.
ITx
Level
Edge
IT1
IE0
IT0
TCON.2
TCON.1
TCON.0
Interrupt 1 Type control bit.
Set/cleared by software to specify fall-
ing edge/low level triggered external
interrupts.
Interrupt 0 Edge flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.
Interrupt 0 Type control bit.
Set/cleared by software to specify fall-
ing edge/low level triggered external
interrupts.
0
Active low
1
INT0 = Negative Edge
INT1 = Positive and Negative Edge
Table 5 External Interrupt Activation
The external interrupt INT1 differs from the standard
80C51 in that it is activated on both edges when in edge
sensitive mode. This is to allow software pulse width
measurement for handling remote control inputs.
Fig.10 Timer/Counter Control (TCON) register
Timer/Counter
Two 16 bit timers/counters are incorporated Timer0 and
Timer1. Both can be configured to operate as either timers
or event counters.
In Timer mode, the register is incremented on every
machine cycle. It is therefore counting machine cycles.
Since the machine cycle consists of 12 oscillator periods,
the count rate is 1/12 Fosc = 1MHz.
2001 Jan 18
32
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
interrupt. Upon overflow an interrupt should also be
generated.
Reset values of all registers should be 00 hex.
In Timer mode, Timer 2 should count down from the value
set on SFRs TP2PR, TP2H and TP2L. It is therefore
counting machine cycles. Since the machine cycle
consists of 12 oscillator periods, the count rate is 1/12 fosc
(1MHz).
Gat C/T M1 M0 Gat C/T M1 M0
Timer 1 Timer 0
Gate
Gating control when set. Timer/counter is enabled only
while px_int_n is high and TR control bit is set. When
cleared timer/counter is enabled whenever TR control bit
is set.
C/T
Timer or Counter selector. Cleared for timer operation
(input from system clock). Set for counter operation (input
from T input pin.
Timer2 interval = (TP2H * 256 + TP2L) * (TP2PR + 1) * 1 us
M1 M0
Operating
0
0
1
0
1
0
8048 Timer, TL serves as 5-bit prescaler.
16-bit Timer/Counter, TL and TH are cascaded.
8-bit auto-reload Timer/Counter, TH holds a value
which is to be loaded into TL.
timer 0: two 8-bit Timers/Counters. TL0 is controlled by
timer 0 control bits. TH0 is controlled by timer 1 control
bits. timer 1: stopped.
WatchDog Timer
The WatchDog timer is a counter that once in an overflow
state forces the micro-controller in to a reset condition. The
purpose of the WatchDog timer is to reset the
micro-controller if it enters an erroneous processor state
(possibly caused by electrical noise or RFI) within a
reasonable period of time. When enabled, the WatchDog
circuitry will generate a system reset if the user program
fails to reload the WatchDog timer within a specified length
of time known as the WatchDog interval.
1
1
Fig.11 Timer/Counter Mode control (TMOD)
The Timer/Counter function is selected by control bits C/T
in the Timer Mode SFR (TMOD). These two
Timer/Counter have four operating modes, which are
selected by bit-pairs (M1.M0) in the TMOD. Refer to the
80C51 based 8-bit micro-controllers - Philips
Semiconductors (ref. IC20) for detail of the modes and
operation.
The WatchDog timer consists of an 8-bit counter with an
16-bit pre-scaler. The pre-scaler is fed with a signal whose
frequency is 1/12 fosc (1MHz).
The 8 bit timer is incremented every ‘t’ seconds where:
TL0/TL1 and TH0/TH1 are the actual timer/counter
registers for timer0 / timer1. TL0/TL1 is the low byte and
TH0/TH1 is the high byte.
t=12x65536x1/fosc=12x65536x1/12x106 = 65.536ms
WATCHDOG TIMER OPERATION
The WatchDog operation is activated when the WLE bit in
the Power Control SFR (PCON) is set. The WatchDog can
be disabled by Software by loading the value 55H into the
WatchDog Key SFR (WDTKEY). This must be performed
before entering Idle/Power Down mode to prevent exiting
the mode prematurely.
Once activated the WatchDog timer SFR (WDT) must be
reloaded before the timer overflows. The WLE bit must be
set to enable loading of the WDT SFR, once loaded the
WLE bit is reset by hardware, this is to prevent erroneous
Software from loading the WDT SFR.
TIMER WITH PRE-SCALER
An additional 16-bit timer with 8-bit pre-scaler is provided
to allow timer periods up to 16.777 seconds. This timer
remains active during IDLE mode.
TP2L sets the lower value of the period for timer 2 and
TP2H is the upper timer value. TP2PR provides an 8-bit
pre-scaler for timer 2. The value on TP2PR, TP2H and
TP2L shall never change unless updated by the software.
If the micro reads TP2R, TP2H orTP2L at any stage, this
should return the value written and not the current timer 2
value. The timer 2 should continue after overflow by
re-loading the timer with the values of SFRs TP2PR, TP2H
and TP2L.
The value loaded into the WDT defines the WatchDog
interval.
TP2CL and TP2CH indicate the current timer 2 value.
These should be readable both when the timer 2 is active
and inactive. Once the timer 2 is disable, the timer 2 value
at the time of disabling should be maintained on the SFRs
TP2CL and TP2CH. At a count of zero (on TP2CL and
TP2CH), the overflow flag should be set:- TP2CRL<1> - ’0’
= no timer 2 overflow, ’1’= timer 2 overflow.
TP2CRL is the control and status for timer 2. TP2CRL.0 is
the timer enable and TP2CRL.1 is the timer overflow
status. The overflow flag will need to be reset by software.
Hence, if required, software may poll flag rather than use
WatchDog interval = (256 - WDT) * t = (256 -WDT) * 65.536ms.
The range of intervals is from WDT=00H which gives
16.777s to WDT=FFH which gives 65.536ms.
PORT Alternate Functions
The Ports 1,2 and 3 are shared with alternate functions to
enable control of external devices and circuitry. The
alternate functions are enabled by setting the appropriate
2001 Jan 18
33
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
SFR and also writing a ‘1’ to the Port bit that the function
occupies.
instruction cycle after the SAD<7:0> value has been set.
The result of the comparison is given on VHI one
instruction cycle after the setting of ST.
PWM PULSE WIDTH MODULATORS
The device has four 6-bit Pulse Width Modulated (PWM)
outputs for analogue control of e.g. volume, balance, bass
and treble. The PWM outputs generate pulse patterns with
a repetition rate of 21.33us, with the high time equal to the
PWM SFR value multiplied by 0.33us. The analogue value
is determined by the ratio of the high time to the repetition
time, a D.C. voltage proportional to the PWM setting is
obtained by means of an external integration network (low
pass filter).
VDDP
ADC0
ADC1
ADC2
MUX
4-1
VHI
ADC3
+
CH<1:0>
-
PWM Control
8-bit
DAC
SAD<7:0>
The relevant PWM is enabled by setting the PWM enable
bit PWxE in the PWMx Control register. The high time is
defined by the value PWxV<5:0>
Fig.12 SAD Block Diagram
TPWM TUNING PULSE WIDTH MODULATOR
The device has a single 14-bit PWM that can be used for
Voltage Synthesis Tuning. The method of operation is
similar to the normal PWM except the repetition period is
42.66us.
SAD Input Voltage
The external analogue voltage that is used for comparison
with the internally generated DAC voltage, does not have
the same voltage range due to the 5 V tolerance of the pin.
It is limited to VDDP-Vtn where Vtn is a maximum of 0.75 V.
For further details refer to the SAA55XX and SAA56XX
Software Analogue to Digital Converter Application Note:
SPG/AN99022.
TPWM Control
Two SFRs are used to control the TPWM, they are TDACL
and TDACH. The TPWM is enabled by setting the TPWE
bit in the TDACH SFR. The most significant bits TD<13:7>
alter the high period between 0 and 42.33us. The 7 least
significant bits TD<6:0> extend certain pulses by a further
0.33us. e.g. if TD<6:0> = 01H then 1 in 128 periods will be
extended by 0.33us, if TD<6:0>=02H then 2 in 128 periods
will be extended.
SAD DC Comparator Mode
The SAD module incorporates a DC Comparator mode
which is selected using the ’DC_COMP’ control bit in the
SADB SFR. This mode enables the micro-controller to
detect a threshold crossing at the input to the selected
analogue input pin (P3.0, P3.1, P3.2 or P3.3) of the
Software A/D Converter. A level sensitive interrupt is
generated when the analogue input voltage level at the pin
falls below the analogue output level of the SAD D/A
converter.
The TPWM will not start to output a new value until TDACH
has been written to. Therefore, if the value is to be
changed, TACL should be written before TDACH.
SAD SOFTWARE A/D
Four successive approximation Analogue to Digital
Converters can be implemented in software by making use
of the on board 8-bit Digital to Analogue Converter and
Analogue Comparator.
This mode is intended to provide the device with a
wake-up mechanism from Power-Down or Idle when a
key-press on the front panel of the TV is detected.
The following software sequence should be used when
utilizing this mode for Power-Down or Idle:-
1. Disable INT1 using the IE SFR.
SAD Control
The control of the required analogue input is done using
the channel select bits CH<1:0> in the SAD SFR, this
selects the required analogue input to be passed to one of
the inputs of the comparator. The second comparator input
is generated by the DAC whose value is set by the bits
SAD<7:0> in the SAD and SADB SFRs. A comparison
between the two inputs is made when the start compare bit
ST in the SAD SFR is set, this must be at least one
2. Set INT1 to level sensitive using the TCON SFR.
3. Set the D/A Converter digital input level to the desired
threshold level using the SAD/SADB SFRs and select
the required input pin (P3.0, P3.1, P3.2 or P3,3) using
CH1, CH0 in the SAD SFR.
4. Enter DC Compare mode by setting the ’DC_COMP’
enable bit in the SADB SFR.
2001 Jan 18
34
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
5. Enable INT1 using the IE SFR.
‘558 fast mode’ (iic_lut=”01”)
This option accommodates the 558 I2C doubled rates as
shown below: -
6. Enter Power-Down/Idle. Upon wake-up the SAD
should be restored to its conventional operating mode
by disabling the ’DC_COMP’ control bit.
f
clk (6MHz)
I2C Serial I/O Bus
I2C Bit Frequency
(KHz) at fclk
The I2C bus consists of a serial data line (SDA) and a serial
clock line (SCL). The definition of the I2C protocol can be
found in the 80C51 based 8-bit micro-controllers - Philips
Semiconductors (ref. IC20).
CR2
CR1
CR0
divided by
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
30
800
20
200
7.5
300
400
50
The device operates in four modes: -
• Master Transmitter
15
120
1600
80
• Master Receiver
• Slave Transmitter
• Slave Receiver
3.75
75
60
100
Table 8 IIC Serial Rates ‘558 fast mode’
The micro-controller peripheral is controlled by the Serial
Control SFR (S1CON) and its Status is indicated by the
status SFR (S1STA). Information is transmitted/received
to/from the I2C bus using the Data SFR (S1DAT) and the
Slave Address SFR (S1ADR) is used to configure the
slave address of the peripheral.
‘558 slow mode’ (iic_lut=”10”)
This option accommodates the 558 I2C rates divided by 2
as shown below: -
The byte level I2C serial port is identical to the I2C serial
port on the 8xC558, except for the clock rate selection bits
CR<2:0>. The operation of the subsystem is described in
detail in the 8xC558 data sheet and can be found in the
80C51 based 8-bit micro-controllers - Philips
Semiconductors (ref. IC20).
Three different IIC selection tables for CR<2:0> can be
configured using the ROMBANK SFR (IIC_LUT<1:0>) as
follows: -
fclk (6MHz)
I2C Bit Frequency
CR2
CR1
CR0
divided by
120
(KHz) at fclk
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
3200
80
1.875
75
60
100
480
12.5
6400
320
0.9375
18.75
25
‘558 nominal mode’ (iic_lut=”00”)
This option accommodates the 558 I2C. The various serial
rates are shown below: -
240
Table 9 IIC Serial Rates ‘558 slow mode’
Note: In the above tables the fclk relates to the clock rate of
the 80c51 IIC module (6MHz).
fclk (6MHz)
I2C Bit Frequency
CR2
CR1
CR0
divided by
60
(KHz) at fclk
I2C Port Enable
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100
One external I2C port is available. This port is enabled
using TXT21.I2C PORT0. Any information transmitted to
the device can only be acted upon if the port is enabled.
Internal communication between the 80c51
1600
40
3.75
150
30
200
240
25
micro-controller and the TV Signal Processor will continue
regardless of the value written to TXT21.I2C PORT0.
3200
160
1.875
37.5
LED Support
120
50
Port pins P0.5 and P0.6 have a 8mA current sinking
capability to enable LEDs in series with current limiting
resistors to be driven directly, without the need for
additional buffering circuitry.
Table 7 IIC Serial Rates ‘558 nominal mode’
2001 Jan 18
35
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
MEMORY INTERFACE
Data Capture Features
• Video Signal Quality detector.
The memory interface controls the access to the
embedded DRAM, refreshing of the DRAM and page
clearing. The DRAM is shared between Data Capture,
Display and Microcontroller sections. The Data Capture
section uses the DRAM to store acquired information that
has been requested. The Display reads the DRAM
information and converts it to RGB output values. The
Microcontroller uses the DRAM as embedded auxiliary
RAM.
• Data Capture for 625 line WST
• Data Capture for 525 line WST
• Data Capture for US Closed Caption
• Data Capture for VPS data (PDC system A)
• Data Capture for Wide Screen Signalling (WSS) bit
decoding
• Automatic selection between 525 WST/625WST
• Automatic selection between 625WST/VPS on line 16 of
VBI
DATA CAPTURE
The Data Capture section takes in the analogue
Composite Video and Blanking Signal (CVBS) from One
Chip, and from this extracts the required data, which is
then decoded and stored in SFR memory.
• Real-time capture and decoding for WST Teletext in
Hardware, to enable optimised microprocessor
throughput
The extraction of the data is performed in the digital
domain. The first stage is to convert the analogue CVBS
signal into a digital form. This is done using an ADC
sampling at 12MHz. The data and clock recovery is then
performed by a Multi-Rate Video Input Processor
(MulVIP). From the recovered data and clock the following
data types are extracted WST Teletext (625/525),Closed
Caption, VPS, WSS. The extracted data is stored in either
memory (DRAM) via the Memory Interface or in SFR
locations.
• Up to 10 pages stored On-Chip
• Inventory of transmitted Teletext pages stored in the
Transmitted Page Table (TPT) and Subtitle Page Table
(SPT)
• Automatic detection of FASTEXT transmission
• Real-time packet 26 engine in Hardware for processing
accented, G2 and G3 characters
• Signal quality detector for WST/VPS data types
• Comprehensive Teletext language coverage
• Full Field and Vertical Blanking Interval (VBI) data
capture of WST data
Analogue to Digital Converter
The CVBS input is passed through a differential to single
ended converter (DIVIS), although in this device it is used
in single ended configuration with a reference.The
analogue output of DIVIS is converted into a digital
representation by a full flash ADC with a sampling rate of
12MHz.
Multi Rate Video Input Processor
The multi rate video input processor is a Digital Signal
Processor designed to extract the data and recover the
clock from the digital CVBS signal.
2001 Jan 18
36
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Data Standards
The data and clock standards that can be recovered are
shown in Table 10 below:-
than 09h, then data being written to TXT3 is ignored. Table
11 shows the contents of the page request RAM.
Up to 10 pages of teletext can be acquired on the 10 page
device, when TXT1.EXT PKT OFF is set to logic 1, and up
to 9 pages can be acquired when this bit is set to logic 0.
f the 'Do Care' bit for part of the page number is set to 0
then that part of the page number is ignored when the
teletext decoder is deciding whether a page being
received off air should be stored or not. For example, if the
Do Care bits for the 4 subcode digits are all set to 0 then
every subcode version of the page will be captured.
Data Standard
Clock Rate
6.9375 MHz
5.7272 MHz
5.0 MHz
625WST
525WST
VPS
WSS
5.0 MHz
Start
Column
Byte
Identification
PRD<4>
PRD<3> PRD<2> PRD<1> PRD<0>
Closed Caption
500 KHz
0
1
2
3
4
5
6
7
Magazine
Page Tens
DO CARE
DO CARE
DO CARE
DO CARE
DO CARE
DO CARE
DO CARE
x
HOLD
PT3
PU3
x
MAG2
PT2
PU2
x
MAG1
PT1
MAG0
PT0
Table 10 Data Slicing Standards
Page Units
PU1
HT1
HU1
MT1
MU1
E1
PU0
HT0
HU0
MT0
MU0
E0
Hours Tens
Hours Units
Minutes Tens
Minutes Units
Error Mode
Data Capture Timing
HU3
x
HU2
MT2
MU2
x
The Data Capture timing section uses the Synchronisation
information extracted from the CVBS signal to generate
the required Horizontal and Vertical reference timings.
The timing section automatically recognises and selects
the appropriate timings for either 625 (50Hz)
synchronisation or 525 (60Hz) synchronisation. A flag
TXT12.Video Signal Quality is set when the timing section
is locked correctly to the incoming CVBS signal. When
TXT12.Video Signal Quality is set another flag
TXT12.625/525 SYNC can be used to identify the
standard.
MU3
x
Table 11 The contents of the Page request RAM
Note: MAG = Magazine PT = Page Tens PU = Page Units
HT = Hours Tens HU = Hours Units
MT = Minutes Tens MU = Minutes Units E = Error check
mode
When the Hold bit is set to 0 the teletext decoder will not
recognise any page as having the correct page number
and no pages will be captured. In addition to providing the
user requested hold function this bit should be used to
prevent the inadvertent capture of an unwanted page
when a new page request is being made. For example, if
the previous page request was for page 100 and this was
being changed to page 234, it would be possible to capture
page 200 if this arrived after only the requested magazine
number had been changed.
The E1 and E0 bits control the error checking which should
be carried out on packets 1 to 23 when the page being
requested is captured. This is described in more detail in a
later section (‘Error Checking’).
For a multi page device, each packet can only be written
into one place in the teletext RAM so if a page matches
more than one of the page requests the data is written into
the area of memory corresponding to the lowest numbered
matching page request.
Acquisition
The acquisition sections extracts the relevant information
from the serial stream of data from the MulVIP and stores
it in memory.
625 WST ACQUISITION
The family is capable of acquiring 625-line and 525-line
World System Teletext. Teletext pages are identified by
seven numbers: magazine (page hundreds), page tens,
page units, hours tens, hours units, minutes tens and
minutes units. The last four digits, hours and minutes, are
known as the subcode, and were originally intended to be
time related, hence their names.
Making a page request
A page is requested by writing a series of bytes into the
TXT3.PRD<4:0> SFR which correspond to the number of
the page required. The bytes written into TXT3 are stored
in a RAM with an auto-incrementing address. The start
address for the RAM is set using the TXT2.SC<2:0> to
define which part of the page request is being written, and
TXT2.REQ<3:0> is used to define which of the 10 page
requests is being modified. If TXT2.REQ<3:0> is greater
At power-up each page request defaults to any page, hold
on and error check mode 0.
Rolling Headers and Time
When a new page has been requested it is conventional
for the decoder to turn the header row of the display green
2001 Jan 18
37
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
and to display each page header as it arrives until the
correct page has been found.
each of blocks 0 to 8 contains a teletext page arranged in
the same way as the basic page memory of the page
device and block 9 contains extension packets. When the
TXT1.EXT PKT OFF bit is logic 1, no extension packets
are captured and block 9 of the memory is used to store
another page. The number of the memory block into which
a page is written corresponds to the page request number
which resulted in the capture of the page.
Packet 0, the page header, is split into 2 parts when it is
written into the text memory. The first 8 bytes of the header
contain control and addressing information. They are
Hamming decoded and written into columns 0 to 7 of row
25. Row 25 also contains the magazine number of the
acquired page and the PBLF flag but the last 14 bytes are
unused and may be used by the software, if necessary.
When a page request is changed (i.e.: when the TXT3
SFR is written to) a flag (PBLF) is written into bit 5, column
9, row 25 of the corresponding block of the page memory.
The state of the flag for each block is updated every TV
line, if it is set for the current display block, the acquisition
section writes all valid page headers which arrive into the
display block and automatically writes an alpha-numerics
green character into column 7 of row 0 of the display block
every TV line.
When a requested page header is acquired for the first
time, rows 1 to 23 of the relevant memory block are
cleared to space, i.e.: have 20h written into every column,
before the rest of the page arrives. Row 24 is also cleared
if the TXT0.X24 POSN bit is set. If the TXT1.EXT PKT OFF
bit is set the extension packets corresponding to the page
are also cleared.
The last 8 characters of the page header are used to
provide a time display and are always extracted from every
valid page header as it arrives and written into the display
block
The TXT0. DISABLE HEADER ROLL bit prevents any
data being written into row 0 of the page memory except
when a page is acquired off air i.e.: rolling headers and
time are not written into the memory. The TXT1.ACQ OFF
bit prevents any data being written into the memory by the
teletext acquisition section.
Row 25 Data Contents
The Hamming error flags are set if the on-board 8/4
Hamming checker detects that there has been an
incorrectable (2 bit) error in the associated byte. It is
possible for the page to still be acquired if some of the
page address information contains incorrectable errors if
that part of the page request was a 'don't care'. There is no
error flag for the magazine number as an incorrectable
error in this information prevents the page being acquired.
The interrupted sequence (C9) bit is automatically dealt
with by the acquisition section so that rolling headers do
not contain a discontinuity in the page number sequence.
The magazine serial (C11) bit indicates whether the
transmission is a serial or a parallel magazine
transmission. This affects the way the acquisition section
operates and is dealt with automatically.
When a parallel magazine mode transmission is being
received only headers in the magazine of the page
requested are considered valid for the purposes of rolling
headers and time. Only one magazine is used even if don't
care magazine is requested. When a serial magazine
mode transmission is being received all page headers are
considered to be valid.
The newsflash (C5), subtitle (C6), suppress header (C7),
inhibit display (C10) and language control (C12 to 14) bits
are dealt with automatically by the display section,
described below.
Error Checking
The update (C8) bit has no effect on the hardware. The
remaining 32 bytes of the page header are parity checked
and written into columns 8 to 39 of row 0. Bytes which pass
the parity check have the MSB set to 0 and are written into
the page memory. Bytes with parity errors are not written
into the memory.
Before teletext packets are written into the page memory
they are error checked. The error checking carried out
depends on the packet number, the byte number, the error
check mode bits in the page request data and the TXT1.8
BIT bit.
If an incorrectable error occurs in one of the Hamming
checked addressing and control bytes in the page header
or in the Hamming checked bytes in packet 8/30, bit 4 of
the byte written into the memory is set, to act as an error
flag to the software. If incorrectable errors are detected in
any other Hamming checked data the byte is not written
into the memory.
Inventory Page
If the TXT0.INV on bit is 1, memory block 8 is used as an
inventory page. The inventory page consists of two tables,
- the Transmitted Page Table (TPT) and the subtitle page
table (SPT).
In each table, every possible combination of the page tens
and units digit, 00 to FFh, is represented by a byte. Each
bit of these bytes corresponds to a magazine number so
each page number, from 100 to 8FF, is represented by a
bit in the table.The bit for a particular page in the TPT is set
Teletext Memory Organisation
The teletext memory is divided into 2 banks of 10 blocks.
Normally, when the TXT1.EXT PKT OFF bit is logic 0,
2001 Jan 18
38
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
when a page header is received for that page. The bit in
the SPT is set when a page header for the page is received
which has the ‘subtitle’ page header control bit (C6)
set.The bit for a particular page in the TPT is set when a
page header is received for that page. The bit in the SPT
is set when a page header for the page is received which
has the ‘subtitle’ page header control bit (C6) set.
setting of the TXT1. 8 BIT bit and the error checking control
bits in the page request data and is the same as that
applied to the data written into the same memory location
in the 625 line format.
The rolling time display (the last 8 characters in row 0) is
taken from any packets X/1/1, 2 or 3 received. In parallel
magazine mode only packets in the correct magazine are
used for rolling time. Packet number X/1/0 is ignored.
The tabulation bit is also used with extension packets. The
first 8 data bytes of packet X/1/24 are used to extend the
Fastext prompt row to 40 characters. These characters are
written into whichever part of the memory the packet 24 is
being written into (determined by the ‘X24 Posn’ bit).
Packets X/0/27/0 contain 5 Fastext page links and the link
control byte and are captured, Hamming checked and
stored by in the same way as are packets X/27/0 in 625
line text. Packets X/1/27/0 are not captured.
Packet 26 Processing
One of the uses of packet 26 is to transmit characters
which are not in the basic teletext character set. The family
automatically decodes packet 26 data and, if a character
corresponding to that being transmitted is available in the
character set, automatically writes the appropriate
character code into the correct location in the teletext
memory. This is not a full implementation of the packet 26
specification allowed for in level 2 teletext, and so is often
referred to as level 1.5.
Because there are only 2 magazine bits in 525 line text,
packets with the magazine bits all set to 0 are referred to
as being in magazine 4. Therefore, the broadcast service
data packet is packet 4/30, rather than packet 8/30. As in
625 line text, the first 20 bytes of packet 4/30 contain
encoded data which is decoded in the same way as that in
packet 8/30. The last 12 bytes of the packet contains half
of the parity encoded status message. Packet 4/0/30
contains the first half of the message and packet 4/1/30
contains the second half. The last 4 bytes of the message
are not written into memory. The first 20 bytes of the each
version of the packet are the same so they are stored
whenever either version of the packet is acquired.
In 525 line text each packet 26 only contains ten 24/18
Hamming encoded data triplets, rather than the 13 found
in 625 line text. The tabulation bit is used as an extra bit
(the MSB) of the designation code, allowing 32 packet 26s
to be transmitted for each page. The last byte of each
packet 26 is ignored.
By convention, the packets 26 for a page are transmitted
before the normal packets. To prevent the default
character data over writing the packet 26 data the device
incorporates a mechanism which prevents packet 26 data
from being overwritten. This mechanism is disabled when
the Spanish national option is detected as the Spanish
transmission system sends even parity (i.e. incorrect)
characters in the basic page locations corresponding to
the characters sent via packet 26 and these will not over
write the packet 26 characters anyway. The special
treatment of Spanish national option is prevented if
TXT12. ROM VER R4 is logic 0 or if the TXT8.DISABLE
SPANISH is set.
Packet 26 data is processed regardless of the TXT1. EXT
PKT OFF bit, but setting theTXT1.X26 OFF disables
packet 26 processing.
The TXT8. Packet 26 received bit is set by the hardware
whenever a character is written into the page memory by
the packet 26 decoding hardware. The flag can be reset by
writing a 0 into the SFR bit.
FASTEXT DETECTION
When a packet 27, designation code 0 is detected,
whether or not it is acquired, the TXT13. FASTEXT bit is
set. If the device is receiving 525 line teletext, a packet
X/0/27/0 is required to set the flag. The flag can be reset
by writing a 0 into the SFR bit.
525 WST
The 525 line format is similar to the 625 line format but the
data rate is lower and there are less data bytes per packet
(32 rather than 40). There are still 40 characters per
display row so extra packets are sent each of which
contains the last 8 characters for four rows. These packets
can be identified by looking at the ‘tabulation bit’ (T), which
replaces one of the magazine bits in 525 line teletext.
When an ordinary packet with T = 1 is received, the
decoder puts the data into the four rows starting with that
corresponding to the packet number, but with the 2 LSBs
set to 0. For example, a packet 9 with T = 1 (packet X/1/9)
contains data for rows 8, 9, 10 and 11. The error checking
carried out on data from packets with T = 1 depends on the
BROADCAST SERVICE DATA DETECTION
When a packet 8/30 is detected, or a packet 4/30 when the
device is receiving a 525 line transmission, the TXT13.
Packet 8/30. The flag can be reset by writing a 0 into the
SFR bit.
VPS ACQUISITION
When the TXT0. VPS ON bit is set, any VPS data present
on line 16, field 0 of the CVBS signal at the input of the
2001 Jan 18
39
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
teletext decoder is error checked and stored in row 25,
block 9 of the basic page memory. The device
automatically detects whether teletext or VPS is being
transmitted on this line and decodes the data
appropriately.
DISPLAY
The display section is based on the requirements for a
Level 1.5 WST Teletext and US Closed Caption. There are
some enhancements for use with locally generated
On-Screen Displays.
The display section reads the contents of the Display
memory and interprets the control/character codes. Using
this information and other global settings, the display
produces the required RGB signals and Video/Data (Fast
Blanking) signal for the TV signal processing.
The display is synchronised to the TV signal processing by
way of Horizontal and Vertical sync signals generated
within TDA935X/6x/8x. From these signals all display
timings are derived.
column
0
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Teletext page
header data
VPS
VPS
VPS
VPS
VPS
VPS
byte 4
VPS
byte 5
row 25
byte 14 byte 15
byte 11 byte 12 byte 13
Fig.13 VPS Data Storage
Each VPS byte in the memory consists of 4 bi-phase
decoded data bits (bits 0-3), a bi-phase error flag (bit 4)
and three 0s (bits5-7). The TXT13. VPS Received bit is set
by the hardware whenever VPS data is acquired. The flag
can be reset by writing a 0 into the SFR bit.
Display Features
• Teletext and Enhanced OSD modes
• Level 1.5 WST features
• US Closed Caption Features
• Serial and Parallel Display Attributes
WSS ACQUISITION
The Wide Screen Signalling data transmitted on line 23
gives information on the aspect ratio and display position
of the transmitted picture, the position of subtitles and on
the camera/film mode. Some additional bits are reserved
for future use. A total of 14 data bits are transmitted. All of
the available data bits transmitted by the Wide Screen
Signalling signal are captured and stored in SFRs WSS1,
WSS2 and WSS3. The bits are stored as groups of related
bits and an error flag is provided for each group to indicate
when a transmission error has been detected in one or
more of the bits in the group. Wide screen signalling data
is only acquired when the TXT8.WSS ON bit is set. The
TXT8.WSS RECEIVED bit is set by the hardware
whenever wide screen signalling data is acquired. The flag
can be reset by writing a 0 into the SFR bit.
• Single/Double/Quadruple Width and Height for
characters
• Scrolling of display region.
• Variable flash rate controlled by software.
• Globally selectable scan lines per row 9/10/13/16.
• Globally selectable character matrix (HxV) 12x9, 12x10,
12x13, 12x16.
• Italics, Underline and Overline.
• Soft Colours using CLUT with 4096 colour palette.
• Fringing (Shadow) selectable from N-S-E-W direction.
• Fringe colour selectable.
• Meshing of defined area.
• Contrast reduction of defined area.
• Cursor.
CLOSED CAPTION ACQUISITION
The US Closed Caption data is transmitted on line 21 (525
line timings) and is used for Captioning information, Text
information and Extended Data Services. Closed Caption
data is only acquired when TXT21.CC ON bit is set.
Two bytes of data are stored per field in SFRs, the first bye
is stored in CCDAT1 and the second byte is stored in
CCDAT2. The value in the CCDAT registers are reset to
00h at the start of the Closed Caption line defined by
CCLIN.CS<4:0>. At the end of the Closed Caption line an
interrupt is generated if IE.ECC is active.
• Special Graphics characters with two planes, allowing
four colours per character.
• 32 Software re-definable On-Screen Display characters.
• 4 WST Character sets(G0/G2) in single device (e.g.
Latin,Cyrillic,Greek,Arabic).
• G1 Mosaic graphics, Limited G3 Line drawing
characters.
• WST Character sets and Closed Caption Character set
in single device.
The processing of the Closed Caption data to convert into
a displayable format is performed by Software.
Display Modes
The display section has two distinct modes with different
features available in each. The two modes are:
2001 Jan 18
40
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
• TXT:This is the display configured as the WST mode
with additional serial and global attributes to enable
the same functionality as the SAA5497 (ETT)
device.The display is configured as a fixed 25 rows
with 40 characters per row.
Display Features available in each mode
The following is a list of features available in each mode.
Each setting can either be a serial or parallel attribute, and
some have a global effect on the display.
• CC:This is the display configured as the US Closed
Caption mode with the same functionality as the
PC83C771 device. The display is configured as a
maximum of 16 rows with a maximum of 48
characters per row.
Feature
Flash
TXT
CC
serial
serial
Boxes
Txt/OSD (Serial)
x1/x2/x4 (serial)
serial
Horizontal Size
Vertical Size
x1/x2 (serial)
x1/x2 (serial)
In both of the above modes the Character matrix, and TV
lines per row can be defined. There is an option of 9, 10,
13 & 16 TV lines per display row, and a Character matrix
(HxV) of 12x9, 12x10, 12x13, or 12x16. Not all
combinations of TV lines per row and maximum display
rows give a sensible OSD display, since there is limited
number of TV scan lines available.
x1/x2 (serial)
x4 (global)
Italic
N/A
serial
Foreground
colours
8 (serial)
8+8 (parallel)
Special Function Register, TXT21 is used to control the
character matrix and lines per row.
Background
colours
8 (serial)
16 (serial)
Soft Colours
(CLUT)
16 from 4096
16 from 4096
Underline
Overline
N/A
serial
serial
N/A
Fringe
N+S+E+W
16 (Global)
N+S+E+W
16 (Serial)
All (Global)
Fringe Colour
Meshing of
Background
Black or Colour
(Global)
Fast Blanking
Polarity
YES
YES
Screen Colour
DRCS
16 (Global)
32 (Global)
16 (Global)
32 (Global)
Character Matrix
(HxV)
12x9/10/13/16
12x9/10/13/16
No. of Rows
25
40
16
48
No. of Columns
No of Characters
displayable
1000
768
Cursor
YES
16
YES
16
Special Graphics
(2 planes per
character)
Scroll
NO
YES
Table 12 Display Features
2001 Jan 18
41
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Display Feature Descriptions
the ‘double width’ or double size (0Eh/BEh/0Fh/BFh)
enables double width characters. Any two consecutive
combination of ‘double width’ or ‘double size’
FLASH
Flashing causes the foreground colour pixel to be
displayed as the background pixels.The flash frequency is
controlled by software setting and resetting display
register REG0: Status at the appropriate interval.
CC: This attribute is valid from the time set (see Table 18)
until the end of the row or until otherwise modified.
TXT: This attribute is set by the control character ‘flash’
(08h) and remains valid until the end of the row or until
reset by the control character ‘steady’ (09h).
(0Eh/BEh/0Fh/Bfh) activates quadruple width characters,
provided quadruple width characters are enabled by
TXT4.Quad Width Enable. Three vertical sizes are
available normal(x1),double(x2),quadruple(x4). The
control characters ‘normal size’ (0Ch/BCh) enable normal
size, the ‘double height’ or ‘double size’
(0Dh/BDh/0Fh/BFh) enable double height characters.
Quadruple height character are achieved by using double
height characters and setting the global attributes
TXT7.Double Height (expand) and TXT7.Bottom/Top.
If double height characters are used in teletext mode,
single height characters in the lower row of the double
height character are automatically disabled.
BOXES
CC: This attribute is valid from the time set until end of row
or otherwise modified if set with Serial Mode 0. If set with
Serial Mode 1, then it is set from the next character
onwards.
ITALIC
In CC text mode the background colour is displayed
regardless of the setting of the box attribute bit. Boxes take
affect only during mixed mode, where boxes are set in this
mode the background colour is displayed. Character
locations where boxes are not set show video/screen
colour (depending on the setting in the display control
register. REG0: Display Control) in stead of the
background colour.
CC: This attribute is valid from the time set until the end of
the row or otherwise modified. The attribute causes the
character foreground pixels to be offset horizontally by 1
pixel per 4 scan lines (interlaced mode). The base is the
bottom left character matrix pixel. The pattern of the
character is indented as shown in Fig.14.
TXT: Two types of boxes exist the Teletext box and the
OSD box. The Teletext box is activated by the ‘start box’
control character (0Bh), Two start box characters are
required begin a Teletext box, with box starting between
the 2 characters. The box ends at the end of the line or
after a ‘end box’ control character.
TXT mode can also use OSD boxes, they are started using
size implying OSD control chracters(BCh/BDh/BEh/BFh).
The box starts after the control character (‘set after’) and
ends either at the end of the row or at the next size
implying OSD character (‘set at’). The attributes flash,
teletext box, conceal, separate graphics, twist and hold
graphics are all reset at the start of an OSD box, as they
are at the start of the row. OSD Boxes are only valid in TV
mode which is defined by TXT5=03h and TXT6=03h.
SIZE
The size of the characters can be modified in both the
horizontal and vertical directions.
CC: Two sizes are available in both the horizontal and
vertical directions. The sizes available are normal (x1),
double (x2) height/width and any combination of these.
The attribute setting is always valid for the whole row.
Mixing of sizes within a row is not possible.
TXT: Three horizontal sizes are available
normal(x1),double(x2),quadruple(x4). The control
characters ‘normal size’ (0Ch/BCh) enables normal size,
2001 Jan 18
42
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
TXT: The Italic attribute is not available.
12x13 character matrix
12x16 character matrix
12x10 character matrix
0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10
0 2 4 6 8 10 0 2 4 6 8 10
0
1
Indented by 7/6/4
Indented by 6/5/3
Indented by 5/4/2
Indented by 4/3/1
Indented by 3/2/0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Indented by 2/1
Indented by 1/0
Indented by 0
Field 1
Field 2
Fig.14 Italic Characters (12x10, 12x13 & 12x16).
TXT: The foreground colour is selected via a control
character. The colour control characters takes effect at the
start of the next character (“Set-After”) and remain valid
until the end of the row, or until modified by a control
character. Only 8 foreground colours are available.
The TEXT foreground control characters map to the CLUT
entries as shown below:
COLOURS
CLUT (Colour Look Up Table)
A CLUT (Colour Look Up Table) with 16 colour entries is
provided. The colours are programmable out of a palette
of 4096(4 bits per R, G and B). The CLUT is defined by
writing data to a RAM that resides in the MOVX address
space of the 80C51.
Control Code
Defined Colour
Black
CLUT Entry
00h
01h
02h
03h
04h
05h
06h
07h
0
1
2
3
4
5
6
7
RED3-0
b11. . .b4
GRN3-0
b7. . .b4
BLU3-0
b3. . .b0
Colour
entry
Red
Green
0 0 0 0
0 0 0 0
...
0 0 0 0
0 0 0 0
...
0 0 0 0
1 1 1 1
...
0
1
Yellow
Blue
...
14
15
Magenta
Cyan
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 0 0
1 1 1 1
White
Table 13 CLUT Colour values
Foreground Colour
CC: The foreground colour can be chosen from 8 colours
on a character by character basis. Two sets of 8 colours
are provided. A serial attribute switches between the
banks (see Table 18 Serial Mode 1, bit 7). The colours are
the CLUT entries 0 to 7 or 8 to 15.
Table 14 Foreground CLUT mapping
Background Colour
CC: This attribute is valid from the time set until end of row
or otherwise modified if set with Serial Mode 0. If set with
Serial Mode 1, then the colour is set from the next
character onwards.
The background colour can be chosen from all 16 CLUT
entries.
2001 Jan 18
43
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
TXT: The control character “New background” (“1Dh”) is
used to change the background colour to the current
foreground colour. The selection is immediate (“Set at”)
and remains valid until the end of the row or until otherwise
modified.
CC: The overline attribute (see Table 18, Serial Mode 0/1,
bit 5) is valid from the time set until end of row or otherwise
modified. Overlining of Italic characters is not possible.
TXT: This attribute is not available.
The TEXT background control characters map to the
CLUT entries as shown below:
END OF ROW
CC: The number of characters in a row is flexible and can
determined by the end of row attribute (see Table 18,
Serial Mode 1, bit 9). However the maximum number of
character positions displayed is determined by the setting
of the REG2:Text Position Horizontal and REG4:Text Area
End.
NOTE: When using the end of row attribute the next
character location after the attribute should always be
occupied by a ’space’.
Control Code
00h+1Dh
01h+1Dh
02h+1Dh
03h+1Dh
04h+1Dh
05h+1Dh
06h+1Dh
07h+1Dh
Defined Colour
Black
CLUT Entry
8
Red
9
Green
10
11
12
13
14
15
TXT: This attribute is not available, Row length is fixed at
40 characters.
Yellow
Blue
Magenta
Cyan
FRINGING
A fringe (shadow) can be defined around characters. The
fringe direction is individually selectable in any of the
North, South, East and West direction using
REG3:Fringing Control. The colour of the fringe can also
be defined as one of the entries in the CLUT, again using
REG3:Fringing Control.
CC: The fringe attribute (see Table 18, Serial Mode 0, bit
9) is valid from the time set until the end of the row or
otherwise modified.
TXT: The display of fringing in TXT mode is controlled by
the TXT4.SHADOW bit. When set all the alphanumeric
characters being displayed are shadowed, graphics
characters are not shadowed.
White
Table 15 Background CLUT mapping
BACKGROUND DURATION
The attribute when set takes effect from the current
position until to the end of the text display defined in
REG4:Text Area End.
CC: The background duration attribute (see Table 18,
Serial Mode 1, bit 8) in combination with the End Of Row
attribute (see Table 18, Serial Mode 1, bit 9) forces the
background colour to be display on the row until the end of
the text area is reached.
TXT: This attribute is not available.
UNDERLINE
The underline attribute causes the characters to have the
bottom scan line of the character cell forced to foreground
colour, including spaces. If background duration is set,
then underline is set until the end of the text area.
CC: The underline attribute (see Table 18, Serial Mode
0/1, bit 4) is valid from the time set until end of row or
otherwise modified.
TXT: This attribute is not available.
OVERLINE
Fig.15 South and Southwest Fringing
The overline attribute causes the characters to have the
top scan line of the character cell forced to foreground
colour, including spaces. If background duration is set,
then overline is set until the end of the text area.
MESHING
The attribute effects the background colour being
displayed. Alternate pixels are displayed as the
background colour or video.The structure is offset by 1
2001 Jan 18
44
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
pixel from scan line to scan line, thus achieving a checker
board display of the background colour and video.
TXT: There are two meshing attributes one that only
affects black background colours TXT4.BMESH and a
second that only affects backgrounds other than black
TXT4.CMESH. A black background is defined as CLUT
entry 8, a none black background is defined as CLUT entry
9-15.
SPECIAL GRAPHICS CHARACTERS
CC/TXT: Several special characters are provided for
improved OSD effects. These characters provide a choice
of 4 colours within a character cell. The total number of
special graphics characters is limited to 16. They are
stored in the character codes 8Xh and 9Xh of the character
table (32 ROM characters), or in the DRCs which overlay
character codes 8Xh and 9Xh. Each special graphics
character uses two consecutive normal characters.
Fringing, underline and overline is not possible for special
graphics characters. Special graphics characters are
activated when TXT21.OSD_PLANE = 1.
CC: The setting of the Mesh bit in REG0:Display Control
has the effect of meshing any background colour.
Background Colour
“set at” (Mode 0)
Serial Attribute
Background Colour
“set after” (Mode 1)
VOLUME
Foreground Colour
Normal Character
Background Colour
Foreground Colour 7
Foreground Colour 6
Special Character
Fig.16 Meshing and Meshing / Fringing (South+West)
Fig.18 Special Character Example
CURSOR
The example in Fig.18 can be done with 8 special graphics
characters.
The cursor operates by reversing the background and
foreground colours in the character position pointed to by
the active cursor position. The cursor is enabled using
TXT7.CURSOR ON. When active, the row the cursor
appears on is defined by TXT9.R<4:0> and the column is
defined by TXT10.C<5:0>. The position of the cursor can
be fixed using TXT9.CURSOR FREEZE.
If the screen colour is transparent (implicit in mixed mode)
and inside the object the box attribute is set, then the
object is surrounded by video. If the box attribute is not set
the background colour inside the object will also be
displayed as transparent.
CC: The valid range for row is 0 to 15. The valid range for
column is 0 to 47. The cursor remains rectangular at all
times, it’s shape is not affected by italic attribute, therefore
it is not advised to use the cursor with italic characters.
TXT: The valid range for row positioning is 0 to 24.The
valid range for column is 0 to 39.
Plane
1 0
Colour Allocation
0 0
0 1
1 0
1 1
Background Colour
Foreground Colour
CLUT entry 6
CLUT entry 7
A B C D E F
Table 16 Special Character Colour allocation
Fig.17 Cursor Display
2001 Jan 18
45
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Character and Attribute Coding
CC MODE
Character coding is split into character oriented attributes (parallel) and character group coding (serial). The serial
attributes take effect either at the position of the attribute (Set At), or at the following location (Set After) and remain
effective until either modified by a new serial attribute or until the end of the row. A serial attribute is represented as a
space (the space character itself however is not used for this purpose), the attributes that are still active, e.g. overline
and underline will be visible during the display of the space. The default setting at the start of a row is:
• 1x size, flash and italics OFF
• overline and underline OFF
• Display mode = superimpose
• fringing OFF
• background colour duration = 0
• end of row = 0
The coding is done in 12 bit words. The codes are stored sequentially in the display memory. A maximum of 768
character positions can be defined for a single display.
PARALLEL CHARACTER CODING
Bits
0-7
8-10
11
Description
8 bit character code
3 bits for 8 foreground colours
Mode bit:
0 = Parallel code
Table 17 Parallel Character Coding
2001 Jan 18
46
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
SERIAL CHARACTER CODING
Bits
Description
Serial Mode 0
(“set at”)
Serial Mode 1
Char.Pos. 1 (“set at”)
Char.Pos. >1 (“set after”)
0-3
4
4 bits for 16 Background
colours
4 bits for 16 Background colours
4 bits for 16 Background colours
0 = Underline OFF
1 = Underline ON
Horizontal Size:
0 = normal
1 = x2
0 = Underline OFF
1 = Underline ON
5
6
7
8
0 = Overline OFF
1 = Overline ON
Vertical Size:
0 = normal
1 = x2
0 = Overline OFF
1 = Overline ON
Display mode:
0 = Superimpose
1 = Boxing
Display mode:
0 = Superimpose
1 = Boxing
Display mode:
0 = Superimpose
1 = Boxing
0 = Flash OFF
1 = Flash ON
Foreground colour switch
0 = Bank 0 (colours 0-7)
1 = Bank 1 (colours 8-15)
Foreground colour switch
0 = Bank 0 (colours 0-7)
1 = Bank 1 (colours 8-15)
0 = Italics OFF
1 = Italics ON
Background colour duration:
0 = stop BGC
Background colour duration
(set at):
1 = set BGC to end of row
0 = stop BGC
1 = set BGC to end of row
9
0 = Fringing OFF
1 = Fringing ON
End of Row
0 = Continue Row
1 = End Row
End of Row (set at):
0 = Continue Row
1 = End Row
10
Switch for Serial coding
mode 0 and 1:
Switch for Serial coding mode 0
and 1:
Switch for Serial coding mode 0
and 1:
0 = mode 0
Mode bit:
1 = mode 1
Mode bit:
1 = mode 1
Mode bit:
11
1 = Serial code
1 = Serial code
1 = Serial code
Table 18 Serial Character Coding
(Set At), or at the following location (Set After). The
attribute remainseffective until either modified by new
serial attributes or until the end of the row.The default
settings at the start of a row is:
TXT MODE
Character coding is in a serial format, with only one
attributes being changed at any single location. The serial
attributes take effect either at the position of the attribute
• foreground colour white (CLUT Address 7)
• background colour black (CLUT Address 8)
2001 Jan 18
47
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
• Horizontal size x1, Vertical size x1 (normal size)
• Alphanumeric ON
• Contiguous Mosaic Graphics
• Release Mosaics
• Flash, Box, Conceal and Twist OFF
The attributes have individual codes which are defined in the basic character table below:
E/W = 0
E/W = 1
b7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
b6
b5
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
0
0
0
1
0
0
1
1
1
1
0
0
0
bits
0
1
1
0
1
1
b4
1
0
1
0
0
1
0
1
1
1
0
0
1
1
0
1
1
0
1
0
b3 b2 b1 b0
column0
1
2 2a 3 3a 4 5 6 6a 7 7a 8 8a
9 9a
D E F
D E F
B C
A
O
O
O
graphics
black
graphics
red
graphics
green
graphics
yellow
graphics
blue
graphics
magenta
graphics
cyan
graphics
white
alpha
Nat
Opt
O
Nat
Opt
bkgnd
black
bkgnd
red
S
S
S
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
S
0
black
alpha
red
alpha
green
alpha
yellow
alpha
blue
alpha
magenta
alpha
cyan
D
D
D
D
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
S
S
S
S
1
D
D
D
D
O
O
bkgnd
green
bkgnd
yellow
bkgnd
blue
bkgnd
magenta
bkgnd
cyan
bkgnd
white
S
S
S
S
2
D
D
D
D
O
O
O
O
O
O
Nat
Opt
S
S
S
S
3
D
D
D
D
O
Nat
Opt
S
S
S
S
4
D
D
D
D
O
S
S
S
S
5
D
D
D
D
O
S
S
S
S
6
D
D
D
D
O
alpha
white
S
S
S
S
7
D
D
D
D
conceal
display
contiguous
graphics
separated
graphics
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
flash
S
S
S
S
8
D
D
D
D
O
steady
S
S
S
S
9
D
D
D
D
O
end
box
start
box
normal
height
double
height
double
width
double
size
S
S
S
S
A
B
C
D
E
F
D
D
D
D
O
Nat
Opt
Nat
Opt
S
twist
S
S
S
D
D
D
D
O
black
bkgnd
new
bkgnd
hold
graphics
release
graphics
Nat
Opt
norm sz
OSD
dbl ht
OSD
dbl wd
OSD
dbl sz
OSD
Nat
Opt
S
S
S
S
D
D
D
D
O
Nat
Opt
Nat
Opt
S
S
S
S
D
D
D
D
O
O
O
O
Nat
Opt
Nat
Opt
S
S
S
S
D
D
D
D
O
O
O
O
Nat
Opt
S
S
S
S
D
D
D
D
Fig.19 TXT Basic Character Set (Pan-European)
2001 Jan 18
48
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Screen and Global Controls
DISPLAY MODES
A number of attributes are available that affect the whole
display region, and cannot be applied selectively to
regions of the display.
CC: When attributes superimpose or when boxing (see
Table 18, Serial Mode 0/1, bit 6) is set, the resulting display
depends on the setting of the following screen control
mode bits in REG0:Display Control.
TV SCAN LINES PER ROW
The number of TV scan lines per field used for each
display row can be defined, the value is independent of the
character size being used. The number of lines can be
either 10/13/16 per display row. The number of TV scan
lines per row is defined TXT21.DISP_LINES<1:0>.
A value of 9 lines per row can be achieved if the display is
forced into 525 line display mode by
TXT17.DISP_FORCE<1:0>, or if the device is in 10 line
mode and the automatic detection circuitry within display
finds 525 line display syncs.
Display Mode
Video
MOD
1 0
Description
0 0
Video mode disables all display
activities and sets the RGB to true
black and VDS to video.
Full Text
0 1
Full Text mode displays screen
colour at all locations not covered by
character foreground or background
colour. The box attribute has no
effect.
CHARACTER MATRIX (HXV)
Mixed Screen
Colour
1 0
1 1
Mixed Screen mode displays screen
colour at all locations not covered by
character foreground, within boxed
areas or, background colour.
There are four different character matrices available, these
are 12x10, 12x13, and 12x16. The selection is made using
TXT21.CHAR_SIZE<1:0> and is independent of the
number of display lines per row.
If the character matrix is less than the number of TV scan
lines per row then the matrix is padded with blank lines. If
the character matrix is greater than the number of TV scan
lines then the character is truncated.
Mixed Video
Mixed Video mode displays video at
all locations not covered by
character foreground, within boxed
areas or, background colour.
Table 19 Display Modes
TXT: The display mode is controlled by the bits in the TXT5
and TXT6. There are 3 control functions - Text on,
Background on and Picture on. Separate sets of bits are
used inside and outside Teletext boxes so that different
display modes can be invoked. TXT6 is used if the
newsflash (C5) or subtitle (C6) bits in row 25 of the basic
page memory are set otherwise TXT5 is used. This allows
the software to set up the type of display required on
newsflash and subtitle pages (e.g. text inside boxes, TV
picture outside) this will be invoked without any further
software intervention when such a page is acquired.
Background
Picture On
Text On
Effect
On
0
0
0
1
1
1
0
1
1
0
1
1
x
Text mode, black screen
Text mode, background always black
Text mode
0
1
x
Video mode
0
Mixed text and TV mode
Text mode, TV picture outside text area
1
Table 20 TXT Display Control Bits
2001 Jan 18
49
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Screen Colour
Screen colour is displayed from 10.5 ms to 62.5 ms after
the active edge of the HSync input and on TV lines 23 to
310 inclusive, for a 625 line display, and lines 17 to 260
inclusive for a 525 line display.
The screen colour is defined by REG0:Display Control and
points to a location in the CLUT table. The screen colour
covers the full video width. It is visible when the Full Text
or Mixed Screen Colour mode is set and no foreground or
background pixels are being displayed.
Display Memory
Text Area
ROW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Display
possible
Soft Scrolling
display possible
10
11
12
13
14
15
Text Display Controls
Display
possible
TEXT DISPLAY CONFIGURATION
Two types of area are possible. The one area is static and
the other is dynamic. The dynamic area allows scrolling of
a region to take place. The areas cannot cross each other.
Only one scroll region is possible.
Display Map
The display map allows a flexible allocation of data in the
memory to individual rows.
Sixteen words are provided in the display memory for this
purpose. The lower 10 bits address the first word in the
memory where the row data starts. This value is an offset
in terms of 16-bit words from the start of Display Memory
(8000 Hex). The most significant bit enables the display
Fig.20 Display Map and Data Pointers
when not within the scroll (dynamic) area.
SOFT SCROLL ACTION
The display map memory is fixed at the first 16 words in
the closed caption display memory.
The dynamic scroll region is defined by the REG5:Scroll
Area, REG6:Scroll Range, REG14:Top Scroll line and the
REG8:Status Register. The scroll area is enabled when
the SCON bit is set in REG8: Status.
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Pointer to Row Data
The position of the soft scroll area window is defined using
the Soft Scroll Position (SSP<3:0), and the height of the
window is defined using the Soft Scroll Height (SSH<3:0>)
both are in REG6:Scroll Range. The rows that are scrolled
through the window are defined using the Start Scroll Row
(STS<3:0>) and the Stop Scroll Row (SPS<3:0>) both are
in REG5:Scroll Area.
Reserved, should be set to 0
Text Display Enable, valid outside Soft Scroll Area
0 = Disable
1 = Enable
Table 21 Display map Bit Allocation
The soft scrolling function is done by modifying the Scroll
Line (SCL<3:0>) in REG14: Top Scroll Line. and the first
scroll row value SCR<3:0> in REG8:Status. If the number
of rows allocated to the scroll counter is larger than the
defined visible scroll area, this allows parts of rows at the
top and bottom to be displayed during the scroll function.
The registers can be written throughout the field and the
values are updated for display with the next field sync.
Care should be taken that the register pairs are written to
by the software in the same field.
Only a region that contains only single height rows or only
double height rows can be scrolled.
2001 Jan 18
50
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
ROW
0
1
2
Horizontal Sync.
Usable for OSD Display
Start Scroll Row
STS<3:0> e.g. 3
Vertical
Sync.
6 Lines
Offset
Screen Colour Offset = 8µs
Should not be used for
OSD Display
3
4
5
6
Soft Scroll Position
Pointer SSP<3:0> e.g. 6
Screen Colour Area
Soft Scroll Height
SSH<3:0> e.g.4
7
8
9
10
11
12
13
14
15
Soft Scrolling Area
Text
Vertical
Offset
H-Sync delay
Text Area
Should not be used for
OSD Display
Stop Scroll Row
SPS<3:0> e.g. 11
Usable for OSD Display
0.25 char. offset
Fig.21 Soft Scroll Area
Text Area Start
Text Area End
56µs
Fig.23 Display Area Positioning
0-63 lines
ROW
0
row0
1
2
3
4
5
row1
P01 NBC
SCREEN COLOUR DISPLAY AREA
row2
row3
row4
Scroll Area
Offset
This area is covered by the screen colour. The screen
colour display area starts with a fixed offset of 8 us from
the leading edge of the horizontal sync pulse in the
horizontal direction. A vertical offset is not necessary.
row5
row6
row7
row8
6
7
8
9
Closed Captioning data row n
Closed Captioning data row n+1
Closed Captioning data row n+2
Closed Captioning data row n+3
10
11
12
13
14
15
Visible area
for scrolling
Horizontal
Vertical
starts 8 us after the leading edge of H-Sync for 56
us.
Closed Captioning data row n+4
row13
row14
line 9, field 1 (321, field 2) with respect to leading
edge of vertical sync (line numbering using 625
Standard).
Fig.22 CC Text Areas
Table 22 Screen Colour Display Area
Display Positioning
TEXT DISPLAY AREA
The display consists of the Screen Colour covering the
whole screen and the Text Area that is placed within the
visible screen area. The screen colour extends over a
large vertical and horizontal range so that no offset is
needed. The text area is offset in both directions relative to
the vertical and horizontal sync pulses.
The text area can be defined to start with an offset in both
the horizontal and vertical direction.
Horizontal
Up to 48 full sized characters per row.
Start position setting from 3 to 64 characters from
the leading edge of H-Sync. Fine adjustment in
quarter characters.
Vertical
256 lines (nominal 41- 297).
Start position setting from leading edge of vertical
sync legal values are 4 to 64 lines.
(line numbering using 625 Standard)
Table 23 Text Display Area
The horizontal offset is set in REG2: Text Area Start. The
offset is done in full width characters using TAS<5:0> and
quarter characters using HOP<1:0> for fine setting. The
2001 Jan 18
51
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
values 00h to 03h for TAS<5:0> will result in a corrupted
display.
ROM ADDRESSING
Three ROM’s are used to generate the correct pixel
information. The first contains the National Option look-up
table, the second contains the Basic Character look-up
table and the third contains the Character Pixel
information. Although these are individual ROM, since
they do not need to be accessed simultaneously they are
all combined into a single ROM unit.
The width of the text area is defined in REG4:Text Area
End by setting the end character value TAE<5:0>. This
number determines where the background colour of the
Text Area will end if set to extend to the end of the row. It
will also terminate the character fetch process thus
eliminating the necessity of a row end attribute. This
entails however writing to all positions.
2400H
The vertical offset is set in REG1:Text Position Vertical
Register. The offset value VOL<5:0> is done in number of
TV scan lines.
CHAR PIXEL
DATA
0800
71680 x 12 bits
NOTE: REG1:Text Position Vertical Register should not
be set to 00 Hex as the Display Busy interrupt is not
generated in these circumstances.
Look-Up Set3
Approx. 710 Text
or
0600
0400
0200
0000
430Text +176CC
Look-Up Set2
Look-Up Set1
Look-Up Set 0
Character Set
To facilitate the global nature of the device the character
set has the ability to accommodate a large number of
characters, which can be stored in different matrices.
0800H
0000H
LOOK-UP
Basic + Nat Opt
2048 location
CHARACTER MATRICES
The character matrices that can be accommodated are: -
(HxVxPlanes) 12x9x1, 12x10x1, 12x13x1, 12x16x1.
These modes allow two colours per character position.
In CC mode two additional character matrices are
available to allow four colours per character: -
(HxVxPlanes) 12x13x2, 12x16x2.
Fig.24 ROM Organisation
The characters are stored physically in ROM in a matrix of
size either 12x10 or 12x16.
CHARACTER SET SELECTION
Four character sets are available in the device. A set can
consist of alphanumeric characters as required by the
WST Teletext or FCC Closed Captioning, Customer
definable On-Screen Display characters, and Special
Graphic characters.
CC:- Only a single character set can be used for display
and this is selected using the Basic Set selection
TXT18.BS<1:0>. When selecting a character set in CC
mode the Twist Set selection TXT18.TS<1:0> should be
set to the same value as TXT18.BS<1:0> for correct
operation.
TXT:- Two character sets can be displayed at once. These
are the basic G0 set or the alternative G0 set (Twist Set).
The basic set is selected using TXT18.BS<1:0>, The
alternative/twist character set is defined by
TXT19.TS<1:0>. Since the alternative character set is an
option it can be enabled or disabled using TXT19.TEN,
and the language code that is defined for the alternative
set is defined by TXT19.TC<2:0>.
2001 Jan 18
52
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
CHARACTER TABLE
The character table is shown in Table 24:-
Character code columns (Bits 4-7)
0
1
®
˚
2
SP
!
3
0
1
2
3
4
5
6
7
8
9
:
4
@
A
B
C
D
E
F
5
P
Q
R
S
6
ú
a
b
c
7
p
q
r
8
9
A
B
C
D
E
F
0
1
2
1/2
¿
"
#
$
%
&
´
3
s
4
™
¢
T
U
V
W
X
Y
Z
[
d
e
t
5
u
v
w
x
y
z
6
£
f
7
G
H
I
g
h
i
8
à
_
è
â
ê
î
(
9
)
A
B
C
D
E
F
á
+
,
J
j
;
K
L
M
N
O
k
l
ç
<
=
>
?
é
-
]
m
n
o
Ñ
ñ
n
ô
û
.
í
/
ó
Table 24 Closed Caption Character Table
Special Characters are in column 8.
Additional table locations for normal characters
Table locations for normal characters
Re-definable Characters
A number of Dynamically Re-definable Characters (DRC) are available. These are mapped onto the normal character
codes, and replace the pre-defined OTP character Rom value.
There are 32 DRCs which occupy character codes 80H to 9FH. Alternatively, These locations can be utilized as 16
special graphics characters. The remapping of the standard OSD to the DRCs is activated when the TXT21.DRCS
ENABLE bit is set. The selection of Normal or Special OSD symbols is defined by the TXT21.OSD PLANES.
Each character is stored in a matrix of 16x16x1 (V x H x planes), this allows for all possible character matrices to be
defined within a single location.
2001 Jan 18
53
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
DRCs are defined by writing data to the DRC RAM using
the 80C51 MOVX command. Setting bits 3 to 9 of the first
line of a 12 wide by 16 line character would require setting
the high byte of the 80C51 data pointer to 88H, the low
byte of the 80C51 data pointer to 00H, using the MOVX
command to load address 8800H with data F8H,
Micro Address
8800
Char Code
80h
CHAR 0
CHAR 1
CHAR 0
A
12 bits
Address
881F
8820
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
81h
82h
883F
8840
CHAR 2
incrementing the data pointer, and finally using the MOVX
command to load address 8801H with data 03H.
885F
Display Synchronization
The horizontal and vertical synchronizing signals from the
TV deflection are used as inputs. Both signals can be
inverted before being delivered to the Phase Selector
section.
CC: The polarity is controlled using either VPOL or HPOL
in REG2:Text position Vertical.
8BC0
CHAR 30
CHAR 31
9Eh
9Fh
8BDF
8BE0
8BFF
Fig.25 Organisation of DRC RAM
TXT: SFRs bits TXT1.HPOL & TXT1.VPOL control the
polarity.
DEFINING CHARACTERS
A line locked 12 MHz clock is derived from the 12MHz free
running oscillator by the Phase Selector. This line locked
clock is used to clock the whole of the Display block.
The H & V Sync signals are synchronized with the 12 MHz
clock before being used in the display section.
The DRC RAM is mapped on to the 80C51 RAM address
space and starts at location 8800H. The character matrix
is 12 bits wide and therefore requires two bytes to be
written for each word, the first byte (even addresses),
addresses the lower 8 bits and the second byte (odd
addresses) addresses the upper 4 bits.
For characters of 9, 10 or 16 lines high the pixel
information starts in the first address and continues
sequentially for the required number of addresses.
Characters of 13 lines high are defined with an initial offset
of 1 address, this is to allow for correct generation of
fringing across boundaries of clustered characters (see
Fig.26). The characters continue sequentially for 13 lines
after which a further line can again be used for generation
of correct fringing across boundaries of clustered
characters.
Video/Data Switch (Fast Blanking) Polarity
The polarity of the Video/Data (Fast Blanking) signal can
be inverted. The polarity is set with the VDSPOL in REG7:
RGB Brightness register.
VDSP
OL
VDS
Condition
0
0
1
1
1
0
0
1
RGB display
Video Display
RGB display
Video Display
Line 13 from
character above
Top Left
Pixel
MSB
Line
No.
0
1
2
3
4
5
6
7
Hex
440
003
00C
030
0C0
300
C00
C00
300
C00
030
00C
003
000
1A8
000
LSB
Fringing
Top Line
Table 25 Fast Blanking Signal Polarity
Video/Data Switch Adjustment
8
9
To take into account the delay between the RGB values
and the VDS signal due to external buffering, the VDS
signal can be moved in relation to the RGB signals. The
VDS signal can be set to be either a clock cycle before or
after the RGB signal, or coincident with the RGB signal.
This is done using VDEL<2:0> in REG15:Configuration.
10
11
12
13
14
15
Bottom Line
Fringing
Line not used
Bottom Right
Pixel
Line 1 from
character below
Fig.26 13 Line High DRC’s Character Format
2001 Jan 18
54
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
RGB Brightness Control
This output is intended to act on the TV’s display circuits to
reduce contrast of the video when it is active. The result of
contrast reduction is to improve the readability of the text
in a mixed teletext and video display.
The bits in the TXT5 & TXT6 SFRs allow the display to be
set up so that, for example, the areas inside teletext boxes
will be contrast reduced when a subtitle is being displayed
but that the rest of the screen will be displayed as normal
video.
A brightness control is provided to allow the RGB upper
output voltage level to be modified. The RGB amplitude
may be varied between 60% and 100%.
The brightness is set in the RGB Brightness register as
follows: -
BRI3-0
0 0 0 0
...
RGB Brightness
Lowest value
...
CC: This feature is not available in CC mode.
Memory Mapped Registers
The memory mapped registers are used to control the
display. The registers are mapped into the Microcontroller
MOVX address space, starting at address 87F0h and
extending to 87FF.
1 1 1 1
Highest value
Table 26 RGB Brightness
Contrast Reduction
TXT: The COR bits in SFRs TXT5 & TXT6 control when
the COR output of the device is activated (i.e. Pulled-low).
MMR MAP
ADD R/W
Names
BIT7
SRC<3>
VPOL
BIT6
SRC<2>
HPOL
BIT5
SRC<1>
VOL<5>
BIT4
SRC<0>
VOL<4>
BIT3
-
BIT2
MSH
BIT1
MOD<1>
VOL<1>
BIT0
MOD<0>
VOL<0>
87F0
R/W
Display Control
87F1
R/W
Text
Position
VOL<3>
VOL<2>
Vertical
87F2
R/W
Text Area Start
Fringing Control
Text Area End
Scroll Area
HOP<1>
FRC<3>
-
HOP<0>
FRC<2>
-
TAS<5>
FRC<1>
TAE<5>
SSH<1>
SPS<1>
-
TAS<4>
FRC<0>
TAE<4>
SSH<0>
SPS<0>
-
TAS<3>
FRDN
TAS<2>
FRDE
TAS<1>
FRDS
TAS<0>
FRDW
87F3
R/W
87F4
R/W
TAE<3>
SSP<3>
STS<3>
BRI<3>
SCR<3>
SCR<3>
HSD<3>
VSD<3>
TAE<2>
SSP<2>
STS<2>
BRI<2>
SCR<2>
SCR<2>
HSD<3>
VSD<2>
TAE<1>
SSP<1>
STS<1>
BRI<1>
SCR<1>
SCR<1>
HSD<1>
TAE<0>
SSP<0>
STS<0>
BRI<0>
SCR<0>
SCR<0>
HSD<0>
87F5
R/W
SSH<3>
SPS<3>
VDSPOL
BUSY
-
SSH<2>
SPS<2>
-
87F6
R/W
Scroll Range
87F7
R/W
RGB Bright.ness
87F8
R
Status read
FIELD
-
SCON
FLR
87F8
W
Status write
SCON
FLR
87FC
R/W
H-Sync. Delay
V-Sync. Delay
Top Scroll Line
Configuration
-
HSD<6>
HSD<5>
HSD<4>
87FD
R/W
-
-
VSD<6>
-
VSD<5>
-
VSD<4>
-
VSD<1>
SCL<1>
VSD<0>
SCL<0>
87FE
R/W
SCL<3>
TXT/V
SCL<2>
87FF
R/W
CC
VDEL<2>
VDEL<1>
VDEL<0>
-
-
-
Table 27 MMR Memory Map
2001 Jan 18
55
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
MMR BIT DEFINITION
Names
ADD
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Display Control.
87F0
SRC<3>
SRC<2>
SRC<1>
SRC<0>
-
MSH
MOD<1>
MOD<0>
00H
SRC<3:0>
MSH
Screen Colour definition
0 - No meshing of background
1 - Meshing all background colours
MOD<1:0>
00 - Video
01 - Full Text
10 - Mixed Screen Colour
11 - Mixed Video
Text Position
Vertical
87F1
VPOL
HPOL
VOL<5>
VOL<4>
VOL<3>
VOL<2>
VOL<1>
VOL<0>
00H
VPOL
0 - Input polarity
1 - Inverted input polarity
HPOL
0 - Input Polarity
1 - Inverted input polarity
VOL<5:0>
Display start Vertical Offset from V-Sync. (lines)
87F2 HOP<1> HOP<0> TAS<5>
Text Area Start
TAS<4>
FRC<0>
TAS<3>
FRDN
TAS<2>
FRDE
TAS<1>
FRDS
TAS<0>
FRDW
00H
00H
HOP<1:0>
Fine Horizontal Offset in quarter of characters
Text area start
TAS<5:0>
Fringing Control.
87F3
FRC<3>
FRC<2>
FRC<1>
FRC<3:0>
FRDN
Fringing colour, value address of CLUT
0 - No fringe in North direction
1 - Fringe in North direction
FRDE
FRDS
0 - No fringe in East direction
1 - Fringe in East direction
0 - No fringe in South direction
1 - Fringe in South direction
FRDW
0 - No fringe in West direction
1 - Fringe in West direction
Text Area End
87F4
Text Area End, in full characters
87F5 SSH<3>
-
-
TAE<5>
SSH<1>
TAE<4>
SSH<0>
TAE<3>
SSP<3>
TAE<2>
SSP<2>
TAE<1>
SSP<1>
TAE<0>
SSP<0>
00H
00H
TAE<5:0>
Scroll Area
SSH<2>
SPS<2>
-
SSH<3:0>
Soft Scroll Height
Soft Scroll Position
SSP<3:0>
Scroll Range
87F6
SPS<3>
SPS<1>
SPS<0>
STS<3>
BRI<3>
STS<2>
BRI<2>
STS<1>
BRI<1>
STS<0>
BRI<0>
00H
00H
SPS<3:0>
Stop Scroll row
Start Scroll row
STS<3:0>
RGB Brightness
87F7
VDSPOL
-
-
2001 Jan 18
56
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
VDSPOL
BRI<3:0>
VDS Polarity
0 - RGB (1), Video (0)
1 - RGB (0), Video (1)
RGB Brightness control
Status read
87F8
BUSY
FIELD
SCON
FLR
SCR<3>
SCR<2>
SCR<1>
SCR<0>
00H
BUSY
FIELD
0 - Access to display memory will not cause display problems
1 - Access to display memory could cause display problems.
0 - Odd Field
1 - Even Field
FLR
0 - Active flash region foreground and background displayed
1 - Active flash region background only displayed
SCR<3:0>
First scroll row
Status write
87F8
-
-
SCON
FLR
SCR<3>
SCR<2>
SCR<1>
SCR<0>
00H
SCON
FLR
0 - Scroll area disabled
1 - Scroll area enabled
0 - Active flash region foreground and background colour displayed
1 - Active flash region background colour only displayed
SCR<3:0>
First Scroll Row
H-Sync. delay
HSD<6:0>
V-Sync Delay
87FC
H-Sync delay, in full size characters
87FD VSD<6>
V-Sync delay in number of TV lines
-
HSD<6>
HSD<5>
HSD<4>
HSD<3>
VSD<3>
HSD<3>
VSD<2>
HSD<1>
VSD<1>
HSD<0>
VSD<0>
00H
00H
00H
00H
-
VSD<5>
-
VSD<4>
-
VSD<6:0>
Top Scroll Line
87FE
-
-
SCL<3>
SCL<2>
SCL<1>
SCL<0>
SCL<3:0>
Top line for scroll
Configuration
87FF
CC
VDEL<2>
VDEL<1>
VDEL<0>
TXT/V
-
-
-
CC
0 - OSD mode
1 - Closed Caption mode
VDEL<2:0>
Pixel delay between VDS and RGB output
000 - VDS switched to video, not active
001 - VDS active one pixel earlier then RGB
010 - VDS synchronous to RGB
100 - VDS active one pixel after RGB
TXT/V
BUSY Signal switch
1 - Horizontal
0 - Vertical
Table 28 MMR Descriptions
2001 Jan 18
57
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
OTP MEMORY
security bits are one-time programmable and CANNOT be
erased.
These may be programmed either using the Parallel
Programming Interface or via the ISP Programming
Interface.
Parallel Programming
The following pins form the parallel programming
interface:-
Pin
Name
IO(0)
IO(1)
IO(2)
IO(3)
IO(4)
IO(5)
IO(6)
IO(7)
OEB
Function
P0.5
P0.6
P1.0
P1.1
P1.2
P1.3
P3.1
P3.2
P2.0
Bit 0:- Address/Data/Mode
Bit 1:- Address/Data/Mode
Bit 2:- Address/Data/Mode
Bit 3:- Address/Data/Mode
Bit 4:- Address/Data/Mode
Bit 5:- Address/Data/Mode
Bit 6:- Address/Data/Mode
Bit 7:- Address/Data/Mode
Output Enable
0 = IO is output
1 = IO is input
P3.0
WEB
Write Enable, programming pulse
>100us
0 = Program
P1.6
P1.7
MODE
A/DB
0 = IO(7:0) defined by A/DB
1 = IO(7:0) contains mode information
0 = IO(7:0) contains Data
1
=
IO(7:0) contains Address
Information
P3.3
VPE
Unused
VPE
RESET
CLK
9V Programming Voltage
Device reset/ mode selection
Clock 4 MHz
RESET
XTALIN
Table 29 Parallel Programming Interface
ISecurity Bits
The family of devices have a set of security bits for the
combined OTP Program ROM, Character ROM and
Packet 26 ROM. The security bits are used to prevent the
ROM from being overwritten once programmed, and also
the contents being verified once programmed. The
2001 Jan 18
58
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
The memory and security bits are structured as follows:-
MEMORY
SECURITY BITS INTERACTION
PROGRAM
ROM
USER ROM Programming
(Enable/Disable)
TEST ROM Programming
(Enable/Disable)
Verify
(Enable/Disable)
USER ROM
(i.e. 128k x 8 bits)
=
=
Yes
No
No
Yes
Yes
TEST ROM
RESERVED
(1k x 8 bits)
Yes
CHARACTER
ROM
USER ROM Programming
(Enable/Disable)
TEST ROM Programming
(Enable/Disable)
Verify
(Enable/Disable)
USER ROM
(9k x 12 bits)
=
=
Yes
No
No
Yes
Yes
TEST ROM
RESERVED
(0.5k x 12 bits)
Yes
PACKET 26
ROM
USER ROM Programming
(Enable/Disable)
TEST ROM Programming
(Enable/Disable)
Verify
(Enable/Disable)
USER ROM
(4k x 8 bits)
=
Yes
No
Yes
Table 30 Security bit structure
The security bits are set as follows for production programmed devices (i.e. programmed by Philips):-
MEMORY
SECURITY BITS SET
USER ROM Programming
(Enable/Disable)
TEST ROM Programming
(Enable/Disable)
Verify
(Enable/Disable)
PROGRAM ROM
CHARACTER ROM
PACKET 26 ROM
=
=
=
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
ENABLED
ENABLED
ENABLED
Table 31 Security bits for production devices
The security bits are set as follows for production un-programmed (blank) devices:-
MEMORY
SECURITY BITS SET
USER ROM Programming
(Enable/Disable)
TEST ROM Programming
(Enable/Disable)
Verify
(Enable/Disable)
PROGRAM ROM
CHARACTER ROM
PACKET 26 ROM
=
=
=
ENABLED
ENABLED
ENABLED
DISABLED
DISABLED
DISABLED
ENABLED
ENABLED
ENABLED
Table 32 Security bits for Blank devices
2001 Jan 18
59
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
2001 Jan 18
60
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR
Vision IF amplifier
FM demodulator
The FM demodulator is realised as narrow-band PLL with
external loop filter, which provides the necessary
selectivity without using an external band-pass filter. To
obtain a good selectivity a linear phase detector and a
constant input signal amplitude are required. For this
reason the intercarrier signal is internally supplied to the
demodulator via a gain controlled amplifier and AGC
circuit. To improve the selectivity an internal bandpass
filter is connected in front of the PLL circuit.
The vision IF amplifier can demodulate signals with
positive and negative modulation. The PLL demodulator is
completely alignment-free.
The VCO of the PLL circuit is internal and the frequency is
fixed to the required value by using the clock frequency of
the µ-Controller/Teletext decoder as a reference. The
setting of the various frequencies (38, 38.9, 45.75 and
58.75 MHz) can be made via the control bits IFA-IFC in
subaddress 27H. Because of the internal VCO the IF
circuit has a high immunity to EMC interferences.
The nominal frequency of the demodulator is tuned to the
required frequency (4.5/5.5/6.0/6.5 MHz) by means of a
calibration circuit which uses the clock frequency of the
µ-Controller/Teletext decoder as a reference. The setting
to the wanted frequency is realised by means of the control
bits FMA/FMB in the control bit 29H.
QSS Sound circuit
The sound IF amplifier is similar to the vision IF amplifier
and has an external AGC decoupling capacitor.
From the output status bytes it can be read whether the
PLL frequency is inside or outside the window and whether
the PLL is in lock or not. With this information it is possible
to make an automatic search system for the incoming
sound frequency. This can be realised by means of a
software loop which switches the demodulator to the
various frequencies and then select the frequency on
which a lock condition has been found.
The single reference QSS mixer is realised by a multiplier.
In this multiplier the SIF signal is converted to the
intercarrier frequency by mixing it with the regenerated
picture carrier from the VCO. The mixer output signal is
supplied to the output via a high-pass filter for attenuation
of the residual video signals. With this system a high
performance hi-fi stereo sound processing can be
achieved.
The deemphasis output signal amplitude is independent of
the TV standard and has the same value for a frequency
deviation of ±25 kHz at the 4.5 MHz standard and for a
deviation of ±50 Khz for the other standards.
The AM sound demodulator is realised by a multiplier. The
modulated sound IF signal is multiplied in phase with the
limited SIF signal. The demodulator output signal is
supplied to the output via a low-pass filter for attenuation
of the carrier harmonics. The AM signal is supplied to the
output (AUDOUT/AMOUT) via the volume control.
Switching between the QSS output and AM output is made
by means of the AM bit in subaddress 29H (see also
Table 1).
2001 Jan 18
61
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Audio circuit and input signal selection
CVBS and Y/C input signal selection
The audio control circuit contains an audio switch with 1
external input and a volume control circuit. The selection
of the various inputs is made by means of the ADX bit. In
various versions the Automatic Volume Levelling (AVL)
function can be activated. The pin to which the external
capacitor has to be connected depends on the IC version.
For the 90° types the capacitor is connected to the EW
output pin. For the 110° types a choice must be made
between the AVL function and a sub-carrier output for
comb filter applications. This choice is made via the
CBM0/1 bits (in subaddress 22H). When the AVL is active
it automatically stabilises the audio output signal to a
certain level.
The circuit has 2 inputs for external CVBS signals and one
input can also be used as one Y/C input (see Fig. 27).
It is possible to supply the selected CVBS signal to the
demodulated IF video output pin. This mode is selected by
means of the SVO bit in subaddress 22H. The vision IF
amplifier is switched off in this mode.
The video ident circuit can be connected to the incoming
‘internal’ video signal or to the selected signal. This ident
circuit is independent of the synchronisation and can be
used to switch the time-constant of the horizontal PLL
depending on the presence of a video signal (via the VID
bit). In this way a very stable OSD can be realised.
It is possible to use the deemphasis pin as additional audio
input. In that case the internal signal must, of course, be
switched off. This can be realised by means of the sound
mute bit (SM in subaddress 29H). When the IF circuit is
switched to positive modulation the internal signal on the
deemphasis pin is automatically muted.
The subcarrier output is combined with a 3-level output
switch (0 V, 2.3 V and 4.5 V). The output level and the
availability of the subcarrier signal is controlled by the
CMB1 and CMB0 bits. The output can be used to switch
sound traps etc. It is also possible to use this pin for the
connection of the AVL capacitor or as AM output.
TO LUMA/SYNC PROCESSING
TO CHROMA PROCESSING
IDENT
VIM
(+)
VIDEO IDENT
IFVO
SVO
C
CVBS2/Y
CVBS1
IFVO/SVO
Fig.27 CVBS switch and interfacing of video ident
2001 Jan 18
62
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Synchronisation circuit
Chroma, luminance and feature processing
The IC contains separator circuits for the horizontal and
vertical sync pulses and a data-slicing circuit which
extracts the digital teletext data from the analog signal.
The chroma band-pass and trap circuits (including the
SECAM cloche filter) are realised by means of gyrators
and are tuned to the right frequency by comparing the
tuning frequency with the reference frequency of the
colour decoder. The luminance delay line and the delay
cells for the peaking circuit are also realised with gyrators.
The horizontal drive signal is obtained from an internal
VCO which is running at a frequency of 25 MHz. This
oscillator is stabilised to this frequency by using a 12 MHz
signal coming from the reference oscillator of the
µ-Controller.
The circuit contains the following picture improvement
features:
• Peaking control circuit. The ratio of the positive and
negative overshoots of the peaking can be adjusted by
means of the bits RPO1/RPO0 in subaddress 2EH.
The horizontal drive is switched on and off via the soft
start/stop procedure. This function is realised by means of
variation of the TON of the horizontal drive pulses. In
addition the horizontal drive circuit has a ‘low-power
start-up’ function.
• Black stretch. This function corrects the black level for
incoming signals which have a difference between the
black level and the blanking level.
The vertical synchronisation is realised by means of a
divider circuit. The vertical ramp generator needs an
external resistor and capacitor. For the vertical drive a
differential output current is available. The outputs must be
DC coupled to the vertical output stage.
In the types which are intended for 90° picture tubes the
following geometry parameters can be adjusted:
• Horizontal shift
• Vertical amplitude
• Vertical slope
• S-correction
• Vertical shift
The types which are intended to be used in combination
with 110° picture tubes have an East-West control circuit
in stead of the AVL function. The additional controls for
these types are:
• EW width
• EW parabola width
• EW upper and lower corner parabola correction
• EW trapezium correction
• Vertical zoom
• horizontal parallelogram and bow correction.
When the vertical amplitude is compressed (zoom
factor <1) it is still possible to display the black current
measuring lines in the overscan. This function is activated
by means of the bit OSVE in subaddress 26H.
2001 Jan 18
63
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Colour decoder
is realised by means of the OPC bit in subaddress 2BH.
When used as one-point control loop the system will
control the black level of the RGB output signals to the
‘low’ reference current and not on the cut off point of the
cathode. In this way spreads in the picture tube
characteristics will no take into account. A further
consequence is that the RGB output signals have a fixed
amplitude (2 VP-P under nominal conditions) and that the
‘cathode drive level’ bits (CL3-CL0) have no effect on
these amplitudes. For this reason the gain of the RGB
output stages has to be adapted to the required drive level
of the cathodes.
The ICs can decode PAL, SECAM and NTSC signals. The
PAL/NTSC decoder does not need external reference
crystals but has an internal clock generator which is
stabilised to the required frequency by using the 12 MHz
clock signal from the reference oscillator of the
µ-Controller.
Under bad-signal conditions (e.g. VCR-playback in feature
mode), it may occur that the colour killer is activated
although the colour PLL is still in lock. When this killing
action is not wanted it is possible to overrule the colour
killer by forcing the colour decoder to the required standard
and to activate the FCO-bit (Forced Colour On) in
subaddress 21H.
A black level off-set can be made with respect to the level
which is generated by the black current stabilization
system. In this way different colour temperatures can be
obtained for the bright and the dark part of the picture.
In the Vg2 adjustment mode (AVG = 1) the black current
stabilization system checks the output level of the 3
channels and indicates whether the black level of the
highest output is in a certain window (WBC-bit) or below or
above this window (HBC-bit). This indication can be read
from the status byte 01 and can be used for automatic
adjustment of the Vg2 voltage during the production of the
TV receiver. During this test the vertical scan remains
active so that the indication of the 2 bits can be made
visible on the TV screen.
The Automatic Colour Limiting (ACL) circuit (switchable
via the ACL bit in subaddress 20H) prevents that
oversaturation occurs when PAL/NTSC signals with a high
chroma-to-burst ratio are received. The ACL circuit is
designed such that it only reduces the chroma signal and
not the burst signal. This has the advantage that the colour
sensitivity is not affected by this function.
The SECAM decoder contains an auto-calibrating PLL
demodulator which has two references, viz: the divided 12
MHz reference frequency (obtained from the µ-Controller)
which is used to tune the PLL to the desired free-running
frequency and the bandgap reference to obtain the correct
absolute value of the output signal. The VCO of the PLL is
calibrated during each vertical blanking period, when the
IC is in search or SECAM mode.
The control circuit contains a beam current limiting circuit
and a peak white limiting circuit. To prevent that the peak
white limiting circuit reacts on the high frequency content
of the video signal a low-pass filter is inserted in front of the
peak detector.
The base-band delay line (TDA 4665 function) is
integrated. This delay line is also active during NTSC to
obtain a good suppression of cross colour effects. The
demodulated colour difference signals are internally
supplied to the delay line.
During switch-off of the TV receiver a fixed beam current
is generated by the black current control circuit. This
current ensures that the picture tube capacitance is
discharged. During the switch-off period the vertical
deflection can be placed in an overscan position so that
the discharge is not visible on the screen.
RGB output circuit and black-current stabilization
In the RGB control circuit the signal is controlled on
contrast, brightness and saturation. The ICs have a linear
input for external RGB/YUV signals. Switching between
RGB and the YUV mode can be realised via the YUV bit in
subaddress 2BH. The signals for OSD and text are
internally supplied to the control circuit. The output signal
has an amplitude of about 2 V black-to-white at nominal
input signals and nominal settings of the various controls.
A wide blanking pulse can be activated in the RGB outputs
by means of the HBL bit in subaddress 2BH. The timing of
this blanking can be adjusted by means of the bits WBF/R
bits in subaddress 03H.
To obtain an accurate biasing of the picture tube the
‘Continuous Cathode Calibration’ (CCC) system has been
included in these ICs. When required the operation of the
CCC system can be changed into a one-point black
current system. The switching between the 2 possibilities
2001 Jan 18
64
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
SOFTWARE CONTROL
The CPU communicates with the peripheral functions
using Special function Registers (SFRs) which are
handbook, halfpage
A6
A5
0
A4
0
A3
0
A2
1
A1
0
A0 R/W
addressed as RAM locations. The registers for the
Teletext decoder appear as normal SFRs in the
µ-Controller memory map and are written to these
functions by using a serial bus. This bus is controlled by
dedicated hardware which uses a simple handshake
system for software synchronisation.
1
1
1/0
MLA743
Fig.28 Slave address (8A)
For compatibility reasons and possible re-use of software
blocks, the I2C-bus control for the TV processor is
organised as in the stand-alone TV signal processors. The
TV processor registers cannot be read, so when the
content of these registers is needed in the software, a copy
should be stored in Auxiliary RAM or Non Volatile RAM.
The slave address of the TV signal processor is given in
Fig.28.
Valid subaddresses: 05H to 2EH, subaddress FE and FF
are reserved for test purposes. Auto-increment mode
available for subaddresses.
2001 Jan 18
65
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
DESCRIPTION OF THE I2C-BUS SUBADDRESSES
Table 33 Inputs TV-processor
DATA BYTE
POR
SUBADDR
FUNCTION
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0 Value
Off-set IF demodulator
Horizontal parallelogram (1)
Horizontal bow (1)
Hue
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PF1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PF0
0
0
0
0
0
0
CM2
0
0
0
HP2
0
AFN
IFB
0
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
0
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
0
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
YD3
A3
A3
A3
A3
A3
MAT
0
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
YD2
A2
A2
A2
A2
A2
MUS
0
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
YD1
A1
A1
A1
A1
A1
ACL
BPS
INB
0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
YD0
A0
A0
A0
A0
20
20
20
00
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
00
20
20
20
20
20
00
00
00
00
00
00
00
00
00
00
00
Horizontal shift (HS)
EW width (EW) (1)
EW parabola/width (PW) (1)
EW upper corner parabola(1)
EW lower corner parabola(1)
EW trapezium (TC) (1)
Vertical slope (VS)
Vertical amplitude (VA)
S-correction (SC)
Vertical shift (VSH)
Vertical zoom (VX) (1)
Black level offset R
Black level offset G
White point R
White point G
White point B
Peaking
Luminance delay time
Brightness
A5
A5
A5
A5
A5
CM1
0
A4
A4
A4
A4
A4
CM0
0
Saturation
Contrast
AGC take-over
Volume control
Colour decoder 0
Colour decoder 1
AV-switch 0
0
CM3
0
A0
CB
FCO
0
RGBL
VID
NCIN
HCO(1)
SVO
0
CMB1 CMB0
INA
0
STB
AV-switch 1
0
0
0
0
0
POC
Synchronisation 0
Synchronisation 1
Deflection
Vision IF 0
Vision IF 1
Sound 0
Control 0
Control 1
Sound 1
FOA
FSL
DFL
IFC
0
FOB
OSO
XDT
VSW
IFLH
VIM
DL
EVG
IFS
FORF FORS
SBL AVG
MOD AFW
0
SM0
CL3
0
0
IFA
SIF
AGN
0
0
0
STM
FFI
AGC1 AGC0
SM1 FMWS AM(3)
0
CL2
YUV
AVL(2)
0
FMB
CL1
0
0
0
FMA
CL0
IE2
IVG
0
0
0
RBL
0
ADX
0
AKB
0
0
0
HBL(1) 00
0
0
0
0
BKS
0
00
00
00
Features 0
Features 1
0
0
RPO1 RPO0
0
0
Note
1. These functions are only available in versions which have the East-West drive output.
2. The AVL function is only available in versions which have no East-West output or when the subcarrier output is used
for the connection of the AVL capacitor (via the bits CMB1 and CMB0 in subaddress 22H).
3. Only available in types with QSS sound IF circuit and AM demodulator.
2001 Jan 18
66
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Table 34 Outputs TV-processor
DATA BYTE
FUNCTION
SUBADDR
D7
D6
D5
D4
D3
D2
D1
D0
Output status bytes
00
01
02
03
04
POR
XPR
SUP
ID7
IFI
NDF
X
LOCK
FSI
X
SL
IVW
QSS
ID4
X
CD3
WBC
AFA
ID3
CD2
HBC
AFB
ID2
X
CD1
BCF
FMW
ID1
CD0
IN2
FML
ID0
X
ID6
SN0
ID5
X
SN1
X
X
Explanation input control data TV-processor
Table 39 Horizontal shift
DAC SETTING
CONTROL
Table 35 Off-set IF demodulator
0
−2 µs
0
DAC SETTING
CONTROL
negative correction
20
3F
0
+2 µs
20
3F
no correction
positive correction
Table 40 EW width
DAC SETTING
CONTROL
Table 36 Horizontal parallelogram
0
output current 700 µA
output current 0 µA
DAC SETTING
CONTROL
screen top 0.5 µs delayed and screen
3F
0
bottom 0.5 µs advanced with respect
to centre
Table 41 EW parabola/width
DAC SETTING
CONTROL
output current 0 µA
20
3F
no correction
0
screen top 0.5 µs advanced and
screen bottom 0.5 µs delayed with
respect to centre
3F
output current 440 µA at top and
bottom of screen
Table 37 Horizontal bow
Table 42 EW upper/lower corner parabola
DAC SETTING
CONTROL
DAC SETTING
CONTROL
0
screen top and bottom 0.5 µs delayed
with respect to centre
0
output current +76 µA
output current 0 µA
11
3F
20
3F
no correction
output current −207 µA
screen top and bottom 0.5 µs
advanced with respect to centre
Table 43 EW trapezium
DAC SETTING
CONTROL
Table 38 Hue control
0
output current at top of screen 100 µA
lower that at bottom
DAC SETTING
CONTROL
0
−45°
0°
20
3F
no correction
20
3F
output current at top of screen 100 µA
higher than at bottom
+45°
2001 Jan 18
67
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Table 51 Peaking centre frequency
Table 44 Vertical slope
PF1
0
PF0
0
CENTRE FREQUENCY
2.7 MHz
DAC SETTING
CONTROL
correction −20%
no correction
correction +20%
0
0
1
3.1 MHz
3.5 MHz
spare
20
3F
1
0
1
1
Table 45 Vertical amplitude
Table 52 Peaking control (overshoot in direction ‘black’)
DAC SETTING
CONTROL
amplitude 80%
amplitude 100%
amplitude 120%
DAC SETTING
CONTROL
depeaking (overshoot −22%)
no peaking
0
0
20
3F
10
3F
overshoot 80%
Table 46 S-correction
Table 53 Y-delay adjustment; note 1
DAC SETTING
CONTROL
correction −10%
no correction
correction 25%
YD0 to YD3
Y-DELAY
0
YD3
YD2
YD1
YD0
YD3 × 160 ns +
YD2 × 80 ns +
YD1 × 80 ns +
YD0 × 40 ns
0E
3F
Table 47 Vertical shift
DAC SETTING
CONTROL
Note
0
shift −5%
1. For an equal delay of the luminance and chrominance
signal the delay must be set at a value of 160 ns. This
is only valid for a CVBS signal without group
delay distortions.
20
3F
no correction
shift +5%
Table 48 Vertical zoom
Table 54 Brightness control
DAC SETTING
CONTROL
DAC SETTING
CONTROL
correction −0.7V
0
amplitude 75%
amplitude 100%
amplitude 138%
0
20
3F
20
3F
no correction
correction +0.7V
Table 49 Black level off-set R/G
Table 55 Saturation control
DAC SETTING
CONTROL
DAC SETTING
CONTROL
colour off (−52 dB)
saturation nominal
saturation +300%
0
off-set of −160 mV
no off-set
0
20
3F
17
3F
off-set of +160 mV
Table 50 White point R/G/B
Table 56 Contrast control
DAC SETTING
CONTROL
DAC SETTING
CONTROL
0
gain −3 dB
no correction
gain +3 dB
0
RGB amplitude −14 dB
RGB amplitude nominal
RGB amplitude +6 dB
20
3F
20
3F
2001 Jan 18
68
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Table 57 AGC take-over
Table 60 PAL-SECAM/NTSC matrix
DAC SETTING
CONTROL
MAT
MATRIX POSITION
0
tuner take-over at IF input signal of
0.4 mV
0
1
adapted to standard
PAL matrix
3F
tuner take-over at IF input signal of 80
mV
Table 61 NTSC matrix
MUS
MATRIX POSITION
Japanese matrix
USA matrix
Table 58 Volume control
0
1
DAC SETTING
CONTROL
attenuation 80 dB
no attenuation
0
3F
Table 62 Automatic colour limiting
ACL
COLOUR LIMITING
Table 59 Colour decoder mode, note 1
0
1
not active
active
CM3 CM2 CM1 CM0 DECODER MODE FREQ
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
PAL/NTSC/SECAM
PAL/SECAM
PAL
A
A
A
A
Table 63 Chroma bandpass centre frequency
CB
0
CENTRE FREQUENCY
NTSC
FSC
SECAM
1
1.1 × FSC
PAL/NTSC
PAL
B
B
Table 64 Bypass of chroma base-band delay line
NTSC
B
BPS
DELAY LINE MODE
PAL/NTSC/SECAM
PAL/NTSC
PAL
ABCD
C
0
1
active
bypassed
C
NTSC
C
Table 65 Forced Colour-On
PAL/NTSC
(Tri-Norma)
BCD
FCO
CONDITION
0
1
off
on
1
1
1
1
1
1
0
1
1
1
0
1
PAL/NTSC
PAL
D
D
D
NTSC
Table 66 Selected video out
Note
SVO
CONDITION
1. The decoder frequencies for the various standards are
obtained from an internal clock generator which is
synchronised by a 12 MHz reference signal which is
obtained from the µ-Controller clock generator.
0
1
IF video available at output
selected CVBS available at output
Table 67 Condition AVL/SNDIF/REFO
CMB1 CMB0 CONDITION
These frequencies are:
a) A: 4.433619 MHz
0
0
1
1
0
1
0
1
AVL/SNDIF active (depends on SIF bit)
output voltage 2.3 V + subcarrier;
output voltage low (<0.8 V)
b) B: 3.582056 MHz (PAL-N)
c) C: 3.575611 MHz (PAL-M)
d) D: 3.579545 MHz (NTSC-M)
output voltage high (>4.5V)
2001 Jan 18
69
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Table 68 Source select
Table 76 Forced slicing level for vertical sync
INA
INB
INC
SELECTED SIGNALS
CVBS1
FSL
SLICING LEVEL
0
0
1
0
1
0
0
0
0
0
1
slicing level dependent on noise detector
fixed slicing level of 60%
CVBS2
Y/C
Table 77 Switch-off in vertical overscan
Table 69 Blanking of RGB outputs
OSO
MODE
Switch-off undefined
Switch-off in vertical overscan
RGBL
CONDITION
0
1
0
1
normal operation
RGB outputs blanked continuously
Table 78 Forced field frequency
Table 70 Synchronization of OSD/TEXT display
FORF
FORS
FIELD FREQUENCY
HP2
µ-CONTROLLER COUPLED TO
ϕ1 loop
ϕ2 loop
0
0
1
1
0
1
0
1
auto (60 Hz when line not in sync)
60 Hz
0
1
keep last detected field frequency
auto (50 Hz when line not in sync)
Table 71 Phase 1 (ϕ1) time constant
Table 79 Interlace
FOA
FOB
MODE
DL
STATUS
0
0
1
1
0
1
0
1
normal
slow
0
1
interlace
de-interlace
slow/fast
fast
Table 80 Vertical divider mode
Table 72 Synchronization mode
NCIN
VERTICAL DIVIDER MODE
POC
MODE
0
1
normal operation
switched to search window
0
1
active
not active
Table 81 AFC switch
Table 73 Stand-by
AFN
MODE
STB
MODE
0
1
normal operation
AFC not active
0
1
stand-by
normal
Table 82 Disable flash protection
Table 74 Video ident mode
DFL
MODE
VIM
MODE
0
1
flash protection active
flash protection disabled
0
1
ident coupled to internal CVBS (pin 40)
ident coupled to selected CVBS
Table 75 Video ident mode
VID
VIDEO IDENT MODE
0
1
ϕ1 loop switched on and off
not active
2001 Jan 18
70
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Table 83 X-ray detection
Table 90 Modulation standard
XDT
MODE
MOD
MODULATION
0
1
protection mode, when a too high EHT is
detected the receiver is switched to stand-by
and the XPR-bit is set to 1
0
1
negative
positive
detection mode, the receiver is not switched
to stand-by and only the XPR-bit is set to 1
Table 91 AFC window
AFW
AFC WINDOW
IF SENSITIVITY
0
1
normal
Table 84 Service blanking
enlarged
SBL
SERVICE BLANKING MODE
0
1
off
on
Table 92 IF sensitivity
IFS
0
1
normal
Table 85 Adjustment Vg2 voltage
reduced
AVG
MODE
0
1
normal operation
Table 93 Search tuning mode
Vg2 adjustment (WBC and HBC bits in output
byte 01 can be read)
STM
MODE
0
1
normal operation
Table 86 Enable vertical guard (RGB blanking)
reduced sensitivity of video indent circuit
EVG
VERTICAL GUARD MODE
Table 94 Selection external input for sound IF circuit
0
1
not active
active
SIF
0
MODE
IF input not selected
IF input selected (see also table 1)
Table 87 EHT tracking mode
1
HCO
TRACKING MODE
Table 95 Calibration of IF PLL demodulator
0
1
EHT tracking only on vertical
IFLH
MODE
calibration system active
calibration system not active
EHT tracking on vertical and EW
0
1
Table 88 PLL demodulator frequency adjust
IFA
IFB
IFC
IF FREQUENCY
58.75 MHz
Table 96 IF AGC speed
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
AGC1
AGC0
AGC SPEED
45.75 MHz
38.90 MHz
38.00 MHz
33.40 MHz
33.90 MHz
0
0
1
1
0
1
0
1
0.7 × norm
norm
3 × norm
6 × norm
Table 97 Fast filter IF-PLL
Table 89 Video mute
FFI
CONDITION
normal time constant
increased time constant
VSW
STATE
0
1
0
1
normal operation
IF-video signal switched off
2001 Jan 18
71
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Table 98 Gain FM demodulator
Table 105 Black current stabilization
AGN
MODE
AKB
MODE
0
1
normal operation
0
1
active
gain +6 dB, to be used for the demodulation of
mono signals in the NTSC system
not active
Table 106 Cathode drive level (15 steps; 3.5 V/step)
Table 99 Sound mute
SETTING CATHODE
DRIVE AMPLITUDE;
SM1
SM0
CONDITION
CL3 CL2 CL1 CL0
0
1
1
1
0
1
see note 1
mute on
mute off
NOTE 1
0
0
1
0
1
1
0
1
1
0
1
1
50 VBL-WH
75 VBL-WH
95 VBL-WH
Note
1. The mute is activated when the digital acquisition help
is out-of-window.
Note
1. The given values are valid for the following conditions:
a) - Nominal CVBS input signal
Table 100Window selection of Narrow-band sound PLL
b) - Nominal settings for contrast, WPA and peaking
c) - Black- and blue-stretch switched-off
FMWS
FUNCTION
0
1
small window
large window
d) - Gain of output stage such that no clipping occurs
e) - Beam current limiting not active
f) The tolerance on these values is about ± 3 V.
Table 101 Selection QSS out or AM out
AM
MODE
QSS output selected
AM output selected
Table 107Activation vertical guard
0
1
IVG
MODE
0
vertical guard connected to black current
input
Table 102Nominal frequency FM demodulator
1
vertical guard connected to BCL input and
“Peak-White-Limiting” disabled
FMB
FMA
FREQUENCY
0
0
1
1
0
1
0
1
5.5 MHz
6.0 MHz
4.5 MHz
6.5 MHz
Table 108 RGB / YUV switch
YUV
STATUS
RGB input activated
YUV input activated
0
1
Table 103Enable fast blanking ext.RGB/YUV
Table 109RGB blanking mode (110° types)
IE2
FAST BLANKING
0
1
not active
active
HBL
MODE
0
1
normal blanking (horizontal flyback)
wide blanking
Table 104 RGB blanking
RBL
RGB BLANKING
0
1
not active
active
2001 Jan 18
72
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Table 110Audio signal selection
Explanation output control data TV-processor
Table 114 Power-on-reset
ADX
SELECTED SIGNAL
0
1
internal audio signal
external audio signal
POR
MODE
0
1
normal
power-down
Table 111Auto Volume Levelling
Table 115 Output video identification
AVL
MODE
0
1
not active
active
IFI
VIDEO SIGNAL
0
1
no video signal identified
video signal identified
Table 112Black stretch
Table 116 IF-PLL lock indication
BKS
BLACK STRETCH MODE
0
1
off
on
LOCK
INDICATION
0
1
not locked
locked
Table 113 Ratio pre- and overshoot
RPO1
RPO0
RATIO PRE-/OVERSHOOT
1 : 1
Table 117 Phase 1 (ϕ1) lock indication
0
0
1
1
0
1
0
1
SL
INDICATION
1 : 1.25
1 : 1.5
1 : 1.8
0
1
not locked
locked
Table 118 Colour decoder mode, note 1
CD3 CD2 CD1 CD0 STANDARD
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
no colour standard identified
NTSC with freq. A
PAL with freq. A
NTSC with freq. B
PAL with freq. B
NTSC with freq. C
PAL with freq. C
NTSC with freq. D
PAL with freq. D
SECAM
Note
1. The values for the various frequencies can be found in
the note of table 59.
Table 119 X-ray protection
XPR
OVERVOLTAGE
no overvoltage detected
overvoltage detected
0
1
2001 Jan 18
73
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Table 120 Output vertical guard
Table 127 Supply voltage indication
NDF
VERTICAL OUTPUT STAGE
SUP
CONDITION
0
1
OK
0
1
supply voltage (8 Volt) not present
supply voltage (8 Volt) present
failure
Table 121 Field frequency indication
Table 128 Version indication
FSI
FREQUENCY
QSS
IC VERSION
0
1
50 Hz
60 Hz
0
1
version with intercarrier mono sound circuit
version with QSS-IF circuit
Table 122 Condition vertical divider
Table 129 AFC output
IVW
STANDARD VIDEO SIGNAL
AFA
AFB
CONDITION
0
1
no standard video signal
0
0
1
1
0
1
0
1
outside window; RF too low
outside window; RF too high
in window; below reference
in window; above reference
standard video signal (525 or 625 lines)
Table 123 Indication output black level in/out window
WBC
CONDITION
Table 130 Indication FM-PLL in/out window
0
1
black current stabilisation outside window
black current stabilisation inside window
FMW
CONDITION
FM-PLL in window
FM-PLL out of window
0
1
Table 124 Indication output black level
HBC
CONDITION
Table 131Indication FM-PLL in/out lock
0
1
black current stabilisation below window
black current stabilisation above window
FML
CONDITION
FM-PLL out of lock
FM-PLL locked
0
1
Table 125 Condition black current loop
BCF
CONDITION
0
1
black current loop is stabilised
black current loop is not stabilised
Table 126 Indication RGB-2 input condition
IN2
RGB INSERTION
0
1
no
yes
2001 Jan 18
74
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
UNIT
VP
−
9
V
V
VDD
supply voltage (all digital
supplies)
−0.5
5.0
VI
digital inputs
note 1
note 1
−0.5
−0.5
−
VDD+ 0.5
VDD+ 0.5
±10
V
V
VO
IO
digital outputs
output current (each output)
DC input or output diode current
storage temperature
mA
mA
°C
°C
°C
°C
V
IIOK
Tstg
Tamb
Tsol
Tj
−
±20
−25
0
+150
70
operating ambient temperature
soldering temperature
operating junction temperature
electrostatic handling
for 5 s
−
260
−
150
Ves
HBM; all pins; notes 2 and 3 −2000
MM; all pins; notes 2 and 4 −300
+2000
+300
V
Notes
1. This maximum value has an absolute maximum of 5.5 V independent of VDD
2. All pins are protected against ESD by means of internal clamping diodes.
3. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.
.
4. Machine Model (MM): R = 0 Ω; C = 200 pF.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
35
K/W
QUALITY SPECIFICATION
In accordance with “SNW-FQ-611E”.
Latch-up
At an ambient temperature of 70 °C all pins meet the following specification:
• Itrigger ≥ 100 mA or ≥1.5VDD(max)
• Itrigger ≤ −100 mA or ≤−0.5VDD(max)
.
2001 Jan 18
75
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
CHARACTERISTICS OF MICRO-COMPUTER AND TEXT DECODER
VDD = 3.3 V ± 10%; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified
NUMBER
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VM.1.1
VM.1.2
VM.1.3
VM.1.4
supply voltage (VDDA/P/C
)
3.0
3.3
3.6
V
periphery supply current (IDDP
)
note 1
1
−
−
−
−
mA
mA
mA
core supply current (IDDC
)
15
45
tbf
tbf
analog supply current (IDDA
)
Digital inputs
RESET
I.1.1
I.1.2
I.1.3
low level input voltage
high level input voltage
−
−
−
−
0.8
5.5
0.7
V
V
V
2.0
0.4
hysteresis of Schmitt Trigger
input
I.1.4
I.1.5
I.1.6
input leakage current
VI = 0
−
−
−
−
1
µA
kΩ
pF
equivalent pull down resistance V = VDD
capacitance of input pin
33
−
−
10
Digital input/outputs
P1.0 TO P1.3, P2.0 TO P2.6 AND P3.0 TO P3.3
IO.1.1
IO.1.2
IO.1.3
low level input voltage
high level input voltage
−
−
−
−
0.8
5.5
0.7
V
V
V
2.0
0.4
hysteresis of Schmitt Trigger
input
IO.1.4
IO.1.5
IO.1.6
IO.1.7
low level output voltage
high level output voltage
high level output voltage
I
OL = 4 mA
−
−
0.4
5.5
−
V
open drain
IOH = 4 mA
−
−
V
2.4
−
−
V
output rise time (push-pull only) load 100 pF
10% to 90%
16
−
ns
IO.1.8
IO.1.9
IO.1.10
output fall time 10% to 90%
load capacitance
load 100pF
−
−
−
14
−
−
ns
pF
pF
100
10
capacitance of input pin
−
2001 Jan 18
76
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
P0.5 AND P0.6
IO.2.1
IO.2.2
IO.2.3
low level input voltage
high level input voltage
−
−
−
−
0.8
V
2.0
0.4
5.5
0.7
V
V
hysteresis of Schmitt Trigger
input
IO.2.4
IO.2.5
IO.2.6
IO.2.7
low level output voltage
high level output voltage
high level output voltage
I
OL = 8mA
−
−
−
−
0.4
5.5
−
V
open drain
IOH = 8mA
−
V
2.4
−
V
output rise time (push-pull only) load 100 pF
10% to 90%
16
−
ns
IO.2.8
IO.2.9
IO.2.10
output fall time 10% to 90%
load capacitance
load 100pF
−
−
−
14
−
−
ns
pF
pF
100
10
capacitance of input pin
−
P1.6 AND P1.7
IO.3.1
IO.3.2
IO.3.3
low level input voltage (VIL)
high level input voltage (VIH)
−
−
−
−
1.5
5.5
−
V
V
V
3.0
0.2
hysteresis of Schmitt-trigger
input
IO.3.4
IO.3.5
IO.3.6
low level output voltage
sink current 8mA
open drain
0
−
−
−
0.4
5.5
250
V
high level output voltage
output fall time (VIH to VIL for CL)
−
V
20+0.1×
ns
CL
IO.3.7
IO.3.8
bus load capacitance
capacitance of IO pin
10
−
−
400
10
pF
pF
−
Crystal oscillator
OSCIN; NOTE 2
X.1.1
X.1.2
X.1.3
X.1.4
X.1.5
resonator frequency
−
12
4.0
5.0
−
−
MHz
pF
pF
pF
Ω
input capacitance (Ci)
output capacitance (Co)
Cx1 = Cx2
−
−
−
−
12
−
56
100
Ri (crystal)
−
Note
1. Peripheral current is dependent on external components and voltage levels on I/Os
2. The simplified circuit diagram of the oscillator is given in Fig.29.
A suitable crystal for this oscillator is the Saronix type 9922 520 00169. The nominal tuning of the crystal is important
to obtain a symmetrical catching range for the PLL in the colour decoder. This tuning can be adapted by means of
the values of the capacitors Cx1 and Cx2 in Fig.29. Good results were obtained with capacitor values of 39 pF,
however, for a new application the optimum value should be determined by checking the symmetry of the catching
range of the colour decoder.
2001 Jan 18
77
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
CHARACTERISTICS OF TV-PROCESSORS
VP = 5 V; Tamb = 25 °C; unless otherwise specified.
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
MAIN SUPPLY; NOTE 1
V.1.1
V.1.2
V.1.4
supply voltage
total supply current
total power dissipation
7.2
8.0
8.4
V
−
−
135
−
−
mA
1085
mW
IF circuit
VISION IF AMPLIFIER INPUTS
input sensitivity (RMS value)
note 2
M.1.1
M.1.2
M.1.3
M.1.4
M.1.5
M.1.6
M.1.7
fi = 38.90 MHz
fi = 45.75 MHz
fi = 58.75 MHz
note 3
−
75
75
75
2
150
150
150
−
µV
µV
µV
kΩ
pF
dB
mV
−
−
input resistance (differential)
input capacitance (differential)
gain control range
−
note 3
−
3
−
64
150
−
−
maximum input signal
(RMS value)
−
−
PLL DEMODULATOR; NOTES 4 AND 5
M.2.1
Free-running frequency of VCO PLL not locked, deviation
from nominal setting
−500
−
+500
kHz
M.2.2
M.2.3
Catching range PLL
without SAW filter
via LOCK bit
−
−
±1
−
MHz
ms
delay time of identification
−
20
VIDEO AMPLIFIER OUTPUT; NOTES 7 AND 8
M.3.1
M.3.2
M.3.3
M.3.4
M.3.5
zero signal output level
negative modulation; note 9
positive modulation; note 9
negative modulation
−
4.7
2.0
2.1
4.5
0
−
V
V
V
V
%
−
−
top sync level
white level
1.9
−
2.3
−
positive modulation
difference in amplitude between
negative and positive modulation
−
15
M.3.6
M.3.7
video output impedance
−
50
−
−
Ω
internal bias current of NPN
1.0
−
mA
emitter follower output transistor
M.3.8
M.3.9
maximum source current
−
−
5
mA
bandwidth of demodulated
output signal
at −3 dB
6
7
−
MHz
M.3.10
M.3.11
differential gain
note 10
−
−
2
5
5
%
differential phase
notes 10 and 6
−
deg
2001 Jan 18
78
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIDEO AMPLIFIER (CONTINUED)
M.3.12
M.3.13
M.3.14
M.3.15
video non-linearity
note 11
−
−
−
−
−
5
−
−
−
%
white spot clamp level
noise inverter clamping level
5.3
1.5
2.8
V
V
V
note 12
note 12
noise inverter insertion level
(identical to black level)
intermodulation
blue
notes 6 and 13
Vo = 0.92 or 1.1 MHz
Vo = 2.66 or 3.3 MHz
Vo = 0.92 or 1.1 MHz
Vo = 2.66 or 3.3 MHz
notes 6 and 14
weighted
M.3.16
M.3.17
M.3.18
M.3.19
60
60
56
60
66
66
62
66
−
−
−
−
dB
dB
dB
dB
yellow
signal-to-noise ratio
M.3.20
M.3.21
M.3.22
M.3.23
56
49
−
60
−
−
−
−
dB
unweighted
53
dB
residual carrier signal
note 6
5.5
2.5
mV
mV
residual 2nd harmonic of carrier note 6
signal
−
IF AND TUNER AGC; NOTE 15
Timing of IF-AGC
M.4.1
modulated video interference
30% AM for 1 mV to 100 mV; −
−
10
%
0 to 200 Hz (system B/G)
M.4.2
response time to IF input signal positive and negative
−
2
−
ms
amplitude increase of 52 dB
modulation
M.4.3
M.4.4
response to an IF input signal
amplitude decrease of 52 dB
negative modulation
positive modulation
−
−
50
−
−
ms
ms
100
Tuner take-over adjustment (via I2C-bus)
M.5.1
minimum starting level for tuner
take-over (RMS value)
−
0.4
0.8
mV
mV
M.5.2
maximum starting level for tuner
take-over (RMS value)
80
150
−
Tuner control output
M.6.1
M.6.2
M.6.3
maximum tuner AGC output
voltage
maximum tuner gain; note 3
−
−
5
−
−
−
8
V
output saturation voltage
minimum tuner gain;
IO = 2 mA
300
−
mV
mA
maximum tuner AGC output
swing
M.6.4
M.6.5
leakage current RF AGC
−
−
1
4
µA
input signal variation for
complete tuner control
0.5
2
dB
2001 Jan 18
79
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AFC OUTPUT (VIA I2C-BUS); NOTE 16
M.7.1
M.7.2
M.7.3
AFC resolution
−
−
−
2
−
−
−
bits
window sensitivity
125
275
kHz
kHz
window sensitivity in large
window mode
VIDEO IDENTIFICATION OUTPUT (VIA IFI BIT IN OUTPUT BYTE 00)
M.8.1
delay time of identification after
the AGC has stabilized on a new
transmitter
−
−
10
ms
2001 Jan 18
80
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
QSS Sound IF circuit
SOUND IF AMPLIFIER
input sensitivity (RMS value)
Q.1.1
Q.1.2
FM mode (−3 dB)
−
−
30
70
µV
AM mode (−3 dB)
60
100
µV
maximum input signal
(RMS value)
Q.1.3
Q.1.4
Q.1.5
Q.1.6
Q.1.7
Q.1.8
FM mode
AM mode
note 3
50
80
−
70
140
2
−
−
−
−
−
−
mV
mV
kΩ
pF
input resistance (differential)
input capacitance (differential)
gain control range
note 3
−
3
64
50
−
dB
dB
crosstalk attenuation between
SIF and VIF input
−
SOUND IF INTERCARRIER OUTPUT; WITH AM = 0
Q.2.1
output signal amplitude (RMS
value)
SC-1; sound carrier 2 off
75
100
125
mV
Q.2.2
Q.2.3
bandwidth (-3 dB)
7.5
10
2
−
−
MHz
mV
residual IF sound carrier (RMS
value)
−
Q.2.4
Q.2.5
Q.2.6
output resistance
DC output voltage
−
−
−
300
2.5
1.0
−
−
−
Ω
V
internal bias current of emitter
follower
mA
Q.2.7
Q.2.8
maximum AC and DC sink
current
−
−
1.0
1.0
−
−
mA
mA
maximum AC and DC source
current
Q.2.9
weighted S/N ratio (SC1/SC2). black picture
53/48
52/47
44/42
58/55
55/53
48/46
−
−
−
dB
dB
dB
Ratio of PC/SC1 at vision IF
Q.2.10
Q.2.11
white picture
input of 40 dB or higher, note 17
6 kHz sinewave
(black-to-white modulation)
Q.2.12
Q.2.13
Q.2.14
250 kHz sine wave
(black-to-white modulation)
44/25
48/30
51/50
52/51
−
−
−
dB
dB
dB
sound carrier subharmonics 45/44
(f=2.75 MHz ± 3 kHz)
sound carrier subharmonics 46/45
(f=2.87 MHz ± 3 kHz)
2001 Jan 18
81
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AM SOUND OUTPUT; DEPENDING ON SETTING OF CMB0/CMB1 AND AM BITS
Q.3.1
AF output signal amplitude
(RMS value)
54% modulation
400
500
600
mV
Q.3.2
Q.3.21
Q.3.3
Q.3.4
Q.3.5
Q.3.6
total harmonic distortion
total harmonic distortion
AF bandwidth
54% modulation
80% modulation
−3 dB
−
0.5
2.0
125
53
1.0
5.0
−
%
−
%
100
47
−
kHz
dB
V
weighted signal-to-noise ratio
DC output voltage
−
2.5
40
−
power supply ripple rejection
−
−
dB
FM demodulator and audio amplifier
FM-PLL DEMODULATOR; NOTE 18
G.1.2
G.1.3
G.1.4
gain control range AGC amplifier
26
−
30
−
−
−
dB
catching range PLL
note 19
note 20
±225
±100
kHz
µA
maximum phase detector output
current
−
G.1.5
G.1.6
VCO steepness ∆fFM/∆VC (K0)
−
−
3.3
9
−
−
MHz/V
phase detector steepness
∆IC/∆ϕVFM (KD)
µA/rad
G.1.7
AM rejection
40
46
1
−
dB
EXTERNAL SOUND IF INPUT (SNDIF, WHEN SELECTED)
G.1.8
input limiting for lock-in of PLL
(RMS value)
−
2
mV
G.1.9
input resistance
note 3
note 3
−
−
50
−
kΩ
G.1.10
input capacitance
−
1.0
pF
DE-EMPHASIS OUTPUT; NOTE 22
G.2.1
output signal amplitude (RMS
notes 19 and 21
−
500
−
mV
value)
G.2.2
G.2.3
G.2.31
output resistance
DC output voltage
−
−
−
15
3.2
50
−
−
−
kΩ
V
signal-to-noise ratio (RMS value) note 23
dB
AUDIO INPUT VIA DEEMPHASIS OUTPUT; NOTE 22
G.2.4
input signal amplitude (RMS
value)
−
500
−
mV
G.2.5
G.2.6
input resistance
−
−
15
9
−
−
kΩ
voltage gain between input and maximum volume
output
dB
2001 Jan 18
82
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Audio Amplifier
AUDIO OUTPUT OR VOLUME CONTROLLED AM-OUT
A.1.1
controlled output signal
amplitude (RMS value)
−6 dB; nominal audio input
signal
500
700
900
mV
A.1.2
A.1.3
A.1.4
A.1.6
A.1.7
A.1.8
A.1.10
A.1.11
output resistance
−
−
−
−
−
−
−
−
500
3.6
−
−
Ω
DC output voltage
−
V
total harmonic distortion
power supply rejection
internal signal-to-noise ratio
external signal-to-noise ratio
control range
note 24
0.5
−
%
note 6
2.5
50
60
80
80
dB
dB
dB
dB
dB
note 6 + 23 + 26
note 6 + 26
see also Fig.30
−
−
−
suppression of output signal
when mute is active
−
A.1.12
DC shift of the output when mute
is active
−
10
50
mV
EXTERNAL AUDIO INPUT
A.2.1
input signal amplitude (RMS
−
500
2000
mV
value)
A.2.2
A.2.3
input resistance
−
−
25
9
−
−
kΩ
voltage gain between input and maximum volume
output
dB
A.2.4
crosstalk between internal and
external audio signals
60
−
−
dB
AUTOMATIC VOLUME LEVELLING; NOTE 28
A.3.1
A.3.2
A.3.3
A.3.4
A.3.5
gain at maximum boost
gain at minimum boost
charge (attack) current
discharge (decay) current
−
−
−
−
−
6
−
−
−
−
−
dB
dB
mA
nA
V
-14
1
200
1
control voltage at maximum
boost
A.3.6
control voltage at minimum boost
−
5
−
V
2001 Jan 18
83
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CVBS, Y/C and RGB/YUV INPUTS
CVBS-Y/C SWITCH
S.1.1
CVBS or Y input voltage
(peak-to-peak value)
note 29
−
−
1.0
1.4
V
S.1.2
S.1.3
CVBS or Y input current
4
−
−
µA
suppression of non-selected
CVBS input signal
notes 6 and 30
50
−
dB
S.1.4
chrominance input voltage (burst note 3 and 31
amplitude)
−
0.3
50
1.0
V
S.1.5
chrominance input impedance
−
−
kΩ
CVBS OUTPUT ON IFVO2
S.1.9
output signal amplitude
−
2.0
−
V
(peak-to-peak value)
S.1.10
S.1.11
top sync level
−
−
1.8
−
V
output impedance
−
50
Ω
EXTERNAL RGB / YUV INPUT
S.2.1
RGB input signal amplitude for note 32
−
0.7
0.8
V
V
an output signal of 2 V
(black-to-white) (peak-to-peak
value)
S.2.2
RGB input signal amplitude
before clipping occurs
(peak-to-peak value)
note 6
1.0
−
−
S.2.3
S.2.4
S.2.5
S.2.6
Y input signal amplitude
(peak-to-peak value)
input signal amplitude for an
output signal of 2 V
(black-to-white); when
activated via the YUV1/YUV0
bits; note 33
−
−
−
−
1.4/1.0
2.0
2.0
1.5
20
V
U/PB input signal amplitude
(peak-to-peak value)
−1.33/
+0.7
V
V/PR input signal amplitude
(peak-to-peak value)
−1.05/
+0.7
V
difference between black level of
internal and external signals at
the outputs
−
mV
S.2.7
S.2.8
input currents
no clamping; note 3
note 6
−
−
0.1
0
1
µA
delay difference for the three
channels
20
ns
2001 Jan 18
84
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FAST INSERTION
S.3.1
S.3.2
S.3.3
S.3.4
input voltage
no data insertion
−
−
−
−
−
0.4
V
data insertion
insertion
0.9
−
−
V
maximum input pulse
3.0
20
V
delay time from RGB in to
RGB out
data insertion; note 6
−
ns
S.3.5
delay difference between
insertion to RGB out and RGB in
to RGB out
data insertion; note 6
−
−
20
ns
S.3.6
S.3.7
input current
−
−
−
0.2
mA
dB
suppression of internal RGB
signals
notes 6 and 30; insertion;
fi = 0 to 5 MHz
55
55
−
S.3.8
suppression of external RGB
signals
notes 6 and 30; no insertion;
fi = 0 to 5 MHz
−
−
dB
Chrominance and Luminance filters
CHROMINANCE TRAP CIRCUIT; NOTE 34
F.1.1
F.1.2
F.1.3
F.1.4
F.1.5
trap frequency
−
fosc
2.8
3.4
26
−
−
−
−
−
MHz
MHz
MHz
dB
Bandwidth at fSC = 3.58 MHz
Bandwidth at fSC = 4.43 MHz
colour subcarrier rejection
−3 dB
−3 dB
−
−
24
−
trap frequency during SECAM
reception
4.3
MHz
CHROMINANCE BANDPASS CIRCUIT
F.2.1
F.2.2
F.2.3
centre frequency (CB = 0)
−
−
−
fosc
−
−
−
MHz
MHz
centre frequency (CB = 1)
bandpass quality factor
1.1×fosc
3
CLOCHE FILTER
F.3.1
centre frequency
Bandwidth
4.26
241
4.29
268
4.31
295
MHz
kHz
F.3.2
Y DELAY LINE
F.4.1
F.4.2
F.4.3
delay time
note 6
−
480
−
−
ns
tuning range delay time
8 steps
−160
+160
ns
bandwidth of internal delay line note 6
8
−
−
MHz
2001 Jan 18
85
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Picture Improvement Features
PEAKING CONTROL; NOTE 35
P.1.1
P.1.2
width of preshoot or overshoot
note 3
−
−
160
−
−
ns
peaking signal compression
threshold
50
IRE
P.1.3
P.1.4
P.1.5
overshoot at maximum peaking positive
−
−
−
45
80
1.8
−
−
−
%
%
negative
Ratio negative/positive
overshoot; note 36
P.1.6
P.1.7
P.1.8
P.1.9
peaking control curve
63 steps
see Fig.31
peaking centre frequency
setting PF1/PF0 = 0/0
setting PF1/PF0 = 0/1
setting PF1/PF0 = 1/0
−
−
−
2.7
3.1
3.5
−
−
−
MHz
MHz
MHz
BLACK LEVEL STRETCHER; NOTE 37
P.2.1
P.2.2
P.2.3
P.2.4
Maximum black level shift
15
−1
−1
6
21
0
27
1
IRE
IRE
IRE
IRE
level shift at 100% peak white
level shift at 50% peak white
level shift at 15% peak white
−
3
8
10
2001 Jan 18
86
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Horizontal and vertical synchronization and drive circuits
SYNC VIDEO INPUT
H.1.1
H.1.2
H.1.3
sync pulse amplitude
note 3
50
300
350
mV
slicing level for horizontal sync
slicing level for vertical sync
note 38
note 38
−
−
50
35
−
−
%
%
HORIZONTAL OSCILLATOR
H.2.1
H.2.2
free running frequency
−
−
15625
−
Hz
%
spread on free running
frequency
−
±2
H.2.3
H.2.4
frequency variation with respect VP = 8.0 V ±10%; note 6
to the supply voltage
−
−
0.2
0.5
80
%
frequency variation with
temperature
T
amb = 0 to 70 °C; note 6
−
Hz
FIRST CONTROL LOOP; NOTE 39
H.3.1
H.3.2
H.3.3
holding range PLL
catching range PLL
−
±0.9
±0.9
24
±1.2
−
kHz
kHz
dB
note 6
±0.6
−
signal-to-noise ratio of the video
input signal at which the time
constant is switched
−
H.3.4
hysteresis at the switching point
−
3
−
dB
SECOND CONTROL LOOP
H.4.1
H.4.2
control sensitivity
−
−
150
19
−
−
µs/µs
µs
control range from start of
horizontal output to flyback at
nominal shift position
H.4.3
H.4.4
horizontal shift range
63 steps
note 40
±2
−
−
−
µs
control sensitivity for dynamic
compensation
−
7.6
µs/V
H.4.5
Voltage to switch-on the ‘flash’
protection
6.0
−
−
V
H.4.6
H.4.7
Input current during protection
−
−
−
1
mA
control range of the
parallelogram correction
note 41
note 41
±0.5
−
µs
H.4.8
control range of the bow
correction
−
±0.5
−
µs
2001 Jan 18
87
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HORIZONTAL OUTPUT; NOTE 42
H.5.1
H.5.2
H.5.3
H.5.4
H.5.5
LOW level output voltage
IO = 10 mA
−
−
−
−
0.3
V
maximum allowed output current
maximum allowed output voltage
duty factor
10
−
−
mA
V
VP
−
VOUT = LOW (TON
)
−
55
%
switch-on time of horizontal drive
pulse
−
1175
−
ms
H.5.6
switch-off time of horizontal drive
pulse
−
43
−
ms
FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT
H.6.1
required input current during
flyback pulse
note 3
100
−
300
µA
H.6.2
output voltage
during burst key
during blanking
4.8
2.3
2.6
5.3
2.5
3.0
5.8
2.7
3.4
V
V
V
H.6.3
clamped input voltage during
flyback
H.6.4
H.6.5
H.6.6
pulse width
burst key pulse
3.3
−
3.5
3.7
−
µs
vertical blanking, note 43
14/9.5
4.8
lines
µs
delay of start of burst key to start
of sync
4.6
5.0
VERTICAL OSCILLATOR; NOTE 44
H.7.1
H.7.2
H.7.3
H.7.4
free running frequency
−
50/60
−
Hz
locking range
45
−
64.5/72 Hz
divider value not locked
locking range
−
625/525
−
lines
434/488
−
722
lines/
frame
VERTICAL RAMP GENERATOR
H.8.1
sawtooth amplitude
VS = 1FH;
−
3.0
−
V
(peak-to-peak value)
C = 100 nF; R = 39 kΩ
H.8.2
H.8.3
discharge current
−
−
1
−
−
mA
charge current set by external
resistor
note 45
16
µA
H.8.4
H.8.5
H.8.6
vertical slope
63 steps; see Fig. 47
f = 60 Hz
−20
−
−
+20
−
%
%
V
charge current increase
LOW level of ramp
19
2.3
−
−
VERTICAL DRIVE OUTPUTS
H.9.1
differential output current
VA = 1FH
−
0.95
−
mA
(peak-to-peak value)
common mode current
output voltage range
H.9.2
H.9.3
−
400
−
µA
0
−
4.0
V
2001 Jan 18
88
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
EHT TRACKING/OVERVOLTAGE PROTECTION
H.10.1
H.10.2
H.10.3
H.10.4
H.10.5
H.10.6
input voltage
1.2
−
−
2.8
V
scan modulation range
vertical sensitivity
−5
−
+5
−
%
6.3
−6.3
−
%/V
%/V
µA
V
EW sensitivity
when switched-on
−
−
EW equivalent output current
overvoltage detection level
+100
−
−100
−
note 40
3.9
DE-INTERLACE
H.11.1
first field delay
−
0.5H
−
EW WIDTH; NOTE 46
H.12.1
H.12.2
H.12.3
H.12.4
control range
63 steps; see Fig. 50
100
0
−
−
−
−
65
%
equivalent output current
EW output voltage range
EW output current range
700
5.0
µA
V
1.0
0
1200
µA
EW PARABOLA/WIDTH
H.13.1
H.13.2
control range
equivalent output current
63 steps; see Fig. 51
0
−
−
23
%
EW=3FH; CP=11H; TC=1FH 0
450
µA
EW UPPER/LOWER CORNER/PARABOLA
H.14.1
H.14.2
control range
63 steps; see Fig. 52
−46
−
−
+17
+76
%
equivalent output current
PW=3FH; EW=3FH; TC=1FH −207
µA
EW TRAPEZIUM
H.15.1
H.15.2
control range
63 steps; see Fig. 53
−5
−
−
+5
%
equivalent output current
EW=1FH; CP=11H; PW=1FH −100
+100
µA
VERTICAL AMPLITUDE
H.16.1
H.16.2
control range
63 steps; see Fig. 46
SC = 0EH
80
−
−
120
%
equivalent differential vertical
drive output current
760
1140
µA
(peak-to-peak value)
VERTICAL SHIFT
H.17.1
H.17.2
control range
63 steps; see Fig. 48
−5
−
−
+5
%
equivalent differential vertical
drive output current
−50
+50
µA
(peak-to-peak value)
S-CORRECTION
H.18.1
control range
63 steps; see Fig. 49
−10
−
25
%
VERTICAL ZOOM MODE (OUTPUT CURRENT VARIATION WITH RESPECT TO NOMINAL SCAN); NOTE 47
H.19.1
H.19.2
vertical expand factor
0.75
−
1.38
output current limiting and RGB
blanking
−
1.05
−
2001 Jan 18
89
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Colour demodulation part
CHROMINANCE AMPLIFIER
D.1.1
D.1.2
ACC control range
note 48
26
−
−
−
dB
change in amplitude of the
output signals over the ACC
range
−
2
dB
D.1.3
D.1.4
threshold colour killer ON
hysteresis colour killer OFF
−30
−
−
−
dB
dB
strong signal conditions;
−
+3
S/N ≥ 40 dB; note 6
D.1.5
noisy input signals; note 6
−
−
+1
−
−
dB
ACL CIRCUIT; NOTE 49
D.2.1
chrominance burst ratio at which
the ACL starts to operate
3.0
REFERENCE PART
Phase-locked loop
D.3.1
D.3.2
catching range
±500
−
−
−
Hz
phase shift for a ±400 Hz
deviation of the oscillator
frequency
note 6
−
2
deg
HUE CONTROL
D.5.1
D.5.2
D.5.3
hue control range
63 steps; see Fig.32
note 6
±35
−
±40
0
−
−
−
deg
deg
deg
hue variation for ±10% VP
hue variation with temperature
Tamb = 0 to 70 °C; note 6
−
0
DEMODULATORS
General
D.6.3
spread of signal amplitude ratio note 6
between standards
−1
−
+1
dB
D.6.5
bandwidth of demodulators
−3 dB; note 50
−
650
−
kHz
PAL/NTSC demodulator
D.6.6
gain between both demodulators
G(B−Y) and G(R−Y)
1.60
1.78
0.1
−
1.96
−
D.6.12
D.6.13
D.6.14
change of output signal
amplitude with temperature
note 6
note 6
−
−
−
%/K
dB
change of output signal
amplitude with supply voltage
±0.1
±5
phase error in the demodulated note 6
signals
−
deg
2001 Jan 18
90
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SECAM demodulator
D.7.1
D.7.2
D.7.3
D.7.4
D.7.5
black level off-set
−
−
7
kHz
pole frequency of deemphasis
ratio pole and zero frequency
non linearity
77
−
85
3
93
−
kHz
−
−
3
%
V
calibration voltage
1.8
2.3
2.8
Base-band delay line
D.8.1
variation of output signal for
adjacent time samples at
constant input signals
−0.1
−
−
0.1
5
dB
D.8.2
residual clock signal
(peak-to-peak value)
−
mV
D.8.3
D.8.4
D.8.5
delay of delayed signal
63.94
40
64.0
60
−
64.06
80
µs
ns
%
delay of non-delayed signal
difference in output amplitude
with delay on or off
−
5
COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT)
PAL/SECAM mode; (R−Y) and (B−Y) not affected
D.9.1
ratio of demodulated signals
(G−Y)/(R−Y)
−
−
−0.51
±10%
−
−
D.9.2
ratio of demodulated signals
(G−Y)/(B−Y)
−0.19
±25%
NTSC mode; the matrix results in the following signals (nominal hue setting)
MUS-bit = 0
D.9.6
(B−Y) signal: 2.03/0°
(R−Y) signal: 1.59/95°
(G−Y) signal: 0.61/240°
2.03UR
D.9.7
−0.14UR + 1.58VR
−0.31UR − 0.53VR
D.9.8
MUS-bit = 1
D.9.9
(B−Y) signal: 2.20/−1°
(R−Y) signal: 1.53/99°
(G−Y) signal: 0.70/223°
2.20UR − 0.04VR
−0.24UR + 1.51VR
−0.51UR − 0.48VR
D.9.10
D.9.11
REFERENCE SIGNAL OUTPUT/SWITCH OUTPUT; NOTE 51
D.10.1
D.10.2
reference frequency
CMB1/CMB0 = 01
CMB1/CMB0 = 01
3.58/4.43
MHz
V
output signal amplitude
(peak-to-peak value)
0.2
0.25
0.3
D.10.3
D.10.4
D.10.5
output level (mid position)
output level LOW
CMB1/CMB0 = 01
CMB1/CMB0 = 10
CMB1/CMB0 = 11
2.3
−
2.5
−
2.7
0.8
−
V
V
V
output level HIGH
4.5
−
2001 Jan 18
91
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Control part
SATURATION CONTROL; NOTE 32
C.1.1
saturation control range
63 steps; see Fig.33
63 steps; see Fig.34
52
−
−
−
dB
CONTRAST CONTROL; NOTE 32
C.2.1
C.2.2
contrast control range
−
−
20
dB
dB
tracking between the three
channels over a control range of
10 dB
−
0.5
C.2.6
contrast reduction
−
−
−
10
−
−
−
dB
V
BRIGHTNESS CONTROL
C.3.1
brightness control range
63 steps; see Fig.35
±0.7
2.0
RGB AMPLIFIERS
C.4.1
output signal amplitude
(peak-to-peak value)
at nominal luminance input
signal, nominal settings for
contrast, white-point
V
adjustment and cathode drive
level(CL3-CL0 = 0111)
C.4.2
maximum signal amplitude
(black-to-white)
note 52
−
5.5
−
V
C.4.3
C.4.4
maximum peak white level
−
−
5.5
2.1
−
−
V
V
output signal amplitude for the
‘red’ channel (peak-to-peak
value)
at nominal settings for
contrast and saturation
control and no luminance
signal to the input (R−Y, PAL)
C.4.5
C.4.6
nominal black level voltage
black level voltage
−
−
2.5
2.5
−
−
V
V
when black level stabilisation
is switched-off (via AKB bit)
C.4.61
C.4.7
black level voltage control range AVG bit active; note 53
1.8
2.5
3.2
V
width of video blanking with HBL note 54
bit active
13.4
13.7
14.0
µs
C.4.71
C.4.72
C.4.8
timing of video blanking with
respect to mid sync (HBL = 1)
start of blanking; note 54
end of blanking; note 54
3.5
7.8
−
−
5.9
10.2
−
µs
µs
V
−
control range of the black-current
stabilisation
±1
C.4.81
C.4.9
RGB output level when RGBL=1
blanking level
−
−
−
0.8
−
−
−
V
V
V
difference with black level,
note 52
−0.5
−0.1
C.4.10
level during leakage
measurement
C.4.11
C.4.12
level during ‘low’ measuring
pulse
−
−
0.25
0.5
−
−
V
V
level during ‘high’ measuring
pulse; note 55
2001 Jan 18
92
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
C.4.13
PARAMETER
CONDITIONS
MIN.
TYP.
±3
MAX.
UNIT
dB
adjustment range of the cathode note 52
drive level
−
−
−
−
C.4.131
gain control range to
±6
dB
compensate spreads in picture
tube characteristics for the
2-point black -current
stabilization system; note 55
C.4.14
variation of black level with
temperature
note 6
−
−
1.0
−
−
mV/K
mV
C.4.141
black level off-set adjustment on 63 steps
the Red and Green channel
±160
C.4.21
C.4.22
C.4.23
C.4.24
C.4.25
C.4.26
signal-to-noise ratio of the output RGB input; note 56
60
50
−
−
−
−
dB
signals
CVBS input; note 56
−
dB
residual voltage at the RGB
outputs (peak-to-peak value)
at fosc
−
15
15
−
mV
mV
MHz
MHz
at 2fosc plus higher harmonics −
−
bandwidth of output signals
RGB input; at −3 dB
CVBS input; at −3 dB;
−
−
15
2.8
−
f
osc = 3.58 MHz
CVBS input; at −3 dB;
osc = 4.43 MHz
C.4.27
C.4.28
−
3.4
−
−
MHz
MHz
f
S-VHS input; at −3 dB
5
−
WHITE-POINT ADJUSTMENT
C.5.1
C.5.2
I2C-bus setting for nominal gain HEX code
−
−
20H
−
−
adjustment range of the relative
R, G and B drive levels
±3
dB
2-POINT BLACK-CURRENT STABILIZATION, NOTES 57
C.6.1
amplitude of ‘low’ reference
current
−
−
8
−
−
µA
µA
C.6.2
amplitude of ‘high’ reference
current; note 55
40
C.6.3
C.6.4
C.6.5
C.6.7
acceptable leakage current
maximum current during scan
input impedance
−
−
−
−
±75
2
−
−
−
−
µA
mA
Ω
500
0.1
minimum input current to
activate the guard circuit
IVG bit = “0”, note 58
mA
BEAM CURRENT LIMITING
C.7.1
C.7.2
C.7.3
C.7.4
contrast reduction starting
voltage
−
−
−
−
2.8
1.8
1.7
0.9
−
−
−
−
V
V
V
V
voltage difference for full contrast
reduction
brightness reduction starting
voltage
voltage difference for full
brightness reduction
2001 Jan 18
93
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
NUMBER
C.7.5
PARAMETER
internal bias voltage
CONDITIONS
MIN.
TYP.
3.3
MAX.
UNIT
−
−
−
−
−
−
V
C.7.6
C.7.7
detection level vertical guard
IVG bit = “1”; note 58
IVG bit = “1”; note 58
3.45
100
V
minimum input current to
activate the guard circuit
µA
C.7.8
maximum allowable current
−
1
−
mA
FIXED BEAM CURRENT SWITCH-OFF; NOTE 59
C.8.1
discharge current during
switch-off
0.85
1.0
38
1.15
mA
ms
C.8.2
discharge time of picture tube
−
−
Notes
1. When the 3.3 V supply is present and the µ-Controller is active a ‘low-power start-up’ mode can be activated. When
all sub-address bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 24H). In this condition the horizontal drive signal has the nominal TOFF and
the TON grows gradually from zero to the nominal value. As soon as the 8 V supply is present the switch-on procedure
(e.g. closing of the second loop) is continued.
2. On set AGC.
3. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
4. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
FPLL input signal level).
5. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the clock frequency of the µ-Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 27H. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
7. Measured at 10 mV (RMS) top sync input signal.
8. Via this pin both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
The selection between both signals is realised by means of the SVO bit in subaddress 22H.
9. So called projected zero point, i.e. with switched demodulator.
10. Measured in accordance with the test line given in Fig.36. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
11. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.37.
12. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal)
13. The test set-up and input conditions are given in Fig.38. The figures are measured with an input signal of
10 mV RMS. This test can only be carried out in a test set-up in which the test options of the IC can be activated.
This because the IF-AGC control input is not available in this IC.
2001 Jan 18
94
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
14. Measured at an input signal of 10 mVRMS. The S/N is the ratio of black-to-white amplitude to the black level noise
voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.
15. The time-constant of the IF-AGC is internal and the speed of the AGC can be set via the bits AGC1 and AGC0 in
subaddress 28H. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The
values given are valid for the ‘norm’ setting (AGC1-AGC0 = 0-1) and when the PLL is in lock.
16. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the
clock frequency of the µ-Controller/Teletext decoder as a reference and is therefore very accurate. For this reason
no maximum and minimum values are given for the window sensitivity figures (parameters M.7.2 and M.7.3). The
tuning information is supplied to the tuning system via the AFA and AFB bits in output byte 02H. The AFC value is
valid only when the LOCK-bit is 1.
17. The weighted S/N ratio is measured under the following conditions:
a) The vision IF modulator must meet the following specifications:
Incidental phase modulation for black-to-white jumps less than 0.5 degrees.
QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio) better
than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.
Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).
b) The measurements must be carried out with the Siemens SAW filters G3962 for vision IF and G9350 for sound
IF. Input level for sound IF 10 mVRMS with 27 kHz deviation.
c) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter
PC/SC ratio. This PC/SC ratio is necessary to achieve the S/N(W) values as indicated.
18. Calculation of the FM-PLL filter can be done approximately by use of the following equations:
K 0 K D
1
f
=
--------------
C P
------
2π
o
1
υ =
----------------------------------
2R K0KDCP
BL−3dB = f0(1.55 − υ2)
These equations are only valid under the conditions that υ ≤ 1 and CS >5CP.
Definitions:
K0 = VCO steepness in rad/V
KD = phase detector steepness µA/rad
R = loop filter resistor
CS = series capacitor
CP = parallel capacitor
f0 = natural frequency of PLL
BL−3dB = loop bandwidth for −3dB
υ = damping factor
Some examples for these values are given in table 132
19. Modulation frequency: 1 kHz, ∆f = ± 50 kHz.
20. f = 4.5/5.5 MHz; FM: 70 Hz, ± 50 kHz deviation; AM: 1.0 kHz, 30% modulation.
21. This figure is independent of the TV standard and valid for a frequency deviation of ±25 kHz at a carrier frequency
of 4.5 MHz or a deviation of ±50 kHz at a carrier frequency of 5.5/6.0/6.5 MHz.
2001 Jan 18
95
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
22. The deemphasis pin can also be used as additional audio input. In that case the internal (demodulated FM signal)
must be switched off. This can be realised by means of the SM (sound mute) bit. When the vision IF amplifier is
switched to positive modulation the signal from the FM demodulator is automatically switched off. The external signal
must be switched off when the internal signal is selected.
23. The signal-to-noise ratio is measured under the following conditions:
a) Input signal to the SNDIF pin (activated via SIF bit) with an amplitude of 100mVRMS, fMOD = 1 kHz and ∆f = 27 kHz
b) Output signal measured at the AUDEEM pin. The noise (RMS value) is measured according to the CCIR 468
definition.
24. Audio input signal 200 mVRMS. Measured with a bandwidth of 15 kHz and the audio attenuator at −6 dB.
25. Audio input signal 1 VRMS and the volume control setting such that no clipping occurs in the audio output.
26. Unweighted RMS value, audio input signal 500 mVRMS, audio attenuator at −6 dB.
27. Audio attenuator at −20 dB; temperature range 10 to 50 °C.
28. In various versions the Automatic Volume Levelling (AVL) function can be activated. The pin to which the external
capacitor has to be connected depends on the IC version. For the 90° types the capacitor is connected to the EW
output pin. For the 110° types a choice can be made between the AVL function and a sub-carrier output / general
purpose switch output. The selection must be made by means of the CMB0 and CMB1 bit in subaddress 22H. More
details about the sub-carrier output are given in the parameters D.10.
The Automatic Volume Levelling (AVL) circuit stabilises automatically the audio output signal to a certain level which
can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation
of the modulation depth of the transmitter. The AVL can be switched on and off via the AVL bit in subaddress 29H.
The AVL is active over an input voltage range (measured at the deemphasis output) of 150 to 1500 mVRMS. The AVL
control curve is given in Fig.39. The control range of +6 dB to −14 dB is valid for input signals with 50% of the
maximum frequency deviation.
29. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
30. This parameter is measured at nominal settings of the various controls.
31. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1).
32. The contrast and saturation control is active on the internal signal (YUV) and on the external RGB/YUV input. The
Text/OSD input can be controlled on brightness only. Nominal contrast is specified with the DAC in position 20 HEX.
Nominal saturation as maximum −10 dB.
33. The YUV input signal amplitudes are based on a colour bar signal with 75/100% saturation.
34. When the decoder is forced to a fixed subcarrier frequency (via the CM-bits) the chroma trap is always switched-on,
also when no colour signal is identified. In the automatic mode the chroma trap is switched-off when no colour signal
is identified.
35. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
36. The ratio between the positive and negative peaks can be varied by means of the bits RPO1 and RPO0 in
subaddress 2EH. For ratios which are smaller than 1.8 the positive peak is not affected and the negative peak is
reduced.
37. For video signals with a black level which deviates from the back-porch blanking level the signal is “stretched” to the
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.40). The black level is
detected by means of an internal capacitor. The black level stretcher can be switched on and off via the BKS bit in
subaddress 2DH. The values given in the specification are valid only when the luminance input signal has an
amplitude of 1 Vp-p
.
2001 Jan 18
96
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
38. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync
separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 Vp-p
.
The vertical slicing level is dependent on the S/N ratio of the incoming video signal. For a S/N ≤ 24 dB the slicing
level is 35%, for a S/N ≥ 24 dB the slicing level is 60%. With the bit FSL (Forced Slicing Level) the vertical slicing
level can be forced to 60%.
39. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the POC, FOA, FOB and VID bits in
subaddress 24H. The circuit contains a noise detector and the time constant is switched to ‘slow’ when too much
noise is present in the signal. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased
50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching of the time
constant can be automatically or can be set by means of the control bits.
The circuit contains a video identification circuit which is independent of the first loop. This identification circuit can
be used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input.
To prevent that the horizontal synchronisation is disturbed by anti copy signals like Macrovision the phase detector
is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width
of the gate pulse is about 22 µs. During weak signal conditions (noise detector active) the gating is active during the
complete scan period and the width of the gate pulse is reduced to 5.7 µs so that the effect of noise is reduced to a
minimum.
The output current of the phase detector in the various conditions are shown in Table 133.
40. The ICs have 2 protection inputs. The protection on the second phase detector pin is intended to be used as ‘flash’
protection. When this protection is activated the horizontal drive is switched-off immediately and then switched-on
again via the slow start procedure.
The protection on the EHT input is intended for overvoltage (X-ray) protection. When this protection is activated the
horizontal drive is directly switched-off (via the slow stop procedure).
The EHT protection input can also be used to switch-off the TV receiver in a correct way when it is switched off via
the mains power switch or when the power supply is interrupted by pulling the mains plug. This can be realised by
means of a detection circuit which monitors the main supply voltage of the receiver. When this voltage suddenly
decreases the EHT protection input must be pulled HIGH and then the horizontal drive is switched off via the slow
stop procedure. Whether the EHT capacitor is discharged in the overscan or not during the switch-off period depends
on the setting of the OSO bit (subaddress 25H, D4). See also note 59.
41. The control range indicates the maximum phase difference at the top and the bottom of the screen. Compared with
the phase position at the centre of the screen the maximum phase difference at the top and the bottom of the screen
is ±0.5 µs for both the parallelogram and the bow correction.
42. During switch-on the horizontal drive starts-up in a soft-start mode. The horizontal drive starts with a very short TON
time of the horizontal output transistor, the ‘off time’ of the transistor is identical to the ‘off time’ in normal operation.
The starting frequency during switch-on is therefore about 2 times higher than the normal value. The ‘on time’ is
slowly increased to the nominal value in a time of about 1175 ms (see Fig.43). The rather slow rise of the TON
between 75% and 100% of TON is introduced to obtain a sufficiently slow rise of the EHT for picture tubes with
Dynamic Astigmatic Focus (DAF) guns. When the nominal frequency is reached the PLL is closed in such a way that
only very small phase corrections are necessary. This ensures a safe operation of the output stage.
During switch-off the soft-stop function is active. This is realised by decreasing the TON of the output transistor
complimentary to the start-up behaviour. The switch-off time is about 43 ms (see Fig.43). When the ‘switch off
command’ is received the soft-stop procedure is started after a delay of about 2 ms. During the switch-off time the
EHT capacitor of the picture tube is discharged with a fixed beam current which is forced by the black current loop
(see also note 59). The discharge time is about 38 ms.
The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on
during the flyback time.
2001 Jan 18
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Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
43. The vertical blanking pulse in the RGB outputs has a width of 27 or 22 lines (50 or 60 Hz system). The vertical pulse
in the sandcastle pulse has a width of 14 or 9.5 lines (50 or 60 Hz system). This to prevent a phase distortion on top
of the picture due to a timing modulation of the incoming flyback pulse.
44. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
During TV reception this divider circuit has 3 modes of operation:
a) Search mode ‘large window’.
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines
per frame outside the range between 311 and 314(50 Hz mode) or between 261 and 264 (60 Hz mode) is
received). In the search mode the divider can be triggered between line 244 and line 361 (approximately
45 to 64.5 Hz).
b) Standard mode ‘narrow window’.
This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp
generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The
circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found
within the window.
c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are
in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched
to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical
sync pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 25H.
When RGB signals are inserted the maximum vertical frequency is increased to 72 Hz. This has the consequence
that the circuit can also be synchronised by signals with a higher vertical frequency like VGA.
45. Conditions: frequency is 50 Hz; normal mode; VS = 1F.
46. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 µA
variation in E-W output current is equivalent to 20% variation in picture width.
47. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason an extra DAC
has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38
of the nominal scan. At an amplitude of 1.06 of the nominal scan the output current is limited and the blanking of the
RGB outputs is activated. This is illustrated in Fig. 42.
a) The nominal scan height must be adjusted at a position of 19 HEX of the vertical ‘zoom’ DAC.
48. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)) the dynamic range of the ACC is +6 and −20 dB.
49. The ACL function can be activated by via the ACL bit in the subaddress 20H. The ACL circuit reduces the gain of the
chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0.
50. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass
filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.
51. The subcarrier output is combined with a 3-level switch output which can be used to switch external circuits like
sound traps etc. This output is controlled by the CMB1 and CMB0 bits in control byte 22H. The subcarrier signal is
available when CMB1/0 are set to 0/1. During the demodulation of SECAM signals the subcarrier signal is only
available during the vertical retrace period. The frequency is 4.43 MHz in this condition. When CMB1/0 are set to 00
in versions for 90° picture tubes (no EW output) the output is high ohmic.
2001 Jan 18
98
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
52. Because of the 2-point black current stabilization circuit both the black level and the amplitude of the RGB output
signals depend on the drive characteristic of the picture tube. The system checks whether the returning measuring
currents meet the requirement and adapts the output level and gain of the circuit when necessary. Therefore the
typical value of the black level and amplitude at the output are just given as an indication for the design of the RGB
output stage.
The 2-point black level system adapts the drive voltage for each cathode in such a way that the 2 measuring currents
have the right value. This has the consequence that a change in the gain of the output stage will be compensated
by a gain change of the RGB control circuit. Because different picture tubes may require different drive voltage
amplitudes the ratio between the output signal amplitude and the inserted measuring pulses can be adapted via the
I2C-bus. This is indicated in the parameter ‘Adjustment range of the cathode drive level’.
Because of the dependence of the output signal amplitude on the application the soft clipping limiting has been
related to the input signal amplitude.
53. The alignment system for the Vg2 voltage of the picture tube can be activated by means of the AVG bit. In that
condition a certain black level is inserted at the RGB outputs during a few lines. The value of this level can be
adjusted by means of the brightness control DAC. An automatic adjustment of the Vg2 of the picture tube can be
realised by using the WBC and HBC bits in output byte 01. For a black level feedback current between 12 and 20 µA
the WBC = 1, for a higher or lower current WBC = 0. Whether the current is too high or too low can be found from
the HBC bit. The indication of these bits can be made visible on the screen via OSD so that this alignment procedure
can also be used for service purposes.
54. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realised by means of a reduction of the horizontal
scan amplitude the edges of the picture may slightly be disturbed. This effect can be prevented by adding an
additional blanking to the RGB signals. The blanking pulse is derived form the horizontal oscillator and is directly
related to the incoming video signal (independent of the flyback pulse). This blanking is activated with the HBL bit.
55. This parameter is valid only when the CCC loop is active.
56. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).
57. This is a current input. The timing of the measuring pulses and the vertical blanking for the 50/60 Hz standard are
given in Fig.44
The start-up procedure is as follows.
When the TV receiver is switched-on the RGB outputs are blanked and the black-current loop will try to adjust the
picture tube to the right bias levels. The RGB drive signals are switched-on as soon as the black current loop is
stabilised. This results in the shortest switch-on time.
When this switch-on system results in a visible disturbance of the picture it is possible to add a further switch-on delay
via a software routine. In that case the RGB outputs must be blanked by means of the RBL bit. As soon as the black
current loop is stabilised the BCF-bit is set to 0 (output byte 01). This information can then be used to switch-on the
RGB outputs with some additional delay.
58. The input of the vertical guard function can be connected to the black current measuring input (BLKIN) or to the beam
current limiting input (BCLIN). The switching between these modes is realised by means of the IVG bit in subaddress
2BH. When the black current input is chosen it should be noted that for a reliable operation of the protection system
and the black current stabilization system the end of the protection pulse during normal operation should not overlap
the measuring pulses (see also Fig.44). Therefore this pulse must end before line 14.
2001 Jan 18
99
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
59. During switch-off the magnitude of the discharge current of the picture tube is controlled by the black current loop.
Dependent on the setting of the OSO bit the vertical scan can be stopped in an overscan position during that time so
that the discharge is not visible on the screen. The switch-off procedure is as follows:
a) When the switch-off command is received the RGB outputs are blanked for a time of about 2 ms.
b) If OSO = 1 the vertical scan is placed in an overscan position
c) If OSO = 0 the vertical deflection will keep running during the switch-off time
d) The soft-stop procedure is started with a reduction of the TON of the output stage from nominal to zero
e) The fixed beam current is forced via the black current loop
f) The soft-stop time has a value of 43 ms, the fixed beam current is flowing during a time of 38 ms.
Table 132 Some examples for the FM-PLL filter
BL−3dB (kHz)
CS (nF)
CP (nF)
R (kΩ)
ν
100
160
4.7
4.7
820
330
2.7
3.9
0.5
0.5
Table 133 Output current of the phase detector in the various conditions
I2C-BUS COMMANDS
IC CONDITIONS
ϕ-1 CURRENT/MODE
VID
POC
FOA
FOB
IFI
SL
NOISE
SCAN
V-RETR GATING MODE
−
−
−
−
−
−
−
−
0
−
0
0
0
0
0
0
0
−
0
1
0
0
0
0
0
1
1
1
−
−
0
0
0
1
1
0
0
1
−
−
yes
yes
yes
yes
yes
yes
yes
−
yes
yes
no
yes
no
yes
yes
−
no
yes
−
200
30
300
30
yes (1)
yes(2)
no
normal
normal
normal
slow
200
30
300
30
−
yes(2)
−
200
200
30
300
300
30
no
slow
no
yes
−
yes(2)
yes(2)
yes(1)
no
slow/fast
slow/fast
fast
200
6
300
6
no
−
−
OSD
−
−
−
−
−
−
off
Note
1. Gating is active during vertical retrace, the width is 22 µs. This gating prevents disturbance due to Macro Vision Anti
Copy signals.
2. Gating is continuously active and is 5.7 µs wide
2001 Jan 18
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Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
g
m
handbook, halfpage
1
fosc
=
----------------------------------------
Ci × Ctot
L ×
---------------------
2 π
Co
i
Ci
Ci + Ctot
276
kΩ
XTALIN
XTALOUT
X
C
a × Cb
C tot = Cp
+
-------------------
C
a + Cb
crystal
or
r
L
R
i
C
i
i
C
p
Ca = Ci + Cx1
Cb = Co + Cx2
Cx1
Cx2
MGR447
Fig.29 Simplified diagram crystal oscillator.
2001 Jan 18
101
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
%
0
dB
80
-20
60
40
20
-40
-60
-80
0
0
10
20
30
40
DAC (HEX)
−20
0
10
20
30
40
DAC (HEX)
Overshoot in direction ‘black’.
Fig. 31 Peaking control curve.
Fig. 30 Volume control curve
MLA740 - 1
300
%
+50
(deg)
250
+30
+10
−10
200
150
100
50
−30
−50
0
10
20
30
40
DAC (HEX)
0
10
20
30
40
DAC(HEX)
Fig.32 Hue control curve.
Fig. 33 Saturation control curve.
2001 Jan 18
102
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Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
MLA742 - 1
MLA741 - 1
0.7
(V)
100
(%)
90
80
70
60
50
40
30
20
10
0.35
0
0.35
0.7
0
0
10
20
30
40
0
10
20
30
40
DAC (HEX)
DAC (HEX)
Fig. 34 Contrast control curve.
Fig. 35 Brightness control curve.
MBC212
MBC211
100%
92%
16 %
100%
86%
72%
58%
44%
30%
30%
µs
32 36 40 44 48 52 56 60 64
10 12
22 26
for negative modulation
100% = 10% rest carrier
Fig. 36 Video output signal.
Fig. 37 Test signal waveform.
2001 Jan 18
103
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
3.2 dB
10 dB
13.2 dB
13.2 dB
30 dB
30 dB
SC CC
PC
SC CC
PC
MBC213
BLUE
YELLOW
PC
Σ
TEST
CIRCUIT
SPECTRUM
ANALYZER
SC
ATTENUATOR
gain setting
adjusted for blue
CC
MBC210
Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier.
All amplitudes with respect to top sync level.
VO at 3.58 or 4.4 MHz
Value at 0.92 or 1.1 MHz = 20 log
Value at 2.66 or 3.3 MHz = 20 log
+ 3.6 dB
------------------------------------------------------------
VO at 0.92 or 1.1 MHz
VO at 3.58 or 4.4 MHz
------------------------------------------------------------
VO at 2.66 or 3.3 MHz
Fig. 38 Test set-up intermodulation.
2001 Jan 18
104
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
CHARACTERISTIC POINTS AVL
A
B
C
D
UNIT
Deemphasis voltage
FM swing
150
15
300
30
500
50
1500
mVRMS
kHz
150
1.8
1.0
AVL is OFF
AVL is ON
A
D
C
B
100.0m
10.0m
1.0
100.0m
2.0
DEEMP
Fig. 39 AVL characteristic
2001 Jan 18
105
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
OUTPUT (IRE)
100
80
60
40
20
B
INPUT (IRE)
0
B
100
40
60
80
20
A
-20
A
A-A: MAXIMUM BLACK LEVEL SHIFT
B-B: LEVEL SHIFT AT 15% OF PEAK WHITE
Fig. 40 I/O relation of the black level stretch circuit
2001 Jan 18
106
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
100
95
BLUE
GREEN (BLS=1)
RED (BLS=1)
90
85
80
85
90
95
100
Peak white level (%)
Fig.41 Blue stretch characteristic
2001 Jan 18
107
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
TOP
PICTURE
%
60
50
138%
40
30
20
10
100%
75%
TIME
T/2
T
0
-10
-20
-30
-40
-50
-60
BOTTOM
PICTURE
BLANKING FOR EXPANSION OF 138%
Fig. 42 Vertical position and blanking pulse for 110° types
2001 Jan 18
108
100
75
Soft stop
Soft start
TON
(%)
50
43
57
73
1045
12
Time (ms)
Discharge current
picture tube
38
Fig. 43 Soft start and soft stop behaviour of horizontal output and timing picture tube discharge current
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
2001 Jan 18
110
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
TEST AND APPLICATION INFORMATION
East-West output stage
The value of REW must be:
Vscan
REW = R ×
----------------------
c
In order to obtain correct tracking of the vertical and
horizontal EHT-correction, the EW output stage should be
dimensioned as illustrated in Fig.45.
18 × Vref
Example: With Vref = 3.9 V; Rc = 39 kΩ and Vscan = 120 V
then REW = 68 kΩ.
Resistor REW determines the gain of the EW output stage.
Resistor Rc determines the reference current for both the
vertical sawtooth generator and the geometry processor.
The preferred value of Rc is 39 kΩ which results in a
reference current of 100 µA (Vref = 3.9 V).
V
b
DD
HORIZONTAL
V
scan
DEFLECTION
STAGE
R
ew
UOC series
DIODE
MODULATOR
V
EW
15
EWD
EW output
stage
20
21
V
ref
R
C
c
saw
39 kΩ
(2%)
100 nF
(5%)
MLA744 - 1
I
ref
Fig.45 East-West output stage
2001 Jan 18
111
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Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
700
500
IVERT
(µA)
300
100
-100
-300
-500
-700
0
T/2
TIME
T
VA = 0, 1FH and 3FH; VSH = 1FH; SC = 0EH.
VS = 0, 1FH and 3FH; VA = 1FH; VSH = 1FH; SC = 0EH.
Fig. 46 Control range of vertical amplitude.
Fig. 47 Control range of vertical slope.
IVERT
(µA)
600
400
200
0
-200
-400
-600
TIME
T/2
T
0
VSH = 0, 1FH and 3FH; VA = 1FH; SC = 0EH.
SC = 0, 0EH and 3FH; VA = 1FH; VSH = 1FH.
Fig. 48 Control range of vertical shift.
Fig. 49 Control range of S-correction.
2001 Jan 18
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Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
IEW
IEW
(µA)
500
(µA)
1200
1000
800
600
400
400
300
200
100
200
0
0
0
0.m
TIME8.m
0
TIME
T
T/2
T/2
T
0
PW = 0, 1FH and 3FH; EW = 3FH; TC = 1FH; CP = 11H.
EW = 0, 1FH and 3FH; PW = 3FH; TC = 1FH; CP = 11H.
Fig. 51 Control range of EW parabola/width ratio.
Fig. 50 Control range of EW width.
IEW
IEW
(µA)
(µA)
650
600
500
400
300
200
100
0
600
550
500
450
400
0
0
TIME
T
T/2
0.0
400.0m
800.0m
350
1
TIME
T/2
T
0
CP = 0, 11H and 3FH; EW = 3FH; PW = 3FH; TC = 1FH.
TC = 0, 1FH and 3FH; EW = 1FH; PW = 1FH; CP = 11H.
Fig. 52 Control range of EW corner/parabola ratio.
Fig. 53 Control range of EW trapezium correction.
2001 Jan 18
113
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Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
Adjustment of geometry control parameters
The first method is recommended for picture tubes that
have a marking for the middle of the screen. With the
vertical shift control the last line of the visible picture is
positioned exactly in the middle of the screen. After this
adjustment the vertical shift should not be changed. The
top of the picture is placed by adjustment of the vertical
amplitude, and the bottom by adjustment of the vertical
slope.
The deflection processor offers 5 control parameters for
picture alignment, viz:
• S-correction
• vertical amplitude
• vertical slope
• vertical shift
The second method is recommended for picture tubes that
have no marking for the middle of the screen. For this
method a video signal is required in which the middle of the
picture is indicated (e.g. the white line in the circle test
pattern). With the vertical slope control the beginning of the
blanking is positioned exactly on the middle of the picture.
Then the top and bottom of the picture are placed
symmetrical with respect to the middle of the screen by
adjustment of the vertical amplitude and vertical shift.
After this adjustment the vertical shift has the right setting
and should not be changed.
• horizontal shift.
The 110° types offer in addition:
• EW width
• EW parabola width
• EW upper/lower corner parabola
• EW trapezium correction.
• Vertical zoom
• Horizontal parallelogram and bow correction
It is important to notice that the ICs are designed for use
with a DC-coupled vertical deflection stage. This is the
reason why a vertical linearity alignment is not necessary
(and therefore not available).
If the vertical shift alignment is not required VSH should be
set to its mid-value (i.e. VSH = 1F). Then the top of the
picture is placed by adjustment of the vertical amplitude
and the bottom by adjustment of the vertical slope. After
the vertical picture alignment the picture is positioned in
the horizontal direction by adjustment of the EW width and
the horizontal shift. Finally (if necessary) the left- and
right-hand sides of the picture are aligned in parallel by
adjusting the EW trapezium control.
For a particular combination of picture tube type, vertical
output stage and EW output stage it is determined which
are the required values for the settings of S-correction, EW
parabola/width ratio and EW corner/parabola ratio. These
parameters can be preset via the I2C-bus, and do not need
any additional adjustment. The rest of the parameters are
preset with the mid-value of their control range (i.e. 1FH),
or with the values obtained by previous TV-set
adjustments.
To obtain the full range of the vertical zoom function the
adjustment of the vertical geometry should be carried out
at a nominal setting of the zoom DAC at position 19 HEX.
The vertical shift control is meant for compensation of
off-sets in the external vertical output stage or in the
picture tube. It can be shown that without compensation
these off-sets will result in a certain linearity error,
especially with picture tubes that need large S-correction.
The total linearity error is in first order approximation
proportional to the value of the off-set, and to the square of
the S-correction needed. The necessity to use the vertical
shift alignment depends on the expected off-sets in vertical
output stage and picture tube, on the required value of the
S-correction, and on the demands upon vertical linearity.
For adjustment of the vertical shift and vertical slope
independent of each other, a special service blanking
mode can be entered by setting the SBL bit HIGH. In this
mode the RGB-outputs are blanked during the second half
of the picture. There are 2 different methods for alignment
of the picture in vertical direction. Both methods make use
of the service blanking mode.
2001 Jan 18
114
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Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
PACKAGE OUTLINE
SDIP64: plastic shrink dual in-line package; 64 leads (750 mil)
SOT274-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
64
33
pin 1 index
E
1
32
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
58.67
57.70
17.2
16.9
3.2
2.8
19.61
19.05
20.96
19.71
mm
0.51
4.57
5.84
1.778
19.05
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-13
95-02-04
SOT274-1
2001 Jan 18
115
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
SOLDERING
Introduction
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC package Databook” (order code 9398 652 90011).
WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
SDIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
QFP
REFLOW SOLDERING
REPAIRING SOLDERED JOINTS
Reflow soldering techniques are suitable for all QFP
packages.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in our “Quality Reference
Handbook” (order code 9397 750 00192).
2001 Jan 18
116
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2001 Jan 18
117
Philips Semiconductors
Tentative Device Specification
TV signal processor-Teletext decoder with
embedded µ-Controller
TDA935X/6X/8X PS/N2 series
2001 Jan 18
118
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