SVF531R3K2CMK4R [NXP]
Standard JTAG;Document Number VYBRIDRSERIESEC
Rev. 8, 01/2018
NXP Semiconductors
Data Sheet: Technical Data
VYBRIDRSERIESEC
VF3xxR, VF5xxR
Features
• Debug
– Standard JTAG
– 16-bit Trace port
• Operating characteristics
– Voltage range 3 V to 3.6 V
– Temperature range(ambient) -40 °C to 85 °C
• Timers
– Motor control/general purpose timer (FTM)
– Periodic Interrupt Timers (PITs)
– Low-power timer (LPTMR0)
– IEEE 1588 Timer per MAC interface (part of
Ethernet Subsystem)
• ARM® Cortex® A5 Core features
– Up to 400 MHz ARM® Cortex® A5 core
– 32 KB/32 KB I/D L1 Cache
– 1.6 DMIPS/MHz based on ARMv7 architecture
– NEON™ MPE (Media Processing Engine) Co-
processor
• Communications
– Double Precision Floating Point Unit
– 512 KB L2 cache (on selected part numbers only)
– Six Universal asynchronous receivers/transmitters
(UART)/Serial communications interface (SCI) with
LIN, ISO7816, IrDA, and hardware flow control
– Four Deserial Serial peripheral interface (DSPI)
– Four Inter-Integrated Circuit (I2C) with SMBUS
support
– Dual USB OTG Controller + PHY
– Dual 4/8 bit Secure Digital Host controller
– Local Media Bus (MLB50)
• ARM Cortex M4 Core features
– Up to 133 MHz ARM Cortex M4
– Integrated DSP capability
– 64 KB Tightly Coupled Memory (TCM)
– 16 KB/16 KB I/D L1 Cache
– 1.25 DMIPS/MHz based on ARMv7 architecture
• Clocks
– Dual 10/100 Ethernet (IEEE 1588)
– Dual FlexCAN3
– 24 MHz crystal oscillator
– 32 kHz crystal oscillator
– Internal reference clocks (128 KHz and 24 MHz)
– Phase Locked Loops (PLLs)
– Low Jitter Digital PLLs
• Security
– ARM TrustZone including the TZ architecture
– Secure Non-Volatile Storage (SNVS)
– Real Time Clock
• System debug, protection, and power management
– Various stop, wait, and run modes to provide low
power based on application needs
– Real Time Integrity Checker (RTIC)
– TrustZone Watchdog (TZ WDOG)
– Trust Zone Address Space Controller
– Random Number Generator
– Hashing
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low voltage warning and detect with selectable trip
points
– Illegal opcode and illegal address detection with
programmable reset or processor exception response
– Hardware CRC module to support fast cyclic
redundancy checks (CRC)
– 128-bit unique chip identifier
– Hardware watchdog
– External Watchdog Monitor (EWM)
– Dual DMA controller with 32 channels (with
DMAMUX)
– Secure JTAG
• Memory Interfaces
– 8/16-bit DRAM Controller with support for
LPDDR2/DDR3 - Up to 400 MHz (ECC supported
for 8-bit only and not 16-bit)
– 8/16-bit NAND Flash controller with ECC (ECC
supported for 8-bit only and not 16-bit)
– Dual Quad SPI with XIP (Execute-In-Place)
– 8/16/32-bit External bus (Flexbus)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Display and Video
– Dual Display Control Unit (DCU) with support for color TFT display up to WVGA
– Segmented LCD (3V Glass only) configurable as 40x4, 38x8, and 36x6
– Video Interface Unit (VIU) for camera
– Open VG Graphics Processing Unit (GPU)
– VideoADC
• Analog
– Dual 12-bit SAR ADC with 1MS/s
– Dual 12-bit DAC
• Audio
– Four Synchronous Audio Interface (SAI)
– Enhanced Serial Audio Interface (ESAI)
– Sony Philips Digital Interface (SPDIF), Rx and Tx
– Asynchronous Sample Rate Converter (ASRC)
• Human-Machine Interface (HMI)
– GPIO pins with interrupt support, DMA request capability, digital glitch filter.
– Hysteresis and configurable pull up/down device on all input pins
– Configurable slew rate and drive strength on all output pins
• On-Chip Memory
– 512 KB On-chip SRAM with ECC
– 1 MB On-chip graphics SRAM (no ECC). This depends on the part selected. Alternate configuration could be 512 KB
graphics and 512 KB L2 cache.
– 96 KB Boot ROM
VF3xxR, VF5xxR, Rev. 8, 01/2018
2
NXP Semiconductors
Table of Contents
1
2
Ordering parts.....................................................................................5
6.2.5.1
Power Down Mode............................. 20
1.1 Determining valid orderable parts ..........................................5
Part identification...............................................................................5
2.1 Description.............................................................................. 5
2.2 Part Number Format................................................................5
2.3 Part Numbers ..........................................................................6
Terminology and guidelines...............................................................7
3.1 Definition: Operating requirement..........................................7
3.2 Definition: Operating behavior............................................... 8
3.3 Definition: Attribute................................................................8
3.4 Definition: Rating....................................................................8
3.5 Result of exceeding a rating....................................................9
3.6 Relationship between ratings and operating requirements......9
3.7 Guidelines for ratings and operating requirements................. 10
3.8 Definition: Typical value........................................................ 10
3.9 Typical Value Conditions........................................................11
Handling ratings.................................................................................11
4.1 ESD handling ratings ............................................................. 11
4.2 Thermal handling ratings........................................................ 12
4.3 Moisture handling ratings........................................................12
Operating Requirements.....................................................................12
5.1 Thermal operating requirements............................................. 12
General............................................................................................... 12
6.1 AC electrical characteristics....................................................12
6.2 Nonswitching electrical specifications ...................................13
6.2.6
EMC radiated emissions operating behaviors........ 21
EMC Radiated Emissions Web Search Procedure
boilerplate............................................................... 21
Capacitance attributes............................................. 21
6.2.7
6.2.8
7
8
I/O parameters....................................................................................22
7.1 GPIO parameters.....................................................................22
3
7.1.1
Output Buffer Impedance measurement................. 24
7.2 DDR parameters......................................................................24
Power supplies and sequencing..........................................................28
8.1 Power sequencing ...................................................................28
8.2 Power supply...........................................................................29
8.3 Absolute maximum ratings..................................................... 31
8.4 Recommended operating conditions....................................... 32
8.5 Recommended Connections for Unused Analog Interfaces... 33
Peripheral operating requirements and behaviours............................34
9.1 Analog..................................................................................... 34
9
4
9.1.1
9.1.2
9.1.3
12-bit ADC electrical characteristics......................34
9.1.1.1
9.1.1.2
12-bit ADC operating conditions........34
12-bit ADC characteristics..................35
5
6
12-bit DAC electrical characteristics......................39
9.1.2.1
9.1.2.2
12-bit DAC operating requirements....39
12-bit DAC operating behaviors......... 39
VideoADC Specifications.......................................43
9.2 Display and Video interfaces.................................................. 45
6.2.1
VREG electrical specifications ..............................13
9.2.1
DCU Switching Specifications............................... 45
6.2.1.1
6.2.1.2
6.2.1.3
6.2.1.4
6.2.1.5
HPREG electrical characteristics........ 13
LPREG electrical characteristics.........14
ULPREG electrical characteristics......14
WBREG electrical characteristics.......15
External NPN Ballast.......................... 15
9.2.1.1
9.2.1.2
Interface to TFT panels (DCU0/1)......45
Interface to TFT LCD Panels—Pixel
Level Timings..................................... 46
Interface to TFT LCD panels—access
level.....................................................47
9.2.1.3
6.2.2
6.2.3
LVD electrical specifications .................................17
9.2.2
9.2.3
Video Input Unit timing..........................................48
LCD driver electrical characteristics...................... 49
6.2.2.1
6.2.2.2
Main Supply electrical characteristics 17
LVD DIG characteristics.....................18
9.3 Ethernet specifications............................................................ 50
LDO electrical specifications .................................18
9.3.1
9.3.2
9.3.3
Ethernet Switching Specifications.......................... 50
Receive and Transmit signal timing specifications 50
Receive and Transmit signal timing specifications
for MII interfaces.................................................... 51
6.2.3.1
6.2.3.2
6.2.3.3
LDO_1P1............................................ 18
LDO_2P5............................................ 19
LDO_3P0 ........................................... 19
6.2.4
6.2.5
Power consumption operating behaviors................20
USB PHY current consumption..............................20
9.4 Audio interfaces...................................................................... 53
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
3
9.4.1
Enhanced Serial Audio Interface (ESAI) Timing
Parameters...............................................................53
SPDIF Timing Parameters......................................55
SAI/I2S Switching Specifications.......................... 56
9.7.4
9.7.5
9.7.6
Slow internal RC oscillator (128 KHz) electrical
characteristics..........................................................84
PLL1 and PLL2 (528 MHz System PLL)
9.4.2
9.4.3
Electrical Parameters.............................................. 84
PLL3 and PLL7 (480 MHz USB PLL) Electrical
Parameters...............................................................84
PLL5 (Ethernet PLL) Electrical Parameters...........85
PLL4 (Audio PLL) Electrical Parameters...............85
PLL6 (Video PLL) Electrical Parameters...............85
9.5 Memory interfaces...................................................................58
9.5.1
9.5.2
9.5.3
9.5.4
QuadSPI timing.......................................................58
NAND flash controller specifications.....................61
FlexBus timing specifications.................................64
DDR controller specifications................................ 66
9.7.7
9.7.8
9.7.9
9.5.4.1
9.5.4.2
9.5.4.3
9.5.4.4
9.5.4.5
9.5.4.6
DDR3 Timing Parameters ..................66
DDR3 Read Cycle...............................68
DDR3 Write cycle...............................69
LPDDR2 Timing Parameter................70
LPDDR2 Read Cycle.......................... 71
LPDDR2 Write Cycle......................... 72
9.8 Debug specifications............................................................... 86
9.8.1
9.8.2
JTAG electricals..................................................... 86
Debug trace timing specifications...........................88
10 Thermal attributes.............................................................................. 89
10.1 Thermal attributes................................................................... 89
11 Dimensions.........................................................................................90
11.1 Obtaining package dimensions ...............................................90
12 Pinouts................................................................................................91
12.1 Pinouts.....................................................................................91
12.2 Pinout diagrams.......................................................................103
9.6 Communication interfaces.......................................................73
9.6.1
9.6.2
MediaLB (MLB) DC Characteristics..................... 73
MediaLB (MLB) Controller AC Timing Electrical
Specifications..........................................................73
DSPI timing specifications..................................... 75
I2C timing...............................................................78
SDHC specifications...............................................80
USB PHY specifications.........................................81
9.6.3
9.6.4
9.6.5
9.6.6
12.2.1
12.2.2
GPIO Mapping........................................................105
Special Signal ........................................................ 109
13 Power Supply Pins............................................................................. 111
13.1 Power Supply Pins.................................................................. 111
14 Functional Assignment Pins...............................................................112
14.1 Functional Assignment Pins....................................................112
15 Revision History.................................................................................121
9.7 Clocks and PLL Specifications............................................... 81
9.7.1
9.7.2
9.7.3
24 MHz Oscillator Specifications...........................81
32 KHz Oscillator Specifications........................... 82
Fast internal RC oscillator (24 MHz) electrical
characteristics..........................................................83
VF3xxR, VF5xxR, Rev. 8, 01/2018
4
NXP Semiconductors
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web.
1. To determine the orderable part numbers for this device, go to www.nxp.com and
search the required part number. The part numbering format is described in the
section that follows.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Part Number Format
The figure below represents the format of part number of this device.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
5
Part identification
R
MK 2
K1 C
S V 3 1 1 R 3
F
Tape & Reel
R = Tape & Reel
(Optional)
Qualification Status
P = engineering samples
S = automotive qualified
Speed (A5 core)
2 = 266MHz
4 = 400MHz
Brand: V = Vybrid
Series: F = current
Family
Package
KU = 176LQFP
3 = Standard
MK = 364BGA
5 = Advanced
Core
1 = Cortex A5
2 = Cortex A5 + M4
3 = M4 Primary
Temp Spec
C = -40 to +85C Ta
Option
K1 = 2N02G with VADC
Graphics
1 = No Open VG
=
K2 3N02G with VADC
2 = Open VG
=
N2 3N02G with no VADC
Version
R = Auto
Memory Option
3 = Standard (1.5MB SRAM)
2 = Optional (1MB SRAM and 512K L2 Cache)
Figure 1. Part Number Format
2.3 Part Numbers
This table lists the part numbers on the device.
Part Number
SVF311R3K2CKU2
SVF312R3K2CKU2
SVF321R3K2CKU2
SVF322R3K2CKU2
SVF331R3K2CKU2
SVF332R3K2CKU2
Mask
3N02G
VADC
YES
Package
Description
A5-266, 176LQFP-EP
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
3N02G
3N02G
3N02G
3N02G
3N02G
YES
YES
YES
YES
YES
A5-266, OpenVG GPU, 176LQFP-EP
A5-266, M4, 176LQFP-EP
A5-266, M4, OpenVG GPU, 176LQFP
A5-266, M4 Primary, 176LQFP-EP
A5-266, M4 Primary, OpenVG GPU,
176LQFP-EP
SVF511R3K2CMK4
SVF512R3K2CMK4
SVF521R3K2CMK4
SVF522R2K2CMK4
3N02G
3N02G
3N02G
3N02G
YES
YES
YES
YES
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
A5-400, 364BGA
A5-400, OpenVG GPU, 364BGA
A5-400, M4, 364BGA
A5-400, M4, L2 Cache, OpenVG GPU,
364BGA
SVF522R3K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, M4, OpenVG GPU, 364BG
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
6
NXP Semiconductors
Terminology and guidelines
Description
Part Number
SVF531R3K2CMK4
SVF532R2K2CMK4
Mask
3N02G
VADC
YES
Package
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, 364BG
3N02G
YES
A5-400, M4 Primary, L2 Cache OpenVG
GPU, 364BGA
SVF532R3K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, OpenVG GPU,
364BGA
SVF311R3N2CKU2
SVF312R3N2CKU2
SVF321R3N2CKU2
SVF322R3N2CKU2
SVF331R3N2CKU2
SVF332R3N2CKU2
3N02G
3N02G
3N02G
3N02G
3N02G
3N02G
NO
NO
NO
NO
NO
NO
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
LQFP-EP 176 24*24*1.6
A5-266, 176LQFP-EP
A5-266, OpenVG GPU, 176LQFP-EP
A5-266, M4, 176LQFP-EP
A5-266, M4, OpenVG GPU, 176LQFP
A5-266, M4 Primary, 176LQFP-EP
A5-266, M4 Primary, OpenVG GPU,
176LQFP-EP
SVF511R3N2CMK4
SVF512R3N2CMK4
SVF521R3N2CMK4
SVF522R2N2CMK4
3N02G
3N02G
3N02G
3N02G
NO
NO
NO
NO
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
A5-400, 364BGA
A5-400, OpenVG GPU, 364BGA
A5-400, M4, 364BGA
A5-400, M4, L2 Cache, OpenVG GPU,
364BGA
SVF522R3N2CMK4
SVF531R3N2CMK4
SVF532R2N2CMK4
3N02G
3N02G
3N02G
NO
NO
NO
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
MAP 364 17*17*1.5 P0.8
A5-400, M4, OpenVG GPU, 364BG
A5-400, M4 Primary, 364BG
A5-400, M4 Primary, L2 Cache OpenVG
GPU, 364BGA
SVF532R3N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, OpenVG GPU,
364BGA
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
7
Terminology and guidelines
3.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
VF3xxR, VF5xxR, Rev. 8, 01/2018
8
NXP Semiconductors
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
9
Terminology and guidelines
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
VF3xxR, VF5xxR, Rev. 8, 01/2018
10
NXP Semiconductors
Handling ratings
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
4 Handling ratings
4.1 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-2000
-500
Max.
2000
500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up Current at ambient temperature of 85 °C
1
2
V
-100
100
mA
1. Determined according to the AEC spec AEC-Q100-002 for HBM
2. Determined according to AEC spec AEC-Q100-011
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
11
Operating Requirements
4.2 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
260
245
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
Solder temperature, leaded
1
2
TSDR
°C
—
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5 Operating Requirements
5.1 Thermal operating requirements
Table 1. Thermal operating requirements
Symbol
TA
Description
Min.
–40
—
Max.
85
Unit
°C
Ambient temperature
Junction temperature
TJ
105
°C
6 General
6.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VF3xxR, VF5xxR, Rev. 8, 01/2018
12
NXP Semiconductors
Nonswitching electrical specifications
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
6.2 Nonswitching electrical specifications
6.2.1 VREG electrical specifications
6.2.1.1 HPREG electrical characteristics
Table 2. HPREG electrical characteristics
Parameters
Power supply
Min
Typ
3.3
Max
3.6
Unit
V
Comments
-
3.0
Current Consumption
-
-
-
1.2
1.5
mA
mA
mA
V
@ no load
@ full load
DC load current
2.0
2.5
12001
Output current capacity
Output voltage @ no load
Output voltage @ full load
External decoupling cap
600
1.23
1.21
1.26
1.20
4.7
V
-
μF
-
0.05
0.1
Ohms
ESR of external
cap
20
mOhms
dB
Total effective
PAD+PCB trace
resistances
PSRR with 4.7uF output cap
@ DC @noload
-48
-40
-20
@ DC @full load
@ worst case any frequency
1. This is peak and not continuous maximum value.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
13
VREG electrical specifications
6.2.1.2 LPREG electrical characteristics
Table 3. LPREG electrical characteristics
Parameters
Power supply
Min
3.0
350
-
Typ
3.3
Max
Unit
V
Comments
3.6
Current Consumption
400
500
100
1.22
μA
@ no load
@ full load
650
200
μA
Output current capacity
Output voltage @ no load
Output voltage @ full load
External decoupling cap
mA
V
DC load current
1.240
1.180
4.7
V
μF
0.05
0.1
20
Ohms
mOhms
ESR of external cap
Total PAD+PCB trace
resistance
PSRR with 4.7uF output cap
@ DC @noload
-40
-35
-12
dB
@ DC @full load
Worst case @ any frequency
6.2.1.3 ULPREG electrical characteristics
Table 4. ULPREG electrical characteristics
Parameters
Min
3.0
1.88
-
Typ
3.3
Max
3.6
Unit
V
Comments
Power supply
Current Consumption
2.3
2.86
670
20
μA
μA
mA
V
@ no load
@ full load
610
Output current capacity
DC load current
Output voltage @ no load
Output voltage @ full load
PSRR with 500 pF output cap
1.175
1.125
-20
V
dB
Worst case at any frequency
across corners
@ DC @noload
-50
-37
-42
-37
-15
dB
@200KHz @noload
@ DC @full load
@200KHz @full load
Worst case @ any frequency
@ any load
VF3xxR, VF5xxR, Rev. 8, 01/2018
14
NXP Semiconductors
VREG electrical specifications
6.2.1.4 WBREG electrical characteristics
Table 5. WBREG electrical characteristics
Parameters
Power supply
Min
Typ
3.3
2
Max
3.6
5
Unit
V
Comments
-
3
-
Current Consumption
µA
µA
mA
V
@ no load
@ full load
DC load current
-
2
5
Output current capacity
Output voltage @ no load
Output voltage @ full load
Output voltage programmability
-
1
2
1.4
1.398
1.4
1.425
1.375
1.4
V
1.7
V
16 steps of 25
mV each
6.2.1.5 External NPN Ballast
The internal main regulator requires an external NPN ballast transistor to be connected as
shown in the following figure as well as an external capacitance to be connected to the
device in order to provide a stable 1.2V digital supply to the device. The HPREG design
allows for collector voltage lower than VDDREG value. See AN4807 at www.nxp.com .
NOTE
To not overload BCTRL output, collector voltage should appear
no later than VDDREG / VDD33 (3.3V).
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
15
VREG electrical specifications
Figure 3. External NPN Ballast connections
Table 6. BCTRL OUTPUT specification
Parameter
Value
Comments
BCTRL OUTPUT specification
20mA
BCTRL driver can not drive more than
20mA current
Maximum pin voltage
VDDREG-0.5V
For Example, VDDREG =3.0V BCTRL
should not exceed 2.5V.
Table 7. Assumptions For calculations
Parameter
Value
VDDREG
3.0V to 3.6V with typical value of 3.3V
0.85A @85 °C
Max DC Collector current
Emitter voltage
1.2V to 1.25V
Collector voltage
Equal to VDDREG
Table 8. General guidelines for selection of NPN ballast
Symbol
Parameters
Value
Unit
Comments
Hfe
Minimum DC
current gain (Beta)
42.5
As BCTRL pin can not drive more than
20mA Minimum value of beta for a
collector current of 0.85A comes out to
be 42.5.
PD (Junction to
ambient)
Minimum power
dissipation @
TA=85 °C
2.04
W
Assuming 0.85A collector current with
Collector voltage of Ballast 3.6V(max)
we get VCE= 3.6V-1.2V=2.4V So power
dissipated is 2.4V*0.85A=2.04W . This
should be met for junction to ambient
power dissipation spec of ballast
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
16
NXP Semiconductors
LVD electrical specifications
Table 8. General guidelines for selection of NPN ballast (continued)
Symbol
Parameters
Value
Unit
Comments
IcmaxDC peak
Maximum peak DC
collector current
0.85
A
1.2A and above capacity device
preferable
VBE
Maximum voltage 1.25V for 0.85A @
V
For a VDDREG of 3.0 V (min.), BCTRL
pin can drive voltage up to VDDREG -
0.5 V = 2.5 V. Since emitter of ballast is
fixed at 1.25 V (max) if chosen ballast
can supply 0.85 A collector current @ 85
°C with a base-to-emitter voltage of 1.25
V or lower, it is suitable for application.
that BCTRL pin can
drive
85 °C
Ft
Unity current gain
Frequency of
Ballast
50
MHz
Reducing the collector-to-emitter voltage drop lowers the ballast transistor heat
dissipation. This can be implemented in two ways:
1. By introducing series resistor or diode(s) between the collector and VDDREG
(placed far enough from the transistor for proper cooling)
2. By connecting the collector to a separate lower-voltage supply
In both of the above cases the transistor has to stay away from the deep saturation region;
otherwise, due to significant Hfe degradation, its base current exceeds the BCTRL output
maximum value.
In general, the transistor must be selected such that its Vce saturation voltage is lower
than the expected minimum Collector-Emitter voltage, and at the same time, the base
current is less than 20 mA for the maximum expected collector current. More information
can be found in collateral documentation at http://www.nxp.com
6.2.2 LVD electrical specifications
6.2.2.1 Main Supply electrical characteristics
Table 9. LVD_MAIN supply electrical characteristics
Main Supply LVD
Parameters
Min
Typ
Max
Unit
Comments
Power supply
3.0
3.3
3.6
V
V
Upper voltage threshold
(value @27oC)
2.76
2.915
Lower voltage threshold
(value @27oC)
2.656
3.3
2.73
V
Time constant of RC filter at
LVD input (0.69*RC)
μs
3.3 V noise rejection at LVD
comparator input
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
17
LDO electrical specifications
6.2.2.2 LVD DIG characteristics
Table 10. LVD DIG electrical specifications [HPREG(RUN MODE) and LPREG(STOP
MODE)]
LVD DIG
Min
Typ
Max
Unit
Comments
Parameters
Power supply
3.0
3.3
3.6
V
V
Upper voltage
threshold
1.135
1.16
1.185
Lower voltage
threshold
1.105
200
1.13
1.155
V
Time constant of
RC filter at LVD
input
ns
1.2V noise rejection at the input of
LVD comparator
Table 11. LVD DIG electrical specifications [ULPREG(STANDBY
MODE)]
LVD DIG Parameters
Power supply
Min
3.0
Typ
3.3
Max
3.6
Unit
V
Comments
Upper voltage threshold
Lower voltage threshold
1.105
1.075
200
1.13
1.10
1.155
1.125
V
V
Time constant of RC filter at
LVD input
ns
1.2V noise rejection at the
input of LVD comparator
6.2.3 LDO electrical specifications
6.2.3.1 LDO_1P1
Table 12. LDO_1P1 parameters
Specification
VDDIO
Min
Typ
Max
Unit
Comments
IO supply
3
3.3
1.1
3.6
1.2
150
1.4
V
VDD1P1_OUT
I_out
0.9
-
V
Regulator output
>= 300mV drop out
mA
V
Regulator output
programming range
0.8
1.1
Programmable in
25mV steps
Brownout Voltage 0.85
0.94
-
V
Brownout offset
step
0
175
-
mV
Programmable in
25mV steps
Minimum external
decoupling
1
-
µF
low ESR
capacitor
VF3xxR, VF5xxR, Rev. 8, 01/2018
18
NXP Semiconductors
LDO electrical specifications
For additional information, see the device reference manual.
6.2.3.2 LDO_2P5
Table 13. LDO_2P5 parameters
Specification
VDDIO
Min
Typ
Max
Unit
Comments
IO supply
3
3.3
2.5
3.6
V
VDD2P5_OUT
I_out
2.3
-
2.6
V
Regulator output
@500mV drop out
350
2.75
mA
V
Regulator output
programming range
2.0
2.5
Programmable in
25mV steps
[P:][C:] Brownout
Voltage
2.25
0
2.33
V
Brownout offset
step
-
-
175
-
mV
µF
Programmable in
25mV steps
Minimum external
decoupling
1
low ESR
capacitor
For additional information, see the reference manual.
6.2.3.3 LDO_3P0
Table 14. LDO_3P0 parameters
Specification
Min
Typ
Max
Unit
Comments
Input OTG VBUS
Supply
4.4
5.25
5.25
3.1
V
Input HOST VBUS 4.4
Supply
V
VDD3P0_OUT
2.9
3.0
V
Regulator output at
default setting
I_out
-
50
mA
V
500 mV drop-out
voltage
Regulator output
programming range
2.625
2.75
0
3.4
Programmable in
25mV steps
[P:][C:] Brownout
Voltage
2.85
V
Brownout offset
step
-
-
175
-
mV
µF
Programmable in
25mV steps
Minimum external
decoupling
1
low ESR
capacitor
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
19
LDO electrical specifications
NOTE
These values are with Anadig_REG_3P0[ENABLE_ILIMIT]=
0 and Anadig_REG_3P0[ENABLE_LINREG]= 1. It is required
to set these values before using USB.
6.2.4 Power consumption operating behaviors
Table 15. Power consumption operating behaviors
Symbol
Description
Typ.1
Max.2
Unit
Notes
IDD_RUN
Run mode current — All functionalities of the chip
available
400
850
mA
IDD_WAIT
Wait mode high frequency current at 3.3 V 10ꢀ
80
13
500
325
mA
mA
3
4
IDD_LPRUN
Low-power run mode current at 3.3 V 10ꢀ,
24MHz operation, PLL Bypass.
IDD_ULPRUN
IDD_STOP
Ultra-low-power run mode current at 3.3 V 10ꢀ
Stop mode current at 3.3 V 10ꢀ
12
7
395
300
mA
mA
uA
5
6
7
IDD_LPS2FIRC/IDD_LPS3FIRC Low power stop 2/low power stop 3 with FIRC
enabled, current at 3.3 V 10ꢀ
300
1300
IDD_LPS2/IDD_LPS3
Low power stop 2/low power stop 3 with FIRC
disabled, current at 3.3 V 10ꢀ
50
5
875
45
uA
uA
7
8
IDD_VBAT
Battery backup mode
1. The Typ numbers represent the average value taken from a matrix lot of parts across normal process variation at ambient
temperature.
2. The Max numbers represent the single worst case value taken from a matrix lot of parts across normal process variation at
maximum temperature.
3. CA5, CM4 cores halted
4. 24MHz operation, PLL Bypass
5. 32 kHz /128 kHz operation, PLL Off
6. Lowest power mode with all power retained, RAM retention and LVD protection.
7. Standby Mode. 64K and 16K RAM retention. ADCs/DACs optionally power-gated. RTC functional. Wakeup from interrupts.
8. All supplies OFF, SRTC, 32kXOSC ON, tampers and monitors ON. 128k IRC optionally ON.
6.2.5 USB PHY current consumption
6.2.5.1 Power Down Mode
Everything powered down, including the VBUS valid detectors, typ condition.
Table 16. USB PHY Current Consumption in Normal Mode
USBx_VBUS
(3.0V)
VDD33_LDOIN
(2.5V)
VDD33_LDOIN
(1.1V)
Avg
Avg
Avg
Current
5.1 μA
1.7 μA
<0.5 μA
VF3xxR, VF5xxR, Rev. 8, 01/2018
20
NXP Semiconductors
LDO electrical specifications
NOTE
The currents on the 2.5 voltage regulator and 3.0 voltage
regulator were identified to be the voltage divider circuits in the
USB-specific level shifters.
6.2.6 EMC radiated emissions operating behaviors
Table 17. EMC radiated emissions operating behaviors
Symbol
Condition1
Clocks
Frequency
band 2
Level
Unit
(Typ)3
VEME
Device Configuration, test conditions and EM testing
per standard IEC 61967-2; Supply voltages: VDD= 5.0 MHz FBUS
V VDD33 = 3.3 V VDD15 = 1.5 V VDD12 = 1.2 V
Temp = 25°C
FCPU = 396 150 KHz –
22
24
25
dBμV
50 MHz
= 66 MHz
External
Crystal = 24
MHz
50 MHz –
150 MHz
150 MHz –
500 MHz
500–1000
IEC level4
20
K
—
1. Measurements were made per IEC 61967-2 while the device was running basic application code.
2. Measurements were performed on the BGA364 version of the device
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from
among the measured orientations in each frequency range.
4. IEC Level Maximums: N ≤ 12dBmV, M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV
6.2.7 EMC Radiated Emissions Web Search Procedure boilerplate
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
6.2.8 Capacitance attributes
Table 18. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
CIN_D
Input capacitance:
analog pins
—
—
7
7
pF
pF
Input capacitance:
digital pins
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
21
I/O parameters
7 I/O parameters
7.1 GPIO parameters
Table 19. GPIO DC operating conditions
Symbol
Parameter
Min
Typ
Max
Unit
vddi1
Core internal
1.2
V
supply voltage
ovdd
I/O output
3
3.3
3.6
V
supply voltage
1. This is internally controlled.
Table 20. GPIO DC Electrical characteristics
Symbol
Parameter
High-level
output voltage
Test condition
Min
Typ
Max
Unit
Voh
Ioh= -1mA
ovdd-0.15
V
VOH/VOL
values are with
respect to
DSE=0011
Vol
Low-level output Iol= 1mA
voltage
0.15
V
V
V
Vih 2
Vil2
High-Level DC
input voltage
0.7*ovdd
0
ovdd
Low-Level DC
input voltage
0.3*ovdd
Vhys
Vt+2, 3
Input Hysteresis ovdd=3.3 V
250
mV
V
Schmitt trigger
VT+
0.5*ovdd
Vt-2, 3
Iin4
Schmitt trigger
VT-
0.5*ovdd
1
V
Input current (no Vin = ovdd or 0 -1
pull-up/down)
uA
uA
Iin_22pu
Input current
(22KOhm PU)
Vin = 0
212
1
Vin = ovdd
Vin = 0
Iin_47pu
Iin_100pu
Iin_100pd
Input current
(47KOhm PU)
100
1
Vin = ovdd
Vin = 0
Input current
(100KOhm PU)
50
1
Vin = ovdd
Vin = 0
Input current
1
(100KOhm PD)
Vin = ovdd
50
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
22
NXP Semiconductors
I/O parameters
Unit
Table 20. GPIO DC Electrical characteristics (continued)
Symbol
R_Keeper
Parameter
Test condition
Min
Typ
Max
Keeper Circuit
Resistance
Vin = 0.3 x
OVDD VI = 0.7 x
OVDD
105
175
7
Ohm
Issod
Issop
Sink current in
open drain
mode
Vin = ovdd
mA
mA
Sink/source
current in Push
Pull mode
Vin = ovdd
7
1. For details about Software MUX Pad Control Register DSE bit, see IOMUX Controller chapter of the device reference
manual.
2. To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current
DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1ns to 1s. Vil and Vih do not
apply when hysteresis is enabled.
3. Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4. Typ condition: typ model, 3.3V, and 25°C. Max condition: bcs model, 3.6V, and -40°C. Min condition: wcs model, 3.0V and
85 °C. These values are for digital IO buffer cells.
Table 21. GPIO AC Electrical Characteristics (3.3V power mode)
Symbol
tpr
Parameter
Drive strength1
Slew
rate
Test conditions
Min
Max
Unit
IO Output Transition Max 1 1 1
Times (PA1), rise/fall
slow
15pF Cload on pad, 1.70
input edge rate 200ps
1.81
ns
ns
ns
fast
1.04
1.18
2.44
1.79
3.31
2.61
5.44
5.18
5.04
3.10
5.68
3.55
6.67
4.11
7.60
6.10
5.21
3.28
5.80
3.71
6.80
High 1 0 1
Medium 1 0 0
Low 0 1 1
slow
fast
2.30
1.69
slow
fast
3.07
2.45
slow
fast
5.13
4.79
tpo
IO Output
Propagation Delay
(PA2), rise/fall
Max 1 1 1
slow
fast
15pF Cload on pad, 5.01
input edge rate 200ps
3.06
High 1 0 1
Medium 1 0 0
Low 0 1 1
slow
fast
5.55
3.52
slow
fast
6.37
4.04
slow
fast
7.39
5.54
tpv
Output Enable to
Output Valid Delay,
rise/fall
Max 1 1 1
slow
fast
15pF Cload on pad, 5.12
input edge rate
200ps, 0->1, 1->0
pad transitions
3.18
High 1 0 1
slow
fast
5.72
3.67
6.55
Medium 1 0 0
slow
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
23
I/O parameters
Table 21. GPIO AC Electrical Characteristics (3.3V power mode) (continued)
Symbol
Parameter
Drive strength1
Slew
rate
Test conditions
Min
Max
Unit
fast
4.06
4.09
Low 0 1 1
slow
7.80
5.72
8.19
6.22
1.31
1.41
fast
tpi
Input Pad
without hysteresis
with hysteresis
-
-
150f Cload on, input 1.06
ns
Propagation Delay
rise/fall
edge rate from pad
=1.2ns
1.22
1. The drive strengths are controlled by the DSE bit of the Software MUX Pad Control Register. For details, see IOMUX
Controller chapter of the device reference manual.
7.1.1 Output Buffer Impedance measurement
Table 22. Output Buffer Average Impedance (3.3V power mode)
Symbol
Rdrv
Parameter
Drive strength1
Min
Typ
Max
Unit
Output driver 0 0 1
impedance
116
58
39
30
24
20
150
75
50
37
30
25
220
110
73
Ohm
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
58
46
38
Extra drive strength
1 1 1
17
20
32
1. The drive strengths are controlled by the DSE bit of the Software MUX Pad Control Register. For details, see IOMUX
Controller chapter of the device reference manual.
7.2 DDR parameters
Table 23. DDR operating conditions
Symbol
vddi
Parameter
Min
1.16
Typ
1.23
1.5
Max
1.26
Unit
V
Core internal supply voltage
ovdd
I/O output supply voltage
(DDR3 mode)
1.425
1.575
V
ovdd
I/O output supply voltage
(LPDDR2 mode)
1.14
2.25
1.2
2.5
1.26
2.75
V
V
vdd2p5
I/O PD predriver and level
shifters supply voltage
VF3xxR, VF5xxR, Rev. 8, 01/2018
24
NXP Semiconductors
I/O parameters
Notes
Table 24. LPDDR2 mode DC Electrical characteristics
Symbol
Voh
Parameter
Test
Min
Typ
Max
Unit
condition
High-level
output voltage
0.9*ovdd
V
V
V
Note that the
JEDEC
LPDDR2
specification
(JESD209_2B
) supersedes
any
specification
in this
Vol
Low-level
output voltage
0.1*ovdd
Vref
Input
0.49*ovdd
0.5*ovdd
0.51*ovdd
reference
voltage
Vih(dc)
Vil(dc)
DC input high
voltage
Vref+0.13
ovss
ovdd
V
V
V
document.
DC input low
voltage
Vref-0.13
Note1
Vih(diff)
DC differential
input logic
high
0.26
Vil(diff)
Iin2
DC differential
input logic low
Note1
-0.26
2.5
V
Input current Vin = ovdd or
uA
(no pull-up/
down)
0
Tri-state I/O
supply
Icc-ovdd
Vin = ovdd or
0
4
current2
Tri-state
Icc-vdd2p5
Vi = vddi or 0
1.5
1
vdd2p5 supply
current2
Tri-state core Icc-vddi
supply
current2
Driver unit
(240 Ohm)
calibration
resolution
Rres
10
Ohm
1. The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well
as the limitations for overshoot and undershoot.
2. Typ condition: typ model, 1.2 V, and 25 °C junction. Max condition: bcs model, 1.26V, and -40 °C. Min condition: wcs
model, 1.14V, and Tj 125 °C.
Table 25. DDR3 mode DC Electrical characteristics
Symbol
Voh
Vol
Parameter
Test
condition
Min
Typ
Max
Unit
Notes
High-level
output voltage
0.8*ovdd
V
V
Note that the
JEDEC
JESD79_3E
specification
supersedes
any
Low-level
output voltage
Iol= 1mA
0.2*ovdd
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
25
I/O parameters
Table 25. DDR3 mode DC Electrical characteristics (continued)
Symbol
Parameter
Test
Min
Typ
Max
Unit
Notes
condition
specification
in this
document
Vref
Input
reference
voltage
0.49*ovdd
0.5*ovdd
0.51*ovdd
V
Vih(dc)
Vil(dc)
DC input high
voltage
Vref+0.1
ovss
ovdd
V
V
V
DC input low
voltage
Vref-0.1
Note1
Vih(diff)
DC differential
input logic
high
0.2
Vil(diff)
Vtt2
DC differential
input logic low
Note1
-0.2
V
Termination
voltage
Vin = ovdd or 0.49*ovdd
0
0.5*ovdd
0.51*ovdd
3
Iin3
Input current Vi = 0 Vi =
uA
(no pullup/
pulldown)
ovdd
Tri-state I/O
supply
Icc-ovdd
Vin = ovdd or
0
5
current3
Tri-state
Icc-vdd2p5
Vi = vddi or 0
1.5
1
vdd2p5 supply
current3
Tri-state core Icc-vddi
supply
current3
Driver unit
(240 Ohm)
calibration
resolution
Rres
10
Ohm
1. The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well
as the limitations for overshoot and undershoot.
2. Vtt is expected to track ovdd/2.
3. Typ condition: typ model, 1.5 V, and 25 °C. Max condition: bcs model, 1.575V, and -40 °C. Min condition: wcs model,
1.425V, and max Tj °C 125 °C junction
Table 26. LPDDR2 mode AC Electrical characteristics
Symbol
Vih(ac)
Parameter
Test condition
Min
Max
Unit
Notes
AC input logic
high
Vref+0.22
ovdd
V
V
V
Note that the
Jedec LPDDR2
specification
(JESD209-2B)
supersedes any
specification in
this document.
Vil(ac)
AC input logic
low
Vref-0.22
-
Vidh(ac)1
AC differential
input high
voltage
0.44
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
26
NXP Semiconductors
I/O parameters
Table 26. LPDDR2 mode AC Electrical characteristics (continued)
Symbol
Vidl(ac)1
Parameter
Test condition
Min
Max
Unit
Notes
AC differential
input low voltage
0.44
0.12
V
V
Vix(ac)2
AC differential
Relative to
-0.12
input crosspoint ovdd/2
voltage
Vpeak
Varea
Over/undershoot
peak
0.35
0.3
V
Over/undershoot at 800MHz data
V*ns
area (above
ovdd or below
ovss)
rate
tsr
Single output
slew rate
0.4
2
V/ns
ns
tskd
Skew between
pad rise/fall
asymmetry +
skew cased by
SSN
0.2
1. Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac)-Vil(ac).
2. The typical value of Vix(ac) is expected to be about 0.5*ovdd, and Vix(ac) is expected to track variation of ovdd. Vix(ac)
indicates the voltage at which differential input signal must cross.
Table 27. DDR3 mode AC Electrical characteristics
Symbol
Vih(ac)
Parameter
Test condition
Min
Max
Unit
Notes
AC input logic
high
Vref+0.175
ovdd
V
V
V
Note that the
JEDEC
JESD79_3E
specification
supersedes any
specification in
this document
Vil(ac)
AC input logic
low
ovss
0.35
Vref-0.175
-
Vidh(ac)1
AC differential
input high
voltage
Vidl(ac)1
Vix(ac)2
AC differential
input low voltage
0.35
V
V
AC differential
relative to
Vref-0.15
Vref+0.15
input crosspoint ovdd/2
voltage
Vpeak
Varea
Over/undershoot
peak
0.4
0.5
V
Over/undershoot at 800 MHz data
V*ns
area (above
ovdd or below
ovss)
rate
tsr
Single output
slew rate
0.4
2
V/ns
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
27
Power supplies and sequencing
Table 27. DDR3 mode AC Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min
Max
Unit
Notes
tskd
Skew between
pad rise/fall
asymmetry +
skew cased by
SSN
0.2
ns
1. Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac)-Vil(ac).
2. The typical value of Vix(ac) is expected to be about 0.5*ovdd, and Vix(ac) is expected to track variation of ovdd. Vix(ac)
indicates the voltage at which differential input signal must cross.
8 Power supplies and sequencing
8.1 Power sequencing
Table 28. Power sequencing
Power Supply (PKG Board Level
Parameters
Power
Order
Comment
Level)
Power Nets
VBAT
VBAT
Battery supply in case of LDOIN
fails
NA
VDD33_LDOIN
VDDREG
VDD33
VDD33
VDD33
LDO input supply (LDO1P1,
LDO2P5, LDO1P1_RTC)
1
VDD33_LDOIN,VDDREG and
VDD33 should come from a
common supply source
(represented as 3.3V SMPS in
the Figure 4)
Device PMU regulator and
External ballast supply
1
VDD33
GPIO 3.3V IO supply, LCD Supply
1
SDRAMC_VDD1P5 SDRAMC_VDD1P5 1.2/1.5 DDR Main IO supply
NA
In case the Ballast transistor’s
collector is connected to the
1.5V DRAM supply (instead of
the 3.3V supply), turn this
1.5V supply on before turning
on the 3.3V.
VDDA33_ADC
VDDA33_ADC
3.3V supply for ADC, DAC and IO
segment
1
VREFH_ADC
VDDA33_AFE
VDD12_AFE
FA_VDD
VREFH_ADC
VDDA33_AFE
VDD
High Reference of ADC, DAC
3.3V supply of AFE (Video ADC)
1.2V supply for AFE (Video ADC)
1
1
2
VDD
Shorted with VDD at Board Level
in 364BGA (Test pin only)
NA
VDD
VDD
1.2V core supply from External
ballast
2
USB0_VBUS 1
USB1_VBUS 2
USB_VBUS
USB_VBUS
VBUS supply for USB
VBUS supply for USB
NA
NA
1. Power sequencing of USB0_VBUS is independent of any other power supply.
VF3xxR, VF5xxR, Rev. 8, 01/2018
28
NXP Semiconductors
Power supplies and sequencing
2. Power sequencing of USB1_VBUS is independent of any other power supply.
NOTE
NA stands for no sequencing needs, for example, the supply
can come in any order.
NOTE
All supplies grouped together e.g. 1,2, others. These have no
power sequencing restriction in between them.
NOTE
If none of the SDRAMC pins are connected on the board, the
SDRAMC supply could be left floating.
NOTE
At power up, 1.2V supply will follow 3.3V supply. At power
down, it should be checked that 1.2V falls before 3.3V.
NOTE
The standby current on USBx_VBUS is 300 - 500 uA. This is
well below the 2.5 mA limit set by the USB 2.0 specification.
This supply will be ON for applications that need to monitor the
USB bus during standby. This supply can be turned-off during
standby in applications that cannot tolerate the standby current
and do not monitor the USB bus.
8.2 Power supply
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
29
Power supplies and sequencing
10uF
VDDA33_AFE
BCTRL
VDD
4.7uF
VDD
VideoADC
HPREG
LPREG
VDDREG
PD1
WELL
*
WBREG
48K
16K
3.3V
ULPREG
VDD33_LDOIN
VDD33
PD0
DAC x 2
12-bit SAR
ADC x 2
VDDA33_ADC
VREFH_ADC
eFUSE
USB 0/1 PHY
PLLs
1.5V/1.2V DDR Supply
SDRAMC_VDD1P5
LDO2P5
COIN
cell
SDRAMC_VDD2P5
DDR IO
PLLs
DECAP_V25_LDO_OUT
DECAP_V11_LDO_OUT
LDO1P1
Battery supply
(See note)
SNVS
LDO
SNVS
LDO3P0
USB_DCAP
USB0_VBUS (5V)
USB1_VBUS (5V)
Figure 4. Power supply
NOTE
VBAT is the backup battery supply. If not required, then VBAT
should be tied to VDDREG.
NOTE
WBREG is the Well Bias Regulator. Supplies PD1 WELL
during well bias modes.
VF3xxR, VF5xxR, Rev. 8, 01/2018
30
NXP Semiconductors
Power supplies and sequencing
8.3 Absolute maximum ratings
NOTE
These are the values above which device can get damaged.
Refer to the recommended operating conditions table for
intended use case values
Table 29. Absolute maximum ratings
Symbol
Parameters
Min
-
Max
5.25
5.25
3.6
Unit
V
USB0_VBUS
USB1_VBUS
USB_DCAP
USB0_DP
USB0_DN
USB1_DP
USB1_DN
VBAT
VBUS supply for USB
VBUS supply for USB
USB LDO 5V->3.3V Outpu
USBx data line input voltage
-
V
-0.3
-0.3
V
3.6
V
Battery supply in case of LDOIN
fails
-0.3
3.6
V
VDD33_LDOIN
LDO input supply
-0.3
-0.3
-0.3
3.6
1.3
3.6
V
V
V
DECAP_V11_LDO_OUT
DECAP_V25_LDO_OUT
LDO 3.3V -> 1.1V Output
LDO 3.3V -> 2.5 Output for PLL,
DDR, EFUSE
VDD33
GPIO 3.3V IO supply
-0.3
-0.3
3.6
3.6
V
V
VDDREG
Device PMU regulator and
External ballast supply
VDDA33_ADC
3.3V supply for ADC, DAC and IO
segment
-0.3
3.6
V
VREFH_ADC
VDDA33_AFE
VDD12_AFE
FA_VDD
3.3V supply of AFE (Video ADC)
3.3V supply of AFE (Video ADC)
1.2V supply for AFE (Video ADC)
Test purpose only
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
3.6
3.6
V
V
V
V
V
V
V
1.3
1.3
VDD
1.2V core supply
1.3
SDRAMC_VDD1P5
SDRAMC_VDD2P5
1.2/1.5 DDR Main IO supply
1.975
3.6
2.5V DDR pre-drive supply
DD2P5_LDO_OUT
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
31
Power supplies and sequencing
8.4 Recommended operating conditions
Table 30. Recommended operating conditions
Symbol
Parameters
Conditions
Min
Typ
Max
Unit
USB0_VBUS
VBUS supply for USB
w.r.t USB0_GND
4.4
5
5.25
V
USB1_VBUS
USB_DCAP
VBUS supply for USB
w.r.t USB1_GND
4.4
5
3
5.25
V
V
USB LDO 5V->3 V
Output
External DCAP (10uF
termination for
USBREG)
VBAT
Battery supply in case
of LDOIN fails
External CAP 0.1uF
2.4
3
3.3
3.6
3.6
V
VDD33_LDOIN
LDO input supply
3.3
1.1
V
V
DECAP_V11_LDO_OU LDO 3.3V -> 1.1V
Output
Recommended
External DCAP:
T
1uF(Min) 10uF (Max)
DECAP_V25_LDO_OU LDO 3.3V -> 2.5 Output
Recommended
External DCAP:
1uF(Min) 10uF (Max)
2.5
V
T
for PLL, DDR pre-
driver, EFUSE
VDD33
GPIO 3.3V IO supply
External CAP (10uF)
External CAP (10uF)
3
3
3.3
3.3
3.6
3.6
V
V
VDDREG
Device PMU regulator
and External ballast
supply
VDDA33_ADC
VREFH_ADC
VREFL_ADC
VDDA33_AFE
VDD12_AFE
FA_VDD
3.3V supply for ADC,
DAC and IO segment
External CAP (10uF)
3
3.3
3.3
0
3.6
V
V
V
V
V
V
High reference voltage
for ADC and DAC
Relation with
VDDDA33_ADC (1uF)
2.5
VDDA33_
ADC
Low reference voltage
for ADC and DAC
External CAP (10uF)
3.3V supply of AFE
(Video ADC)
External CAP 10uF
3
3.3
1.23
1.23
3.6
1.2V supply for AFE
(Video ADC)
1.16
1.16
1.26
1.26
For testing purpose
only should be shorted
to VDD on board.
VDD1
1.2V core supply
4.7uF with a low ESR
value (100 milliohms)
1.16
1.23
1.26
V
USB0_GND
USB1_GND
VSS_KEL0
Ground supply for USB
Ground supply for USB
0
0
0
V
V
V
USB LDO ground
output
VSS
VSS ground
0
0
V
V
VSSA33_ADC
Ground supply for ADC,
DAC and IO segment
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
32
NXP Semiconductors
Power supplies and sequencing
Table 30. Recommended operating conditions (continued)
Symbol
Parameters
Conditions
Min
Typ
Max
Unit
VSSA33_AFE
Ground supply of AFE
(Video ADC)
0
V
VSS12_AFE
Ground supply for AFE
(Video ADC)
0
V
SDRAMC_VDD1P5
SDRAMC_VDD1P5
SDRAMC_VDD2P5
LPDDR2
DDR3
External CAP 10uF
External CAP 10uF
External CAP 10uF
1.142
1.425
2.25
1.2
1.5
2.5
1.26
1.575
2.75
V
V
V
2.5V DDR pre-drive
supply
DD2P5_LDO_OUT
-
Maximum power supply
ramp rate (Slew limit for
power-up)
-
0.1
V/us
1. For customer applications, this is governed by ballast output which is controlled by the device and appropriate voltage
ranges are maintained.
8.5 Recommended Connections for Unused Analog Interfaces
NOTE
There are two options to handle unused power pins:
1. Connect all unused supplies to their respective voltage. To
save the power, do not enable the module and/or do not
enable clock gate to the module.
2. Keep all unused supplies floating.
If pin is shared by several peripheral, then all peripherals
connected to multiplexer have to be powered. For example: if
pin is shared by GPIO and ADC input and GPIO functionality
is used, then ADC has to be powered due to internal structure of
the multiplexer. Keep unused input signals grounded if power
pins are powered. Keep unused input signals floating if power
pins are floating. Keep unused output signals floating.
Module
Name
Recommendation if Unused
ADC
VDDA33_ADC
3.3V or float (Note: Powers both ADC
and DAC)
VREFH_ADC, VREFL_ADC
VREFH_ADC same as VDDA33_ADC
VREFL_ADC ground or float
ADC0SE8, ADC0SE9, ADC1SE8,
ADC1SE9
Ground or float
CCM
DAC
LVDS0P, LVDS0N
DACO0, DACO1
Float
Float
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
33
Peripheral operating requirements and behaviours
Module
Name
Recommendation if Unused
USB
USB_DCAP, USB0_VBUS,
USB1_VBUS
Connect USBx_VBUS and USB_DCAP
together and tie to ground through a 10K
ohm resistor. Do NOT tie directly to
ground, latch-up risk.
USB0_GND, USB1_GND
Ground
Float
USB0_VBUS_DETECT,
USB1_VBUS_DETECT
USB0_DM, USB0_DP, USB1_DM,
USB1_DP
Float
Video ADC
VDDA33_AFE
VDD12_AFE
3.3V or Float
1.2V or Float
Float
VADC_AFE_BANDGAP
VADCSE0, VADCSE1, VADCSE2,
VADCSE3
Ground or Float
9 Peripheral operating requirements and behaviours
9.1 Analog
9.1.1 12-bit ADC electrical characteristics
9.1.1.1 12-bit ADC operating conditions
Table 31. 12-bit ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typ
Max
Unit
Comment
1
Supply voltage
Absolute
VDDAD
2.5
-
3.6
V
-
-
Delta to VDDAD (VDD-
VDDAD), 2
ΔVDDAD
-100
0
100
mV
Ground voltage
Delta to VSSAD (VSS-
VSSAD)2
ΔVSSAD
-100
0
100
mV
-
Ref Voltage High
Ref Voltage Low
Input Voltage
-
VREFH
VREFL
VADIN
CADIN
RADIN
1.5
VDDAD
VSSAD
-
VDDAD
VSSAD
VREFH
2
V
V
-
-
-
-
-
-
-
-
VSSAD
-
VREFL
V
Input Capacitance
Input Resistance
8/10/12 bit modes
ADLPC=0, ADHSC=1
ADLPC=0, ADHSC=0
ADLPC=1, ADHSC=0
-
-
-
-
1.5
pF
5
7
kohms
kohms
kohms
12.5
25
15
30
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
34
NXP Semiconductors
Analog
Table 31. 12-bit ADC Operating Conditions (continued)
Characteristic
Conditions
Symb
Min
Typ
Max
Unit
Comment
1
Analog Source
Resistance
12 bit mode fADCK
40MHz ADLSMP=0,
=
RAS
-
-
1
kohms
Tsamp=150
ns
ADSTS=10, ADHSC=1
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
ADC Conversion Clock ADLPC=0, ADHSC=1
fADCK
4
4
4
-
-
-
40
30
20
MHz
MHz
MHz
-
-
-
Frequency
12 bit mode
ADLPC=0, ADHSC=0
12 bit mode
ADLPC=1, ADHSC=0
12 bit mode
1. Typical values assume VDDAD = 3.3 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference
Simplified input pin
equivalent circuit
ZADIN
Pad
leakage
due to
Simplified channel
select circuit
ZAS
ADC SAR
engine
input
protection
RADIN
RAS
+
VADIN
–
+
–
AS
V
CAS
RADIN
RADIN
RADIN
Input pin
Input pin
Input pin
CADIN
Figure 5. 12-bit ADC Input Impedance Equivalency Diagram
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
35
Analog
9.1.1.2 12-bit ADC characteristics
Table 32. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD
)
Characteristic
Conditions1
Symb
Min
Typ 2
Max
Unit
Comment
Supply Current
ADLPC=1, ADHSC=0
ADLPC=0, ADHSC=0
ADLPC=0, ADHSC=1
IDDAD
250
µA
ADLSMP=0
ADSTS=10 ADCO=1
350
400
Supply Current
Stop, Reset, Module
Off
IDDAD
0.01
0.8
µA
ADC Asynchronous
Clock Source
ADHSC=0
ADHSC=1
fADACK
10
20
2
MHz
tADACK = 1/fADACK
Sample Cycles
Conversion Cycles
Conversion Time
ADLSMP=0,
ADSTS=00
Csamp
Cconv
Tconv
cycles
cycles
µs
ADLSMP=0,
ADSTS=01
4
6
ADLSMP=0,
ADSTS=10
ADLSMP=0,
ADSTS=11
8
ADLSMP=1,
ADSTS=00
12
16
20
24
28
30
32
34
38
42
46
50
0.7
0.75
ADLSMP=1,
ADSTS=01
ADLSMP=1,
ADSTS=10
ADLSMP=1,
ADSTS=11
ADLSMP=0
ADSTS=00
ADLSMP=0
ADSTS=01
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
ADLSMP=0
ADSTS=00
Fadc=40 MHz
ADLSMP=0
ADSTS=01
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
36
NXP Semiconductors
Analog
Table 32. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
Conditions1
Symb
Min
Typ 2
Max
Unit
Comment
ADLSMP=0
ADSTS=10
0.8
ADLSMP=0
ADSTS=11
0.85
0.95
1.05
1.15
1.25
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
Total Unadjusted
Error
12 bit mode
10 bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
12 bit mode
TUE
DNL
INL
EZS
EFS
EQ
-2
-
+5
+2
+1.5
1.5
1
LSB3
LSB3
LSB3
LSB3
LSB3
LSB3
With Max Averaging
-0.5
-
-0.25
-
Differential Non-
Linearity
-
0.6
0.5
0.25
2
Waiting for histogram
method confirmation
-
-
0.5
4
Integral Non-Linearity
Zero-Scale Error
Full-Scale Error
-
Waiting for histogram
method confirmation
-
1
2
-
0.5
+1.0
0.4
0.1
2
1
-
1.6
0.8
0.4
3.5
1
VADIN = VREFL With
Max Averaging
-
-
-
VADIN = VREFH With
Max Averaging
-
0.5
0.25
1 to 0
0.5
0.5
10.7
-
0.75
Quantization Error
-
-
-
Effective Number of
Bits
ENOB
SINAD
EIL
10.1
-
Bits
dB
Fin = 100Hz
Signal to Noise plus
Distortion
See ENOB
all modes
SINAD = 6.02 x ENOB + 1.76
IIn x RAS
Input Leakage Error
mV
IIn = 400 nA leakage
current
Temperature Sensor
Slope
Across the full
temperature range of
the device
m
--
-
1.84
696
--
-
mV/°C
Temperature Sensor
Voltage
25°C
VTEMP25
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
2. Typical values assume VDDAD = 3.3 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
37
Analog
3. 1 LSB = (VREFH - VREFL)/2N
NOTE
The ADC electrical spec would be met with the calibration
enabled configuration.
Figure 6. Minimum Sample Time Vs Ras (Cas = 2pF)
Figure 7. Minimum Sample Time Vs Ras (Cas = 5pF)
VF3xxR, VF5xxR, Rev. 8, 01/2018
38
NXP Semiconductors
Analog
Figure 8. Minimum Sample Time Vs Ras (Cas = 10pF)
9.1.2 12-bit DAC electrical characteristics
9.1.2.1 12-bit DAC operating requirements
Table 33. 12-bit DAC operating requirements
Symbol
Desciption
Min.
3.0
Typ
3.3
3.3
Max.
Unit
V
Notes
VDDA33_ADC
VREFH_ADC
Supply voltage
Reference voltage
3.6
2.5
VDDA33_
ADC
V
1
2
CL
IL
Output load capacitance
Output load current
—
—
100
1
pF
mA
1. User will need to set up DACx_STATCTRL [DACRFS]=1 to select the valid VREFH_ADC reference. When
DACx_STATCTRL [DACRFS]=0, the DAC reference is connected to an internal ground node and is not a valid voltage
reference. Note that the DAC and ADC share the VREFH_ADC reference simultaneously. )
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
9.1.2.2 12-bit DAC operating behaviors
Table 34. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
100
μA
P
IDDA_DACH Supply current — high-power mode
—
—
—
500
15
μA
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
10
1
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
39
Analog
Table 34. 12-bit DAC operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
3
5
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
low-power mode
μs
1
—
—
—
5
1
—
—
high-power mode
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
—
—
—
VDACR
INL
Integral non-linearity error — high speed
mode
—
8
1
LSB
LSB
2
3
DNL
Differential non-linearity error — VDACR
VREF_OUT
=
—
VOFFSET Offset error
EG Gain error
—
—
0.4
0.1
70
0.8
0.6
ꢀFSR
ꢀFSR
dB
4
4
PSRR Power supply rejection ratio, VDDA =3 V, T =
25 C
TCO
TGE
AC
Temperature coefficient offset voltage
Temperature coefficient gain error
Offset aging coefficient
—
—
—
—
3.7
0.000421
—
—
—
μV/C
ꢀFSR/C
μV/yr
Ω
5
100
250
Rop
SR
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
—
V/μs
High power (SPHP
Low power (SPLP
Channel to channel cross talk
)
1.7
0.3
70
3
)
0.6
CT
—
dB
1. Settling within 1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100mV to VDACR−100 mV
4. Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV
5. VDDA = 3.3 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40 °C to 85 °C
VF3xxR, VF5xxR, Rev. 8, 01/2018
40
NXP Semiconductors
Analog
Figure 9. INL error vs. digital code
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
41
Analog
Figure 10. DNL error vs. digital code
VF3xxR, VF5xxR, Rev. 8, 01/2018
42
NXP Semiconductors
Analog
Figure 11. Offset at half scale vs. temperature
9.1.3 VideoADC Specifications
This section describes the electrical specification and characteristics of the VideoADC
Analog Front End.
Table 35. VideoADC Specifications
Symbol
Description
Supply voltage
Min. Typ. Max. Unit
Notes
VDDA33_AFE
3.0
—
3.3
—
3.6
41
V
—
—
—
—
—
Supply current
mA
V
VDDA12_AFE
Vin
Supply voltage
1.1
—
1.2
—
1.26
14
Supply current
mA
Input signal voltage range
0.5
0
1.4
V
External AC coupling
10
47
nF
The external AC coupling
capacitance cannot be too large.
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
43
Analog
Table 35. VideoADC Specifications (continued)
Symbol
Description
Bandgap voltage
Min. Typ. Max. Unit
0.6
Notes
VBG
—
—
V
Bandgap voltage on
VADC_AFE_BANDGAP pin. Pin
should be decoupled with a 100nF
capacitor
VDDA33_AFE
VSSA33_AFE
VDD12_AFE
VSS12_AFE
100nF
(See notes)
100nF
(See notes)
VADC_AFE_BANDGAP
100nF
Band Gap
Control
Interface
47nF
VADCSE0
VADCSE1
VADCSE2
Mux,
Clamp
and
47nF
To Video
Decoder
47nF
ADC
Correction
VADCSE3
47nF
Filter
Figure 12. VideoADC supply scheme
Figure 13. VideoADC supply decoupling
VF3xxR, VF5xxR, Rev. 8, 01/2018
44
NXP Semiconductors
Display and Video interfaces
NOTE
VideoADC 3.3V and 1.2V power supply pins should be
decoupled to their respective grounds using low-ESR 100nF
capacitors
NOTE
If possible, avoid using switched voltage regulators for the AFE
power domains. Use linear voltage regulators instead.
NOTE
The 3.3V and 1.2V power domains should be separated from
other circuitry on the board by inductors/beads to filter out high
frequency noise.
9.2 Display and Video interfaces
9.2.1 DCU Switching Specifications
9.2.1.1 Interface to TFT panels (DCU0/1)
This section provides the LCD interface timing for a generic active matrix color TFT
panel. In the figure below, signals are shown with positive polarity. The sequence of
events for active matrix interface timing:
• PCLK latches data into the panel on its positive edge (when positive polarity is
selected). In active mode, PCLK runs continuously. This signal frequency could be
from 5 to 66 MHz depending on the panel type.
• HSYNC causes the panel to start a new line. It always encompasses at least one
PCLK pulse.
• VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DE acts like an output enable signal to the LCD panel. This output enables the data
to be shifted onto the display. When disabled, the data is invalid and the trace is off.
Figure 14. TFT LCD interface timing overview1
1. In the figure, LD[23:0]” signal is “line data,” an aggregation of the DCU’s RGB signals—R[0:7], G[0:7] and B[0:7].
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
45
DCU Switching Specifications
VSYNC
LINE
n-1
HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
HSYNC
DE
1
2
3
m-1
m
PCLK
LD[23:0]
9.2.1.2 Interface to TFT LCD Panels—Pixel Level Timings
This section provides the horizontal timing (timing of one line), including both the
horizontal sync pulse and data. All parameters shown in the figure below are
programmable. This timing diagram corresponds to positive polarity of the PCLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of
the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and
VSYNC signals via the SYN_POL register, whether active-high or active-low. The
default is active-high. The DE signal is always active-high. Pixel clock inversion and a
flexible programmable pixel clock delay are also supported. They are programmed via
the clock divide . The DELTA_X and DELTA_Y parameters are programmed via the
DISP_SIZE register. The PW_H, BP_H and FP_H parameters are programmed via the
HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the
VSYN_PARA register.
Table 36. LCD interface timing parameters—horizontal and vertical
Symbol
tPCP
Characteristic
Display pixel clock period
Unit
11.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPWH
tBPH
tFPH
tSW
HSYNC pulse width
HSYNC back porch width
HSYNC front porch width
Screen width
PW_H * tPCP
BP_H * tPCP
FP_H * tPCP
DELTA_X * tPCP
tHSP
tPWV
tBPV
tFPV
tSH
HSYNC (line) period
VSYNC pulse width
VSYNC back porch width
VSYNC front porch width
Screen height
(PW_H + BP_H + FP_H + DELTA_X ) * tPCP
PWV * tHSP
BP_V * tHSP
FP_V * tHSP
DELTA_Y * tHSP
tVSP
VSYNC (frame) period
(PW_V + BP_V + FP_V + DELTA_Y ) * tHSP
VF3xxR, VF5xxR, Rev. 8, 01/2018
46
NXP Semiconductors
DCU Switching Specifications
tHSP
tPWH
tPCP
tBPH
tSW
tFPH
Start
of line
PCLK
LD[23:0]
HSYNC
DE
Invalid Data
1
2
3
Invalid Data
DELTA_X
Figure 15. Horizontal sync timing
tVSP
tPWV
tHCP
tBPV
tSH
tFPV
Start of
Frame
HSYNC
LD[23:0]
(Line Data)
Invalid Data
1
2
3
Invalid Data
DELTA_Y
HSYNC
DE
Figure 16. Vertical sync pulse
9.2.1.3 Interface to TFT LCD panels—access level
This section provides the access level timing parameters of the LCD interface.
Table 37. LCD Interface Timing Parameters1, 2, 3—Access Level
Symbol
tCKP
tDV
tDV
tDV
Description
Min
Max
Unit
Pixel Clock Period
11.2
_
_
ns
ns
ns
ns
ns
ns
ns
TFT interface data valid after pixel clock
TFT interface HSYNC valid after pixel clock
TFT interface VSYNC valid after pixel clock
TFT interface DE valid after pixel clock
4.4
4.4
4.4
4.4
_
_
_
tDV
tHO
_
TFT interface output hold time for data and control bits
Relative skew between the data bits
0
_
4.4
1. The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on -ve
edg6
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
47
DCU Switching Specifications
2. Intra bit skew is less than 2 ns
3. Load CL = 50 pf
tHO
tDV
Figure 17. LCD Interface Timing Parameters—Access Level
9.2.2 Video Input Unit timing
This section provides the timing parameters of the Video Input Unit (VIU) interface.
These are the clocking requirements of the VIU interface:
• The platform bus clock must be 2.5x pixel clock
• If the VIU3 does 2x horizontal upscaling, the ratio must be 3x
VF3xxR, VF5xxR, Rev. 8, 01/2018
48
NXP Semiconductors
DCU Switching Specifications
tSU
tHO
Figure 18. VIU Timing Parameters
Table 38. VIU Timing Parameters
Symbol
fPIX_CK
tDSU
tDHD
Characteristic
Min Value
Max Value
Unit
MHz
VIU pixel clock frequency
VIU data setup time
VIU data hold time
_
4
1
64
_
ns
ns
_
9.2.3 LCD driver electrical characteristics
This section provides LCD driver electrical specification at VDD33 = 3.3 V 10%.
Table 39. LCD driver specifications
Symbol
Parameter
Min
Typical
Max
Unit
VLCD
ZBP/FP
Voltage on VLCD (LCD supply) pin with
respect to VSS
0
_
VDD33 +
0.3
V
LCD output impedance
(BP[n-1:0],FP[m-1:0]) for output levels
VDDE, VSS
_
5.0
KΩ
IBP/FP
LCD output current (BP[n-1:0],FP[m-1:0]) for _
outputs charge/discharge voltage levels
VDDE2/3, VDDE1/2, VDDE/3)1
25
_
µA
1. With PWR=10, BSTEN=0, and BSTAO=0
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
49
Ethernet specifications
9.3 Ethernet specifications
9.3.1 Ethernet Switching Specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface. All Ethernet
signals use pad type pad_fsr. The timing specifications described i the section assume a
pad slew rate setting of 11 and a load of 50 pF2.
9.3.2 Receive and Transmit signal timing specifications
This section provides timing specs that meet the requirements for RMII interfaces for a
range of transceiver devices.
Table 40. Receive signal timing for RMII interfaces
Characteristic
RMII Mode
Min Max
Unit
—
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
—
35ꢀ
35ꢀ
4
50
MHz
E3, E7
E4, E8
E1
65ꢀ
65ꢀ
—
RMII_CLK period
RMII_CLK pulse width low
RMII_CLK period
RXD[1:0], CVS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN valid
RMII_CLK to TXD[1:0], TXEN invalid
ns
ns
ns
ns
E2
2
—
E6
—
4
14
E5
—
Figure 19. RMII receive signal timing diagram
2. These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11).
When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase
edge rise and fall times, thus reducing EMI.
VF3xxR, VF5xxR, Rev. 8, 01/2018
50
NXP Semiconductors
Ethernet specifications
Figure 20. RMII transmit signal timing diagram
NOTE
See the most current device errata document when using the
internally generated RXCLK and TXCLK clocks.
t
CYC
t
PWH
RX_CLK
(Input)
t
t
S
H
RXDn,
RX_DV,
RX_ER
(Input)
(n = 0-3)
Figure 21. MII receive signal timing diagram
Table 41. Receive signal timing for MII interfaces
Characteristic
MII Mode
Unit
Min
Typ
40/400
50
Max
RX_CLK clock period (100/10 MBPS) tCYC
RX_CLK duty cycle, tPWH/tCYC
ns
ꢀ
45
5
55
Input setup time before RX_CLK
Input setup time after RX_CLK
tS
tH
ns
ns
5
9.3.3 Receive and Transmit signal timing specifications for MII
interfaces
This section provides timing specs that meet the requirements for MII interfaces for a
range of transceiver devices.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
51
Ethernet specifications
t
CYC
t
PWH
RX_CLK
(Input)
t
t
S
H
RXDn,
RX_DV,
RX_ER
(Input)
(n = 0-3)
Figure 22. MII receive signal timing diagram
Table 42. Receive signal timing for MII interfaces
Characteristic
MII Mode
Unit
Min
Typ
40/400
50
Max
RX_CLK clock period (100/10 MBPS) tCYC
RX_CLK duty cycle, tPWH/tCYC
ns
ꢀ
45
5
55
Input setup time before RX_CLK
Input hold time after RX_CLK
ts
th
ns
ns
5
t
CYC
t
PWH
TX_CLK
(Input)
t
D
TXDn,
TX_EN,
TX_ER
(Output)
Note: Device pins applicable to MII interface are applicable to TMII interface,
and operates at 50 MHz reference clock.
Figure 23. MII transmit signal timing diagram
Table 43. Transmit signal timing for MII interfaces
Characteristic
MII Mode
Typ
Unit
Min
Max
TX_CLK clock period (100/10 MBPS) tCYC
TX_CLK duty cycle, tPWH/tCYC
40/400
50
ns
ꢀ
45
2
55
25
Out delay from TX_CLK
tD
ns
VF3xxR, VF5xxR, Rev. 8, 01/2018
52
NXP Semiconductors
Audio interfaces
9.4 Audio interfaces
9.4.1 Enhanced Serial Audio Interface (ESAI) Timing Parameters
The ESAI consists of independent transmitter and receiver sections, each section with its
own clock generator. The following table shows the interface timing values.
Table 44. Enhanced Serial Audio Interface (ESAI) Timing
No
Characteristics
Symbol
Min
30.0
Max
—
Condition1
Unit
1
Clock cycle2
tSSICC
master
ns
(4 × Tc)
—
2
Clock high period:
• master
—
—
—
—
—
ns
6
—
• slave
(2 × Tc −
9.0)
15
(2 × Tc)
3
Clock low period:
• master
—
—
6 (2 × Tc −
9.0)
—
—
—
—
ns
• slave
15 (2 × Tc)
4
5
6
7
8
9
FSR Input and Data Input setup time before SCKR
(SCK in synchronous mode) falling edge
—
—
—
—
—
—
—
—
—
—
—
—
—
6
15
2
—
—
—
—
15
6
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
—
ns
ns
ns
ns
ns
ns
ns
FSR Input and Data Input hold time after SCKR
falling edge
0
SCKT rising edge to FST out and Data out valid
SCKT rising edge to FST out and Data out hold
FST input setup time before SCKT falling edge
FST input hold time after SCKT falling edge
—
—
—
—
6
0
0
—
—
—
—
—
15
2
0
10 HCKR/HCKT clock cycle
15
(2 x TC)
—
—
11 HCKT input rising edge to SCKT output
12 HCKR input rising edge to SCKR output
—
—
18.0
18.0
—
—
ns
ns
1. SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) =
receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock
2. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
53
Audio interfaces
1
2
3
SCKT
(input/output)
FST (bit) out
6
FST (word) out
Data out
First bit
Lastbit
9
FST (bit) in
8
9
FST (word) in
Figure 24. ESAI Transmitter Timing
1
2
3
SCKR
(input/output)
FSR (bit) out
FSR (word) out
5
4
Data in
FSR (bit) in
First bit
Last bit
FSR (word) in
Figure 25. ESAI Receiver Timing
VF3xxR, VF5xxR, Rev. 8, 01/2018
54
NXP Semiconductors
Audio interfaces
9.4.2 SPDIF Timing Parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase
marking code. When encoding, the SPDIF data signal is modulated by a clock that is
twice the bit rate of the data signal. Table and Figure below show SPDIF timing
parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the
timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing of the
modulating Tx clock (STCLK) for SPDIF in Tx mode.
Table 45. SPDIF Timing Parameters
Characteristic
Symbol
Timing Parameter Range
Unit
Min
Max
SPDIFIN Skew: asynchronous inputs, no specs apply
0.7
1.5
ns
ns
SPDIFOUT output (Load = 50pf)
• Skew
• 1.5
• 24.2
• 31.3
• Transition rising
• Transition falling
SPDIFOUT1 output (Load = 30pf) - Skew
ns
• Transition rising
• Transition falling
Refer Table 21
Modulating Rx clock (SRCK) period
SRCK high period
srckp
40
16
16
40
16
16
ns
ns
ns
ns
ns
ns
srckph
srckpl
stclkp
stclkph
stclkpl
SRCK low period
Modulating Tx clock (STCLK) period
STCLK high period
STCLK low period
Figure 26. SRCK Timing Diagram
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
55
Audio interfaces
Figure 27. STCLK Timing Diagram
9.4.3 SAI/I2S Switching Specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame
sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 46. Master Mode SAI Timing
Num
Characteristic
SAI_MCLK cycle time
Min
2 x tSYS
Max
Unit
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
—
ns
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
40ꢀ
60ꢀ
—
MCLK period
4 x tSYS
ns
SAI_BCLK pulse width high/low
SAI_BCLK to SAI_FS output valid
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
40ꢀ
—
0
60ꢀ
15
—
BCLK period
ns
ns
ns
ns
ns
ns
—
0
15
—
SAI_BCLK to SAI_TXD invalid
SAI_RXD/SAI_FS input setup before SAI_BCLK
SAI_RXD/SAI_FS input hold after SAI_BCLK
15
0
—
—
VF3xxR, VF5xxR, Rev. 8, 01/2018
56
NXP Semiconductors
Audio interfaces
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S6
S10
S9
S7
S8
S7
S8
S9
S10
I2S_RXD
Figure 28. SAI Timing — Master Modes
Table 47. Slave Mode SAI Timing
Num
Characteristic
Min
4 x tSYS
Max
Unit
S11
S12
S13
S14
S15
S16
S17
S18
SAI_BCLK cycle time (input)
—
ns
SAI_BCLK pulse width high/low (input)
SAI_FS input setup before SAI_BCLK
SAI_FS input hold after SAI_BCLK
SAI_BCLK to SAI_TXD/SAI_FS output valid
SAI_BCLK to SAI_TXD/SAI_FS output invalid
SAI_RXD setup before SAI_BCLK
SAI_RXD hold after SAI_BCLK
40ꢀ
10
2
60ꢀ
—
BCLK period
ns
ns
ns
ns
ns
ns
—
—
0
20
—
10
2
—
—
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 29. SAI Timing — Slave Modes
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
57
Memory interfaces
9.5 Memory interfaces
9.5.1 QuadSPI timing
• All data is based on a negative edge data launch from the device and a negative edge
data capture, as shown in the timing diagrams in this section. This corresponds to the
N/1 sample point as shown in the reference manual QSPI section "Internal Sampling
of Serial Flash Input Data."
• Measurements are with a load of 35 pF on output pins. I/P Slew : 1ns
• Timings assume a setting of 0x0000_000x for QSPI_SMPR register (see the
reference manual for details).
SDR mode
Tck
SCK
Tcss
Tcsh
CS
Tis
Tih
Data in
Figure 30. QuadSPI Input/Read timing (SDR mode)
Table 48. QuadSPI Input/Read timing (SDR mode)
Symbol
Parameter
Value
Unit
Min
Max
Tis
Tih
Setup time for incoming data
5.4
0
—
—
ns
ns
Hold time requirement for incoming data
VF3xxR, VF5xxR, Rev. 8, 01/2018
58
NXP Semiconductors
Memory interfaces
Tck
SCK
CS
Tcss
Tcsh
Toh
Tov
Data out
Figure 31. QuadSPI Output/Write timing (SDR mode)
Table 49. QuadSPI Output/Write timing (SDR mode)
Symbol
Parameter
Value
Unit
Min
Max
Tov
Output Data Valid
Output Data Hold
SCK clock period
-
3.2
ns
Toh
Tck
0
-
-
ns
80
-
MHz
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
3
3
SCK clock cycles
SCK clock cycles
-
NOTE
• Tcss and Tcsh are set by QuadSPI_FLSCH register, the
minimum values of 3 shown are the register default values,
refer to Reference Manual for further details.
• The timing in the datasheet is based on default values for
the QuadSPI-SMPR register and is the recommended
setting for highest SCK frequency in SDR mode.
• A negative time indicates the actual capture edge inside the
device is earlier than clock appearing at pad.
• Frequency calculator guideline (Max read frequency): Tck
> (Flash access time)max + (Tis)max
• A negative input hold time has no bearing on the maximum
achievable operating frequency.
DDR Mode
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
59
Memory interfaces
Tck
SCK
CS
Tcss
Tcsh
Tih
Tis
Data in
Figure 32. QuadSPI Input/Read timing (DDR mode)
NOTE
• The numbers are for a setting of 0x1 in register
QuadSPI_SMPR[DDRSMP]
• Read frequency calculations should be: Tck/2 > (flash
access time) + Setup (Tis) -
(QuadSPI_SMPR[DDRSMP])x Tck/4
• Frequency calculator guideline (Max read frequency):
Tck/2 > (Flash access time)max + (Tis)max -
(QuadSPI_SMPR[DDRSMP]) x Tck/4
• Hold timing: flash_access (min) + flash_data_valid (min) >
Tck/2 + HOLD(Tih) + (QuadSPI_SMPR[DDRSMP])Tck/4
Table 50. QuadSPI Input/Read timing (DDR mode)
Symbol
Parameter
Value
Unit
Min
Max
Tis
Tih
Setup time for incoming data
6.5
0
—
—
ns
ns
Hold time requirement for incoming data
NOTE
VF3xxR, VF5xxR, Rev. 8, 01/2018
60
NXP Semiconductors
Memory interfaces
Tck
SCK
CS
Tcss
Tcsh
Tov
Toh
Data out
Figure 33. QuadSPI Output/Write timing (DDR mode)
Table 51. QuadSPI Output/Write timing (DDR mode)
Symbol
Parameter
Value
Unit
Min
Max
Tov
Output Data Valid
Output Data Hold
SCK clock period
—
0
-
3.9
—
45
-
ns
Toh
Tck
ns
MHz
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
3
3
Clk(sck)
Clk(sck)
-
9.5.2 NAND flash controller specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• TH is the flash clock high time and
• TL is flash clock low time,
which are defined as:
TNFC = TH + TL
NOTE
See the CCM section of the product reference manual for
further details on setting up the NFC clocks
(CCM_CSCDR2[NFC_FRAC_DIV_EN + NFC_FRAC_DIV]
and CCM_CSCDR3[NFC_PRE_DIV]).
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
61
Memory interfaces
Table 52. NFC specifications
Num
tCLS
tCLH
tCS
Description
Min.
2TH + TL – 1
TH + TL – 1
2TH + TL – 1
TH + TL
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NFC_CLE setup time
NFC_CLE hold time
NFC_CEn setup time
NFC_CEn hold time
NFC_WP pulse width
NFC_ALE setup time
NFC_ALE hold time
Data setup time
tCH
tWP
tALS
tALH
tDS
TL – 1
2TH + TL
TH + TL
TL – 1
tDH
Data hold time
TH – 1
tWC
tWH
tRR
Write cycle time
TH + TL – 1
TH – 1
NFC_WE hold time
Ready to NFC_RE low
NFC_RE pulse width
Read cycle time
4TH + 3TL + 90
TL + 1
tRP
tRC
TL + TH – 1
TH – 1
tREH
tIS
NFC_RE high hold time
Data input setup time
11
NFC_CLE
tCLS
tCS
tCLH
tCH
NFC_CEn
NFC_WE
NFC_IOn
tWP
tDS
tDH
Figure 34. Command latch cycle timing
VF3xxR, VF5xxR, Rev. 8, 01/2018
62
NXP Semiconductors
Memory interfaces
NFC_ALE
NFC_CEn
NFC_WE
NFC_IOn
tALS
tCS
tALH
tCH
tWP
tDS
tDH
address
Figure 35. Address latch cycle timing
tCS
tCH
tWC
NFC_CEn
NFC_WE
NFC_IOn
tWP
tDS
tWH
tDH
data
data
data
Figure 36. Write data latch cycle timing
tCH
tRC
tRP
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tREH
tIS
data
data
data
tRR
Figure 37. Read data latch cycle timing in Slow mode
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
63
Memory interfaces
tCH
tRC
tRP
NFC_CEn
tREH
NFC_RE
NFC_IOn
NFC_RB
tIS
data
data
data
tRR
Figure 38. Read data latch cycle timing in Fast mode and EDO mode
9.5.3 FlexBus timing specifications
This section provides FlexBus timing parameters. All processor bus timings are
synchronous; input setup/hold and output delay are given in respect to the rising edge of a
reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal
system bus frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the FlexBus output clock (FB_CLK). All other timing relationships can be
derived from these values.
All FlexBus signals use pad type pad_fsr. The following timing specifications assume a
pad slew rate setting of 11 and a load of 50 pF3
Table 53. FlexBus timing specifications
Num
Characteristic
Frequency of operation
Min
Max
Unit
—
831 (with
MHz
Wait state)
572 without
Wait state ,
-1
FB1
FB4
FB5
FB2
FB3
Clock Period
Input setup
Input hold
12
10.6
0
—
—
—
6.4
—
ns
ns
ns
ns
ns
Output valid
Output hold
—
0
1. Freq = 1000/(11+ access time of external memory+ trace delay for clk and data)
2. Freq = 1000/(17+access time of external memory)
3. These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11).
VF3xxR, VF5xxR, Rev. 8, 01/2018
64
NXP Semiconductors
Memory interfaces
Figure 39. FlexBus read timing
Figure 40. FlexBus write timing
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
65
DDR controller specifications
9.5.4 DDR controller specifications
9.5.4.1 DDR3 Timing Parameters
Figure 41. DDR3 Command and Address Timing Parameters
NOTE
RESET pin has a external weak pull DOWN requirement if
DDR3 memory is NOT required to support content retention in
the device low power modes where core voltage is off but
DRAM voltage is on.
VF3xxR, VF5xxR, Rev. 8, 01/2018
66
NXP Semiconductors
DDR controller specifications
NOTE
RESET pin has a external weak pull UP requirement if DDR3
memory is required to support content retention in the device
low power modes where core voltage is off but DRAM voltage
is on.
NOTE
CKE pin has a external weak pull down requirement.
Table 54. DDR3 Timing Parameter
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
DDR1
DDR2
DDR4
CK clock high-level
width
tCH
tCL
tIS
0.47
0.53
tCK
tCK
ps
CK clock low-level
width
0.47
440
0.53
-
CS, RAS, CAS,
CKE, WE, ODT
setup time
DDR5
CS, RAS, CAS,
CKE, WE, ODT
hold time
tIH
315
-
ps
DDR6
DDR7
Address output
setup time
tIS
tIH
440
315
-
-
ps
ps
Address output
hold time
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
67
DDR controller specifications
9.5.4.2 DDR3 Read Cycle
Figure 42. DDR3 Read Cycle
Table 55. DDR3 Read Cycle
ID
Parameter
Symbol
CK = 400 MHz
Max
Unit
Min
DDR26
Minimum required DQ valid
window width
-
750
-
ps
NOTE
To receive the reported setup and hold values, read calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF
VF3xxR, VF5xxR, Rev. 8, 01/2018
68
NXP Semiconductors
DDR controller specifications
9.5.4.3 DDR3 Write cycle
Figure 43. DDR3 Write cycle
Table 56. DDR3 Write cycle
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
DDR17
DDR18
DDR21
DQ and DQM setup time to DQS
(differential strobe)
tDS
tDH
240
215
—
ps
ps
DQ and DQM hold time to DQS
(differential strobe)
—
DQS latching rising transitions to
associated clock edges
tDQSS
-0.25
+0.25
tCK
DDR22
DDR22
DQS high level width
DQS low level width
tDQSH
tDQSL
0.45
0.45
0.55
0.55
tCK
tCK
NOTE
To receive the reported setup and hold values, write calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
69
DDR controller specifications
9.5.4.4 LPDDR2 Timing Parameter
Figure 44. LPDDR2 Command and Address timing parameter
NOTE
RESET pin has a external weak pull DOWN requirement if
LPDDR2 memory is NOT required to support content retention
in the device low power modes where core voltage is off but
DRAM voltage is on.
NOTE
RESET pin has a external weak pull UP requirement if
LPDDR2 memory is required to support content retention in the
device low power modes where core voltage is off but DRAM
voltage is on.
NOTE
CKE pin has a external weak pull down requirement.
Table 57. LPDDR2 Timing Parameter
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
LP1
LP2
LP3
LP4
LP3
LP4
SDRAM clock high-level width
SDRAM clock LOW-level width
CS, CKE setup time
CS, CKE hold time
tCH
tCL
tIS
0.45
0.45
230
230
230
230
0.55
tCK
tCK
ps
0.55
-
-
-
-
tIH
tIS
ps
CA setup time
ps
CA hold time
tIH
ps
NOTE
All measurements are in reference to Vref level.
VF3xxR, VF5xxR, Rev. 8, 01/2018
70
NXP Semiconductors
DDR controller specifications
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
9.5.4.5 LPDDR2 Read Cycle
Figure 45. LPDDR2 Read cycle
Table 58. LPDDR2 Read Cycle
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
LP26
Minimum required DQ valid
window width for LPDDR2
-
270
-
ps
NOTE
To receive the reported setup and hold values, read calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
71
DDR controller specifications
9.5.4.6 LPDDR2 Write Cycle
Figure 46. LPDDR3 Write Cycle
Table 59. LPDDR2 Write Cycle
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
LP17
LP18
LP21
DQ and DQM setup time to DQS
(differential strobe)
tDS
tDH
220
0.55
ps
ps
DQ and DQM hold time to DQS
(differential strobe)
220
0.55
DQS latching rising transitions to
associated clock edges
tDQSS
-0.25
+0.25
tCK
LP22
LP23
DQS high level width
DQS low level width
tDQSH
tDQSL
0.4
0.4
-
-
tCK
tCK
NOTE
To receive the reported setup and hold values, write calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
VF3xxR, VF5xxR, Rev. 8, 01/2018
72
NXP Semiconductors
Communication interfaces
9.6 Communication interfaces
9.6.1 MediaLB (MLB) DC Characteristics
The section lists the MediaLB 3-pin interface electrical characteristics.
Table 60. MediaLB 3-Pin Interface Electrical DC Specifications
Parameter
Maximum input voltage
Low level input threshold
High level input threshold
Low level output threshold
High level output threshold
Input leakage current
Symbol
Test Conditions
Min
Max
3.6
Unit
—
—
—
—
V
V
V
V
V
VIL
—
0.7
—
VIH
VOL
VOH
See Note1
1.8
—
IOL = –6 mA
IOH = –6 mA
0 < Vin < VDD
0.4
—
2.0
—
10
μA
IL
1. Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated
and assumed by the customer.
9.6.2 MediaLB (MLB) Controller AC Timing Electrical Specifications
This section describes the timing electrical information of the MediaLB module.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
73
Communication interfaces
Figure 47. MediaLB 3-PinTiming
Ground = 0.0 V; Load Capacitance = 40 pF, input transition= 1 ns; MediaLB speed =
256/512 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold
as listed below; unless otherwise noted.
Table 61. MLB 256/512 Fs Timing Parameters
Parameter
Symbol
Min
Max
25.6
Unit
MHz
Comment
MLBCLK operating frequency
fmck
11.264
256xFs at 44.0 kHz,
512xFs at 50.0 kHz
MLBCLK rise time
MLBCLK fall time
MLBCLK low time1
MLBCLK high time
tmck
tmck
tmck
tmck
r
f
Refer Table 21
ns
ns
ns
ns
ns
VIL to V
IH
VIH to V
IL
l
30, 14
30, 14
3
—
—
—
256xFs, 512xFs
256xFs, 512xFs
—
h
MLBSIG/MLBDAT receiver input setup to
MLBCLK falling
tdsmcf
tdhmcf
tmcfdz
tmdzh
MLBSIG/MLBDAT receiver input hold from
MLBCLK low
2
0
2
—
16
—
ns
ns
ns
—
2
MLBSIG/MLBDAT output valid from
MLBCLK low
Bus output hold from MLBCLK low
—
1. MLBCLK low/high time includes the pluse width variation.
VF3xxR, VF5xxR, Rev. 8, 01/2018
74
NXP Semiconductors
Communication interfaces
2. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the
maximum load capacitance listed.
Table 62. MLB 1024 Fs Timing Parameters
Parameter
Symbol
Min
Max
51.2
Unit
MHz
Comme
nt
MLBCLK Operating Frequency1
fmck
45.056
1024xfs
at 44.0
kHz
1024xfs
at 50.0
kHz
MLBCLK rise time
MLBCLK fall time
MLBCLK low time
MLBCLK high time
fmckr
fmckf
tmckl
tmckh
tdsmcf
Refer Table 21
ns
ns
ns
ns
ns
VIL to VIH
VIH to V
IL
6.1
9.3
3
—
—
—
2
MLBSIG/MLBDAT receiver input setup
to MLBCLK falling
MLBSIG/MLBDAT receiver input hold
from MLBCLK low
tdhmcf
tmcfdz
tmdzh
2
-
—
16
—
ns
ns
ns
MLBSIG/MLBDAT output valid from
MLBCLK low
3
Bus Hold from MLBCLK low
2
1. The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLBCLK.
2. MLBCLK low/high time includes the pluse width variation.
3. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the
maximum load capacitance listed.
9.6.3 DSPI timing specifications
Table 63. DSPI timing
No.
Symbol
tSCK
Characteristic
SCK Cycle Time
Condition
Min
tSYS * 2
Max
Unit
1
4
2
3
5
—
—
—
ns
tSDC
tCSC
tASC
tA
SCK Clock Pulse Width
CS to SCK Delay
40ꢀ
16
60ꢀ
—
tSCK
ns
Master
Master
After SCK Delay
16
—
ns
Slave Access Time (SS active Slave
to SOUT driven)
—
15
ns
6
9
tDI
Slave Disable Time (SS
inactive to SOUT High-Z or
invalid)
Slave
—
10
—
ns
ns
tSUI
Data Setup Time for Inputs
Master
9
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
75
Communication interfaces
Table 63. DSPI timing (continued)
No.
Symbol
Characteristic
Condition
Slave
Min
Max
Unit
4
—
—
—
5
10
11
12
tHI
Data Hold Time for Inputs
Master
Slave
0
ns
ns
ns
2
tDV
Data Valid (after SCK edge)
for Outputs
Master
Slave
—
—
0
10
—
—
tHO
Data Hold Time for Outputs
Master
Slave
0
2
3
C S x
1
4
S C K O u tp u t
(C P O L = 0 )
4
S C K O u tp u t
(CP OL = 1 )
1 0
9
L a st D a ta
F irst D a ta
D a ta
S IN
1 2
1 1
F irst D a ta
D a ta
L a st D a ta
S O U T
Figure 48. DSPI classic SPI timing master, CPHA=0
VF3xxR, VF5xxR, Rev. 8, 01/2018
76
NXP Semiconductors
Communication interfaces
C S x
S C K O u tp u t
(C P O L = 0 )
1 0
S C K O u tp u t
(CP OL = 1 )
9
D a ta
D a ta
F irst D a ta
L a st D a ta
S IN
1 2
1 1
S O U T
L a st D a ta
F irst D a ta
Figure 49. DSPI classic SPI timing master, CPHA=1
3
2
S S
1
4
S C K In p u t
(C P O L = 0 )
4
S C K In p u t
(C P O L = 1 )
5
1 1
1 2
6
F irst D a ta
D a ta
L a st D a ta
S O U T
S IN
9
1 0
F irst D a ta
D a ta
L a st D a ta
Figure 50. DSPI classic SPI timing slave, CPHA=0
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
77
Communication interfaces
S S
S C K In p u t
(C P O L = 0 )
S C K In p u t
(C P O L = 1 )
1 1
5
6
1 2
L a st D a ta
D a ta
D a ta
S O U T
S IN
F irst D a ta
1 0
9
L a st D a ta
F irst D a ta
Figure 51. DSPI classic SPI timing slave, CPHA=1
9.6.4 I2C timing
Table 64. I2C input timing specifications — SCL and SDA 1
No.
Parameter
Min.
Max.
Unit
1
Start condition hold time
2
—
PER_CLK
Cycle2
2
Clock low time
8
—
PER_CLK
Cycle
3
4
5
Bus free time between Start and Stop condition
Data hold time
4.7
0.0
4
—
—
—
μs
μs
Clock high time
PER_CLK
Cycle
6
7
Data setup time
0.0
2
—
—
ns
Start condition setup time (for repeated start condition only)
PER_CLK
Cycle
8
Stop condition setup time
2
—
PER_CLKCyc
le
1. I2C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1
ns (10ꢀ – 90ꢀ).
2. PER_CLK is the IPG Clock which drives the I2C BIU and module clock inputs. Typically this is 66 MHz. See the Clocking
Overview chapter in the device reference manual for more details.
Table 65. I2C output timing specifications — SCL and SDA 1, 2, 3, 4
No.
Parameter
Min
Max
Unit
1
Start condition hold
time
6
—
PER_CLK Cycle5
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
78
NXP Semiconductors
Communication interfaces
Table 65. I2C output timing specifications — SCL and SDA 1, 2, 3, 4 (continued)
No.
Parameter
Clock low time
Min
Max
Unit
PER_CLK Cycle
μs
2
3
10
—
—
Bus free time between 4.7
Start and Stop condition
4
5
6
7
Data hold time
Clock high time
Data setup time
7
—
—
—
—
PER_CLK Cycle
PER_CLK Cycle
PER_CLK Cycle
PER_CLK Cycle
10
2
Start condition setup
time (for repeated start
condition only)
20
8
Stop condition setup
time
10
—
PER_CLK Cycle
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speedsand may
cause incorrect operation.
4. Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output
timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.
5. PER_CLK is the IPG Clock which drives the I2C BIU and module clock inputs. Typically this is 66 MHz. See the Clocking
Overview chapter in the device reference manual for more details.
Figure 52. I2C input/output timing
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
79
Communication interfaces
9.6.5 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface. A load of 50
pF is assumed.
Table 66. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
4
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 53. SDHC timing
VF3xxR, VF5xxR, Rev. 8, 01/2018
80
NXP Semiconductors
Clocks and PLL Specifications
9.6.6 USB PHY specifications
This section describes the USB-OTG PHY and the USB Host port PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal
Serial Bus Revision 2.0 OTG, USB Host with the amendments below (On-The-Go and
Embedded Host Supplement to the USB Revision 2.0 Specification is not applicable to
Host port).
• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
• Revision 2.0 plus errata and ecn June 4, 2010
• Battery Charging Specification (available from USB-IF)
• Revision 1.2, December 7, 2010
9.7 Clocks and PLL Specifications
9.7.1 24 MHz Oscillator Specifications
The system crystal oscillator consists of a Pierce-type structure running off the digital
supply. A straight forward biased-inverter implementation is used. The crystal must be
rated for a drive level of 250 μW or higher. An ESR (equivalent series resistance) of 80 Ω
or less is recommended to achieve a gain margin of 5.
Table 67. 24MHz external oscillator electrical characteristics
Symbol
Parameter
Condition
Value
Typ
Unit
Min
Max
fosc
Iosc
tuposc
Crystal oscillator range
Startup current
—
—
—
—
24
—
MHz
mA
ms
—
—
< 5
< 5
—
—
Oscillator startup time
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
81
Clocks and PLL Specifications
Table 67. 24MHz external oscillator electrical characteristics (continued)
Symbol
Parameter
Condition
Value
Typ
Unit
Min
Max
CIN
Input Capacitance
EXTAL and XTAL pins
—
—
9
—
pF
V
VIH
XTAL pin input high voltage
0.8 x
Vdd1
—
Vdd
+0.3
VIL
XTAL pin input low voltage
—
Vss
-0.3
—
0.2 x
Vdd
V
1. VDD =1.1 V 10ꢀ, TA = -40 to +85 °C, unless otherwise specified.
9.7.2 32 KHz Oscillator Specifications
This block implements an amplifier that when combined with a suitable quartz crystal
and external load capacitors implements a low power oscillator. It also implements a
power mux such that it can be powered from either a ~3 V backup battery or VDDIO
such as the oscillator consumes power from VDDIO when that supply is available and
transitions to the back up battery when VDDIO is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the
source of the 32 K will automatically switch to the 128kHz internal RC clock divided by
4.
The OSC32k runs from vdd_rtc supply, generated inside OSC32k itself from VDDIO/
VBAT. The target battery is a ~3 V coin cell. Proper choice of coin cell type is necessary
for chosen VDDIO range. Appropriate series resistor (Rs) must be used when connecting
the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell.
For example:
• Average Discharge Voltage is 2.5 V
• Maximum Charge Current is 0.6 mA
For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k
Table 68. OSC32K Main Characteristics
Notes
Min
Typ
Max
FOSC
This frequency is nominal and determined mainly by the
crystal selected. 32.0 K would work as well.
32.768 KHz
Current
The 4 μA is the consumption of the oscillator alone (OSC32k).
4 μA
consumption Total supply consumption will depend on what the digital
portion of the RTC consumes. The ring oscillator consumes 1
μA when ring oscillator is inactive, 20 μA when the ring
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
82
NXP Semiconductors
Clocks and PLL Specifications
Table 68. OSC32K Main Characteristics (continued)
Notes
Min
Typ
Max
oscillator is running. Another 1.5 μA is drawn from vdd_rtc in
the power_detect block. So, the total current is 6.5 μA on
vdd_rtc when the ring oscillator is not running.
Bias resistor This the integrated bias resistor that sets the amplifier into a
high gain state. Any leakage through the ESD network,
external board leakage, or even a scope probe that is
significant relative to this value will debias the amp. The
debiasing will result in low gain, and will impact the circuit's
ability to start up and maintain oscillations.
14 MΩ
Crystal Properties
Cload
Usually crystals can be purchased tuned for different Cloads.
This Cload value is typically 1/2 of the capacitances realized
on the PCB on either side of the quartz. A higher Cload will
decrease oscillation margin, but increases current oscillating
through the crystal
12.5 pF
50 kΩ
ESR
Equivalent series resistance of the crystal. Choosing a crystal
with a higher value will decrease the oscillating margin.
9.7.3 Fast internal RC oscillator (24 MHz) electrical characteristics
This section describes a fast internal RC oscillator (FIRC). This is used as the default
clock at the power-up of the device.
Table 69. Fast internal oscillator electrical characteristics
Symbol
Parameter
Condition1
Value
Typ
Min
Max
Unit
fRCM
RC oscillator high frequency
TA= 25 °C, trimmed
TA= 25 °C, trimmed
—
24
—
MHz
μA
IRCMRUN
RC oscillator high frequency
current in running mode
—
55
IRCMPWD
RCMTRIM
RCMVAR
RC oscillator high frequency
current in power down mode
TA= 25 °C
TA= 25 °C
100
—
nA
ꢀ
RC oscillator precision after
trimming of fRC
-1
-5
+1
+5
RC oscillator variation in
ꢀ
temperature and supply with
respect to fRC at TA = 55 °C in
high frequency configuration
1. VDD = 1.2 V , TA = -40 to +85 °C, unless otherwise specified.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
83
Clocks and PLL Specifications
9.7.4 Slow internal RC oscillator (128 KHz) electrical characteristics
This section describes a slow internal RC oscillator (SIRC). This can be used as the
reference clock for the RTC module.
Table 70. Slow internal RC oscillator electrical characteristics
Symbol
Parameter
Condition1
Value
Typ
Min
Max
Unit
fRCL
IRCL
RC oscillator low frequency
TA= 25 °C, trimmed
TA= 25 °C, trimmed
—
128
—
kHz
μA
RC oscillator low frequency
current
—
-1
-5
3.1
RCLTRIM
RC oscillator precision after
trimming of fRCL
TA= 25 °C
—
—
+1
+5
ꢀ
ꢀ
RCLVAR 3
RC oscillator variation in
High frequency configuration
temperature and supply with
respect to fRC at TA = 55 °C in
high frequency configuration
1. VDD = 1.2 V , TA = -40 to +85 °C, unless otherwise specified.
9.7.5 PLL1 and PLL2 (528 MHz System PLL) Electrical Parameters
Table 71. PLL1 and PLL2 Electrical Parameters
Parameter
Value
528 MHz PLL output
Clock output range
Reference clock
Lock time
24 MHz
<7500 reference cycles
<140ps
Period jitter(p2p)
Duty Cycle
48.9ꢀ~51.7ꢀ PLL output
9.7.6 PLL3 and PLL7 (480 MHz USB PLL) Electrical Parameters
Table 72. PLL3 and PLL7 Electrical Parameters
Parameter
Value
480 MHz PLL output
Clock output range
Reference clock
Lock time
24 MHz
<425 reference cycles
<140 ps
Period jitter(p2p)
Duty Cycle
48.9ꢀ~51.7ꢀ PLL output
VF3xxR, VF5xxR, Rev. 8, 01/2018
84
NXP Semiconductors
Clocks and PLL Specifications
9.7.7 PLL5 (Ethernet PLL) Electrical Parameters
Table 73. PLL5 Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
500 MHz
24 MHz
<7500 reference cycles
<400ps @ 50 MHz
45ꢀ~55ꢀ
Cycle to cycle jitter (p2p)1
Duty Cycle
1. Jitter numbers are measured at divided PLL clock because high frequency cannot be brought-out IO pad.
9.7.8 PLL4 (Audio PLL) Electrical Parameters
Table 74. PLL4 Electrical Parameters
Parameter
Value
650 MHz ~1.3 GHz
Clock output range
Reference clock
Lock time
24 MHz
<7500 reference cycles
<42ps @1128MHz
<115ps@1128MHz
43ꢀ~57ꢀ
Long term jitter(RMS)
Period jitter(p2p)1
Duty Cycle
1. Jitter numbers are measured at divided PLL clock because high frequency cannot be brought-out on IO pad.
9.7.9 PLL6 (Video PLL) Electrical Parameters
Table 75. PLL6 Electrical Parameters
Parameter
Value
650 MHz ~1.3 GHz
Clock output range
Reference clock
Lock time
Long term jitter(RMS)1
Period jitter(p2p)
Duty Cycle
24 MHz
<7500 reference cycles
<42ps @ 1128 MHz
<130ps @960MHz
43ꢀ~57ꢀ
1. Jitter numbers are measured at divided PLL clock because high frequency cannot be brought-out on IO pad & at use case
frequency.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
85
Debug specifications
9.8 Debug specifications
9.8.1 JTAG electricals
Table 76. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
-
-
-
25
25
25
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
20
20
20
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
Refer Table 21
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
8
1.3
—
—
8
—
—
17
17
—
—
17
17
J6
J7
J8
J9
J10
J11
J12
1.3
—
—
TCLK low to TDO high-Z
NOTE
Input transition (1ns), output load (25 pf) and SRE (000), DSE
(111), FSEL(011).
J2
J3
J3
TCLK (input)
J4
J4
Figure 54. Test clock input timing
VF3xxR, VF5xxR, Rev. 8, 01/2018
86
NXP Semiconductors
Debug specifications
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 55. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 56. Test Access Port timing
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
87
Debug specifications
9.8.2 Debug trace timing specifications
Table 77. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
50
Low pulse width
2
2
—
—
Twh
Tr
High pulse width
Clock and data rise time
Clock and data fall time Refer
Data output valid
Data output hold
ns
Refer Table 21
ns
Tf
ns
tDV
tHO
3
—
—
ns
1
ns
TRACECLK
T
r
T
f
T
T
wh
wl
T
cyc
Figure 57. TRACE_CLKOUT specifications
traceoutput clock
traceoutput data
t
HO
t
DV
Figure 58. Trace data specifications
VF3xxR, VF5xxR, Rev. 8, 01/2018
88
NXP Semiconductors
Thermal attributes
10 Thermal attributes
10.1 Thermal attributes
This table shows the thermal attributes for the 176 LQFP package.
Board type
Symbol
Description
176 LQFP
Unit
Notes
Single-layer (1s)
RθJA
Thermal
50
32
40
25
°C/W
°C/W
°C/W
°C/W
1, 2
resistance, junction
to ambient (natural
convection)
Four-layer (2s2p)
Single-layer (1s)
Four-layer (2s2p)
RθJA
Thermal
1,3
resistance, junction
to ambient (natural
convection)
RθJMA
Thermal
1, 3
1, 3
resistance, junction
to ambient (200 ft./
min. air speed)
RθJMA
Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
—
—
—
RθJB
Thermal
resistance, junction
to board
21
12
3
°C/W
°C/W
°C/W
4
5
6
RθJCtop
Thermal
resistance, junction
to case top
ΨJT
Thermal
characterization
parameter, junction
to package top
(natural
convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
This table shows the thermal attributes for the 364 MAPBGA package.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
89
Dimensions
Board type
Symbol
Description
364 MAPBGA
Unit
Notes
Single-layer (1s)
Four-layer (2s2p)
Single-layer (1s)
Four-layer (2s2p)
RθJA
Thermal
45
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1,3
resistance, junction
to ambient (natural
convection)
RθJA
Thermal
28
37
24
resistance, junction
to ambient (natural
convection)
RθJMA
Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
RθJMA
Thermal
1,3
resistance, junction
to ambient (200 ft./
min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance, junction
to board
17
10
2
°C/W
°C/W
°C/W
4
5
6
Thermal
resistance, junction
to case
Thermal
characterization
parameter, junction
to package top
outside center
(natural
convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
11 Dimensions
11.1 Obtaining package dimensions
Package dimensions are provided in package drawing.
To find a package drawing, go to www.nxp.com and perform a keyword search for the
drawing’s document number:
VF3xxR, VF5xxR, Rev. 8, 01/2018
90
NXP Semiconductors
Pinouts
Package
Document Number
176-pin LQFP
364 MAPBGA
98ASA00452D
98ASA00418D
12 Pinouts
12.1 Pinouts
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The IOMUX Controller Module is
responsible for selecting which ALT functionality is available on each pin.
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
Y2
—
ADC0SE8
N/
A
ADC0_SE8
W2
W3
Y3
—
—
—
34
33
31
ADC0SE9
ADC0_SE9
ADC1_SE8
ADC1_SE9
VREFH_ADC
VREFL_ADC
ADC1SE8
ADC1SE9
W1
U3
V1
VREFH_ADC
VREFL_ADC
VDDA33_
ADC
VDDA33_
ADC
V2
32
VSSA33_
ADC
VSSA33_
ADC
U1
U2
Y4
U4
W4
V5
V3
29
30
35
37
—
—
40
DACO0
DACO0
DACO1
DACO1
VADCSE0
VADCSE1
VADCSE2
VADCSE3
VADCSE0
VADCSE1
VADCSE2
VADCSE3
VDDA33_
AFE
VDDA33_
AFE
V4
T5
R5
U5
39
36
38
41
VSSA33_AFE
VDD12_AFE
VSS12_AFE
VSSA33_AFE
VDD12_AFE
VSS12_AFE
VADC_AFE_
BANDGAP
VADC_AFE_
BANDGAP
Y13
W13
Y12
73
72
70
EXTAL
XTAL
EXTAL
XTAL
EXTAL32
EXTAL32
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
91
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
W12
T4
71
28
XTAL32
XTAL32
RESETB/
RESETB/
RESETB/
RESET_OUT RESET_OUT
RESET_OUT
N5
19
PTA6
PTA6
RMII_
CLKOUT
RMII_CLKIN/
MII0_TXCLK
DCU1_
TCON11
DCU1_R2
T3
T1
27
23
69
TEST
TEST
Ext_POR
TEST2
V12
DECAP_
V11_LDO_
OUT
DECAP_
V11_LDO_
OUT
T11
65
DECAP_
V25_LDO_
OUT
DECAP_
V25_LDO_
OUT
T2
P5
26
24
68
BCTRL
BCTRL
VDDREG
VDDREG
T12
VDD33_
LDOIN
VDD33_
LDOIN
V11
U11
W14
Y14
K4
67
66
—
—
3
VSS
VSS
VSS_KEL0
LVDS0P
LVDS0N
VSS_KEL0
LVDS0P
LVDS0N
JTCLK/
SWCLK
JTCLK/
SWCLK
PTA8
JTCLK/
SWCLK
DCU0_R0
DCU0_R1
DCU0_G0
DCU0_G1
MLBCLK
K2
K1
L1
4
5
JTDI
JTDI
PTA9
JTDI
RMII_
CLKOUT
RMII_CLKIN/
MII0_TXCLK
WDOG_b
JTDO
JTDO/
TRACESWO
PTA10
PTA11
PTA12
PTA16
PTA17
PTA18
PTA19
PTA20
JTDO
EXT_AUDIO_
MCLK
ENET_TS_
CLKIN
MLBSIGNAL
MLBDATA
6
JTMS/
SWDIO
JTMS/
SWDIO
JTMS/
SWDIO
L3
7
PTA12
PTA16
PTA17
PTA18
PTA19
PTA20
TRACECK
TRACED0
TRACED1
TRACED2
TRACED3
TRACED4
EXT_AUDIO_
MCLK
VIU_DATA13 I2C0_SCL
VIU_DATA14 I2C0_SDA
VIU_DATA15 I2C1_SCL
VIU_DATA16 I2C1_SDA
Y5
Y6
V6
U6
B18
43
44
46
47
143
USB0_
VBUS_EN
ADC1_SE0
ADC1_SE1
LCD29
LCD30
LCD31
LCD32
LCD33
SAI2_TX_
BCLK
USB0_
VBUS_OC
USB0_SOF_
PULSE
ADC0_SE0
FTM1_QD_
PHA
SAI2_TX_
DATA
ADC0_SE1
FTM1_QD_
PHB
SAI2_TX_
SYNC
VIU_DATA17 QSPI1_A_
SCK
SCI3_TX
DCU1_
HSYNC/
DCU1_
TCON1
D18
145
PTA21
PTA21/
MII0_RXCLK
TRACED5
SAI2_RX_
BCLK
SCI3_RX
DCU1_
VSYNC/
DCU1_
TCON2
VF3xxR, VF5xxR, Rev. 8, 01/2018
92
NXP Semiconductors
Pinouts
364
MAP LQFP
BGA
176
Pin Name
Default
ALT0
ALT1
TRACED6
TRACED7
ALT2
ALT3
ALT4
ALT5
ALT6
I2C2_SCL
I2C2_SDA
ALT7
EzPort
E17
C17
147
148
PTA22
PTA22
SAI2_RX_
DATA
DCU1_TAG/
DCU1_
TCON0
PTA23
PTA23
SAI2_RX_
SYNC
DCU1_DE/
DCU1_
TCON3
R16
R17
R19
R20
P20
P18
P17
P16
T6
—
—
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
PTA30
PTA31
PTB0
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
PTA30
PTA31
PTB0
TRACED8
TRACED9
TRACED10
TRACED11
TRACED12
TRACED13
TRACED14
TRACED15
FTM0_CH0
FTM0_CH1
FTM0_CH2
FTM0_CH3
FTM0_CH4
FTM0_CH5
FTM0_CH6
FTM0_CH7
FTM1CH0
FTM1CH1
SCI0_TX
USB1_
VBUS_EN
SDHC1_CLK
DCU1_
TCON4
USB1_
VBUS_OC
SDHC1_CMD DCU1_
TCON5
—
SAI3_TX_
BCLK
SDHC1_
DAT0
DCU1_
TCON6
—
SAI3_RX_
BCLK
SDHC1_
DAT1
DCU1_
TCON7
—
SAI3_RX_
DATA
ENET1_
1588_TMR0
SCI4_TX
SCI4_RX
SCI4_RTS
SCI4_CTS
LCD34
SDHC1_
DAT2
DCU1_
TCON8
—
SAI3_TX_
DATA
ENET1_
1588_TMR1
SDHC1_
DAT3
DCU1_
TCON9
—
SAI3_RX_
SYNC
ENET1_
1588_TMR2
I2C3_SCL
SCI3_TX
SCI3_RX
—
SAI3_TX_
SYNC
ENET1_
1588_TMR3
I2C3_SDA
49
50
51
53
54
55
56
166
121
123
159
164
ADC0_SE2
ADC0_SE3
ADC1_SE2
ADC1_SE3
SCI1_TX
TRACECTL
SAI2_RX_
BCLK
VIU_DATA18 QSPI1_A_
CS0
T7
PTB1
RCON30
RCON31
PTB1
RCON30
LCD35
SAI2_RX_
DATA
VIU_DATA19 QSPI1_A_
DATA3
V7
PTB2
PTB2
RCON31
LCD36
SAI2_RX_
SYNC
VIU_DATA20 QSPI1_A_
DATA2
W7
Y7
PTB3
PTB3
EXTRIG
LCD37
VIU_DATA21 QSPI1_A_
DATA1
PTB4
PTB4
ADC0_SE4
ADC1_SE4
LCD38
VIU_FID
VIU_DATA22 QSPI1_A_
DATA0
Y8
PTB5
PTB5
SCI1_RX
LCD39
VIU_DE
VIU_DATA23 QSPI1_A_
DQS
W8
D13
J16
J19
B15
D14
PTB6
PTB6
SCI1_RTS
SCI1_CTS
QSPI0_A_
CS1
LCD40
FB_CLKOUT
VIU_HSYNC
SCI2_TX
SCI2_RX
DCU1_R6
DCU1_R7
PTB7
PTB7
QSPI0_B_
CS1
LCD41
VIU_VSYNC
PTB8
PTB8
FTM1_QD_
PHA
VIU_DE
VIU_DE
PTB9
PTB9
FTM1_QD_
PHB
PTB10
PTB11
PTB10
PTB11
DCU0_
TCON4
CKO1
CKO2
ENET_TS_
CLKIN
SCI0_RX
DCU0_
TCON5
SNVS_
ALARM_
OUT_B
ENET0_
1588_TMR0
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
93
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
E13
D15
B14
A14
C14
A15
B12
165
156
162
161
163
160
171
PTB12
NMI
PTB12
SCI0_RTS
SCI0_CTS
CAN0_RX
CAN0_TX
CAN1_RX
CAN1_TX
SPI0_PCS1
SPI0_PCS5
SPI0_PCS4
DCU0_
TCON6
FB_AD1
FB_AD0
NMI
ENET0_
1588_TMR1
PTB13
PTB14
PTB15
PTB16
PTB17
PTB18
PTB13
PTB14
PTB15
PTB16
PTB17
PTB18
DCU0_
TCON7
TRACECTL
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
DCU0_
TCON8
DCU1_PCLK
DCU0_
TCON9
VIU_PIX_
CLK
DCU0_
TCON10
DCU0_
TCON11
EXT_AUDIO_
MCLK
VIU_DATA9
CCM_OBS0
C13
A13
E12
D12
V10
T10
T9
167
169
173
172
61
PTB19
PTB19
PTB20
PTB21
PTB22
SPI0_PCS0
SPI0_SIN
VIU_DATA10 CCM_OBS1
VIU_DATA11 CCM_OBS2
VIU_DATA12 DCU1_PCLK
PTB20
LCD42
LCD43
PTB21
SPI0_SOUT
SPI0_SCK
USB0_GND
USB0_DP
PTB22
VIU_FID
USB0_GND
USB0_DP
USB0_DM
USB0_VBUS
USB_DCAP
63
62
USB0_DM
USB0_VBUS
USB_DCAP
W11
Y10
Y11
60
59
64
USB0_
VBUS_
DETECT
USB0_
VBUS_
DETECT
Y9
W9
V9
—
—
—
—
—
USB1_GND
USB1_DP
USB1_GND
USB1_DP
USB1_DM
USB1_VBUS
USB1_DM
USB1_VBUS
W10
U9
USB1_
VBUS_
DETECT
USB1_
VBUS_
DETECT
L4
L5
8
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
RMII0_MDC/
MII0_MDC
FTM1CH0
SPI0_PCS3
SPI0_PCS2
ESAI_SCKT
ESAI_FST
SDHC0_CLK
VIU_DATA0
RCON18
RCON19
RCON20
DCU0_R0
DCU0_R1
DCU0_G0
9
RMII0_MDIO/ FTM1CH1
MII0_MDIO
SDHC0_CMD VIU_DATA1
M5
M3
L2
11
12
14
15
RMII0_CRS_
DV
SCI1_TX
ESAI_SDO0
ESAI_SDO1
SDHC0_
DAT0
VIU_DATA2
VIU_DATA3
VIU_DATA4
VIU_DATA5
RMII0_RXD1/ SCI1_RX
MII0_RXD[1]
SDHC0_
DAT1
RMII0_RXD0/ SCI1_RTS
MII0_RXD[0]
SPI1_PCS1
SPI1_PCS0
ESAI_SDO2/
ESAI_SDI3
SDHC0_
DAT2
M1
RMII0_RXER/ SCI1_CTS
MII0_RXER
ESAI_SDO3/
ESAI_SDI2
SDHC0_
DAT3
VF3xxR, VF5xxR, Rev. 8, 01/2018
94
NXP Semiconductors
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
N1
N2
N4
16
17
18
PTC6
PTC6
RMII0_TXD1/
MII0_TXD[1]
SPI1_SIN
ESAI_SDO5/
ESAI_SDI0
SDHC0_WP
VIU_DATA6
VIU_DATA7
VIU_DATA8
DCU0_G1
DCU0_B0
DCU0_B1
PTC7
PTC8
PTC7
PTC8
RMII0_TXD0/
MII0_TXD[0]
SPI1_SOUT
SPI1_SCK
ESAI_SDO4/
ESAI_SDI1
RMII0_TXEN/
MII0_TXEN
T15
U15
P4
—
—
—
PTC9
PTC9
RMII1_MDC
RMII1_MDIO
ESAI_SCKT
ESAI_FST
MLBCLK
PTC10
PTC11
PTC10
PTC11
MLBSIGNAL
MLBDATA
RMII1_CRS_
DV
ESAI_SDO0
P3
P1
R1
P2
R3
R4
—
—
—
—
—
—
PTC12
PTC13
PTC14
PTC15
PTC16
PTC17
PTC12
PTC13
PTC14
PTC15
PTC16
PTC17
RMII1_RXD1
RMII1_RXD0
RMII1_RXER
RMII1_TXD1
RMII1_TXD0
RMII1_TXEN
ESAI_SDO1
SAI2_TX_
BCLK
ESAI_SDO2/
ESAI_SDI3
SAI2_RX_
BCLK
ESAI_SDO3/
ESAI_SDI2
SCI5_TX
SCI5_RX
SCI5_RTS
SCI5_CTS
SAI2_RX_
DATA
ADC0_SE6
ADC0_SE7
ADC1_SE6
ESAI_SDO5/
ESAI_SDI0
SAI2_TX_
DATA
ESAI_SDO4/
ESAI_SDI1
SAI2_RX_
SYNC
ADC1_SE7
SAI2_TX_
SYNC
USB1_SOF_
PULSE
B10
D9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DDR_A[15]
DDR_A[14]
DDR_A[13]
DDR_A[12]
DDR_A[11]
DDR_A[10]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_A[5]
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
DDR_A[0]
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
DDR_CAS_b
DDR_CKE[0]
DDR_A15
DDR_A14
DDR_A13
DDR_A12
DDR_A11
DDR_A10
DDR_A9
A10
C10
D10
D7
B9
A11
A7
DDR_A8
DDR_A7
A9
DDR_A6
B6
DDR_A5
A6
DDR_A4
B7
DDR_A3
A8
DDR_A2
C11
C7
DDR_A1
DDR_A0
D8
DDR_BA2
DDR_BA1
DDR_BA0
DDR_CAS_b
DDR_CKE0
C9
C8
B4
A5
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
95
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
A2
B2
—
—
DDR_CLK[0]
DDR_CLK0
DDR_CLK_
b[0]
DDR_CLK_
b0
C5
—
DDR_CS_
b[0]
DDR_CS_b0
D2
H2
C1
G1
E2
H1
D1
J1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DDR_D[15]
DDR_D[14]
DDR_D[13]
DDR_D[12]
DDR_D[11]
DDR_D[10]
DDR_D[9]
DDR_D15
DDR_D14
DDR_D13
DDR_D12
DDR_D11
DDR_D10
DDR_D9
DDR_D[8]
DDR_D8
G3
C3
J3
DDR_D[7]
DDR_D7
DDR_D[6]
DDR_D6
DDR_D[5]
DDR_D5
F3
G4
D4
H3
F4
G2
J4
DDR_D[4]
DDR_D4
DDR_D[3]
DDR_D3
DDR_D[2]
DDR_D2
DDR_D[1]
DDR_D1
DDR_D[0]
DDR_D0
DDR_DQM[1]
DDR_DQM[0]
DDR_DQS[1]
DDR_DQS[0]
DDR_DQM1
DDR_DQM0
DDR_DQS1
DDR_DQS0
E1
D3
F1
DDR_DQS_
b[1]
DDR_DQS_
b1
E3
—
DDR_DQS_
b[0]
DDR_DQS_
b0
A4
C6
—
—
—
—
—
—
—
—
—
—
—
—
DDR_RAS_b
DDR_WE_b
DDR_ODT[0]
DDR_ODT[1]
DDR_VREF
DDR_ZQ
DDR_RAS_b
DDR_WE_b
DDR_ODT0
DDR_ODT1
DDR_VREF
DDR_ZQ
C4
B1
G5
A3
D6
DDR_RESET
PTD31
DDR_RESET
FB_AD31
J20
H20
H18
H17
H16
PTD31
NF_IO15
NF_IO14
NF_IO13
NF_IO12
NF_IO11
FTM3_CH0
FTM3_CH1
FTM3_CH2
FTM3_CH3
FTM3_CH4
SPI2_PCS1
SPI2_PCS0
SPI2_SIN
PTD30
PTD30
PTD29
PTD28
PTD27
FB_AD30
PTD29
FB_AD29
PTD28
FB_AD28
I2C2_SCL
I2C2_SDA
SPI2_SOUT
SPI2_SCK
PTD27
FB_AD27
VF3xxR, VF5xxR, Rev. 8, 01/2018
96
NXP Semiconductors
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
G16
G18
G19
G20
—
—
PTD26
PTD26
FB_AD26
FB_AD25
FB_AD24
FB_AD23
NF_IO10
NF_IO9
NF_IO8
NF_IO7
FTM3_CH5
FTM3_CH6
FTM3_CH7
SDHC1_WP
PTD25
PTD24
PTD23
PTD25
PTD24
—
124
PTD23/
MII0_
RXDATA[3]
FTM2CH0
FTM2CH1
ENET0_
1588_TMR0
SDHC0_
DAT4
SCI2_TX
SCI2_RX
DCU1_R3
DCU1_R4
F20
126
PTD22
PTD22/
MII0_
FB_AD22
NF_IO6
ENET0_
1588_TMR1
SDHC0_
DAT5
RXDATA[2]
F19
F17
F16
E18
128
129
130
131
PTD21
PTD20
PTD19
PTD18
PTD21/
MII0_CRS
FB_AD21
FB_AD20
FB_AD19
FB_AD18
NF_IO5
NF_IO4
NF_IO3
NF_IO2
ENET0_
1588_TMR2
SDHC0_
DAT6
SCI2_RTS
SCI2_CTS
DCU1_R5
DCU1_R0
DCU1_R1
DCU1_G0
PTD20/
MII0_COL
ENET0_
1588_TMR3
SDHC0_
DAT7
PTD19
PTD18
ESAI_SCKR
ESAI_FSR
I2C0_SCL
I2C0_SDA
FTM2_QD_
PHA
MII0_
TXDATA[3]
FTM2_QD_
PHB
MII0_
TXDATA[2]
E20
D20
Y17
132
133
86
PTD17
PTD16
PTD0
PTD17
PTD16
PTD0
FB_AD17
FB_AD16
NF_IO1
NF_IO0
SCI2_TX
ESAI_HCKR
ESAI_HCKT
I2C1_SCL
I2C1_SDA
FB_AD15
MII0_TXERR
DCU1_G1
DCU1_G2
QSPI0_A_
SCK
SPDIF_
EXTCLK
Y18
V18
Y19
W19
W20
V20
V19
U17
U18
U20
T20
T19
T18
87
88
89
90
91
92
93
94
97
98
99
100
101
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTD8
PTD9
PTD10
PTD11
PTD12
PTD13
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTD8
PTD9
PTD10
PTD11
PTD12
PTD13
QSPI0_A_
CS0
SCI2_RX
SCI2_RTS
SCI2_CTS
FB_AD14
FB_AD13
FB_AD12
FB_AD11
FB_AD10
FB_AD9
FB_AD8
FB_AD7
FB_AD6
FB_AD5
FB_AD4
FB_AD3
FB_AD2
SPDIF_IN1
QSPI0_A_
DATA3
SPI1_PCS3
SPI1_PCS2
SPI1_PCS1
SPI1_PCS0
SPI1_SIN
SPDIF_OUT1
QSPI0_A_
DATA2
SPDIF_
PLOCK
QSPI0_A_
DATA1
SPDIF_
SRCLK
QSPI0_A_
DATA0
QSPI0_A_
DQS
QSPI0_B_
SCK
SPI1_SOUT
SPI1_SCK
QSPI0_B_
CS0
FB_CLKOUT
SPI3_PCS1
SPI3_PCS0
SPI3_SIN
QSPI0_B_
DATA3
SAI1_TX_
SYNC
DCU1_B0
DCU1_B1
QSPI0_B_
DATA2
QSPI0_B_
DATA1
QSPI0_B_
DATA0
SPI3_SOUT
SPI3_SCK
QSPI0_B_
DQS
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
97
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
A19
A18
B17
A17
U8
141
142
149
150
57
PTB23
PTB23
SAI0_TX_
BCLK
SCI1_TX
SCI1_RX
SCI1_RTS
SCI1_CTS
FB_MUXED_ FB_TS_b
ALE
SCI3_RTS
SCI3_CTS
DCU1_G3
DCU1_G4
DCU1_G5
DCU1_G6
DCU1_G7
DCU1_B6
DCU1_B7
DCU1_B2
DCU1_B3
DCU1_B4
DCU1_B5
DCU1_B6
PTB24
PTB25
PTB26
PTB27
PTB28
PTC26
PTC27
PTC28
PTC29
PTC30
PTC31
PTE0
PTB24
PTB25
PTB26
PTB27
PTB28
PTC26
PTC27
PTC28
PTC29
PTC30
PTC31
PTE0
SAI0_RX_
BCLK
FB_MUXED_ NF_WE_b
TSIZ0
SAI0_RX_
DATA
FB_CS1_b
FB_CS0_b
FB_OE_b
FB_RW_b
FB_TA_b
NF_CE0_b
RCON21
RCON22
RCON23
RCON24
RCON25
RCON26
RCON27
RCON28
RCON29
BOOTMOD1
SAI0_TX_
DATA
RCON21
RCON22
RCON23
RCON24
RCON25
RCON26
RCON27
RCON28
RCON29
NF_CE1_b
SAI0_RX_
SYNC
FB_MUXED_ NF_RE_b
TBST_b
A16
D16
E16
E15
C16
T8
151
153
154
155
152
58
SAI0_TX_
SYNC
SAI1_TX_
BCLK
SPI0_PCS5
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
SPI1_PCS2
NF_RB_b
SAI1_RX_
BCLK
FB_BE3_b
FB_BE2_b
FB_BE1_b
FB_CS3_b
FB_CS2_b
NF_ALE
NF_CLE
SAI1_RX_
DATA
SAI1_TX_
DATA
FB_MUXED_
TSIZ1
SAI1_RX_
SYNC
FB_MUXED_ FB_TSIZ0
BE0_b
ADC0_SE5
ADC1_SE5
W5
42
SAI1_TX_
SYNC
N16
103
DCU0_
HSYNC/
DCU0_
TCON1
BOOTMOD1
BOOTMOD0
LCD0
LCD1
N18
104
PTE1
BOOTMOD0
PTE1
DCU0_
VSYNC/
DCU0_
TCON2
N19
Y15
105
77
PTE2
PTE3
PTE2
PTE3
DCU0_PCLK
LCD2
LCD3
DCU0_TAG/
DCU0_
TCON0
N20
106
PTE4
PTE4
DCU0_DE/
DCU0_
LCD4
TCON3
T16
W16
M20
M19
M17
M16
L16
80
PTE5
PTE6
PTE7
PTE8
PTE9
PTE10
PTE11
PTE12
PTE5
PTE6
PTE7
PTE8
PTE9
PTE10
PTE11
PTE12
DCU0_R0
DCU0_R1
DCU0_R2
DCU0_R3
DCU0_R4
DCU0_R5
DCU0_R6
DCU0_R7
LCD5
LCD6
LCD7
LCD8
LCD9
LCD10
LCD11
LCD12
81
109
110
111
112
113
114
RCON0
RCON1
RCON2
RCON3
RCON4
RCON5
RCON0
RCON1
RCON2
RCON3
RCON4
RCON5
L17
SPI1_PCS3
LPT_ALT0
VF3xxR, VF5xxR, Rev. 8, 01/2018
98
NXP Semiconductors
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
Y16
W15
L18
L20
K20
K19
K18
A12
V16
W17
J17
78
76
PTE13
PTE13
DCU0_G0
DCU0_G1
DCU0_G2
DCU0_G3
DCU0_G4
DCU0_G5
DCU0_G6
DCU0_G7
DCU0_B0
DCU0_B1
DCU0_B2
DCU0_B3
DCU0_B4
DCU0_B5
DCU0_B6
DCU0_B7
LCD13
PTE14
PTE15
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
PTE24
PTE25
PTE26
PTE27
PTE28
PTA7
PTE14
PTE15
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
PTE24
PTE25
PTE26
PTE27
PTE28
PTA7
LCD14
LCD15
LCD16
LCD17
LCD18
LCD19
LCD20
LCD21
LCD22
LCD23
LCD24
LCD25
LCD26
LCD27
LCD28
115
116
117
118
119
170
79
RCON6
RCON6
RCON7
RCON8
RCON9
RCON10
RCON11
RCON7
RCON8
RCON9
RCON10
RCON11
I2C0_SCL
I2C0_SDA
EWM_in
84
122
134
135
137
138
120
75
RCON12
RCON13
RCON14
RCON15
RCON16
RCON17
RCON12
RCON13
RCON14
RCON15
RCON16
RCON17
D19
C19
C20
B20
K16
V15
I2C1_SCL
I2C1_SDA
EWM_out
VIU_PIX_
CLK
T14
U14
T13
—
—
—
EXT_
TAMPER0
EXT_
TAMPER0
EXT_
TAMPER1
EXT_
TAMPER1
EXT_
EXT_
TAMPER2/
EXT_WM0_
TAMPER_IN
TAMPER2/
EXT_WM0_
TAMPER_IN
U13
—
EXT_
EXT_
TAMPER3/
EXT_WM0_
TAMPER_
OUT
TAMPER3/
EXT_WM0_
TAMPER_
OUT
U12
U10
—
—
EXT_
EXT_
TAMPER4/
EXT_WM1_
TAMPER_IN
TAMPER4/
EXT_WM1_
TAMPER_IN
EXT_
EXT_
TAMPER5/
EXT_WM1_
TAMPER_
OUT
TAMPER5/
EXT_WM1_
TAMPER_
OUT
G7
J7
2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
22
48
—
85
L7
H8
K8
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
99
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
M8
P8
102
125
136
174
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G9
N9
H10
P10
G11
N11
H12
P12
G13
J13
L13
N13
H14
K14
M14
P14
A1
A20
B3
13
20
25
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B5
B8
B11
B13
B16
B19
C2
D17
E5
E8
E11
E14
E19
F2
G17
H4
J2
J18
M2
VF3xxR, VF5xxR, Rev. 8, 01/2018
100
NXP Semiconductors
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
M4
M18
R2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R18
U7
U19
V13
W6
V17
Y1
Y20
H19
L19
P19
J5
SDRAMC_
VDD2P5
SDRAMC_
VDD2P5
E6
E10
E4
—
—
—
—
—
—
—
—
—
—
SDRAMC_
VDD2P5
SDRAMC_
VDD2P5
SDRAMC_
VDD2P5
SDRAMC_
VDD2P5
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
D5
F5
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
H5
K5
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
E7
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
E9
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
D11
SDRAMC_
VDD1P5
SDRAMC_
VDD1P5
K3
N3
10
21
52
—
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
V8
C12
C15
U16
K17
83
95
108
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
101
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
N17
T17
C18
F18
W18
H7
127
140
146
158
168
—
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD33
VDD33
VDD33
VDD33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K7
74
82
96
107
—
M7
P7
G8
J8
L8
139
—
N8
H9
157
175
176
—
J9
K9
L9
M9
—
P9
—
G10
J10
K10
L10
M10
N10
H11
J11
K11
L11
M11
P11
G12
J12
K12
L12
M12
N12
H13
K13
M13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VF3xxR, VF5xxR, Rev. 8, 01/2018
102
NXP Semiconductors
Pinouts
364
176
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
P13
G14
J14
L14
N14
N7
—
—
VSS
VSS
VSS
VSS
—
VSS
VSS
—
VSS
VSS
—
VSS
VSS
—
FA_VDD
VBAT
VSS
FA_VDD
VBAT
VSS
V14
—
—
FLG
12.2 Pinout diagrams
NOTE
The 176 LQFP parts are not pin compatible between the F and
R series families devices.
NOTE
If tamper detection is not required, the tamper pins must be tied
to ground.
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
103
Pinouts
VSS
VDD
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
PTD17
PTD18
PTD19
PTD20
PTD21
VDD33
PTD22
VDD
2
JTCLK/SWCLK
JTDI
3
4
JTDO
5
JTMS/SWDIO
PTA12
6
7
PTC0
8
PTC1
9
PTD23
PTB9
VDD33
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PTC2
PTE23
PTB8
PTC3
VSS
PTE28
PTE19
PTE18
PTE17
PTE16
PTE15
PTE12
PTE11
PTE10
PTE9
PTC4
PTC5
PTC6
PTC7
PTC8
PTA6
VSS
VDD33
VDD
FLG
Ext_POR
VDDREG
VSS
PTE8
PTE7
VDD33
VSS
BCTRL
TEST
PTE4
RESETB/RESET_OUT
DACO0
PTE2
PTE1
DACO1
PTE0
VDDA33_ADC
VSSA33_ADC
VREFL_ADC
VREFH_ADC
VADCSE0
VDD12_AFE
VADCSE1
VSS12_AFE
VSSA33_AFE
VDDA33_AFE
VADC_AFE_BANDGAP
PTC31
VDD
PTD13
PTD12
PTD11
PTD10
PTD9
VSS
98
97
96
95
VDD33
PTD8
PTD7
PTD6
PTD5
PTD4
PTD3
94
93
92
91
PTA16
90
PTA17
89
Figure 59. 176 LQFP Pinout Diagram
VF3xxR, VF5xxR, Rev. 8, 01/2018
104
NXP Semiconductors
Pinouts
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
VSS
DDR_
CLK[0]
DDR_ZQ
DDR_
RAS_b
DDR_
CKE[0]
DDR_A[4] DDR_A[7] DDR_A[2] DDR_A[6] DDR_A[13] DDR_A[8]
PTE20
PTB20
PTB15
PTB17
PTB28
PTB26
PTB24
PTB23
VSS
A
B
C
D
E
F
DDR_
ODT[1]
DDR_
CLK_b[0]
VSS
DDR_
CAS_b
VSS
DDR_A[5] DDR_A[3]
VSS
DDR_A[9] DDR_A[15]
VSS
PTB18
VDD33
PTB22
PTB21
VSS
PTB14
PTB16
PTB11
VSS
PTB10
VDD33
PTB13
PTC28
VSS
PTB25
PTA23
VSS
PTA20
VDD33
PTA21
PTD18
VDD33
PTD25
PTD29
VSS
VSS
PTE25
PTE24
VSS
PTE27
PTE26
PTD16
PTD17
PTD22
PTD23
PTD30
PTD31
PTE17
PTE16
PTE7
DDR_D[13]
VSS
DDR_D[6]
DDR_
ODT[0]
DDR_
CS_b[0]
DDR_
WE_b
DDR_A[0] DDR_BA[0] DDR_BA[1] DDR_A[12] DDR_A[1]
PTB19
PTB7
PTC29
PTC26
PTC27
PTD19
PTD26
PTD27
PTB8
DDR_D[9] DDR_D[15]
DDR_
DQS[0]
DDR_
D[2]
SDRAMC_
VDD1P5
DDR_
RESET
DDR_A[10] DDR_BA[2] DDR_A[14]
DDR_
A[11]
SDRAMC_
VDD1P5
DDR_
DQS[1]
DDR_
D[11]
DDR_
DQS_b[0]
SDRAMC_
VDD1P5
VSS
SDRAMC_ SDRAMC_
VSS
SDRAMC_ SDRAMC_
VSS
PTB12
PTA22
PTD20
VSS
VDD2P5
VDD1P5
VDD1P5
VDD2P5
DDR_
DQS_b[1]
VSS
DDR_D[4]
DDR_
D[0]
SDRAMC_
VDD1P5
PTD21
PTD24
VSS
G
H
J
DDR_
D[12]
DDR_
DQM[1]
DDR_
D[7]
DDR_
D[3]
DDR_
VREF
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
G
H
J
DDR_
D[10]
DDR_
D[14]
DDR_
D[1]
VSS
SDRAMC_
VDD1P5
PTD28
PTE23
VDD33
PTE12
PTE9
DDR_D[8]
JTDO
VSS
JTDI
DDR_D[5]
VDD33
PTA12
PTC3
DDR_
DQM[0]
SDRAMC_
VDD2P5
VDD
PTB9
PTE18
VSS
K
L
JTCLK/
SWCLK
SDRAMC_
VDD1P5
VSS
PTE28
PTE11
PTE10
PTE0
PTE19
PTE15
VSS
K
L
JTMS
/SWDIO
PTC4
VSS
PTC0
VSS
PTC1
PTC2
VDD
M
N
P
R
T
PTC5
PTC6
VSS
PTE8
PTE2
VSS
M
N
P
R
T
PTC7
PTC15
VSS
VDD33
PTC12
PTC16
TEST
PTC8
PTC11
PTC17
PTA6
FA_VDD
VSS
VDD33
PTA30
PTA25
VDD33
PTD8
PTE1
PTE4
PTC13
PTC14
TEST2
DACO0
VDDREG
PTA31
PTA24
PTE5
PTA29
VSS
PTA28
PTA27
PTD11
PTD10
PTD6
VSS12_
AFE
PTA26
PTD12
VSS
DECAP_
V25_LDO
_OUT
RESETB
/RESET_
OUT
EXT_TAMPER2
/EXT_WM0_
TAMPER_IN
BCTRL
DACO1
VDD12_
AFE
PTB0
PTA19
PTA18
VSS
PTB1
VSS
PTC30
PTB27
VDD33
PTB6
USB0_DM USB0_DP
VDD33_
LDOIN
EXT_
TAMPER0
PTC9
PTC10
PTA7
PTD13
PTD9
VADC_
AFE_
BANDGAP
USB1_
EXT_TAMPER4
/EXT_WM1_
TAMPER_IN
EXT_TAMPER3
/EXT_WM0_
TAMPER_OUT
EXT_TAMPER5
U
V
W
Y
VREFL_
ADC
VADCSE1
VSS_KEL0
VSS
EXT_
TAMPER1
VDD33
PTE21
PTE6
U
V
W
Y
/EXT_WM1_
VBUS_
TAMPER_OUT
DETECT
DECAP_
V11_LDO_
OUT
VDDA33_ VSSA33_ VDDA33_ VSSA33_ VADCSE3
ADC ADC AFE AFE
PTB2
PTB3
USB1_DM
USB1_DP
USB0_
GND
VSS
VBAT
VSS
PTD2
PTD7
PTD4
VREFH_ ADC0SE9 ADC1SE8 VADCSE2
ADC
PTC31
USB1_
VBUS
USB0_
VBUS
XTAL32
XTAL
LVDS0P
PTE14
PTE22
VDD33
PTD5
USB0_
VBUS_
DETECT
VSS
1
ADC0SE8 ADC1SE9 VADCSE0
PTA16
5
PTA17
6
PTB4
7
PTB5
8
USB1_GND
9
USB_
DCAP
EXTAL32
12
EXTAL
13
LVDS0N
14
PTE3
15
PTE13
16
PTD0
17
PTD1
18
PTD3
19
VSS
20
2
3
4
10
11
Figure 60. 364-pin BGA package ballmap
12.2.1 GPIO Mapping
Table 78. RGPIO versus Pins
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
RGPIO[0]
PORT0[0]
PTA6
IOMUXC_PTA6
40048000
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
105
Pinouts
Table 78. RGPIO versus Pins (continued)
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
RGPIO[1]
RGPIO[2]
PORT0[1]
PORT0[2]
PORT0[3]
PORT0[4]
PORT0[5]
PORT0[6]
PORT0[7]
PORT0[8]
PORT0[9]
PORT0[10]
PORT0[11]
PORT0[12]
PORT0[13]
PORT0[14]
PORT0[15]
PORT0[16]
PORT0[17]
PORT0[18]
PORT0[19]
PORT0[20]
PORT0[21]
PORT0[22]
PORT0[23]
PORT0[24]
PORT0[25]
PORT0[26]
PORT0[27]
PORT0[28]
PORT0[29]
PORT0[30]
PORT0[31]
PORT1[0]
PORT1[1]
PORT1[2]
PORT1[3]
PORT1[4]
PORT1[5]
PORT1[6]
PORT1[7]
PTA8
PTA9
IOMUXC_PTA8
IOMUXC_PTA9
IOMUXC_PTA10
IOMUXC_PTA11
IOMUXC_PTA12
IOMUXC_PTA16
IOMUXC_PTA17
IOMUXC_PTA18
IOMUXC_PTA19
IOMUXC_PTA20
IOMUXC_PTA21
IOMUXC_PTA22
IOMUXC_PTA23
IOMUXC_PTA24
IOMUXC_PTA25
IOMUXC_PTA26
IOMUXC_PTA27
IOMUXC_PTA28
IOMUXC_PTA29
IOMUXC_PTA30
IOMUXC_PTA31
IOMUXC_PTB0
IOMUXC_PTB1
IOMUXC_PTB2
IOMUXC_PTB3
IOMUXC_PTB4
IOMUXC_PTB5
IOMUXC_PTB6
IOMUXC_PTB7
IOMUXC_PTB8
IOMUXC_PTB9
IOMUXC_PTB10
IOMUXC_PTB11
IOMUXC_PTB12
IOMUXC_PTB13
IOMUXC_PTB14
IOMUXC_PTB15
IOMUXC_PTB16
IOMUXC_PTB17
40048004
40048008
4004800C
40048010
40048014
40048018
4004801C
40048020
40048024
40048028
4004802C
40048030
40048034
40048038
4004803C
40048040
40048044
40048048
4004804C
40048050
40048054
40048058
4004805C
40048060
40048064
40048068
4004806C
40048070
40048074
40048078
4004807C
40048080
40048084
40048088
4004808C
40048090
40048094
40048098
4004809C
RGPIO[3]
PTA10
PTA11
PTA12
PTA16
PTA17
PTA18
PTA19
PTA20
PTA21
PTA22
PTA23
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
PTA30
PTA31
PTB0
RGPIO[4]
RGPIO[5]
RGPIO[6]
RGPIO[7]
RGPIO[8]
RGPIO[9]
RGPIO[10]
RGPIO[11]
RGPIO[12]
RGPIO[13]
RGPIO[14]
RGPIO[15]
RGPIO[16]
RGPIO[17]
RGPIO[18]
RGPIO[19]
RGPIO[20]
RGPIO[21]
RGPIO[22]
RGPIO[23]
RGPIO[24]
RGPIO[25]
RGPIO[26]
RGPIO[27]
RGPIO[28]
RGPIO[29]
RGPIO[30]
RGPIO[31]
RGPIO[32]
RGPIO[33]
RGPIO[34]
RGPIO[35]
RGPIO[36]
RGPIO[37]
RGPIO[38]
RGPIO[39]
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
PTB8
PTB9
PTB10
PTB11
PTB12
PTB13
PTB14
PTB15
PTB16
PTB17
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
106
NXP Semiconductors
Pinouts
Table 78. RGPIO versus Pins (continued)
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
400480A0
400480A4
400480A8
400480AC
400480B0
400480B4
400480B8
400480BC
400480C0
400480C4
400480C8
400480CC
400480D0
400480D4
400480D8
400480DC
400480E0
400480E4
400480E8
400480EC
400480F0
400480F4
400480F8
400480FC
40048100
40048104
40048108
4004810C
40048110
40048114
40048118
4004811C
40048120
40048124
40048128
4004812C
40048130
40048134
40048138
RGPIO[40]
RGPIO[41]
RGPIO[42]
RGPIO[43]
RGPIO[44]
RGPIO[45]
RGPIO[46]
RGPIO[47]
RGPIO[48]
RGPIO[49]
RGPIO[50]
RGPIO[51]
RGPIO[52]
RGPIO[53]
RGPIO[54]
RGPIO[55]
RGPIO[56]
RGPIO[57]
RGPIO[58]
RGPIO[59]
RGPIO[60]
RGPIO[61]
RGPIO[62]
RGPIO[63]
RGPIO[64]
RGPIO[65]
RGPIO[66]
RGPIO[67]
RGPIO[68]
RGPIO[69]
RGPIO[70]
RGPIO[71]
RGPIO[72]
RGPIO[73]
RGPIO[74]
RGPIO[75]
RGPIO[76]
RGPIO[77]
RGPIO[78]
PORT1[8]
PORT1[9]
PORT1[10]
PORT1[11]
PORT1[12]
PORT1[13]
PORT1[14]
PORT1[15]
PORT1[16]
PORT1[17]
PORT1[18]
PORT1[19]
PORT1[20]
PORT1[21]
PORT1[22]
PORT1[23]
PORT1[24]
PORT1[25]
PORT1[26]
PORT1[27]
PORT1[28]
PORT1[29]
PORT1[30]
PORT1[31]
PORT2[0]
PORT2[1]
PORT2[2]
PORT2[3]
PORT2[4]
PORT2[5]
PORT2[6]
PORT2[7]
PORT2[8]
PORT2[9]
PORT2[10]
PORT2[11]
PORT2[12]
PORT2[13]
PORT2[14]
PTB18
PTB19
PTB20
PTB21
PTB22
PTC0
IOMUXC_PTB18
IOMUXC_PTB19
IOMUXC_PTB20
IOMUXC_PTB21
IOMUXC_PTB22
IOMUXC_PTC0
IOMUXC_PTC1
IOMUXC_PTC2
IOMUXC_PTC3
IOMUXC_PTC4
IOMUXC_PTC5
IOMUXC_PTC6
IOMUXC_PTC7
IOMUXC_PTC8
IOMUXC_PTC9
IOMUXC_PTC10
IOMUXC_PTC11
IOMUXC_PTC12
IOMUXC_PTC13
IOMUXC_PTC14
IOMUXC_PTC15
IOMUXC_PTC16
IOMUXC_PTC17
IOMUXC_PTD31
IOMUXC_PTD30
IOMUXC_PTD29
IOMUXC_PTD28
IOMUXC_PTD27
IOMUXC_PTD26
IOMUXC_PTD25
IOMUXC_PTD24
IOMUXC_PTD23
IOMUXC_PTD22
IOMUXC_PTD21
IOMUXC_PTD20
IOMUXC_PTD19
IOMUXC_PTD18
IOMUXC_PTD17
IOMUXC_PTD16
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTC8
PTC9
PTC10
PTC11
PTC12
PTC13
PTC14
PTC15
PTC16
PTC17
PTD31
PTD30
PTD29
PTD28
PTD27
PTD26
PTD25
PTD24
PTD23
PTD22
PTD21
PTD20
PTD19
PTD18
PTD17
PTD16
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
107
Pinouts
Table 78. RGPIO versus Pins (continued)
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
RGPIO[79]
RGPIO[80]
RGPIO[81]
RGPIO[82]
RGPIO[83]
RGPIO[84]
RGPIO[85]
RGPIO[86]
RGPIO[87]
RGPIO[88]
RGPIO[89]
RGPIO[90]
RGPIO[91]
RGPIO[92]
RGPIO[93]
RGPIO[94]
RGPIO[95]
RGPIO[96]
RGPIO[97]
RGPIO[98]
RGPIO[99]
RGPIO[100]
RGPIO[101]
RGPIO[102]
RGPIO[103]
RGPIO[104]
RGPIO[105]
RGPIO[106]
RGPIO[107]
RGPIO[108]
RGPIO[109]
RGPIO[110]
RGPIO[111]
RGPIO[112]
RGPIO[113]
RGPIO[114]
RGPIO[115]
RGPIO[116]
RGPIO[117]
PORT2[15]
PORT2[16]
PORT2[17]
PORT2[18]
PORT2[19]
PORT2[20]
PORT2[21]
PORT2[22]
PORT2[23]
PORT2[24]
PORT2[25]
PORT2[26]
PORT2[27]
PORT2[28]
PORT2[29]
PORT2[30]
PORT2[31]
PORT3[0]
PORT3[1]
PORT3[2]
PORT3[3]
PORT3[4]
PORT3[5]
PORT3[6]
PORT3[7]
PORT3[8]
PORT3[9]
PORT3[10]
PORT3[11]
PORT3[12]
PORT3[13]
PORT3[14]
PORT3[15]
PORT3[16]
PORT3[17]
PORT3[18]
PORT3[19]
PORT3[20]
PORT3[21]
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTD8
PTD9
PTD10
PTD11
PTD12
PTD13
PTB23
PTB24
PTB25
PTB26
PTB27
PTB28
PTC26
PTC27
PTC28
PTC29
PTC30
PTC31
PTE0
IOMUXC_PTD0
IOMUXC_PTD1
IOMUXC_PTD2
IOMUXC_PTD3
IOMUXC_PTD4
IOMUXC_PTD5
IOMUXC_PTD6
IOMUXC_PTD7
IOMUXC_PTD8
IOMUXC_PTD9
IOMUXC_PTD10
IOMUXC_PTD11
IOMUXC_PTD12
IOMUXC_PTD13
IOMUXC_PTB23
IOMUXC_PTB24
IOMUXC_PTB25
IOMUXC_PTB26
IOMUXC_PTB27
IOMUXC_PTB28
IOMUXC_PTC26
IOMUXC_PTC27
IOMUXC_PTC28
IOMUXC_PTC29
IOMUXC_PTC30
IOMUXC_PTC31
IOMUXC_PTE0
IOMUXC_PTE1
IOMUXC_PTE2
IOMUXC_PTE3
IOMUXC_PTE4
IOMUXC_PTE5
IOMUXC_PTE6
IOMUXC_PTE7
IOMUXC_PTE8
IOMUXC_PTE9
IOMUXC_PTE10
IOMUXC_PTE11
IOMUXC_PTE12
4004813C
40048140
40048144
40048148
4004814C
40048150
40048154
40048158
4004815C
40048160
40048164
40048168
4004816C
40048170
40048174
40048178
4004817C
40048180
40048184
40048188
4004818C
40048190
40048194
40048198
4004819C
400481A0
400481A4
400481A8
400481AC
400481B0
400481B4
400481B8
400481BC
400481C0
400481C4
400481C8
400481CC
400481D0
400481D4
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
PTE7
PTE8
PTE9
PTE10
PTE11
PTE12
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
108
NXP Semiconductors
Pinouts
Table 78. RGPIO versus Pins (continued)
RGPIO
In GPIO module
Corresponding Pin
on the chip
IOMUX register name
IOMUX register
address
400481D8
400481DC
400481E0
400481E4
400481E8
400481EC
400481F0
400481F4
400481F8
400481FC
40048200
40048204
40048208
4004820C
40048210
40048214
40048218
RGPIO[118]
RGPIO[119]
RGPIO[120]
RGPIO[121]
RGPIO[122]
RGPIO[123]
RGPIO[124]
RGPIO[125]
RGPIO[126]
RGPIO[127]
RGPIO[128]
RGPIO[129]
RGPIO[130]
RGPIO[131]
RGPIO[132]
RGPIO[133]
RGPIO[134]
PORT3[22]
PORT3[23]
PORT3[24]
PORT3[25]
PORT3[26]
PORT3[27]
PORT3[28]
PORT3[29]
PORT3[30]
PORT3[31]
PORT4[0]
PORT4[1]
PORT4[2]
PORT4[3]
PORT4[4]
PORT4[5]
PORT4[6]
PTE13
PTE14
PTE15
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
PTE24
PTE25
PTE26
PTE27
PTE28
PTA7
IOMUXC_PTE13
IOMUXC_PTE14
IOMUXC_PTE15
IOMUXC_PTE16
IOMUXC_PTE17
IOMUXC_PTE18
IOMUXC_PTE19
IOMUXC_PTE20
IOMUXC_PTE21
IOMUXC_PTE22
IOMUXC_PTE23
IOMUXC_PTE24
IOMUXC_PTE25
IOMUXC_PTE26
IOMUXC_PTE27
IOMUXC_PTE28
IOMUXC_PTA7
12.2.2 Special Signal
Table 79. Special Signal Considerations
Special Signal
Comments
DDR_VREF
DDR_ZQ
When using DDR_VREF with DDR I/O, the nominal reference
voltage must be half of the SDRAMC_VDD1P5 supply. The
user must tie DDR_VREF to a precision external resistor
divider. Shunt each resistor with a closely-mounted 0.1 μF
capacitor.
DRAM calibration resistor 240 Ω 1ꢀ used as reference during
DRAM output buffer driver calibration should be connected
between this pad and GND
DECAP_V25_LDO_OUT
DCAP_V25_LDO_OUT can be tied to SDRAMC_VDD2P5 to
provide the predriver supply for the DDR I/O segment.
SDRAMC_VDD1P5 requires an external regulated supply. If
SDRAMC_VDD2P5 uses an external 2.5V supply, do NOT tie
it to DCAP_V25_LDO_OUT.
EXT_POR, TEST
Factory use only, tie to ground..
EXT_TAMPER0, EXT_TAMPER1, EXT_TAMPER2,
EXT_TAMPER3, EXT_TAMPER4, EXT_TAMPER5
Security related tamper detection inputs, if not in use they
must be tied to ground.
FA_VDD
Factory use only, tie to VDD.
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
109
Pinouts
Table 79. Special Signal Considerations (continued)
Special Signal
Comments
JTCLK, JTDI, JTDO, JTMS
For JTAG the use of external resistors is unnecessary.
However, if external resistors are used, the user must ensure
that the on-chip pull-up/down configuration is matched. For
example, do not use an external pull down on an input that
has on-chip pull-up. JTDO is configured with a keeper circuit
such that the floating condition is eliminated if an external pull
resistor is not present. An external pull resistor on JTDO is
detrimental and should be avoided.
LVDS0N, LVDS0P
Not recommended for application use, intended for clock
observation purposes during debug only.
RESETB/RESET_OUT
Active low input used to generate a system wide reset (except
the SRTC). A glitch filter is include to help prevent
unexpected resets, a minimum pulse width of 125 nsecs is
required to guarantee a reset is detected.
XTAL, EXTAL
A 24.0 MHz fundamental mode crystal should be connected
between XTAL and EXTAL. The crystal must be rated for a
drive level of 250 μW or higher. An ESR (equivalent series
resistance) of 80 Ω or less is recommended. This clock is
used as a reference for USB, so there are strict frequency
tolerance and jitter requirements. The crystal can be
eliminated if an external 24 MHz oscillator is available in the
system. In this case, XTAL must be directly driven by the
external oscillator and EXTAL floated. The XTAL signal level
must swing from ~0.8 x DECAP_V11_ LDO_OUT to ~0.2 V.
XTAL32, EXTAL32
If the user wishes to configure XTAL32 and EXTAL32 as an
RTC oscillator, a 32.768 kHz crystal, (≤50 kΩ ESR, 10 pF
load) should be connected between XTAL32 and EXTAL32.
Keep in mind the capacitors implemented on either side of the
crystal are about twice the crystal load capacitor. To hit the
exact oscillation frequency, the board capacitors need to be
reduced to account for board and chip parasitics. The
integrated oscillation amplifier is self biasing, but relatively
weak. Care must be taken to limit parasitic leakage from
XTAL32 and EXTAL32 to either power or ground (>100 MΩ).
This will debias the amplifier and cause a reduction of startup
margin. Typically XTAL32 and EXTAL32 should bias to
approximately 0.5 V. If it is desired to feed an external low
frequency clock into XTAL32 the EXTAL32 pin should be left
floating or driven with a complimentary signal. The logic level
of this forcing clock should not exceed DECAP_V11_
LDO_OUT level and the frequency should be <100 kHz under
typical conditions. In the case where the SIRC is used, it is
recommended to connect XTAL32 to ground and leave
EXTAL32 floating.
VF3xxR, VF5xxR, Rev. 8, 01/2018
110
NXP Semiconductors
Power Supply Pins
13 Power Supply Pins
13.1 Power Supply Pins
Table 80. Power Supply Pins
Supply Rail Name
DECAP_V11_ LDO_OUT
DECAP_V25_ LDO_OUT
364 MAP BGA
176 LQFP (R-series ONLY)
69
Comment
On-chip 1.1V LDO output
V12
T11
65
On-chip 2.5V LDO output
(Intended to supply DRAM IO
when required)
FA_VDD
N7
—
Factory Use Only (Connect to
VDD, internally bonded in
LQFP)
SDRAMC_ VDD1P5
D5, D11, E4, E7, E9, F5, H5, DRAM not supported in LQFP 1.5V DDR3 DRAM Supply
K5
(1.2V for LPDDR2)
SDRAMC_ VDD2P5
USB_DCAP
E6, E10, J5
Y10
DRAM not supported in LQFP 2.5V DRAM Supply
59
On-chip 3V LDO output
(Intended to be fed by
external USB VBUS supply)
USB0_GND
V10
Y9
61
USB1_GND
USB1 not supported in LQFP
41
VADC_AFE_ BANDGAP
VBAT
U5
Video ADC Bandgap Output
V14
VBAT not supported in LQFP On-chip SNVS regulator
battery back-up supply option
VDD
G7, G9, G11, G13, H8, H10, 2, 22, 48, 85, 102, 125, 136, 1.2V Core Supply (Internally
H12, H14, J7, J13, K8, K14,
L7, L13, M8, M14, N9, N11,
N13, P8, P10, P12, P14
174
Regulated)
VDD33
C12, C15, C18, F18, K3, K17, 10, 21, 52, 83, 95, 108, 127, 3.3V IO Supply
N3, N17, T17, U16, V8, W18 140, 146, 158, 168
VDDA33_ADC
VDD12_AFE
VDDA33_AFE
VDD33_ LDOIN
V1
31
36
40
68
3.3V Analog To Digital
convertor supply
T5
1.2V Analog Front End supply
for Video ADC
V3
T12
3.3V Analog Front End supply
for Video ADC
On-chip 2.5V LDO, 1.1V LDO
and SNVS regulators input
supply
VDDREG
P5
24
On-chip HPREG, LPREG,
WBREG and ULPREG
regulators input supply
VREFH_ADC
VREFL_ADC
W1
U3
34
33
ATD High Voltage Reference
ATD Low Voltage Reference
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
111
Functional Assignment Pins
Table 80. Power Supply Pins (continued)
Supply Rail Name
364 MAP BGA
176 LQFP (R-series ONLY)
Comment
VSS
A1, A20, B3, B5, B8, B11,
1, 13, 20, 25, 45, 67, 74, 82, Ground. Connect "Flag pad
B13, B16, B19, C2, D17, E5, 96, 107, 139, 144, 157, 175, (FLG)" to the internal GND
E8, E11, E14, E19, F2, G8,
G10, G12, G14, G17, H4, H7,
H9, H11, H13, H19, J2, J8,
J9, J10, J11, J12, J14, J18,
K7, K9, K10, K11, K12, K13,
L8, L9, L10, L11, L12, L14,
L19, M2, M4, M7, M9, M10,
M11, M12, M13, M18, N8,
N10, N12, N14, P7, P9, P11,
P13, P19, R2, R18, U7, U19,
V11, V13, V17, W6, Y1, Y20
176, FLG
plane with numerous vias—for
both electrical and thermal
purposes.
VSSA33_ADC
VSS12_AFE
VSSA33_AFE
VSS_KEL0
V2
32
38
39
66
ATD Ground
R5
V4
Video ADC Ground
Video ADC Ground
U11
Ground (VSS and VSS_KEL0
are NOT connected internally)
14 Functional Assignment Pins
14.1 Functional Assignment Pins
Table 81. Functional Assignment Pins
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
ADC0SE8
ADC0SE9
ADC1SE8
ADC1SE9
Y2
W2
W3
Y3
—
—
—
—
VDDA33_A Analog
DC
—
—
—
—
ADC0SE8
ADC0SE9
ADC1SE8
ADC1SE9
—
—
—
—
—
—
—
—
VDDA33_A Analog
DC
VDDA33_A Analog
DC
VDDA33_A Analog
DC
BCTRL
DACO0
T2
U1
26
29
VDDREG Analog
—
—
BCTRL
DACO0
—
—
—
—
VDDA33_A Analog
DC
DACO1
U2
C7
30
—
VDDA33_A Analog
DC
—
—
DACO1
—
—
—
—
DDR_A[0]
SDRAMC_ DDR
VDD2P5
DDR_A[0]
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
112
NXP Semiconductors
Functional Assignment Pins
Table 81. Functional Assignment Pins
(continued)
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
DDR_A[1]
DDR_A[2]
DDR_A[3]
DDR_A[4]
DDR_A[5]
DDR_A[6]
DDR_A[7]
DDR_A[8]
DDR_A[9]
DDR_A[10]
DDR_A[11]
DDR_A[12]
DDR_A[13]
DDR_A[14]
DDR_A[15]
DDR_BA[0]
DDR_BA[1]
DDR_BA[2]
C11
A8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDRAMC_ DDR
VDD2P5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DDR_A[1]
DDR_A[2]
DDR_A[3]
DDR_A[4]
DDR_A[5]
DDR_A[6]
DDR_A[7]
DDR_A[8]
DDR_A[9]
DDR_A[10]
DDR_A[11]
DDR_A[12]
DDR_A[13]
DDR_A[14]
DDR_A[15]
DDR_BA[0]
DDR_BA[1]
DDR_BA[2]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDRAMC_ DDR
VDD2P5
B7
SDRAMC_ DDR
VDD2P5
A6
SDRAMC_ DDR
VDD2P5
B6
SDRAMC_ DDR
VDD2P5
A9
SDRAMC_ DDR
VDD2P5
A7
SDRAMC_ DDR
VDD2P5
A11
B9
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
D7
D10
C10
A10
D9
B10
C8
C9
D8
B4
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
DDR_CAS_
b
SDRAMC_ DDR
VDD2P5
DDR_CAS_
b
DDR_CKE[0
]
A5
SDRAMC_ DDR
VDD2P5
DDR_CKE[0 —
]
DDR_CLK[0
]
A2
SDRAMC_ DDR
VDD2P5
DDR_CLK[0 —
]
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
113
Functional Assignment Pins
Table 81. Functional Assignment Pins
(continued)
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
DDR_CLK_
b[0]
B2
C5
F4
H3
D4
G4
F3
J3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDRAMC_ DDR
VDD2P5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DDR_CLK_
b[0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DDR_CS_b[
0]
SDRAMC_ DDR
VDD2P5
DDR_CS_b[ —
0]
DDR_D[0]
DDR_D[1]
DDR_D[2]
DDR_D[3]
DDR_D[4]
DDR_D[5]
DDR_D[6]
DDR_D[7]
DDR_D[8]
DDR_D[9]
DDR_D[10]
DDR_D[11]
DDR_D[12]
DDR_D[13]
DDR_D[14]
DDR_D[15]
SDRAMC_ DDR
VDD2P5
DDR_D[0]
DDR_D[1]
DDR_D[2]
DDR_D[3]
DDR_D[4]
DDR_D[5]
DDR_D[6]
DDR_D[7]
DDR_D[8]
DDR_D[9]
DDR_D[10]
DDR_D[11]
DDR_D[12]
DDR_D[13]
DDR_D[14]
DDR_D[15]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
C3
G3
J1
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
D1
H1
E2
G1
C1
H2
D2
J4
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
SDRAMC_ DDR
VDD2P5
DDR_DQM[
0]
SDRAMC_ DDR
VDD2P5
DDR_DQM[
0]
DDR_DQM[
1]
G2
D3
SDRAMC_ DDR
VDD2P5
DDR_DQM[
1]
DDR_DQS[
0]
SDRAMC_ DDR
VDD2P5
DDR_DQS[
0]
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
114
NXP Semiconductors
Functional Assignment Pins
Table 81. Functional Assignment Pins
(continued)
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
DDR_DQS_
b[0]
E3
E1
F1
C4
B1
A4
D6
G5
C6
A3
—
—
—
—
—
—
—
—
—
—
SDRAMC_ DDR
VDD2P5
—
—
—
—
—
—
—
—
—
—
DDR_DQS_ —
b[0]
—
—
—
—
—
—
—
—
—
—
DDR_DQS[
1]
SDRAMC_ DDR
VDD2P5
DDR_DQS[
1]
—
DDR_DQS_
b[1]
SDRAMC_ DDR
VDD2P5
DDR_DQS_ —
b[1]
DDR_ODT[0
]
SDRAMC_ DDR
VDD2P5
DDR_ODT[0 —
]
DDR_ODT[1
]
SDRAMC_ DDR
VDD2P5
DDR_ODT[1 —
]
DDR_RAS_
b
SDRAMC_ DDR
VDD2P5
DDR_RAS_
b
—
DDR_RESE
T
SDRAMC_ DDR
VDD2P5
DDR_RESE —
T
DDR_VREF
DDR_WE_b
DDR_ZQ
SDRAMC_ DDR
VDD2P5
DDR_VREF —
SDRAMC_ DDR
VDD2P5
DDR_WE_b —
SDRAMC_ DDR
VDD2P5
DDR_ZQ
—
EXT_POR
T1
23
—
VDD33
VBAT
GPIO
—
—
EXT_POR
—
—
—
—
EXT_TAMP
ER0
T14
Analog
EXT_TAMP
ER0
EXT_TAMP
ER1
U14
T13
—
—
VBAT
VBAT
Analog
Analog
—
—
EXT_TAMP
ER1
—
—
—
—
EXT_TAMP
ER2/
EXT_TAMP
ER2/
EXT_WM0_
TAMPER_I
N
EXT_WM0_
TAMPER_I
N
EXT_TAMP
ER3/
EXT_WM0_
TAMPER_
OUT
U13
U12
U10
—
—
—
VBAT
VBAT
VBAT
Analog
Analog
Analog
—
—
—
EXT_TAMP
ER3/
EXT_WM0_
TAMPER_
OUT
—
—
—
—
—
—
EXT_TAMP
ER4/
EXT_WM1_
TAMPER_I
N
EXT_TAMP
ER4/
EXT_WM1_
TAMPER_I
N
EXT_TAMP
ER5/
EXT_TAMP
ER5/
EXT_WM1_
TAMPER_
OUT
EXT_WM1_
TAMPER_
OUT
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
115
Functional Assignment Pins
Table 81. Functional Assignment Pins
(continued)
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
EXTAL
Y13
Y12
K4
73
70
3
DECAP_V1 Analog
—
—
EXTAL
—
—
—
—
1_
LDO_OUT
EXTAL32
DECAP_V1 Analog
EXTAL32
JTAG
1_
LDO_OUT
JTCLK/
SWCLK
VDD33
GPIO
ALT1
Input
100K PU
JTDI
K2
K1
L1
4
5
6
VDD33
VDD33
VDD33
GPIO
GPIO
GPIO
ALT1
ALT1
ALT1
JTAG
JTAG
JTAG
Input
100K PU
—
JTDO
Disabled
Input
JTMS/
100K PU
SWDIO
LVDS0P
W14
Y14
—
—
DECAP_V2 Analog
—
—
LVDS0P
LVDS0N
—
—
—
—
5_
LDO_OUT
LVDS0N
DECAP_V2 Analog
5_
LDO_OUT
PTA6
PTA7
N5
V15
L3
19
75
7
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT3
ALT3
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
RCON30
RCON31
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Input
PTA12
PTA16
PTA17
PTA18
PTA19
PTA20
PTA21
PTA22
PTA23
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
PTA30
PTA31
PTB0
Y5
43
44
46
47
143
145
147
148
—
Y6
V6
U6
B18
D18
E17
C17
R16
R17
R19
R20
P20
P18
P17
P16
T6
—
—
—
—
—
—
—
49
50
51
PTB1
T7
Disabled
Disabled
PTB2
V7
Input
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
116
NXP Semiconductors
Functional Assignment Pins
Table 81. Functional Assignment Pins
(continued)
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
PTB3
PTB4
W7
Y7
53
54
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
GPIO
ALT0
GPIO
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Input
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT3
ALT3
ALT3
ALT3
ALT3
ALT3
ALT7
ALT7
ALT7
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
GPIO
PTB5
Y8
55
GPIO
PTB6
W8
D13
J16
J19
B15
D14
E13
D15
B14
A14
C14
A15
B12
C13
A13
E12
D12
A19
A18
B17
A17
U8
56
GPIO
PTB7
166
121
123
159
164
165
156
162
161
163
160
171
167
169
173
172
141
142
149
150
57
GPIO
PTB8
GPIO
PTB9
GPIO
PTB10
PTB11
PTB12
PTB13
PTB14
PTB15
PTB16
PTB17
PTB18
PTB19
PTB20
PTB21
PTB22
PTB23
PTB24
PTB25
PTB26
PTB27
PTB28
PTC0
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Disabled
Disabled
GPIO
Input
GPIO
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Input
GPIO
GPIO
GPIO
GPIO
GPIO
RCON21
RCON22
RCON23
RCON18
RCON19
RCON20
GPIO
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Input
A16
L4
151
8
Input
Input
PTC1
L5
9
Input
PTC2
M5
11
Input
PTC3
M3
12
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTC4
L2
14
GPIO
PTC5
M1
15
GPIO
PTC6
N1
16
GPIO
PTC7
N2
17
GPIO
PTC8
N4
18
GPIO
PTC9
T15
U15
—
GPIO
PTC10
—
GPIO
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
117
Functional Assignment Pins
Table 81. Functional Assignment Pins
(continued)
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
PTC11
PTC12
PTC13
PTC14
PTC15
PTC16
PTC17
PTC26
PTC27
PTC28
PTC29
PTC30
PTC31
PTD0
P4
P3
—
—
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
GPIO
ALT0
GPIO
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Input
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT3
ALT3
ALT3
ALT3
ALT3
ALT3
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
GPIO
P1
—
GPIO
R1
—
GPIO
P2
—
GPIO
R3
—
GPIO
R4
—
GPIO
D16
E16
E15
C16
T8
153
154
155
152
58
RCON24
RCON25
RCON26
RCON27
RCON28
RCON29
GPIO
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Input
Input
Input
Input
W5
42
Input
Y17
Y18
V18
Y19
W19
W20
V20
V19
U17
U18
U20
T20
T19
T18
D20
E20
E18
F16
F17
F19
F20
G20
G19
G18
86
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTD1
87
GPIO
PTD2
88
GPIO
PTD3
89
GPIO
PTD4
90
GPIO
PTD5
91
GPIO
PTD6
92
GPIO
PTD7
93
GPIO
PTD8
94
GPIO
PTD9
97
GPIO
PTD10
PTD11
PTD12
PTD13
PTD16
PTD17
PTD18
PTD19
PTD20
PTD21
PTD22
PTD23
PTD24
PTD25
98
GPIO
99
GPIO
100
101
133
132
131
130
129
128
126
124
—
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
—
GPIO
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
118
NXP Semiconductors
Functional Assignment Pins
Table 81. Functional Assignment Pins
(continued)
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
PTD26
PTD27
PTD28
PTD29
PTD30
PTD31
PTE0
G16
H16
H17
H18
H20
J20
—
—
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
GPIO
ALT0
GPIO
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Input
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT0
ALT0
ALT0
ALT0
ALT2
ALT2
ALT0
ALT0
ALT0
ALT0
ALT0
ALT3
ALT3
ALT3
ALT3
ALT3
ALT3
ALT0
ALT0
ALT3
ALT3
ALT3
ALT3
ALT3
ALT3
ALT0
ALT0
ALT3
ALT3
ALT3
ALT3
ALT3
ALT3
—
GPIO
—
GPIO
—
GPIO
—
GPIO
—
GPIO
N16
N18
N19
Y15
N20
T16
W16
M20
M19
M17
M16
L16
L17
Y16
W15
L18
L20
K20
K19
K18
A12
V16
W17
J17
103
104
105
77
BMODE1
BMODE0
GPIO
Disabled
Disabled
PTE1
Input
PTE2
Disabled
Disabled
Disabled
Disabled
Disabled
Input
PTE3
GPIO
PTE4
106
80
GPIO
PTE5
GPIO
PTE6
81
GPIO
PTE7
109
110
111
112
113
114
78
RCON0
RCON1
RCON2
RCON3
RCON4
RCON5
GPIO
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTE8
Input
PTE9
Input
PTE10
PTE11
PTE12
PTE13
PTE14
PTE15
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
PTE24
PTE25
PTE26
PTE27
PTE28
Input
Input
Input
Disabled
Disabled
Input
76
GPIO
115
116
117
118
119
170
79
RCON6
RCON7
RCON8
RCON9
RCON10
RCON11
GPIO
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Input
Input
Input
Input
Input
Disabled
Disabled
Input
84
GPIO
122
134
135
137
138
120
28
RCON12
RCON13
RCON14
RCON15
RCON16
RCON17
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
—
D19
C19
C20
B20
K16
T4
Input
Input
Input
Input
Input
RESETB/
RESET_OU
T
RESETB/
RESET_OU
T
—
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
119
Functional Assignment Pins
Table 81. Functional Assignment Pins
(continued)
Signal
Name
364 MAP
BGA
176 LQFP
(R-series
ONLY)
Power
Group
Pad Type
Default
Mode
(Reset)
Default
Function
Input/
Output
Value
TEST
T3
T9
27
62
63
60
VDD33
GPIO
—
—
—
—
TEST
—
—
—
—
—
—
—
—
USB0_DM
USB0_DP
USB_DCAP Analog
USB_DCAP Analog
USB_DCAP Analog
USB0_DM
USB0_DP
T10
W11
USB0_VBU
S
USB0_VBU
S
USB0_VBU
S_ DETECT
Y11
64
USB_DCAP Analog
—
USB0_VBU
S_ DETECT
—
—
USB1_DM
USB1_DP
V9
W9
—
—
—
USB_DCAP Analog
USB_DCAP Analog
USB_DCAP Analog
—
—
—
USB1_DM
USB1_DP
—
—
—
—
—
—
USB1_VBU
S
W10
USB1_VBU
S
USB1_VBU
S_ DETECT
U9
Y4
—
USB_DCAP Analog
—
—
USB1_VBU
S_ DETECT
—
—
—
—
VADCSE0
VADCSE1
VADCSE2
VADCSE3
35
VDDA33_A Analog
VADCSE0
VADCSE1
VADCSE2
VADCSE3
DC /
VDD12_AF
E /
VADC_AFE
_BANDGAP
?
U4
W4
V5
37
—
—
VDDA33_A Analog
—
—
—
—
—
—
—
—
—
DC /
VDD12_AF
E /
VADC_AFE
_BANDGAP
?
VDDA33_A Analog
DC /
VDD12_AF
E /
VADC_AFE
_BANDGAP
?
VDDA33_A Analog
DC /
VDD12_AF
E /
VADC_AFE
_BANDGAP
?
XTAL
W13
W12
72
71
DECAP_V1 Analog
—
—
XTAL
—
—
—
—
1_
LDO_OUT
XTAL32
DECAP_V1 Analog
XTAL32
1_
LDO_OUT
VF3xxR, VF5xxR, Rev. 8, 01/2018
120
NXP Semiconductors
Revision History
15 Revision History
The following table provides a revision history for this document.
Table 82. Revision History
Rev.
No.
Date
Substantial Changes
Rev 1
Rev 2
12/2011 Initial release
2/2012
Updated feature list
Updated VREG electrical specifications
Updated LDO_1P1, LDO2P5 tables
Updated DDR IO parameters
Added DDR memory controller parameters
Updated Power sequencing table
Added Power supply diagram
Updated Recommended operating conditions
Replaced DryIce Tamper Electrical Specifications with Voltage and temperature monitor electrical
specifications
Updated VideoADC electricals. Updated VideoADC supply scheme diagram. Added VideoADC
supply_decoupling diagram
Added QuadSPI DDR mode electrical specifications
Updated Fast internal RC oscillator table
Updated Slow internal RC oscillator table
Updated Pinouts section
Rev 3
4/2012
Updated device name throughout the document
Minor editorial updates in the feature list
Updated VREG electrical specifications
Updated LDO electrical specifications
Updated Power consumption operating behaviors table
Added USB PHY Current Consumption table
Updated GPIO parameters
Updated DDR parameters
Updated Power sequencing
Updated Power supply figure
Updated Recommended operating conditions table
Removed Reset specifications
Updated 12-bit DAC operating requirements
Added a note in 12-bit ADC operating conditions section
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
121
Revision History
Table 82. Revision History (continued)
Rev.
No.
Date
Substantial Changes
Updated VideoADC Specifications table
Updated LCD driver specifications table
QuadSPI timing- Replaced VDDE with VDD33
Added notes in DDR3 Timing Parameters and LPDD2 Timing Parameters sections.
Updated 24MHz external oscillator electrical characteristics table
Updated OSC32K Main Characteristics table
Updated Document Number for 144-pin LQFP
Changed pin-name from EXT_POR to TEST2, VBAT to VBB
Updated Pinouts section
Updated GPIO Mapping
Rev 4
8/2012
Updated Part identification
Editorial changes in USB PHY Current Consumption in Normal Mode, GPIO AC Electrical
Characteristics (3.3V power mode)
Updated Power sequencing table
Updated Power supply diagram
Updated AC electrical specification of following modules: DCU, 12-bit DAC, Ethernet, Enhanced Serial
Audio Interface (ESAI), SAI/I2S, Flexbus, MLB, DSPI, 24MHz External Oscillator, JTAG, Debug, ESAI,
QSPI
Updated Thermal Attributes for 364 MAPBGA
Updated document number for 176-pin LQFP and 364 MAPBGA
Updated VREG specifications
Added WBREG specifications
Updated Recommended operating conditions table
Updated DAC INL and DNL charts
Updated Pinouts
Rev 5
4/2013
• Removed references to VF1xxR and refernces to F100 and 144 LQFP and 256 MAPBGA
• Replaced references to Auto and IMM by R-series and F-series respectively
• In the feature list, the ARM Core frequency changed to 500 MHz for F-series
• In the feature list, changed the DRAM controller frequency
• Updated Part Nummbering format
• Clarified the Fields table as per Marketing
• Sample numbers updated
• From the VREG electrical specifications tables, deleted pre-trimming rows and comments
• .In the HPREG electrical characteristics table, add footnote on maximum Output Current Capacity
• In the ULPREG electrical characteristics table, clarified max value of Output voltage @ no load
and min value of Output voltage @ full load
• In the WBREG electrical characteristics table, clarified max value of Output voltage @ no load and
min value of Output voltage @ full load
• In the LVD electrical specifications table, added typ. values of Upper voltage threshold (value
@27oC) and Lower voltage threshold (value @27oC)
• In the LVD DIG electrical specifications table, removed pretrimming values and clarified other
values
• Updated LVD DIG electrical specifications values
• Updated LDO_1P1 tables
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
122
NXP Semiconductors
Revision History
Table 82. Revision History (continued)
Rev.
No.
Date
Substantial Changes
• Updated LDO_2P5 table
• Updated Power consumption operating behaviors tables
• Updated Absolute maximum ratings table
• Removed Temperature Voltage Monitor section to security RM
• Updated VideoADC Specifications table
Rev 6
1/2014
• Added QuadSPI electricals
• Changed VBB references to VBAT
• In the feature list, clarified that ECC supported for 8-bit mode only, not 16-bit.
• Revised the part number format
• Revised the field table
• Added Absolute Maximum Rating table, which was madde non_cust in the previous version
• In the Power Consumption Operating Behavior table, Revised min and max value of IDD_LPS3
and IDD_LPS2. Removed IDD_LPS1 row
• In the USB PHY Current Consumption table, removed the Normal Mode
• In the Power Sequence table, revised the Power UP/ Down Order column for USB0_VBUs and
USB1_VBUS
• In the Recommended operating conditions table, revised the min value of VBAT. Revised the min
value of VREFH_ADC Revised the min and max values of SDRAMC_VDD1P5
• In the Recommended Connections for Unused Analog Interfaces section, added the notes.
Revised the Recommendation if Unused column
• In the 12-bit ADC operating conditions, revised Conditions for Ground voltage. Revised min Ref
High Voltage
• In the 12-bit DAC operating requirements, revised the min and max value of VREFH_ADC
• In the SDHC switching specifications, revised the max value of SD6
• In the 24MHz external oscillator electrical characteristics table, revised the min value of VIH and
max value of VIL
Rev 7
11/2014
• Updated list of security features on page 1.
• In "Part number format" figure, updated explanation for '1'.
• In "Fields" table, updated definition of 'R'.
• In "Part Numbers" table, added parts SVF331R3K1CKU2, SVF531R3K1CMK4, and
SVF532R2K1CMK4.
• In "External NPN ballast" section, updated recommendations for transistor selection.
• In "DDR parameters" section, updated table footnotes regarding typical condition.
• In "Power sequencing" table, added comment regarding SDRAMC_VDD1P5: "In case the Ballast
transistor’s collector is connected to the 1.5 V DRAM supply (instead of the 3.3 V supply), turn this
1.5 V supply on before turning on the 3.3V."
• In "VideoADC specifications" table, added supply current values.
• In "Receive and Transmit signal timing specifications," added the following note: "See the most
current errata document when using the internally generated RXCLK and TXCLK clocks."
• Updated "QuadSPI timing" section, presenting data based on a negative edge data launch from
the device and a negative edge data capture; updated the figure, "QuadSPI Input/Read timing
(SDR mode)"; updated the table, "QuadSPI Input/Read timing (SDR mode)."
• For the "SDHC switching specifcations" table, added the statement, "A load of 50 pF is assumed";
updated max value for SD6, SDHC output delay (output valid).
• In the "24 MHz oscillator specifications" section, added the statement, "The crystal must be rated
for a drive level of 250 μW or higher. An ESR (equivalent series resistance) of 80 Ω or less is
recommended to achieve a gain margin of 5."
• In "Pinouts" section, for the 176LQFP package, added information about exposed pad on the
bottom side.
• In "Special Signal Considerations" table, added that a "fundamental-mode" crystal should be
connected between XTAL and EXTAL; updated maximum drive level of crystal rating to 250 μW.
Rev 8
01/2018
• Throughout: Updated references to company website
• In the "Part number format" figure, updated the "Option" box with mask options
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
123
Revision History
Table 82. Revision History
Rev.
No.
Date
Substantial Changes
• Deleted the "Fields" section
• Updated part numbers in "Part numbers" section
• In "Power consumption operating behaviors" section, updated descriptions and footnotes for
IDD_LPS3 and IDD_LPS2
• In "Absolute maximum ratings" table, added rows for USB0_DP, USB0_DN, USB1_DP, and
USB1_DN
• In the table, "12-bit ADC characteristics (VREFH = VDDAD, VREFL = VSSAD)":
• Changed mentions of "Temp Sensor" to "Temperature Sensor"
• Added footnotes 2 and 3
• In the table, "12-bit DAC operating behaviors," in footnote 5, changed "VDDA = 3.0 V" to "VDDA
3.3 V"
=
• In "Video Input Unit timing" section, added clocking requirements after introduction
• Updated "QuadSPI timing" section
• For "NFC specifications" section:
• Changed title to "NAND flash controller specifications"
• In the note, specified that the reader should see the CCM section of the product reference
manual for more information
• Changed title of the figure "Read data latch cycle timing in non-fast mode" to "Read data
latch cycle timing in Slow mode"
• Changed title of the figure "Read data latch cycle timing in fast mode" to "Read data latch
cycle timing in Fast mode and EDO mode"
• In the table footnotes in the "I2C timing" section, updated the frequency of the PER_CLK, from 83
MHz to 66 MHz
• In the "Pinouts" table, for L5, changed RMII0_MDIO/MII0_MDC to RMII0_MDIO/ MII0_MDIO
VF3xxR, VF5xxR, Rev. 8, 01/2018
124
NXP Semiconductors
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
NXP, the NXP logo, I2C BUS, Freescale, the Freescale logo, and Vybrid are
trademarks of NXP B.V. All other product or service names are the property of
their respective owners. Arm, Cortex, and TrustZone are registered trademarks
of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. NEON is a
trademark of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All
rights reserved.
© 2012-2013, 2017 NXP B.V.
Document Number VYBRIDRSERIESEC
Revision 8, 01/2018
相关型号:
©2020 ICPDF网 联系我们和版权申明