SSTUH32865_技术文档

SSTUH32865

1.8 V 28-bit high output drive 1:2 registered buffer with parity

for DDR2 RDIMM applications

Rev. 01 — 11 March 2005

Product data sheet

1. General description

The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register speciﬁcally designed for

use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2)

memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but

integrates the functionality of the normally required two registers in a single package,

thereby freeing up board real-estate and facilitating routing to accommodate high-density

Dual In-line Memory Module (DIMM) designs.

The SSTUH32865 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

The SSTUH32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which—while requiring a minimum

9 mm × 13 mm of board space—allows for adequate signal routing and escape using

conventional card technology.

The SSTUH32865 is identical to SSTU32865 in function and performance, with

higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while

maintaining speed and signal integrity.

2. Features

■ 28-bit data register supporting DDR2

■ Higher output drive strength version of SSTU32865 optimized for high-capacitive load

nets

■ Fully compliant to JEDEC standard JESD82-9

■ Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2 × SSTU32864 or 2 × SSTU32866)

■ Parity checking function across 22 input data bits

■ Parity out signal

■ Controlled output impedance drivers enable optimal signal integrity and speed

■ Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation

delay, 2.0 ns max. mass-switching)

■ Supports up to 450 MHz clock frequency of operation

■ Optimized pinout for high-density DDR2 module design

■ Chip-selects minimize power consumption by gating data outputs from changing state

■ Supports Stub Series Terminated Logic SSTL_18 data inputs

■ Differential clock (CK and CK) inputs

SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

■ Supports Low Voltage Complementary Metal Oxide Silicon (LVCMOS) switching levels

on the control and RESET inputs

■ Single 1.8 V supply operation

■ Available in 160-ball 9 mm × 13 mm, 0.65 mm ball pitch TFBGA package

3. Applications

■ High-density (for example, 2 rank by 4) DDR2 registered DIMMs

■ DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality

■ Stacked or planar high-DRAM count registered DIMMs

4. Ordering information

Table 1:

Ordering information

Solder process

Type number

Package

Name

Description

Version

SSTUH32865ET/G Pb-free (SnAgCu solder ball TFBGA160 plastic thin ﬁne-pitch ball grid array package; SOT802-1

compound) 160 balls; body 9 × 13 × 0.8 mm

SSTUH32865ET

SnPb solder ball compound TFBGA160 plastic thin ﬁne-pitch ball grid array package; SOT802-1

160 balls; body 9 × 13 × 0.8 mm

9397 750 14136

Product data sheet

Rev. 01 — 11 March 2005

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

5. Functional diagram

(CS ACTIVE)

VREF

SSTUH32865

PARITY

D

Q

GENERATOR

AND

CHECKER

PARIN

22

PTYERR

R

Q0A

Q0B

D

R

D0

Q21A

Q21B

D

R

D21

QCS0A

QCS0B

DCS0

D

R

CSGATEEN

DCS1

QCS1A

QCS1B

D

R

QCKE0A,

QCKE1A

DCKE0,

2

DCKE1

2

D

R

QCKE0B,

QCKE1B

QODT0A,

QODT1A

DODT0,

2

DODT1

D

R

QODT0B,

QODT1B

RESET

002aab111

CK

Fig 1. Functional diagram of SSTUH32865

9397 750 14136

Product data sheet

Rev. 01 — 11 March 2005

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

6. Pinning information

6.1 Pinning

SSTUH32865ET/G

SSTUH32865ET

ball A1

index area

2

4

6

8

10 12

9 11

1

3

5

7

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

002aab112

Transparent top view

Fig 2. Pin conﬁguration for TFBGA160

9397 750 14136

Product data sheet

Rev. 01 — 11 March 2005

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

1

VREF

D1

2

n.c.

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

PARIN

n.c.

QCKE1A QCKE0A

QCKE1B QCKE0B

Q21A

Q21B

Q19A

Q19B

Q18A

Q18B

Q17B

Q17A

D2

QODT0B QODT0A

QODT1B QODT1A

D3

D4

D6

D5

VDDL

GND

VDDL

GND

VDDL

n.c.

GND

Q20B

Q16B

Q1B

Q20A

Q16A

Q1A

D7

D8

VDDL

VDDR

D11

D9

VDDR

GND

VDDR

GND

D18

D12

D15

DCS0

DCS1

D14

D10

D16

D21

D20

DODT0

DCKE1

m.c.l.

Q2B

Q2A

G

H

J

CSGATEEN

CK

Q5B

Q5A

VDDR

GND

VDDR

GND

QCS0B

QCS1B

Q6B

QCS0A

QCS1A

Q6A

CK

VDDL

GND

K

L

RESET

D0

VDDR

GND

VDDR

GND

Q10B

Q9B

Q10A

Q9A

M

N

P

R

T

D17

VDDL

GND

VDDR

GND

VDDR

GND

D19

VDDL

VDDR

GND

Q11B

Q15B

Q14B

Q0B

Q11A

Q15A

Q14A

Q8B

D13

GND

DODT1

DCKE0

VREF

m.c.l.

PTYERR

n.c.

m.c.h.

Q3B

Q3A

Q12B

Q12A

Q7B

Q7A

Q4B

Q4A

Q13B

Q13A

U

V

Q0A

Q8A

002aab011

160-ball, 12 × 18 grid; top view.

An empty cell indicates no ball is populated at that grid point.

n.c. denotes a no-connect (ball present but not connected to the die).

m.c.l. denotes a pin that must be connected LOW.

m.c.h. denotes a pin that must be connected HIGH.

Fig 3. Ball mapping

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

6.2 Pin description

Table 2:

Pin description

Symbol

Type

Description

Ungated inputs

DCKE0, DCKE1

DODT0, DODT1

U1, U2

T2, T1

SSTL_18

DRAM function pins not associated with Chip Select.

Chip Select gated inputs

D0 to D21

M1, B1, B2, C1, C2, D2, D1, SSTL_18

E1, E2, F2, M2, F1, G2, R1,

L2, H2, N2, N1, G1, P1, R2,

P2

DRAM inputs, re-driven only when Chip Select is LOW.

Chip Select inputs

DCS0, DCS1

J2, K2

SSTL_18

DRAM Chip Select signals. These pins initiate DRAM

address/command decodes, and as such at least one will

be LOW when a valid address/command is present. The

register can be programmed to re-drive all D-inputs only

(CSGATEEN = HIGH) when at least one Chip Select

input is LOW.

Re-driven outputs

Q0A to Q21A

V11, F12, G12, V6, V9, H12, SSTL_18

L12, V8, V12, N12, M12,

P12, V7, V10, T12, R12,

Outputs of the register, valid after the speciﬁed clock

count and immediately following a rising edge of the

clock.

E12, A12, A10, A9, D12, A8

Q0B to Q21B

U11, F11, G11, U6, U9,

H11, L11, U8, U12, N11,

M11, P11, U7, U10, T11,

R11, E11, A11, B10, B9,

D11, B8

QCS0A, QDS1A,

QCS0B, QCS1B

J12, K12, J11, K11

QCKE0A, QCKE1A, A7, A6, B7, B6

QCKE0B, QCKE1B

QODT0A, QODT1A, B12, C12, B11, C11

QODT0B, QODT1B

Parity input

PARIN

A3

U4

SSTL_18

Parity input for the D0 to D21 inputs. Arrives one clock

cycle after the corresponding data input.

Parity error

PTYERR

open drain When LOW, this output indicates that a parity error was

identiﬁed associated with the address and/or command

inputs. PTYERR will be active for two clock cycles, and

delayed by an additional clock cycle for compatibility with

ﬁnal parity out timing on the industry-standard DDR2

register with parity (in JEDEC deﬁnition).

Program inputs

CSGATEEN

H1

1.8 V

LVCMOS

Chip Select Gate Enable. When HIGH, the D0 to D21

inputs will be latched only when at least one Chip Select

input is LOW during the rising edge of the clock. When

LOW, the D0 to D21 inputs will be latched and redriven

on every rising edge of the clock.

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

Table 2:

Symbol

Pin description …continued

Type

Description

Clock inputs

CK, CK

J1, K1

SSTL_18

Differential master clock input pair to the register. The

register operation is triggered by a rising edge on the

positive clock input (CK).

Miscellaneous inputs

m.c.l.

U3, V2, V3

U5, V5

L1

Must be connected to a logic LOW

Must be connected to a logic HIGH.

m.c.h.

RESET

1.8 V

LVCMOS

Asynchronous reset input. When LOW, it causes a reset

of the internal latches, thereby forcing the outputs LOW.

RESET also resets the PTYERR signal.

VREF

VDDL

VDDR

GND

A1, V1

0.9 V

nominal

Input reference voltage for the SSTL_18 inputs. Two pins

(internally tied together) are used for increased reliability.

D4, E4, E6, F4, G4, H4, K4,

K5, N4, N5, P5, P6, R5, R6

power supply voltage

ground

E7, F8, F9, G8, G9, J8, J9,

L8, L9, N8, N9, P7, P8

D5, D8, D9, E5, E8, E9, F5,

G5, H5, H8, H9, J4, J5, K8,

K9, L4, L5, M4, M5, M8, M9,

P4, P9, R4, R7, R8, R9

n.c.

A2, A4, A5, B3, B4, B5, D6,

D7, V4

ball present but not connected to die

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

7. Functional description

7.1 Function table

Table 3:

RESET

Function table (each ﬂip-ﬂop)

Inputs

Outputs^[1]

DCS0

DCS1

CSGATEEN

CK

Dn, DODTn,

DCKEn

Qn

QCS0 QCS1 QODTn,

QCKEn

H

L

X

↑

↓

L

H

L

H

X

↑

↓

H

L

X

L or H

X

Q₀

L

Q₀

L

Q₀

H

Q₀

L

H

L

X

↑

↓

L

X

↑

↓

H

L

H

L

X

L or H

X

Q₀

L

Q₀

H

Q₀

L

Q₀

L

H

X

↑

↓

L

X

↑

↓

H

L

H

L

X

L or H

X

Q₀

L

Q₀

H

Q₀

H

Q₀

L

H

L

↑

↓

L

↑

L or H

↑

↓

L or H

↓

H

L

X

Q₀

L

Q₀

H

Q₀

H

Q₀

L

H

L

H

↑

↓

H

X

H

L or H

Q₀

L

Q₀

L

Q₀

L

X or

X or ﬂoating

X or

X or ﬂoating

ﬂoating

[1] Q₀is the previous state of the associated output.

Table 4:

RESET

Parity and standby function table

Inputs

Output

PTYERR^{[2] [3]}

DCS0

DCS1

CK

∑ of inputs = H

PARIN^[1]

(D0 to D21)

H

L

H

L

↑

↓

even

odd

L

H

↑

↓

L

↑

↓

even

odd

H

L

↑

↓

H

X

↑

↓

even

odd

L

H

L

↑

↓

L

↑

↓

even

odd

H

L

↑

↓

H

X

PTYERR₀

H

L or H

X

X or ﬂoating X or ﬂoating X or ﬂoating X or ﬂoating

X or ﬂoating

[1] PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated

correctly.

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

[2] This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched

LOW for two clock cycles or until RESET is driven LOW.

CSGATEEN is ‘don’t care’ for PTYERR.

[3] PTYERR₀is the previous state of output PTYERR.

7.2 Functional information

This 28-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V V_DDoperation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTUH32865 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and undriven (ﬂoating) data, clock and

reference voltage (V_REF) inputs are allowed. In addition, when RESET is LOW all registers

are reset, and all outputs except PTYERR are forced LOW. The LVCMOS RESET input

must always be held at a valid logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUH32865 ensures that the outputs remain LOW, thus

ensuring no glitches on the output.

The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from

changing states when both DCS0 and DCS1 are HIGH. If either DCS0 or DCS1 input is

LOW, the Qn outputs will function normally. The RESET input has priority over the DCS0

and DCS1 control and will force the Qn outputs LOW and the PTYERR output HIGH. If the

DCSn-control functionality is not desired, then the CSGATEEN input can be hardwired to

ground, in which case, the setup-time requirement for DCSn would be the same as for the

other Dn data inputs.

The SSTUH32865 includes a parity checking function. The SSTUH32865 accepts a parity

bit from the memory controller at its input pin PARIN, compares it with the data received

on the Dn inputs (with either DCS0 or DCS1 active) and indicates whether a parity error

has occurred on its open-drain PTYERR pin (active LOW).

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

7.3 Functional differences to SSTU32864

The SSTUH32865 for its basic register functionality, signal deﬁnition and performance is

based upon the industry-standard SSTU32864, but provides key operational features

which differ (at least in part) from the industry-standard register in the following aspects:

7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN)

As a means to reduce device power, the internal latches will only be updated when one or

both of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the

clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include

addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining

signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they

are independent of CS. The CS gating function can be disabled by tying CSGATEEN

LOW, enabling all internal latches to be updated on every rising edge of the clock.

Table 5:

Mode

Chip Select gating mode

Signal name

CSGATEEN

HIGH

Description

Gating

Registers only re-drive signals to the DRAMs when

Chip Select inputs are LOW.

Non-gating

CSGATEEN

LOW

Registers always re-drive signals on every clock cycle,

independent of the state of the Chip Select inputs.

7.3.2 Parity error checking and reporting

The SSTUH32865 incorporates a parity function, whereby the signal received on input pin

PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs.

The received parity bit is then compared to the parity calculated across these same inputs

by the register parity logic to verify that the information has not been corrupted. The 22

CS-gated input signals will be latched and re-driven on the ﬁrst clock, and any error will be

reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive

clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a

common signal pin for reporting the occurrence of a parity error during a valid command

cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive

clock cycles to allow the memory controller sufﬁcient time to sense and capture the error

even. A LOW state on PTYERR indicates that a parity error has occurred.

7.3.3 Reset (RESET)

Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all

internal latches and all outputs will be driven LOW quickly except the PTYERR output,

which will be ﬂoated (and will normally default HIGH by their external pull-up).

7.3.4 Power-up sequence

The reset function for the SSTUH32865 is similar to that of the SSTU32864 except that

the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive

clock cycles.

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

RESET

DCSn

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

ACT

t

h

su

(1)

Dn

t

, t

PDM PDMSS

CK to Q

Qn

t

h

su

PARIN

t

, t

PHL PLH

PHL

CK to PTYERR

PTYERR

002aaa983

HIGH, LOW, or Don't care

HIGH or LOW

(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum

time of t_ACT(max)to avoid false error.

Fig 4. RESET switches from LOW to HIGH

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

RESET

DCSn

CK

m

m + 1

m + 2

m + 3

m + 4

CK

t

h

su

(1)

Dn

t

, t

PDM PDMSS

CK to Q

Qn

t

su

t

h

PARIN

t

, t

PHL PLH

CK to PTYERR

PTYERR

002aaa984

Output signal is dependent

on the prior unknown event

Unknown input event

HIGH or LOW

Fig 5. RESET being held HIGH

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

RESET

DCSn

t

INACT

(1)

CK

(1)

CK

(1)

Dn

t

RPHL

RESET to Q

Qn

(1)

PARIN

t

RPLH

RESET to PTYERR

PTYERR

002aaa985

HIGH, LOW, or Don't care

HIGH or LOW

(1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not

ﬂoating) for a minimum time of t_INACT(max)

.

Fig 6. RESET switches from HIGH to LOW

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Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

22

Dn

QnA

QnB

D

Q

D

PTYERR

D

LATCHING AND

RESET FUNCTION

(1)

PARIN

CLOCK

002aaa417

(1) This function holds the error for two cycles. For details, see Section 7 “Functional description” and Figure 4 “RESET

switches from LOW to HIGH”.

Fig 7. Parity logic diagram

9397 750 14136

Product data sheet

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SSTUH32865

Philips Semiconductors

1.8 V high output drive DDR registered buffer with parity

8. Limiting values

Table 6:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I

Parameter

Conditions

Min

Max

Unit

V

supply voltage

−0.5

+2.5

[2]

receiver input voltage

driver output voltage

input clamp current

output clamp current

continuous output current

−0.5

+2.5

V

V_O

−0.5

V_DD+ 0.5

−50

V

I_IK

V_I< 0 V or V_I> V_DD

V_O< 0 V or V_O> V_DD

0 V < V_O< V_DD

-

mA

I_OK

±50

I_O

±50

I_CCC

continuous current through

each V_DDor GND pin

±100

T_stg

storage temperature

−65

+150

-

°C

V_esd

electrostatic discharge

voltage

Human Body Model (HBM); 1.5 kΩ;

100 pF

2

kV

Machine Model (MM); 0 Ω; 200 pF

200

-

V

[1] Stresses beyond those listed under ‘absolute maximum ratings’ may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under ‘recommended operating

conditions’ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

[2] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

9. Recommended operating conditions

Table 7:

Symbol

V_DD

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max

Unit

V

supply voltage

1.7

-

1.9

V_REF

V_TT

reference voltage

0.49 × V_DD

0.50 × V_DD0.51 × V_DD

V

termination voltage

V_REF− 40 mV

V_REF

V_REF+ 40 mV

V

V_I

input voltage

0

-

V_DD

-

V

[1]

[2]

V_IH(AC)

V_IL(AC)

V_IH(DC)

V_IL(DC)

V_IH

AC HIGH-level input voltage

AC LOW-level input voltage

DC HIGH-level input voltage

DC LOW-level input voltage

HIGH-level input voltage

LOW-level input voltage

data inputs (Dn)

RESET

V_REF+ 250 mV

V

-

V_REF− 250 mV

V

V_REF+ 125 mV

-

V

-

V_REF− 125 mV

-

V

0.65 × V_DD

V

V_IL

RESET

-

0.35 × V_DD

V

V_ICR

common mode input voltage

range

CK, CK

0.675

1.125

V

V_ID

I_OH

I_OL

differential input voltage

HIGH-level output current

LOW-level output current

CK, CK

600

-

mV

mA

°C

-

−12

12

+70

-

T_amb

operating ambient temperature

in free air

0

[1] The differential inputs must not be ﬂoating, unless RESET is LOW.

[2] The RESET input of the device must be held at valid logic levels (not ﬂoating) to ensure proper device operation.

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1.8 V high output drive DDR registered buffer with parity

10. Characteristics

Table 8:

Characteristics

Over recommended operating conditions, unless otherwise noted.

Symbol

V_OH

V_OL

Parameter

Conditions

Min

Typ

Max

-

Unit

V

HIGH-level output voltage

LOW-level output voltage

input current

I_OH= −12 mA; V_DD= 1.7 V

I_OL= 12 mA; V_DD= 1.7 V

all inputs; V_I= V_DDor GND;

1.2

-

0.5

±5

V

I_I

µA

V_DD= 1.9 V

I_DD

static standby current

static operating current

RESET = GND; V_DD= 1.9 V

-

100

40

µA

RESET = V_DD; V_DD= 1.9 V;

V_I= V_IH(AC)or V_IL(AC)

mA

I_DDD

dynamic operating current per MHz, RESET = V_DD

;

-

16

-

µA

clock only

V_I= V_IH(AC)or V_IL(AC); CK and CK

switching at 50 % duty cycle.

I_O= 0 mA; V_DD= 1.8 V

dynamic operating current per MHz, RESET = V_DD

;

-

19

-

per each data input

V_I= V_IH(AC)or V_IL(AC); CK and CK

switching at 50 % duty cycle. One

data input switching at half clock

frequency, 50 % duty cycle.

I_O= 0 mA; V_DD= 1.8 V

C_i

input capacitance, data inputs

input capacitance, CK and CK

V_I= V_REF± 250 mV; V_DD= 1.8 V

2.5

2

-

3.5

3

pF

V_ICR= 0.9 V; V_ID= 600 mV;

V_DD= 1.8 V

input capacitance, RESET

V_I= V_DDor GND; V_DD= 1.8 V

3

-

5

pF

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1.8 V high output drive DDR registered buffer with parity

Table 9:

Timing requirements

Over recommended operating conditions, unless otherwise noted.

Symbol

f_clock

Parameter

Conditions

Min

Typ

Max

450

-

Unit

MHz

ns

clock frequency

-

t_W

pulse duration, CK, CK HIGH or

LOW

1

[1] [2]

[1] [3]

t_ACT

t_INACT

t_su

differential inputs active time

differential inputs inactive time

setup time, Chip Select

-

10

15

-

ns

-

DCS0, DCS1 valid before

clock switching

0.7

setup time, Data

Dn valid before clock

switching

0.5

-

ns

setup time, PARIN

hold time

PARIN before CK and CK

0.5

-

ns

t_h

input to remain valid after

clock switching

hold time, PARIN

PARIN after CK and CK

0.5

-

ns

[1] This parameter is not necessarily production tested.

[2] Data inputs must be active below a minimum time of t_ACT(max)after RESET is taken HIGH.

[3] Data and clock inputs must be held at valid levels (not ﬂoating) a minimum time of t_INACT(max)after RESET is taken LOW.

Table 10: Switching characteristics

Over recommended operating conditions, unless otherwise noted.

Symbol

f_MAX

t_PDM

t_LH

Parameter

Conditions

Min

450

1.41

1.2

1

Typ

Max

-

Unit

MHz

ns

maximum input clock frequency

propagation delay

-

[1]

CK and CK to output

CK and CK to PTYERR

from RESET to PTYERR

CK and CK to output

1.8

3

LOW-to-HIGH delay

ns

t_HL

HIGH-to-LOW delay

3

ns

t_PLH

LOW-to-HIGH propagation delay

-

3

ns

[1] [2]

t_PDMSS

propagation delay, simultaneous

switching

-

2.0

ns

t_PHL

propagation delay

RESET to output

-

3

ns

[1] Includes 350 ps of test-load transmission line delay.

[2] This parameter is not necessarily production tested.

Table 11: Output edge rates

Over recommended operating conditions, unless otherwise noted.

Symbol

dV/dt_r

dV/dt_f

dV/dt_∆

Parameter

Conditions

Min

Typ

Max

Unit

V/ns

rising edge slew rate

falling edge slew rate

1

-

4

1

absolute difference between dV/dt_r

and dV/dt_f

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1.8 V high output drive DDR registered buffer with parity

11. Test information

11.1 Test circuit

All input pulses are supplied by generators having the following characteristics: Pulse

Repetition Rate (PRR) ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless

otherwise speciﬁed.

The outputs are measured one at a time with one transition per measurement.

V

DD

DUT

R

= 1000 Ω

L

T

= 50 Ω

T

= 350 ps, 50 Ω

L

CK

CK inputs

OUT

(1)

= 45 pF

C

L

R

L

test point

R

L

= 100 Ω

002aab113

test point

(1) C_Lincludes probe and jig capacitance.

Fig 8. Load circuit

LVCMOS

V

DD

RESET

V

/2

DD

V

/2

DD

0 V

t

ACT

INACT

90 %

(1)

DD

I

10 %

002aaa372

(1) I_DDtested with clock and data inputs held at V_DDor GND, and I_O= 0 mA.

Fig 9. Voltage and current waveforms; inputs active and inactive times

t

W

V

IH

IL

V

input

V

ICR

ID

ICR

002aaa373

V_ID= 600 mV

V_IH= V_REF+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_REF− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 10. Voltage waveforms; pulse duration

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1.8 V high output drive DDR registered buffer with parity

CK

V

ICR

ID

CK

t

h

su

V

IH

IL

input

V

REF

V

REF

002aaa374

V_ID= 600 mV

V_REF= V_DD/2

V_IH= V_REF+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_REF− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 11. Voltage waveforms; setup and hold times

CK

V

ICR

i(p-p)

CK

t

PHL

PLH

V

OH

OL

V

output

TT

002aaa375

t_PLHand t_PHLare the same as t_PD

.

Fig 12. Voltage waveforms; propagation delay times (clock to output)

LVCMOS

V

IH

RESET

V

/2

DD

IL

t

PHL

OH

OL

output

V

TT

002aaa376

t_PLHand t_PHLare the same as t_PD

.

V_IH= V_REF+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_REF− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 13. Voltage waveforms; propagation delay times (reset to output)

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11.2 Output slew rate measurement

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 50 Ω

L

OUT

test point

002aab117

(1)

= 15 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 14. Load circuit, HIGH-to-LOW slew measurement

output

V

OH

80 %

dv_f

20 %

V

OL

dt_f

002aaa378

Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement

DUT

OUT

test point

(1)

= 15 pF

C

L

R

L

= 50 Ω

002aab118

(1) C_Lincludes probe and jig capacitance.

Fig 16. Load circuit, LOW-to-HIGH slew measurement

dt_r

V

OH

80 %

dv_r

20 %

output

OL

002aaa380

Fig 17. Voltage waveforms, LOW-to-HIGH slew rate measurement

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1.8 V high output drive DDR registered buffer with parity

11.3 Error output load circuit and voltage measurement

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 1 kΩ

L

OUT

test point

002aaa500

(1)

= 10 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 18. Load circuit, error output measurements

LVCMOS

V

CC

RESET

V

/2

CC

0 V

t

PLH

V

OH

0.15 V

output

waveform 2

0 V

002aaa501

Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

RESET input

timing

inputs

V

i(p-p)

V

ICR

t

HL

V

CC

OL

output

waveform 1

V

/2

CC

002aaa502

Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect

to clock inputs

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1.8 V high output drive DDR registered buffer with parity

timing

inputs

V

i(p-p)

V

ICR

t

LH

V

OH

output

waveform 2

0.15 V

0 V

002aaa503

Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

clock inputs

9397 750 14136

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1.8 V high output drive DDR registered buffer with parity

12. Package outline

TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.8 mm

SOT802-1

D

B

A

ball A1

index area

A

2

E

1

A

detail X

C

e

1

v M

w M

C

A

B

e

b

y

C

1

1/2e

V

U

T

P

R

N

e

M

K

H

L

J

e

2

1/2e

G

E

C

A

F

D

B

ball A1

index area

1

3

5

7

9

11

2

4

6

8

10

12

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

D

E

e

v

w

y

1

2

1

2

max.

0.35 0.85 0.45

0.25 0.75 0.35

9.1

8.9

13.1

12.9

mm

1.2

0.65 7.15 11.05 0.15 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

03-01-29

SOT802-1

- - -

Fig 22. Package outline SOT802-1 (TFBGA160)

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1.8 V high output drive DDR registered buffer with parity

13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

13.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

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1.8 V high output drive DDR registered buffer with parity

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

13.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

13.5 Package related soldering information

Table 12: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

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1.8 V high output drive DDR registered buffer with parity

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

14. Revision history

Table 13: Revision history

Document ID

Release date Data sheet status

20050311 Product data sheet

Change notice Doc. number

9397 750 14136

Supersedes

SSTUH32865_1

-

9397 750 14136

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1.8 V high output drive DDR registered buffer with parity

15. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Deﬁnitions

17. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14136

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1.8 V high output drive DDR registered buffer with parity

19. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

Functional description . . . . . . . . . . . . . . . . . . . 8

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional information . . . . . . . . . . . . . . . . . . . 9

Functional differences to SSTU32864 . . . . . . 10

Chip Select (CS) gating of key inputs (DCS0,

DCS1, CSGATEEN) . . . . . . . . . . . . . . . . . . . . 10

Parity error checking and reporting. . . . . . . . . 10

Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . 10

Power-up sequence . . . . . . . . . . . . . . . . . . . . 10

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.3.4

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15

Recommended operating conditions. . . . . . . 15

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 16

9

10

11

Test information. . . . . . . . . . . . . . . . . . . . . . . . 18

Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Output slew rate measurement. . . . . . . . . . . . 20

Error output load circuit and voltage

11.1

11.2

11.3

measurement . . . . . . . . . . . . . . . . . . . . . . . . . 21

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

13

13.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 24

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25

Package related soldering information . . . . . . 25

13.2

13.3

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Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 27

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Contact information . . . . . . . . . . . . . . . . . . . . 27

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 11 March 2005

Document number: 9397 750 14136

Published in The Netherlands


型号：	SSTUH32865
厂家：	NXP
描述：	1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applications 1.8 V 28位高输出驱动1 ：带奇偶校验的DDR2 RDIMM应用2寄存缓冲器驱动双倍数据速率
文件：	总28页 (文件大小：143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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