SL3S4011FHK [NXP]
UCODE I2C;型号: | SL3S4011FHK |
厂家: | NXP |
描述: | UCODE I2C |
文件: | 总30页 (文件大小:314K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SL3S4011_4021
UCODE I²C
Rev. 3.5 — 18 September 2018
204935
Product data sheet
COMPANY PUBLIC
1 General description
The UHF EPCglobal Generation-2 standard allows the commercialized provision of
mass adoption of UHF RFID technology for passive smart tags and labels. Main fields
of applications are supply chain management and logistics for worldwide use with
special consideration of European, US and Chinese frequencies to ensure that operating
distances of several meters can be realized.
The NXP Semiconductors UCODE product family is compliant to this EPC Gen2
standard offering anti-collision and collision arbitration functionality. This allows a reader
to simultaneously operate multiple labels/tags within its antenna field.
The UCODE-based label/ tag requires no external power supply for contactless
operation. Its contactless interface generates the power supply via the antenna circuit by
propagative energy transmission from the interrogator (reader), while the system clock is
generated by an on-chip oscillator. Data transmitted from the interrogator to the label/tag
is demodulated by the interface, and it also modulates the interrogator's electromagnetic
field for data transmission from the label/tag to the interrogator.
A label/tag can be then operated without the need for line of sight or battery, as long as it
is connected to a dedicated antenna for the targeted frequency range. When the label/tag
is within the interrogator's operating range, the high-speed wireless interface allows data
transmission in both directions.
With the UCODE I2C product, NXP Semiconductors introduces now the possibility to
combine 2 independent UHF Interfaces (following EPC Gen2 standard) with an I2C
interface. Its large memory can be then read or write via both interfaces.
This I2C functionality enables the standard EPC Gen2 functionalities to be linked to an
electronic device microprocessor. By linking the rich functionalities of the EPC Gen2
standards to the Electronics world, the UCODE I2C product opens a whole new range of
application.
The I2C interface needs to be supplied externally and supports standard and fast I2C
modes. Its large memory is based on a field proven non-volatile memory technology
commonly used in high-quality automotive applications.
2 Features and benefits
2.1 UHF interface
• Dual UHF antenna port
• -18 dBm READ sensitivity
• -11 dBm WRITE sensitivity
• -23 dBm READ and WRITE sensitivity with the chip powered
NXP Semiconductors
SL3S4011_4021
UCODE I²C
• Compliant to EPCglobal Radio-Frequency Identity Protocols Class-1 Generation-2 UHF
RFID Protocol for communications at 860 MHz to 960 MHz version 1.2.0
• Wide RF interface temperature range: -40 °C up to +85 °C
• Memory read protection
• Interrupt output
• RF - I2C bridge function based on SRAM memory
2.2 I2C interface
• Supports Standard (100 kHz) and Fast (400 kHz) mode (see Ref. 1)
• UCODE I2C can be used as standard I2C EEPROMs
2.3 Command set
• All mandatory EPC Gen2 v1.2.0 commands
• Optional commands: Access, Block Write (32 bit)
• Custom command: ChangeConfig
2.4 Memory
• 3328-bit user memory
• 160-bit EPC memory
• 96-bit tag identifier (TID) including 48-bit unique serial number
• 32-bit KILL password to permanently disable the tag
• 32-bit ACCESS password to allow a transition into the secured transmission state
• Encoding speed one word 5 ms
• Data retention: 20 years at 55 °C
• Write endurance: 100 kcycles at 85 °C
2.5 Package
• SOT-902-3; MO-255B footprint
• Outline 1.6 × 1.6 mm
• Thickness ≤ 0.5 mm
3 Applications
• Firmware downloads
• Return management
• Counterfeit protection and authentication
• Production information
• Theft protection and deterrence
• Production automation
• Device customization/product configuration
• Offline Diagnostics
There are known limitations for applications where both interfaces are powered. For
details refer to Ref. 6.
SL3S4011_4021
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Product data sheet
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UCODE I²C
4 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Name
Description
Version
SL3S4011FHK
SL3S4021FHK
XQFN8
Single differential RF Front End [1]- Plastic, extremely thin quad flat
package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm
SOT902-3
XQFN8
Dual differential RF Front End - Plastic, extremely thin quad flat
package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm
SOT902-3
[1] RFP1, RFN1
5 Marking
Table 2.ꢀMarking
Type Number
Marking code
1FE
SL3S4011FHK
SL3S4021FHK
2FE
6 Block diagram
RFP1
RFN1
DIFFERENTIAL
UHF FRONTEND 1
UHF antenna 1
ISO18000-6
DIGITAL
INTERFACE
VDDB
VDDB
GND
POWER
MANAGEMENT/
ANALOG
RFN2
RFP2
NON
VOLATILE
MEMORY
DIFFERENTIAL
UHF FRONTEND 2
UHF antenna 2
2
I C INTERFACE
2
I C DRIVER/SCL
SCL
INT SIGNALLING DRIVER
50 ns SPIKE INPUT FILTER
2
I C DRIVER/SDA
SDA
CE OUPUT DRIVER
50 ns SPIKE INPUT FILTER
001aao224
Figure 1.ꢀBlock diagram
SL3S4011_4021
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UCODE I²C
7 Pinning information
7.1 Pinning
A
GND
8
RF1P
1
7
6
5
RF2P
RF2N
SDA
A RF1N
SCL
2
3
4
VDD
Transparent top view
B
side view
001aao225
1. Dimension A: 1.6 mm
2. Dimension B: 0.5 mm
Figure 2.ꢀPin configuration
7.2 Pin description
Table 3.ꢀPin description
Pin
1
Symbol
RF1P
RF1N
SCL
Description
active antenna 1 connector
2
antenna 1
3
I2C clock / _INT
supply
4
VDD
5
SDA
I2C data
6
RF2N
RF2P
GND
antenna 2
7
active antenna 2 connector
ground
8
SL3S4011_4021
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NXP Semiconductors
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UCODE I²C
8 Mechanical specification
8.1 SOT902 specification
Table 4.ꢀMechanical properties XQFN8
Package name
Outline code
Package size
Reel format
SOT902
SOT902-3
size: 1.6 mm × 1.6 mm
thickness: 0.5 mm
4000 pcs
7" diameter
Carrier tape width 8 mm
Carrier pocket pitch 4 mm
9 Functional description
9.1 Air interface standards
The UCODE I2C fully supports all mandatory parts of the "Specification for RFID Air
Interface EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2
UHF RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0".
9.2 Power transfer
The interrogator provides an RF field that powers the tag, equipped with a UCODE I2C.
The antenna transforms the impedance of free space to the chip input impedance in
order to get the maximum possible power for the UCODE I2C on the tag.
The RF field, which is oscillating on the operating frequency provided by the interrogator,
is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC.
For I2C operation, the UCODE I2C has to be supplied externally via the VDD pin.
9.3 Data transfer air interface
9.3.1 Interrogator to tag Link
An interrogator transmits information to the UCODE I2C by modulating a UHF RF signal.
The UCODE I2C receives both information and operating energy from this RF signal.
Tags are passive, meaning that they receive all of their operating energy from the
interrogator's RF waveform.
An interrogator is using a fixed modulation and data rate for the duration of at least one
inventory round. The interrogator communicates to the UCODE I2C by modulating an RF
carrier using DSB-ASK with PIE encoding.
9.3.2 Tag to reader Link
An interrogator receives information from a UCODE I2C by transmitting an unmodulated
RF carrier and listening for a backscattered reply. The UCODE I2C backscatters by
switching the reflection coefficient of its antenna between two states in accordance with
the data being sent.
SL3S4011_4021
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NXP Semiconductors
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UCODE I²C
The UCODE I2C communicates information by backscatter-modulating the amplitude
and/or phase of the RF carrier. Interrogators shall be capable of demodulating either
demodulation type.
The encoding format, selected in response to interrogator commands, is either FM0
baseband or Miller-modulated subaltern.
9.4 Data transfer to I2C interface
The UCODE I2C memory can be read/written similar to a standard I2C serial EEPROM
device. The address space is arranged in a linear manner. When performing a sequential
read, the address pointer is increased linearly from start of the EPC memory to the end of
the user memory.
At the end address of each bank, the address pointer jumps automatically to the first
address in the subsequent bank. In I2C write modes only even address values are
accepted, due to the word wise organization of the EEPROM.
Regarding arbitration between RF and I2C, see Section 12 "RF interface/I2C interface
arbitration").
Write operation:
• Write word
• Write block (2 words)
Read operation:
• current address read
• random address read
• sequential current read
• random sequential read
9.5 Supported commands
The UCODE I2C supports all mandatory EPCglobal V1.2.0 commands.
In addition, the UCODE I2C supports the following optional commands.
• Access
• BlockWrite (32 bit)
The UCODE I2C features the following custom commands described in more detail later:
• ChangeConfig
9.6 UCODE I2C memory
The UCODE I2C memory is implemented according to EPCglobal Gen2. It is organized
in four sections all accessible via both RF and I2C operation except the reserved memory
section which only accessible via RF:
Table 5.ꢀUCODE I2C memory sections
Name
Size
Bank
00b
Reserved memory (32-bit ACCESS and 32-bit KILL password)
EPC (excluding 16 bit CRC-16 and 16-bit PC)
64 bit
160 bit
01b
SL3S4011_4021
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UCODE I²C
Name
Size
Bank
01b
01b
10b
11b
Download register
16 bit
16 bit
96 bit
3328 bit
UCODE I2C Configuration Word
TID (including unique 48-bit serial number)
User Memory
The logical addresses of all memory banks begin at zero (00h).
In addition to the 4 memory banks, one configuration word to handle the UCODE I2C-
specific features is available at EPC bank 01b address 200h. The configuration word is
described in detail in section "UCODE I2C special features".
SL3S4011_4021
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UCODE I²C
9.6.1 UCODE I2C overall memory map
Table 6.ꢀMemory map
Bank address
Memory address
Type
Content
Initial
value
Remark
RF
I2C
Bank 00
00h to 1Fh
20h to 3Fh
00h to 0Fh
not accessible via i2C
not accessible via i2C
2000h
reserved
reserved
EPC
kill password
all 00h
all 00h
unlocked memory
access password
unlocked memory
Bank 01
EPC
CRC-16:
memory mapped calculated CRC
refer to Ref. 5
10h to 1Fh
20h to 2Fh
...
2002h
2004h
EPC
EPC
EPC
EPC
EPC
EPC
TID
PC
3000h
unlocked memory
unlocked memory
unlocked memory
unlocked memory
for the bridge function
[1]
EPC bit [0 to 15]
...
B0h to BFh
1F0h to 1FFh
200h to 20Fh
00h to 0Fh
10h to 1Fh
20h to 2Fh
30h to 3Fh
40h to 4Fh
50h to 5Fh
000h to 00Fh
2016h
203Eh
2040h
4000h
4002h
4004h
4006h
4008h
400Ah
6000h
EPC bit [144 to 159]
download register
Configuration word, see Section 10.2
TID header
Bank 10 TID
n.a.
n.a.
locked memory
locked memory
locked memory
locked memory
locked memory
locked memory
unlocked memory
TID
TID header
TID
XTID_header
0000h
[2]
TID
TID serial number
TID serial number
TID serial number
user memory bit [0 to 15]
TID
n.a.
TID
n.a.
Bank 11
UM
all 00h
User memory
010h to 01Fh
...
6002h
619Eh
UM
UM
UM
user memory bit [16 to 31]
all 00h
all 00h
all 00h
unlocked memory
unlocked memory
unlocked memory
CF0h to CFFh
user memory bit [3311 to 3327]
[1] SL3S4011 EPC: E200 680D 0000 0000 0000 0000 0000 0000 0000 0000
SL3S4021 EPC: E200 688D 0000 0000 0000 0000 0000 0000 0000 0000
[2] see TID paragraph
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UCODE I²C
9.6.2 UCODE I2C TID memory details
Table 7.ꢀUCODE I2C TID description
Model number
Type
First 32 bit of TID
memory
Class ID
Mask designer ID
Config Word
indicator
Sub version number Version (Silicon) number
UCODE SL3S4011
UCODE SL3S4021
E200680D
E200688D
E2h
E2h
006h
006h
1
1
0000b
0001b
0001101
0001101
Addresses 00h
CFh
TID
LS Byte
MS Byte
MS Bit LS Bit
Addresses 00h
07h 08h
13h 14h
1Fh 20h
2Fh 30h
5Fh
0
Class Identifier
Mask-Designer Identifier
11
Model Number
80Dh or 88Dh
XTID Header
0000h
Serial Number
Bits
TID Example
7
0
0
11
0
15
0
47
E2h
(EAN.UCC)
006h
(NXP)
2
2
(UCODE I C)
(UCODE I C)
Addresses 14h
18h 19h
Sub Version Number
1Fh
Version Number
0001101b
Bits
0
3
0
6
0
000b or 001b
2
(UCODE I C)
aaa-006851
Figure 3.ꢀUCODE I2C TID memory structure
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UCODE I²C
10 Supported features
The UCODE I2C is equipped with a number of additional features and a custom
command. Nevertheless, the chip is designed in a way that standard EPCglobal READ /
WRITE / ACCESS commands can be used to operate the features.
The memory map in the previous section describes the Configuration Word used to
control the additional features located after address 200h of the EPC memory, hence
UCODE I2C features are controlled by bits located in the EPC number space. For this
reason, the standard READ / WRITE commands of a UHF EPCglobal compliant reader
can be used to select the flags or activate/deactivate features if the memory bank is not
locked. In case of locked memory banks the ChangeConfig custom command has to be
used.
The bits (flags) of the ConfigurationWord are selectable using the standard EPC SELECT
command.
10.1 UCODE I2C special feature
• Externally Supplied flag
The flag will indicate the availability of an external supply.
• RF active flag
The flag will indicate on which RF port power is available and signal transmission
ongoing.
• RF Interface on/off switching
For privacy reasons, the two RF ports as well as the I2C interface can be switched on/
off by toggling the related bits of the ConfigurationWord. The ConfigurationWord is
accessible via RF and I2C interface. Although it is possible to kill the RF interface via
the KILL feature of EPC Gen2, a minimum of one port shall be active at all times. In the
case of the dual port version, either one or both RF can be active. In the case of the
single front-end version, the RF port cannot be deactivated.
• I2C Interface on/off switching
For privacy reasons, the I2C port can be disabled by toggling the related bit of the
ConfigWord but only via RF.
• RF - I2C Bridge feature
The UCODE I2C can be used as an RF- I2C bridge to directly forward data from the
RF interface to the I2C interface and vice versa. The UCODE I2C is equipped with
a download/upload register of 16-bit data buffer located in the EPC bank. The data
received via RF can be read via I2C like regular memory content. In case the buffer
is empty reading the register returns NAK. This feature should be combined with the
Download Indicator or the interrupt signaling. The content of the buffer is only valid if
the download indicator is set and an interrupt was triggered (when interrupt signaling is
enabled in the ConfigWord).
– Upload Indicator flag (I2C to UHF) - address 203h in the configuration word
The flag will indicate if data in the download/upload register is available. Will be
automatically cleared when the download/upload register is read out via UHF.
– Download Indicator flag (UHF to I2C) - address 200h in the configuration word
The flag will indicate if data in the download/upload register is available. Will be
automatically cleared when the download/upload register is read out via I2C.
• Interrupt signaling/Download Indicator
The UCODE I2C features two methods of signaling:
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UCODE I²C
1. Signaling via ConfigWord "Download/Upload Indicator" (200h or 203h):
– The Download/Upload Indicator will go high as soon new data from the RF reader or
from the I2C interface is written to the buffer register. This flag can be polled via I2C
READ or using the SELECT command. Reading an empty buffer register will return
NAK.
– The Download/Upload Indicator will automatically return to low as soon as the data is
read.
2. Interrupt Signaling via the I2C-SCL line:
• If the SCL INT enabler of the ConfigWord is set (20Bh) the SCL line will be pulled low
for at least 210 μs in case new data was written by the reader or at least 85 μs in case
new data has been read by the reader (see Figure 4 "SCL interrupt signalling" and
Table 8 "Interrupt signaling via the I2C-SCL line timing").
UHF
Write DL Reg
Command
Write DL Reg
Response
SCL
UHF
t
SCL low_write
Read DL Reg
Command
Read DL Reg
Response
SCL
t
SCL low_read
aaa-005682
Figure 4.ꢀSCL interrupt signalling
Table 8.ꢀInterrupt signaling via the I2C-SCL line timing
Symbol
Min
210
85
Typ
Max
320
Unit
μs
tSCL low_write
266
102[2]
[1]
tSCL low_read
7800
μs
[1] This timing parameter is dependent on the chosen return link frequency.
[2] At 640 kHz return link frequency.
Remark: The features can even be operated (enabled/disabled) with '0' as ACCESS
password. It is recommended to set an ACCESS password to avoid unauthorized
manipulation of the features via the RF interface.
10.2 UCODE I2C special features control mechanism
Special features of the UCODE I2C are managed using a Configuration Word
(ConfigWord) located at the end of the EPC memory bank (address 200h via RF or
2040h via I2C) - see Table 9 and Table 10.
The bits of the ConfigWord are selectable (using the standard EPC SELECT command)
and can be read, via RF, using standard EPC READ command and via I2C. They can
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UCODE I²C
be modified using the ChangeConfig custom command or standard READ/WRITE
commands or via the I2C interface (if allowed).
The permanent bits in Table 9 and Table 10 are toggle bits.
Table 9.ꢀConfiguration Word accessible located at bit address 200h via UHF (word address 20h/32d) of the EPC
bank and I2C address 2040h (1 RF front-end version SL3S4011)
Feature
Bit type
via RF
bit address
200h
via I2C
Address
2040h
Access
read
read
read
read
r/w
Access
read
Download indicator
Externally supplied flag
RF active flag
indicator[1]
indicator
201h
read
indicator
202h
read
Upload indicator
Indicator
203h
read
I2C address bit 3[2]
I2C address bit 2[2]
I2C address bit 1[2]
I2C port on/off
permanent[3]
permanent
permanent
permanent
locked
204h
read only
read only
read only
read only
read only
205h
r/w
206h
r/w
207h
r/w
UHF antenna port1 on
rfu
208h
read only
209h
rfu
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
SCL INT enable
permanent
permanent
permanent
permanent
permanent
r/w
r/w
r/w
r/w
r/w
read only
r/w
bit for read protect user memory
bit for read protect EPC
bit for read protect TID SNR (48 bits)
PSF alarm flag
r/w
r/w
read only
[1] Indicator bits are reset at power-up but cannot be changed by command
[2] Defaults values for bit3/bit2/bit1 are 0/0/1 (see Table 15)
[3] Permanent bits are permanently stored bits in the memory
Table 10.ꢀConfiguration Word accessible located at bit address 200h via UHF (word address 20h/32d) of the EPC
bank and I2C address 2040h (2 RF front-end version SL3S4021)
Feature
Bit type
via RF
bit address
200h
via I2C
Address
2040h
Access
read
read
read
read
r/w
Access
read
Download indicator
Externally supplied flag
RF active flag
indicator[1]
indicator
201h
read
indicator
202h
read
Upload indicator
I2C address bit 3[2]
I2C address bit 2[2]
I2C address bit 1[2]
I2C port on/off
indicator
203h
read
permanent[3]
permanent
permanent
permanent
204h
read only
read only
read only
read only
205h
r/w
206h
r/w
207h
r/w
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UCODE I²C
Feature
Bit type
via RF
bit address
208h
via I2C
Access
r/w
Address
Access
r/w
UHF antenna port1 on/off
UHF antenna port2 on/off
rfu
permanent
permanent
209h
r/w
r/w
20Ah
SCL INT enable
permanent
permanent
permanent
permanent
permanent
20Bh
r/w
r/w
r/w
r/w
r/w
read only
r/w
bit for read protect user memory
bit for read protect EPC
bit for read protect TID SNR (48 bits)
PSF alarm flag
20Ch
20Dh
r/w
20Eh
r/w
20Fh
read only
[1] Indicator bits are reset at power-up but cannot be changed by command
[2] Defaults values for bit3/bit2/bit1 are 0/0/1 (see Table 15)
[3] Permanent bits are permanently stored bits in the memory
10.3 Change Config Command
The UCODE I2C ChangeConfig custom command allows handling the special features
described in the previous paragraph. As long the EPC bank is not write locked standard
EPC READ/WRITE commands can be used to modify the flags.
Table 11.ꢀChangeConfig custom command
Command
RFU
Data
RN
CRC-16
No. of bits
16
8
16
16
16
-
Description
11100000
00000111
00000000
Toggle bits
XOR RN16
handle
The bits to be toggled in the configuration register need to be set to '1'.
E.g., sending 0000 0000 0000 0000 1001 XOR RN16 will activate the EPC Read Protect
and PSF bit. Sending the very same command a second time will disable the features.
The reply of the ChangeConfig will return the current register setting.
Table 12.ꢀChangeConfig custom response table
Starting state
Condition
Response
Next state
ready
ready
all
all
-
-
arbitrate, reply,
acknowledged
arbitrate
open
valid handle, Status word
needs to change
Backscatter unchanged
StatusWord immediately
open
valid handle, Status word
does not need to change
Backscatter StatusWord
immediately
open
secured
valid handle, Status word
needs to change
Backscatter modified
StatusWord, when done
secured
secured
valid handle, Status word
does not need to change
Backscatter StatusWord
immediately
invalid handle
-
secured
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UCODE I²C
Starting state
killed
Condition
Response
Next state
all
-
killed
The features can only be activated/deactivated in the open or secured state and with
a non-zero ACCESS password. If the EPC memory bank is locked for writing, the
ChangeConfig command is needed to modify the ConfigurationWord.
10.4 UCODE I2C memory bank locking mechanism
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10.4.1 Possibilities
Table 13.ꢀMemory banks locking possibilities for UCODE I2C via RF and I2C
I2C interface
RF interface
Memory bank
Lock
PermaLock (entire bank) Lock (entire bank)
via Access Password
PermaLock (entire bank) via Access
Password
(entire bank)
01
11
EPC
yes
yes
yes
yes
yes
yes
yes
yes
User Memory
10.4.2 Via RF
The UCODE I2C memory banks can be locked following EPC Gen2 mandatory command via RF (see table Table 14).
Table 14.ꢀLock payload and usage
Kill pwd
Access pwd
EPC memory
TID memory
13
User memory
19
18
17
16
15
14
12
11
10
Mask
skip/write
9
skip/write
8
skip/write
skip/write
6
skip/write
5
skip/write
4
skip/write
3
skip/write
2
skip/write
1
skip/write
0
7
Action pwd read/write
permalock
pwd read/write
permalock
pwd write
permalock
pwd write
permalock
pwd write
permalock
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10.4.3 Via I2C
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UCODE I²C
The EPC Gen2 locking bits for the memory banks are also accessible via the I2C
interface for read and write operation and are located at the I2C address 803Ch. But it is
not possible to read and write the access and kill password.
Data Byte 1
Data Byte 2
MSB
LSB
Mask field
Kill PWD
Access PWD
EPC memory
TID memory
User memory
Skip/
write
Skip/
write
Skip/
write
Skip/
write
Skip/
write
Skip/
write
Skip/
write
Skip/
write
Skip/
write
Skip/
write
X
X
X
X
X
X
Data Byte 3
Data Byte 4
MSB
LSB
Action field
Kill PWD
Access PWD
EPC memory
TID memory
User memory
PWD
write
PWD
write
PWD
write
n/a
n/a
n/a
n/a
permalock
permalock
permalock
X
X X X X X
aaa-003734
Figure 5.ꢀI2C memory bank lock write and read access
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UCODE I²C
11 I2C commands
11.1 UCODE I2C operation
For details on I2C interface refer to Ref. 1.
SCL
SDA
Start
Condition
SDA
Input
SDA
Change
Stop
Condition
SCL
SDA
1
2
3
7
8
9
MSB
ACK
Start
Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
Stop
Condition
001aao231
Figure 6.ꢀI2C bus protocol
The UCODE I2C supports the I2C protocol. This is summarized in Figure 7. Any device
that sends data on to the bus is defined to be a transmitter, and any device that reads
the data to be a receiver. The device that controls the data transfer is known as the bus
master, and the other as the slave device. A data transfer can only be initiated by the bus
master, which will also provide the serial clock for synchronization. The device is always
a slave in all communications.
11.2 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is
stable in the high state. A Start condition must precede any data transfer command. The
UCODE I2C continuously monitors (except during a Write cycle) Serial Data (SDA) and
Serial Clock (SCL) for a Start condition, and will not respond unless one is given.
11.3 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the UCODE I2C
and the bus master. A Read command that is followed by NoAck can be followed by a
Stop condition to force the UCODE I2C into the Standby mode. A Stop condition at the
end of a Write command triggers the internal Write cycle.
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11.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending 8 bits
of data. During the ninth clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
11.5 Data input
During data input, the UCODE I2C samples Serial Data (SDA) on the rising edge of Serial
Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the
rising edge of Serial Clock (SCL). The Serial Data (SDA) signal must change only when
Serial Clock (SCL) is driven low.
11.6 Addressing
To start communication between a bus master and the UCODE I2C slave device, the
bus master must initiate a Start condition. Following this, the bus master sends the
device select code. The 7-bit device select code consists of a 4-bit device identifier (value
Ah) which is initialized in wafer test and cannot be changed in the user mode. Three
additional bits in the configuration word are reserved to alter the device address via RF
interface after initialization. This allows up to eight UCODE I2C devices to be connected
to a bus master at the same time.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write
operations.
If a match occurs on the device select code, the UCODE I2C gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the UCODE I2C does not match the device
select code, it deselects itself from the bus.
Table 15.ꢀDevice select code
Device type identifier
Device address in
configuration word 204h
to 206h
R/W
Device select
code
b7
1
b6
0
b5
1
b4
0
b3
b2
b1
b0
Value
0 [1]
0 [1]
1 [1]
1/0
[1] Initial values - can be changed - See also Table 9 and Table 10.
Table 16.ꢀI2C addressing
Most significant b15
byte
b14
b13
b12
EPC memory word address
b4 b3 b2 b1
b11
b10
b9
b8
b0
EPC address
EPC/Lock EPC memory
bank
Least
b7
b6
b5
significant byte
EPC address
EPC memory word address
MSB/
LSB
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11.7 Write Operation
The byte address must be an even value due to the word wise organization of the
EEPROM.
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Word Write
Page Write
Dev select
Byte address
Byte address
Byte address
Data in 1
Data in 1
Data in 2
Data in 2
R/W
ACK
ACK
Dev select
ACK
Byte address
ACK
R/W
Page Write
(cont'd)
Data in N
001aao230
Figure 7.ꢀI2C write operation
Following a Start condition the bus master sends a device select code with the Read/
Write bit (RW) reset to 0. The UCODE I2C acknowledges this, as shown in Figure 7 and
waits for two address bytes. The UCODE I2C responds to each address byte with an
acknowledge bit, and then waits for the data Byte.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte (Table 16) is sent first, followed by the Least Significant Byte (Table 16). Bits b15 to
b0 form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the ACK bit (in the
"10th bit" time slot), either at the end of a Word Write or a Page Write, the internal Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the UCODE
I2C does not respond to any requests.
11.7.1 Word Write
After the device select code and the address word, the bus master sends one word data.
If the addressed location is Write-protected, the UCODE I2C replies with NACK, and the
location is not modified. If, instead, the addressed location is not Write-protected, the
UCODE I2C replies with ACK. The bus master terminates the transfer by generating a
Stop condition, as shown in Figure 7.
11.7.2 Page Write
The Page Write mode allows 2 words to be written in a single Write cycle, provided that
they are all located in the same 'row' in the memory: that is, the most significant memory
address bits (b12-b2) are the same and b1= 0 and b0 = 0. If more than two words are
sent than each additional byte will cause a NACK on SDA.
The bus master sends from 1 to 2 words of data, each of which is acknowledged by the
UCODE I2C. The transfer is terminated by the bus master generating a Stop condition.
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11.8 Read operation
ACK
NO ACK
Current
Address
Read
Dev select
Data out
R/W
ACK
ACK
ACK
ACK
NO ACK
Random
Address
Read
Dev select *
Byte address
Byte address
Dev select *
Data out
R/W
ACK
R/W
NO ACK
Data out N
ACK
ACK
ACK
ACK
Sequential
Current
Read
Dev select
Data out 1
R/W
ACK
ACK
ACK
Sequential
Random
Read
Dev select *
ACK
Byte address
Byte address
Dev select *
Data out 1
R/W
R/W
NO ACK
Data out N
001aao229
Figure 8.ꢀI2C read operation
After the successful completion of a read operation, the UCODE I2C's internal address
counter is incremented by one, to point to the next byte address.
11.8.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown
in Figure 8) but without sending a Stop condition. Then, the bus master sends another
Start condition, and repeats the device select code, with the Read/Write bit (RW) set to
1. The UCODE I2C acknowledges this, and outputs the contents of the addressed byte.
The bus master must not acknowledge the byte, and terminates the transfer with a Stop
condition.
11.8.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a UCODE I2C select code with the Read/Write bit (RW) set to 1. The UCODE
I2C acknowledges this, and outputs the byte addressed by the internal address counter.
The counter is then incremented. The bus master terminates the transfer with a Stop
condition, as shown in Figure 8, without acknowledging the Byte.
11.8.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read.
The bus master does acknowledge the data byte output, and sends additional clock
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UCODE I²C
pulses so that the UCODE I2C continues to output the next byte in sequence. To
terminate the stream of bytes, the bus master must not acknowledge the last byte, and
must generate a Stop condition, as shown in Figure 8.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output.
11.8.4 Acknowledge in Read mode
For all Read commands, the UCODE I2C waits, after each byte read, for an
acknowledgment during the 9th bit time. If the bus master does not drive Serial Data
(SDA) low during this time, the UCODE I2C terminates the data transfer and switches to
its Standby mode.
11.8.5 EPC memory bank handling
After the last memory address within one EPC memory bank, the address counter 'rolls-
over' to the next EPC memory bank, and the UCODE I2C continues to output data from
memory address 00h in the successive EPC memory bank.
Example: EPC Bank 01 → EPC Bank 10 → EPC Bank 11 → EPC Bank 01
12 RF interface/I2C interface arbitration
The UCODE I2C needs to arbitrate the EEPROM access between the RF and the I2C
interface.
The arbitration is implemented as following:
• First come, first serve strategy - the interface which provides data by having a first valid
preamble on RF envelope (begin of a command) or a start condition and a valid I2C
device address on the I2C interface will be favored.
• I2C access to the chip memory is possible regardless if it is in the EPC Gen2 secured
state or not
• During an I2C command, starting with an I2C start followed by valid I2C device address
and ending with an I2C stop condition, any RF command is ignored.
• During any EPC Gen2 command, any I2C command is ignored
There are known limitations for applications where both interfaces are powered. For
details refer to Ref. 6.
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13 Limiting values
Table 17.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND.[1][2][3]
Symbol
Die
Parameter
Conditions
Min
Max
Unit
Vmax
maximum voltage
on pin VDD, SDA,
SCL, GND
-0.3
3.6
V
Tstg
storage temperature
ambient temperature
-55
-40
-
+125
+85
±2
°C
°C
kV
Tamb
VESD
electrostatic discharge
voltage
Human body
model; SNW-
FQ-302A
Charged device
model
-
±500
V
[1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any conditions other than those described in the
Operating Conditions and Electrical Characteristics section of this specification is not implied.
[2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of
excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater
than the rated maxima.
[3] For ESD measurement, the die chip has been mounted into a CDIP8 package.
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14 Characteristics
Table 18.ꢀCharacteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
EEPROM characteristics
tret
retention time
Tamb ≤ 55 °C
Tamb ≤ 85 °C
20
-
-
-
-
year
Nendu(W)
write endurance
100000
cycle
Interface characteristics
Ptot
total power dissipation
-
-
30
mW
foper
Pmin
operating frequency
840
-
960
MHz
dBm
dBm
dBm
minimum operating power
supply[1]
Read mode
Write mode
-
-
-
-18
-11
-23
-
-
-
Read and Write mode
with VDD input
VDD
VDD
supply voltage
I2C, on VDD input
1.8
-
-
3.6
-
V
supply voltage rise time
requirements
100
μs
IDD
supply current
from VDD in I2C read
mode
from VDD in I2C write
mode
-
-
10
40
-
-
μA
μA
Z
impedance (package)
915 MHz
866 MHz
953 MHz
-
-
-
-
12.7-j 199
13.8-j 210
12.4-j 190
-4
-
-
-
-
Ω
Ω
Ω
-
-
modulated jammer suppression
≥ 1.0 MHz
dB
unmodulated jammer
suppression ≥ 1.0 MHz
-
-4
-
dB
VIL
LOW-level input voltage[2]
HIGH-level input voltage[2]
-0.5
-
-
-
0.3 VDD
V
V
V
[3]
VIH
Vhys
0.7 VDD
0.05 VDD
-
hysteresis of Schmitt trigger
inputs[4]
-
VOL1
LOW-level output voltage 1
LOW-level output voltage 2[4]
(open-drain or open-
collector)
0
-
0.4
V
at 3 mA sink current[5];
VDD > 2 V
VOL2
(open-drain or open-
collector)
at 2 mA sink current[[5];
VDD ≤ 2 V
0
-
0.2 VDD
V
[1] Tag sensitivity on a 2 dBi gain antenna
[2] Some legacy Standard-mode devices had fixed input levels of VIL = 1.5 V and VIH = 3.0 V.
[3] Maximum VIH = VDD(max) + 0.5 V.
[4] Only applies to Fast Mode and Fast Mode Plus.
[5] The same resistor value to drive 3 mA at 3.0 V VDD provides the same RC time constant when using <2 V VDD with a smaller current draw.
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15 Package outline
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-3
X
D
B
A
E
terminal 1
index area
A
A
1
detail X
e
e
C
v
C
C
A B
L
y
y
w
C
1
4
b
3
2
5
6
7
e
e
1
1
1
terminal 1
index area
8
metal area
not for soldering
0
1
2 mm
scale
Dimensions
Unit
A
A
b
D
E
e
e
L
v
w
y
y
1
1
1
max 0.5 0.05 0.25 1.65 1.65
0.45
0.40
0.35
nom
min
0.20 1.60 1.60
0.00 0.15 1.55 1.55
mm
0.6
0.5
0.1 0.05 0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot902-3_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
11-08-16
11-08-18
SOT902-3
MO-255
Figure 9.ꢀPackage outline SOT902-3
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16 Abbreviations
Table 19.ꢀAbbreviations
Acronym
CRC
Description
Cyclic Redundancy Check
Continuous Wave
CW
EEPROM
EPC
Electrically Erasable Programmable Read Only Memory
Electronic Product Code (containing Header, Domain Manager, Object Class
and Serial Number)
FM0
HBM
IC
Bhi phase space modulation
Human Body Model
Integrated Circuit
LSB
MSB
NRZ
RF
Least Significant Byte/Bit
Most Significant Byte/Bit
Non-Return to Zero coding
Radio Frequency
RTF
Tari
UHF
Xxb
Reader Talks First
Type A Reference Interval (ISO 18000-6)
Ultra High Frequency
Value in binary notation
Value in hexadecimal notation
XXhex
17 References
1. I2C-bus specification and user manual (NXP standard UM10204.pdf / Rev. 03 - 19
June 2007)
2. EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for
Communications at 860 MHz - 960 MHz Version 1.2.0
3. EPC Conformance Standard Version 1.0.5
4. ESD Method SNW -FQ-302A
5. ISO/IEC 18000-1: Information technology - Radio frequency identification for item
management - Part 1: Reference architecture and definition of parameters to be
standardized
6. Errata Sheet UCODE I²C (NXP document ES3715.pdf)
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18 Revision history
Table 20.ꢀRevision history
Document ID
Release date
20180918
Data sheet status
Change notice
Supersedes
SL3S4011_4021 v. 3.5
Modifications:
Product data sheet
-
SL3S4011_4021 v. 3.4
• Table 18: Unit of VDD corrected
• Section 2.4: Bullet "Encoding speed one word 5 ms" added
SL3S4011_4021 v. 3.4
Modifications:
20170524
• Write endurance updated into 100 kcycles
20170215 Product data sheet
• Table 2 Marking added
Product data sheet
-
SL3S4011_4021 v. 3.3
SL3S4011_4021 v. 3.2
SL3S4011_4021 v. 3.3
Modifications:
-
• Table 18: Impedances for all frequencies added
• References to errata sheet added
• Minor editorial updates
SL3S4011_4021 v. 3.2
Modifications:
20151012
Product data sheet
-
SL3S4011_4021 v. 3.1
• Section 10.1 "UCODE I2C special feature": "RF - I2C Bridge feature" updated
• Minor editorial updates
SL3S4011_4021 v. 3.1
Modifications:
20130703
Product data sheet
-
SL3S4011_4021 v. 3.0
SL3S4011_4021 v. 2.3
SL3S4011_4021 v. 2.2
• General update
20130416
SL3S4011_4021 v. 3.0
Modifications:
Product data sheet
-
• Data sheet status changed to Product data sheet
SL3S4011_4021 v. 2.3
Modifications:
20130305
Preliminary data sheet
-
• General update
• Security status changed into COMPANY PUBLIC
SL3S4011_4021 v. 2.2
Modifications:
20121127
Preliminary data sheet
Preliminary data sheet
Preliminary data sheet
Objective data sheet
SL3S4011_4021 v. 2.1
SL3S4001FHK v. 2.0
SL3S4001FHK v. 1.2
SL3S4001FHK v. 1.1
• General update
20120726
SL3S4011_4021 v. 2.1
Modifications:
-
-
-
• General update
20120627
SL3S4011_4021 v. 2.0
Modifications:
• General update
20111004
SL3S4001FHK v. 1.2
Modifications:
• Table 1 "Ordering information": updated
• Figure 3 "UCODE I2C wafer layout": values updated
SL3S4001FHK v. 1.1
Modifications:
20110707 Objective data sheet
-
SL3S4001FHK v. 1.0
• Table 3 "Mechanical properties XQFN8": updated
• Section 10.6 "Addressing": updated
SL3S4001FHK v. 1.0
20110609
Objective data sheet
-
-
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19 Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
19.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
SL3S4011_4021
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
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204935
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NXP Semiconductors
SL3S4011_4021
UCODE I²C
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
19.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
UCODE — is a trademark of NXP B.V.
SL3S4011_4021
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© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.5 — 18 September 2018
204935
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NXP Semiconductors
SL3S4011_4021
UCODE I²C
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Ordering information ..........................................3
20h/32d) of the EPC bank and I2C address
2040h (2 RF front-end version SL3S4021) ......12
Tab. 11. ChangeConfig custom command .................... 13
Tab. 12. ChangeConfig custom response table ............ 13
Tab. 13. Memory banks locking possibilities for
UCODE I2C via RF and I2C ........................... 15
Tab. 14. Lock payload and usage .................................15
Tab. 15. Device select code ..........................................18
Tab. 16. I2C addressing ................................................18
Tab. 17. Limiting values ................................................ 22
Tab. 18. Characteristics .................................................23
Tab. 19. Abbreviations ...................................................25
Tab. 20. Revision history ...............................................26
Marking ..............................................................3
Pin description ...................................................4
Mechanical properties XQFN8 .......................... 5
UCODE I2C memory sections .......................... 6
Memory map ..................................................... 8
UCODE I2C TID description ............................. 9
Interrupt signaling via the I2C-SCL line
timing ...............................................................11
Configuration Word accessible located at
bit address 200h via UHF (word address
20h/32d) of the EPC bank and I2C address
2040h (1 RF front-end version SL3S4011) ......12
Tab. 9.
Tab. 10. Configuration Word accessible located at
bit address 200h via UHF (word address
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Block diagram ................................................... 3
Pin configuration ............................................... 4
UCODE I2C TID memory structure ...................9
SCL interrupt signalling ...................................11
I2C memory bank lock write and read access .. 16
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
I2C bus protocol ..............................................17
I2C write operation ..........................................19
I2C read operation .......................................... 20
Package outline SOT902-3 ............................. 24
SL3S4011_4021
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© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.5 — 18 September 2018
204935
29 / 30
NXP Semiconductors
SL3S4011_4021
UCODE I²C
Contents
1
2
General description ............................................ 1
12
13
14
15
16
17
18
19
RF interface/I2C interface arbitration .............. 21
Limiting values ..................................................22
Characteristics .................................................. 23
Package outline .................................................24
Abbreviations .................................................... 25
References .........................................................25
Revision history ................................................ 26
Legal information ..............................................27
Features and benefits .........................................1
UHF interface .................................................... 1
I2C interface ...................................................... 2
Command set .................................................... 2
Memory ..............................................................2
Package .............................................................2
Applications .........................................................2
Ordering information .......................................... 3
Marking .................................................................3
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ...............................................................4
Pin description ...................................................4
Mechanical specification ....................................5
SOT902 specification .........................................5
Functional description ........................................5
Air interface standards .......................................5
Power transfer ................................................... 5
Data transfer air interface ..................................5
Interrogator to tag Link ...................................... 5
Tag to reader Link .............................................5
Data transfer to I2C interface ............................ 6
Supported commands ........................................6
UCODE I2C memory .........................................6
UCODE I2C overall memory map ..................... 8
UCODE I2C TID memory details .......................9
Supported features ........................................... 10
UCODE I2C special feature .............................10
UCODE I2C special features control
2.1
2.2
2.3
2.4
2.5
3
4
5
6
7
7.1
7.2
8
8.1
9
9.1
9.2
9.3
9.3.1
9.3.2
9.4
9.5
9.6
9.6.1
9.6.2
10
10.1
10.2
mechanism .......................................................11
Change Config Command ............................... 13
UCODE I2C memory bank locking
10.3
10.4
mechanism .......................................................14
Possibilities ...................................................... 15
Via RF ............................................................. 15
Via I2C .............................................................16
I2C commands .................................................. 17
UCODE I2C operation .....................................17
Start condition ..................................................17
Stop condition ..................................................17
Acknowledge bit (ACK) ....................................18
Data input ........................................................ 18
Addressing .......................................................18
Write Operation ............................................... 19
Word Write .......................................................19
Page Write .......................................................19
Read operation ................................................20
Random Address Read ................................... 20
Current Address Read .....................................20
Sequential Read .............................................. 20
Acknowledge in Read mode ............................21
EPC memory bank handling ............................21
10.4.1
10.4.2
10.4.3
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.7.1
11.7.2
11.8
11.8.1
11.8.2
11.8.3
11.8.4
11.8.5
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 September 2018
Document identifier: SL3S4011_4021
Document number: 204935
相关型号:
SL3S4021FHK
SPECIALTY MICROPROCESSOR CIRCUIT, PQCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, MO-255, SOT902-3, PLASTIC, XQFN-8
NXP
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