SIMXRT8RT10601DAE6A [NXP]
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products;
| 型号： | SIMXRT8RT10601DAE6A |
| 厂家： | 
NXP |
| 描述： | i.MX RT1010 Crossover Processors Data Sheet for Consumer Products |
| 文件： | 总65页 (文件大小：1256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: IMXRT1010CEC
Rev. 0, 09/2019
NXP Semiconductors
Data Sheet: Technical Data
MIMXRT1011DAE5A
i.MX RT1010 Crossover
Processors Data Sheet
for Consumer Products
Package Information
Plastic Package
80-Pin LQFP, 12 x 12 mm, 0.5 mm pitch
Ordering Information
See Table 1 on page 4
1 i.MX RT1010 introduction
The i.MX RT1010 is a member of i.MX RT real-time
1. i.MX RT1010 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 4
2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1. Special signal considerations . . . . . . . . . . . . . . . 12
3.2. Recommended connections for unused analog
®
®
processor family based on the Arm Cortex -M7 core,
which operates at speeds up to 500 MHz to provide high
CPU performance and best real-time response.
The i.MX RT1010 processor has 128 KB on-chip RAM,
which can be flexibly configured as TCM or
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 15
4.2. System power and clocks . . . . . . . . . . . . . . . . . . 21
4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.5. External memory interface . . . . . . . . . . . . . . . . . 34
4.6. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.7. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.8. Communication interfaces . . . . . . . . . . . . . . . . . . 49
4.9. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 55
5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 55
5.2. Boot device interface allocation . . . . . . . . . . . . . . 55
6. Package information and contact assignments . . . . . . . 57
6.1. 12 x 12 mm package information . . . . . . . . . . . . 57
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
general-purpose on-chip RAM. The i.MX RT1010
integrates advanced power management module with
DCDC and LDO that reduces complexity of external
power supply and simplifies power sequencing. The
i.MX RT1010 also provides various memory interfaces,
including Quad SPI, and a wide range of connectivity
interfaces, including UART, SPI, I2C, and USB; for
connecting peripherals including WLAN, Bluetooth™,
and GPS. The i.MX RT1010 also has rich audio features,
including SPDIF and I2S audio interface. Various analog
IP integration, including ADC, temperature sensor, and
etc.
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
i.MX RT1010 introduction
The i.MX RT1010 is specifically useful for applications, such as:
•
•
•
•
•
Audio
Industrial
Motor Control
Home Appliance
IoT
1.1
Features
The i.MX RT1010 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the
following features:
®
®
•
Supports single Arm Cortex -M7 with:
— 16 KB L1 Instruction Cache
— 8 KB L1 Data Cache
— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
— Support the Armv7-M Thumb instruction set, defined in the ARM v7-M architecture
Integrated MPU, up to 16 individual protection regions
Up to 128 KB I-TCM and D-TCM in total
•
•
•
•
•
Up to 500 MHz frequency
®
Cortex M7 CoreSight™ components integration for debug
Frequency of the core, as per Table 9, "Operating ranges," on page 16.
The SoC-level memory system consists of the following additional components:
— Boot ROM (64 KB)
— On-chip RAM (128 KB)
– Configurable RAM size up to 128 KB shared with CM7 TCM
•
•
External memory interfaces:
— SPI NOR FLASH
— Single/Dual channel Quad SPI FLASH with XIP support and on-the-fly decryption
— Octal flash
Timers and PWMs:
— Two General Programmable Timers (GPT)
– 4-channel generic 32-bit resolution timer for each
– Each support standard capture and compare operation
— Periodical Interrupt Timer (PIT)
– Generic 32-bit resolution timer
– Periodical interrupt generation
— FlexPWM
– Up to 4 submodules
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
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NXP Semiconductors
i.MX RT1010 introduction
– 16-bit resolution PWM suitable for Motor Control applications
Each i.MX RT1010 processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
•
Audio:
— SPDIF input and output
— Two synchronous audio interface (SAI) modules, which support I2S, AC97, TDM, and
codec/DSP interfaces
— MQS interface for medium quality audio via GPIO pads
Connectivity:
•
— One USB 2.0 OTG controller with integrated PHY interface
— Four universal asynchronous receiver/transmitter (UART) modules
— Two I2C modules
— Two SPI modules
•
GPIO and Pin Multiplexing:
— General-purpose input/output (GPIO) modules with interrupt capability
— Input/output multiplexing controller (IOMUXC) to provide centralized pad control
— 44 GPIOs for 80-pin LQFP package
— FlexIO
The i.MX RT1010 processors integrate advanced power management unit and controllers:
•
•
•
Full PMIC integration, including on-chip DCDC and LDOs
Temperature sensor with programmable trim points
GPC hardware power management controller
The i.MX RT1010 processors support the following system debug:
®
®-
•
•
•
Arm Cortex M7 CoreSight debug and trace architecture
Trace Port Interface Unit (TPIU) to support off-chip real-time trace
1
Support for 5-pin JTAG and SWD debug interfaces
Security functions are enabled and accelerated by the following hardware:
•
•
High Assurance Boot (HAB)
Data Co-Processor (DCP):
— AES-128, ECB, and CBC mode
— SHA-1 and SHA-256
— CRC-32
•
•
FlexSPI with On-The-Fly AES Decryption (OTFAD)
— AES-128, CTR mode
— On-the-fly QSPI Flash decryption
True random number generation (TRNG)
1. SWD is the default debug interface.
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
NXP Semiconductors
3
i.MX RT1010 introduction
•
Secure Non-Volatile Storage (SNVS)
— Secure real-time clock (RTC)
— Zero Master Key (ZMK)
Secure JTAG Controller (SJC)
•
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions such as connectivity interfaces, and security features are not
offered on all derivatives.
1.2
Ordering information
Table 1 provides orderable part numbers covered by this data sheet.
Table 1. Ordering information
Junction
Temperature
Tj (C)
Part Number
Features
Package
MIMXRT1011DAE5A
• 500 MHz, consumer
• SPI x2
12 x 12 mm 80-pin LQFP, 0.5 0 to 95
grade for general
purpose
• KPP
• ADC x1
mm pitch
• DMA
• FlexSPI
• Boot ROM (64KB)
• On-chip RAM
(128KB)
• USB OTG x1
• SAI x2
• FLEXIO
• GPIO
• HAB/DCP/OTFAD
• TRNG
• SNVS
• SPDIF x1
• MQS x1
• SJC
• DCDC
• GPT x2
• PWM x1
• 4-channel PIT
• WDOG x4
• UART x4
• I2C x2
• Temperature sensor
• GPC hardware power
management
controller
Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be
identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The
primary characteristic which describes which data sheet applies to a specific part is the temperature grade
(junction) field.
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMXRT or
contact an NXP representative for details.
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
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NXP Semiconductors
i.MX RT1010 introduction
M
IMX X X
@
##
%
+
VV
$
A
Silicon Rev
A
Qualification Level
M
A0
A
Prototype Samples
Mass Production
Special
P
M
S
Frequency
400 MHz
500 MHz
600 MHz
700 MHz
800 MHz
1000 MHz
$
4
5
6
7
8
A
Part # series
XX
i.MX RT
RT
@
Family
First Generation RT family
Reserved
1
2
3
4
5
6
7
8
VV
Package Type
80-pin LQFP, 12 x 12 mm, 0.5 mm pitch
AE
Sub-Family
##
Temperature
Consumer: 0 to + 95 °C
Industrial: -40 to +105 °C
+
D
C
01
02
05
06
RT1010
RT1020
RT1050
RT1060
Tie
1
%
Standard Feature General Purpose
Enhanced Feature
5
Figure 1. Part number nomenclature—i.MX RT1010
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
NXP Semiconductors
5
Architectural overview
2 Architectural overview
The following subsections provide an architectural overview of the i.MX RT1010 processor system.
2.1
Block diagram
1
Figure 2 shows the functional modules in the i.MX RT1010 processor system .
CPU Platform
System Control
Connectivity
ARM Cortex-M7
Security JTAG
UART x4
16 KB I-cache
FPU
8 KB D-cache
4 x 4 Keypad
I2C x2
PLL / OSC
NVIC
MPU
RTC and Reset
HSGPIO
128K I-TCM and D-TCM
SPI x2
Embedded DMA
IOMUX
FlexIO
External Memory
Dual-Channel Quad-SPI
Octal/Hyper Flash/RAM
GPIO
GP Timer x3
FlexPWM x1
Watch Dog x4
I2S / SAI x2
FlexSPI with on-the-fly AES decryption
SPDIF Tx/Rx
MQS
Security
HAB
Power Management
USB2.0 OTG with PHY x1
DCDC
Ciphers
RNG
LDO
Internal Memory
Temp Monitor
128 KB SRAM shared with TCM
Secure RTC
eFuse
ADC
64 KB ROM
ADC (15-ch) x1
.
Figure 2. i.MX RT1010 system block diagram
1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
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NXP Semiconductors
Modules list
3 Modules list
The i.MX RT1010 processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX RT1010 modules list
Block mnemonic
Block name
Subsystem
Analog
Brief description
ADC1
Analog to Digital
Converter
The ADC is a 12-bit general purpose analog to digital
converter.
ADC_ETC
AOI
ADC External Trigger
Control
Analog
The ADC_ETC enables multiple users to share an ADC
module in a Time-Division-Multiplexing (TDM) way.
And-Or-Inverter
Cross Trigger
The AOI provides a universal boolean function
generator with using a four team sum of products
expression, for each product term containing true or
complement values of the four selected inputs (A, B, C,
D).
Arm
Arm Platform
Arm
The Arm Core Platform includes 1x Cortex-M7 core. It
also includes associated sub-blocks, such as Nested
Vectored Interrupt Controller (NVIC), Floating-Point
Unit (FPU), Memory Protection Unit (MPU), and
CoreSight debug modules.
CCM
GPC
SRC
Clock Control Module,
General Power
Controller, System Reset
Controller
Clocks, Resets, and These modules are responsible for clock and reset
Power Control
distribution in the system, and also for the system
power management.
CSU
DAP
Central Security Unit
Security
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
RT1010 platform.
Debug Access Port
System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-M7
Core Platform.
DCDC
DCDC Converter
Analog
The DCDC module is used for generating power supply
for core logic. Main features are:
• Adjustable high efficiency regulator
• Supports 3.3 V input voltage
• Supports nominal run and low power standby modes
• Supports at 0.9 ~ 1.3 V output in run mode
• Supports at 0.9 ~ 1.0 V output in standby mode
• Over current and over voltage detection
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
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Modules list
Table 2. i.MX RT1010 modules list (continued)
Block mnemonic
Block name
Subsystem
Brief description
eDMA
enhanced Direct Memory System Control
There is an enhanced DMA (eDMA) engine and
DMA_MUX.
Access
Peripherals
• The eDMA is a 16-channel DMA engine, which is
capable of performing complex data transfers with
minimal intervention from a host processor.
• The DMA_MUX is capable of multiplexing up to 128
DMA request sources to the 16 DMA channels of
eDMA.
EWM
External Watchdog
Monitor
Timer Peripherals
The EWM modules is designed to monitor external
circuits, as well as the software flow. This provides a
back-up mechanism to the internal WDOG that can
reset the system. The EWM differs from the internal
WDOG in that it does not reset the system. The EWM,
if allowed to time-out, provides an independent trigger
pin that when asserted resets or places an external
circuit into a safe mode.
FlexIO1
Flexible Input/output
Connectivity and
Communications
The FlexIO is capable of supporting a wide range of
protocols including, but not limited to: UART, I2C, SPI,
I2S, camera interface, display interface, PWM
waveform generation, etc. The module can remain
functional when the chip is in a low power mode
provided the clock it is using remain active.
FlexPWM1
FlexRAM
Pulse Width Modulation Timer Peripherals
The pulse-width modulator (PWM) contains four PWM
sub-modules, each of which is set up to control a single
half-bridge power stage. Fault channel support is
provided. The PWM module can generate various
switching patterns, including highly sophisticated
waveforms.
RAM
Memories
The i.MX RT1010 has 128 KB of on-chip RAM which
could be flexible allocated to I-TCM, D-TCM, and
on-chip RAM (OCRAM) in a 32 KB granularity. The
FlexRAM is the manager of the 128 KB on-chip RAM
array. Major functions of this blocks are: interfacing to
I-TCM and D-TCM of Arm core and OCRAM controller;
dynamic RAM arrays allocation for I-TCM, D-TCM, and
OCRAM.
FlexSPI
Quad Serial Peripheral
Interface
Connectivity and
Communications
FlexSPI acts as an interface to one or two external
serial flash devices, each with up to four bidirectional
data lines.
GPIO1
GPIO2
GPIO5
General Purpose I/O
Modules
System Control
Peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
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Modules list
Table 2. i.MX RT1010 modules list (continued)
Block mnemonic
Block name
General Purpose Timer
Subsystem
Brief description
GPT1
GPT2
Timer Peripherals
Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
KPP
Keypad Port
Human Machine
Interfaces
The KPP is a 16-bit peripheral that can be used as a
keypad matrix interface or as general purpose
input/output (I/O). It supports 8 x 8 external key pad
matrix. Main features are:
• Multiple-key detection
• Long key-press detection
• Standby key-press detection
• Supports a 2-point and 3-point contact key matrix
LPI2C1
LPI2C2
Low Power
Inter-integrated Circuit
Connectivity and
Communications
The LPI2C is a low power Inter-Integrated Circuit (I2C)
module that supports an efficient interface to an I2C bus
as a master.
The I2C provides a method of communication between
a number of external devices. More detailed
information, see Section 4.8.2, "LPI2C module timing
parameters".
LPSPI1
LPSPI2
Low Power Serial
Peripheral Interface
Connectivity and
Communications
The LPSPI is a low power Serial Peripheral Interface
(SPI) module that support an efficient interface to an
SPI bus as a master and/or a slave.
• It can continue operating while the chip is in stop
mode, if an appropriate clock is available.
• Designed for low CPU overhead, with DMA off
loading of FIFO register access.
LPUART1
LPUART2
LPUART3
LPUART4
UART Interface
Connectivity
Peripherals
Each of the UART modules support the following serial
data transmit/receive protocols and configurations:
• 7- bit or 8-bit data words, 1 or 2 stop bits,
programmable parity (even, odd or none)
• Programmable baud rates up to 5 Mbps.
OTFAD
PIT
On-the-Fly AES
Decryption
Security
OTFAD co-works with FlexSPI to provide superior
cryptographic decryption capabilities without
compromising system performance.
Periodical Interrupt Timer Timer Peripherals
The PIT features 32-bit counter timer, programmable
count modules, clock division, interrupt generation, and
a slave mode to synchronize count enable for multiple
PITs.
MQS
Medium Quality Sound
Multimedia
Peripherals
MQS is used to generate 2-channel medium quality
PWM-like audio via two standard digital GPIO pins.
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
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9
Modules list
Table 2. i.MX RT1010 modules list (continued)
Block mnemonic
Block name
Subsystem
Brief description
The ROMCP acts as an interface between the Arm
ROMCP
ROM Controller with
Patch
Memories and
Memory Controllers advanced high-performance bus and the ROM. The
on-chip ROM is only used by the Cortex-M7 core during
boot up. Size of the ROM is 64 KB.
RTC OSC
RTWDOG
Real Time Clock
Oscillator
Clock Sources and The RTC OSC provides the clock source for the
Control
Real-Time Clock module. The RTC OSC module, in
conjunction with an external crystal, generates a 32.678
kHz reference clock for the RTC.
Watch Dog
Timer Peripherals
The RTWDG module is a high reliability independent
timer that is available for system to use. It provides a
safety feature to ensure software is executing as
planned and the CPU is not stuck in an infinite loop or
executing unintended code. If the WDOG module is not
serviced (refreshed) within a certain period, it resets the
MCU. Windowed refresh mode is supported as well.
SAI1
SAI3
Synchronous Audio
Interface
Multimedia
Peripherals
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
SA-TRNG
SJC
StandaloneTrueRandom Security
Number Generator
The SA-TRNG is hardware accelerator that generates
a 512-bit entropy as needed by an entropy consuming
module or by other post processing functions.
Secure JTAG Controller System Control
Peripherals
The SJC provides JTAG interface, which complies with
JTAG TAP standards, to internal logic. The i.MX
RT1010 processors use JTAG port for production,
testing, and system debugging. In addition, the SJC
provides BSR (Boundary Scan Register) standard,
which complies with IEEE1149.1 and IEEE1149.6.
The JTAG port is accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX RT1010 SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, and Master Key
Control.
SPDIF
Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly
by the Sony and Phillips corporations. It has Transmitter
and Receiver functionality.
Temp Monitor
Temperature Monitor
Analog
The temperature sensor implements a temperature
sensor/conversion function based on a
temperature-dependent voltage to time conversion.
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
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Modules list
Table 2. i.MX RT1010 modules list (continued)
Block name Subsystem Brief description
Universal Serial Bus 2.0 Connectivity USB 2.0 (USB OTG1) contains:
Block mnemonic
USB 2.0
Peripherals
• One high-speed OTG 2.0 module with integrated HS
USB PHY
• Support eight Transmit (TX) and eight Receive (RX)
endpoints, including endpoint 0
WDOG1
WDOG2
WDOG3
Watch Dog
Cross BAR
Timer Peripherals
The Watch Dog Timer supports two comparison points
during each counting period. Each of the comparison
points is configurable to evoke an interrupt to the Arm
core, and a second point evokes an external event on
the WDOG line.
XBAR
Cross Trigger
Each crossbar switch is an array of muxes with shared
inputs. Each mux output provides one output of the
crossbar. The number of inputs and the number of
muxes/outputs are user configurable and registers are
provided to select which of the shared inputs are routed
to each output.
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Modules list
3.1
Special signal considerations
Table 3 lists special signal considerations for the i.MX RT1010 processors. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, "Package information and contact
assignments".” Signal descriptions are provided in the i.MX RT1010 Reference Manual
(IMXRT1010RM).
Table 3. Special signal considerations
Signal name
Remarks
DCDC_PSWITCH
PAD is in DCDC_IN domain and connected the ground to bypass DCDC.
To enable DCDC function, assert to DCDC_IN with at least 1 ms delay for DCDC_IN rising edge.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of
startup margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin must
remain unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical
conditions.
In case when high accuracy real time clock are not required, system may use internal low
frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and keep
RTC_XTALO unconnected.
XTALI/XTALO
A 24.0 MHz crystal should be connected between XTALI and XTALO. External load capacitance
value depends on the typical load capacitance of crystal used and PCB design.
The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series
resistance) of typical 80 is recommended. NXP SDK software requires 24 MHz on
XTALI/XTALO.
The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this
case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF
capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level.
If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter
requirements. See OSC24M chapter and relevant interface specifications chapters for details.
If driving the chip with an external clock source, then a 24 MHz oscillator can be driven in one of
three configurations using a nominal 1.1 V source.
• A single ended external clock source can be used to overdrive the output of the amplifier
(XTALO). Since the oscillation sensing amplifier is differential, the XTALI pin should be
externally floating and capacitively loaded. The combination of the internal biasing resistor and
the external capacitor will filter the signal applied to the XTALO pin and develop a rough
reference for the sensing amplifier to compare.
• A single ended external clock source can be used to drive XTALI. In this configuration, XTALO
should be left externally unconnected.
• A differential external clock source can be used to drive both XTALI and XTALO.
Generally, second configuration is anticipated to be the most used configuration, but all three
configurations may be utilized.
GPANAIO
This signal is reserved for NXP manufacturing use only. This output must remain unconnected.
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Modules list
Table 3. Special signal considerations (continued)
Remarks
Signal name
JTAG_nnnn
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated
if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX RT1010 reference manual. Both names refer
to the same signal. JTAG_MOD must be externally connected to GND for normal operation.
Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD
set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD
set to low configures the JTAG interface for common SW debug adding all the system TAPs to the
chain.
NC
These signals are No Connect (NC) and should be disconnected by the user.
POR_B
This cold reset negative logic input resets all modules and logic in the IC.
May be used in addition to internally generated power on reset signal (logical AND, both internal
and external signals are considered active low).
ONOFF
ONOFF can be configured in debounce, off to on time, and max time-out configurations. The
debounce and off to on time configurations supports 0, 50, 100, and 500 ms. Debounce is used to
generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than
the debounce time, the power off interrupt is generated. Off to on time supports the time it takes
to request power on after a configured button press time has been reached. While in the OFF
state, if ONOFF button is pressed longer than the off to on time, the state will transition from OFF
to ON. Max time-out configuration supports 5, 10, 15 seconds, and disable. Max time-out
configuration supports the time it takes to request power down after ONOFF button has been
pressed for the defined time.
TEST_MODE
TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.
Table 4. JTAG controller interface summary
JTAG
I/O type
On-chip termination
100 kpull-down
JTAG_TCK
JTAG_TMS
JTAG_TDI
Input
Input
47 kpull-up
47 kpull-up
Keeper
Input
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
3-state output
Input
47 kpull-up
100 kpull-down
Input
3.2
Recommended connections for unused analog interfaces
Table 5 shows the recommended connections for unused analog interfaces.
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Modules list
Module
Table 5. Recommended connections for unused analog interfaces
Pad name
Recommendations
if unused
USB
ADC
USB_OTG1_CHD_B, USB_OTG1_DN, USB_OTG1_DP, USB_OTG1_VBUS
VDDA_ADC_3P3
Not connected
VDDA_ADC_3P3
must be powered
even if the ADC is
not used.
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Electrical characteristics
4 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX RT1010
processors.
4.1
Chip-level conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX RT1010 chip-Level conditions
For these characteristics
Topic appears
Absolute maximum ratings
Thermal resistance
on page 15
on page 16
on page 16
on page 18
on page 18
on page 20
on page 20
Operating ranges
External clock sources
Maximum supply currents
Low power mode supply currents
USB PHY current consumption
4.1.1
Absolute maximum ratings
CAUTION
Stress beyond those listed under Table 7 may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
Table 7 shows the absolute maximum operating ratings.
Table 7. Absolute maximum ratings
Parameter Description
Core supplies input voltage
Symbol
VDD_SOC_IN
Min
Max
Unit
-0.3
-0.3
-0.3
-0.3
1.6
3.7
3.6
3.6
V
V
V
V
VDD_HIGH_IN supply voltage
Power for DCDC
VDD_HIGH_IN
DCDC_IN
Supply input voltage to Secure Non-Volatile Storage VDD_SNVS_IN
and Real Time Clock
USB VBUS supply
USB_OTG1_VBUS
VDDA_ADC
—
5.5
3.6
3.6
V
V
V
Supply for 12-bit ADC
-0.3
-0.3
IO supply for GPIO bank (3.3 V mode)
NVCC_GPIO
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Electrical characteristics
Table 7. Absolute maximum ratings (continued)
ESD Damage Immunity:
Vesd
Human Body Model (HBM)
Charge Device Model (CDM)
—
—
1000
500
V
Input/Output Voltage range
Storage Temperature range
Vin/Vout
-0.5
-40
OVDD + 0.31
150
V
TSTORAGE
o C
1
OVDD is the I/O supply voltage.
4.1.2
Thermal resistance
Following sections provide the thermal resistance data.
4.1.2.1 Package thermal characteristics
Table 8 displays the 12 x 12 mm LQFP package thermal resistance data.
Table 8. 12 x 12 mm package thermal resistance data
Rating
Board type1
JESD51-9, 2s2p
Symbol
RJA
Value
Unit
Junction to Ambient
46.5
oC/W
Thermal Resistance2
Junction to Package Top
Thermal Resistance2
JESD51-9, 2s2p
JT
2.0
oC/W
oC/W
Junction to Case Thermal Resistance3
JESD51-9, 1s
RJC
22.1
1
Thermal test board meets JEDEC specification for this package (JESD51-9)
2
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
3
Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the mold surface
temperature at the package top side dead centre.
4.1.3
Operating ranges
Table 9 provides the operating ranges of the i.MX RT1010 processors. For details on the chip's power
structure, see the “Power Management Unit (PMU)” chapter of the i.MX RT1010 Reference Manual
(IMXRT1010RM).
Table 9. Operating ranges
Parameter
Description
Operating
Conditions
Symbol
Min
Typ Max1 Unit
Comment
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Electrical characteristics
Table 9. Operating ranges (continued)
Run Mode
VDD_SOC_IN
VDD_SOC_IN
Overdrive
1.25
1.15
—
—
1.3
1.3
V
V
—
—
M7 core at 396
MHz
M7 core at 132
MHz
1.15
0.925
1.15
—
—
—
1.3
1.3
1.3
M7 core at 24
MHz
IDLE Mode
VDD_SOC_IN
M7 core
V
—
operation at 396
MHz or below
SUSPEND (DSM) VDD_SOC_IN
Mode
—
0.925
—
1.3
V
V
Refer to Table 12 Low power mode
current and power consumption
SNVS Mode
VDD_SOC_IN
—
—
—
0
1.3
3.6
3.6
—
—
Power for DCDC DCDC_IN
3.0
3.0
3.3
—
VDD_HIGH
VDD_HIGH_IN2
V
V
Must match the range of voltages
that the rechargeable backup
battery supports.
internal regulator
Backup battery
supply range
VDD_SNVS_IN3
—
2.40
—
3.6
Can be combined with
VDDHIGH_IN, if the system does
not require keeping real time and
other data on OFF state.
USB supply
voltages
USB_OTG1_VBUS —
4.40
3.0
—
5.5
3.6
V
V
—
A/D converter
VDDA_ADC_3P3
—
3.3
VDDA_ADC_3P3 must be
powered even if the ADC is not
used.
VDDA_ADC_3P3 cannot be
powered when the other SoC
supplies (except VDD_SNVS_IN)
are off.
Temperature Operating Ranges
Junction
temperature
Tj
Standard
Commercial
0
—
95
oC
See the application note, i.MX
RT1010 Product Lifetime Usage
Estimates for information on
product lifetime (power-on years)
for this processor.
1
2
3
Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set
point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio.
Applying the maximum voltage results in shorten lifetime. 3.6 V usage limited to < 1% of the use profile. Reset of profile limited
to below 3.49 V.
In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX RT1010 Hardware
Development Guide (IMXRT1010HDG).
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Electrical characteristics
4.1.4
External clock sources
Each i.MX RT1010 processor has two external input system clocks: a low frequency (RTC_XTALI) and
a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, slow system and watch-dog counters. The clock input can be
connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is
an internal ring oscillator, which can be used instead of the RTC_XTALI if accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either external oscillator or a crystal using internal
oscillator amplifier.
Table 10 shows the interface frequency requirements.
Table 10. External input clock frequency
Parameter Description
Symbol
Min
Typ
Max
Unit
RTC_XTALI Oscillator1,2
XTALI Oscillator2,4
fckil
fxtal
—
—
32.7683/32.0
24
—
—
kHz
MHz
1
External oscillator or a crystal with internal oscillator amplifier.
2
The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware
Development Guide for i.MX RT1010 Crossover Processors (IMXRT1010HDG).
3
4
Recommended nominal frequency 32.768 kHz.
External oscillator or a fundamental frequency crystal with internal oscillator amplifier.
The typical values shown in Table 10 are required for use with NXP SDK to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available.
•
External crystal oscillator with on-chip support circuit:
— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
— Higher accuracy than ring oscillator
— If no external crystal is present, then the ring oscillator is utilized
The decision of choosing a clock source should be taken based on real-time clock use and precision
time-out.
4.1.5
Maximum supply currents
The data shown in Table 11 represent a use case designed specifically to show the maximum current
consumption possible. All cores are running at the defined maximum frequency and are limited to L1
cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited
practical use case, if at all, and be limited to an extremely low duty cycle unless the intention was to
specifically show the worst case power consumption.
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NXP Semiconductors
Electrical characteristics
See the i.MX RT1010 Power Consumption Measurement Application Note for more details on typical
power consumption under various use case definitions.
Table 11. Maximum supply currents
Power Rail
Conditions
Max Current
Unit
DCDC_IN
Max power for chip at 125 oC
Include internal loading in analog
—
200
75
mA
mA
A
VDD_HIGH_IN
VDD_SNVS_IN
57.5
25
USB_OTG1_VBUS
VDDA_ADC_3P3
25 mA for each active USB interface
mA
mA
3.3 V power supply for 12-bit ADC, 600 34.5
A typical, 750 A max, for each ADC.
100 Ohm max loading for touch panel,
cause 33 mA current.
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Electrical characteristics
4.1.6
Low power mode supply currents
Table 12 shows the current core consumption (not including I/O) of i.MX RT1010 processors in selected
low power modes.
Table 12. Low power mode current and power consumption
Mode
Test Conditions
Supply
Typical1
2.09
Units
mA
SYSTEM IDLE
• SOC_VDD_IN set to 1.1 V for SOG and ARM
• CPU in WFI, CPU clock gated
• 24 MHz XTAL is ON
• System PLL is active, other PLLs are power down
• Peripheral clock gated, but remain powered
DCDC_IN (3.3 V)
VDD_HIGH_IN (3.3 V)
VDD_SNVS_IN (3.3 V)
Total
6.58
0.019
28.67
0.778
0.245
0.042
3.51
0.10
0.02
0.015
0.45
0
mW
mA
LOW POWER IDLE
• SOC_VDD_IN set to Weak mode
• CPU in Power Gate mode
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC used as
clock source
DCDC_IN (3.3 V)
VDD_HIGH_IN (3.3 V)
VDD_SNVS_IN (3.3 V)
Total
mW
mA
• Peripheral are powered off
SUSPEND
(DSM)
• SOC_VDD_IN is shut off
• CPU in Power Gate mode
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC is off
• All clocks are shut off, except 32 kHz RTC
• Peripheral are powered off
DCDC_IN (3.3 V)
VDD_HIGH_IN (3.3 V)
VDD_SNVS_IN (3.3 V)
Total
mW
mA
SNVS (RTC)
• All SOC digital logic, analog module are shut off DCDC_IN (0 V)
• 32 kHz RTC is alive
VDD_HIGH_IN (0 V)
0
VDD_SNVS_IN (3.3 V)
Total
0.015
0.05
mW
1
The typical values shown here are for information only and are not guaranteed. These values are average values measured
on a typical process wafer at 25oC.
4.1.7
USB PHY current consumption
Power down mode
4.1.7.1
In power down mode, everything is powered down, including the USB VBUS valid detectors in typical
condition. Table 13 shows the USB interface current consumption in power down mode.
Table 13. USB PHY current consumption in power down mode
VDD_USB_CAP (3.0 V)
5.1 A
VDD_HIGH_CAP (2.5 V)
1.7 A
NVCC_PLL (1.1 V)
< 0.5 A
Current
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Electrical characteristics
NOTE
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were
identified to be the voltage divider circuits in the USB-specific level
shifters.
4.2
System power and clocks
This section provide the information about the system power and clocks.
4.2.1
Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
•
•
•
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the processor (worst-case scenario)
Power On
Run Mode <-> Standby Mode
Run Mode <-> SNVS Mode
TSNVSDly
VDD_SNVS_IN
VDD_SNVS_CAP
DCDC_IN
VDD_HIGH_CAP
NVCC_PLL
POR_B
PMIC_ON_REQ
PMIC_STBY_REQ
DCDC_PSWITCH
ON_OFF
TStbyExt
1ms
1ms
VDD_SOC_IN
DCDC_OK
TDCDCSetup
DCDC_LP power rail
DCDC_IN power rail
VDD_SNVS_IN power rail
VDD_SNVS_CAP power rail
Signal Floating
VDD_SOC power rail
VDDA_2P5_CAP power rail
VDDA_1P1_CAP power rail
LEGEND
Signal in VDD_SOC power
domain
Signal in DCDC_IN power
domain
Signal in VDD_SNVS_CAP
power domain
Figure 3. Power sequence
4.2.1.1
Power-up sequence
The below restrictions must be followed:
•
•
•
•
VDD_SNVS_IN supply must be turned on before any other power supply or be connected
(shorted) with VDD_HIGH_IN supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other
supply is switched on.
When internal DCDC is enabled, external delay circuit is required to delay the
“DCDC_PSWITCH” signal at least 1 ms after DCDC_IN is stable.
POR_B should be held low during the entire power up sequence.
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Electrical characteristics
NOTE
The POR_B input (if used) must be immediately asserted at power-up and
remain asserted until after the last power rail reaches its working voltage. In
the absence of an external reset feeding the POR_B input, the internal POR
module takes control. It is recommended to reset IC. See the i.MX RT1010
Reference Manual (IMXRT1010RM) for further details and to ensure that
all necessary requirements are being met.
NOTE
Need to ensure that there is no back voltage (leakage) from any supply on
the board towards the 3.3 V supply (for example, from the external
components that use the 3.3 V supply).
NOTE
USB_OTG1_VBUS and VDDA_ADC_3P3 are not part of the power
supply sequence and may be powered at any time.
4.2.1.2
Power-down sequence
The following restrictions must be followed:
•
VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted)
with VDD_HIGH_IN supply.
•
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply
is switched off.
4.2.1.3
Power supplies usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.
This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O
power supply of each pin, see “Power Rail” columns in pin list tables of Section 6, "Package information
and contact assignments".”
4.2.2
Integrated LDO voltage regulator parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins
named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use
only and should not be used to power any external circuitry. See the i.MX RT1010 Reference Manual
(IMXRT1010RM) for details on the power tree scheme.
NOTE
The *_CAP signals should not be powered externally. These signals are
intended for internal LDO operation only.
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Electrical characteristics
4.2.2.1
Digital regulators (LDO_SNVS)
There are one digital LDO regulator (“Digital”, because of the logic loads that they drive, not because of
their construction). The advantages of the regulator is to reduce the input supply variation because of its
input supply ripple rejection and its on-die trimming. This translates into more stable voltage for the
on-chip logics.
The regulator has two basic modes:
•
Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.
The analog part of the regulator is powered down here limiting the power consumption.
•
Analog regulation mode. The regulation FET is controlled such that the output voltage of the
regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV
steps.
For additional information, see the i.MX RT1010 Reference Manual (IMXRT1010RM).
4.2.2.2
Regulators for analog modules
LDO_1P1
4.2.2.2.1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V
to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, and PLLs. A
programmable brown-out detector is included in the regulator that can be used by the system to determine
when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting
can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can
also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1010 Crossover Processors (IMXRT1010HDG).
For additional information, see the i.MX RT1010 Reference Manual (IMXRT1010RM).
4.2.2.2.2
LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is 2.25 V
to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the USB PHY, E-fuse module, and
PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to
determine when the load capability of the regulator is being exceeded, to take the necessary steps.
Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.
Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased
low-precision weak-regulator is included that can be enabled for applications needing to keep the output
voltage alive during low-power modes where the main regulator driver and its associated global bandgap
reference module are disabled. The output of the weak-regulator is not programmable and is a function of
the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output
is 2.525 V and its output impedance is approximately 40 .
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Electrical characteristics
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1010 Crossover Processors (IMXRT1010HDG).
For additional information, see the i.MX RT1010 Reference Manual (IMXRT1010RM).
4.2.2.2.3
LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB
voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector
is included in the regulator that can be used by the system to determine when the load capability of the
regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows
the user to select to run the regulator from either USB VBUS supply, when both are present. If only one
of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit
is also included to help the system meet in-rush current targets.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1010 Crossover Processors (IMXRT1010HDG).
For additional information, see the i.MX RT1010 Reference Manual (IMXRT1010RM).
4.2.2.2.4
DCDC
DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During
the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a
minimum quiescent current to maintain high efficiency.
DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold,
DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly
detect the current loading.
DCDC also includes the following protection functions:
•
Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in
the P-type power switch. In power save mode, DCDC stop charging inductor when detecting large
current in the P-type power switch. The threshold is also different in run mode and in power save
mode: the former is 1 A–2A, and the latter is 200 mA–250 mA.
•
•
Over voltage protection. DCDC shuts down when detecting the output voltage is too high.
Low voltage detection. DCDC shuts down when detecting the input voltage is too low.
NOTE
It is recommended that using the internal DCDC as core supply for cost
solution.
If the DCDC bypass mode is used, it is not recommended to switch back to
the internal DCDC mode.
For additional information, see the i.MX RT1010 Reference Manual (IMXRT1010RM).
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Electrical characteristics
4.2.3
PLL’s electrical characteristics
This section provides PLL electrical characteristics.
4.2.3.1
Audio PLL’s electrical parameters
Table 14. Audio PLL’s electrical parameters
Parameter
Value
Clock output range
Reference clock
Lock time
650 MHz ~1.3 GHz
24 MHz
< 11250 reference cycles
4.2.3.2
System PLL
Table 15. System PLL’s electrical parameters
Parameter
Value
Value
Value
Clock output range
Reference clock
Lock time
528 MHz PLL output
24 MHz
< 11250 reference cycles
4.2.3.3
Ethernet PLL
Table 16. Ethernet PLL’s electrical parameters
Parameter
Clock output range
Reference clock
Lock time
1 GHz
24 MHz
< 11250 reference cycles
4.2.3.4
USB PLL
Table 17. USB PLL’s electrical parameters
Parameter
Clock output range
Reference clock
Lock time
480 MHz PLL output
24 MHz
< 383 reference cycles
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Electrical characteristics
4.2.4
On-chip oscillators
4.2.4.1
OSC24M
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.2.4.2
OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement a low power oscillator. It also implements a power mux such that it can be powered
from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes
power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when
VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K
will automatically switch to a crude internal ring oscillator. The frequency range of this block is
approximately 10–45 kHz. It highly depends on the process, voltage, and temperature.
The OSC32k runs from VDD_SNVS_CAP supply, which comes from the
VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type
is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when
connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For
example, for Panasonic ML621:
•
•
Average Discharge Voltage is 2.5 V
Maximum Charge Current is 0.6 mA
For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.
Table 18. OSC32K main characteristics
Min
Typ
Max Comments
Fosc
—
32.768 KHz
—
—
This frequency is nominal and determined mainly by the crystal selected.
32.0 K would work as well.
Current consumption
—
4 A
The 4 A is the consumption of the oscillator alone (OSC32k). Total supply
consumption will depend on what the digital portion of the RTC consumes.
The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A
when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc in
the power_detect block. So, the total current is 6.5 A on vdd_rtc when the
ring oscillator is not running.
Bias resistor
—
14 M
—
This integrated bias resistor sets the amplifier into a high gain state. Any
leakage through the ESD network, external board leakage, or even a
scope probe that is significant relative to this value will debias the amp. The
debiasing will result in low gain, and will impact the circuit's ability to start
up and maintain oscillations.
Crystal Properties
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Electrical characteristics
Table 18. OSC32K main characteristics
Max Comments
Min
Typ
10 pF
Cload
—
—
Usually crystals can be purchased tuned for different Cloads. This Cload
value is typically 1/2 of the capacitances realized on the PCB on either side
of the quartz. A higher Cload will decrease oscillation margin, but
increases current oscillating through the crystal.
ESR
—
50 k
100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher
value will decrease the oscillating margin.
4.3
I/O parameters
This section provide parameters on I/O interfaces.
4.3.1
I/O DC parameters
This section includes the DC parameters of the following I/O types:
•
•
XTALI and RTC_XTALI (Clock Inputs) DC Parameters
General Purpose I/O (GPIO)
NOTE
The term ‘NVCC_XXXX’in this section refers to the associated supply rail
of an input or output.
Figure 4. Circuit for parameters Voh and Vol for I/O cells
4.3.1.1
XTALI and RTC_XTALI (clock inputs) DC parameters
Table 19 shows the DC parameters for the clock inputs.
1
Table 19. XTALI and RTC_XTALI DC parameters
Symbol Test Conditions Min
Parameter
Max
Unit
XTALI high-level DC input voltage
XTALI low-level DC input voltage
Vih
Vil
—
—
0.8 x NVCC_PLL
0
NVCC_PLL
0.2
V
V
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Electrical characteristics
1
Table 19. XTALI and RTC_XTALI DC parameters (continued)
Parameter
Symbol Test Conditions
Min
Max
Unit
RTC_XTALI high-level DC input voltage
Vih
Vil
—
—
0.8 x NVCC_PLL
0
NVCC_PLL
0.2
V
V
RTC_XTALI low-level DC input voltage
1
The DC parameters are for external clock input only.
4.3.1.2
Single voltage general purpose I/O (GPIO) DC parameters
Table 20 shows DC parameters for GPIO pads. The parameters in Table 20 are guaranteed per the
operating ranges in Table 9, unless otherwise noted.
Table 20. Single voltage GPIO DC parameters
Parameter
Symbol
VOH
Test Conditions
Min
Max
Units
High-level output voltage1
Ioh= -0.1mA (ipp_dse=001,010) NVCC_XXXX -
–
V
Ioh= -1mA
(ipp_dse=011,100,101,110,111)
0.2
–
Low-level output voltage1
VOL
Iol= 0.1mA (ipp_dse=001,010)
Iol= 1mA
0.2
V
(ipp_dse=011,100,101,110,111)
High-Level input voltage1,2
Low-Level input voltage1,2
VIH
VIL
—
—
0.7 x
NVCC_XXXX
NVCC_XXXX
V
0
0.3 x
V
NVCC_XXXX
Input Hysteresis
(NVCC_XXXX=3.3V)
VHYS_High NVCC_XXXX=3.3V
VDD
250
—
mV
mV
mV
Schmitt trigger VT+2,3
Schmitt trigger VT-2,3
VTH+
—
0.5 x
NVCC_XXXX
—
VTH-
—
—
0.5 x
NVCC_XXXX
Pull-up resistor (22_k PU)
Pull-up resistor (22_k PU)
Pull-up resistor (47_k PU)
Pull-up resistor (47_k PU)
Pull-up resistor (100_k PU)
Pull-up resistor (100_k PU)
RPU_22K
RPU_22K
RPU_47K
RPU_47K
Vin=0V
—
—
—
—
—
—
—
—
-1
212
1
A
A
A
A
A
A
A
A
A
k
Vin=NVCC_XXXX
Vin=0V
100
1
Vin=NVCC_XXXX
RPU_100K Vin=0V
48
1
RPU_100K Vin=NVCC_XXXX
Pull-down resistor (100_k PD) RPD_100K Vin=NVCC_XXXX
Pull-down resistor (100_k PD) RPD_100K Vin=0V
48
1
Input current (no PU/PD)
Keeper Circuit Resistance
IIN
VI = 0, VI = NVCC_XXXX
1
R_Keeper
VI =0.3 x NVCC_XXXX, VI = 0.7 105
x NVCC_XXXX
175
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Electrical characteristics
1
Overshoot and undershoot conditions (transitions above NVCC_XXXX and below GND) on switching pads must be held
below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/
undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line
termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage
to the device.
2
3
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4.3.2
I/O AC parameters
This section includes the AC parameters of the following I/O types:
General Purpose I/O (GPIO)
Figure 5 shows load circuit for output, and Figure 6 show the output transition time waveform.
•
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 5. Load circuit for output
OVDD
0 V
80%
20%
80%
20%
tr
Output (at pad)
tf
Figure 6. Output transition time waveform
4.3.2.1
General purpose I/O AC parameters
The I/O AC parameters for GPIO are presented in the Table 21, respectively. Note that the fast or slow I/O
behavior is determined by the appropriate control bits in the IOMUXC control registers.
Table 21. General purpose I/O AC parameters 3.3 V mode
Parameter
Symbol
Test condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall tr, tf
(Max Drive, ipp_dse=101)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
1.70/1.79
1.06/1.15
—
—
Output Pad Transition Times, rise/fall tr, tf
(High Drive, ipp_dse=011)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
2.35/2.43
1.74/1.77
—
—
—
—
ns
Output Pad Transition Times, rise/fall tr, tf
(Medium Drive, ipp_dse=010)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.13/3.29
2.46/2.60
Output Pad Transition Times, rise/fall tr, tf
(Low Drive. ipp_dse=001)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
5.14/5.57
4.77/5.15
—
—
—
—
ns
ns
Input Transition Times1
trm
—
25
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Electrical characteristics
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
4.4
System modules
This section contains the timing and electrical parameters for the modules in the i.MX RT1010 processor.
4.4.1
Reset timings parameters
Figure 7 shows the reset timing and Table 22 lists the timing parameters.
POR_B
(Input)
CC1
Figure 7. Reset timing diagram
Table 22. Reset timing parameters
ID
CC1
Parameter
Min Max
Unit
Duration of POR_B to be qualified as valid.
1
—
RTC_XTALI cycle
4.4.2
WDOG reset timing parameters
Figure 8 shows the WDOG reset timing and Table 23 lists the timing parameters.
WDOGn_B
(Output)
CC3
Figure 8. WDOGn_B timing diagram
Table 23. WDOGn_B timing parameters
ID
CC3
Parameter
Duration of WDOGn_B Assertion
Min
Max
Unit
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOGn_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
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Electrical characteristics
4.4.3
Secure JTAG Controller (SJC) timing parameters
Figure 9 depicts the SJC test clock input timing. Figure 10 depicts the SJC boundary scan timing.
Figure 11 depicts the SJC test access port. Signal parameters are listed in Table 24.
SJ1
SJ2
SJ2
JTAG_TCK
(Input)
VM
VM
VIH
VIL
SJ3
SJ3
Figure 9. Test clock input timing diagram
JTAG_TCK
(Input)
VIH
SJ5
VIL
SJ4
Input Data Valid
Data
Inputs
SJ6
Data
Outputs
Output Data Valid
SJ7
SJ6
Data
Outputs
Data
Outputs
Output Data Valid
Figure 10. Boundary secure (JTAG) timing diagram
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Electrical characteristics
JTAG_TCK
(Input)
VIH
SJ9
VIL
SJ8
Input Data Valid
JTAG_TDI
JTAG_TMS
(Input)
SJ10
SJ11
SJ10
JTAG_TDO
(Output)
Output Data Valid
JTAG_TDO
(Output)
JTAG_TDO
(Output)
Output Data Valid
Figure 11. Test access port timing diagram
JTAG_TCK
(Input)
SJ13
JTAG_TRST_B
(Input)
SJ12
Figure 12. JTAG_TRST_B timing diagram
Table 24. JTAG timing
All frequencies
Min Max
ID
Parameter1,2
Unit
1
SJ0
JTAG_TCK frequency of operation 1/(3•TDC
)
0.001
45
22.5
—
22
—
—
3
MHz
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
SJ8
JTAG_TCK cycle time in crystal mode
ns
ns
ns
ns
ns
ns
ns
ns
2
JTAG_TCK clock pulse width measured at VM
JTAG_TCK rise and fall times
Boundary scan input data set-up time
Boundary scan input data hold time
JTAG_TCK low to output data valid
JTAG_TCK low to output high impedance
JTAG_TMS, JTAG_TDI data set-up time
5
—
—
40
40
—
24
—
—
5
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Electrical characteristics
Table 24. JTAG timing (continued)
Parameter1,2
All frequencies
Min Max
ID
Unit
SJ9
JTAG_TMS, JTAG_TDI data hold time
JTAG_TCK low to JTAG_TDO data valid
JTAG_TCK low to JTAG_TDO high impedance
JTAG_TRST_B assert time
25
—
—
44
44
—
—
ns
SJ10
SJ11
SJ12
SJ13
ns
ns
ns
ns
—
100
40
JTAG_TRST_B set-up time to JTAG_TCK low
= target frequency of SJC
1
T
DC
2
VM = mid-point voltage
4.4.4
Debug trace timing specifications
Table 25. Debug trace operating behaviors
Symbol
Description
Min
Max
Unit
T1
T2
T3
T4
T5
T6
T7
T8
ARM_TRACE_CLK frequency of operation
ARM_TRACE_CLK period
Low pulse width
—
1/T1
6
70
—
—
—
1
MHz
s
ns
High pulse width
6
ns
Clock and data rise time
Clock and data fall time
Data setup
—
—
2
ns
1
ns
—
—
ns
Data hold
0.7
ns
!2-?42!#%?#,+
4ꢀ
T6
T4
4ꢂ
4ꢁ
Figure 13. ARM_TRACE_CLK specifications
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Electrical characteristics
ARM_TRACE_CLK
ARM_TRACE0-3
T7
T8
T7
T8
Figure 14. Trace data specifications
4.4.5
Power mode transition operating behaviors
Table 26 shows the power mode transition operating behaviors.
1
Table 26. Power mode transition operating behaviors
Core, memory
frequency (MHz)
Description
System clock
Min.
Typ.2
Max.
Unit
SUSPEND to RUN3
ENET PLL
0, 0 ->500, 500
—
532.04
—
s
1
2
3
Typical value is the average value of total test.
The temperature is at 25oC.
The code runs in the ITCM.
4.5
External memory interface
The following sections provide information about external memory interfaces.
4.5.1
FlexSPI parameters
Measurements are with a load 15 pf and input slew rate of 1 V/ns.
4.5.1.1
FlexSPI input/read timing
There are three sources for the internal sample clock for FlexSPI read data:
• Dummy read strobe generated by FlexSPI controller and looped back internally
(FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through the
DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1)
• Read strobe provided by memory device and input from DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x3)
The following sections describe input signal timing for each of these four internal sample clock sources.
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Electrical characteristics
4.5.1.1.1
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 27. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
—
8.67
0
60
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
ns
Table 28. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
—
2
133
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
1
—
ns
SCK
SIO[0:7]
TIS
TIH
TIS
TIH
Internal Sample Clock
Figure 15. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge, and FlexSPI controller sampling read data on the falling edge.
4.5.1.1.2
SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in SDR mode:
• A1–Memory generates both read data and read strobe on SCK rising edge (or falling
edge)
• A2–Memory generates read data on SCK falling edge and generates read strobe on
SCK rising edgeSCK rising edge
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Table 29. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)
Value
Symbol
Parameter
Unit
Min
Max
—
Frequency of operation
—
—
—
-2
133
—
—
2
MHz
ns
TSCKD
Time from SCK to data valid
Time from SCK to DQS
TSCKDQS
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
ns
SCK
TSCKD
TSCKD
SIO[0:7]
TSCKDQS
TSCKDQS
DQS
Figure 16. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A1)
NOTE
Timing shown is based on the memory generating read data and read strobe
on the SCK rising edge. The FlexSPI controller samples read data on the
DQS falling edge.
Table 30. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)
Value
Symbol
Parameter
Unit
Min
Max
—
Frequency of operation
—
—
—
-2
133
—
—
2
MHz
ns
TSCKD
Time from SCK to data valid
Time from SCK to DQS
TSCKDQS
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
ns
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SCK
TSCKD
TSCKD
TSCKD
SIO[0:7]
TSCKDQS
TSCKDQS
TSCKDQS
DQS
Internal Sample Clock
Figure 17. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half cycle delayed DQS falling edge.
4.5.1.1.3
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 31. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
—
8.67
0
30
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
ns
Table 32. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
—
2
66
—
—
MHz
ns
TIS
TIH
Setup time for incoming data
Hold time for incoming data
1
ns
SCLK
TIS
TIH
TIS
TIH
SIO[0:7]
Internal Sample Clock
Figure 18. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
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Electrical characteristics
4.5.1.1.4
DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in DDR mode:
• B1–Memory generates both read data and read strobe on SCK edge
• B2–Memory generates read data on SCK edge and generates read strobe on SCK2
edge
Table 33. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
—
—
—
-1
133
—
—
1
MHz
ns
TSCKD
Time from SCK to data valid
Time from SCK to DQS
TSCKDQS
ns
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
ns
SCK
TSCKD
SIO[0:7]
TSCKDQS
DQS
Figure 19. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)
Table 34. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)
Symbol
Parameter
Frequency of operation
Min
Max
Unit
—
—
—
-1
133
—
1
MHz
ns
TSCKD
Time from SCK to data valid
TSCKD - TSCKDQS
Time delta between TSCKD and TSCKDQS
ns
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Electrical characteristics
SCK
SIO[0:7]
SCK2
TSCKD
TSCK2DQS
DQS
Figure 20. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)
4.5.1.2
FlexSPI output/write timing
The following sections describe output signal timing for the FlexSPI controller including control signals
and data outputs.
4.5.1.2.1
SDR mode
Table 35. FlexSPI output timing in SDR mode
Symbol
Parameter
Min
Max
Unit
—
Frequency of operation
SCK clock period
—
6.0
1331
—
MHz
ns
Tck
TDVO
TDHO
TCSS
TCSH
Output data valid time
Output data hold time
Chip select output setup time
Chip select output hold time
—
1
ns
-1
—
ns
3 x TCK -1
3 x TCK + 2
—
ns
—
ns
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1010 Reference Manual (IMXRT1010RM) for more details.
SCK
TCSH
T
CSS
T
CK
CS
TDVO
TDVO
SIO[0:7]
TDHO
TDHO
Figure 21. FlexSPI output timing in SDR mode
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Electrical characteristics
4.5.1.2.2
DDR mode
Table 36. FlexSPI output timing in DDR mode
Symbol
Parameter
Frequency of operation1
Min
Max
Unit
—
—
133
—
MHz
ns
Tck
SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
Output data valid time
6.0
—
TDVO
TDHO
TCSS
TCSH
2.2
—
ns
Output data hold time
0.8
ns
Chip select output setup time
Chip select output hold time
3 x TCK / 2 - 0.7
3 x TCK / 2 + 0.8
—
ns
—
ns
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1010 Reference Manual (IMXRT1010RM) for more details.
SCK
T
CSS
T
CK
TCSH
CS
TDVO
TDVO
SIO[0:7]
TDHO
TDHO
Figure 22. FlexSPI output timing in DDR mode
4.6
Audio
This section provide information about SAI/I2S and SPDIF.
4.6.1
SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
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Table 37. Master mode SAI timing
Characteristic Min
Num
Max
Unit
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
SAI_MCLK cycle time
2 x tsys
40%
4 x tsys
40%
—
—
ns
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
60%
—
MCLK period
ns
SAI_BCLK pulse width high/low
SAI_BCLK to SAI_FS output valid
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
60%
15
BCLK period
ns
ns
ns
ns
ns
ns
0
—
—
15
SAI_BCLK to SAI_TXD invalid
SAI_RXD/SAI_FS input setup before SAI_BCLK
SAI_RXD/SAI_FS input hold after SAI_BCLK
0
—
15
—
0
—
Figure 23. SAI timing—master modes
Table 38. Slave mode SAI timing
Num
Characteristic
SAI_BCLK cycle time (input)
Min
4 x tsys
Max
Unit
S11
S12
S13
S14
S15
S16
—
ns
SAI_BCLK pulse width high/low (input)
SAI_FS input setup before SAI_BCLK
SAI_FA input hold after SAI_BCLK
40%
10
2
60%
—
BCLK period
ns
ns
ns
ns
—
SAI_BCLK to SAI_TXD/SAI_FS output valid
SAI_BCLK to SAI_TXD/SAI_FS output invalid
—
0
20
—
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Electrical characteristics
Num
Table 38. Slave mode SAI timing
Characteristic Min
Max
Unit
S17
S18
SAI_RXD setup before SAI_BCLK
SAI_RXD hold after SAI_BCLK
10
2
—
—
ns
ns
Figure 24. SAI timing—slave modes
4.6.2
SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 39 and Figure 25 and Figure 26 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 39. SPDIF timing parameters
Timing parameter range
Characteristics
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
ns
SPDIF_OUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
SPDIF_OUT1 output (Load = 30pf)
• Skew
• Transition rising
—
—
—
ns
ns
—
—
—
1.5
13.6
18.0
• Transition falling
Modulating Rx clock (SPDIF_SR_CLK) period
srckp
40.0
—
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Electrical characteristics
Table 39. SPDIF timing parameters (continued)
Timing parameter range
Min Max
Characteristics
Symbol
Unit
SPDIF_SR_CLK high period
srckph
srckpl
stclkp
stclkph
stclkpl
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
ns
ns
ns
ns
ns
SPDIF_SR_CLK low period
Modulating Tx clock (SPDIF_ST_CLK) period
SPDIF_ST_CLK high period
SPDIF_ST_CLK low period
srckp
srckpl
VM
srckph
VM
SPDIF_SR_CLK
(Output)
Figure 25. SPDIF_SR_CLK timing diagram
stclkp
stclkpl
VM
stclkph
VM
SPDIF_ST_CLK
(Input)
Figure 26. SPDIF_ST_CLK timing diagram
4.7
Analog
The following sections provide information about analog interfaces.
4.7.1
DCDC
Table 40 introduces the DCDC electrical specification.
Table 40. DCDC electrical specifications
Buck mode only, one output
3.3 V
Mode
Notes
Input voltage
Output voltage
Max loading
± 10%
1.1 V
Configurable 0.8 ~ 1.575 with 25 mV one step
500 mA
—
Loading in low power modes
Efficiency
200 A ~ 30 mA
90% max
—
@150 mA
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Electrical characteristics
Mode
Table 40. DCDC electrical specifications (continued)
Buck mode only, one output
Notes
Low power mode
Run mode
Open loop mode
Ripple is about 15 mV
Configurable by register
• Always continuous mode
• Support discontinuous mode
Inductor
4.7 H
33 F
1.6 V
—
—
Capacitor
Over voltage protection
Detect VDDSOC, when the voltage is higher
than 1.6 V, shutdown DCDC.
Over Current protection
Low battery detection
1 A
Detect the peak current
• Run mode: when the current is larger than
1 A, shutdown DCDC.
• Stop mode: when the current is larger than
250 mA, stop charging the inductor.
2.6 V
Detect the battery, when battery is lower than
2.6 V, shutdown DCDC.
4.7.2
A/D converter
This section introduces information about A/D converter.
4.7.2.1
12-bit ADC electrical characteristics
The section provide information about 12-bit ADC electrical characteristics.
4.7.2.1.1
12-bit ADC operating conditions
Table 41. 12-bit ADC operating conditions
Typ1
Characteristic
Conditions
Absolute
Symb
Min
Max
Unit
Comment
Supply voltage
VDDA
3.0
-
3.6
V
—
—
Delta to VDD
(VDD-VDDA)2
VDDA
-100
0
100
mV
Ground voltage
Delta to VSS
VSSAD
-100
0
100
mV
—
(VSS-VSSAD)
Ref Voltage High
Ref Voltage Low
Input Voltage
—
VDDA
VSS
1.13
VSS
VSS
—
VDDA
VSS
—
VDDA
VSS
VDDA
2
V
—
—
—
—
—
—
—
—
V
—
VADIN
CADIN
RADIN
V
Input Capacitance
Input Resistance
8/10/12 bit modes
ADLPC=0, ADHSC=1
ADLPC=0, ADHSC=0
ADLPC=1, ADHSC=0
1.5
5
pF
—
7
kohms
kohms
kohms
—
12.5
25
15
—
30
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Electrical characteristics
Table 41. 12-bit ADC operating conditions (continued)
Characteristic
Conditions
Symb
RAS
Min
Typ1
Max
Unit
kohms
Comment
Analog Source
Resistance
12 bit mode fADCK
40MHz ADLSMP=0,
=
—
—
1
Tsamp=150
ns
ADSTS=10, ADHSC=1
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
ADC Conversion Clock ADLPC=0, ADHSC=1
fADCK
4
4
4
—
—
—
40
30
20
MHz
MHz
MHz
—
—
—
Frequency
12 bit mode
ADLPC=0, ADHSC=0
12 bit mode
ADLPC=1, ADHSC=0
12 bit mode
1
2
Typical values assume VDDAD = 3.0 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
DC potential differences
Figure 27. 12-bit ADC input impedance equivalency diagram
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Electrical characteristics
12-bit ADC characteristics
Table 42. 12-bit ADC characteristics (V
= V
, V
= V
)
SSAD
REFH
DDA
REFL
Characteristic
Conditions1
Symb
IDDA
Min
Typ2
Max
Unit
Comment
Supply Current
ADLPC=1,
ADHSC=0
—
250
350
400
0.01
—
µA
ADLSMP= 0,ADSTS
= 10, ADCO = 1
ADLPC=0,
ADHSC=0
ADLPC=0,
ADHSC=1
Supply Current
Stop, Reset, Module IDDA
Off
—
0.8
µA
—
ADC Asynchronous
Clock Source
ADHSC=0
ADHSC=1
fADACK
—
—
—
10
20
2
—
—
—
MHz
tADACK = 1/fADACK
Sample Cycles
ADLSMP=0,
ADSTS=00
Csamp
cycles
—
ADLSMP=0,
ADSTS=01
4
ADLSMP=0,
ADSTS=10
6
ADLSMP=0,
ADSTS=11
8
ADLSMP=1,
ADSTS=00
12
16
20
24
ADLSMP=1,
ADSTS=01
ADLSMP=1,
ADSTS=10
ADLSMP=1,
ADSTS=11
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Electrical characteristics
) (continued)
Table 42. 12-bit ADC characteristics (V
= V
, V
= V
REFL SSAD
REFH
DDA
Characteristic
Conditions1
Symb
Cconv
Min
Typ2
Max
Unit
cycles
Comment
Conversion Cycles
ADLSMP=0
—
28
30
32
34
38
42
46
50
—
—
ADSTS=00
ADLSMP=0
ADSTS=01
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
Conversion Time
ADLSMP=0
ADSTS=00
Tconv
—
0.7
—
µs
Fadc = 40 MHz
ADLSMP=0
ADSTS=01
0.75
0.8
ADLSMP=0
ADSTS=10
ADLSMP=0
ADSTS=11
0.85
0.95
1.05
1.15
1.25
ADLSMP=1
ADSTS=00
ADLSMP=1
ADSTS=01
ADLSMP=1
ADSTS=10
ADLSMP=1,
ADSTS=11
Total Unadjusted
Error
12 bit mode
10 bit mode
8 bit mode
TUE
DNL
—
—
—
3.4
1.5
1.2
—
—
—
LSB
1 LSB =
(VREFH
VREFL)/2
N
AVGE = 1, AVGS = 11
AVGE = 1, AVGS = 11
-
Differential
Non-Linearity
12 bit mode
10bit mode
8 bit mode
—
—
—
0.76
0.36
0.14
—
—
—
LSB
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Electrical characteristics
Table 42. 12-bit ADC characteristics (V
= V
, V
= V
) (continued)
Unit Comment
REFH
DDA
REFL
SSAD
Characteristic
Conditions1
Symb
INL
Min
Typ2
2.78
Max
Integral Non-Linearity 12 bit mode
10bit mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSB
AVGE = 1, AVGS = 11
AVGE = 1, AVGS = 11
AVGE = 1, AVGS = 11
0.61
8 bit mode
0.14
Zero-Scale Error
Full-Scale Error
12 bit mode
10bit mode
8 bit mode
12 bit mode
10bit mode
8 bit mode
EZS
-1.14
-0.25
-0.19
-1.06
-0.03
-0.02
10.7
LSB
LSB
EFS
Effective Number of 12 bit mode
Bits
ENOB
SINAD
10.1
Bits
dB
AVGE = 1, AVGS = 11
AVGE = 1, AVGS = 11
Signal to Noise plus See ENOB
Distortion
SINAD = 6.02 x ENOB + 1.76
1
2
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE
The ADC electrical spec is met with the calibration enabled configuration.
Figure 28. Minimum Sample Time Vs Ras (Cas = 2 pF)
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Electrical characteristics
Figure 29. Minimum Sample Time Vs Ras (Cas = 5 pF)
Figure 30. Minimum Sample Time Vs Ras (Cas = 10 pF)
4.8
Communication interfaces
The following sections provide the information about communication interfaces.
4.8.1
LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables provide timing
characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% V and 80% V thresholds, unless noted, as well as input
DD
DD
signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
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Electrical characteristics
Table 43. LPSPI Master mode timing
Number
Symbol
Description
Frequency of operation
Min.
Max.
Units
Note
1
1
2
3
4
5
6
7
8
9
fSCK
tSCK
tLead
tLag
tWSCK
tSU
—
fperiph / 2
MHz
µs
2
SCK period
2 x tperiph
—
—
—
—
—
—
8
Enable lead time
1
tperiph
tperiph
ns
—
—
—
—
—
—
—
Enable lag time
1
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SCK edge)
Data hold time (outputs)
tSCK / 2 - 3
10
2
ns
tHI
ns
tV
—
0
ns
tHO
—
ns
1
2
Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be
guaranteed this limit is not exceeded.
tperiph = 1000 / fperiph
1
PCS
(OUTPUT)
3
2
4
SCK
(CPOL=0)
(OUTPUT)
5
5
SCK
(CPOL=1)
(OUTPUT)
6
7
SIN
(INPUT)
2
LSB IN
BIT 6 . . . 1
8
MSB IN
9
SOUT
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 31. LPSPI Master mode timing (CPHA = 0)
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Electrical characteristics
1
PCS
(OUTPUT)
2
4
3
SCK
(CPOL=0)
(OUTPUT)
5
5
SCK
(CPOL=1)
(OUTPUT)
6
7
SIN
(INPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
9
8
MASTER MSB OUT2
SOUT
(OUTPUT)
PORT DATA
BIT 6 . . . 1
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 32. LPSPI Master mode timing (CPHA = 1)
s
Table 44. LPSPI Slave mode timing
Number
Symbol
Description
Frequency of operation
Min.
Max.
Units
Note
1
1
2
fSCK
tSCK
tLead
tLag
tWSCK
tSU
0
fperiph / 2
—
MHz
µs
2
SCK period
2 x tperiph
3
Enable lead time
1
—
tperiph
tperiph
ns
—
—
—
—
4
Enable lag time
1
—
5
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
tSCK / 2 - 5
—
6
2.7
3.8
—
—
—
0
—
ns
7
tHI
—
ns
—
3
8
ta
tperiph
tperiph
14.5
—
ns
4
9
tdis
Slave MISO disable time
Data valid (after SCK edge)
Data hold time (outputs)
ns
10
11
tV
ns
—
—
tHO
ns
1
Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be
guaranteed this limit is not exceeded.
2
3
4
tperiph = 1000 / fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
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Electrical characteristics
PCS
(INPUT)
2
4
SCK
(CPOL=0)
(INPUT)
5
5
3
SCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
SEE
NOTE
SIN
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
note
6
SOUT
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 33. LPSPI Slave mode timing (CPHA = 0)
PCS
(INPUT)
4
2
3
SCK
(CPOL=0)
(INPUT)
5
5
SCK
(CPOL=1)
(INPUT)
11
9
10
see
SIN
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE MSB OUT
SLAVE LSB OUT
LSB IN
note
(OUTPUT)
8
6
7
SOUT
(INPUT)
MSB IN
Figure 34. LPSPI Slave mode timing (CPHA = 1)
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Electrical characteristics
4.8.2
LPI2C module timing parameters
This section describes the timing parameters of the LPI2C module.
Table 45. LPI2C module timing parameters
Symbol
Description
Standard mode (Sm)
Min
Max
100
Unit
Notes
1, 2
fSCL
SCL clock frequency
0
0
0
0
0
kHz
Fast mode (Fm)
400
Fast mode Plus (Fm+)
Ultra Fast mode (UFm)
High speed mode (Hs-mode)
1000
5000
3400
1
Hs-mode is only supported in slave mode.
See General switching specifications.
2
4.8.3
LPUART electrical specifications
Please refer to Section 4.3.2.1, "General purpose I/O AC parameters".
4.8.4
USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG with the following amendments.
•
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
Battery Charging Specification (available from USB-IF)
•
•
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Electrical characteristics
— Revision 1.2, December 7, 2010
— Portable device only
4.9
Timers
This section provide information on timers.
4.9.1
Pulse Width Modulator (PWM) characteristics
This section describes the electrical information of the PWM.
Table 46. PWM timing parameters
Parameter
Symbo
Min
Typ
Max
Unit
PWM Clock Frequency
Power-up Time
—
—
—
—
132
—
MHz
tpu
25
s
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Boot mode configuration
5 Boot mode configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot mode configuration pins
Table 47 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1010
Fuse Map document and the System Boot chapter in i.MX RT1010 Reference Manual (IMXRT1010RM).
Table 47. Fuses and associated pins used for boot
Pad
GPIO_SD_04
Default setting on reset
eFuse name
Details
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
100 K pull-down
src.BOOT_MODE[0]
src.BOOT_MODE[1]
src.BT_CFG[0]
GPIO_SD_03
GPIO_SD_02
GPIO_SD_01
GPIO_SD_00
Boot Options, Pin value overrides fuse
settings for BT_FUSE_SEL = ‘0’.
Signal Configuration as Fuse Override
Input at Power Up.
src.BT_CFG[1]
src.BT_CFG[2]
These are special I/O lines that control
the boot up configuration during
product development. In production,
the boot configuration can be
controlled by fuses.
5.2
Boot device interface allocation
The following tables list the interfaces that can be used by the boot process in accordance with the specific
boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 48. Boot through FlexSPI
PAD Name
IO Function
flexspi.B_DATA[3]
Mux Mode
Comments
GPIO_SD_04
GPIO_SD_02
GPIO_SD_01
GPIO_SD_03
GPIO_SD_13
GPIO_00
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
—
—
—
flexspi.B_DATA[2]
flexspi.B_DATA[1]
flexspi.B_DATA[0]
flexspi.B_SCLK
flexspi.B_DQS
GPIO_SD_00
GPIO_SD_12
GPIO_SD_06
flexspi.B_SS0_B
flexspi.A_DQS
flexspi.A_SS0_B
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Boot mode configuration
PAD Name
Table 48. Boot through FlexSPI (continued)
IO Function Mux Mode
flexspi.A_SS1_B
Comments
GPIO_SD_05
GPIO_SD_10
GPIO_SD_09
GPIO_SD_07
GPIO_SD_08
GPIO_SD_11
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
ALT 0
—
—
—
—
—
—
flexspi.A_SCLK
flexspi.A_DATA[0]
flexspi.A_DATA[1]
flexspi.A_DATA[2]
flexspi.A_DATA[3]
Table 49. FlexSPI reset
PAD Name
IO Function
Mux Mode
Mux Mode
Comments
Comments
GPIO_13
gpiomux.IO[13]
ALT 5
—
Table 50. Boot through UART1
IO Function
PAD Name
GPIO_10
GPIO_09
GPIO_08
GPIO_07
lpuart1.TX
ALT 0
—
—
—
—
lpuart1.RX
ALT 0
ALT 6
ALT 6
lpuart1.CTS_B
lpuart1.RTS_B
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Package information and contact assignments
6 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
12 x 12 mm package information
12 x 12 mm, 0.5 mm pitch, ball matrix
6.1.1
Figure 35 shows the top, bottom, and side views of the 12 x 12 mm LQFP package.
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Package information and contact assignments
Figure 35. 12 x 12 mm LQFP, case x package top and side views
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Package information and contact assignments
6.1.2
12 x 12 mm supplies contact assignments and functional contact
assignments
Table 51 shows the device connection list for ground, sense, and reference contact signals.
Table 51. 12 x 12 mm supplies contact Assignment
Supply Rail Name
Pin(s) Position(s)
Remark
DCDC_IN
18
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DCDC_IN_Q
DCDC_GND
DCDC_LP
17
20
19
DCDC_PSWITCH
NGND_KEL0
15
34
NVCC_GPIO
7, 50, 63, 71
NVCC_PLL
40
VDDA_ADC_3P3
VDD_HIGH_CAP
VDD_HIGH_IN
VDD_SNVS_CAP
VDD_SNVS_IN
VDD_SOC_IN
VDD_USB_CAP
VSS
42
35
39
26
25
14, 53, 77
31
16, 54, 30, 78
41
VSSA_ADC_3P3
Table 52 shows an alpha-sorted list of functional contact assignments for the 12 x 12 mm package.
Table 52. 12 x 12 mm functional contact assignments
Default setting
on Reset
Default Setting
12 x 12
Pin
Power
Group
Pin
Type
Pin Name
Default
Mode
Default
Input/
Input/
Output
Value
Value
Function
Output
13
12
11
10
NVCC_GPIO Digital
GPIO
Alt 5
Alt 5
Alt 5
Alt 5
GPIOMUX_IO00
GPIOMUX_IO01
GPIOMUX_IO02
GPIOMUX_IO03
Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
100K PD
GPIO_00
NVCC_GPIO Digital
GPIO
Input
Input
Input
Keeper
Keeper
Keeper
GPIO_01
GPIO_02
GPIO_03
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
NXP Semiconductors
59
Package information and contact assignments
Table 52. 12 x 12 mm functional contact assignments (continued)
9
NVCC_GPIO Digital
GPIO
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 7
Alt 7
Alt 7
GPIOMUX_IO04
GPIOMUX_IO05
GPIOMUX_IO06
GPIOMUX_IO07
GPIOMUX_IO08
GPIOMUX_IO09
GPIOMUX_IO10
GPIOMUX_IO11
GPIOMUX_IO12
GPIOMUX_IO13
GPIOMUX_IO14
GPIOMUX_IO15
GPIOMUX_IO16
GPIOMUX_IO17
GPIOMUX_IO18
GPIOMUX_IO19
GPIOMUX_IO20
GPIOMUX_IO21
JTAG_TRSTB
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
GPIO_04
8
NVCC_GPIO Digital
GPIO
GPIO_05
6
NVCC_GPIO Digital
GPIO
GPIO_06
5
NVCC_GPIO Digital
GPIO
GPIO_07
4
NVCC_GPIO Digital
GPIO
GPIO_08
3
NVCC_GPIO Digital
GPIO
GPIO_09
2
NVCC_GPIO Digital
GPIO
GPIO_10
1
NVCC_GPIO Digital
GPIO
GPIO_11
80
79
60
59
58
57
56
55
52
51
49
48
47
NVCC_GPIO Digital
GPIO
GPIO_12
NVCC_GPIO Digital
GPIO
GPIO_13
NVCC_GPIO Digital
GPIO
GPIO_AD_00
GPIO_AD_01
GPIO_AD_02
GPIO_AD_03
GPIO_AD_04
GPIO_AD_05
GPIO_AD_06
GPIO_AD_07
GPIO_AD_08
GPIO_AD_09
GPIO_AD_10
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
Keeper Output1 Keeper
NVCC_GPIO Digital
GPIO
Keeper Input
Keeper Input
Keeper Input
47K PU Input
Keeper Input
47K PU Input
Keeper
Keeper
Keeper
47K PU
Keeper
47K PU
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
JTAG_TDO
NVCC_GPIO Digital
GPIO
JTAG_TDI
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
NXP Semiconductors
60
Package information and contact assignments
Table 52. 12 x 12 mm functional contact assignments (continued)
46
45
44
43
76
75
74
73
72
70
69
68
67
66
65
64
62
61
21
24
22
NVCC_GPIO Digital
GPIO
Alt 7
Alt 7
Alt 7
Alt 5
Alt 5
Alt 5
Alt 5
Alt 6
Alt 6
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 5
Alt 0
Alt 0
Alt 0
JTAG_MOD
Input
Input
Input
Input
Input
Input
Input
100K PD Input
100K PD Input
47K PU Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
100K PD Input
100K PD Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
Keeper Input
100K PU Input
100K PD
100K PD
47K PU
Keeper
GPIO_AD_11
GPIO_AD_12
GPIO_AD_13
GPIO_AD_14
GPIO_SD_00
GPIO_SD_01
GPIO_SD_02
GPIO_SD_03
GPIO_SD_04
GPIO_SD_05
GPIO_SD_06
GPIO_SD_07
GPIO_SD_08
GPIO_SD_09
GPIO_SD_10
GPIO_SD_11
GPIO_SD_12
GPIO_SD_13
ONOFF
NVCC_GPIO Digital
GPIO
JTAG_TCK
NVCC_GPIO Digital
GPIO
JTAG_TMS
NVCC_GPIO Digital
GPIO
GPIOMUX_IO28
GPIO2_IO00
GPIO2_IO01
GPIO2_IO02
NVCC_GPIO Digital
GPIO
100K PD
100K PD
100K PD
100K PD
100K PD
Keeper
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
NVCC_GPIO Digital
GPIO
SRC_BOOT_MOD Input
E1
NVCC_GPIO Digital
GPIO
SRC_BOOT_MOD Input
E0
NVCC_GPIO Digital
GPIO
GPIO2_IO05
GPIO2_IO06
GPIO2_IO07
GPIO2_IO08
GPIO2_IO09
GPIO2_IO10
GPIO2_IO11
GPIO2_IO12
GPIO2_IO13
SRC_RESET_B
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
NVCC_GPIO Digital
GPIO
Keeper
NVCC_GPIO Digital
GPIO
Keeper
NVCC_GPIO Digital
GPIO
Keeper
NVCC_GPIO Digital
GPIO
Keeper
NVCC_GPIO Digital
GPIO
Keeper
NVCC_GPIO Digital
GPIO
Keeper
NVCC_GPIO Digital
GPIO
Keeper
NVCC_GPIO Digital
GPIO
100K PD
100K PU
VDD_SNVS_I Digital
N
GPIO
VDD_SNVS_I Digital
SNVS_PMIC_ON_ Output 100K PU Output 100K PU
REQ
PMIC_ON_REQ
POR_B
N
GPIO
VDD_SNVS_I Digital
SRC_POR_B
Input
100K PU Input
100K PU
N
GPIO
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
NXP Semiconductors
61
Package information and contact assignments
Table 52. 12 x 12 mm functional contact assignments (continued)
27
28
23
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RTC_XTALI
RTC_XTALO
TEST_MODE
—
—
VDD_SNVS_I Digital
N
Alt 0
TCU_TEST_MOD Input
E
100K PD Input
100K PD
GPIO
36
—
—
—
—
—
—
—
—
USB_OTG1_CH
D_B
32
33
29
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_VB
US
37
38
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XTALI
XTALO
1
This pin output is in a high level until the system reset is complete.
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
NXP Semiconductors
62
Package information and contact assignments
6.1.3
12 x 12 mm package pin assignments
Figure 36 shows the pin assignments of the 12 x 12 mm package.
1
GPIO_11
GPIO_10
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GPIO_AD_00
2
GPIO_AD_01
3
GPIO_09
GPIO_AD_02
4
GPIO_08
GPIO_AD_03
5
GPIO_07
GPIO_AD_04
6
GPIO_06
GPIO_AD_05
7
NVCC_GPIO
GPIO_05
VSS
8
VDD_SOC_IN
GPIO_AD_06
9
GPIO_04
10
11
12
13
14
15
16
17
18
19
20
GPIO_03
GPIO_AD_07
GPIO_02
NVCC_GPIO
GPIO_01
GPIO_AD_08
GPIO_00
GPIO_AD_09
VDD_SOC_IN / DCDC_SENSE
DCDC_PSWITCH
VSS
GPIO_AD_10
GPIO_AD_11
GPIO_AD_12
DCDC_IN_Q
DCDC_IN
GPIO_AD_13
GPIO_AD_14
DCDC_LP
VDDA_ADC_3P3 / ADC_VREFH
VSSA_ADC_3P3 / ADC_VREFL
DCDC_GND
Figure 36. The pin assignments of the 12 x 12 mm package
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
NXP Semiconductors
63
Revision history
7 Revision history
Table 53 provides a revision history for this data sheet.
Table 53. i.MX RT1010 data sheet document revision history
Rev.
Number
Date
Substantive Change(s)
Rev. 0
09/2019 • Initial version
i.MX RT1010 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 09/2019
NXP Semiconductors
64
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Document Number: IMXRT1010CEC
© 2019 NXP B.V.
Rev. 0
09/2019
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