SCC2681TC1A44,512 [NXP]
SCC2681T - Dual asynchronous receiver/transmitter (DUART) LCC 44-Pin;
| 型号： | SCC2681TC1A44,512 |
| 厂家： | 
NXP |
| 描述： | SCC2681T - Dual asynchronous receiver/transmitter (DUART) LCC 44-Pin 通信 时钟 数据传输 外围集成电路 |
| 文件： | 总15页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SCC2681T
Dual asynchronous receiver/transmitter
(DUART)
Product data
2004 Apr 06
Philips
Semiconductors
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
DESCRIPTION
The Philips Semiconductors SCC2681 Dual Universal
• Programmable baud rate for each receiver and transmitter
selectable from:
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. The SCC2681T features a faster bus cycle time than the
standard SCC2681. The quick bus cycle eliminates or reduces the
need for wait states with fast CPUs and permits high throughput in
I/O intensive systems. Higher external clock rates may be used with
the transmitter, receiver and counter timer which in turn provide
greater versatility in baud rate generation. The SCC2681T interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system. It is manufactured in CMOS technology.
– 22 fixed rates: 50 to 115.2 k baud
– Non-standard rates to 115.2
– Non-standard user-defined rate derived from programmable
counter/timer
– External 1× or 16× clock
• Parity, framing, and overrun error detection
• False start bit detection
• Line break detection and generation
• Programmable channel mode
– Normal (full-duplex)
– Automatic echo
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16× clock derived from a programmable counter/timer,
or an external 1× or 16× clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
– Local loopback
– Remote loopback
• Multi-function programmable 16-bit counter/timer
• Multi-function 7-bit input port
– Can serve as clock or control inputs
– Change of state detection on four inputs
– 100 kΩ typical pull-up resistors
Each receiver is quadruple buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the receiver buffer is full.
• Multi-function 8-bit output port
– Individual bit set/reset capability
Also provided on the SCC2681T are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
– Outputs can be programmed to be status/interrupt/DMA signals
– Auto 485 turn-around
• Versatile interrupt system
– Single interrupt output with eight maskable interrupting
For a complete functional description and programming information
for the SCC2681T, refer to the SCC2681 product specification.
conditions
– Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
FEATURES
• Maximum data transfer rates:
– 1× – 1 MB/sec transmitter and receiver
• Fast bus cycle times reduce or eliminate CPU wait states
– 16× – 500 kB/sec receiver and 250 kB/sec transmitter
• Dual full-duplex asynchronous receiver/transmitters
• Quadruple buffered receiver data registers
• Automatic wake-up mode for multidrop applications
• Start-end break interrupt/status
• Programmable data format
– 5 to 8 data bits plus parity
• Detects break which originates in the middle of a character
• On-chip crystal oscillator
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
• Single +5 V power supply
• 16-bit programmable Counter/Timer
• Commercial temperature range
ORDERING INFORMATION
DESCRIPTION
V
CC
= +5 V ± 10%, T
= 0 °C to +70 °C
DWG #
amb
44-Pin Plastic Lead Chip Carrier (PLCC)
SCC2681TC1A44
SOT187-2
NOTE: For a full register description and programming information see the SCC2681.
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2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
BLOCK DIAGRAM
8
CHANNEL A
D0–D7
BUS BUFFER
TRANSMIT
TxDA
RxDA
HOLDING REG
TRANSMIT
SHIFT REGISTER
OPERATION CONTROL
RDN
RECEIVE
HOLDING REG (3)
WRN
CEN
ADDRESS
DECODE
4
RECEIVE
SHIFT REGISTER
A0–A3
RESET
R/W CONTROL
MRA1, 2
CRA
SRA
INTERRUPT CONTROL
TxDB
RxDB
INTRN
IMR
ISR
CHANNEL B
(AS ABOVE)
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
TIMING
7
IP0-IP6
BAUD RATE
GENERATOR
IPCR
ACR
CLOCK
SELECTORS
COUNTER/
TIMER
OUTPUT PORT
FUNCTION
SELECT LOGIC
8
OP0-OP7
X1/CLK
X2
XTAL OSC
OPCR
OPR
CSRA
CSRB
ACR
U
CTLR
CTLR
V
CC
GND
SD00099
Figure 1. Block Diagram
NOTE:
Refer to SCC2681 for functional description.
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2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
PIN CONFIGURATION
IP2 40
IP6 41
IP5 42
IP4 43
VCC 44
28 D0
27 D2
26 D4
25 D6
24 INTRN
23 n.c.
22 GND
21 D7
20 D5
19 D3
18 D1
SCC2681TC1A44
n.c.
A0
1
2
3
4
5
6
IP3
A1
IP1
A2
SD00737
Figure 2. Pin configuration
PIN DESCRIPTION
MNEMONIC
PIN
TYPE
NAME AND FUNCTION
D0–D7
21, 25, 20,
26, 19, 27,
18, 28
I/O
Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
CEN
39
I
Chip Enable: Active LOW input signal. When LOW, data transfers between the CPU and the DUART
are enabled on D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is HIGH, the
DUART places the D0–D7 lines in the three-state condition.
WRN
RDN
9
I
I
Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
10
Read Strobe: When low and CEN is also LOW, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
A0–A3
2, 4, 6, 7
38
I
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the
HIGH state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and
TxDB outputs in the mark (HIGH) state. Clears Test modes, sets MR pointer to MR1.
INTRN
24
36
O
I
Interrupt Request: Active-LOW, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
X1/CLK
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock
Timing.
X2
37
I
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
connected.
It must not be grounded.
RxDA
RxDB
35
11
I
I
Channel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’
is LOW.
Channel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’
is LOW.
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Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
MNEMONIC
PIN
TYPE
NAME AND FUNCTION
TxDA
33
O
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is HIGH, ‘space’ is LOW.
TxDB
13
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback
mode. ‘Mark’ is HIGH, ‘space’ is LOW.
OP0
OP1
OP2
OP3
OP4
OP5
32
14
31
15
30
16
O
O
O
O
O
O
Output 0: General purpose output, or channel A request to send (RTSAN, active-LOW). Can be
deactivated automatically on receive or transmit.
Output 1: General purpose output, or channel B request to send (RTSBN, active-LOW). Can be
deactivated automatically on receive or transmit.
Output 2: General purpose output, or channel A transmitter 1× or 16× clock output, or channel A
receiver 1× clock output.
Output 3: General purpose output, or open-drain, active-LOW counter/timer interrupt output, or channel
B transmitter 1× clock output, or channel B receiver 1× clock output.
Output 4: General purpose output, or channel A open-drain, active-LOW, RxRDYA/FFULLA interrupt
output.
Output 5: General purpose output, or channel B open-drain, active-LOW, RxRDYB/FFULLB interrupt
output.
OP6
OP7
IP0
29
17
8
O
O
I
Output 6: General purpose output, or channel A open-drain, active-LOW, TxRDYA interrupt output.
Output 7: General purpose output, or channel B open-drain, active-LOW TxRDYB interrupt output.
Input 0: General purpose input, or channel A clear to send active-LOW input (CTSAN). Pin has an
internal V pull-up device supplying 1 to 4 µA of current.
CC
IP1
IP2
IP3
5
40
3
I
I
I
Input 1: General purpose input, or channel B clear to send active-LOW input (CTSBN). Pin has an
internal V pull-up device supplying 1 to 4 µA of current.
CC
Input 2: General purpose input, or counter/timer external clock input. Pin has an internal V pull-up
CC
device supplying 1 to 4 µA of current.
Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has
an internal V pull-up device supplying 1 to 4 µA of current.
CC
IP4
IP5
IP6
43
42
41
I
I
I
Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V pull-up device supplying 1 to 4 µA of current.
CC
Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has
an internal V pull-up device supplying 1 to 4 µA of current.
CC
Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V pull-up device supplying 1 to 4 µA of current.
CC
V
44
22
I
I
Power Supply: +5 V supply input.
Ground
CC
GND
n.c.
1, 12, 23,
34
not connected
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2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
0 to +70
UNIT
°C
°C
V
2
T
Operating ambient temperature range
amb
T
stg
Storage temperature range
–65 to +150
–0.5 to +6.0
3
All voltages with respect to GND
Pin voltage range
V
SS
– 0.5 to V + 0.5
V
CC
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150 °C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
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Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
1, 2, 3
DC ELECTRICAL CHARACTERISTICS
T
= 0 °C to +70 °C; V = +5.0 V ± 10%
amb
CC
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Typ
Max
V
V
V
V
LOW-level input voltage
–
2.0
2.5
–
–
–
–
0.8
–
–
V
V
V
V
IL
HIGH-level input voltage (except X1/CLK)
HIGH-level input voltage (except X1/CLK)
HIGH-level input voltage (X1/CLK)
T
T
amb
≥ 0 °C
< 0 °C
IH
IH
IH
amb
0.8 V
–
CC
V
V
LOW-level output voltage
–
–
–
0.4
–
V
V
I
= 2.4 mA
OL
OL
4
HIGH-level output voltage (except open-drain outputs)
V
CC
– 0.5
I
= –400 µA
OH
OH
I
X1/CLK input current
–10
–
–
–
+10
0
75
µA
µA
µA
V
IN
= 0 V to V
CC
IX1
I
I
X1/CLK input LOW current – operating
X1/CLK input HIGH current – operating
V
IN
= 0 V
–75
0
ILX1
V
IN
= V
IHX1
CC
I
I
I
I
X2 output HIGH current – operating
0
–
–
–
–
+75
–1
0
µA
mA
µA
V
= V ; X1 = 0
OHX2
OUT
CC
X2 output HIGH short circuit current – operating
X2 output LOW current – operating
X2 output LOW short circuit current – operating
V
= 0 V; X1 = 0
= 0 V; X1 = V
CC
–10
–75
1
OHX2S
OLX2
OUT
V
OUT
V
OUT
= V ; X1 = V
CC
10
mA
OLX2S
CC
Input leakage current:
All except input port pins
Input port pins
I
I
V
V
= 0 V to V
= 0 V to V
–10
–20
–
–
+10
+10
µA
µA
IN
CC
IN
CC
I
I
Output off current HIGH, 3-state data bus
Output off current LOW, 3-state data bus
V
V
= V
CC
= 0 V
–
–10
–
–
10
–
µA
µA
OZH
IN
OZL
IN
I
I
Open-drain output LOW current in off-state
Open-drain output HIGH current in off-state
V
= 0 V
–10
–
–
–
–
10
µA
µA
ODL
IN
V
IN
= V
ODH
CC
5
Power supply current
I
CC
Operating mode
CMOS input levels
–
10
mA
–
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: C = 50 pF, R = 2.7 kΩ to V .
L
L
L
CC
5. All outputs are disconnected. Inputs are switching between CMOS levels of V – 0.2 V and V + 0.2 V.
CC
SS
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2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
1, 2, 3, 4
AC ELECTRICAL CHARACTERISTICS
LIMITS
Typ
SYMBOL
PARAMETER
UNIT
Max
Min
Reset timing (see Figure 3)
t
Reset pulse width
1.0
–
–
µs
RES
Bus timing (see Figure 4) (Note 5)
t
t
t
t
t
t
t
t
t
t
t
A0–A3 set-up to RDN and CEN, or WRN and CEN LOW
RDN and CEN, or WRN and CEN LOW to A0–A3 invalid
RDN and CEN LOW to RDN or CEN HIGH
0
100
120
110
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVEL
ELAX
RLRH
EHEL
RLDA
RLDV
RHDI
–
6, 7
CEN HIGH to CEN LOW
CEN and RDN LOW to data outputs active
CEN and RDN LOW to data valid
–
–
100
–
CEN or RDN HIGH to data invalid
10
–
75
35
15
CEN or RDN HIGH to data outputs floating
WRN and CEN LOW to WRN or CEN HIGH
Data input valid to WRN or CEN HIGH
WRN or CEN HIGH to data invalid
65
–
RHDF
WLWH
DVWH
WHDI
–
–
Port timing (see Figure 5)
t
t
t
Port input set-up time before RDN LOW
Port input hold time after RDN HIGH
Port output valid after WRN HIGH
0
0
–
–
–
–
–
–
200
ns
ns
ns
PS
PH
PD
Interrupt timing (see Figure 6)
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
–
–
–
–
–
–
–
–
–
–
–
–
200
200
200
200
200
200
ns
ns
ns
ns
ns
ns
t
IR
Clock timing (see Figure 7)
t
f
t
f
t
X1/CLK HIGH or LOW time
X1/CLK frequency
90
2
ns
MHz
ns
CLK
CLK
CTC
CTC
RX
4
8
CTCLK (IP2) HIGH or LOW time
55
0
8
CTCLK (IP2) frequency
MHz
ns
RxC HIGH or LOW time
55
0
8
RxC frequency
(16×)
3.6864
8
1
MHz
MHz
ns
f
RX
8
(1×)
0
t
f
TxC HIGH or LOW time
TxC frequency
110
0
TX
8
(16×)
4
1
MHz
MHz
TX
8
(1×)
0
Transmit timing (see Figure 8)
t
t
TxD output delay from TxC external clock input on IP pin
Output delay from TxC LOW at OP pin to TxD data output
–
0
–
–
300
100
ns
ns
TXD
TCS
Receive timing (see Figure )
t
t
RxD data set-up time before RxC HIGH at external clock input on IP pin
RxD data hold time after RxC HIGH at external clock input on IP pin
200
25
–
–
–
–
ns
ns
RXS
RXH
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
supply range.
CC
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a
transition time of 20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.0 V. All time measurements are referenced at input
voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V as appropriate.
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
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2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
4. Test conditions for outputs: C = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: C = 50 pF, R = 2.7 kΩ to V .
CC
L
L
L
5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must
be negated for t
to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the
EHEL
RDN input even if the CEN is used as the strobing signal for bus operations.
7. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
8. Minimum frequencies are not tested but are guaranteed by design.
RESET
t
RES
SD00028
Figure 3. Reset Timing
A0–A3
t
t
ELAX
AVEL
CEN
(READ)
t
EHEL
t
RLRH
RDN
t
RHDF
t
RLDV
t
RHDI
t
RLDA
D0–D7
(READ)
FLOAT
INVALID
VALID
FLOAT
CEN
(WRITE)
t
EHEL
t
WLWH
WRN
t
DVWH
t
WHDI
D0–D7
(WRITE)
VALID
SD00100
Figure 4. Bus Timing
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2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
RDN
t
t
PH
PS
IP0–IP6
(a) INPUT PINS
WRN
t
PD
OP0–OP7
OLD DATA
NEW DATA
(b) OUTPUT PINS
SD00101
Figure 5. Port Timing
V
M
t
WRN
1
IR
INTERRUPT
OUTPUT
V
+0.5V
OL
V
OL
NOTES:
1. INTRN or OP3-OP7 when used as interrupt outputs.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, V , to a point 0.5V above V . This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
M
OL
test environment are pronounced and can greatly affect the resultant measurement.
SD00102
Figure 6. Interrupt Timing
10
2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
t
t
CLK
CTC
+5 V
t
Rx
t
Tx
R1
X1/CLK
CTCLK
RxC
1 kΩ
X1
X2
U1
TxC
t
t
CLK
CTC
RESISTOR REQUIRED
WHEN U1 IS A TTL DEVICE
t
Rx
NC
t
Tx
SCC2681T
C1 = C2 = 24 pF FOR C = 20 pF
L
X1
3 pF
50 TO
3.6864 MHz
150 kΩ
X2
TO INTERNAL CLOCK DRIVERS
4 pF
NOTE:
C1 AND C2 SHOULD BE BASED ON MANUFACTURER’S SPECIFICATION. PARASITIC CAPACITANCE SHOULD BE
INCLUDED WITH C1 AND C2. R1 IS ONLY REQUIRED IF U1 WILL NOT DRIVE TO X1 INPUT LEVELS
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY:
LOAD CAPACITANCE (C ):
2 – 4 MHz
12 – 32 pF
L
TYPE OF OPERATION:
PARALLEL RESONANT, FUNDAMENTAL MODE
SD00726
Figure 7. Clock Timing
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
t
TXD
TxD
t
TCS
TxC
(1X OUTPUT)
SD00103
Figure 8. Transmit
RxC
(1X INPUT)
t
t
RXH
RXS
RxD
SD00104
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2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
Figure 9. Receive
TxD
D1
D2
D3
BREAK
D4
D6
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
D1
D2
D3
START
BREAK
D4
STOP
BREAK
D5 WILL
NOT BE
D6
TRANSMITTED
1
CTSN
(IP0)
2
RTSN
(OP0)
OPR(0) = 1
OPR(0) = 1
NOTES:
1. Timing shown for MR2(4) = 1.
2. Timing shown for MR2(5) = 1.
SD00094
Figure 10. Transmitter Timing
D1
D2
D3
D4
D5
D6
D7
D8
RxD
D6, D7, D8 WILL BE LOST
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDY/
FFULL
2
(OP5)
RDN
S = STATUS
D = DATA
S
D
S D
S
D
S
D
D1
D2
D3
D4
OVERRUN
(SR4)
D5 WILL
BE LOST
RESET BY
COMMAND
1
RTS
(OP0)
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1.
2. Shown for OPCR(4) = 1 and MR1(6) = 0.
SD00105
Figure 11. Receiver Timing
12
2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
MASTER STATION
BIT 9
1
BIT 9
0
BIT 9
1
ADD#1
D0
ADD#2
TxD
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
MR1(4–3) = 11
MR1(2) = 1
ADD#1 MR1(2) = 0D0
MR1(2) = 1
ADD#2
PERIPHERAL STATION
BIT 9
BIT 9
1
BIT 9
BIT 9
BIT 9
0
RxD
0
ADD#1
D0
0
ADD#2 1
RECEIVER
ENABLED
RxRDY
(SR0)
RDN/WRN
S = STATUS
D = DATA
S
D
S
D
MR1(4–3) = 11
ADD#1
D0
ADD#2
SD00106
Figure 12. Wake-Up Mode
13
2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
14
2004 Apr 06
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC2681T
REVISION HISTORY
Rev
Date
Description
_1
20040406
Product data (9397 750 12073). ECN 853-2446 01-A15014 of 15 December 2003.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 04-04
9397 750 12073
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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