SC16C2550BIBS,128_技术文档

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte

FIFOs

Rev. 05 — 12 January 2009

Product data sheet

1. General description

The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert parallel

data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

The SC16C2550B is pin compatible with the ST16C2550. It will power-up to be

functionally equivalent to the 16C2450. The SC16C2550B provides enhanced UART

functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The

DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDYn and

RXRDYn signals. On-board status registers provide the user with error indications and

operational status. System interrupts and modem control features may be tailored by

software to meet speciﬁc user requirements. An internal loopback capability allows

on-board diagnostics. Independent programmable baud rate generators are provided to

select transmit and receive baud rates.

The SC16C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,

and is available in plastic PLCC44, LQFP48, DIP40 and HVQFN32 packages.

2. Features

I 2 channel UART

I 5 V, 3.3 V and 2.5 V operation

I 5 V tolerant on input only pins¹

I Industrial temperature range

I Pin and functionally compatible to 16C2450 and software compatible with INS8250,

SC16C550

I Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V

I 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

I 16-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

I Independent transmit and receive UART control

I Four selectable Receive FIFO interrupt trigger levels

I Software selectable baud rate generator

I Standard asynchronous error and framing bits (Start, Stop and Parity Overrun Break)

I Transmit, Receive, Line Status and Data Set interrupts independently controlled

1. For data bus pins D7 to D0, see Table 23 “Limiting values”.

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

I Fully programmable character formatting:

N 5-bit, 6-bit, 7-bit or 8-bit characters

N Even, odd or no-parity formats

N 1, 1¹⁄₂or 2-stop bit

N Baud generation (DC to 5 Mbit/s)

I False start-bit detection

I Complete status reporting capabilities

I 3-state output TTL drive capabilities for bidirectional data bus and control bus

I Line break generation and detection

I Internal diagnostic capabilities:

N Loopback controls for communications link fault isolation

I Prioritized interrupt system controls

I Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)

3. Ordering information

Table 1.

Ordering information

Package

Name

SC16C2550BIA44 PLCC44

Type number

Description

Version

plastic leaded chip carrier; 44 leads

SOT187-2

SOT617-1

SC16C2550BIBS

HVQFN32 plastic thermal enhanced very thin quad ﬂat package; no leads;

32 terminals; body 5 × 5 × 0.85 mm

SC16C2550BIB48 LQFP48

SC16C2550BIN40 DIP40

plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm

SOT313-2

SOT129-1

plastic dual in-line package; 40 leads (600 mil)

3.1 Ordering options

Table 2.

Ordering options

Type number

Topside mark

SC16C2550BIA44

2550B

SC16C2550BIA44

SC16C2550BIBS

SC16C2550BIB48

SC16C2550BIN40

16C2550B

SC16C2550BIN40

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

2 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

4. Block diagram

SC16C2550B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTER

D0 to D7

IOR

DATA BUS

AND

IOW

RESET

CONTROL

LOGIC

RECEIVE

FIFO

RECEIVE

SHIFT

RXA, RXB

REGISTER

A0 to A2

CSA

REGISTER

SELECT

LOGIC

CSB

DTRA, DTRB

RTSA, RTSB

OP2A, OP2B

MODEM

CONTROL

LOGIC

CTSA, CTSB

RIA, RIB

CDA, CDB

DSRA, DSRB

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

002aaa595

XTAL1

XTAL2

Fig 1. Block diagram of SC16C2550B

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

3 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

5. Pinning information

5.1 Pinning

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

D6

D7

RESET

RTSA

OP2A

INTA

INTB

A0

RXB

RXA

TXA

TXB

OP2B

CSA

SC16C2550BIBS

A1

A2

002aab746

Transparent top view

Fig 2. Pin conﬁguration for HVQFN32

SC16C2550BIN40

1

2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

D0

D1

V

CC

RIA

3

D2

CDA

DSRA

CTSA

4

D3

5

D4

6

D5

RESET

DTRB

DTRA

RTSA

OP2A

INTA

INTB

A0

7

D6

8

D7

9

RXB

RXA

TXA

TXB

OP2B

CSA

CSB

XTAL1

XTAL2

IOW

CDB

GND

10

11

12

13

14

15

16

17

18

19

20

A1

A2

CTSB

RTSB

RIB

DSRB

IOR

002aaa596

Fig 3. Pin conﬁguration for DIP40

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

4 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7

39

38

37

36

35

34

33

32

31

30

29

D5

D6

RESET

DTRB

DTRA

RTSA

OP2A

RXRDYA

INTA

INTB

A0

8

9

D7

10

11

12

13

14

15

16

17

RXB

RXA

TXRDYB

TXA

SC16C2550BIA44

TXB

OP2B

CSA

A1

CSB

A2

002aaa597

Fig 4. Pin conﬁguration for PLCC44

1

2

36

35

34

33

32

31

30

29

28

27

26

25

D5

D6

RESET

DTRB

DTRA

RTSA

OP2A

RXRDYA

INTA

INTB

A0

3

D7

4

RXB

RXA

TXRDYB

TXA

5

6

SC16C2550BIB48

7

8

TXB

9

OP2B

CSA

CSB

n.c.

10

11

12

A1

A2

n.c.

002aaa598

Fig 5. Pin conﬁguration for LQFP48

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

5 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

5.2 Pin description

Table 3.

Symbol Pin

HVQFN32 DIP40 PLCC44 LQFP48

Pin description

Type Description

A0

19

18

17

8

28

27

26

14

15

31

30

29

16

17

28

27

26

10

11

I

Address 0 select bit. Internal register address selection.

Address 1 select bit. Internal register address selection.

Address 2 select bit. Internal register address selection.

A1

A2

CSA

CSB

Chip Select A, B (active LOW). This function is associated

with individual channels, A through B. These pins enable data

transfers between the user CPU and the SC16C2550B for the

channel(s) addressed. Individual UART sections (A, B) are

addressed by providing a logic 0 on the respective CSA, CSB

pin.

9

D0

27

28

29

30

31

32

1

2

44

45

46

47

48

1

I/O

I

Data bus (bidirectional). These pins are the 8-bit, 3-state data

bus for transferring information to or from the controlling CPU.

D0 is the least signiﬁcant bit and the ﬁrst data bit in a transmit

or receive serial data stream.

D1

2

3

D2

3

4

D3

4

5

D4

5

6

D5

6

7

D6

7

8

2

D7

2

8

9

3

GND

INTA

INTB

13

21

20

30

29

22

33

32

17

30

29

Signal and power ground.

O

Interrupt A, B (3-state). This function is associated with

individual channel interrupts, INTA, INTB. INTA, INTB are

enabled when MCR bit 3 is set to a logic 1, interrupts are

enabled in the Interrupt Enable Register (IER) and is active

when an interrupt condition exists. Interrupt conditions include:

receiver errors, available receiver buffer data, transmit buffer

empty or when a modem status ﬂag is detected.

O

IOR

14

12

21

18

24

20

19

15

I

Read strobe (active LOW strobe). A logic 0 transition on this

pin will load the contents of an internal register deﬁned by

address bits A0 to A2 onto the SC16C2550B data bus

(D0 to D7) for access by external CPU.

IOW

Write strobe (active LOW strobe). A logic 0 transition on this

pin will transfer the contents of the data bus (D0 to D7) from the

external CPU to an internal register that is deﬁned by address

bits A0 to A2.

OP2A

OP2B

22

7

31

13

35

15

32

9

O

Output 2 (user-deﬁned). This function is associated with

individual channels, A through B. The state at these pin(s) are

deﬁned by the user and through MCR register bit 3. INTA, INTB

are set to the active mode and OP2 to logic 0 when MCR[3] is

set to a logic 1. INTA, INTB are set to the 3-state mode and

OP2 to a logic 1 when MCR[3] is set to a logic 0. See Table 18

“Modem Control Register bits description”, bit 3 (MCR[3]).

Since these bits control both the INTA, INTB operation and

OP2 outputs, only one function should be used at one time, INT

or OP2.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

6 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 3.

Pin description …continued

Symbol Pin

Type Description

HVQFN32 DIP40 PLCC44 LQFP48

RESET

24

35

39

36

I

Reset (active HIGH). A logic 1 on this pin will reset the internal

registers and all the outputs. The UART transmitter output and

the receiver input will be disabled during reset time. (See

Section 7.10 “SC16C2550B external reset condition” for

initialization details.)

RXRDYA

RXRDYB

-

34

23

31

18

O

Receive Ready A, B (active LOW). This function is associated

with PLCC44 and LQFP48 packages only. This function

provides the RX FIFO/RHR status for individual receive

channels (A-B). RXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the receive data FIFOs. A logic 0

indicates there is a receive data to read/upload, that is, receive

ready status with one or more RX characters available in the

FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty

or when the programmed trigger level has not been reached.

This signal can also be used for single mode transfers (DMA

mode 0).

TXRDYA

TXRDYB

-

1

43

6

O

Transmit Ready A, B (active LOW). This function is

associated with PLCC44 and LQFP48 packages only. These

outputs provide the TX FIFO/THR status for individual transmit

channels (A, B). TXRDYn is primarily intended for monitoring

DMA mode 1 transfers for the transmit data FIFOs. An

individual channel’s TXRDYA, TXRDYB buffer ready status is

indicated by logic 0, that is, at least one location is empty and

available in the FIFO or THR. This pin goes to a logic 1 (DMA

mode 1) when there are no more empty locations in the FIFO

or THR. This signal can also be used for single mode transfers

(DMA mode 0).

12

V_CC

26

10

40

16

44

18

42

13

I

Power supply input.

XTAL1

Crystal or external clock input. Functions as a crystal input

or as an external clock input. A crystal can be connected

between this pin and XTAL2 to form an internal oscillator

circuit. Alternatively, an external clock can be connected to this

pin to provide custom data rates. (See Section 6.5

“Programmable baud rate generator”.) See Figure 6.

XTAL2

11

17

19

14

O

Output of the crystal oscillator or buffered clock. (See also

XTAL1.) Crystal oscillator output or buffered clock output.

Should be left open if an external clock is connected to XTAL1.

For extended frequency operation, this pin should be tied to

V_CCvia a 2 kΩ resistor.

CDA

CDB

-

38

19

42

21

40

16

I

Carrier Detect (active LOW). These inputs are associated

with individual UART channels A through B. A logic 0 on this

pin indicates that a carrier has been detected by the modem for

that channel.

CTSA

CTSB

25

16

36

25

40

28

38

23

I

Clear to Send (active LOW). These inputs are associated with

individual UART channels, A through B. A logic 0 on the CTSn

pin indicates the modem or data set is ready to accept transmit

data from the SC16C2550B. Status can be tested by reading

MSR[4]. This pin has no effect on the UART’s transmit or

receive operation.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

7 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 3.

Pin description …continued

Symbol Pin

Type Description

HVQFN32 DIP40 PLCC44 LQFP48

DSRA

DSRB

-

37

22

41

25

39

20

I

Data Set Ready (active LOW). These inputs are associated

with individual UART channels, A through B. A logic 0 on this

pin indicates the modem or data set is powered-on and is ready

for data exchange with the UART. This pin has no effect on the

UART’s transmit or receive operation.

DTRA

DTRB

-

33

34

37

38

34

35

O

Data Terminal Ready (active LOW). These outputs are

associated with individual UART channels, A through B.

A logic 0 on this pin indicates that the SC16C2550B is

powered-on and ready. This pin can be controlled via the

Modem Control Register. Writing a logic 1 to MCR[0] will set

the DTRn output to logic 0, enabling the modem. This pin will

be a logic 1 after writing a logic 0 to MCR[0] or after a reset.

This pin has no effect on the UART’s transmit or receive

operation.

RIA

RIB

-

39

23

43

26

41

21

I

Ring Indicator (active LOW). These inputs are associated

with individual UART channels, A through B. A logic 0 on this

pin indicates the modem has received a ringing signal from the

telephone line. A logic 1 transition on this input pin will generate

an interrupt.

RTSA

RTSB

23

15

32

24

36

27

33

22

O

Request to Send (active LOW). These outputs are associated

with individual UART channels, A through B. A logic 0 on the

RTSn pin indicates the transmitter has data ready and waiting

to send. Writing a logic 1 in the Modem Control Register

MCR[1] will set this pin to a logic 0, indicating data is available.

After a reset this pin will be set to a logic 1. This pin has no

effect on the UART’s transmit or receive operation.

RXA

RXB

4

3

10

9

11

10

5

4

I

Receive data A, B. These inputs are associated with individual

serial channel data to the SC16C2550B receive input circuits,

A and B. The RXn signal will be a logic 1 during reset, idle (no

data) or when the transmitter is disabled. During the local

Loopback mode, the RXn input pin is disabled and TX data is

connected to the UART RX input, internally.

TXA

TXB

5

6

11

12

13

14

7

8

O

Transmit data A, B. These outputs are associated with

individual serial transmit channel data from the SC16C2550B.

The TXn signal will be a logic 1 during reset, idle (no data) or

when the transmitter is disabled. During the local Loopback

mode, the TXn output pin is disabled and TX data is internally

connected to the UART RX input.

n.c.

-

12, 24,

25, 37

-

not connected

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

8 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6. Functional description

The SC16C2550B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC16C2550B represents such

an integration with greatly enhanced features. The SC16C2550B is fabricated with an

advanced CMOS process.

The SC16C2550B is an upward solution that provides a dual UART capability with

16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The

SC16C2550B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C2550B by the transmit and receive FIFOs. This allows the external processor to

handle more networking tasks within a given time. For example, the ST16C2450 without a

receive FIFO, will require unloading of the RHR in 93 microseconds (this example uses a

character length of 11 bits, including start/stop bits at 115.2 kbit/s). This means the

external CPU will have to service the receive FIFO less than every 100 microseconds.

However, with the 16-byte FIFO in the SC16C2550B, the data buffer will not require

unloading/loading for 1.53 ms. This increases the service interval, giving the external CPU

additional time for other applications and reducing the overall UART interrupt servicing

time. In addition, the four selectable receive FIFO trigger interrupt levels are uniquely

provided for maximum data throughput performance especially when operating in a

multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement

of the external controlling CPU, increases performance and reduces power consumption.

The SC16C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a

crystal or external clock input of 7.3728 MHz, the user can select data rates up to

460.8 kbit/s.

The rich feature set of the SC16C2550B is available through internal registers. Selectable

receive FIFO trigger levels, selectable TX and RX baud rates and modem interface

controls are all standard features. Following a power-on reset or an external reset, the

SC16C2550B is software compatible with the previous generation, ST16C2450.

6.1 UART A-B functions

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC16C2550B package and an external serial device. A

logic 0 on chip select pins CSA and/or CSB allows the user to conﬁgure, send data,

and/or receive data via UART channels A through B. Individual channel select functions

are shown in Table 4.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

9 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 4.

Serial port selection

Chip Select

CSA, CSB = 1

CSA = 0

Function

none

UART channel A

UART channel B

CSB = 0

6.2 Internal registers

The SC16C2550B provides two sets of internal registers (A and B) consisting of

12 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 5. The UART registers function as data holding

registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control

Register (FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM) and a

user-accessible Scratchpad Register (SPR).

Table 5.

A2

Internal registers decoding

A0 READ mode

A1

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

1

LSB of Divisor Latch

MSB of Divisor Latch

LSB of Divisor Latch

MSB of Divisor Latch

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

10 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.3 FIFO operation

The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

(FCR) bit 0. The user can set the receive trigger level via FCR bits 7:6, but not the transmit

trigger level. The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. An interrupt is generated whenever the Receive Holding

Register (RHR) has not been read following the loading of a character or the receive

trigger level has not been reached.

Table 6.

Flow control mechanism

Selected trigger level (characters)

INTn pin activation

1

4

8

14

6.4 Hardware/software and time-out interrupts

The interrupts are enabled by IER[3:0]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C2550B

will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to

continuing operations. The ISR register provides the current singular highest priority

interrupt only. A condition can exist where a higher priority interrupt may mask the lower

priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority

interrupt(s) be reﬂected in the status register. Servicing the interrupt without investigating

further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the SC16C2550B

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time

Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center

of each stop bit received or each time the Receive Holding Register (RHR) is read. The

actual time-out value is 4 character time, including data information length, start bit, parity

bit and the size of stop bit, that is, 1×, 1.5× or 2× bit times.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

11 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.5 Programmable baud rate generator

The SC16C2550B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

The SC16C2550B can support a standard data rate of 921.6 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable baud rate generator is capable of

operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is necessary

to use full rail swing on the clock input. The SC16C2550B can be conﬁgured for internal or

external clock operation. For internal clock oscillator operation, an industry standard

microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins.

Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal

baud rate generator for standard or custom rates (see Table 7).

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC16C2550B divides the basic external clock by 16. The basic 16× clock provides table

rates to support standard and custom applications using the same system design. The

rate table is conﬁgured via the DLL and DLM internal register functions. Customized baud

rates can be achieved by selecting the proper divisor values for the MSB and LSB

sections of baud rate generator.

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 7 shows the

selectable baud rate table available when using a 1.8432 MHz external clock input.

XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 6. Crystal oscillator connection

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

12 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 7.

Baud rate generator programming table using a 1.8432 MHz clock

Output

baud rate

(bit/s)

Output

16× clock divisor

(decimal)

Output

16× clock divisor

(hexadecimal)

DLM

program value

(hexadecimal)

DLL

program value

(hexadecimal)

50

2304

1536

1047

768

384

192

96

900

600

417

300

180

C0

60

09

06

04

03

01

00

17

00

80

C0

60

30

20

18

10

0C

06

03

02

01

75

110

150

300

600

1200

2400

3600

4800

7200

9600

19.2 k

38.4 k

57.6 k

115.2 k

48

30

32

20

24

18

16

10

12

0C

06

6

3

03

2

02

1

01

6.6 DMA operation

The SC16C2550B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an

empty location(s). The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA

mode is de-activated (DMA Mode 0), the SC16C2550B activates the interrupt output pin

(INTn) for each data transmit or receive operation. When DMA mode is activated (DMA

Mode 1), the user takes the advantage of block mode operation by loading or unloading

the FIFO in a block sequence determined by the receive trigger level and the transmit

FIFO. In this mode, the SC16C2550B sets the TXRDYn (or RXRDYn) output pin when

characters in the transmit FIFO is below 16 or the characters in the receive FIFOs are

above the receive trigger level.

6.7 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally

(see Figure 7). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are

disconnected from their associated interface pins and instead are connected together

internally. The CTS, DSR, CD and RI are disconnected from their normal modem control

input pins and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2]

(OP1). Loopback test data is entered into the transmit holding register via the user data

bus interface, D0 through D7. The transmit UART serializes the data and passes the serial

data to the receive UART via the internal loopback connection. The receive UART

SC16C2550B_5

Product data sheet

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13 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

converts the serial data back into parallel data that is then made available at the user data

interface D0 through D7. The user optionally compares the received data to the initial

transmitted data for verifying error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The modem

control interrupts are also operational.

SC16C2550B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

D0 to D7

IOR

DATA BUS

AND

IOW

RESET

CONTROL

LOGIC

MCR[4] = 1

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RXA, RXB

REGISTER

SELECT

LOGIC

A0 to A2

CSA, CSB

RTSA, RTSB

CTSA, CTSB

DTRA, DTRB

MODEM

CONTROL

LOGIC

DSRA, DSRB

(OP1A, OP1B)

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

RIA, RIB

(OP2A, OP2B)

CDA, CDB

002aaa599

XTAL2

XTAL1

Fig 7. Internal Loopback mode diagram

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

14 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7. Register descriptions

Table 8 details the assigned bit functions for the SC16C2550B internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.10.

Table 8.

SC16C2550B internal registers

A2 A1 A0 Register Default^[1]Bit 7

General register set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

0

bit 6

0

bit 5

0

bit 4

0

bit 3

bit 2

bit 1

bit 0

modem receive transmit receive

status line holding holding

interrupt status register register

interrupt interrupt

0

1

0

1

FCR

ISR

00

01

00

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

reserved reserved DMA

XMIT RCVR

FIFO FIFO

FIFOs

enable

0

mode

select

reset

FIFOs

enabled enabled

FIFOs

0

INT

status

priority

bit 2

priority

bit 1

priority

bit 0

LCR

divisor

latch

enable

set break set parity even

parity

enable

stop bits word

length

word

length

bit 0

bit 1

1

0

1

MCR

LSR

00

60

0

loop

back

OP2/INT (OP1)

enable

RTS

DTR

FIFO

data

error

THR and THR

TSR

empty

break

interrupt error

framing parity

overrun receive

error

empty

error

data

ready

1

0

1

MSR

SPR

X0

FF

CD

RI

DSR

bit 5

CTS

bit 4

∆CD

∆RI

∆DSR

∆CTS

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

Special register set^[3]

0

1

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown represents the register’s initialized hexadecimal value; X = not applicable.

[2] Accessible only when LCR[7] is logic 0.

[3] Baud rate registers accessible only when LCR[7] is logic 1.

7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 through D0)

to the TSR and UART via the THR, providing that the THR is empty. The THR empty ﬂag

in the LSR register will be set to a logic 1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can be performed when the THR

empty ﬂag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550B and

receive FIFO by reading the RHR register. The receive section provides a mechanism to

SC16C2550B_5

Product data sheet

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15 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

prevent false starts. On the falling edge of a start or false start bit, an internal receiver

counter starts counting clocks at the 16× clock rate. After 7¹⁄₂clocks, the start bit time

should be shifted to the center of the start bit. At this time the start bit is sampled and if it

is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver

from assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INTA, INTB output pins.

Table 9.

Interrupt Enable Register bits description

Bit

7:4

3

Symbol

Description

IER[7:4]

IER[3]

not used

Modem Status Interrupt. This interrupt will be issued whenever there is a

modem status change as reﬂected in MSR[3:0].

logic 0 = disable the Modem Status Register interrupt (normal default

condition)

logic 1 = enable the Modem Status Register interrupt

2

1

IER[2]

IER[1]

Receive Line Status interrupt. This interrupt will be issued whenever a

receive data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will

be issued whenever the THR is empty and is associated with LSR[5]. In the

FIFO modes, this interrupt will be issued whenever the FIFO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

0

IER[0]

Receive Holding Register. In the 16C450 mode, this interrupt will be issued

when the RHR has data or is cleared when the RHR is empty. In the FIFO

mode, this interrupt will be issued when the FIFO has reached the

programmed trigger level or is cleared when the FIFO drops below the

trigger level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt (normal

default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

SC16C2550B_5

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SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1) and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR register or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C2550B in the FIFO polled

mode of operation. In this mode, interrupts are not generated and the user must poll the

LSR register for TX and/or RX data status. Since the receiver and transmitter have

separate bits in the LSR either or both can be used in the polled mode by selecting

respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation and is similar to

the 16C450 mode. Transmit Ready (TXRDYn) on PLCC44 and LQFP48 packages will go

to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive Ready

(RXRDYn) on PLCC44 and LQFP48 packages will go to a logic 0 whenever the Receive

Holding Register (RHR) is loaded with a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is empty. TXRDYn on PLCC44 and LQFP48 packages remains a logic 0

as long as one empty FIFO location is available. The receive interrupt is set when the

receive FIFO ﬁlls to the programmed trigger level. However, the FIFO continues to ﬁll

SC16C2550B_5

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SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and

LQFP48 packages transitions LOW when the FIFO reaches the trigger level and

transitions HIGH when the FIFO empties.

7.3.2 FIFO mode

Table 10. FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7:6]

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

logic 0 (or cleared) = normal default condition

logic 1 = RX trigger level

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to be

loaded until it is full. Refer to Table 11.

5:4

3

FCR[5:4]

FCR[3]

Not used; initialized to logic 0.

DMA mode select.

logic 0 = set DMA mode ‘0’

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C2550B is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0) and when there are no

characters in the transmit FIFO or Transmit Holding Register, the TXRDYn

pin in PLCC44 or LQFP48 packages will be a logic 0. Once active, the

TXRDYn pin will go to a logic 1 after the ﬁrst character is loaded into the

Transmit Holding Register.

Receive operation in mode ‘0’: When the SC16C2550B is in mode ‘0’

(FCR[0] = logic 0) or in the FIFO mode (FCR[3] = logic 0) and there is at

least one character in the receive FIFO, the RXRDYn pin will be a logic 0.

Once active, the RXRDYn pin on PLCC44 and LQFP48 packages will go

to a logic 1 when there are no more characters in the receiver.

Transmit operation in mode ‘1’: When the SC16C2550B is in FIFO

mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin on PLCC44

and LQFP48 packages will be a logic 1 when the transmit FIFO is

completely full. It will be a logic 0 if one or more FIFO locations are empty.

Receive operation in mode ‘1’: When the SC16C2550B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached

or a Receive Time-out has occurred, the RXRDYn pin on PLCC44 and

LQFP48 packages will go to a logic 0. Once activated, it will go to a logic 1

after there are no more characters in the FIFO.

2

FCR[2]

XMIT FIFO reset.

logic 0 = Transmit FIFO not reset (normal default condition).

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the Transmit Shift Register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

SC16C2550B_5

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SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 10. FIFO Control Register bits description …continued

Bit

Symbol

Description

1

FCR[1]

RCVR FIFO reset.

logic 0 = Receive FIFO not reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the Receive Shift Register is not cleared or altered). This

bit will return to a logic 0 after clearing the FIFO.

0

FCR[0]

FIFOs enabled.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’

when other FCR bits are written to or they will not be programmed.

Table 11. RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level

0

1

0

1

0

1

01

04

08

14

7.4 Interrupt Status Register (ISR)

The SC16C2550B provides four levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with four

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged until

the pending interrupt is serviced. A lower level interrupt may be seen after servicing the

higher level interrupt and re-reading the interrupt status bits. Table 12 “Interrupt source”

shows the data values (bits 3:0) for the four prioritized interrupt levels and the interrupt

sources associated with each of these interrupt levels.

Table 12. Interrupt source

Priority ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

2

3

4

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data Time-out)

TXRDY (Transmitter Holding Register empty)

MSR (Modem Status Register)

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SC16C2550B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 13. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not

being used in the 16C450 mode. They are set to a logic 1 when the

FIFOs are enabled in the SC16C2550B mode.

logic 0 or cleared = default condition

not used

5:4

3:1

ISR[5:4]

ISR[3:1]

INT priority bits 2:0. These bits indicate the source for a pending interrupt

at interrupt priority levels 1, 2 and 3 (see Table 12).

logic 0 or cleared = default condition

INT status.

0

ISR[0]

logic 0 = an interrupt is pending and the ISR contents may be used as

a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits and the parity are selected by writing the

appropriate bits in this register.

Table 14. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

LCR[6]

Set break. When enabled, the Break control bit causes a break condition

to be transmitted (the TX output is forced to a logic 0 state). This

condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3

2

LCR[5:3]

LCR[2]

Programs the parity conditions (see Table 15)

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with

the programmed word length (see Table 16).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 17).

logic 0 or cleared = default condition

Table 15. LCR[5:3] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

X

0

1

X

0

1

0

1

0

1

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

SC16C2550B_5

Product data sheet

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SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 16. LCR[2] stop bit length

LCR[2]

Word length (bits)

Stop bit length (bit times)

0

1

5, 6, 7, 8

5

1

1¹⁄₂

6, 7, 8

2

Table 17. LCR[1:0] word length

LCR[1]

LCR[0]

Word length (bits)

0

1

0

1

0

1

5

6

7

8

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 18. Modem Control Register bits description

Bit

7:5

4

Symbol

MCR[7:5]

MCR[4]

Description

reserved; set to ‘0’

Loopback. Enable the local Loopback mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS, DSR, CD and RI

are disconnected from the SC16C2550B I/O pins. Internally the modem

data and control pins are connected into a loopback data conﬁguration

(see Figure 7). In this mode, the receiver and transmitter interrupts remain

fully operational. The Modem Control Interrupts are also operational, but

the interrupts’ sources are switched to the lower four bits of the Modem

Control. Interrupts continue to be controlled by the IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

OP2/INT enable

3

2

MCR[3]

MCR[2]

logic 0 = forces INT (A, B) outputs to the 3-state mode and sets OP2 to a

logic 1 (normal default condition)

logic 1 = forces the INT (A, B outputs to the active mode and sets OP2 to

a logic 0

(OP1). OP1A/OP1B are not available as an external signal in the

SC16C2550B. This bit is instead used in the Loopback mode only. In the

Loopback mode, this bit is used to write the state of the modem RI

interface signal.

1

0

MCR[1]

MCR[0]

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

SC16C2550B_5

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SC16C2550B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C2550B and

the CPU.

Table 19. Line Status Register bits description

Bit Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when there are no remaining error ﬂags

associated with the remaining data in the FIFO.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the Transmit Holding Register and the Transmit Shift Register

are both empty. It is reset to logic 0 whenever either the THR or TSR contains a

data character. In the FIFO mode, this bit is set to ‘1’ whenever the Transmit

FIFO and Transmit Shift Register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmit

FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error.

logic 0 = no parity error (normal default condition

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the Receive Shift

Register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the Receive Shift Register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

SC16C2550B_5

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SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 19. Line Status Register bits description …continued

Bit Symbol Description

0

LSR[0]

Receive data ready.

logic 0 = no data in Receive Holding Register or FIFO (normal default

condition)

logic 1 = data has been received and is saved in the Receive Holding Register

or FIFO

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem or

other peripheral device to which the SC16C2550B is connected. Four bits of this register

are used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

Table 20. Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD. During normal operation, this bit is the complement of the CD input.

Reading this bit in the Loopback mode produces the state of MCR[3] (OP2).

6

5

4

3

MSR[6]

MSR[5]

MSR[4]

MSR[3]

RI. During normal operation, this bit is the complement of the RI input.

Reading this bit in the Loopback mode produces the state of MCR[2] (OP1).

DSR. During normal operation, this bit is the complement of the DSR input.

During the Loopback mode, this bit is equivalent to MCR[0] (DTR).

CTS. During normal operation, this bit is the complement of the CTS input.

During the Loopback mode, this bit is equivalent to MCR[1] (RTS).

∆CD ^[1]

logic 0 = no CD change (normal default condition)

logic 1 = the CD input to the SC16C2550B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

2

1

0

MSR[2]

MSR[1]

MSR[0]

∆RI ^[1]

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C2550B has changed from a logic 0 to a

logic 1. A modem Status Interrupt will be generated.

∆DSR ^[1]

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C2550B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

∆CTS ^[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C2550B has changed state since the

last time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

23 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.9 Scratchpad Register (SPR)

The SC16C2550B provides a temporary data register to store 8 bits of user information.

7.10 SC16C2550B external reset condition

Table 21. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

FCR

ISR

FCR[7:0] = 0

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

SFR[7:0] = 1

MSR

SPR

DLL

DLL[7:0] = X

DLM

DLM[7:0] = X

Table 22. Reset state for outputs

Output

Reset state

logic 1

TXA, TXB

OP2A, OP2B

RTSA, RTSB

DTRA, DTRB

INTA, INTB

logic 1

3-state condition

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

24 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

8. Limiting values

Table 23. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

7

Unit

V

supply voltage

-

V_n

voltage on any other pin

at D7 to D0 pins

at input only pins

GND − 0.3

V_CC+ 0.3

5.3

V

GND − 0.3

V

T_amb

operating temperature

−40

−65

-

+85

°C

mW

T_stg

storage temperature

+150

500

P_tot/pack

total power dissipation per package

9. Static characteristics

Table 24. Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

Min Max

−0.3 +0.45 −0.3

1.8 V_CC2.4

−0.3 +0.65 −0.3

V_CC= 3.3 V

V_CC= 5.0 V Unit

Min

Max

+0.6

V_CC

+0.8

-

Min

−0.5

3.0

Max

+0.6

V_CC

+0.8

-

V_IL(clk)

V_IH(clk)

V_IL

clock LOW-level input voltage

V

clock HIGH-level input voltage

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

except X1 clock

on all outputs^[1]

−0.5

2.2

V_IH

1.6

-

2.0

V_OL

I_OL= 5 mA

(data bus)

-

0.4

V

I_OL= 4 mA

(other outputs)

-

0.4

-

I_OL= 2 mA

(data bus)

-

0.4

-

I_OL= 1.6 mA

(other outputs)

-

0.4

-

V_OH

HIGH-level output voltage

I_OH= −5 mA

(data bus)

-

2.0

-

2.4

I_OH= −1 mA

(other outputs)

-

I_OH= −800 µA

(data bus)

1.85

I_OH= −400 µA

-

(other outputs)

I_LIL

I_L(clk)

I_CC

C_i

LOW-level input leakage current

clock leakage current

supply current

-

±10

±30

3.5

5

-

±10

±30

4.5

5

-

±10 µA

±30 µA

4.5 mA

f = 5 MHz

input capacitance

5

pF

[1] Except XTAL2, V_OL= 1 V typical.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

25 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

10. Dynamic characteristics

Table 25. Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

t_w1

t_w2

f_XTAL

t_6s

clock pulse duration

10

-

6

-

6

-

ns

clock pulse duration

oscillator/clock frequency

address set-up time

address hold time

ns

[1][2]

48

-

80

-

80

-

MHz

ns

0

t_6h

0

-

0

-

ns

t_7d

IOR delay from chip select

IOR strobe width

10

77

0

-

10

26

0

-

10

23

0

-

ns

t_7w

t_7h

25 pF load

-

ns

chip select hold time from

IOR

-

ns

t_9d

read cycle delay

25 pF load

20

-

77

15

-

20

-

26

15

-

20

-

23

15

-

ns

t_12d

t_12h

t_13d

t_13w

t_13h

delay from IOR to data

data disable time

-

IOW delay from chip select

IOW strobe width

10

20

0

10

20

0

10

15

0

-

chip select hold time from

IOW

-

t_15d

t_16s

t_16h

t_17d

t_18d

write cycle delay

data set-up time

25

20

15

-

25

20

5

-

20

15

5

-

ns

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from 25 pF load

Modem input

-

t_19d

t_20d

t_21d

t_22d

t_23d

t_24d

t_25d

t_26d

t_27d

delay to reset interrupt from 25 pF load

IOR

-

100

T_RCLK

100

-

24

T_RCLK

29

-

23

T_RCLK

28

ns

s

[3]

delay from stop to set

interrupt

delay from IOR to reset

interrupt

25 pF load

ns

s

delay from start to set

interrupt

100

45

40

[3]

delay from IOW to transmit

start

8T_RCLK24T_RCLK8T_RCLK24T_RCLK8T_RCLK24T_RCLK

delay from IOW to reset

interrupt

-

100

T_RCLK

100

-

45

T_RCLK

45

-

40

T_RCLK

40

ns

s

delay from stop to set

RXRDY

delay from IOR to reset

RXRDY

ns

delay from IOW to set

TXRDY

100

45

40

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

26 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 25. Dynamic characteristics …continued

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

[3]

[4]

t_28d

delay from start to reset

TXRDY

-

8T_RCLK

-

8T_RCLK

-

8T_RCLK

s

t_RESET

N

RESET pulse width

baud rate divisor

200

1

-

40

1

-

40

1

-

ns

(2¹⁶− 1)

[1] Applies to external clock, crystal oscillator max 24 MHz.

1

t_w3

[2] Maximum frequency =

-------

[3] RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.

[4] Reset pulse must happen when these signals are inactive: CS, IOW, IOR.

10.1 Timing diagrams

t

6h

valid

address

A0 to A2

CSA, CSB

IOW

t

13h

6s

active

t

13d

15d

t

13w

active

t

16h

t

16s

D0 to D7

data

002aae279

Fig 8. General write timing

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

27 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

t

6h

7h

valid

address

A0 to A2

CSA, CSB

IOR

t

6s

active

t

7d

9d

t

7w

active

t

12h

12d

D0 to D7

data

002aae278

Fig 9. General read timing

active

IOW

t

17d

RTSA, RTSB

DTRA, DTRB

change of state

CDA, CDB

CTSA, CTSB

DSRA, DSRB

change of state

t

18d

INTA, INTB

active

t

19d

IOR

t

18d

change of state

RIA, RIB

002aae277

Fig 10. Modem input/output timing

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

28 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

t

w1

w2

EXTERNAL

CLOCK

002aaa112

t

w3

1

t_w3

f _XTAL

=

-------

Fig 11. External clock timing

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RXA, RXB

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

20d

active

INTA, INTB

t

21d

active

IOR

16 baud rate clock

002aae276

Fig 12. Receive timing

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

29 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXn

t

25d

active data

ready

RXRDYn

IOR

t

26d

active

002aae275

Fig 13. Receive ready timing in non-FIFO mode

start

bit

parity stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

first byte that

reaches the

trigger level

t

25d

active data

ready

RXRDYA, RXRDYB

t

26d

active

IOR

002aae274

Fig 14. Receive ready timing in FIFO mode

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

30 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

TXA, TXB

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INTA, INTB

transmitter ready

t

22d

t

24d

t

23d

active

IOW

16 baud rate clock

002aae273

Fig 15. Transmit timing

start

bit

parity stop start

bit bit bit

data bits (0 to 7)

D3 D4

TXA, TXB

D0

D1

D2

D5

D6

D7

active

IOW

D0 to D7

byte #1

t

28d

t

27d

active

transmitter ready

transmitter

not ready

TXRDYA, TXRDYB

002aae272

Fig 16. Transmit ready timing in non-FIFO mode

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

31 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

start

bit

parity stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TXA, TXB

5 data bits

6 data bits

7 data bits

IOW

active

t

28d

D0 to D7

byte #16

t

27d

TXRDYA, TXRDYB

FIFO full

002aae271

Fig 17. Transmit ready timing in FIFO mode (DMA mode ‘1’)

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

32 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

11. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

E

D

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

A

Z

E

4

1

(1)

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

3

1

D

E

D

E

p

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27

VERSION

IEC

JEDEC

JEITA

SOT187-2

112E10

MS-018

EDR-7319

01-11-14

Fig 18. Package outline SOT187-2 (PLCC44)

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

33 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 19. Package outline SOT617-1 (HVQFN32)

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

34 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 20. Package outline SOT313-2 (LQFP48)

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

35 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

D

M

E

A

2

A

L

A

1

c

e

w M

Z

b

1

(e )

1

b

M

H

40

21

pin 1 index

E

1

20

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

Z

A

(1)

1

2

w

UNIT

mm

b

c

D

E

e

L

M

1

E

H

max.

min.

max.

1.70

1.14

0.53

0.38

0.36

0.23

52.5

51.5

14.1

13.7

3.60

3.05

15.80

15.24

17.42

15.90

4.7

0.51

4

2.54

0.1

15.24

0.6

0.254

0.01

2.25

0.067

0.045

0.021

0.015

0.014

0.009

2.067

2.028

0.56

0.54

0.14

0.12

0.62

0.60

0.69

0.63

inches

0.19

0.02

0.16

0.089

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT129-1

051G08

MO-015

SC-511-40

Fig 21. Package outline SOT129-1 (DIP40)

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

36 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

37 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 22) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 26 and 27

Table 26. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 27. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 22.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

38 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 22. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Soldering of through-hole mount packages

13.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

13.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

13.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

39 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

13.4 Package related soldering information

Table 28. Suitability of through-hole mount IC packages for dipping and wave soldering

Package

Soldering method

Dipping

Wave

CPGA, HCPGA

-

suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL

PMFP^[2]

suitable

-

suitable^[1]

not suitable

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

14. Abbreviations

Table 29. Abbreviations

Acronym

CPU

DLL

Description

Central Processing Unit

Divisor Latch LSB

DLM

DMA

FIFO

ISDN

LSB

Divisor Latch MSB

Direct Memory Access

First In/First Out

Integrated Service Digital Network

Least Signiﬁcant Bit

MSB

RHR

THR

Most Signiﬁcant Bit

Receive Holding Register

Transmit Holding Register

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

TTL

UART

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

40 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

15. Revision history

Table 30. Revision history

Document ID

SC16C2550B_5

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20090112

Product data sheet

-

SC16C2550B_4

• Section 2 “Features”: 3^rdbullet item changed from “5 V tolerant inputs” to “5 V tolerant on input

only pins” and added Footnote 1.

• Figure 7 “Internal Loopback mode diagram”:

–

at signals coming out of ‘modem control logic’ block, changed from “OP1A, OP2B” to

“OP1A, OP1B”

• Table 23 “Limiting values”:

symbol V_nsplit to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins”

• Table 24 “Static characteristics”:

–

changed symbol/parameter from “V_IL(CK), LOW-level clock input voltage” to “V_IL(clk), clock

LOW-level input voltage”

changed symbol/parameter from “V_IH(CK), HIGH-level clock input voltage” to “V_IH(clk), clock

HIGH-level input voltage”

changed symbol/parameter from “I_CL, clock leakage” to “I_L(clk), clock leakage current”

• Table 25 “Dynamic characteristics”: added Table note [4] and its reference at t_RESET

• updated soldering information

SC16C2550B_4

SC16C2550B_3

20070215

20050926

20041214

Product data sheet

Product data

-

SC16C2550B_3

SC16C2550B-02

SC16C2550B-01

SC16C2550B-02

(9397 750 14449)

SC16C2550B-01

(9397 750 11982)

20050719

Product data

-

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

41 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

16.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

SC16C2550B_5

Product data sheet

Rev. 05 — 12 January 2009

42 of 43

SC16C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

12.4

13

13.1

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 38

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Soldering of through-hole mount packages. 39

Introduction to soldering through-hole mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Soldering by dipping or by solder wave . . . . . 39

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 39

Package related soldering information. . . . . . 40

3

3.1

4

13.2

13.3

13.4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

14

15

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . 41

6

Functional description . . . . . . . . . . . . . . . . . . . 9

UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9

Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11

Hardware/software and time-out interrupts. . . 11

Programmable baud rate generator . . . . . . . . 12

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 13

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 13

16

Legal information . . . . . . . . . . . . . . . . . . . . . . 42

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.1

6.2

6.3

6.4

6.5

6.6

6.7

16.1

16.2

16.3

16.4

17

18

Contact information . . . . . . . . . . . . . . . . . . . . 42

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 15

Transmit Holding Register (THR) and Receive

Holding Register (RHR) . . . . . . . . . . . . . . . . . 15

Interrupt Enable Register (IER) . . . . . . . . . . . 16

IER versus Transmit/Receive FIFO interrupt

7.2

7.2.1

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17

IER versus Receive/Transmit FIFO polled

7.2.2

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 17

FIFO Control Register (FCR) . . . . . . . . . . . . . 17

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 17

Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 17

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Interrupt Status Register (ISR) . . . . . . . . . . . . 19

Line Control Register (LCR) . . . . . . . . . . . . . . 20

Modem Control Register (MCR) . . . . . . . . . . . 21

Line Status Register (LSR). . . . . . . . . . . . . . . 22

Modem Status Register (MSR). . . . . . . . . . . . 23

Scratchpad Register (SPR) . . . . . . . . . . . . . . 24

SC16C2550B external reset condition . . . . . . 24

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 25

Static characteristics. . . . . . . . . . . . . . . . . . . . 25

Dynamic characteristics . . . . . . . . . . . . . . . . . 26

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 27

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33

9

10

10.1

11

12

Soldering of SMD packages . . . . . . . . . . . . . . 37

Introduction to soldering . . . . . . . . . . . . . . . . . 37

Wave and reﬂow soldering . . . . . . . . . . . . . . . 37

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 37

12.1

12.2

12.3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 January 2009

Document identifier: SC16C2550B_5


型号：	SC16C2550BIBS,128
厂家：	NXP
描述：	SC16C2550B - 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs QFN 32-Pin 通信时钟数据传输先进先出芯片外围集成电路
文件：	总43页 (文件大小：212K)
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