PSMN2R5-30YL_09 [NXP]
N-channel TrenchMOS logic level FET; N沟道的TrenchMOS逻辑电平FET型号: | PSMN2R5-30YL_09 |
厂家: | NXP |
描述: | N-channel TrenchMOS logic level FET |
文件: | 总14页 (文件大小:231K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN2R5-30YL
N-channel TrenchMOS logic level FET
Rev. 03 — 28 December 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
Suitable for logic level gate drive
and conduction losses
sources
1.3 Applications
Class-D amplifiers
Motor control
DC-to-DC converters
Server power supplies
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
Min
Typ
Max Unit
VDS
ID
-
-
-
-
30
V
A
[1]
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1
100
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
88
W
Dynamic characteristics
QGD
gate-drain charge
total gate charge
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14
and 15
-
-
6.5
27
-
-
nC
nC
QG(tot)
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 10 V; ID = 15 A;
Tj = 25 °C
-
1.79 2.4
mΩ
[1] Continuous current is limited by package.
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
S
S
S
G
D
source
source
source
gate
mb
D
2
3
G
4
mbb076
S
mb
mounting base; connected to
drain
1
2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
PSMN2R5-30YL
LFPAK
SOT669
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
30
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
V
VDGR
VGS
-
30
V
-20
20
V
[1]
[1]
ID
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
-
100
100
580
88
A
-
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation Tmb = 25 °C; see Figure 2
storage temperature
-
W
°C
°C
-55
-55
175
175
junction temperature
Source-drain diode
[1]
IS
source current
peak source current
Tmb = 25 °C;
-
-
100
580
A
A
ISM
tp ≤ 10 µs; pulsed; Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 30 V;
-
103
mJ
drain-source avalanche RGS = 50 Ω; unclamped
energy
[1] Continuous current is limited by package.
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
2 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa16
003aac656
120
120
I
D
(A)
(1)
P
der
100
80
60
40
20
0
(%)
80
40
0
0
50
100
150
200
0
50
100
150
200
T
mb
(°C)
T
mb
(°C)
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aac659
103
10 μs
ID
Limit RDSon = VDS / ID
(A)
102
100 μs
10
1
1 ms
DC
10 ms
100 ms
10-1
10-1
1
10
102
VDS (V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
3 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to
mounting base
see Figure 4
-
-
1.4
K/W
003aac657
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
10-1
10-2
10-3
0.1
0.05
0.02
tp
δ =
P
T
single shot
t
tp
T
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
4 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 20 A; VGS = 0 V; Tj = 25 °C; tav= 100 ns
ID = 250 µA; VGS = 0 V; Tj = 25 °C
35
30
27
1.3
-
-
V
V
V
V
-
-
ID = 250 µA; VGS = 0 V; Tj = -55 °C
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS= VGS; Tj = 25 °C; see Figure 11
1.7
2.15
voltage
and 12
ID = 1 mA; VDS= VGS; Tj = 150 °C;
see Figure 12
0.65
-
-
V
ID = 1 mA; VDS= VGS; Tj = -55 °C; see Figure 12
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 15 A; Tj = 25 °C
-
-
-
-
-
-
-
-
2.45
1
V
IDSS
drain leakage current
gate leakage current
-
µA
µA
nA
nA
mΩ
mΩ
-
100
100
100
3.16
4.2
IGSS
-
-
RDSon
drain-source on-state
resistance
2.47
-
VGS = 10 V; ID = 15 A; Tj = 150 °C;
see Figure 13
VGS = 10 V; ID = 15 A; Tj = 25 °C
f = 1 MHz
-
-
1.79
0.67
2.4
1.5
mΩ
RG
gate resistance
Ω
Dynamic characteristics
QG(tot)
total gate charge
ID = 10 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14 and 15
-
27
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
52
57
-
-
nC
nC
ID = 10 A; VDS = 12 V; VGS = 10 V;
see Figure 14 and 15
QGS
gate-source charge
ID = 10 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14 and 15
-
-
8.5
5.7
-
-
nC
nC
QGS(th)
pre-threshold
gate-source charge
QGS(th-pl)
post-threshold
-
2.8
-
nC
gate-source charge
QGD
gate-drain charge
-
-
6.5
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
VDS = 12 V; see Figure 14 and 15
2.35
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C;
see Figure 16
-
-
-
3468
710
-
-
-
pF
pF
pF
reverse transfer
capacitance
314
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
-
-
-
-
39
62
61
25
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
5 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Symbol
Characteristics …continued
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode
VSD
trr
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17
-
-
-
0.79
39
1.2
V
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 20 V
-
-
ns
nC
Qr
38
[1] Tested to JEDEC standards where applicable.
003aac651
003aac653
80
ID
(A)
160
ID
(A)
140
10
4.5
VGS (V) = 3.2
60
120
100
80
60
40
20
0
3
40
20
0
Tj = 150 °C
2.8
2.6
25 °C
2.4
2.2
0
1
2
3
4
0
2
4
6
8
10
VGS (V)
VDS (V)
Fig 6. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 5. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
003aac655
003aac658
140
9
gfs
RDSon
(S)
(mΩ)
120
100
80
7
VGS (V) = 3.2
5
4.5
10
3
1
60
40
0
20
40
60
80
D (A)
0
50
100
150
ID (A)
I
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values
Fig 7. Forward transconductance as a function of
drain current; typical values
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
6 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aac661
003aac654
6000
4
Ciss
RDSon
C
(pF)
(mΩ)
4000
2000
0
3
2
1
Crss
0
2
4
6
8
10
2
4
6
8
10
VGS (V)
V
GS (V)
Fig 10. Drain-source on-state resistance as a function
of gate-source voltage; typical values
Fig 9. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
003aab271
003aac337
10-1
3
ID
(A)
10-2
VGS(th)
(V)
max
min
typ
max
2
10-3
10-4
10-5
10-6
typ
min
1
0
-60
0
1
2
V
GS (V)
3
0
60
120
180
Tj (°C)
Fig 11. Sub-threshold drain current as a function of
gate-source voltage
Fig 12. Gate-source threshold voltage as a function of
junction temperature
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
7 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa27
2
V
DS
a
I
D
1.5
V
GS(pl)
V
GS(th)
1
V
GS
Q
GS1
Q
GS2
0.5
0
Q
GS
Q
GD
Q
G(tot)
003aaa508
−60
0
60
120
180
T ( C)
°
j
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 14. Gate charge waveform definitions
003aac662
003aac660
10
5000
VGS
(V)
C
(pF)
Ciss
8
4000
3000
2000
1000
0
VDS = 19 (V)
VDS = 12 (V)
Coss
6
4
2
0
Crss
0
20
40
60
80
10-1
1
10
102
VDS (V)
Q
G (nC)
Fig 15. Gate-source voltage as a function of gate
charge; typical values
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
8 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aac652
100
IS
(A)
80
60
40
20
0
T = 150 °C
j
25 °C
0.0
0.2
0.4
0.6
0.8
1.0
SD (V)
V
Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
9 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads
SOT669
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e
A
(A )
3
C
A
1
θ
L
detail X
y
C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
D
(1)
D
(1)
(1)
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max
1.20 0.15 1.10
1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10
0.35 3.62 2.0 0.7 0.19 0.24 3.80
5.0 3.3
4.8 3.1
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
8°
0°
mm
0.25
4.20
1.27
0.25 0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-10-13
06-03-16
SOT669
MO-235
Fig 18. Package outline SOT669 (LFPAK)
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
10 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN2R5-30YL_3
Modifications:
20091228
Product data sheet
-
PSMN2R5-30YL_2
• Various changes to content.
PSMN2R5-30YL_2
PSMN2R5-30YL_1
20090105
Product data sheet
-
-
PSMN2R5-30YL_1
-
20080910
Preliminary data sheet
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
11 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
Suitability for use— NXP Semiconductors products are not designed,
9.2 Definitions
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications— Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet— A short data sheet is an extract from a full data sheet with
the same product type number(s) and title. A short data sheet is intended for
quick reference only and should not be relied upon to contain detailed and full
information. For detailed and full information see the relevant full data sheet,
which is available on request via the local NXP Semiconductors sales office.
In case of any inconsistency or conflict with the short data sheet, the full data
sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification— The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Quick reference data— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
9.3 Disclaimers
Limiting values— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability— Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale— NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published athttp://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with theTerms and conditions of commercial saleof NXP Semiconductors.
No offer to sell or license— Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes— NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
12 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
Export control— This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use of
the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products— Unless the data sheet of an NXP
Semiconductors product expressly states that the product is automotive
qualified, the product is not suitable for automotive use. It is neither qualified
nor tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS— is a trademark of NXP B.V.
10. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to:salesaddresses@nxp.com
PSMN2R5-30YL_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 28 December 2009
13 of 14
PSMN2R5-30YL
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 December 2009
Document identifier: PSMN2R5-30YL_3
相关型号:
PSMN2R5-40YLD
N-channel 40 V, 2.6 mΩ, 160 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus technologyProduction
NEXPERIA
PSMN2R6-100SSF
NextPower 100 V, 2.6 mΩ, 200 Amp, N-channel MOSFET in LFPAK88 packageDevelopment
NEXPERIA
PSMN2R6-30YLC
N-channel 30 V 2.8 mΩ logic level MOSFET in LFPAK using NextPower technologyProduction
NEXPERIA
PSMN2R6-30YLC,115
PSMN2R6-30YLC - N-channel 30 V 2.8 mΩ logic level MOSFET in LFPAK using NextPower technology SOIC 4-Pin
NXP
©2020 ICPDF网 联系我们和版权申明