PSMN075-100MSE [NXP]
N-channel 100 V 71 m standard level MOSFET in LFPAK33 designed specifically for PoE applications; N沟道100伏71米标准电平MOSFET在LFPAK33专门针对PoE应用而设计型号: | PSMN075-100MSE |
厂家: | NXP |
描述: | N-channel 100 V 71 m standard level MOSFET in LFPAK33 designed specifically for PoE applications |
文件: | 总13页 (文件大小:365K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3
3
K
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33
designed specifically for PoE applications
A
P
F
L
26 March 2013
Product data sheet
1. General description
New standards and proprietary approaches are enabling the next generation of Power-
over-Ethernet (PoE) systems capable of delivering up to 100W to each powered
device (PD). Large screen LCD displays, 3G / 4G / Wi-Fi hot-spots and pan-tilt-zoom
CCTV cameras, for example, are placing increased demands on the power sourcing
equipment (PSE) in terms of “soft-start” procedures, resilience to short-circuits, thermal
management and power density. Part of NXP’s “NextPower Live” MOSFET portfolio,
the PSMN075-100MSE has been designed specifically to compliment the latest PoE
controllers, offering both superior linear mode operation and very low RDS(on) in a cost-
effective, industry compatible, LFPAK33 package.
2. Features and benefits
Enhanced forward biased safe operating area for superior linear mode operation
Low Rdson for low conduction losses
Ultra reliable LFPAK33 package – no glue, no wires, 175°C
Very low IDSS
•
•
•
•
3. Applications
IEEE802.3at and proprietary solutions - (type 2)
Suitable for PoE applications upto 30W
Use PSMN040-100MSE for higher power requirements
•
•
•
4. Quick reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
100
18
Unit
V
VDS
ID
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj = 25 °C; VGS = 10 V; Fig. 1
-
-
-
-
-
-
A
Ptot
total power dissipation Tmb = 25 °C; Fig. 2
65
W
Static characteristics
RDSon drain-source on-state
resistance
Dynamic characteristics
QGD gate-drain charge
VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12
-
-
57
71
-
mΩ
nC
VGS = 10 V; ID = 5 A; VDS = 50 V;
Tj 25 °C; Fig. 14; Fig. 15
5.3
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NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
QG(tot)
total gate charge
VGS = 10 V; ID = 5 A; VDS = 50 V;
Tj = 25 °C; Fig. 14; Fig. 15
-
16.4
-
nC
Avalanche Ruggedness
EDS(AL)S non-repetitive drain-
VGS = 10 V; Tj(init) = 25 °C; ID = 18 A;
Vsup ≤ 100 V; RGS = 50 Ω; unclamped;
Fig. 3
-
-
25
mJ
source avalanche
energy
5. Pinning information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
D
S
1
S
S
S
G
D
source
source
source
gate
2
G
3
mbb076
4
mb
mounting base; connected to
drain
1
2
3
4
LFPAK33 (SOT1210)
6. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN075-100MSE
LFPAK33
Plastic single ended surface mounted package (LFPAK33); 4
leads
SOT1210
7. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN075-100MSE
M75E10
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
100
100
Unit
drain-source voltage
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
-
V
V
VDGR
PSMN075-100MSE
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Product data sheet
26 March 2013
2 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
Symbol
VGS
Parameter
Conditions
Min
Max
20
Unit
V
gate-source voltage
drain current
-20
ID
VGS = 10 V; Tj = 25 °C; Fig. 1
VGS = 10 V; Tmb = 100 °C; Fig. 1
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4
Tmb = 25 °C; Fig. 2
-
18
A
-
13
A
IDM
peak drain current
-
74
A
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
peak soldering temperature
-
65
W
°C
°C
°C
-55
-55
-
175
175
260
Tsld(M)
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
54
74
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
Avalanche Ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 18 A;
Vsup ≤ 100 V; RGS = 50 Ω; unclamped;
Fig. 3
-
25
mJ
003aak714
03aa16
20
16
12
8
120
I
D
(A)
P
der
(%)
80
40
4
0
0
0
25
50
75 100 125 150 175 200
T (°C)
0
50
100
150
200
j
T
(°C)
mb
Fig. 1. Continuous drain current as a function of
mounting base temperature
Fig. 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN075-100MSE
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© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
3 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
003aak715
2
10
I
AL
(A)
10
(1)
(2)
1
-1
10
-3
-2
-1
10
10
10
1
AL
10
t
(ms)
Fig. 3. Single pulse avalanche rating; avalanche current as a function of avalanche time
003aak716
2
10
I
D
(A)
Limit R
= V / I
DS
DSon
D
t
= 10 us
p
10
100 us
1 ms
DC
1
10 ms
100 ms
-1
10
2
3
1
10
10
10
V
(V)
DS
Fig. 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
2.09
2.32
K/W
PSMN075-100MSE
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© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
4 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
003aak717
10
Z
th(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
t
0.05
p
-1
P
10
10
δ =
T
0.02
single shot
t
t
p
T
-2
-6
-5
-4
-3
-2
-1
10
10
10
10
10
10
1
t
p
(s)
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
100
90
-
-
V
V
V
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
2.3
3.3
4
voltage
Fig. 10; Fig. 11
ID = 1 mA; VDS = VGS; Tj = 175 °C;
Fig. 10
1
-
-
-
-
V
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
Fig. 10
4.6
IDSS
drain leakage current
gate leakage current
VDS = 100 V; VGS = 0 V; Tj = 25 °C
VDS = 100 V; VGS = 0 V; Tj = 175 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12
-
-
-
-
-
-
0.01
-
1
µA
µA
nA
500
100
100
71
IGSS
10
10
57
-
nA
RDSon
drain-source on-state
resistance
mΩ
mΩ
VGS = 10 V; ID = 5 A; Tj = 100 °C;
Fig. 13; Fig. 12
128
VGS = 10 V; ID = 5 A; Tj = 175 °C;
Fig. 13; Fig. 12
-
-
-
192
-
mΩ
Ω
RG
gate resistance
f = 10 MHz
1.55
PSMN075-100MSE
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© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
5 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic characteristics
QG(tot)
total gate charge
ID = 5 A; VDS = 50 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
-
-
16.4
12.9
-
-
nC
nC
ID = 0 A; VDS = 0 V; VGS = 10 V;
Tj = 25 °C
QGS
gate-source charge
ID = 5 A; VDS = 50 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
-
-
3.1
2.1
-
-
nC
nC
QGS(th)
pre-threshold gate-
source charge
QGS(th-pl)
post-threshold gate-
source charge
-
-
1
-
-
nC
nC
QGD
gate-drain charge
ID = 5 A; VDS = 50 V; VGS = 10 V;
Tj 25 °C; Fig. 14; Fig. 15
5.3
VGS(pl)
gate-source plateau
voltage
ID = 5 A; VDS = 50 V; Tj = 25 °C;
Fig. 14; Fig. 15
-
4.3
-
V
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 16
-
-
-
773
66
-
-
-
pF
pF
pF
reverse transfer
capacitance
48
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 50 V; RL = 10 Ω; VGS = 10 V;
RG(ext) = 5 Ω; Tj = 25 °C
-
-
-
-
5.5
-
-
-
-
ns
ns
ns
ns
5.8
turn-off delay time
fall time
12.4
6.2
Source-drain diode
VSD source-drain voltage
trr
IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 17
-
-
-
0.89
35.8
50.7
1.2
V
reverse recovery time IS = 5 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
-
ns
nC
VDS = 50 V; Tj = 25 °C
recovered charge
Qr
PSMN075-100MSE
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© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
6 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
003aak718
003aak719
20
200
R
DSon
6.5 V
I
10 V
8 V
D
(A)
6 V
7 V
16
12
8
160
120
80
40
0
V
= 5.5 V
GS
5 V
4.5 V
44VV
4
0
0
0.5
1
1.5
2
2.5
(V)
3
0
4
8
12
16
(V)
20
V
V
DS
GS
Fig. 6. Output characteristics; drain current as a
function of drain-source voltage; typical values
Fig. 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aak720
003aak721
10
25
g
fs
(S)
I
D
(A)
8
6
4
2
0
20
15
10
5
175°C
3
T = 25°C
j
0
0
2
4
6
8
10
(A)
12
0
1
2
4
5
6
V
7
(V)
8
I
D
GS
Fig. 8. Forward transconductance as a function of
drain current; typical values
Fig. 9. Transfer characteristics; drain current as a
function of gate-source voltage; typical values
PSMN075-100MSE
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© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
7 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
003aak573
003aak574
- 1
- 2
- 3
- 4
- 5
- 6
5
(V)
10
V
GS(th)
I
D
(A)
min
typ max
Max
4
10
10
10
10
10
3
2
1
0
Typ
Min
-60 -30
0
30
60
90 120 150 180
0
2
4
6
T (°C)
j
V
(V)
GS
Fig. 10. Gate-source threshold voltage as a function of
junction temperature
Fig. 11. Sub-threshold drain current as a function of
gate-source voltage
003aak722
003aaj323
160
3
4.5 V
5 V
5.5 V
6 V
R
DSon
a
140
2.4
120
100
80
1.8
1.2
0.6
0
6.5 V
60
7 V 8 V 10 V
40
-60
0
60
120
180
0
4
8
12
16
(A)
20
°
Tj ( C)
I
D
Fig. 12. Drain-source on-state resistance as a function
of drain current; typical values
Fig. 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN075-100MSE
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© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
8 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
003aak723
10
V
V
DS
GS
(V)
I
D
8
V
= 20 V
GS
V
GS(pl)
80 V
6
4
2
0
V
GS(th)
GS
V
50 V
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
003aaa508
Fig. 14. Gate charge waveform definitions
0
4
8
12
16
(nC)
20
Q
G
Fig. 15. Gate-source voltage as a function of gate
charge; typical values
003aak724
003aak725
3
10
20
C
(pF)
I
S
(A)
C
iss
16
12
8
2
10
C
C
oss
rss
175°C
T = 25°C
j
4
10
-1
0
2
10
1
10
10
0
0.2
0.4
0.6
0.8
1
(V)
1.2
V
(V)
V
DS
SD
Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain
as a function of drain-source voltage; typical
values
voltage; typical values
PSMN075-100MSE
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© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
9 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
11. Package outline
Plastic single ended surface mounted package (LFPAK33); 8 leads
SOT1210
A
E
A
e
1
c
1
b
1
E
L
1
mounting
base
D
1
D
H
1
4
e
X
b
w
A
c
A
C
1
θ
Lp
y
C
detail X
0
1
2.5
5 mm
L
scale
Dimensions
(1)
(1)
(1)
Unit
A
A
b
b
c
c
D
D
1
E
E
1
e
e
1
H
L
p
w
y
θ
1
1
°
max 0.90 0.10 0.35 0.35 0.20 0.30 2.70 2.35 3.40 2.45
nom
3.40 0.25 0.50
3.20 0.13 0.30
8
0
mm
0.65 0.65
0.20 0.10
°
0.80 0.00 0.25 0.25 0.10 0.20 2.50 1.90 3.20 2.00
min
Note
1. Plastic or metal protrusions of 0.15 mm per side are not included.
sot1210_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
11-12-19
12-03-12
SOT1210
Fig. 18. Package outline LFPAK33 (SOT1210)
PSMN075-100MSE
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© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
10 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
12. Legal information
12.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
Product
Definition
status [1][2] status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preliminary
[short] data
sheet
Qualification This document contains data from the
preliminary specification.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
12.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
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applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
12.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
PSMN075-100MSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
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NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN075-100MSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
12 / 13
NXP Semiconductors
PSMN075-100MSE
N-channel 100 V 71 mΩ standard level MOSFET in LFPAK33 designed
specifically for PoE applications
13. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
Applications ........................................................... 1
Quick reference data ............................................. 1
Pinning information ...............................................2
Ordering information .............................................2
Marking ...................................................................2
Limiting values .......................................................2
Thermal characteristics .........................................4
Characteristics .......................................................5
Package outline ................................................... 10
3
4
5
6
7
8
9
10
11
12
Legal information .................................................11
Data sheet status ............................................... 11
Definitions ...........................................................11
Disclaimers .........................................................11
Trademarks ........................................................ 12
12.1
12.2
12.3
12.4
© NXP B.V. 2013. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 March 2013
PSMN075-100MSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
26 March 2013
13 / 13
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