PSMN015-100B,118 [NXP]
N-channel TrenchMOS SiliconMAX standard level FET D2PAK 3-Pin;型号: | PSMN015-100B,118 |
厂家: | NXP |
描述: | N-channel TrenchMOS SiliconMAX standard level FET D2PAK 3-Pin |
文件: | 总12页 (文件大小:191K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN015-100B
N-channel TrenchMOS SiliconMAX standard level FET
Rev. 06 — 17 December 2009
Product data sheet
1. Product profile
1.1 General description
SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in
a plastic package using TrenchMOS technology. This product is designed and qualified for
use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
Rated for avalanche ruggedness
Switched-mode power supplies
on-state resistance
1.3 Applications
DC-to-DC convertors
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
Min
Typ
Max Unit
VDS
ID
-
-
-
-
100
75
V
A
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1 and 3
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
-
300
-
W
Dynamic characteristics
QGD gate-drain charge
VGS = 10 V; ID = 75 A;
VDS = 80 V; Tj = 25 °C;
see Figure 11
35
nC
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 10 V; ID = 25 A;
Tj = 25 °C;
-
12
15
mΩ
see Figure 9 and 10
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
2. Pinning information
Table 2.
Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
G
D
S
D
gate
mb
D
[1]
2
drain
source
3
G
mb
mounting base; connected to
drain
mbb076
S
2
1
3
SOT404 (D2PAK)
[1] It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN015-100B
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads (one
lead cropped)
SOT404
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≤ 175 °C; Tj ≥ 25 °C; RGS = 20 kΩ
-
100
100
20
V
VDGR
VGS
-
V
-20
V
ID
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1 and 3
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
-
60.8
75
A
-
A
IDM
Ptot
Tstg
Tj
peak drain current
-
240
300
175
175
A
total power dissipation Tmb = 25 °C; see Figure 2
storage temperature
-
W
°C
°C
-55
-55
junction temperature
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
75
A
A
ISM
tp ≤ 10 µs; pulsed; Tmb = 25 °C
240
Avalanche ruggedness
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 36 A; Vsup ≤ 50 V;
-
320
mJ
drain-source avalanche unclamped; tp = 0.11 ms; RGS = 50 Ω
energy
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
2 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
03an67
03aa16
120
120
P
(%)
I
der
der
(%)
80
80
40
40
0
0
0
50
100
150
200
(°C)
0
50
100
150
200
T
mb
T
mb
(°C)
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
03am53
3
10
I
D
Limit R
= V /I
DS D
DSon
(A)
t
= 10 s
μ
p
2
10
100
s
μ
DC
10
1 ms
10 ms
1
2
3
1
10
10
10
V
DS
(V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
3 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from see Figure 4
junction to mounting
base
-
-
0.5
K/W
Rth(j-a)
thermal resistance from mounted on a printed-circuit board;
-
50
-
K/W
junction to ambient
minimum footprint; vertical in still air
03am52
10
Z
th(j-mb)
(K/W)
1
= 0.5
δ
−1
−2
−3
10
10
10
0.2
0.1
t
p
0.05
P
δ =
T
0.02
single pulse
t
t
p
T
−5
−4
−3
−2
−1
10
10
10
10
10
t
p
(s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
4 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
89
100
1
-
-
-
-
-
-
V
V
V
VGS(th)
gate-source threshold ID = 1 mA; VDS= VGS; Tj = 175 °C;
voltage
see Figure 8
ID = 1 mA; VDS= VGS; Tj = -55 °C;
see Figure 8
-
-
4.4
4
V
V
ID = 1 mA; VDS= VGS; Tj = 25 °C;
see Figure 8
2
3
IDSS
drain leakage current
gate leakage current
VDS = 100 V; VGS = 0 V; Tj = 25 °C
VDS = 100 V; VGS = 0 V; Tj = 175 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
0.05
10
µA
µA
nA
nA
mΩ
-
500
100
100
40.5
IGSS
2
2
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 9 and 10
32.4
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 9 and 10
-
12
15
mΩ
Dynamic characteristics
QG(tot)
QGS
QGD
Ciss
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
ID = 75 A; VDS = 80 V; VGS = 10 V;
Tj = 25 °C; see Figure 11
-
-
-
-
-
-
90
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
20
35
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 12
4900
390
220
Coss
Crss
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 50 V; RL = 1.8 Ω; VGS = 10 V;
RG(ext) = 5.6 Ω; Tj = 25 °C
-
-
-
-
25
65
95
50
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 13
-
0.8
1.1
V
trr
reverse recovery time
recovered charge
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 25 V; Tj = 25 °C
-
-
80
-
-
ns
Qr
115
nC
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
5 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
03am56
03am54
80
50
I
10 V 6 V 5.6 V 5.4 V
V
> I x R
D DSon
T = 25 C
°
D
DS
j
I
D
(A)
(A)
40
5.2 V
5 V
60
30
20
10
0
40
20
0
4.8 V
4.6 V
4.4 V
175 °C
T = 25 °C
j
V
= 4.2 V
GS
0
0.2
0.4
0.6
0.8
1
(V)
0
2
4
6
V
V
(V)
DS
GS
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
03aa35
03aa32
−1
10
5
I
V
D
GS(th)
(V)
(A)
min
typ
max
−2
−3
−4
−5
−6
10
10
10
10
10
4
max
3
typ
2
min
1
0
0
2
4
6
−60
0
60
120
180
V
GS
(V)
T (°C)
j
Fig 7. Sub-threshold drain current as a function of
gate-source voltage
Fig 8. Gate-source threshold voltage as a function of
junction temperature
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
6 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
03am55
03al21
3
30
V
= 5 V
GS
T = 25 C
°
j
R
DSon
a
5.2 V
(m
)
Ω
2
20
10
0
5.4 V
5.6 V
6 V
10 V
1
0
0
10
20
30
40
50
-60
0
60
120
180
I
(A)
Tj (°C)
D
Fig 9. Drain-source on-state resistance as a function
of drain current; typical values
Fig 10. Normalized drain-source on-state resistance
factor as a function of junction temperature
03am59
03am58
4
10
10
V
I = 75 A
D
GS
(V)
C
(pF)
°
T = 25 C
V
= 20 V
C
j
DD
iss
8
6
4
2
0
80 V
3
10
C
C
oss
rss
2
10
0
25
50
75
100
−1
2
10
1
10
10
V
(V)
Q
(nC)
DS
G
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
7 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
03am57
100
V
= 0 V
GS
I
S
(A)
75
50
25
0
175 °C
T = 25 °C
j
0
0.3
0.6
0.9
1.2
(V)
V
SD
Fig 13. Source current as a function of source-drain voltage; typical values
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
8 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
7. Package outline
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-02-11
06-03-16
SOT404
Fig 14. Package outline SOT404 (D2PAK)
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
9 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN015-100B_6
Modifications:
20091217
Product data sheet
-
PSMN015_100P_100B-05
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Type number PSMN015-100B separated from data sheet PSMN015_100P_100B-05.
PSMN015_100P_100B-05
(9397 750 12543)
20040114
Product data
-
-
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
10 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
9. Legal information
9.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
Applications— Applications that are described herein for any of these
9.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet— A short data sheet is an extract from a full data sheet with
the same product type number(s) and title. A short data sheet is intended for
quick reference only and should not be relied upon to contain detailed and full
information. For detailed and full information see the relevant full data sheet,
which is available on request via the local NXP Semiconductors sales office.
In case of any inconsistency or conflict with the short data sheet, the full data
sheet shall prevail.
Terms and conditions of sale— NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
athttp://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3 Disclaimers
General— Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license— Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes— NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control— This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use— NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS— is a trademark of NXP B.V.
10. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to:salesaddresses@nxp.com
PSMN015-100B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 17 December 2009
11 of 12
PSMN015-100B
NXP Semiconductors
N-channel TrenchMOS SiliconMAX standard level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 December 2009
Document identifier: PSMN015-100B_6
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