PPC5777MK0MVA8B_技术文档

NXP Semiconductors

Data Sheet: Technical Data

Document Number: MPC5777M

Rev. 6, 06/2016

MPC5777M

416 TEPBGA

27mm x 27 mm

512 TEPBGA

MPC5777M Microcontroller

Data Sheet

25 mm x 25 mm

• Three main CPUs, single issue, 32-bit CPU core complexes

(e200z7), one of which is a dedicated lockstep core.

– Dual phase-locked loops with stable clock domain for

peripherals and FM modulation domain for

computational shell

®

– Power Architecture embedded specification

compliance

• Dual crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters with

end-to-end ECC

• Hardware Security Module (HSM) to provide robust

integrity checking of flash memory

• System Integration Unit Lite (SIUL)

• Boot Assist Module (BAM) supports factory programming

using serial bootload through ‘UART Serial Boot Mode

Protocol’. Physical interface (PHY) can be:

– UART/LIN

– Instruction set enhancement allowing variable length

encoding (VLE), encoding a mix of 16-bit and 32-bit

instructions, for code size footprint reduction

– Single-precision floating point operations

– 16 KB Local instruction RAM and 64 KB local data

RAM

– 16 KB I-Cache and 4 KB D-Cache

• I/O Processor, dual issue, 32-bit CPU core complex

(e200z4), with

– Power Architecture embedded specification compliance

– Instruction set enhancement allowing variable length

encoding (VLE), encoding a mix of 16-bit and 32-bit

instructions, for code size footprint reduction

– Single-precision floating point operations

– Lightweight Signal Processing Auxiliary Processing

Unit (LSP APU) instruction support for digital signal

processing (DSP)

– CAN

• GTM104 — generic timer module

• Enhanced analog-to-digital converter system with

– Twelve separate 12-bit SAR analog converters

– Ten separate 16-bit Sigma-Delta analog converters

• Eight deserial serial peripheral interface (DSPI) modules

• Two Peripheral Sensor Interface (PSI5) controllers

• Three LIN and three UART communication interface

(LINFlexD) modules (6 total)

– 16 KB Local instruction RAM and 64 KB local data

RAM

– LINFlexD_0 is a Master/Slave

– 8 KB I-Cache

• 8640 KB on-chip flash

– LINFlexD_1, LINFlexD_2, LINFlexD_14,

LINFlexD_15, and LINFlexD_16 are Masters

• Four modular controller area network (MCAN) modules

and one time-triggered controller area network

(M-TTCAN)

– Supports read during program and erase operations, and

multiple blocks allowing EEPROM emulation

• 404 KB on-chip general-purpose SRAM including 64 KB

standby RAM (+ 192 KB data RAM included in the

CPUs). Of this 404 KB, 64 KB can be powered by a

separate supply so the contents of this portion can be

preserved when the main MCU is powered down.

• Multichannel direct memory access controllers (eDMA): 2

x 64 channels per eDMA (128 channels total)

• Triple Interrupt controller (INTC)

• External Bus Interface (EBI)

– Dual routing of accesses to EBI

– Access path determined by access address

– Access path downstream of PFLASH controller

– Allows EBI accesses to share buffer and prefetch

capabilities of internal flash

– Allows internal flash accesses to be remapped to

memories connected to EBI

NXP reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

Table of Contents

1

2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3.14.2 Power management integration . . . . . . . . . . . . 75

3.14.3 3.3 V flash supply. . . . . . . . . . . . . . . . . . . . . . . 76

3.14.4 Device voltage monitoring . . . . . . . . . . . . . . . . 77

3.14.5 Power up/down sequencing. . . . . . . . . . . . . . . 79

3.15 Flash memory electrical characteristics. . . . . . . . . . . . 80

3.15.1 Flash memory program and erase

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3 Device feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Package pinouts and signal descriptions . . . . . . . . . . . . . . . .10

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.2 Pin/ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2.1 Power supply and reference voltage pins/balls .15

2.2.2 System pins/balls. . . . . . . . . . . . . . . . . . . . . . . .16

2.2.3 LVDS pins/balls . . . . . . . . . . . . . . . . . . . . . . . . .17

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21

3.3 Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . .23

3.4 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.5 DC electrical specifications. . . . . . . . . . . . . . . . . . . . . .27

3.6 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.6.1 I/O input DC characteristics. . . . . . . . . . . . . . . .31

3.6.2 I/O output DC characteristics. . . . . . . . . . . . . . .35

3.7 I/O pad current specification . . . . . . . . . . . . . . . . . . . . .42

3.8 Reset pad (PORST, ESR0) electrical characteristics . .45

3.9 Oscillator and FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . .48

3.10 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

3.10.1 ADC input description . . . . . . . . . . . . . . . . . . . .53

3.10.2 SAR ADC electrical specification. . . . . . . . . . . .54

3.10.3 S/D ADC electrical specification . . . . . . . . . . . .58

3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.12 LVDS Fast Asynchronous Serial Transmission

specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.15.2 Flash memory FERS program and

erase specifications . . . . . . . . . . . . . . . . . . . . . 82

3.15.3 Flash memory Array Integrity and Margin

Read specifications . . . . . . . . . . . . . . . . . . . . . 83

3

3.15.4 Flash memory module life specifications . . . . . 84

3.15.5 Data retention vs program/erase cycles. . . . . . 84

3.15.6 Flash memory AC timing specifications . . . . . . 85

3.15.7 Flash read wait state and address pipeline

control settings. . . . . . . . . . . . . . . . . . . . . . . . . 85

3.16 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.16.1 Debug and calibration interface timing. . . . . . . 86

3.16.2 DSPI timing with CMOS and LVDS pads . . . . . 94

3.16.3 FEC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.16.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . 115

3.16.5 PSI5 timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 118

3.16.6 UART timing. . . . . . . . . . . . . . . . . . . . . . . . . . 118

3.16.7 External Bus Interface (EBI) Timing. . . . . . . . 119

3.16.8 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3.16.9 GPIO delay timing . . . . . . . . . . . . . . . . . . . . . 124

3.16.10Package characteristics. . . . . . . . . . . . . . . . . 124

3.17 416 TEPBGA (production) case drawing . . . . . . . . . 125

3.18 416 TEPBGA (emulation) case drawing. . . . . . . . . . 127

3.19 512 TEPBGA case drawing . . . . . . . . . . . . . . . . . . . 130

3.20 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . 132

3.20.1 General notes for specifications at

(LFAST) pad electrical characteristics . . . . . . . . . . . . .67

3.12.1 LFAST interface timing diagrams . . . . . . . . . . .68

3.12.2 LFAST and MSC/DSPI LVDS interface

electrical characteristics . . . . . . . . . . . . . . . . . .69

maximum junction temperature . . . . . . . . . . . 132

3.12.3 LFAST PLL electrical characteristics . . . . . . . . .72

3.13 Aurora LVDS electrical characteristics . . . . . . . . . . . . .73

3.14 Power management: PMC, POR/LVD, sequencing . . .75

3.14.1 Power management electrical characteristics . .75

4

5

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 137

MPC5777M Microcontroller Data Sheet, Rev. 6

2

NXP Semiconductors

— Access path via dedicated AXBS slave port

Avoids contention with other memory accesses

–

•

Two Dual-channel FlexRay controllers

Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard

Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)

Self-test capability

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

3

Introduction

1

Introduction

1.1

Document overview

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5777M series of

microcontroller units (MCUs). For functional characteristics, see the MPC5777M Microcontroller Reference Manual.

1.2

Description

This family of MCUs is targeted at automotive powertrain controller and chassis control applications from single cylinder

motorcycles at the very bottom end; through 4 to 8 cylinder gasoline and diesel engines; transmission control; steering and

breaking applications; to high end hybrid and advanced combustion systems at the top end.

Many of the applications are considered to be functionally safe and the family is designed to achieve ISO26262 ASIL-D

compliance.

1.3

Device feature

Table 1. MPC5777M feature

Feature

MPC5777M

Process

Main processor

55 nm

Core

e200z7

Number of main cores

2

1

Number of checker cores

Local RAM (per main core)

16 KB Instruction

64 KB Data

Single precision floating point

Yes

No

LSP

VLE

Yes

Cache

16 KB Instruction

4 KB Data

I/O processor

Core

e200z4

Local RAM

16 KB instruction

64 KB Data

Single precision floating point

Yes

LSP

Yes

VLE

Cache

8 KB instruction

300 MHz¹

200 MHz

0

Main processor frequency

I/O processor frequency

MMU entries

MPU

Yes

Semaphores

Yes

MPC5777M Microcontroller Data Sheet, Rev. 6

4

NXP Semiconductors

Introduction

Table 1. MPC5777M feature (continued)

Feature

MPC5777M

CRC channels

2

Software watchdog timer

(Task SWT/Safety SWT)

4 (3/1)

Core Nexus class

3+

Sequence processing unit (SPU)

Yes

Debug and calibration interface (DCI) / run control

module

System SRAM

404 KB

8640 KB

4  256 bit

Flash memory

Flash memory fetch accelerator

Data flash memory (EEPROM)

8  64 KB

+ 2  16 KB

Flash memory overlay RAM

External bus

16 KB

32 bit

Calibration interface

DMA channels

64-bit IPS Slave

2  64

DMA Nexus Class

LINFlex (UART/MSC)

MCAN/TTCAN

3+

6 (3/3)

4/1

DSPI

8 (4/3/1)

(SPI/MSC/sync SCI)

Microsecond bus downlink

Yes

SENT bus

15

I²C

2

5

PSI5 bus

PSI5-S UART-to-PSI5 interface

Yes

FlexRay

2  dual channel

MII / RMII

High speed

Ethernet

Zipwire^(SIPI / LFAST²) Interprocessor Communication

Interface

System timers

8 PIT channels

3 AUTOSAR (STM)

®

64-bit PIT

Yes

BOSCH^GTM Timer³

GTM RAM

58 KB

Interrupt controller

ADC (SAR)

727 sources

12

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

5

Introduction

Table 1. MPC5777M feature (continued)

Feature

MPC5777M

ADC (SD)

10

Temperature sensor

Self test controller

PLL

Yes

Dual PLL with FM

None

Integrated linear voltage regulator

External power supplies

5 V

3.3 V⁷

1.2 V

Low-power modes

Packages

Stop mode

Slow mode

• 416 TEPBGA⁴

• 512 TEPBGA⁵

1

Includes four user-programmable CPU cores and one safety core. The main computational shell consists of

dual e200z7 CPUs operating at 300 MHz with a third identical core running as a safety checker core in delayed

lockstep mode with one of the dual e200z7 cores. The I/O subsystem includes a CPU targeted at managing

the peripherals. This is an e200z4 CPU running at 200 MHz. The fifth CPU is an e200z0 running at 100 MHz

and is embedded in the Hardware Security Module. All CPUs are compatible with the Power Architecture.

2

3

4

5

LVDS Fast Asynchronous Serial Transmission

BOSCH^®is a registered trademark of Robert Bosch GmbH.

416 TEPBGA package supports development and production applications with the same package footprint.

512 TEPBGA package supports development and production applications with the same package footprint.

MPC5777M Microcontroller Data Sheet, Rev. 6

6

NXP Semiconductors

Package pinouts and signal descriptions

EBI

TDM

PCM

LVIIO

2 x XBIC

2 x AXBS

2 x SMPU

PRAM

LVIFLASH

LVI 1.2V

HVI 1.2V

PFLASH

SEMA4

INTC_0

4 x SWT

3 x STM

2 x DMA

FEC

PMC

TSENS

IIC_1

FLEXRAY_1

9 x SAR ADC

PSI5_1

12 x CMU

BAF

SSCM

PSI5_S_0

CRC_1

SENT_1

GTM

3 x SAR ADC

PSI5_0

3 x DSPI

FCCU

PASS

Peripheral Bus (AIPS_1)

CFLASH_0

2 x LFAST

FLEXRAY_0

SENT_0

2 x LINFlexD

5 x SD ADC

2 x SIPI

SUIL2

Peripheral

Cluster B

IIC_0

ME

5 x DSPI

CMU_PLL

PLL

4 x LINFlexD

4 x MCAN

TTCAN_0

SRAM CAN

5 x SD ADC

HSM INTERFACE

DTS

OSC_DIG

RCOSC_DIG_0

CGM

RGM

PCU

Peripheral

Cluster A

JDC

WKPU

Peripheral Bus (AIPS_0)

STCU2

JTAGM

MEMU

IMA

CRC_0

10 x DMAMUX

ATX

2 x PIT_RTC

Figure 2. Periphery allocation

2

Package pinouts and signal descriptions

See the MPC5777M Microcontroller Reference Manual for signal information.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

9

Package pinouts and signal descriptions

2.2

Pin/ball descriptions

The following sections provide signal descriptions and related information about device functionality and configuration.

2.2.1

Power supply and reference voltage pins/balls

Table 2 contains information on power supply and reference pin functions for the devices.

NOTE

All ground supplies must be tied to ground. They can NOT float.

Table 2. Power supply and reference pins

Supply

BGA ball

416ED 512PD

Symbol

Type

Ground

Description

416PD

512ED

V_{SS_HV}

High voltage ground

A26, B25, C24, D23, B2, B29, B30, F6,

D15, D8, J4, L23, F25, G7, G24, H29,

R23,T4, W23, AC23, H30, J9, J22, K10,

AC19

K21,V29, AA21,

AB22, AD24, AE25,

AJ10, AJ29, AK10

V_{SS_LV}

Ground

Low voltage ground

K10, K11, K12, K13,

K14, K15, K16, K17,

M14, M15, M16,

M17, N14, N15,

L10, L11, L12, L13, N16, N17, P12, P13,

L14, L15, L16, L17, P15, P16, P18, P19,

M10, M11, M12,

M13, M14, M15,

R13, R14, R15,

R16, R17, R18,

M16, M17, N10, N11, T13,T14, T15, T16,

N12, N13, N14,

N15,N 16, N17, P11,

T17, T18, U12, U13,

U 15, U16, U18,

P12, P13, P14, P15, U19, V14, V15 V16,

P16, R 11, R12, R13,

R14, R15, R16, T10,

T11, T12, T13, T14,

T15, T16, T17

V17, W14, W17

V_{DD_LV}

Power

Low voltage power supply for

production device

(PLL is also powered by this pin.)

B26, C25, D9, D24,

E23, H4, P23, V23,

AB23, AC20

M18, N19, V12,

V19, W13, W18

V_{DD_LV_BD}

Power

Low voltage power supply for

buddy die

—

R1, R4

—

M13,

N12

V_{DD_HV_PMC}

V_{DD_HV_IO_MAIN}

High voltage power supply for

internal power management unit

D14

—

High voltage power supply for I/O A25, B24, C23, D22, A2, A29, B3, B28,

K4, AC16, AD16,

AE16, AF16

F7, F24, G8, G23,

AC24, AD25, AH29,

AJ30

V_{DD_HV_IO_BD}

Power

High voltage power supply for

buddy die I/O

—

P17

—

R19

V_{SS_HV_OSC}

V_{DD_HV_JTAG}

Ground

Power

Oscillator ground supply

F25

E26

T25

V25

JTAG/Oscillator power supply

MPC5777M Microcontroller Data Sheet, Rev. 6

14

NXP Semiconductors

Package pinouts and signal descriptions

Table 2. Power supply and reference pins (continued)

Supply

BGA ball

Symbol

Type

Power

Description

416PD

416ED

512PD

J10

512ED

V_{DD_HV_IO_FLEX}

FlexRay/Ethernet 3.3 V I/O

supply

D7

V_{DD_HV_IO_FLEXE}

V_{DD_HV_IO_EBI}

Power

FLexRay/Ethernet/EBI I/O

Segment Voltage Supply

AC18, AC22

M23,T23,Y23

AJ11, AK11, AK20,

AK29

EBIAddress/ControlI/OSegment

Voltage Supply

J29, J30, V30, AH30

V_{DD_HV_FLA}

Power

Decoupling supply pin for flash

Ground supply for ADC SAR

Voltage supply for ADC SAR

Ground supply for ADC SD

Voltage supply for ADC SD

Ground reference for ADC SAR

Voltage reference for ADC SAR

Ground reference for ADC SD

Voltage reference for ADC SD

Standby RAM supply

A18, B18

AF9

J21, K20

AE9, AJ8

AE10, AJ9

AK8

V_{SS_HV_ADV_S}

V_{DD_HV_ADV_S}

V_{SS_HV_ADV_D}

V_{DD_HV_ADV_D}

V_{SS_HV_ADR_S}

V_{DD_HV_ADR_S}

V_{SS_HV_ADR_D}

V_{DD_HV_ADR_D}

V_DDSTBY

Ground

Power

AE9

Ground

Power

AF5

AE5

AK9

Reference

Power

AE8

AE12

AF8

AE11

Y4, AC6

W4, AD6

AD9

AA7

AA6

AA16

2.2.2

System pins/balls

Table 3 contains information on system pin functions for the devices.

Table 3. System pins

BGA ball

416PD 416ED 512PD 512ED

Symbol

Description

Direction

PORST

Power on reset with Schmitt trigger

characteristics and noise filter. PORST is

active low

Bidirectional

B22

A23

B23

M22

L21

N24

ESR0

External functional reset with Schmitt

trigger characteristics and noise filter.

ESR0 is active low

Bidirectional

Input only

TESTMODE Pin for testing purpose only. TESTMODE

pull-down is implemented to prevent the

device from entering TESTMODE. It is

recommended to connect the

TESTMODE pin to VSS_HV_IO on the

board. The value of the TESTMODE pin

is latched at the negation of reset and has

no affect afterward.

Note: The device will not exit reset with

the TESTMODE pin asserted

during power-up.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

15

Package pinouts and signal descriptions

Table 3. System pins (continued)

Description Direction

BGA ball

Symbol

416PD 416ED 512PD 512ED

XTAL

Analog output of the oscillator amplifier

Output

G25

U24

circuit

needs to be grounded if oscillator is used

in bypass mode.

EXTAL

Analog input of the oscillator amplifier

circuit when oscillator is not in bypass

mode

Input

G26

U25

Analog input for the clock generator when

oscillator is in bypass mode

2.2.3

LVDS pins/balls

The following table contains information on LVDS pin functions for the devices.

Table 4. LVDS pin descriptions

BGA ball

(416 PD,

416 ED)

BGA ball

(512 PD,

512 ED)

Functional block Port pin

Signal

Signal description

SIPI / LFAST¹

PA[14]

PD[6]

PD[7]

PF[13]

SIPI_TXP

Interprocessor Bus LFAST,

LVDS Transmit Positive

Terminal

O

I

C26

D26

G23

H23

P25

R25

P24

R24

SIPI_TXN

SIPI_RXP

SIPI_RXN

Interprocessor Bus LFAST,

LVDS Transmit Negative

Terminal

Interprocessor Bus LFAST,

LVDS Receive Positive

Terminal

Interprocessor Bus LFAST,

LVDS Receive Negative

Terminal

I

High-Speed

Debug (HSD) /

LFAST^1,2

PA[7]

PA[8]

PA[9]

PA[5]

DEBUG_TXP Debug LFAST, LVDS

Transmit Positive Terminal

O

I

F24

E25

D25

F23

R21

N22

N21

T24

DEBUG_TXN Debug LFAST, LVDS

Transmit Negative Terminal

DEBUG_RXP Debug LFAST, LVDS Receive

Positive Terminal

DEBUG_RXN Debug LFAST, LVDS Receive

Negative Terminal

I

MPC5777M Microcontroller Data Sheet, Rev. 6

16

NXP Semiconductors

Package pinouts and signal descriptions

Table 4. LVDS pin descriptions (continued)

BGA ball

(416 PD,

416 ED)

BGA ball

(512 PD,

512 ED)

Functional block Port pin

Signal

Signal description

DSPI 4

Microsecond Bus

PD[2]

PD[3]

PD[0]

PD[1]

PF[10]

PF[9]

SCK_P

DSPI 4 Microsecond Bus

Serial Clock, LVDS Positive

Terminal

O

C18

C17

C16

D17

J24

K23

J26

J25

A17

B17

B16

A16

F17

G17

F16

G16

W24

W25

Y24

Y25

A16

B16

A15

B15

SCK_N

SOUT_P

SOUT_N

SCK_P

DSPI 4 Microsecond Bus

Serial Clock, LVDS Negative

Terminal

DSPI 4 Microsecond Bus

Serial Data, LVDS Positive

Terminal

DSPI 4 Microsecond Bus

Serial Data, LVDS Negative

Terminal

DSPI 5

Microsecond Bus

DSPI 5 Microsecond Bus

Serial Clock, LVDS Positive

Terminal

SCK_N

DSPI 5 Microsecond Bus

Serial Clock, LVDS Negative

Terminal

PF[12]

PF[11]

PQ[9]

PQ[8]

PQ[11]

PQ[10]

SOUT_P

SOUT_N

SCK_P

DSPI 5 Microsecond Bus

Serial Data, LVDS Positive

Terminal

DSPI 5 Microsecond Bus

Serial Data, LVDS Negative

Terminal

DSPI 6

Microsecond Bus

DSPI 6Microsecond Bus

Serial Clock, LVDS Positive

Terminal

SCK_N

DSPI 6 Microsecond Bus

Serial Clock, LVDS Negative

Terminal

SOUT_P

SOUT_N

DSPI 6 Microsecond Bus

Serial Data, LVDS Positive

Terminal

DSPI 6 Microsecond Bus

Serial Data, LVDS Negative

Terminal

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

17

Package pinouts and signal descriptions

Table 4. LVDS pin descriptions (continued)

BGA ball

(416 PD,

416 ED)

BGA ball

(512 PD,

512 ED)

Functional block Port pin

Signal

Signal description

Differential DSPI

2

PD[2]

PD[3]

PD[0]

SCK_P

SCK_N

SOUT_P

Differential DSPI 2 Clock,

LVDS Positive Terminal

O

C18

C17

C16

F17

G17

F16

Differential DSPI 2 Clock,

LVDS Negative Terminal

Differential DSPI 2 Serial

Output, LVDS Positive

Terminal

PD[1]

SOUT_N

Differential DSPI 2 Serial

Output, LVDS Negative

Terminal

O

D17

G16

PD[7]

SIN_P

SIN_N

Differential DSPI 2 Serial

Input, LVDS Positive Terminal

I

G23

H23

P24

R24

PF[13]

Differential DSPI 2 Serial

Input, LVDS Negative

Terminal

Differential DSPI

5

PF[10]

PF[9]

SCK_P

SCK_N

SOUT_P

Differential DSPI 5 Clock,

LVDS Positive Terminal

O

J24

K23

J26

W24

W25

Y24

Differential DSPI 5 Clock,

LVDS Negative Terminal

PF[12]

Differential DSPI 5 Serial

Output, LVDS Positive

Terminal

PF[11]

SOUT_N

Differential DSPI 5 Serial

Output, LVDS Negative

Terminal

O

J25

Y25

PD[7]

SIN_P

SIN_N

Differential DSPI 5 Serial

Input, LVDS Positive Terminal

I

G23

H23

P24

R24

PF[13]

Differential DSPI 5 Serial

Input, LVDS Negative

Terminal

PI[15]

PI[14]

SIN_P

SIN_N

Differential DSPI 5 Serial

Input, LVDS Positive Terminal

I

G24

J23

P22

R22

Differential DSPI 5 Serial

Input, LVDS Negative

Terminal

1

2

DRCLK and TCK/DRCLK usage for SIPI LFAST and Debug LFAST are described in the MPC5777M

Microcontroller Reference Manual SIPI LFAST and Debug LFAST chapters.

Pads use special enable signal form DCI block: DCI driven enable for Debug LFAST pads is transparent to user.

MPC5777M Microcontroller Data Sheet, Rev. 6

18

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Aurora pin descriptions

Signal Description

BGA

Functional

Block

PAD

Signal

416PD

416ED

512PD 512ED

Nexus Aurora

High Speed

Trace

—

TX0P Nexus Aurora High Speed

Trace Lane 0, LVDS Positive

Terminal

O

I

—

U15

—

AB19

AB18

AB17

AB16

W16

W15

R12

—

TX0N Nexus Aurora High Speed

Trace Lane 0, LVDS Negative

Terminal

U14

U13

U12

U11

U10

P10

R10

U17

U16

TX1P Nexus Aurora High Speed

Trace Lane 1, LVDS Positive

Terminal

TX1N Nexus Aurora High Speed

Trace Lane 1, LVDS Negative

Terminal

TX2P Nexus Aurora High Speed

Trace Lane 2, LVDS Positive

Terminal

TX2N Nexus Aurora High Speed

Trace Lane 2, LVDS Negative

Terminal

TX3P Nexus Aurora High Speed

Trace Lane 3, LVDS Positive

Terminal

TX3N Nexus Aurora High Speed

Trace Lane 3, LVDS Negative

Terminal

T12

CLKP Nexus Aurora High Speed

(BD-AGB Trace Clock, LVDS Positive

TCLKP) Terminal

AB21

AB20

CLKN Nexus Aurora High Speed

(BD-AGB Trace Clock, LVDS Negative

TCLKN) Terminal

I

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

19

Electrical characteristics

3

Electrical characteristics

3.1

Introduction

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” (Controller

Characteristics) is included in the “Symbol” column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol

“SR” (System Requirement) is included in the “Symbol” column.

NOTE

Within this document, V

refers to supply pins V

,

DD_HV_IO

DD_HV_IO_MAIN

V

, V

V

, V

, and

DD_HV_IO_JTAG DD_HV_IO_FLEX, DD_HV_IO_FLEXE

DD_HV_IO_EBI

. V

refers to ADC supply pins V and

refers to ADC reference pins V

refers to ADC ground pins V

DD_HV_FLA

DD_HV_ADV

DD_HV_ADV_S

. V

and

DD_HV_ADR_S

DD_HV_ADV_D

DD_HV_ADR

and

DD_HV_ADR_D

SS_HV_ADV

SS_HV_ADV_S

. V

.

refers to ADC reference pins V

and

SS_HV_ADV_D

SS_HV_ADR_D

SS_HV_ADR

SS_HV_ADR_S

3.2

Absolute maximum ratings

Table 6 describes the maximum ratings of the device.

1

Table 6. Absolute maximum ratings

Value

Symbol

Parameter

Conditions

Unit

Min

Max

Cycle

V_{DD_LV}

SR Lifetime power cycles

—

1000 k

1.5

—

V

SR 1.2 V core supply voltage^2,3,4

SR Emulation module voltage^2,3,4

SR I/O supply voltage^5,6

–0.3

V_{DD_LV_BD}

V_{DD_HV_IO}

V_{DD_HV_PMC}

1.5

6.0

SR Power Management Controller

supply voltage⁵

6.0

V_{DD_HV_FLA}

V_DDSTBY

SR Flash core voltage⁷

—

–0.3

4.5

6.0

0.3

6.0

V

SR RAM standby supply voltage⁵

8

V_{SS_HV_ADV}

SR SAR and S/D ADC ground voltage Reference to V_{SS_HV}

9

V_{DD_HV_ADV}

SR SAR and S/D ADC supply voltage Reference to corresponding –0.3

V_{SS_HV_ADV}

10

V_{SS_HV_ADR}

SR SAR and S/D ADC low reference

Reference to V_{SS_HV}

–0.3

0.3

6.0

V

11

V_{DD_HV_ADR}

SR SAR and S/D ADC high reference Reference to corresponding –0.3

V_{SS_HV_ADR}

V_{DD_HV_IO_JTAG}

SR Crystal oscillator, FEC MDIO/MDC, Reference to V_{SS_HV}

LFAST, JTAG⁵

–0.3

6.0

V

MPC5777M Microcontroller Data Sheet, Rev. 6

20

NXP Semiconductors

Electrical characteristics

1

Table 6. Absolute maximum ratings (continued)

Value

Unit

Symbol

Parameter

Conditions

Min

Max

V_{DD_HV_IO_EBI}

SR External Bus Interface supply

voltage

—

–0.3

6.0

V

_{DD_LV_BD}– V_{DD_LV}SR Emulation module supply

–0.3

1.5

differential to 1.2 V core supply

V_IN

SR I/O input voltage range¹²

—

–0.3

—

6.0

—

0.3

5

13,14

Relative to V_{SS_HV_IO}

Relative to V_{DD_HV_IO}

I_INJD

I_INJA

SR Maximum DC injection current for Per pin, applies to all digital

digital pad pins

–5

mA

SR Maximum DC injection current for Per pin, applies to all analog

analog pad pins

–5

5

I_MAXD

SR Maximum output DC current when Medium

7

8

driven

Strong

Very strong

–10

–11

–90

10

11

90

I_MAXSEG

T_STG

SR Maximum current per power

segment¹⁵

—

mA

°C

SR Storage temperature range and

non-operating times

–55

—

175

20

STORAGE

SR Maximum storage time, assembled No supply; storage

years

part programmed in ECU

temperature in range –40 °C

to 60 °C

T_SDR

SR Maximum solder temperature¹⁶

Pb-free package

—

260

°C

MSL

SR Moisture sensitivity level¹⁷

SR X-ray screen time¹⁸

—

3

—

t_XRAY

At 160 KeV at max 5 mm

min

1

2

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress

ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect

device reliability or cause permanent damage to the device.

Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum T_J= 150 °C, remaining time as defined in note 3

and note 4

3

4

Allowed 1.38– 1.45 V– for 10 hours cumulative time at maximum T_J= 150 °C, remaining time as defined in note 4

1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at

maximum T_J= 150 °C.

5

6

7

8

Allowed 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset,

T_J= 150 °C, remaining time at or below 5.5 V.

V_{DD_HV_IO}applies to V_{DD_HV_IO_MAIN}, V_{DD_HV_IO_FLEX}, V_{DD_HV_IO_FLEXE}, V_{DD_HV_IO_JTAG}, and V_{DD_HV_IO_EBI}I/O

power supplies.

Allowed 3.6–4.5 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset,

T_J= 150 °C, remaining time at or below 3.6 V.

Includes ADC grounds V_{SS_HV_ADV_S and}V_{SS_HV_ADV_D}

.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

21

Electrical characteristics

9

Includes ADC supplies V_{DD_HV_ADV_S and}V_{DD_HV_ADV_D}. V_{DD_HV_ADV_S}is also the supply for the device

temperature sensor, RCOSC, and bandgap reference.

¹⁰Includes ADC low references V_{SS_HV_ADR_S}and V_{SS_HV_ADR_D}

.

¹¹Includes ADC high references V_{DD_HV_ADR_S}and V_{DD_HV_ADR_D}

.

¹²The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current

condition on a pin, the voltage equals the supply plus the voltage drop across the internal ESD diode from I/O pin to

supply. The diode voltage varies significantly across process and temperature, but a value of 0.3V can be used for

nominal calculations.

13

V

/V_{SS_HV_IO}refers to supply pins and corresponding grounds: V_{DD_HV_IO_MAIN}, V_{DD_HV_IO_FLEX},

_{DD_HV_IO_JTAG}, V_{DD_HV_OSC}, V_{DD_HV_FLA.}

DD_HV_IO

¹⁴Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameters I_INJD

and I_INJA).

¹⁵Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V_{DD_HV_IO}power segment

is defined as one or more GPIO pins located between two V_{DD_HV_IO}supply pins.

¹⁶Solder profile per IPC/JEDEC J-STD-020D

¹⁷Moisture sensitivity per JEDEC test method A112

¹⁸Three Screen done, 1 minute each. No change in device parameters during characterization of at least 10 devices at

30 minutes exposure of 150 KeV at maximum 5 mm.

3.3

Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device.

1,2

Table 7. ESD ratings

Parameter

Conditions

Value

Unit

ESD for Human Body Model (HBM)³

All pins

2000

500

V

ESD for field induced Charged Device Model (CDM)⁴

1

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

2

Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification

requirements, which includes the complete DC parametric and functional testing at room temperature and hot

temperature. Maximum DC parametrics variation within 10% of maximum specification”

3

4

This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing

This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level

3.4

Operating conditions

The following table describes the operating conditions for the device for which all specifications in the data sheet are valid,

except where explicitly noted.

The device operating conditions must not be exceeded or the functionality of the device is not guaranteed.

1

Table 8. Device operating conditions

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

Frequency

f_SYS

SR Device operating

frequency²

T_J 40 °C to 150 °C

—

300

MHz

MPC5777M Microcontroller Data Sheet, Rev. 6

22

NXP Semiconductors

Electrical characteristics

1

Table 8. Device operating conditions (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

Temperature

T_J

SR Operating temperature

range - junction

—

–40.0

—

150.0

125.0

°C

T_A(T_Lto T_H)

SR Ambient operating

temperature range

—

Voltage

V_{DD_LV}

SR External core supply

voltage^3,4

LVD/HVD enabled

1.24

1.19

—

1.38⁵

V

LVD/HVD

disabled^6,7,8,9

10,11

V_{DD_HV_IO_MAIN}

SR I/O supply voltage

LVD400/HVD600

enabled¹⁸

4.5

4.2

3.0

—

5.5¹²

5.5

LVD400/HVD600

disabled ^{6,13,14,15,18}

LVD360/HVD600

5.5

disabled ^{6,13,14,16,17,18}

V_{DD_HV_IO_JTAG}

V_{DD_HV_IO_FLEX}

V_{DD_HV_IO_FLEXE}

V_{DD_HV_IO_EBI}

V_{DD_HV_OSC}

SR JTAG I/O supply

voltage^6,19

5 V range

3.3 V range

5 V range

3.3 V range

4.5

3.0

—

5.5

3.6

5.5

3.6

5.5

3.6

5.5

3.6

5.5

3.6

5.5

3.5

V

SR FlexRay I/O supply

voltage

4.5

3.0

SR FlexRay/EBI I/O supply 5 V range

4.5

voltage

3.3 V range

3.0

SR External Bus Interface 5 V range

4.5

supply voltage

3.3 V range

3.0

SR Oscillator supply

voltage^6,20

5 V range

4.5

3.3 V range

3.0

V_{DD_HV_PMC}

SR Power Management

Controller (PMC)

supply voltage

Full functionality^22,23

3.5^24,25

21

Reduced internal

regulator output

capability²⁶

3.15

Supply monitoring

activity only (LVD/HVD)

3.0

1.1

—

3.15

5.5

V_DDSTBY

SR RAM standby supply

voltage^27,28,29

—

V

V_{DD_HV_ADV}

SR SARADC, SDADC,

Temperature Sensor,

and Bandgap

LVD400 enabled

4.5

4.0

—

5.5

LVD400

5.5³²

disabled^30,31,34

Reference supply

voltage

LVD300

3.7

—

5.5³²

disabled^{6,30,31,33,34}

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

23

Electrical characteristics

1

Table 8. Device operating conditions (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

V_{DD_HV_ADR_D}

SR SD ADC supply

reference voltage

Reduced SNR

Full SNR

3.0

4.5

—

V_{DD_HV_ADV_D}

4.5

5.5³²

25

V

V_{DD_HV_ADR_D}

–

SR SD ADC reference

differential voltage

—

mV

V

V_{DD_HV_ADV_D}

V_{SS_HV_ADR_D}

SR SD ADC ground

reference voltage

V_{SS_HV_ADV_D}

—

V_{SS_HV_ADR_D}

–

SR V_{SS_HV_ADR_D}

differential voltage

–25

25

mV

V

V_{SS_HV_ADV_D}

35

V_{DD_HV_ADR_S}

SR SARADC reference

2.0

4.0

V_{DD_HV_ADV_S}

4.0

5.5³²

V_{SS_HV_ADR_S}

V_{DD_HV_ADR_S}

SR SAR ADC ground

reference voltage

—

V_{SS_HV_ADV_S}

V

–

SR SARADC reference

differential voltage

—

–25

—

25

mV

V_{DD_HV_ADV_S}

V_{SS_HV_ADR_S}

–

SR V_{SS_HV_ADR_S}

differential voltage

mV

V_{SS_HV_ADV_S}

V_{SS_HV_ADV}– V_SSSR V_{SS_HV_ADV}differential

25

mV

voltage

V_{RAMP_LV}

V_{RAMP_HV}

SR Slew rate on core

power supply pins

100

V/ms

SR Slew rate on HV power

supply pins

—

V_{por_rel}

V_{por_hys}

V_IN

CC POR release trip point

CC POR hysteresis

-40 °C < Tj < 150 °C

—

3.10

150

0

—

4.26

300

5.5

V

mV

V

SR I/O input voltage range

Injection current

I_IC

SR DC injection current

(per pin)^36,37,38

Digital pins and analog

pins

–3.0

–80

—

3.0

80

mA

I_MAXSEG

SR Maximum current per

power segment³⁹

—

1

2

The ranges in this table are design targets and actual data may vary in the given range.

Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clocking chapter

in the MPC5777M Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks

on the device.

3

4

Core voltage as measured on device pin to guarantee published silicon performance.

During power ramp, voltage measured on silicon might be lower. maximum performance is not guaranteed, but correct

silicon operation is guaranteed. Refer to the Power Management and Reset Generation Module chapters in the MPC5777M

Microcontroller Reference Manual for further information.

MPC5777M Microcontroller Data Sheet, Rev. 6

24

NXP Semiconductors

Electrical characteristics

5

6

Although the maximum V_{DD_LV}operating voltage is 1.38 V, reset is not entered at that voltage. An external voltage monitor

is needed or the HVD140_C can be monitored (via an interrupt or by polling the HVD140_C flag bit). Performance above

1.38 V is not guaranteed, and allowed operation above 1.38 V is defined in Absolute maximum ratings.

In the LVD/HVD disabled case, it is necessary for the system to be within a higher voltage range during destructive reset

events.

7

8

9

Maximum core voltage is not permitted for entire product life. See Absolute maximum rating.

When internal LVD/HVDs are disabled, external monitoring is required to guarantee correct device operation.

Vdd_lv should be above 1.24 V during destructive resets or POR events.

¹⁰VDD_HV_IO_MAIN range limited to 4.75–5.25 V when FERS = 1 to enable the fast erase time of the flash memory.

¹¹During power up operation, the minimum required voltage to come out of reset state is determined by the V_{PORUP_HV}

monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V_{PORUP_HV}monitor is connected

to the V_{DD_HV_IO_MAIN0}physical I/O segment.

¹²When the LVD/HVDs are enabled, the V_{DD_HV_IO_MAIN}must be less than 5.412 V to exit from a destructive reset.

¹³Maximum voltage is not permitted for entire product life. See Absolute maximum rating.

¹⁴When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor

externally supply voltage may result in erroneous operation of the device.

¹⁵When these LVD/HVDs are disabled, the V_{DD_HV_IO_MAIN}supply must be between 3.182 V and 5.412 V.

¹⁶Reduced output capabilities below 4.2 V. See performance derating values in I/O pad electrical characteristics.

¹⁷When the LVD/HVDs are disabled, the VDD_HV_IO_MAIN must be between 3.024 V and 5.412 V.

¹⁸The PMC supply voltage (V_{DD_HV_PMC}) must be within the correct range (see the V_{DD_HV_PMC}specification).

¹⁹When the LVD/HVDs are disabled, the HV I/O JTAG supply (V_{DD_HV_IO_JTAG}) must be above 3.024 V.

²⁰When the LVD/HVDs are disabled, the HV OSC supply (V_{DD_HV_OSC}) must be above 3.024 V.

²¹Flash read operation is supported for a minimum V_{DD_HV_PMC}value of 3.15 V. Flash read, program, and erase operations

are supported for a minimum V_{DD_HV_PMC}value of 3.5 V.

²²When the LVD/HVDs are disabled, the V_{DD_HV_PMC}must be below 5.412 V during destructive reset events.

²³A minimum of 4.5 V is required to guarantee correct user logic BIST operation.

²⁴During power up operation, the minimum required voltage to come out of reset state is determined by the V_{PORUP_HV}

monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V_{PORUP_HV}monitor is connected

to the V_{DD_HV_IO_MAIN0}physical I/O segment.

²⁵Above Ta = 25°C, the minimum V_{DD_HV_PMC}voltage is 3.6 V.

²⁶With the reduced internal regulator output capability, erases and writes to the device flash cannot be guaranteed for a single

event and multiple erases and writes may be necessary. User logic BIST is not supported with reduced capability.

²⁷RAM data retention is guaranteed at a voltage that is always below the maximum brownout flag trip point voltage (see the

DC Electrical Specification table). The minimum V_DDSTBYvoltage at the pin is larger in order to account for on-chip IR drop

and noise. There is no effect on RAM operation when V_DDSTBYis below 1.1 V, and V_{DD_LV}is above the minimum operating

value.

²⁸Non-regulated supplies can be used on the VDDSTBY pin if the absolute maximum and operating condition voltage limits

are met. There is no static clamp to a supply rail for the VDDSTBY pin, only dynamic protection for ESD events.

²⁹The VDDSTBY pin should be connected to ground in the application when the standby RAM feature is not used.

30

V

is required to be between 4.5 V and 5.5 V to read the internal Temperature Sensor and Bandgap Reference.

DD_HV_ADV_S

³¹SAR ADC only. SDADC minimum is 4.5 V.

³²The ADC is functional up to 5.9V with no reliability issues, but performance is not guaranteed.

³³When the LVD/HVDs are disabled, the HV ADC supply (V_{DD_HV_ADV}) must be above 3.182 V.

³⁴For supply voltages between 3.0 V and 4.0 V there is no guaranteed precision of ADC (accuracy/linearity). ADCs recover to

a fully functional state when the voltage rises above 4.0 V.

35

V

must be between 4.5 V and 5.5 V for accurate reading of the device Temperature Sensor.

DD_HV_ADR_S

³⁶Full device lifetime without performance degradation

³⁷I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the

Absolute maximum ratings table for maximum input current for reliability requirements.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

25

Electrical characteristics

³⁸The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is above

the supply rail, current is injected through the clamp diode to the supply rail. For external RC network calculation, assume

typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.

³⁹Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V_{DD_HV_IO}power segment is defined

as one or more GPIO pins located between two V_{DD_HV_IO}supply pins.

1

Table 9. Emulation (buddy) device operating conditions

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

Frequency

—

SR Standard JTAG 1149.1/1149.7 frequency

SR High-speed debug frequency

SR Data trace frequency

—

50

MHz

320 MHz

1250 MHz

Temperature

T_{J_BD}

SR Device junction operating temperature

range

—

–40.0

—

150.0

125.0

°C

T_{A _BD}

SR Ambient operating temperature range

Voltage

V_{DD_LV_BD}SR Buddy core supply voltage

—

1.2

3.0

—

1.365

5.5

V

V_{DD_HV_IO_BD}SR Buddy I/O supply voltage

V_{RAMP_LV_BD}SR Buddy slew rate on core power supply pins

V_{RAMP_HV_BD}SR Buddy slew rate on HV power supply pins

100 V/ms

—

1

The ranges in this table are design targets and actual data may vary in the given range.

3.5

DC electrical specifications

The following table describes the DC electrical specifications.

Table 10. DC electrical specifications

1

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

I_{DD_LV}

CC

Maximum operating

T_J= 150 ^oC

—

1140

mA

current on the V_{DD_LV}V_{DD_LV}= 1.325 V

supply²

f_MAX

I_{DDAPP_LV}

Application use case

T_J= 150 °C

—

950

40

operating current on the V_{DD_LV}= 1.325 V

V_{DD_LV}supply³

f_MAX

I_{DD_LV_PE}

Operating current on

the V_{DD_LV}supply for

flash program/erase

T_J= 150 ^oC

MPC5777M Microcontroller Data Sheet, Rev. 6

26

NXP Semiconductors

Electrical characteristics

1

Table 10. DC electrical specifications (continued)

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

I_{DD_HV_PMC}

CC

Operating current on

the V_{DD_HV_PMC}

supply^4,5

Flash read

—

10

40

mA

Flash P/E

PMC only

25⁶

7

I_{DD_MAIN_CORE_AC}

CC

Main Core 0/1 dynamic 300 MHz

operating current

115

mA

I_{DD_CHKR_CORE_AC}

Checker Core 0

dynamic operating

current

300 MHz

—

80

I_{DD_HSM_AC}

CC

HSM platform dynamic 100 MHz

operating current

—

20

mA

µA

I_{DDSTBY_RAM}

64 KB RAM Standby

Leakage Current

(RAM not

V_{DDSTBY @}1.1 V

to 5.5 V, T_J=

150 °C

350

operational)^8,9,10,11

CC

V

_{DDSTBY @}1.1 V

—

60

100

50

to 5.5 V, T_A=

40 °C

V

_{DDSTBY @}1.1 V

to 5.5 V, T_A=

85 °C

I_{DDSTBY_REG}

64 KB RAM Standby

Leakage Current¹²

V_{DDSTBY @}1.3 V

to 5.5 V, T_A=

125 °C

µA

mA

I_{DD_LV_BD}

BD Debug/Emulation

low voltage supply

operating current¹³

T_J= 150 °C

V_{DD_LV_BD}

1.32 V

290

130

=

I_{DD_HV_IO_BD}

Debug/Emulation high T_J= 150 °C

voltage supply

operating current

(Aurora +

JTAGM/LFAST)

I_{DD_BD_STBY}

CC

BD Debug/Emulation

low voltage supply

standby current^14,15

V_{DD_LV_BD}

1.32 V,

T_J= 150 °C

=

—

230

5

mA

V_{DD_LV_BD}

1.32 V,

T_J= 55 °C

=

I_SPIKE

Maximum short term

current spike¹⁶

< 20 µs

observation

window

90

20

mA

%

dI

Current difference ratio 20 µs

to average current

observation

window

(dI/avg(I))¹⁷

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

27

Electrical characteristics

1

Table 10. DC electrical specifications (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

18

I_SR

CC

Current variation during See footnote¹⁹

power up/down

—

90

mA

µA

I_BG

Bandgap reference

current consumption

—

600

—

I_DDOFF

Power-off current on

high voltage supply

rails²⁰

V_{DD_HV}= 2.5 V

100

V_{STBY_BO}

CC

Standby RAM brownout

flag trip point voltage

—

0.9²¹

—

V

V_{DD_LV_STBY_SW}

Standby RAM switch

VDD_LV voltage

threshold

0.93

V_{REF_BG_T}

V_{REF_BG_TC}

V_{REF_BG_LR}

CC

Bandgap trimmed

reference voltage

T_J= 40 °C to

150 °C

1.200

—

1.237

50

V

V_{DD_HV_ADV}

5 V ± 10%

=

Bandgap temperature T_J= 40 °C to

ppm/°

C

coefficient²²

150 °C

V_{DD_HV_ADV}

5 V

=

Bandgap line

regulation²²

T_J= 40 °C

V_{DD_HV_ADV}

5 V ± 10%

—

8000 ppm/V

4000

T_J= 150 °C

V_{DD_HV_ADV}

5 V ± 10%

1

All parameters in this data sheet are valid for operation within an operating range of -40° C  T_J 150 °C except where

otherwise noted

2

f_MAXas specified per IP. Excludes flash P/E and HSM dynamic current. Measured on an application specific pattern.

Calculation of total current for the device, all rails, is done by adding the applicable dynamic currents to the I_{DD_LV}value

for the core supply, and summing the currents based on use case for the 5 V blocks, for which current consumption values

are defined in later sections of the DC electrical specification.

3

4

f_MAXas specified per IP. Excludes flash P/E and HSM dynamic current. Measured on an application specific pattern.

V_{DD_HV_PMC}only available in the 416 BGA package. PMC supply is shorted to V_{DD_HV_IO_MAIN}in the 512 BGA, with an

external bypass capacitor connected to the V_{DD_HV_PMC_BYP}ball. The flash read and P/E current, and PMC current apply

to V_{DD_HV_IO_MAIN}for the 512 BGA.

5

6

The flash read and flash P/E currents are mutually exclusive, and are not cumulative.

This includes PMC consumption, LFAST PLL regulator current, and Nwell bias regulator current. If the V_{DD_LV}auxiliary

regulator is enabled, the PMC supply may see short term (10 µs) spikes of up to 150 mA depending on transient current

conditions from use case of the device. The auxiliary regulator can be disabled at power-up in the user DCF clients in the

flash memory.

7

8

There is an additional 25 mA when FERS = 1 to enable the fast erase time of the flash memory.

Data is retained for full T_Jrange of -40 °C to 150 °C. RAM supply switch to the standby regulator occurs when the V_{DD_LV}

supply falls below 0.95V.

MPC5777M Microcontroller Data Sheet, Rev. 6

28

NXP Semiconductors

Electrical characteristics

9

V_DDSTBYmay be supplied with a non-regulated power supply, but the absolute maximum voltage on VDDSTBY given in

the absolute maximum ratings table must be observed.

¹⁰Standby current is reduced by a factor of two from T_J=150 °C, for approximately every ~20 °C drop in operating

temperature.

¹¹The maximum value for I_{DDSTBY_ON}is also valid when switching from the core supply to the standby supply, and when

powering up the device and switching the RAM supply back to V_{DD_LV}

.

¹²The standby RAM regulator current is present on the VDDSTBY pin whenever a voltage is applied to the pin. This also

applies to normal operation where the RAM is powered by the VDD_LV supply. Connecting the VDDSTBY pin to ground

when not using the standby RAM feature will remove the leakage current on the VDDSTBY pin.

¹³If Aurora and JTAGM/LFAST not used, V_{DD_LV_BD}current is reduced by ~20mA.

¹⁴Applies to 2MB calibration RAM in the BD.

¹⁵Buddy device leakage dependency on temperature can be estimated by dividing the 150 °C leakage by two for each

temperature drop of ~20 °C.

¹⁶Current spike may occur during normal operation that are above average current, valid for I_DDAPPand its conditions given

in Table 10 (DC electrical specifications). Internal schemes must be used (eg frequency ramping, feature enable) to

ensure that incremental demands are made on the external power supply. An internal fast regulator providing ~40mA peak

current within 1us to filter any core power supply droops is available on the device. Assumption is minimum 13.3 µF (20 µF

typical) capacitance on the core supply.]

¹⁷Moving window, valid for I_DDAPPand its conditions given in Table 10 (DC electrical specifications), with a maximum of

90 mA for the worst case application

¹⁸This specification is the maximum value and is a boundary for the dl specification.

¹⁹Condition1: For power on period from 0 V up to normal operation with reset asserted. Condition 2: From reset asserted

until PLL running free. Condition 3: Increasing PLL from free frequency to full frequency. Condition 4: reverse order for

power down to 0 V.

20

I

is the minimum guaranteed consumption of the device during power-up. It can be used to correctly size power-off

DDOFF

ballast in case of current injection during power-off state.Power up/down current transients can be limited by controlling

the clock ramp rates with the Progressive Clock Frequency Switching block on the device.

21

V

is the maximum voltage that sets the standby RAM brown-out flag in the device logic. The minimum voltage for

STBY_BO

RAM data retention is guaranteed to always be less than the V_{STBY_BO}maximum value.

²²The temperature coefficient and line regulation specifications are used to calculate the reference voltage drift at an

operating point within the specified voltage and temperature operating conditions.

3.6

I/O pad specification

The following table describes the different pad type configurations.

Table 11. I/O pad specification descriptions

Pad type

Description

Weak configuration

Provides a good compromise between transition time and low electromagnetic emission.

Pad impedance is centered around 800 

Medium configuration

Strong configuration

Provides transition fast enough for the serial communication channels with controlled

current to reduce electromagnetic emission.

Pad impedance is centered around 200 

Provides fast transition speed; used for fast interface.

Pad impedance is centered around 50 

Very strong configuration Provides maximum speed and controlled symmetric behavior for rise and fall transition.

Used for fast interface including Ethernet, FlexRay, and the EBI data bus interfaces

requiring fine control of rising/falling edge jitter.

Pad impedance is centered around 40 

EBI configuration

Provides necessary speed for fast external memory interfaces on the EBI address and

control signals. Drive strength is matched to four selectable loads.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

29

Electrical characteristics

Pad type

Table 11. I/O pad specification descriptions (continued)

Description

Differential configuration A few pads provide differential capability providing very fast interface together with good

EMC performances.

Input only pads

These low input leakage pads are associated with the ADC channels.

NOTE

Each I/O pin on the device supports specific drive configurations. See the signal description

table in the device reference manual for the available drive configurations for each I/O pin.

The device supports both 3.3 V and 5 V nominal I/O voltages. In order to use 3.3 V on the

V

physical I/O segment, the HV supply low voltage monitor (V

)

DD_HV_IO_MAIN0

LVD400

must be disabled by DCF client. All other physical I/O segments are unaffected by the

LVD400.

3.6.1

I/O input DC characteristics

Table 12 provides input DC electrical characteristics as described in Figure 7.

V

IN

V

DD

V

IH

V

HYS

V

IL

V

INTERNAL

(SIUL register)

Figure 7. I/O input DC electrical characteristics definition

Table 12. I/O input DC electrical characteristics

Value

Typ

Symbol

Parameter

Conditions¹

Unit

Min

Max

TTL

V_IHTTL

SR Input high level TTL

SR Input low level TTL

4.5 V < V_{DD_HV_IO}< 5.5 V⁶

2

—

V_{DD_HV_IO}

+ 0.3

V

V_ILTTL

4.5 V < V_{DD_HV_IO}< 5.5 V⁶

–0.3

—

0.8

—

V_HYSTTL— Input hysteresis TTL

0.275

MPC5777M Microcontroller Data Sheet, Rev. 6

30

NXP Semiconductors

Electrical characteristics

Table 12. I/O input DC electrical characteristics (continued)

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

V_DRFTTTL— Input V_IL/V_IHtemperature

drift TTL

—

100

mV

AUTOMOTIVE

2

V_IHAUT

SR Input high level

AUTOMOTIVE

4.5 V < V_{DD_HV_IO}< 5.5 V

3.8

–0.3

0.4

—

V_{DD_HV_IO}

+ 0.3

V

3

V_ILAUT

SR Input low level

AUTOMOTIVE

2.2

4

V_HYSAUT

— Input hysteresis

AUTOMOTIVE

—

V

V_DRFTAUT— Input V_IL/V_IHtemperature

drift

100⁵

mV

CMOS/EBI

V_{IHCMOS_H}SR Input high level CMOS

3.0 V < V_{DD_HV_IO}< 3.6 V

4.5 V < V_{DD_HV_IO}< 5.5 V

3.0 V < V_{DD_HV_IO}< 3.6 V

4.5 V < V_{DD_HV_IO}< 5.5 V

3.0 V < V_{DD_HV_IO}< 3.6 V

4.5 V < V_{DD_HV_IO}< 5.5 V

3.0 V < V_{DD_HV_IO}< 3.6 V

4.5 V < V_{DD_HV_IO}< 5.5 V

3.0 V < V_{DD_HV_IO}< 3.6 V

4.5 V < V_{DD_HV_IO}< 5.5 V⁷

3.0 V < VDD_HV_IO < 3.6 V

4.5 V < VDD_HV_IO < 5.5 V

0.70 *

V_{DD_HV_IO}

—

V_{DD_HV_IO}

+ 0.3

V

6

(with hysteresis)

6

V_IHCMOSSR Input high level CMOS

0.6 *

V_{DD_HV_IO}

+ 0.3

(without hysteresis)

6

V_{ILCMOS_H}SR Input low level CMOS

–0.3

0.35 *

V_{DD_HV_IO}

V

(with hysteresis)

6

V_ILCMOSSR Input low level CMOS

0.4 *

V_{DD_HV_IO}

V

(without hysteresis)

V_HYSCMOS— Input hysteresis CMOS

0.1 *

V_{DD_HV_IO}

—

V

V_DRFTCMOS— Input V_IL/V_IHtemperature

drift CMOS

—

100⁵

mV

INPUT CHARACTERISTICS⁸

I_LKG

CC Digital input leakage

4.5 V < V_{DD_HV}< 5.5 V

V_{SS_HV}< V_IN< V_{DD_HV}

TJ = 150 °C

—

750

nA

pF

I_{LKG_EBI}CC Digital input leakage for 4.5 V < V_{DD_HV}< 5.5 V

EBI pad

V_{SS_HV}< V_IN< V_{DD_HV}

TJ = 150 °

C_IN

CC Digital input capacitance

GPIO input pins

EBI input pins

—

7

1

During power up operation, the minimum required voltage to come out of reset state is determined by the V_{PORUP_HV}

monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V_{PORUP_HV}monitor is

connected to the V_{DD_HV_IO_MAIN0}physical I/O segment.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

31

Electrical characteristics

2

A good approximation for the variation of the minimum value with supply is given by formula

V

_IHAUT= 0.69 × V_{DD_HV_IO.}

A good approximation for the variation of the maximum value with supply is given by formula

_ILAUT= 0.49 × V_{DD_HV_IO.}

A good approximation of the variation of the minimum value with supply is given by formula

_HYSAUT= 0.11 × V_{DD_HV_IO.}

3

4

5

6

V

In a 1 ms period, assuming stable voltage and a temperature variation of ±30 °C, V_IL/V_IHshift is within ±50 mV. For

SENT requirement refer to NOTE on page 41.

Only for V_{DD_HV_IO_JTAG}and V_{DD_HV_IO_FLEX}power segment. The TTL threshold are controlled by the VSIO bit.

VSIO[VSIO_xx] = 0 in the range 3.0 V < V_{DD_HV_IO}< 4.0 V, VSIO[VSIO_xx] = 1 in the range

4.5 V < V_{DD_HV_IO}< 5.5 V.

7

8

Only for V_{DD_HV_IO_JTAG}and V_{DD_HV_IO_FLEX}power segment.

For LFAST, microsecond bus and LVDS input characteristics, refer to dedicated communication module chapters.

Table 13 provides weak pull figures. Both pull-up and pull-down current specifications are provided.

Table 13. I/O pull-up/pull-down DC electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

I_WPU



CC Weak pull-up current V_IN= 0 V

absolute value²V_{DD_POR}³< V_{DD_HV_IO}< 3.0 V^4,5

10.6 * V_{DD_HV}– 10.6

—

µA

V

_IN> V_IL= 1.1 V (TTL)

—

10

—

25

23

—

40

34

—

130

—

4.5 V < V_DD< 5.5 V

V_IN= 0.75*V_{DD_HV_IO}(AUTO)

3.0 V < V_{DD_HV_IO}< 3.6 V

V_IN= 0.35* V_{DD_HV_IO}(AUTO)

3.0 V < V_{DD_HV_IO}< 3.6 V

70

V_IN= 0.35* V_{DD_HV_IO}(CMOS)

80

3.0 V < V_{DD_HV_IO}< 3.6 V

V_IN= 0.69* V_{DD_HV_IO}(AUTO)

—

4.5 V < V_{DD_HV_IO}< 5.5 V

V_IN= 0.49* V_{DD_HV_IO}(AUTO)

4.5 V < V_{DD_HV_IO}< 5.5 V

82

V_IN= 0.35* V_{DD_HV_IO}(CMOS)

120

62

4.5 V < V_{DD_HV_IO}< 5.5 V

R_WPUCC Weak pull-up

resistance

—

k

MPC5777M Microcontroller Data Sheet, Rev. 6

32

NXP Semiconductors

Electrical characteristics

Table 13. I/O pull-up/pull-down DC electrical characteristics (continued)

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

I_WPD



CC Weak pull-down

V_IN< V_IL= 0.9 V (TTL)

16

—

µA

current absolute value 4.5 V < V_DD< 5.5 V

V

_IN= 0.75* V_{DD_HV_IO}(AUTO)

—

19

25

—

40

30

—

92

—

3.0 V < V_{DD_HV_IO}< 3.6 V

V_IN= 0.35* V_{DD_HV_IO}(AUTO)

3.0 V < V_{DD_HV_IO}< 3.6 V

V_IN= 0.65* V_{DD_HV_IO}(CMOS)

3.0 V < V_{DD_HV_IO}< 3.6 V

80

V_IN= 0.69* V_{DD_HV_IO}(AUTO)

130

—

4.5 V < V_{DD_HV_IO}< 5.5 V

V_IN= 0.49* V_{DD_HV_IO}(AUTO)

4.5 V < V_{DD_HV_IO}< 5.5 V

V_IN= 0.65* V_{DD_HV_IO}(CMOS)

4.5 V < V_{DD_HV_IO}< 5.5 V

120

55

R_WPDCC Weak pull-down

resistance

—

k

1

During power up operation, the minimum required voltage to come out of reset state is determined by the

V_{PORUP_HV}monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V_{PORUP_HV}

monitor is connected to the V_{DD_HV_IO_MAIN0}physical I/O segment.

2

3

Weak pull-up/down is enabled within t_{WK_PU}= 1 µs after internal/external reset has been asserted. Output voltage

will depend on the amount of capacitance connected to the pin.

V_{DD_POR}is the minimum V_{DD_HV_IO}supply voltage for the activation of the device pull-up/down, and is given in the

Reset electrical characteristics table of Section Reset pad (PORST, ESR0) electrical characteristics in this Data

Sheet.

4

5

V_{DD_POR}is defined in the Reset electrical characteristics table of Section Reset pad (PORST, ESR0) electrical

characteristics in this Data Sheet.

Weak pull-up behavior during power-up. Operational with V_{DD_HV_IO}> V_{DD_POR}

.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

33

Electrical characteristics

t

WK_PU

V

DD_HV_IO

V

DD_POR

RESET

(INTERNAL)

pull-up

enabled

YES

NO

(1)

PAD

(1)

POWER-UP

Application defined

RESET

Application defined

POWER-DOWN

1. Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply.

Figure 8. Weak pull-up electrical characteristics definition

3.6.2

I/O output DC characteristics

The figure below provides description of output DC electrical characteristics.

MPC5777M Microcontroller Data Sheet, Rev. 6

34

NXP Semiconductors

Electrical characteristics

V

INTERNAL

(SIUL register)

V

HYS

t

PD50-50

t

PD50-50

t

V

SKEW20-80

out

90%

80%

50%

20%

10%

t

R20-80

t

F20-80

t

R10-90

t

F10-90

t

(max) = MAX(t

;t

)

TR

R10-90 F10-90

t

(max) = MAX(t

;t

)

TR20-80

R20-80 F20-80

(min) = MIN(t

;t

)

R10-90 F10-90

(min) = MIN(t

;t

)

TR20-80

R20-80 F20-80

t

= t

-t_F20-80

SKEW20-80

R20-80

Figure 9. I/O output DC electrical characteristics definition

The following tables provide DC characteristics for bidirectional pads:

•

Table 14 provides output driver characteristics for I/O pads when in WEAK configuration.

Table 15 provides output driver characteristics for I/O pads when in MEDIUM configuration.

Table 16 provides output driver characteristics for I/O pads when in STRONG configuration.

Table 17 provides output driver characteristics for I/O pads when in VERY STRONG configuration.

Table 18 provides output driver characteristics for the EBI pads.

NOTE

Driver configuration is controlled by SIUL2_MSCRn registers. It is available within two

PBRIDGEA_CLK clock cycles after the associated SIUL2_MSCRn bits have been written.

Table 14 shows the WEAK configuration output buffer electrical characteristics.

Table 14. WEAK configuration output buffer electrical characteristics

Value

Symbol

Parameter

Conditions^1,2

Unit

Min

Typ

Max

R_{OH_W}CC PMOS output impedance

weak configuration

4.5 V < V_{DD_HV_IO}< 5.5 V

Push pull, I_OH< 0.5 mA

520

800

1052



R_{OL_W}CC NMOS output impedance

weak configuration

4.5 V < V_{DD_HV_IO}< 5.5 V

Push pull, I_OL< 0.5 mA

520

800

1052

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

35

Electrical characteristics

Table 14. WEAK configuration output buffer electrical characteristics (continued)

Value

Typ

Symbol

Parameter

Conditions^1,2

C_L= 25 pF³

Unit

Min

Max

f_{MAX_W}CC Output frequency

weak configuration

—

40

—

2

1

MHz

C_L= 50 pF³

C_L= 200 pF³

0.25

120

t_{TR_W}CC Transition time output pin

weak configuration⁴

C_L= 25 pF,

4.5 V < V_{DD_HV_IO}< 5.5 V

ns

C_L= 50 pF,

4.5 V < V_{DD_HV_IO}< 5.5 V

80

320

50

—

240

820

150

300

1050

25

C_L= 200 pF,

4.5 V < V_{DD_HV_IO}< 5.5 V

C_L= 25 pF,

3.0 V < V_{DD_HV_IO}< 3.6 V⁵

C_L= 50 pF,

100

350

—

3.0 V < V_{DD_HV_IO}< 3.6 V⁵

C_L= 200 pF,

3.0 V < V_{DD_HV_IO}< 3.6 V⁵

t_{SKEW_W} CC Difference between rise and

—

%

fall time

I_{DCMAX_W}CC Maximum DC current

—

4

mA

1

All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V

are valid for VSIO[VSIO_xx] = 0

2

During power up operation, the minimum required voltage to come out of reset state is determined by the

V_{PORUP_HV}monitor, which is defined in the voltage monitor electrical characteristics table. Note that the

V_{PORUP_HV}monitor is connected to the V_{DD_HV_IO_MAIN0}physical I/O segment.

3

4

C_Lis the sum of external capacitance. Device and package capacitances (C_IN, defined in Table 12) are to be added

to calculate total signal capacitance (C_TOT= C_L+ C_IN).

Transition time maximum value is approximated by the following formula:

0 pF < C_L< 50 pF

t_{TR_W}(ns) = 22 ns + C_L(pF)  4.4 ns/pF

50 pF < C_L< 200 pF t_{TR_W}(ns) = 50 ns + C_L(pF)  3.85 ns/pF

Only for V_{DD_HV_IO_JTAG}segment when VSIO[VSIO_IJ] = 0 or V_{DD_HV_IO_FLEX}segment when VSIO[VSIO_IF] = 0.

5

Table 15 shows the MEDIUM configuration output buffer electrical characteristics.

Table 15. MEDIUM configuration output buffer electrical characteristics

Value

Symbol

Parameter

Conditions^1,2

Unit

Min

Typ

Max

R_{OH_M}CC PMOS output impedance

MEDIUM configuration

4.5 V < V_{DD_HV_IO}< 5.5 V

Push pull, I_OH< 2 mA

135

200

260



R_{OL_M}CC NMOS output impedance

MEDIUM configuration

4.5 V < V_{DD_HV_IO}< 5.5 V

Push pull, I_OL< 2 mA

135

200

260

MPC5777M Microcontroller Data Sheet, Rev. 6

36

NXP Semiconductors

Electrical characteristics

Table 15. MEDIUM configuration output buffer electrical characteristics (continued)

Value

Typ

Symbol

Parameter

Conditions^1,2

C_L= 25 pF³

Unit

Min

Max

f_{MAX_M}CC Output frequency

MEDIUM configuration

—

12

6

MHz

C_L= 50 pF³

C_L= 200 pF³

1.5

4

t_TPD50-50CC 50-50 % Output pad

V_{DD_HV_IO}= 5 V +/- 10 %, C_L

= 25 pF

21/17

ns

propagation delay time

V_{DD_HV_IO}= 5.0 V +/- 10 %,

—

10

20

60

12

24

70

—

35/27

30

C_L= 50 pF

t_{TR_M}

CC Transition time output pin

MEDIUM configuration⁵

C_L= 25 pF

4.5 V < V_{DD_HV_IO}< 5.5 V

C_L= 50 pF

4.5 V < V_{DD_HV_IO}< 5.5 V

60

C_L= 200 pF

4.5 V < V_{DD_HV_IO}< 5.5 V

200

42

C_L= 25 pF,

3.0 V < V_{DD_HV_IO}< 3.6 V⁶

C_L= 50 pF,

86

3.0 V < V_{DD_HV_IO}< 3.6 V⁶

C_L= 200 pF,

300

25

3.0 V < V_{DD_HV_IO}< 3.6 V⁶

t_{SKEW_M} CC Difference between rise and fall

—

%

time

I_{DCMAX_M}CC Maximum DC current

—

4

mA

1

2

All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V

are valid for VSIO[VSIO_xx] = 0

During power up operation, the minimum required voltage to come out of reset state is determined by the

V_{PORUP_HV}monitor, which is defined in the voltage monitor electrical characteristics table. Note that the

V_{PORUP_HV}monitor is connected to the V_{DD_HV_IO_MAIN0}physical I/O segment.

3

4

5

C_Lis the sum of external capacitance. Device and package capacitances (C_IN, defined in Table 12) are to be added

to calculate total signal capacitance (C_TOT= C_L+ C_IN).

If two values are given for propagation delay, the first value is for rising edge signals and the second for falling

edge signals.

Transition time maximum value is approximated by the following formula:

0 pF < C_L< 50 pF

t_{TR_M}(ns) = 5.6 ns + C_L(pF)  1.11 ns/pF

50 pF < C_L< 200 pF t_{TR_M}(ns) = 13 ns + C_L(pF)  0.96 ns/pF

Only for V_{DD_HV_IO_JTAG}segment when VSIO[VSIO_IJ] = 0 or V_{DD_HV_IO_FLEX}segment when VSIO[VSIO_IF] = 0

6

Table 16 shows the STRONG configuration output buffer electrical characteristics.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

37

Electrical characteristics

Table 16. STRONG configuration output buffer electrical characteristics

Value

Symbol

Parameter

Conditions^1,2

Unit

Min

Typ

Max

R_{OH_S}CC PMOS output impedance

STRONG configuration

4.5 V < V_{DD_HV_IO}< 5.5 V

Push pull, I_OH< 8 mA

30

50

77



R_{OL_S}CC NMOS output impedance

STRONG configuration

4.5 V < V_{DD_HV_IO}< 5.5 V

Push pull, I_OL< 8 mA

30

50

77

f_{MAX_S}CC Output frequency

STRONG configuration

C_L= 25 pF³

C_L= 50 pF³

C_L= 200 pF³

—

40

20

5

MHz

4

t_TPD50-50CC 50-50 % Output pad

V_{DD_HV_IO}= 5 V +/- 10 %, C_L

8/7

ns

propagation delay time

= 25 pF

V_{DD_HV_IO}= 5.0 V +/- 10 %,

—

3

—

11/9

10

16

50

15

27

83

25

10

C_L= 50 pF

t_{TR_S}

CC Transition time output pin

STRONG configuration⁵

C_L= 25 pF

4.5 V < V_{DD_HV_IO}< 5.5 V

C_L= 50 pF

4.5 V < V_{DD_HV_IO}< 5.5 V

5

C_L= 200 pF

4.5 V < V_{DD_HV_IO}< 5.5 V

17

4

C_L= 25 pF,

3.0 V < V_{DD_HV_IO}< 3.6 V⁶

C_L= 50 pF,

6

3.0 V < V_{DD_HV_IO}< 3.6 V⁶

C_L= 200 pF,

20

—

3.0 V < V_{DD_HV_IO}< 3.6 V⁶

t_{SKEW_S} CC Difference between rise and fall

—

%

time

I_{DCMAX_S}CC Maximum DC current

—

mA

1

All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V

are valid for VSIO[VSIO_xx] = 0

2

During power up operation, the minimum required voltage to come out of reset state is determined by the

V_{PORUP_HV}monitor, which is defined in the voltage monitor electrical characteristics table. Note that the

V_{PORUP_HV}monitor is connected to the V_{DD_HV_IO_MAIN0}physical I/O segment.

3

4

C_Lis the sum of external capacitance. Device and package capacitances (C_IN, defined in Table 12) are to be

added to calculate total signal capacitance (C_TOT= C_L+ C_IN).

If two values are given for propagation delay, the first value is for rising edge signals and the second for falling

edge signals.

5

6

Transition time maximum value is approximated by the following formula: t_{TR_S}(ns) = 4.5 ns + C_L(pF) x 0.23 ns/pF.

Only for V_{DD_HV_IO_JTAG}segment when VSIO[VSIO_IJ] = 0 or V_{DD_HV_IO_FLEX}segment when VSIO[VSIO_IF] = 0

Table 17 shows the VERY STRONG configuration output buffer electrical characteristics.

MPC5777M Microcontroller Data Sheet, Rev. 6

38

NXP Semiconductors

Electrical characteristics

1

Table 17. VERY STRONG configuration output buffer electrical characteristics

Value

Symbol

Parameter

Conditions^2,3

Unit

Min

Typ

Max

R_{OH_V}

CC PMOS output impedance

V_{DD_HV_IO}= 5.0 V ± 10%,

20

40

72



VERY STRONG configuration VSIO[VSIO_xx] = 1

I_OH= 8 mA

V

_{DD_HV_IO}= 3.3 V ± 10%,

30

20

30

50

40

50

90

72

90

VSIO[VSIO_xx] = 0,

I

_OH= 7 mA⁴

R_{OL_V}

CC NMOS output impedance

VERY STRONG configuration VSIO[VSIO_xx] = 1

_OL= 8 mA

V_{DD_HV_IO}= 5.0 V ± 10%,



I

V

_{DD_HV_IO}= 3.3 V ± 10%,

VSIO[VSIO_xx] = 0,

_OL= 7 mA⁴

I

f_{MAX_V}

CC Output frequency

V_{DD_HV_IO}= 5.0 V ± 10%,

—

1

—

50

MHz

VERY STRONG configuration C_L= 25 pF⁵

VSIO[VSIO_xx] = 1,

C_L= 15 pF^4,5

6

t_TPD50-50CC 50-50 % Output pad

V_{DD_HV_IO}= 5 V +/- 10 %, C_L=

25 pF

5.5

6.5

ns

propagation delay time

V_{DD_HV_IO}= 5.0 V +/- 10 %, C_L

= 50 pF

V_{DD_HV_IO}= 3.3 V +/- 10 %, C_L

= 15 pF

7.3/7.6 ns

t_{TR_V}

CC 10–90% threshold transition V_{DD_HV_IO}= 5.0 V ± 10%,

5.3

12

45

4

ns

time output pin VERY

STRONG configuration

C_L= 25 pF⁵

V

_{DD_HV_IO}= 5.0 V ± 10%,

3

C_L= 50 pF⁵

V_{DD_HV_IO}= 5.0 V ± 10%,

C_L= 200 pF⁵

14

0.8

1

t_TR20-80CC 20–80% threshold transition V_{DD_HV_IO}= 5.0 V ± 10%,

ns

time⁷output pin VERY

STRONG configuration

C_L= 25 pF⁵

V

_{DD_HV_IO}= 3.3 V ± 10%,

5

C_L= 15 pF⁵

t_TRTTL

CC TTL threshold transition time⁸V_{DD_HV_IO}= 3.3 V ± 10%,

1

5

ns

for output pin in VERY

STRONG configuration

C_L= 25 pF⁵

t_TR20-80CC Sum of transition time

20–80% output pin VERY

V_{DD_HV_IO}= 5.0 V ± 10%,

C_L= 25 pF

—

0

—

9

1

STRONG configuration⁹

V

_{DD_HV_IO}= 3.3 V ± 10%,

C_L= 15 pF⁵

t_{SKEW_V}



CC Difference between rise and V_{DD_HV_IO}= 5.0 V ± 10%,

fall time at 20–80%

C_L= 25 pF⁵

ns

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

39

Electrical characteristics

1

Table 17. VERY STRONG configuration output buffer electrical characteristics (continued)

Value

Symbol

Parameter

Conditions^2,3

Unit

Min

Typ

Max

I_{DCMAX_VS}CC Maximum DC current

—

10

mA

1

2

Refer to FlexRay section for parameter dedicated to this interface.

All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V

are valid for VSIO[VSIO_xx] = 0.

3

During power up operation, the minimum required voltage to come out of reset state is determined by the

V_{PORUP_HV}monitor, which is defined in the voltage monitor electrical characteristics table. Note that the

V

_{PORUP_HV}monitor is connected to the V_{DD_HV_IO_MAIN0}physical I/O segment.

4

5

Only available on the V_{DD_HV_IO_JTAG}, V_{DD_HV_IO_FLEXE}, and V_{DD_HV_IO_FLEX}segments.

C_Lis the sum of external capacitance. Add device and package capacitances (C_IN, defined in the I/O input DC

electrical characteristics table in this Data Sheet) to calculate total signal capacitance (C_TOT= C_L+ C_IN).

6

If two values are given for propagation delay, the first value is for rising edge signals and the second for falling

edge signals.

7

8

9

20–80% transition time as per FlexRay standard.

TTL transition time as for Ethernet standard.

For specification per Electrical Physical Layer Specification 3.0.1, see the dCCTxD_RISE25+dCCTxD_FALL25(Sum of

Rise and Fall time of TxD signal at the output pin) specification in TxD output characteristics table in Section TxD

of this Data Sheet.

Table 18 shows the EBI pad electrical specification.

Table 18. EBI pad output electrical specification

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

EBI Mode Output Specifications¹

C_DRVCC External Bus Load Capacitance MSCR[OERC] = b101

MSCR[OERC] = b110

—

10

20

30

pF

MSCR[OERC] = b111

f_{MAX_EBI}CC External Bus Maximum Operat- C_DRV= 10/20/30 pF

ing Frequency

66.7 MHz

t_{TR_EBI}CC 10%–90% threshold transition C_DRV= 10/20/30 pF

time External Bus output pins

0.9

1.9

—

3.0

4.0

ns

t_{PD_EBI}CC 50%–50% threshold propaga- C_DRV= 10/20/30 pF

tion delay time External Bus

output pins

t_{SKEW_EB}CC Difference between rise and fall

_I time

—

25

12

%

I_{DCMAX_E}CC Maximum DC current

mA

BI

GPIO Mode Output Specifications - MSCR[OERC] = b100

MPC5777M Microcontroller Data Sheet, Rev. 6

40

NXP Semiconductors

Electrical characteristics

Table 18. EBI pad output electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

R_{OH_EBI_}CC PMOS output impedance

4.5 V < V_{DD_HV_IO_EBI}< 5.5 V

Push pull, I_OH< 2 mA

100

225

400



GPIO

R_{OL_EBI_}CC NMOS output impedance

4.5 V < V_{DD_HV_IO_EBI}< 5.5 V

Push pull, I_OH< 2 mA

100

200

400



GPIO

f_{MAX_EBI_}CC Output frequency

C_L= 25 pF²

C_L= 50 pF

C_L= 200 pF

—

12

6

MHz

GPIO

1.5

4

I_{DCMAX_E}CC Maximum DC current

mA

BI_GPIO

1

2

All EBI mode specifications are valid for V_{DD_HV_IO_EBI}= 3.3V +/- 10%.

C_Lis the sum of the capacitance loading external to the device.

3.7

I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair.

DD SS

Table 19 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment remain below the I

value given

MAXSEG

in the Table 6 (Absolute maximum ratings). Use the RMS current consumption values to calculate total segment current.

In order to ensure device functionality, the sum of the dynamic and static currents of the I/O on a single segment should remain

below the I

value given in the Table 8 (Device operating conditions). Use the dynamic current consumption values to

MAXSEG

calculate total segment current.

Pad mapping on each segment can be optimized using the pad usage information provided in the I/O Signal Description table.

The sum of all pad usage ratios within a segment should remain below 100%.

NOTE

In order to maintain the required input thresholds for the SENT interface, the sum of all I/O

pad output percent IR drop as defined in the I/O Signal Description table, must be below

50 %. See the I/O Signal Description attachment.

NOTE

The MPC5777M I/O Signal Description and Input Multiplexing Tables are contained in a



Microsoft Excel workbook file attached to this document. Locate the paperclip symbol on

the left side of the PDF window, and click it. Double-click on the Excel file to open it and

select the I/O Signal Description Table tab.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

41

Electrical characteristics

1

Table 19. I/O consumption

Value

Symbol

Parameter

Conditions²

Unit

Min Typ Max

I_{RMS_W}

I_{RMS_M}

I_{RMS_S}

I_{RMS_V}

CC RMS I/O current for WEAK

configuration

C_L= 25 pF, 2 MHz

V_DD= 5.0 V ± 10%

—

1.1 mA

C_L= 50 pF, 1 MHz

V_DD= 5.0 V ± 10%

1.1

C_L= 25 pF, 2 MHz

0.6

V_DD= 3.3 V ± 10%

C_L= 50 pF, 1 MHz

V_DD= 3.3 V ± 10%

0.6

CC RMS I/O current for MEDIUM

configuration

C_L= 25 pF, 12 MHz

V_DD= 5.0 V ± 10%

4.7 mA

4.8

C_L= 50 pF, 6 MHz

V_DD= 5.0 V ± 10%

C_L= 25 pF, 12 MHz

V_DD= 3.3 V ± 10%

2.6

C_L= 50 pF, 6 MHz

V_DD= 3.3 V ± 10%

2.7

CC RMS I/O current for STRONG

configuration

C_L= 25 pF, 50 MHz

V_DD= 5.0 V ± 10%

19

10

22

11

9

mA

C_L= 50 pF, 25 MHz

V_DD= 5.0 V ± 10%

C_L= 25 pF, 50 MHz

V_DD= 3.3 V ± 10%

C_L= 50 pF, 25 MHz

V_DD= 3.3 V ± 10%

CC RMS I/O current for VERY STRONG C_L= 25 pF, 50 MHz,

configuration

V_DD= 5.0V +/- 10%

C_L= 50 pF, 25 MHz,

V_DD= 5.0V ± 10%

C_L= 25 pF, 50 MHz,

V_DD= 3.3V ± 10%

C_L= 25 pF, 25 MHz,

V_DD= 3.3V ± 10%

I_{RMS_EBI}CC RMS I/O current for External Bus

output pins

C_DRV= 6 pF, f_EBI= 66.7 MHz,

V_{DD_HV_IO_EBI}= 3.3 V ± 10%

C_DRV= 12 pF, f_EBI= 66.7 MHz,

15

27

42

V_{DD_HV_IO_EBI}= 3.3 V ± 10%

C_DRV= 18 pF, f_EBI= 66.7 MHz,

V_{DD_HV_IO_EBI}= 3.3 V ± 10%

C_DRV= 30 pF, f_EBI= 66.7 MHz,

V_{DD_HV_IO_EBI}= 3.3 V ± 10%

MPC5777M Microcontroller Data Sheet, Rev. 6

42

NXP Semiconductors

Electrical characteristics

1

Table 19. I/O consumption

Value

Unit

Symbol

Parameter

Conditions²

Min Typ Max

3

I_{DYN_W}

CC Dynamic I/O current for WEAK

configuration

C_L= 25 pF,

V_DD= 5.0 V ± 10%

—

5.0 mA

C_L= 50 pF,

5.1

V_DD= 5.0 V ± 10%

C_L= 25 pF,

V_DD= 3.3 V ± 10%

2.2

C_L= 50 pF,

V_DD= 3.3 V ± 10%

2.3

I_{DYN_M}

CC Dynamic I/O current for MEDIUM

configuration

C_L= 25 pF,

15

15.5

7.0

7.1

50

mA

V_DD= 5.0 V ± 10%

C_L= 50 pF,

V_DD= 5.0 V ± 10%

C_L= 25 pF,

V_DD= 3.3 V ± 10%

C_L= 50 pF,

V_DD= 3.3 V ± 10%

I_{DYN_S}

CC Dynamic I/O current for STRONG

configuration

C_L= 25 pF,

V_DD= 5.0 V ± 10%

C_L= 50 pF,

V_DD= 5.0 V ± 10%

55

C_L= 25 pF,

V_DD= 3.3 V ± 10%

22

C_L= 50 pF,

V_DD= 3.3 V ± 10%

25

I_{DYN_V}

CC Dynamic I/O current for VERY

STRONG configuration

C_L= 25 pF,

V_DD= 5.0 V ± 10%

60

C_L= 50 pF,

64

V_DD= 5.0 V ± 10%

C_L= 25 pF,

V_DD= 3.3 V ± 10%

26

C_L= 50 pF,

V_DD= 3.3 V ± 10%

29

4

I_{DYN_EBI}

CC Dynamic I/O current for External Bus C_DRV= 10 pF, f_EBI= 66.7 MHz,

output pins _{DD_HV_IO_EBI}= 3.3 V ± 10%

30

V

C_DRV= 20 pF, f_EBI= 66.7 MHz,

50

V_{DD_HV_IO_EBI}= 3.3 V ± 10%

C_DRV= 30 pF, f_EBI= 66.7 MHz,

V_{DD_HV_IO_EBI}= 3.3 V ± 10%

80

1

I/O current consumption specifications for the 4.5 V <= V_{DD_HV_IO}<= 5.5 V range are valid for VSIO_[VSIO_xx] = 1,

and VSIO[VSIO_xx] = 0 for 3.0 V <= V_{DD_HV_IO}<= 3.6 V.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

43

Electrical characteristics

2

During power up operation, the minimum required voltage to come out of reset state is determined by the V_{PORUP_HV}

monitor, which is defined in the voltage monitor electrical characterstics table. Note that the V_{PORUP_HV}monitor is

connected to the V_{DD_HV_IO_MAIN0}physical I/O segment.

3

4

Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible

(timed output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.

For I_{DYN_EBI_GPIO}dynamic current for EBI GPIO mode use the I_{DYN_M}values.

3.8

Reset pad (PORST, ESR0) electrical characteristics

The device implements a dedicated bidirectional reset pin (PORST).

NOTE

PORST pin does not require active control. It is possible to implement an external pull-up

to ensure correct reset exit sequence. Recommended value is 4.7 k.

V

DD

V

DDMIN

V

DD_POR

PORST

V

IH

V

IL

PORST undriven.

Device reset by

internal power-on

reset.

device start-up phase

PORST driven low by

internal power-on reset.

Device reset forced by

external circuitry.

Figure 10. Start-up reset requirements

Figure 11 describes device behavior depending on supply signal on PORST:

1. PORST low pulse amplitude is too low—it is filtered by input buffer hysteresis. Device remains in current state.

2. PORST low pulse duration is too short—it is filtered by a low pass filter. Device remains in current state.

3. PORST low pulse generates a reset:

a) PORST low but initially filtered during at least W

. Device remains initially in current state.

FRST

b) PORST potentially filtered until W

. Device state is unknown: it may either be reset or remains in current

NFRST

state depending on other factors (temperature, voltage, device).

c) PORST asserted for longer than W . Device is under reset.

NFRST

MPC5777M Microcontroller Data Sheet, Rev. 6

44

NXP Semiconductors

Electrical characteristics

V_PORST,V_ESR0

V

DD

V

IH

V

HYS

V

IL

internal

reset

filtered by

hysteresis

filtered by

lowpass filter

unknown reset

state

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

3b

1

2

3a

3c

Figure 11. Noise filtering on reset signal

Table 20. Reset electrical characteristics

Value¹

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

V_IH

V_IL

SR Input high level TTL

(Schmitt trigger)

2.2

—

V_{DD_HV_IO}

+0.4

V

—

SR Input low level TTL

(Schmitt trigger)

–0.4

300

—

0.8

V_HYS

CC Input hysteresis TTL

(Schmitt trigger)

—

mV

V

V_{DD_POR}CC Minimum supply for strong

pull-down activation

1.2

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

45

Electrical characteristics

Table 20. Reset electrical characteristics (continued)

Value¹

Symbol

Parameter

CC Strong pull-down current²

Conditions

Unit

Min

Typ

Max

I_{OL_R}

Device under power-on reset

0.2

—

mA

V_{DD_HV_IO}= V_{DD_POR}

,

V_OL= 0.35 * V_{DD_HV_IO}

Device under power-on reset

3.0 V < V_{DD_HV_IO}< 5.5 V,

V_OL> 0.9 V

11

—

mA

µA

|I_WPU

|

CC Weak pull-up current absolute ESR0 pin

23

—

82

value

V_IN= 0.69 * V_{DD_HV_IO}

ESR0 pin

V_IN= 0.49 * V_{DD_HV_IO}

|I_WPD

|

CC Weak pull-down current

absolute value

PORST pin

V_IN= 0.69 * V_{DD_HV_IO}

—

130

—

µA

PORST pin

V_IN= 0.49 * V_{DD_HV_IO}

40

W_FRST

SR PORST and ESR0 input

filtered pulse

—

500

—

ns

W_NFRST

SR PORST and ESR0 input not

filtered pulse

—

2000

W_FNMI

SR ESR1 input filtered pulse

—

15

—

ns

W_NFNMI

SR ESR1 input not filtered pulse

400

1

2

An external 4.7 KOhm pull-up resistor is recommended to be used with the PORST and ESR0 pins for fast negation

of the signals.

I_{OL_R}applies to both PORST and ESR0: Strong pull-down is active on PHASE0 for PORST. Strong pull-down is active

on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for ESR0.

NOTE

PORST can optionally be connected to an external power-on supply circuitry.

NOTE

No restrictions exist on reset signal slew rate apart from absolute maximum rating

compliance.

MPC5777M Microcontroller Data Sheet, Rev. 6

46

NXP Semiconductors

Electrical characteristics

3.9

Oscillator and FMPLL

The Reference PLL (PLL0) and the System PLL (PLL1) generate the system and auxiliary clocks from the main oscillator

driver.

PLL0_PHI

RCOSC

PLL0

PLL0_PHI1

XOSC

PLL1_PHI

PLL1

Figure 12. PLL integration

Table 21. PLL0 electrical characteristics

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

f_PLL0IN

_PLL0IN

f_PLL0VCO

SR

CC

PLL0 input clock^1,2

—

8

—

44

60

MHz

%

PLL0 input clock duty cycle²

40

PLL0 VCO frequency

600

35

1250

400

MHz

f_PLL0VCOFR

PLL0 VCO free running

frequency

f_PLL0PHI

t_PLL0LOCK

CC

PLL0 output frequency

—

4.762

—

400

110

200

MHz

µs

PLL0 lock time

_PLL0PHISPJ

|

PLL0_PHI single period jitter³

fPLL0IN = 20 MHz (resonator)

f

_PLL0PHI= 400 MHz,

—

ps

6-sigma

_PLL0PHI1SPJ

|

CC

PLL0_PHI1 single period jitter³f_PLL0PHI1= 40 MHz,

—

300⁴

ps

6-sigma

fPLL0IN = 20 MHz (resonator)

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

47

Electrical characteristics

Table 21. PLL0 electrical characteristics (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

_PLL0LTJ

CC

PLL0 output long term jitter^3,410 periods

—

±250

ps

f_PLL0IN= 20 MHz (resonator),

VCO frequency = 800 MHz

accumulated jitter

(80 MHz equivalent

frequency), 6-sigma

pk-pk

16 periods

—

±300

ps

accumulated jitter

(50 MHz equivalent

frequency), 6-sigma

pk-pk

long term jitter

(< 1 MHz equivalent

frequency), 6-sigma

pk-pk)

—

±500

5

ps

I_PLL0

CC

PLL0 consumption

FINE LOCK state

mA

1

f_PLL0INfrequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range 8

MHz–20 MHz.

2

3

4

PLL0IN clock retrieved directly from either internal RCOSC or external XOSC clock. Input characteristics are granted when

using internal RCOSC or external oscillator is used in functional mode.

PLL jitter is guaranteed when transient currents on the V_DDLVsupply are within the I_SPIKEparameter value in Table 10 (DC

electrical specifications).

Noise on the V_{DD_LV}supply with frequency content below 40 KHz and above 50 MHz is filtered by the PLL. Noise on the

V_{DD_LV}supply with frequency content in the range of 40 KHz – 50 MHz must be filtered externally to the device.

Table 22. PLL1 electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

f_PLL1IN

_PLL1IN

f_PLL1VCO

SR

CC

PLL1 input clock¹

—

38

35

—

78

65

MHz

%

PLL1 input clock duty cycle¹

PLL1 VCO frequency

600

35

1250

400

MHz

f_PLL1VCOFR

PLL1 VCO free running

frequency

f_PLL1PHI

t_PLL1LOCK

f_PLL1MOD

CC

PLL1 output clock PHI

PLL1 lock time

—

4.762

—

600

100

250

2

MHz

µs

PLL1 modulation frequency

—

kHz

%

_PLL1MOD

|

PLL1 modulation depth (when Center spread

enabled)

0.25

0.5

—

Down spread

4

%

I_PLL1

CC

PLL1 consumption

FINE LOCK state

6

mA

1

PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when

using internal PLL0 or external oscillator is used in functional mode.

MPC5777M Microcontroller Data Sheet, Rev. 6

48

NXP Semiconductors

Electrical characteristics

1

Table 23. External Oscillator electrical specifications

Value

Unit

Symbol

Parameter

Conditions

Min

Max

f_XTAL

CC

Crystal Frequency Range²

—

4

>8

>20

—

8

20

40

5

MHz

—

T_J= 150 °C

—

t_cst

t_rec

CC

Crystal start-up time ^3,4

Crystal recovery time⁵

ms

V

—

0.5

—

V_IHEXT

EXTAL input high voltage^6,7

(External Clock Input)

V

_REF= 0.28 * V_{DD_HV_IO_JTAG}V_REF

+

0.6

V_ILEXT

C_{S_xtal}

V_EXTAL

CC

EXTAL input low voltage^6,7

(External Clock Input)

V_REF= 0.28 * V_{DD_HV_IO_JTAG}

BGA416, BGA512

—

8

V_REF- 0.6

8.6

V

pF

V

Total on-chip stray capacitance

on XTAL/EXTAL pins⁸

Oscillation Amplitude on the

EXTAL pin after startup⁹

T_J= –40 °C to 150 °C

0.5

1.6

V_HYS

I_XTAL

CC

Comparator Hysteresis

XTAL current^13,10

T_J= –40 °C to 150 °C

0.1

—

1.0

14

V

mA

1

2

3

4

5

All oscillator specifications are valid for VDD_HV_IO_JTAG = 3.0 V – 5.5 V.

The range is selectable by UTEST miscellaneous DCF clients XOSC_LF_EN and XOSC_EN_40MHZ.

This value is determined by the crystal manufacturer and board design.

Proper PC board layout procedures must be followed to achieve specifications.

Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load

capacitor value.

6

7

8

This parameter is guaranteed by design rather than 100% tested.

Applies to an external clock input and not to crystal mode.

See crystal manufacturer’s specification for recommended load capacitor (C_L) values.The external oscillator requires

external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (C_{S_EXTAL}/C_{S_XTAL}

and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load

capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB

capacitance.

)

9

Amplitude on the EXTAL pin after startup is determined by the ALC block, i.e., the Automatic Level Control Circuit. The

function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to

reduce power, distortion, and RFI, and to avoid over-driving the crystal. The operating point of the ALC is dependent on the

crystal value and loading conditions.

10

I

is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum

XTAL

current during startup of the oscillator. The current after oscillation is typically in the 2–3 mA range and is dependent on the

load and series resistance of the crystal. Test circuit is shown in Figure 13.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

49

Electrical characteristics

Table 24. Selectable load capacitance

load_cap_sel[4:0] from DCF record

Load capacitance^1,2(pF)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

1.032

1.976

2.898

3.823

4.751

5.679

6.605

7.536

8.460

9.390

10.317

11.245

12.173

13.101

14.029

14.957

1

2

Values are determined from simulation across process corners and voltage and temperature

variation. Capacitance values vary ±12% across process, 0.25% across voltage, and no variation

across temperature.

Values in this table do not include the die and package capacitances given by Cs_xtal/Cs_extal in

Table 23 (External Oscillator electrical specifications).

MPC5777M Microcontroller Data Sheet, Rev. 6

50

NXP Semiconductors

Electrical characteristics

VDDOSC

Bias

Current

ALC

I_XTAL

XTAL

-

EXTAL

Comparator

+

A

OFF

VSSOSC

VSS

V

Conditions

Z = R + jL

VEXTAL=0 V

VXTAL=0 V

Tester

ALC INACTIVE

PCB

GND

Figure 13. Test circuit

Table 25. Internal RC Oscillator electrical specifications

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

f_Target

CC

IRC target frequency

—

16

—

8

MHz

%

f_{var_noT}

IRC frequency variation

without temperature

compensation

T < 150 ^oC

–8

f_{var_T}

CC

IRC frequency variation with

temperature compensation

T < 150 ^oC

–3

–1

—

3

1

%

1

f_{var_SW}

IRC software trimming

accuracy

Trimming

temperature

f_

IRC Software trimming step

—

-48

—

+40

5

kHz

µs

T_{start_noT}

CC

Startup time to reach within

f_{var_noT}

No trimming

T_{start_T}

Startup time to reach within

f_{var_T}

Factory

trimming

—

120

µs

already applied

I_AVDD5

CC

Current consumption on 5 V

power supply

After T_{start_T}

—

400

175

µA

I_DVDD12

Current consumption on 1.2 V After T_{start_T}

power supply

1

IRC software trimmed accuracy is performed either with the CMU_0 clock monitor, using the XOSC as a reference or

through the CCCU (CAN clock control Unit), extracting reference clock from CAN master clock. Software trim must be

repeated as the device operating temperature varies in order to maintain the specified accuracy.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

51

Electrical characteristics

3.10 ADC specifications

3.10.1 ADC input description

Figure 14 shows the input equivalent circuit for fast SARn channels.

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Sampling

Selection

R

AD

SW1

C

S

P1

P2

Common mode

switch

R

C

R

Channel Selection Switch Impedance

Sampling Switch Impedance

Pin Capacitance (two contributions, C and C

Sampling Capacitance

Common mode switch

SW1

AD

Common mode

resistive ladder

)

P2

P

P1

S

CMSW

CML

Common mode resistive ladder

This figure can be used as approximation circuitry for external filtering definition.

Figure 14. Input equivalent circuit (Fast SARn channels)

Figure 15 shows the input equivalent circuit for SARB channels.

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Selection

Extended

Switch

Sampling

R

AD

SW2

SW1

C

S

C

P2

P1

P3

Common mode

switch

Common mode

resistive ladder

R

:

Channel Selection Switch Impedance (two contributions R

Sampling Switch Impedance

and R

)

SW2

SW

SW1

AD

C :

Pin Capacitance (three contributions, C , C and C )

P

P1 P2 P3

C :

Sampling Capacitance

S

R

Common mode switch

Common mode resistive ladder

CMSW:

:

CML

The above figure can be used as approximation circuitry for external filtering definition.

Figure 15. Input equivalent circuit (SARB channels)

MPC5777M Microcontroller Data Sheet, Rev. 6

52

NXP Semiconductors

Electrical characteristics

1

Table 26. ADC pin specification

Value

Unit

Symbol

Parameter

Conditions

Min

Max

I_{LK_INUD}

CC Input leakage current, two ADC

channels input with weak pull-up and

weak pull-down

T_J< 40 °C

—

50

nA

mA

T_J< 150 °C

150

I_{LK_INUSD}

I_{LK_INREF}

I_{LK_INOUT}

I_INJ

CC Input leakage current, two ADC

channels input with weak pull-up and

strong pull-down

T_J< 40 °C

—

80

T_J< 150 °C

250

CC Input leakage current, two ADC

channels input with weak pull-up and

weak pull-down and alternate reference

T_J< 40 °C

—

160

400

T_J< 150 °C

CC Input leakage current, two ADC

channels input, GPIO output buffer with

weak pull-up and weak pull-down

T_J< 40 °C

—

140

380

T_J< 150 °C

CC Injection current on analog input

preserving functionality

Applies to any analog pins

–3

3

C_{HV_ADC}

C_P1

SR V_{DD_HV_ADV}external capacitance²

1

0

6

0

2.2

10

µF

pF

CC Pad capacitance

—

C_P2

CC Internal routing capacitance

SARn channels

0.5

1

SARB channels

C_P3

C_S

CC Internal routing capacitance

CC SAR ADC sampling capacitance

CC Analog switches resistance

Only for SARB channels

1

pF

k

—

8.5

1.1

1.7

0.6

2.6

3.5

300

R_SWn

SARn channels

SARB channels

R_AD

CC ADC input analog switches resistance

CC Common mode switch resistance

CC Common mode resistive ladder

—

k



R_CMSW

R_CMRL

3

R_SAFEPD

CC Discharge resistance for AN7/AN35

channels (strong pull-down for safety)

1

2

3

All specifications in this table valid for the full input voltage range for the analog inputs.

For noise filtering, add a high frequency bypass capacitance of 0.1 µF between V_{DD_HV_ADV}and V_{SS_HV_ADV}

Safety pull-down is available for port pin PB[5] and PE[14].

.

3.10.2 SAR ADC electrical specification

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The

SARn architecture allows input channel multiplexing.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

53

Electrical characteristics

1

Table 27. SARn ADC electrical specification

Value

Symbol

Parameter

Conditions

Unit

Min

2.0

Max

V_{DD_HV_ADV_S}

V_ALTREF

SR ADC alternate

V_ALTREF< V_{DD_HV_IO_MAIN}

V

reference voltage

SR ADC input signal

SR Clock frequency

SR ADC precharge time

V_IN

0 < V_IN< V_{DD_HV_IO_MAIN}

T_J< 150 °C

V_{SS_HV_ADR_S}V_{DD_HV_ADR_S}

V

MHz

ns

f_ADCK

7.5

135

270

14.6

—

t_ADCPRECH

Fast SAR—fast precharge

Fast SAR—full precharge

—

Slow SAR (SARADC_B)—fast

precharge

—

Slow SAR (SARADC_B)—full

precharge

540

—

V_PRECH

SR Precharge voltage

precision

Full precharge

V_PRECH= V_{DD_HV_ADR_S}/2

T_J< 150 °C

–0.25

0.25

V

Fast precharge

–0.5

0.5

V_PRECH= V_{DD_HV_ADR_S}/2

T_J< 150 °C

V_INTREF

CC Internal reference

voltage precision

Applies to all internal reference

points (V_{SS_HV_ADR_S}

0.20

0.20

,

1/3 * V_{DD_HV_ADR_S}

2/3 * V_{DD_HV_ADR_S}

,

V_{DD_HV_ADR_S}

)

t_ADCSAMPLESR ADC sample time²

Fast SAR – 12-bit configuration

0.750

1.500

—

µs

Slow SAR (SARADC_B) – 12-bit

configuration

t_ADCEVAL

SR ADC evaluation time

12-bit configuration (25 clock

cycles)

1.712

—

7

µs

3,4

I_ADCREFH

CC ADC high reference

current

Run mode t_conv 5 µs

(average across all codes)

µA

Run mode t_conv= 2.5 µs

(average across all codes)

—

7

Power Down mode

Bias Current⁵

—

6

+2

15

4

I_ADCREFL

CC ADC low reference

current

Run mode t_conv 5 µs

µA

V_{DD_HV_ADR_S}<= 5.5 V

Run mode t_conv= 2.5 µs

—

30

1

V_{DD_HV_ADR_S}<= 5.5 V

Power Down mode

V_{DD_HV_ADR_S}<= 5.5 V

MPC5777M Microcontroller Data Sheet, Rev. 6

54

NXP Semiconductors

Electrical characteristics

1

Table 27. SARn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

4

I_{ADV_S}

CC V_{DD_HV_ADV_S}power Run mode t_conv 5 µs

—

–4

4.0

1.0

4

mA

supply current (each

Run mode t_conv= 2.5 µs

ADC)

Power Down mode

TUE₁₂

CC Total unadjusted error T_J< 150 °C,

in 12-bit configuration⁶V_{DD_HV_ADV_S}> 4 V,

V_{DD_HV_ADR_S}> 4 V

LSB

(12b)

T_J< 150 °C,

–6

6

V_{DD_HV_ADV_S}> 4 V,

4 V > V_{DD_HV_ADR_S}> 2 V

T_J< 150 °C,

–12

12

4 V > V_{DD_HV_ADV_S}> 3.5 V

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

55

Electrical characteristics

1

Table 27. SARn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

TUE₁₂

CC TUE degradation due V_IN< V_{DD_HV_ADV_S}

0

LSB

to V_{DD_HV_ADR_S}offset V_{DD_HV_ADR_S} V_{DD_HV_ADV_S}



(12b)

with respect to

[0:25 mV]

V_{DD_HV_ADV_S}

V_IN< V_{DD_HV_ADV_S}

V_{DD_HV_ADR_S} V_{DD_HV_ADV_S}

[25:50 mV]

–2

–4

2

4

V_IN< V_{DD_HV_ADV_S}

V_{DD_HV_ADR_S} V_{DD_HV_ADV_S}

[50:75 mV]

V_IN< V_{DD_HV_ADV_S}

–6

6

V_{DD_HV_ADR_S} V_{DD_HV_ADV_S}

[75:100 mV]

V_{DD_HV_ADV_S}< V_IN

<

–2.5

2.5

V_{DD_HV_ADR_S}

V_{DD_HV_ADR_S} V_{DD_HV_ADV_S}

[0:25 mV]



V_{DD_HV_ADV_S}< V_IN

<

–4

–7

4

7

V_{DD_HV_ADR_S}

V_{DD_HV_ADR_S} V_{DD_HV_ADV_S}

[25:50 mV]

V_{DD_HV_ADV_S}< V_IN

<

V_{DD_HV_ADR_S}

V_{DD_HV_ADR_S} V_{DD_HV_ADV_S}

[50:75 mV]

V_{DD_HV_ADV_S}< V_IN

<

–12

12

V_{DD_HV_ADR_S}

V_{DD_HV_ADR_S} V_{DD_HV_ADV_S}

[75:100 mV]

DNL

INL

CC Differential

non-linearity

V

_{DD_HV_ADV_S}> 4 V

–1

–3

–5

2

3

5

LSB

V_{DD_HV_ADR_S}> 4 V

(12b)

CC Integral non-linearity 4.0 V < V_{DD_HV_ADV_S}< 5.5 V

4.0 V < V_{DD_HV_ADR_S}< 5.5 V

LSB

(12b)

V_{DD_HV_ADV_S}= 2V

V_{DD_HV_ADR_S}= 2 V

1

2

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress

ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect

device reliability or cause permanent damage to the device.

Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal

sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB

within the sampling window. Please refer to Figure 14 and Figure 15 for models of the internal ADC circuit, and the

values to use in external RC sizing and calculating the sampling window duration.

3

I_ADCREFHand I_ADCREFLare independent from ADC clock frequency. It depends on conversion rate: consumption is

driven by the transfer of charge between internal capacitances during the conversion.

4

5

Current parameter values are for a single ADC.

Extra bias current is present only when BIAS is selected.

MPC5777M Microcontroller Data Sheet, Rev. 6

56

NXP Semiconductors

Electrical characteristics

6

This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to

± 6 LSB.

3.10.3 S/D ADC electrical specification

The SDn ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps maximum output rate.

1

Table 28. SDn ADC electrical specification

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

—

V_{DD_HV_ADV}

V_IN

SR ADC input signal

—

0

V

_D

2

V_{IN_PK2PK}

SR Input range peak to Single ended

peak V_INM= V_{SS_HV_ADR_D}

V_{DD_HV_ADR_D}/GAIN

±0.5*V_{DD_HV_ADR_D}

3

V

V_INM

_{IN_PK2PK}= V_INP–

Single ended

4

V_INM= 0.5*V_{DD_HV_ADR_D}

GAIN = 1

Single ended

±V_{DD_HV_ADR_D}/GAIN

V_INM= 0.5*V_{DD_HV_ADR_D}

GAIN = 2,4,8,16

Differential,

±V_{DD_HV_ADR_D}/GAIN

0 < V_IN< V_{DD_HV_IO_MAIN}

f_{ADCD_M}

f_{ADCD_S}

SR S/D modulator Input

Clock

—

4

14.4

—

16

MHz

ksps

SR Output conversion

rate

—

333

CC Oversampling ratio

Internal modulator

24

—

256

—

bit

—

External modulator

2’s complement notation

RESOLUTION

GAIN

CC S/D register

resolution⁵

16

SR ADC gain

Defined via ADC_SD[PGA]

register. Only integer powers of 2

are valid gain values.

1

—

16

—

_GAIN

CC Absolute value of the Before calibration (applies to gain

—

1.5

5

%

ADC gain error^6,7

setting = 1)

After calibration, V_{DD_HV_ADR_D}

5%

V_{DD_HV_ADV_D} 10%

T_J 50 °C



mV

After calibration, V_{DD_HV_ADR_D}

5%

V_{DD_HV_ADV_D} 10%

T_J 100 °C

—

7.5

10

After calibration, V_{DD_HV_ADR_D}

5%

V_{DD_HV_ADV_D} 10%

T_J 150 °C

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

57

Electrical characteristics

1

Table 28. SDn ADC electrical specification (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

V_OFFSET

CC Input Referred Offset Before calibration (applies to all

—

10*

(1+1/gain)

20

mV

Error^6,7,8

gain settings – 1, 2, 4, 8, 16)

After calibration,

V_{DD_HV_ADR_D} 10%

T_J 50 °C

—

5

After calibration, V_{DD_HV_ADV_D}

10%

T_J 100 °C



7.5

10

—

After calibration, V_{DD_HV_ADV_D}

10%

T_J 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 1

0.5

80

SNR_DIFF150CC Signal to noise ratio in

differential mode

—

dBFS

150 ksps output rate

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 2

77

74

71

68

—

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 4

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 8

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 16

T_J< 150 °C

MPC5777M Microcontroller Data Sheet, Rev. 6

58

NXP Semiconductors

Electrical characteristics

1

Table 28. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 1

SNR_DIFF333CC Signal to noise ratio in

differential mode

74

—

dBFS

333 ksps output rate

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 2

71

68

65

62

74

71

68

65

62

—

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 4

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 8

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 16

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 1

SNR_SE150CC Signal to noise ratio in

single ended mode

150 ksps output

dBFS

T_J< 150 °C

rate¹¹

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 2

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 4

T_J< 150 °C

4.5 < V_{DD_HV_ADV_D}< 5.5^9,10,17

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

GAIN = 8

T_J< 150 °C

9,10,17

4.5 < V_{DD_HV_ADV_D}< 5.5

V_{DD_HV_ADR_D}=V_{DD_HV_ADV_D}

GAIN = 16

T_J< 150 °C

SFDR

CC Spurious free

dynamic range

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

60

—

dBc

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

59

Electrical characteristics

1

Table 28. SDn ADC electrical specification (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

Z_DIFF

D Differential Input

impedance¹²¹³

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

GAIN=1

GAIN=2

GAIN=4

GAIN=8

GAIN=16

—

1000

600

300

200

1400

1000

700

500

110

1250

800

400

250

1800

1300

950

650

144

1500

1000

500

k

300

Z_CM

D Common Mode Input

impedance^{14 15}

2200

1600

1150

800

k

800

R_BIAS

V_INTCM

V_BIAS

D Bare Bias resistance

180

k

%

V

D common mode input

reference voltage¹⁶

—

-12

—

+12

—

CC Bias voltage

V_{DD_HV_}

_{ADR_D}/2

V_BIAS

CC Bias voltage accuracy

—

–2.5

54

—

+2.5

—

%

V_cmrr

SR Common mode

rejection ratio

dB

R_Caaf

SR Anti-aliasing filter

CC

External series resistance

Filter capacitances

—

20

—

k

pF

180

0.01

f_PASSBANDCC Pass band¹⁷

0.333 *

kHz

f_{ADCD_S}

_RIPPLE

CC Pass band ripple¹⁸

0.333 * f_{ADCD_S}

CC Stop band attenuation [0.5 * f_{ADCD_S}, 1.0 * f_{ADCD_S}

[1.0 * f_{ADCD_S}, 1.5 * f_{ADCD_S}

–1

40

45

50

55

60

—

1

%

F_rolloff

]

—

dB

[1.5 * f_{ADCD_S}, 2.0 * f_{ADCD_S}

[2.0 * f_{ADCD_S}, 2.5 * f_{ADCD_S}

[2.5 * f_{ADCD_S}, f_{ADCD_M}/2]

MPC5777M Microcontroller Data Sheet, Rev. 6

60

NXP Semiconductors

Electrical characteristics

1

Table 28. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

_GROUP

CC Group delay

Within pass band – Tclk is f_{ADCD_M}

/ 2

—

OSR = 24

—

238.5

278

Tclk

OSR = 28

OSR = 32

317.5

357

OSR = 36

OSR = 40

396.5

436

OSR = 44

OSR = 48

475.5

554.5

633.5

712.5

699

OSR = 56

OSR = 64

OSR = 72

OSR = 75

OSR = 80

791.5

870.5

949.5

1107.5

1265.5

1423.5

1581.5

1739.5

1897.5

2213.5

2529.5

OSR = 88

OSR = 96

OSR = 112

OSR = 128

OSR = 144

OSR = 160

OSR = 176

OSR = 192

OSR = 224

OSR = 256

Distortion within pass band

–0.5/

+0.5/

—

f_ADCD

f_{ADCD_S}

_S

f_HIGH

CC High pass filter 3dB Enabled

frequency

—

10e-5*

f_{ADCD_S}

—

µs

—

t_STARTUP

t_LATENCY

CC Start-up time from

power down state

—

100

CC Latency between

input data and

HPF = ON

_GROUP+

f_{ADCD_S}

converted data when

input mux does not

change¹⁹

HPF = OFF

_GROUP

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

61

Electrical characteristics

1

Table 28. SDn ADC electrical specification (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

t_SETTLING

CC Settling time after

mux change

Analog inputs are muxed

HPF = ON

—

2*_GROUP

3*f_{ADCD_S}

+

—

HPF = OFF

—

2*_GROUP+

2*f_{ADCD_S}

t_ODRECOVERYCC Overdrive recovery

time

After input comes within range

from saturation

2*_GROUP+

f_{ADCD_S}

HPF = ON

HPF = OFF

—

2*_GROUP

75*GAIN

600

—

fF

C_{S_D}

CC S/D ADC sampling

capacitance after

GAIN = 1, 2, 4, 8

GAIN = 16

sampling switch²⁰

I_BIAS

CC Bias consumption

At least 1 ADCD enabled

3.5

mA

I_{ADV_D}

CC V_{DD_HV_ADV_D}power ADCD enabled

—

72

—

supply current (each

ADC)

I_{ADR_D}

CC Sum of all ADC

reference

ADCD enabled, f_{ADCD_M}

14.4 MHz

=

30

—

µA

consumption

SINAD_DIFF150CC Signal to Noise and Gain = 1

dBFS

Distortion Ratio,

Differential Mode,

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

150 Ksps output rate Tj < 150 °C

Gain = 2

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

72

69

—

Gain = 4

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 8

68.8

64.8

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 16

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

MPC5777M Microcontroller Data Sheet, Rev. 6

62

NXP Semiconductors

Electrical characteristics

1

Table 28. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

SINAD_DIFF333CC Signal to Noise and Gain = 1

Distortion Ratio, 4.5 V < V_{DD_HV_ADV_D}< 5.5 V

66

—

dBFS

Single-ended Mode, V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

150Ksps output rate Tj < 150 °C

Gain = 2

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

66

63

62

59

66

63

62

59

—

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 4

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 8

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 16

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

SINAD_SE150CC Signal to Noise and Gain = 1

Distortion Ratio, 4.5 V < V_{DD_HV_ADV_D}< 5.5 V

dBFS

Single-ended Mode, V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

150Ksps output rate Tj < 150 °C

Gain = 2

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 4

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 8

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 16

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

63

Electrical characteristics

1

Table 28. SDn ADC electrical specification (continued)

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

THD_DIFF150CC Total Harmonic

Gain = 1

65

—

dBFS

Distortion, Differential 4.5 V < V_{DD_HV_ADV_D}< 5.5 V

Mode, 150Ksps

output rate

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 2

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

68

74

80

65

68

74

80

—

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 4

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 8

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 16

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

THD_DIFF333CC Total Harmonic

Gain = 1

dBFS

Distortion, Differential 4.5 V < V_{DD_HV_ADV_D}< 5.5 V

Mode, 333Ksps

output rate

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 2

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 4

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 8

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 16

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

MPC5777M Microcontroller Data Sheet, Rev. 6

64

NXP Semiconductors

Electrical characteristics

1

Table 28. SDn ADC electrical specification (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

THD_SE150CC Total Harmonic

Distortion,

Gain = 1

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

68

—

dBFS

Single-ended Mode, V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

150Ksps output rate Tj < 150 °C

Gain = 2

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

68

—

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 4

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 8

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

Gain = 16

4.5 V < V_{DD_HV_ADV_D}< 5.5 V

V_{DD_HV_ADR_D}= V_{DD_HV_ADV_D}

Tj < 150 °C

1

2

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress

ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect

device reliability or cause permanent damage to the device.

For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and

the signal will only be ‘clipped’.

3

4

5

V_INPis the input voltage applied to the positive terminal of the SDADC.

V_INMis the input voltage applied to the negative terminal of the SDADC.

When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. The

gives an effective resolution of 15 bits.

6

7

Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.

Calibration of gain is possible when gain = 1.

Offset Calibration should be done with respect to 0.5*V_{DD_HV_ADR_D}for differential mode and single ended mode with

negative input=0.5*V_{DD_HV_ADR_D}

.

Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0".

Both offset and Gain Calibration is guaranteed for ±5% variation of V_{DD_HV_ADR_D}, ±10% variation of V_{DD_HV_ADV_D}

and ± 50 °C temperature variation.

,

8

9

Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred

offset error.

S/D ADC is functional in the range 3.6 V – 4.5 V, SNR parameter degrades by 3 dB. Degraded SNR value based on

simulation.

¹⁰S/D ADC is functional in the range 3.0 V –4.5 V, SNR parameter degrades by 9 dB. Degraded SNR value based on

simulation.

¹¹This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to

a value of 6 dB less.

¹²Input impedance in differential mode Z_IN(input impedance) = Z_DIFF

.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

65

Electrical characteristics

¹³Impedance given at F_{ADCD_M}= 16 MHz. Impedance is inversely proportional to SDADC clock frequency.

Z

_DIFF(F_{ADCD_M}) = (16 MHz / F_{ADCD_M}) * Z_DIFF, Z_CM(F_{ADCD_M}) = (16MHz / F_{ADCD_M}) * Z_CM

¹⁴Input impedance in single-ended mode Z_IN= (2 * Z_DIFF* Z_CM) / (Z_DIFF+ Z_CM).

¹⁵Impedance given at F_{ADCD_M}= 16 MHz. Impedance is inversely proportional to SDADC clock frequency.

Z_DIFF(F_{ADCD_M}) = (16 MHz / F_{ADCD_M}) * Z_DIFF, Z_CM(F_{ADCD_M}) = (16MHz / F_{ADCD_M}) * Z_CM

.

¹⁶Vintcm is the common mode input reference voltage for the SDADC, and has a nominal value of (V_{DD_HV_ADC}

V_{SS_HV_ADC}) / 2.

-

¹⁷SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the

frequency range of f_{ADCD_M}– f_{ADCD_S}to f_{ADCD_M}+ f_{ADCD_S}, where f_{ADCD_M}is the input sampling frequency, and

f

_{ADCD_S}is the output sample frequency. A proper external input filter should be used to remove any interfering signals

in this frequency range.

¹⁸The ±1% passband ripple specification is equivalent to 20 * log₁₀(0.99) = 0.087 dB.

¹⁹Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by

the different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain

synchronizers. The time elapsed between data availability at pin and internal S/D module registers is given by the

below formula:

REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fPBRIDGEx_CLK

where fADCD_S is the frequency of the sampling clock, fADCD_M is the frequency of the modulator, and

fPBRIDGEx_CLK is the frequency of the peripheral bridge clock feeds to the ADC S/D module. The (~+1) symbol

refers to the number of clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the

signal during clock domain crossing.

Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received

from the ADC S/D module.

²⁰This capacitance does not include pin capacitance, that can be considered together with external capacitance, before

sampling switch.

3.11 Temperature sensor

The following table describes the temperature sensor electrical characteristics.

Table 29. Temperature sensor electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

—

CC Temperature monitoring range

CC Sensitivity

—

–40

—

5.18

—

150

—

°C

mV/°C

°C

T_SENS

T_ACC

—

T_J 150 °C

—

CC Accuracy

–3

—

3

I_{TEMP_SENS}CC V_{DD_HV_ADV_S}power supply

current

—

700

µA

3.12 LVDS Fast Asynchronous Serial Transmission (LFAST) pad

electrical characteristics

The LFAST pad electrical characteristics apply to both the SIPI and high-speed debug serial interfaces on the device. The same

LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces, with different characteristics given in the

following tables.

MPC5777M Microcontroller Data Sheet, Rev. 6

66

NXP Semiconductors

Electrical characteristics

3.12.1 LFAST interface timing diagrams

Signal excursions above this level NOT allowed

Max. common mode input at RX

1743 mV

1600 mV

_VOD



Max Differential Voltage =

285 mV p-p (LFAST)

400 mV p-p (MSC/DSPI)

Minimum Data Bit Time

Opening =

0.55 * T (LFAST)

0.50 * T (MSC/DSPI)

V_OS= 1.2 V +/- 10%

TX common mode

“No-Go” Area

_VOD



Min Differential Voltage =

100 mV p-p (LFAST)

150 mV p-p (MSC/DSPI)

V_ICOM

PER_EYE

Data Bit Period

T = 1 /F_DATA

Min. common mode input at RX

150 mV

0 V

Signal excursions below this level NOT allowed

Figure 16. LFAST and MSC/DSPI LVDS timing definition

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

67

Electrical characteristics

H

lfast_pwr_down

L

t

PD2NM_TX

Differential TX

Data Lines

pad_p/pad_n

Data Valid

Figure 17. Power-down exit time

V_IH

Differential TX

Data Lines

90%

10%

pad_p/pad_n

V_IL

t_TR

Figure 18. Rise/fall time

3.12.2 LFAST and MSC/DSPI LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.

1,2

Table 30. LVDS pad startup and receiver electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

STARTUP^3,4

t_{STRT_BIAS}CC Bias current reference startup time⁵

—

0.5

0.4

4

µs

t_{PD2NM_TX}CC Transmitter startup time (power

down to normal mode)⁶

2.75

MPC5777M Microcontroller Data Sheet, Rev. 6

68

NXP Semiconductors

Electrical characteristics

1,2

Table 30. LVDS pad startup and receiver electrical characteristics (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

t_{SM2NM_TX}CC Transmitter startup time (sleep mode Not applicable to the

—

0.2

0.5

µs

ns

to normal mode)⁷

MSC/DSPI LVDS pad

t_{PD2NM_RX}CC Receiver startup time (power down

to normal mode)⁸

—

20

—

40

50

t_{PD2SM_RX}CC Receiver startup time (power down Not applicable to the

ns

to sleep mode)⁹

MSC/DSPI LVDS pad

I_{LVDS_BIAS}CC LVDS bias current consumption

Tx or Rx enabled

0.95

mA

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Z₀

SR Transmission line characteristic

—

47.5

50

52.5

105



impedance

Z_DIFF

SR Transmission line differential

impedance

—

95

100

RECEIVER

V_ICOM

|_VI|

V_HYS

R_IN

SR Common mode voltage

SR Differential input voltage¹²

CC Input hysteresis

—

0.15¹⁰

100

25

—

1.6¹¹

—

V

mV



—

CC Terminating resistance

CC Differential input capacitance¹³

3.0 V–5.5 V

—

80

125

3.5

—

150

6.0

0.5

C_IN

—

pF

mA

I_{LVDS_RX}CC Receiver DC current consumption

Enabled

—

1

The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed De-

bug (HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the conditions.

2

3

All LVDS pad electrical characteristics are valid from –40 °C to 150 °C.

All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in

the LVDS control registers (LCR) of the LFAST and High-Speed Debug modules. The value of the LCR bits for the

LFAST/HSD modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode.

Startup times for MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS

in the corresponding SIUL2 MSCR ODC field.

4

5

6

7

8

9

Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmit-

ter electrical characteristic tables.

Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after

being enabled.

Total transmitter startup time from power down to normal mode is t_{STRT_BIAS}+ t_{PD2NM_TX}+ 2 peripheral bridge clock

periods.

Total transmitter startup time from sleep mode to normal mode is t_{SM2NM_TX}+ 2 peripheral bridge clock periods. Bias

block remains enabled in sleep mode.

Total receiver startup time from power down to normal mode is t_{STRT_BIAS}+ t_{PD2NM_RX}+ 2 peripheral bridge clock

periods.

Total receiver startup time from power down to sleep mode is t_{PD2SM_RX}+ 2 peripheral bridge clock periods. Bias

block remains enabled in sleep mode.

¹⁰Absolute min = 0.15 V – (285 mV/2) = 0 V

¹¹Absolute max = 1.6 V + (285 mV/2) = 1.743 V

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

69

Electrical characteristics

¹²The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure proper LFAST receive

timing.

¹³Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.

1,2

Table 31. LFAST transmitter electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

f_DATA

V_OS

SR Data rate

—

312/320³Mbps

CC Common mode voltage

1.08

110

1.32

285

V

|

CC Differential output voltage swing

(terminated)^4,5

171

mV

VOD

t_TR

CC Rise/Fall time (absolute value of the

differential output voltage swing)^4,5

—

0.26

—

1.5

ns

C_L

SR External lumped differential load

capacitance³

V_{DD_HV_IO}= 4.5 V

V_{DD_HV_IO}= 3.0 V

Enabled

—

10.0

8.5

pF

I_{LVDS_TX}CC Transmitter DC current consumption

3.2

mA

1

The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance

values shown in Figure 19.

2

3

All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from –40 °C to 150 °C.

The 312 Mbps data rate is achieved with a 26 MHz reference clock, and 320 Mbps is achieved with a 10 or 20 MHz

reference clock.

4

5

Valid for maximum data rate f_DATA. Value given is the capacitance on each terminal of the differential pair, as shown in

Figure 19.

Valid for maximum external load C_L.

1,2

Table 32. MSC/DSPI LVDS transmitter electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

Data Rate

f_DATA

V_OS

SR Data rate

—

80

Mbps

V

CC Common mode voltage

1.08

150

1.32

400

|

CC Differential output voltage swing

(terminated)^3,4

214

mV

VOD

t_TR

CC Rise/Fall time (absolute value of the

differential output voltage swing)^3,4

—

0.8

—

4.0

ns

C_L

SR External lumped differential load

capacitance³

V_{DD_HV_IO}= 4.5 V

—

50

39

pF

V_{DD_HV_IO}= 3.0 V

I_{LVDS_TX}CC Transmitter DC current consumption

Enabled

4.0

mA

1

2

The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst case

internal capacitance values given in Figure 19.

All MSC and DSPI LVDS pad electrical characteristics are valid from –40 °C to 150 °C.

MPC5777M Microcontroller Data Sheet, Rev. 6

70

NXP Semiconductors

Electrical characteristics

3

4

Valid for maximum data rate f_DATA. Value given is the capacitance on each terminal of the differential pair, as shown

in Figure 19.

Valid for maximum external load C_L.

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WHUPLQDWRU

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Figure 19. LVDS pad external load diagram

3.12.3 LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.

1

Table 33. LFAST PLL electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min

Nominal

Max

f_{RF_REF}SR PLL reference clock frequency

—

10

–1

45

—

26

1

MHz

%

ERR_REFCC PLL input reference clock frequency error

—

DC_REF

PN

CC PLL input reference clock duty cycle

55

%

CC Integrated phase noise (single side band)

f_{RF_REF}= 20 MHz

–58

–64

dBc

f

_{RF_REF}= 10 MHz

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

71

Electrical characteristics

1

Table 33. LFAST PLL electrical characteristics (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Nominal

Max

f_VCO

CC PLL VCO frequency

CC PLL phase lock³

—

640²

—

40

MHz

µs

t_LOCK

PER_REFSR Input reference clock jitter (peak to peak)

Single period,

—

300

ps

f

_{RF_REF}= 10 MHz

Long term,

–500

—

500

400

ps

f

_{RF_REF}= 10 MHz

—

PER_EYECC Output Eye Jitter (peak to peak)⁴

1

2

The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.

The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO

frequency is 624 MHz.

3

4

The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral

bridge clock that is connected to the PLL on the device.

Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. See

Figure 19.

3.13 Aurora LVDS electrical characteristics

The following table describes the Aurora LVDS electrical characteristics.

NOTE

The Aurora interface is AC coupled, so there is no common-mode voltage specification.

1,2

Table 34. Aurora LVDS electrical characteristics

Value

Symbol

Parameter

Conditions

Unit

Min Typ Max

Transmitter

F_TX

CC Transmit Data Rate

—

1.25 Gbps

V_{OD_LVDS}



CC Differential output voltage swing

(terminated)³

±400 ±600 ±800 mV

t_{TR_LVDS}

R_{V_L_Tx}

T_Loss

CC Rise/Fall time (10%–90% of swing)

SR Differential Terminating resistance

—

60

—

ps



81 100 120

CC Transmission Line Loss due to loading

effects

—

6⁴

dB

Transmission line characteristics (PCB track)

L_LINE

Z_LINE

SR Transmission line length

—

45

—

50

—

20

55

cm



SR Transmission line characteristic impedance

C_{ac_clk}

SR Clock Receive Pin External AC Coupling

Capacitance

Values are nominal, valid

for +/– 50% tolerance

100

270

pF

MPC5777M Microcontroller Data Sheet, Rev. 6

72

NXP Semiconductors

Electrical characteristics

1,2

Table 34. Aurora LVDS electrical characteristics (continued)

Value

Unit

Symbol

Parameter

Conditions

Min Typ Max

C_{ac_tx}

SR Transmit Lane External AC Coupling

Capacitance

Values are nominal, valid

for +/– 50% tolerance

250

—

2000 pF

Receiver

F_RX

CC Receive Clock Rate

T_J= 150 °C

—

1.25 Gbps

1000 mV

V_{I_L}



SR Differential input voltage (peak to peak)

CC Differential Terminating resistance

—

200

R_{V_L_Rx}

81 100 120



1

2

3

All Aurora electrical characteristics are valid from –40 °C to 150 °C, except where noted.

All specifications valid for maximum transmit data rate F_TX

The minimum value of 400 mV is only valid for differential terminating resistance (R_{V_L}) = 99 ohm to 101 ohm. The

differential output voltage swing tracks with the value of R_{V_L}

.

4

Transmission line loss maximum value is specified for the maximum drive level of the Aurora transmit pad.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

73

Electrical characteristics

3.14 Power management: PMC, POR/LVD, sequencing

3.14.1 Power management electrical characteristics

The power management module monitors the different power supplies. It also generates the internal supplies that are required

for correct device functionality. The power management is supplied by the V

supply (see Table 8).

DD_HV_PMC

3.14.2 Power management integration

In order to ensure correct functionality of the device, it is recommended to follow below integration scheme.

C_{HV_PMC}

C_{HV_FLA}

VDD_HV_IO

VDD_LV

(2)

MPC5777M

(1)

C_{HV_IO}

C_LV

VSS

(1) One capacitance near each V_{DD_LV}pin

(2) One capacitance near each V_{DD_HV}pin

Figure 20. Recommended supply pin circuits

MPC5777M Microcontroller Data Sheet, Rev. 6

74

NXP Semiconductors

Electrical characteristics

The following table describes the supply stability capacitances required on the device for proper operation.

Table 35. Device power supply integration

Value¹

Symbol

Parameter

Conditions

Unit

Min Typ Max

C_LV

SR Minimum VDD_LV external Bulk capacitance

External regulator

bandwidth > 20 KHz

10

—

µF

capacitance²

Total bypass

capacitance at

external pin³

Note

3

C_{HV_IO}

C_{HV_FLA}

C_{HV_PMC}

SR Minimum VDD_HV_IO external capacitance

SR Minimum VDD_HV_FLA external capacitance^4,5

SR Minimum V_{DD_HV_PMC}External Capacitance^6,7

—

4.7

—

µF

0.75 1.5

512 BGA balls A29, 2.2 4.7

B28, F24, and G23

C_{HV_ADC}

SR Minimum V_{DD_HV_ADV}external capacitance⁸

1.5 3.3

—

µF

1

2

3

4

See Figure 20 for capacitor integration.

Recommended X7R or X5R ceramic low ESR capacitors, ±15% variation over voltage, temperature, and aging.

Each VDD_LV pin requires both a 0.1µF and 0.01µF capacitor for high-frequency bypass and EMC requirements.

The recommended flash regulator composition capacitor is 1.5 µF typical X7R or X5R, with –50% and +35% as min and

max. This puts the min cap at 0.75 µF.

5

6

7

8

Start-up time of the internal flash regulator from release of the LVD360 is worst case 500 us. This is based on the typical

CHV_FLA bulk capacitance value.

For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between V_{DD_HV_PMC}and

V_{SS_HV}

.

In the 512BGA package, V_{DD_HV_PMC}is shorted to V_{DD_HV_IO_MAIN}. Use a local 200 nF capacitor on 512BGA balls A29,

B28, F24, G3, in addition to the normal V_{DD_HV_IO_MAIN}bulk and local external capacitance.

For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between V_{DD_HV_ADV}and

V_{SS_HV_ADV}

.

3.14.3 3.3 V flash supply

Table 36. Flash power supply

Value

Symbol

Parameter

Conditions

Unit

Min Typ Max

1

V_{DD_HV_FLA}

CC

Flash regulator DC output voltage

Before trimming

3.1²3.3

3.15 3.3

3.5

3.4

V

After trimming

–40°C  T_J 25°C

After trimming

3.10 3.3

3.4

25°C  T_J150°C

1

2

Min value accounts for all static and dynamic variations of the regulator (min cap as 0,75uF).

Min value of 3.1 V for VDD_HV_REG at 3.15V assumes that the auxiliary regulator on VDD_LV does not actively provide

any current to the chip. If the auxiliary regulator actively provides current, the min value may go lower than 3.1 V drop to

IR drop caused by auxiliary current demanding on VDD_HV_REG supply.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

75

Electrical characteristics

3.14.4 Device voltage monitoring

The LVD/HVDs and their associated levels for the device are given in the following table. The figure below illustrates the

workings of voltage monitoring threshold.

V

DD_xxx

V

HVD(rise)

HVD(fall)

V

LVD(rise)

LVD(fall)

t

VDRELEASE

VDASSERT

HVD TRIGGER

(INTERNAL)

t

VDASSERT

VDRELEASE

LVD TRIGGER

(INTERNAL)

Figure 21. Voltage monitor threshold definition

Table 37. Voltage monitor electrical characteristics

1

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

2

V_{PORUP_LV}CC LV supply power on reset threshold Rising voltage (power up)

1111

—

1235 mV

1125

Falling voltage (power down)³1015

Hysteresis on power-up

See note ⁵

50

—

V_LVD096

V_LVD108

V_LVD112

CC LV internal⁴supply low voltage

monitoring

1015

1145 mV

CC Core LV internal⁴supply low voltage See note ⁶

monitoring

1150

1175

—

1220 mV

1235 mV

CC LV external⁷supply low voltage

monitoring

See note ⁵

MPC5777M Microcontroller Data Sheet, Rev. 6

76

NXP Semiconductors

Electrical characteristics

1

Table 37. Voltage monitor electrical characteristics (continued)

Value

Unit

Symbol

Parameter

Conditions

See note ⁸

Min

Typ

Max

V_HVD140

V_HVD145

CC LV external¹⁰supply high voltage

monitoring

1385

—

1475 mV

CC LV externa¹⁰supply high voltage

reset threshold

—

1430

4040

2730

2870

—

1510 mV

4480¹⁰mV

3030

V_{PORUP_HV}CC HV supply power on reset threshold⁹Rising voltage (power up) on

PMC/IO Main supply

2

Rising voltage (power up) on

IO JTAG and Osc supply

Rising voltage (power up) on

ADC supply

3182

Falling voltage (power down)¹¹2850

—

3162

Hysteresis on power up¹²

878

2420

2400

2750

2700

—

1630

V_POR240

V_LVD270

V_LVD295

V_HVD360

V_LVD360

V_LVD400

V_HVD600

CC HV supply power-on reset voltage

monitoring

Rising voltage

2780 mV

2760

Falling voltage

Rising voltage

CC HV supply low voltage monitoring

3000 mV

2950

Falling voltage

Rising voltage

CC Flash supply low voltage

monitoring¹³

3120 mV

3100

Falling voltage

2920

3435

3415

—

CC Flash supply high voltage monitoring Rising voltage

Falling voltage

3650 mV

—

CC HV supply low voltage monitoring

CC HV supply high voltage monitoring

Rising voltage

Falling voltage

Rising voltage

Falling voltage

Rising voltage

Falling voltage

4000 mV

3880

3600

4110

3970

5560

5500

0.1

4410 mV

4270

5960 mV

5900

t_VDASSERTCC Voltage detector threshold crossing

assertion

—

2

µs

t_VDRELEASECC Voltage detector threshold crossing

de-assertion

—

5

—

20

µs

1

2

For V_{DD_LV}levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR

drop is estimated by multiplying the supply current by 0.5 .

V_{PORUP_LV}and V_{PORUP_HV}threshold are untrimmed values before completion of the power-up sequence. All other

LVD/HVD thresholds are provided after trimming.

3

4

5

Assume all of LVDs on LV supplies disabled.

LV internal supply levels are measured on device internal supply grid after internal voltage drop.

LVD is released after t_VDRELEASEtemporization when upper threshold is crossed, LVD is asserted t_VDASSERTafter

detection when lower threshold is crossed.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

77

Electrical characteristics

6

This specification is driven by LVD108_C. There are additional LVDs on PLL and Flash VDD_LV supply nets which will

assert at voltage below LVD108_C.

7

LV external supply levels are measured on the die side of the package bond wire after package voltage drop. This is

monitoring external regulator supply voltage and board voltage drop. This does not guarantee device is working down

to minimum threshold. For minimum supply, refer to operating condition table.

8

HVD is released after t_VDRELEASEtemporization when lower threshold is crossed, HVD is asserted t_VDASSERTafter

detection when upper threshold is crossed. HVD140 does not cause reset.

9

This supply also needs to be below 5472 mV (untrimmed HVD600 min)

10

The PMC supply also needs to be below 5472 mV (untrimmed HVD600 mV).

¹¹Untrimmed LVD300_A will be asserted first on power down.

¹²Hysteresis is implemented only between the VDD_HV_IO_MAIN High voltage Supplies and the ADC high voltage

supply. When these two supplies are shorted together, the hysteresis is as is shown in Table 37. If the supplies are not

shorted (VDD_IO_MAIN and ADC high voltage supply), then there will be no hysteresis on the high voltage supplies.

13

V

supply range is guaranteed by internal regulator.

DD_HV_FLA

3.14.5 Power up/down sequencing

Table 38 shows the constraints and relationships for the different power supplies

Table 38. Device supply relation during power-up/power-down sequence

Supply 2¹

V_{DD_LV}V_{DD_HV_PMC}V_{DD_HV_IO}V_{DD_HV_FLA}V_{DD_HV_ADV}V_{DD_HV_ADR}ALTREFn²V_DDSTBY

V_{DD_LV}

V_{DD_HV_PMU}

V_{DD_HV_IO}

V_{DD_HV_FLA}

V_{DD_HV_ADV}

V_{DD_HV_ADR}

ALTREFn

2 mA³

5 mA

10 mA⁴

V_DDSTBY

1

2

Red cells: supply1 (row) can exceed supply2 (column), granted that external circuitry ensure current flowing from supply1

is less than absolute maximum rating current value provided.

ALTREFn are the alternate references for the ADC that can be used in place of the default reference (V_{DD_HV_ADR_*}). They

are SARB.ALTREF and SAR2.ALTREF.

3

4

V_{DD_HV_FLA}is generated internally in normal mode. Above current constraints is guaranteed.

ADC performances is not guaranteed with ALTREFn above V_{DD_HV_IO}/ V_{DD_HV_ADV}

During power-up, all functional terminals are maintained into a known state as described within the following table.

MPC5777M Microcontroller Data Sheet, Rev. 6

78

NXP Semiconductors

Electrical characteristics

Table 39. Functional terminals state during power-up and reset

TERMINAL

TYPE¹

POWERUP²

pad state

RESET

pad state

DEFAULT

pad state³

Comments

Power-on reset pad

PORST

ESR0⁵

Strong

Weak pull-down

Strong pull-down

Weak pull-down

Weak pull-up

pull-down⁴

Strong

Functional reset pad.

pull-down

ESR1

High impedance

Weak pull-down

Weak pull-up

—

TESTMODE

Weak pull-down⁶

GPIO

Weak pull-up⁴

High impedance

Weak pull-up

High impedance

Weak pull-up

High impedance

—

ANALOG

ERROR0

During functional reset, pad state

can be overridden by FCCU

JCOMP

High impedance

Weak pull-down

—

TCK

TMS

TDI

High impedance

Weak pull-down

Weak pull-up

Weak pull-down

Weak pull-up

—

Weak pull-up

TDO

High impedance

1

2

Refer to pinout information for terminal type

POWERUP state is guaranteed from V_{DD_HV_IO}>1.1 V and maintained until supply cross the power-on reset

threshold: V_{PORUP_LV}for LV supply, V_{PORUP_HV}for high voltage supply.

3

4

Before software configuration

Pull-down and pull-up strength are provided as part of Table 13 in Section 3.6.1, I/O input DC characteristics.

Pull-up/Pull-down are activated within 2 µs after internal reset has been asserted. Actual pad transition will depend

on external capacitance.

5

6

Unlike ESR0, ESR1 is provided as normal GPIO and implements weak pull-up during power-up.

An internal pull-down is implemented on the TESTMODE pin to prevent the device from entering test mode if the

package TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin to V_{SS_HV_IO}on the

board for maximum robustness, but not required. The value of TESTMODE is latched at the negation of reset and

has no affect afterward. The device will not exit functional reset with the TESTMODE pin asserted during power-up.

The TESTMODE pin can be connected externally directly to ground without any other components.

3.15 Flash memory electrical characteristics

The following sections contain flash memory electrical specifications.

3.15.1 Flash memory program and erase specifications

NOTE

All timing, voltage, and current numbers specified in this section are defined for a single

embedded flash memory within an SoC, and represent average currents for given supplies

and operations.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

79

Electrical characteristics

Table 40 shows the estimated Program/Erase times.

Table 40. Flash memory program and erase specifications (pending characterization)

Factory

Field Update

Programming^3,4

Typical

Initial Max

Full Temp

Symbol

Characteristic¹

Typ²Initial Max

End of

Lifetime Max⁶

Units

Life⁵

20°C T_a -40°C T_J-40°C T_J 1,000 250,000

30°C

 150°C

150 °C

cycles

t_dwpgmDoubleword (64 bits) program time

t_ppgmPage (256 bits) program time

43

73

100

200

800

290

45

150

300

1,200

320

50

55

108

396

250

40

500

µs

t_qppgnQuad-page (1024 bits) program time 268

2,000

1,000

1,200

1.200

1,600

µs

t_16kers16 KB Block erase time

t_16kpgn16 KB Block program time

t_32kers32 KB Block erase time

t_32kpgm32 KB Block program time

t_64kers64 KB Block erase time

t_64kpgm64 KB Block program time

t_256kers256 KB Block erase time

t_256kpgm256 KB Block program time

168

34

ms

217

69

360

100

490

180

1,520

720

390

110

310

90

315

138

884

552

590

210

2,030

880

420

170

1,080

650

4,000

—

1

Program times are actual hardware programming times and do not include software overhead. Block program times assume

quad-page programming.

2

Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

3

4

5

Conditions:  150 cycles, nominal voltage.

Plant Programming times provide guidance for timeout limits used in the factory.

Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical

End of Life program and erase values may be used for throughput calculations.

6

Conditions: -40°C T_J 150°C; full spec voltage.

MPC5777M Microcontroller Data Sheet, Rev. 6

80

NXP Semiconductors

Electrical characteristics

3.15.2 Flash memory FERS program and erase specifications

Table 41. Flash memory FERS program and erase specifications (pending characterization)

Factory Programming with FERS=1 and Vfers

pin is

5V ± 5%²

Symbol

Characteristic¹

Units

Initial Max

Full Temp

Initial Max

Typ³

20°CT_A30°C⁴-40°CT_J150°C⁴

t_dwpgm

t_ppgm

Doubleword (64 bits) program time

Page (256 bits) program time

Quad-page (1024 bits) program time

16 KB erase time

30

43

90

145

530

782

24

135

218

795

782

35

µs

t_qppgn

134

160

18

µs

t_16kers

t_16kpgn

t_32kers

t_32kpgm

t_64kers

t_64kpgm

t_256kers

t_256kpgm

ms

16 KB program time

32 KB erase time

190

36

782

47

782

68

32 KB program time

64 KB erase time

250

72

782

94

782

135

2,070

568

64 KB program time

256 KB erase time

600

288

1,380

374

256 KB program time

1

Program times are actual hardware programming times and do not include software overhead. Block program times assume

quad-page programming.

2

3

Conditions: 150 cycles, nominal voltage.

Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

4

Plant Programming times provide guidance for timeout limits used in the factory.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

81

Electrical characteristics

3.15.3 Flash memory Array Integrity and Margin Read specifications

Table 42. Flash memory Array Integrity and Margin Read specifications (characterized but not tested)

Symbol

Characteristic

Min

Typical

Max¹

Units²

t_ai16kseqArray Integrity time for sequential sequence on 16KB block.

t_ai32kseqArray Integrity time for sequential sequence on 32KB block.

t_ai64kseqArray Integrity time for sequential sequence on 64KB block.

t_ai256kseqArray Integrity time for sequential sequence on 256KB block.

t_aifullseqArray Integrity time for sequential sequence full array.

—

512 ×

Tperiod ×

Nread

—

1024 ×

Tperiod ×

Nread

—

2048 ×

Tperiod ×

Nread

8192 ×

Tperiod ×

Nread

3.77e5 ×

Tperiod ×

Nread

t_aifullpropArray Integrity time for proprietary sequence (applies to full

array or single block).

9.96e6 ×

Tperiod ×

Nread

t_mr16kseqMargin Read time for sequential sequence on 16KB block.

t_mr32kseqMargin Read time for sequential sequence on 32KB block.

t_mr64kseqMargin Read time for sequential sequence on 64KB block.

73.81

128.43

237.65

—

110.7

192.6

356.5

1,339.5

60.26

µs

ms

t_mr256kseqMargin Read time for sequential sequence on 256KB block. 893.01

t_mrfullMargin Read time for sequential sequence full array. 45.21

1

2

Array Integrity times need to be calculated and are dependent on system frequency and number of clocks per read.

The equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal

5e-9) and Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup

that requires 6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read,

and has the address pipeline set to 2, Nread would equal 4 (or 6 - 2).)

The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

MPC5777M Microcontroller Data Sheet, Rev. 6

82

NXP Semiconductors

Electrical characteristics

3.15.4 Flash memory module life specifications

Table 43. Flash memory module life spec (pending characterization)

Symbol

Characteristic

Conditions

Min

Typical

Units

Array P/E Number of program/erase cycles per

—

250,000

—

P/E

cycles

block for 16 KB, 32 KB and 64 KB

blocks.¹

cycles

Number of program/erase cycles per

block for 256 KB blocks.²

—

1,000

50

250,000

P/E

cycles

Data

retention

Minimum data retention.

Blocks with 0 – 1,000 P/E

cycles.

—

Years

Blocks with 100,000 P/E

cycles.

20

Blocks with 250,000 P/E

cycles.

10

1

2

Program and erase supported across standard temperature specs.

3.15.5 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window

represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the

qualification limits.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

83

Electrical characteristics

3.15.6 Flash memory AC timing specifications

Table 44. Flash memory AC timing specifications (characterized but not tested)

Symbol

Characteristic

Min

Typical

Max

Units

t_psus

Time from setting the MCR-PSUS bit until MCR-DONE bit

is set to a 1.

—

7 plus four 9.1 plus

µs

system

clock

four

system

clock

periods

t_esus

Time from setting the MCR-ESUS bit until MCR-DONE bit

is set to a 1.

—

16 plus

four

20.8 plus

four

µs

system

clock

system

clock

periods

t_res

Time from clearing the MCR-ESUS or PSUS bit with

EHV = 1 until DONE goes low.

—

100

ns

µs

t_done

t_dones

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared.

—

5

Time from 1 to 0 transition on the MCR-EHV bit aborting a

program/erase until the MCR-DONE bit is set to a 1.

16 plus

four

20.8 plus

four

system

clock

system

clock

periods

t_drcv

Time to recover once exiting low power mode.

16 plus

seven

system

clock

—

45 plus

seven

system

clock

µs

periods

t_aistart

Time from 0 to 1 transition of UT0-AIE initiating a Margin

Read or Array Integrity until the UT0-AID bit is cleared.

This time also applies to the resuming from a suspend or

breakpoint by clearing AISUS or clearing NAIBP

—

5

ns

t_aistop

Time from 1 to 0 transition of UTO-AIE initiating an Array

Integrity abort until the UT0-AID bit is set. This time also

applies to the UT0-AISUS to UT0-AID setting in the event

of a Array Integrity suspend request.

—

80

plus fifteen

system

clock

periods

t_mrstopTime from 1 to 0 transition of UTO-AIE initiating a Margin

Read abort until the UT0-AID bit is set. This time also

10.36

plus four

—

20.42

plus four

system

clock

µs

applies to the UT0-AISUS to UT0-AID setting in the event system

of a Margin Read suspend request.

clock

periods

3.15.7 Flash read wait state and address pipeline control settings

Table 45 describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic

flash access times of the C55FMC array at 150 °C.

MPC5777M Microcontroller Data Sheet, Rev. 6

84

NXP Semiconductors

Electrical characteristics

Table 45. Flash Read Wait State and Address Pipeline Control Combinations

Flash Frequency

RWSC setting

APC setting

0 MHz < fFLASH  33 MHz

33 MHz < fFLASH  100 MHz

100 MHz < fFLASH  133 MHz

133 MHz < fFLASH  167 MHz

167 MHz < fFLASH  200 MHz

0

2

3

4

5

0

1

2

3.16 AC specifications

All AC timing specifications are valid up to 150 °C, except where explicitly noted.

3.16.1 Debug and calibration interface timing

3.16.1.1 JTAG interface timing

1,2

Table 46. JTAG pin AC electrical characteristics

Value

#

Symbol

Characteristic

Unit

Min

Max

1

2

t_JCYC

t_JDC

CC TCK cycle time

100

40

—

5

—

60

ns

%

CC TCK clock pulse width

3

t_TCKRISE

CC TCK rise and fall times (40%–70%)

CC TMS, TDI data setup time

3

ns

4

t_{TMSS, TDIS}

t

—

5

t

_TMSH,t_TDIHCC TMS, TDI data hold time

5

—

6

t_TDOV

t_TDOI

CC TCK low to TDO data valid

—

0

16³

7

CC TCK low to TDO data invalid

—

8

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

CC TCK low to TDO high impedance

CC JCOMP assertion time

—

100

40

—

15

9

—

10

11

12

13

14

15

CC JCOMP setup time to TCK low

—

CC TCK falling edge to output valid

600⁴

600

—

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

CC TCK falling edge to output valid out of high impedance

CC TCK falling edge to output high impedance

CC Boundary scan input valid to TCK rising edge

CC TCK rising edge to boundary scan input invalid

—

1

2

These specifications apply to JTAG boundary scan only. See Table 47 for functional specifications.

JTAG timing specified at V_{DD_HV_IO_JTAG}= 4.0 V to 5.5 V, and maximum loading per pad type as specified in the

I/O section of the data sheet.

3

Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

85

Electrical characteristics

4

Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG

delay.

TCK

2

3

2

1

Figure 22. JTAG test clock input timing

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 23. JTAG test access port timing

MPC5777M Microcontroller Data Sheet, Rev. 6

86

NXP Semiconductors

Electrical characteristics

TCK

10

JCOMP

9

Figure 24. JTAG JCOMP timing

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

87

Electrical characteristics

TCK

11

13

Output

Signals

12

Output

Signals

14

15

Input

Signals

Figure 25. JTAG boundary scan timing

3.16.1.2 Nexus interface timing

1

Table 47. Nexus debug port timing

Value

Min Max

#

Symbol

Characteristic

Unit

2

7

8

9

t_EVTIPWCC EVTI pulse width

t_EVTOPWCC EVTO pulse width

t_TCYCCC TCK cycle time

4

40

—

t_CYC

ns

2

2^3,4

t_CYC

ns

t_TCYCCC Absolute minimum TCK cycle time⁵(TDO/TDOC sampled on posedge of 40⁶

TCK)

Absolute minimum TCK cycle time⁷(TDO/TDOC sampled on negedge of 20⁶

TCK)

—

11⁸

t_NTDISCC TDI/TDIC data setup time

5

ns

MPC5777M Microcontroller Data Sheet, Rev. 6

88

NXP Semiconductors

Electrical characteristics

1

Table 47. Nexus debug port timing (continued)

Value

Unit

#

Symbol

Characteristic

Min Max

12

t_NTDIHCC TDI/TDIC data hold time

5

—

16

—

ns

13⁹t_NTMSSCC TMS/TMSC data setup time

14

15¹⁰

16

t_NTMSHCC TMS/TMSC data hold time

5

—

CC TDO/TDOC propagation delay from falling edge of TCK¹¹

—

2.25

CC TDO/TDOC hold time with respect to TCK falling edge (minimum

TDO/TDOC propagation delay)

1

Nexus timing specified at V_{DD_HV_IO_JTAG}= 4.0 V to 5.5 V, and maximum loading per pad type as specified in the

I/O section of the data sheet.

2

3

t_CYCis system clock period.

Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is

less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral

frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided

by a number greater than or equal to that specified here.

4

This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the

Absolute minimum TCK period specification.

5

6

This value is TDO/TDOC propagation time 36ns + 4 ns setup time to sampling edge.

This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability

of the design (system frequency / 4) depending on the actual system frequency being used.

7

8

9

This value is TDO/TDOC propagation time 16ns + 4 ns setup time to sampling edge.

TDIC represents the TDI bit frame of the scan packet in compact JTAG 2-wire mode.

TMSC represents the TMS bit frame of the scan packet in compact JTAG 2-wire mode.

¹⁰TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.

¹¹Timing includes TCK pad delay, clock tree delay, logic delay and TDO/TDOC output pad delay.

TCK

EVTI

EVTO

9

Figure 26. Nexus event trigger and test clock timings

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

89

Electrical characteristics

TCK

11

13

12

14

TMS/TMSC,

TDI/TDIC

15

16

TDO/TDOC

Figure 27. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing

3.16.1.3 Aurora LVDS interface timing

Table 48. Aurora LVDS interface timing specifications

Value

Typ

Symbol

Parameter

Unit

Min

Max

Data Rate

STARTUP

—

SR Data rate

—

1250

Mbps

t_{STRT_BIAS}CC Bias startup time¹

t_{STRT_TX}

CC Transmitter startup time²

t_{STRT_RX}

CC Receiver startup time³

—

5

4

µs

1

2

Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down

(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.

Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been

deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality

is guaranteed only after the startup time.

MPC5777M Microcontroller Data Sheet, Rev. 6

90

NXP Semiconductors

Electrical characteristics

3

Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been

deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality

is guaranteed only after the startup time.

3.16.1.4 Aurora debug port timing

Table 49. Aurora debug port timing

Value

#

Symbol

Characteristic

Unit

Min

Max

1

1a

2

t_REFCLK

CC Reference clock frequency

625

—

1250

400

55

MHz

ps

t_MCYC

t_RCDC

J_RC

CC Reference clock rise/fall time

CC Reference clock duty cycle

CC Reference clock jitter

45

%

3

—

40

ps

4

t_STABILITY

BER

J_D

CC Reference clock stability

CC Bit error rate

50

—

PPM

—

5

—

10^–12

0.17

0.35

20

6

SR Transmit lane deterministic jitter

SR Transmit lane total jitter

CC Differential output skew

CC Lane to lane output skew

CC Aurora lane unit interval¹

—

OUI

ps

7

J_T

—

8

S_O

—

9

S_MO

OUI

—

1000

1600

800

ps

10

625 Mbps

1.25 Gbps

1600

800

ps

1

± 100 PPM

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

91

Electrical characteristics

1

2

CLOCK_REF

Zero Crossover

CLOCK_REF

-

+

1a

8

Tx Data

-

Ideal Zero Crossover

Tx Data

+

Tx Data [n]

Zero Crossover

Tx Data [n+1]

Zero Crossover

Tx Data [m]

Zero Crossover

9

Figure 28. Aurora timings

MPC5777M Microcontroller Data Sheet, Rev. 6

92

NXP Semiconductors

Electrical characteristics

3.16.2 DSPI timing with CMOS and LVDS¹pads

DSPI channel frequency support is shown in Table 50. Timing specifications are shown in Table 51, Table 52, Table 54,

Table 55 and Table 56.

Table 50. DSPI channel frequency support

Max usable

DSPI use mode

frequency (MHz)^1,2

CMOS (Master mode)

LVDS (Master mode)³

Full duplex – Classic timing (Table 51)

17

30

33

40

Full duplex – Modified timing (Table 52)

Output only mode (SCK/SOUT/PCS) (Table 51 and Table 52)

Output only mode TSB mode (SCK/SOUT/PCS) (Table 56)

Full duplex – Modified timing (Table 54)

Output only mode TSB mode (SCK/SOUT/PCS) (Table 55)

1

Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

Maximum usable frequency does not take into account external device propagation delay.

µS Channel and LVDS timing is not supported for DSPI12.

2

3

3.16.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads

3.16.2.1.1 DSPI CMOS Master Mode – Classic Timing

1

Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1

Condition

Pad drive³

SCK drive strength

Value²

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

1

t_SCKCC SCK cycle time

Very strong

Strong

25 pF

50 pF

33.0

80.0

—

ns

Medium

200.0

2

t_CSCCC PCS to SCK delay SCK and PCS drive strength

Very strong

Strong

25 pF

(N⁴× t_SYS⁵) – 16

(N⁴× t_SYS⁵) – 29

—

ns

50 pF

Medium

50 pF

PCS medium

PCS = 50 pF

and SCK strong SCK = 50 pF

1. DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

93

Electrical characteristics

1

Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1

Condition

Pad drive³

SCK and PCS drive strength

Value²

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

3

t_ASCCC After SCK delay

Very strong

PCS = 0 pF

SCK = 50 pF

(M⁶× t_SYS⁵) – 35

—

ns

Strong

PCS = 0 pF

SCK = 50 pF

Medium

PCS = 0 pF

SCK = 50 pF

PCS medium

PCS = 0 pF

and SCK strong SCK = 50 pF

4

t_SDCCC SCK duty cycle⁷

SCK drive strength

Very strong

Strong

0 pF

¹/₂t_SCK– 2

¹/₂t_SCK– 5

¹/₂t_SCK+ 2

¹/₂t_SCK+ 5

ns

Medium

PCS strobe timing

5

6

t_PCSCCC PCSx to PCSS

time⁸

PCS and PCSS drive strength

Strong

25 pF

16.0

—

ns

t_PASCCC PCSS to PCSx

time⁸

PCS and PCSS drive strength

Strong

25 pF

SIN setup time

7

8

9

t_SUI

CC SIN setup time to SCK drive strength

SCK⁹

Very strong

Strong

25 pF

25.0

32.75

52.0

—

ns

50 pF

Medium

SIN hold time

t_HI

CC SIN hold time from SCK drive strength

SCK⁹

Very strong

Strong

0 pF

–1.0

—

0 pF

Medium

SOUT data valid time (after SCK edge)

SOUT and SCK drive strength

t_SUOCC SOUT data valid

time from SCK¹⁰

Very strong

Strong

25 pF

50 pF

—

7.0

8.0

Medium

16.0

SOUT data hold time (after SCK edge)

MPC5777M Microcontroller Data Sheet, Rev. 6

94

NXP Semiconductors

Electrical characteristics

1

Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1

Condition

Pad drive³

SOUT and SCK drive strength

Value²

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

10

t_HO

CC SOUT data hold

time after SCK¹⁰

Very strong

Strong

25 pF

50 pF

–7.7

–11.0

–15.0

—

ns

Medium

1

2

3

All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

All timing values for output signals in this table are measured to 50% of the output voltage.

Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds

and may cause incorrect operation.

4

N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software

programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless

TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS

and SCK are driven by the same edge of DSPI_CLKn).

5

6

t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

t_SYS= 10 ns).

M is the number of clock cycles added to time between SCK negation and PCS negation and is software

programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB

mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and

SCK are driven by the same edge of DSPI_CLKn).

7

t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd

divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

8

9

PCSx and PCSS using same pad configuration.

Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

¹⁰SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the

same value.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

95

Electrical characteristics

t_CSC

t_ASC

PCSx

t_SCK

t_SDC

SCK Output

(CPOL = 0)

t_SDC

SCK Output

(CPOL = 1)

t_SUI

t_HI

First Data

SIN

Data

Last Data

t_SUO

t_HO

Data

Last Data

SOUT

Figure 29. DSPI CMOS master mode – classic timing, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

t_SUI

t_HI

Data

First Data

Last Data

SIN

t_SUO

t_HO

Data

SOUT

First Data

Last Data

Figure 30. DSPI CMOS master mode – classic timing, CPHA = 1

MPC5777M Microcontroller Data Sheet, Rev. 6

96

NXP Semiconductors

Electrical characteristics

t_PCSC

t_PASC

PCSS

PCSx

Figure 31. DSPI PCS strobe (PCSS) timing (master mode)

3.16.2.1.2

DSPI CMOS Master Mode – Modified Timing

1

Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 1

Condition

Pad drive³

SCK drive strength

Value²

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

1

t_SCKCC SCK cycle time

Very strong

Strong

25 pF

33.0

80.0

—

ns

50 pF

Medium

200.0

2

t_CSCCC PCS to SCK delay SCK and PCS drive strength

Very strong

Strong

25 pF

50 pF

(N⁴× t_SYS⁵) – 16

(N⁴× t_SYS⁵) – 29

—

ns

Medium

PCS medium PCS = 50 pF

and SCK

strong

SCK = 50 pF

3

t_ASCCC After SCK delay

SCK and PCS drive strength

Very strong

PCS = 0 pF

SCK = 50 pF

(M⁶× t_SYS⁵) – 35

—

ns

Strong

PCS = 0 pF

SCK = 50 pF

Medium

PCS = 0 pF

SCK = 50 pF

PCS medium PCS = 0 pF

and SCK

strong

SCK = 50 pF

4

t_SDCCC SCK duty cycle⁷

SCK drive strength

Very strong

Strong

0 pF

¹/₂t_SCK– 2

¹/₂t_SCK– 5

¹/₂t_SCK+ 2

¹/₂t_SCK+ 5

ns

0 pF

Medium

PCS strobe timing

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

97

Electrical characteristics

Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 1

1

Condition

Pad drive³

PCS and PCSS drive strength

Strong 25 pF

PCS and PCSS drive strength

Value²

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

5

t_PCSCCC PCSx to PCSS

time⁸

16.0

—

ns

6

7

t_PASCCC PCSS to PCSx

time⁸

Strong

25 pF

SIN setup time

t_SUI

CC SIN setup time to

SCK

SCK drive strength

5

Very strong

Strong

25 pF

25 – (P¹⁰× t_SYS

)

—

ns

CPHA = 0⁹

50 pF

32.75 – (P¹⁰× t_SY

5

)

S

5

Medium

50 pF

52 – (P¹⁰× t_SYS

)

—

SIN setup time to

SCK

SCK drive strength

Very strong

Strong

25 pF

25.0

32.75

52.0

—

CPHA = 1⁹

50 pF

Medium

SIN hold time

8

t_HI

CC SIN hold time from SCK drive strength

SCK

Very strong

Strong

0 pF

–1 + (P⁹× t_SYS

)

—

ns

4

CPHA = 0⁹

4

0 pF

)

Medium

SIN hold time from SCK drive strength

SCK

Very strong

Strong

0 pF

–1.0

—

CPHA = 1⁹

0 pF

Medium

SOUT data valid time (after SCK edge)

SOUT and SCK drive strength

9

t_SUOCC SOUT data valid

time from SCK

5

Very strong

Strong

25 pF

50 pF

—

7.0 + t_SYS

8.0 + t_SYS

ns

CPHA = 0¹⁰

5

Medium

16.0 + t_SYS

SOUT data valid

time from SCK

CPHA = 1¹⁰

SOUT and SCK drive strength

Very strong

Strong

25 pF

50 pF

—

7.0

8.0

Medium

16.0

SOUT data hold time (after SCK edge)

MPC5777M Microcontroller Data Sheet, Rev. 6

98

NXP Semiconductors

Electrical characteristics

1

Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 1

Condition

Pad drive³

SOUT and SCK drive strength

Value²

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

10

t_HO

CC SOUT data hold

time after SCK

CPHA = 0¹¹

5

Very strong

Strong

25 pF

50 pF

–7.7 + t_SYS

—

ns

5

–11.0 + t_SYS

–15.0 + t_SYS

5

Medium

SOUT data hold

time after SCK

CPHA = 1¹¹

SOUT and SCK drive strength

Very strong

Strong

25 pF

50 pF

–7.7

–11.0

–15.0

—

ns

Medium

1

2

3

All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

All timing values for output signals in this table are measured to 50% of the output voltage.

Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds

and may cause incorrect operation.

4

N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software

programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless

TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS

and SCK are driven by the same edge of DSPI_CLKn).

5

6

t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

t_SYS= 10 ns).

M is the number of clock cycles added to time between SCK negation and PCS negation and is software

programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB

mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and

SCK are driven by the same edge of DSPI_CLKn).

7

t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd

divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

8

9

PCSx and PCSS using same pad configuration.

Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

¹⁰P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is

automatically set to 1.

¹¹SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the

same value.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

99

Electrical characteristics

t_CSC

t_ASC

PCSx

t_SCK

t_SDC

SCK Output

(CPOL = 0)

t_SDC

SCK Output

(CPOL = 1)

t_SUI

t_HI

First Data

SIN

Data

Last Data

t_SUO

t_HO

Data

Last Data

SOUT

Figure 32. DSPI CMOS master mode – modified timing, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

t_HI

t_SUI

t_HI

Data

First Data

SIN

Last Data

t_SUO

t_HO

Data

SOUT

First Data

Last Data

Figure 33. DSPI CMOS master mode – modified timing, CPHA = 1

MPC5777M Microcontroller Data Sheet, Rev. 6

100

NXP Semiconductors

Electrical characteristics

t_PCSC

t_PASC

PCSS

PCSx

Figure 34. DSPI PCS strobe (PCSS) timing (master mode)

3.16.2.1.3

DSPI LVDS Master Mode – Modified Timing

Table 53. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1

Condition

Value¹

#

Symbol

Characteristic

Unit

Pad drive

LVDS

Load

Min

Max

1

t_SCKCC SCK cycle time

15 pF

30.0

—

ns

to 25 pF

differential

2

t_CSCCC PCS to SCK delay PCS drive strength

(LVDS SCK)

Very strong

Strong

25 pF

(N²× t_SYS³) – 10

(N²× t_SYS³) – 32

(M⁴× t_SYS³) – 8

—

ns

50 pF

Medium

3

t_ASCCC After SCK delay Very strong

(LVDS SCK)

PCS = 0 pF

SCK = 25 pF

Strong

PCS = 0 pF

SCK = 25 pF

(M⁴× t_SYS³) – 8

¹/₂t_SCK– 2

—

ns

Medium

PCS = 0 pF

SCK = 25 pF

4

7

t_SDCCC SCK duty cycle⁵LVDS

15 pF

¹/₂t_SCK+2

to 25 pF

differential

t_SUI

CC

SIN setup time

SIN setup time to SCK drive strength

SCK

3

LVDS

15 pF

to 25 pF

differential

23 – (P⁷× t_SYS

)

—

ns

CPHA = 0⁶

SIN setup time to SCK drive strength

SCK

LVDS

15 pF

to 25 pF

23

CPHA = 1⁶

differential

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

101

Electrical characteristics

Table 53. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1

Condition

Pad drive

Value¹

#

Symbol

Characteristic

Unit

Load

Min

Max

8

t_HI

CC

SIN Hold Time

SIN hold time

from SCK

SCK drive strength

LVDS

0 pF differential –1 + (P⁷× t_SYS

3

)

—

ns

CPHA = 0⁶

SIN hold time

from SCK

SCK drive strength

LVDS 0 pF differential

–1

CPHA = 1⁶

9

t_SUOCC

SOUT data valid time (after SCK edge)

SOUT data valid SOUT and SCK drive strength

time from SCK

3

LVDS

15 pF

—

7.0 + t_SYS

ns

CPHA = 0⁸

to 25 pF

differential

SOUT data valid SOUT and SCK drive strength

time from SCK

LVDS

15 pF

to 25 pF

differential

7.0

CPHA = 1⁸

10

t_HO

CC

SOUT data hold time (after SCK edge)

SOUT data hold SOUT and SCK drive strength

time after SCK

3

LVDS

15 pF

–7.5 + t_SYS

—

ns

CPHA = 0⁸

to 25 pF

differential

SOUT data hold SOUT and SCK drive strength

time after SCK

LVDS

15 pF

to 25 pF

differential

–7.5

CPHA = 1⁸

1

2

All timing values for output signals in this table are measured to 50% of the output voltage.

N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software

programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB

mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and

SCK are driven by the same edge of DSPI_CLKn).

3

4

t_SYSis the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

t_SYS= 10 ns).

M is the number of clock cycles added to time between SCK negation and PCS negation and is software

programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB

mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and

SCK are driven by the same edge of DSPI_CLKn).

5

t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd

divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

6

7

Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = ±100 mV.

P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically

set to 1.

MPC5777M Microcontroller Data Sheet, Rev. 6

102

NXP Semiconductors

Electrical characteristics

8

SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the

same value.

1

Table 54. DSPI LVDS slave timing – full duplex – modified transfer format (MTFE = 0/1)

Condition

Pad drive

Value

#

Symbol

Characteristic

Unit

Load

Min

Max

1

2

3

4

5

t_SCKCC SCK cycle time²

t_CSCSR SS to SCK delay²

—

62

16

30

—

ns

—

50

60

5

t_ASC

t_SDCCC SCK duty cycle²

SR SCK to SS delay²

—

t_A

CC Slave Access

Time^{2, 3, 4}(SS

active to SOUT

driven)

Very strong

Strong

Medium

Very strong

Strong

Medium

25 pF

50 pF

25 pF

50 pF

—

6

t_DIS

CC Slave SOUT

Disable Time ^{2, 3,}

⁴(SS inactive to

SOUT High-Z or

invalid)

5

10

7

8

9

t_SUI

t_HI

CC Data setup time

for inputs²

—

10

—

ns

CC Data hold time for —

inputs²

t_SUOCC

SOUT Valid

Time^{2, 3, 4}(after

SCK edge)

Very strong

Strong

25 pF

50 pF

25 pF

50 pF

—

30

50

—

ns

—

Medium

Very strong

Strong

—

10

t_HO

CC

SOUT Hold

Time^{2, 3, 4}(after

SCK edge)

2.5

Medium

1

DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that

case only.

2

3

4

Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.

All timing values for output signals in this table, are measured to 50% of the output voltage.

All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

103

Electrical characteristics

t_CSC

t_ASC

PCSx

t_SCK

t_SDC

SCK Output

(CPOL = 0)

t_SDC

SCK Output

(CPOL = 1)

t_SUI

t_HI

First Data

SIN

Data

Last Data

t_SUO

t_HO

Data

Last Data

SOUT

Figure 35. DSPI LVDS master mode – modified timing, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

t_HI

t_SUI

t_HI

Data

First Data

SIN

Last Data

t_SUO

t_HO

Data

SOUT

First Data

Last Data

Figure 36. DSPI LVDS master mode – modified timing, CPHA = 1

MPC5777M Microcontroller Data Sheet, Rev. 6

104

NXP Semiconductors

Electrical characteristics

3.16.2.1.4

DSPI Master Mode – Output Only

Table 55. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or

1,2

1, continuous SCK clock

Condition

Value

#

Symbol

Characteristic

Unit

Pad drive

LVDS

Load

Min

Max

1

t_SCKCC SCK cycle time

15 pF

25.0

—

ns

to 50 pF

differential

2

3

4

t_CSVCC PCS valid after SCK³Very strong

25 pF

—

6.0

ns

(SCK with 50 pF

differential load cap.)

Strong

50 pF

10.5

t_CSHCC PCS hold after SCK³Very strong

0 pF

–4.0

—

ns

(SCK with 50 pF

differential load cap.)

Strong

t_SDCCC SCK duty cycle

(SCK with 50 pF

LVDS

15 pF

to 50 pF

differential

¹/₂t_SCK– 2

¹/₂t_SCK+ 2

ns

differential load cap.)

SOUT data valid time (after SCK edge)

5

6

t_SUOCC SOUT data valid time SOUT and SCK drive strength

from SCK⁴

LVDS

15 pF

to 50 pF

differential

—

3.5

SOUT data hold time (after SCK edge)

t_HO

CC SOUT data hold time SOUT and SCK drive strength

after SCK⁴

LVDS

15 pF

–3.5

—

to 50 pF

differential

1

All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS

with pad driver strength as defined. Timing may degrade for weaker output drivers.

2

3

TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of

DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.

4

SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the

same value.

Table 56. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or

1,2

1, continuous SCK clock

Condition

Pad drive⁴

SCK drive strength

Value³

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

1

t_SCKCC SCK cycle time

Very strong

Strong

25 pF

50 pF

33.0

80.0

—

ns

Medium

200.0

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

105

Electrical characteristics

Table 56. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or

1,2

1, continuous SCK clock (continued)

Condition

Pad drive⁴

SCK and PCS drive strength

Value³

#

Symbol

Characteristic

Unit

Load (C_L)

Min

Max

2

t_CSVCC PCS valid after SCK⁵

Very strong

Strong

25 pF

7

8

—

ns

50 pF

Medium

50 pF

16

29

PCS medium

PCS = 50 pF

and SCK strong SCK = 50 pF

3

t_CSHCC PCS hold after SCK⁵

SCK and PCS drive strength

Very strong

Strong

PCS = 0 pF

SCK = 50 pF

–14

–33

–35

—

ns

PCS = 0 pF

SCK = 50 pF

Medium

PCS = 0 pF

SCK = 50 pF

PCS medium

PCS = 0 pF

and SCK strong SCK = 50 pF

4

9

t_SDCCC SCK duty cycle⁶

SCK drive strength

Very strong

Strong

0 pF

¹/₂t_SCK– 2

¹/₂t_SCK– 5

¹/₂t_SCK+ 2 ns

¹/₂t_SCK+ 5 ns

Medium

SOUT data valid time (after SCK edge)

t_SUOCC SOUT data valid time from

SOUT and SCK drive strength

SCK

Very strong

Strong

25 pF

50 pF

—

7.0

8.0

ns

CPHA = 1⁷

Medium

16.0

SOUT data hold time (after SCK edge)

CC SOUT data hold time after SOUT and SCK drive strength

10

t_HO

SCK

Very strong

Strong

25 pF

50 pF

–7.7

–11.0

–15.0

—

ns

CPHA = 1⁷

Medium

1

2

3

4

TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

All timing values for output signals in this table are measured to 50% of the output voltage.

Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds

and may cause incorrect operation.

5

With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of

DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.

MPC5777M Microcontroller Data Sheet, Rev. 6

106

NXP Semiconductors

Electrical characteristics

6

7

t_SDCis only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd

divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the

same value.

PCSx

t_CSV

t_SCK

t_SDC

t_CSH

SCK Output

(CPOL = 0)

t_SUO

t_HO

First Data

Last Data

SOUT

Data

Figure 37. DSPI LVDS and CMOS master timing – output only – modified transfer format MTFE = 1, CHPA = 1

3.16.2.2 Slave Mode timing

1

Table 57. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)

Condition

#

Symbol

Characteristic

Min

Max

Unit

Pad Drive

Load

1

2

3

4

5

t_SCKCC

t_CSCSR

SCK Cycle Time²

SS to SCK Delay²

SCK to SS Delay²

SCK Duty Cycle²

-

62

16

30

—

50

ns

-

t_ASC

SR

-

t_SDCCC

t_A

CC

Slave Access Time^2,3,4

(SS active to SOUT driven)

Very

Strong

25 pF

Strong

50 pF

25 pF

—

50

60

5

ns

Medium

6

t_DIS

Slave SOUT Disable

Time^2,3,4

Very

Strong

(SS inactive to SOUT High-Z

or invalid)

Strong

Medium

—

50 pF

—

10

5

ns

10

—

9

t_SUI

t_HI

CC Data Setup Time for Inputs²

CC Data Hold Time for Inputs²

10

—

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

107

Electrical characteristics

Table 57. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)

Condition

1

#

Symbol

Characteristic

Min

Max

Unit

Pad Drive

Load

11

t_SUOCC

SOUT Valid Time^2,3,4

(after SCK edge)

Very

Strong

25 pF

—

30

ns

Strong

50 pF

25 pF

—

30

50

—

ns

Medium

12

t_HO

CC

SOUT Hold Time^2,3,4

(after SCK edge)

Very

2.5

Strong

50 pF

2.5

—

ns

Medium

1

DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for

that case only.

2

3

4

Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.

All timing values for output signals in this table, are measured to 50% of the output voltage.

All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

t_ASC

t_CSC

SS

t_SCK

SCK Input

t_SDC

(CPOL=0)

t_SDC

SCK Input

(CPOL=1)

t_HO

t_SUO

t_A

t_DIS

First Data

t_SUI

Data

Last Data

SOUT

SIN

t_HI

Last Data

First Data

Figure 38. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 0

MPC5777M Microcontroller Data Sheet, Rev. 6

108

NXP Semiconductors

Electrical characteristics

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

t_SUO

t_A

t_DIS

t_HO

Last Data

First Data

t_HI

Data

SOUT

SIN

t_SUI

First Data

Last Data

Figure 39. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 1

3.16.3 FEC timing

The FEC provides both MII and RMII interfaces in the 416 TEPBGA and 512 TEPBGA packages, and the MII and RMII

signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

3.16.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.

1

Table 58. MII receive signal timing

Value

Symbol

Characteristic

Unit

Min

Max

M1

M2

M3

M4

CC RXD[3:0], RX_DV, RX_ER to RX_CLK setup

CC RX_CLK to RXD[3:0], RX_DV, RX_ER hold

CC RX_CLK pulse width high

5

—

ns

5

ns

35%

65%

RX_CLK period

CC RX_CLK pulse width low

1

All timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

109

Electrical characteristics

M3

RX_CLK (input)

M4

RXD[3:0] (inputs)

RX_DV

RX_ER

M2

M1

Figure 40. MII receive signal timing diagram

3.16.3.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of

TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.

Refer to the MPC5777M Microcontroller Reference Manual’s Fast Ethernet Controller (FEC) chapter for details of this option

and how to enable it.

1

Table 59. MII transmit signal timing

Value²

Symbol

Characteristic

Unit

Min

Max

M5

M6

M7

M8

CC TX_CLK to TXD[3:0], TX_EN, TX_ER invalid

CC TX_CLK to TXD[3:0], TX_EN, TX_ER valid

CC TX_CLK pulse width high

5

—

25

ns

—

ns

35%

65%

TX_CLK period

CC TX_CLK pulse width low

1

2

All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.

Output parameters are valid for C_L= 25 pF, where C_Lis the external load to the device. The internal package

capacitance is accounted for, and does not need to be subtracted from the 25 pF value.

MPC5777M Microcontroller Data Sheet, Rev. 6

110

NXP Semiconductors

Electrical characteristics

M7

TX_CLK (input)

M5

M8

TXD[3:0] (outputs)

TX_EN

TX_ER

M6

Figure 41. MII transmit signal timing diagram

3.16.3.3 MII async inputs signal timing (CRS and COL)

Table 60. MII async inputs signal timing

Value

Symbol

Characteristic

Unit

Min

Max

M9

CC CRS, COL minimum pulse width

1.5

—

TX_CLK period

CRS, COL

M9

Figure 42. MII async inputs timing diagram

3.16.3.4 MII and RMII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

1

Table 61. MII serial management channel timing

Value²

Symbol

Characteristic

Unit

Min

Max

M10

M11

CC MDC falling edge to MDIO output invalid (minimum

propagation delay)

0

—

ns

CC MDC falling edge to MDIO output valid (max prop

delay)

—

25

M12

M13

M14

M15

CC MDIO (input) to MDC rising edge setup

CC MDIO (input) to MDC rising edge hold

CC MDC pulse width high

10

0

—

ns

40%

60%

MDC period

CC MDC pulse width low

1

All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and

2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

111

Electrical characteristics

2

Output parameters are valid for C_L= 25 pF, where C_Lis the external load to the device. The internal package

capacitance is accounted for, and does not need to be subtracted from the 25 pF value.

M14

M15

MDC (output)

M10

MDIO (output)

M11

MDIO (input)

M12

M13

Figure 43. MII serial management channel timing diagram

3.16.3.5 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency

requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of

the REF_CLK frequency.

1

Table 62. RMII receive signal timing

Value

Symbol

Characteristic

Unit

Min

Max

R1

R2

R3

R4

CC RXD[1:0], CRS_DV to REF_CLK setup

CC REF_CLK to RXD[1:0], CRS_DV hold

CC REF_CLK pulse width high

4

—

ns

2

ns

35%

65%

REF_CLK period

CC REF_CLK pulse width low

1

All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

MPC5777M Microcontroller Data Sheet, Rev. 6

112

NXP Semiconductors

Electrical characteristics

R3

REF_CLK (input)

R4

RXD[1:0] (inputs)

CRS_DV

R1

R2

Figure 44. RMII receive signal timing diagram

3.16.3.6 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%. There is no minimum frequency

requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of

the REF_CLK frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK,

and the timing is the same in either case. These options allows the use of non-compliant RMII PHYs.

1, 2

Table 63. RMII transmit signal timing

Value³

Symbol

Characteristic

Unit

Min

Max

R5

R6

R7

R8

CC REF_CLK to TXD[1:0], TX_EN invalid

CC REF_CLK to TXD[1:0], TX_EN valid

CC REF_CLK pulse width high

2

—

16

ns

—

ns

35%

65%

REF_CLK period

CC REF_CLK pulse width low

1

2

RMII timing is valid only up to a maximum of 150 ^oC junction temperature.

All timing specifications are referenced for TTL or CMOS input levels for REF_CLK to the valid output levels, 0.8 V

and 2.0 V.

3

Output parameters are valid for C_L= 25 pF, where C_Lis the external load to the device. The internal package

capacitance is accounted for, and does not need to be subtracted from the 25 pF value.

R7

REF_CLK (input)

R5

R8

TXD[1:0] (outputs)

TX_EN

R6

Figure 45. RMII transmit signal timing diagram

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

113

Electrical characteristics

3.16.4 FlexRay timing

This section provides the FlexRay Interface timing characteristics for the input and output signals.

These are recommended numbers as per the FlexRay EPL v3.0 specification.

3.16.4.1 TxEN

TxEN

80 %

20 %

dCCTxEN_FALL

dCCTxEN_RISE

Figure 46. TxEN signal

1

Table 64. TxEN output characteristics

Value

Symbol

Characteristic

Unit

Min

Max

dCCTxEN_RISE25CC Rise time of TxEN signal at CC

dCCTxEN_FALL25CC Fall time of TxEN signal at CC

—

9

ns

dCCTxEN₀₁

CC Sum of delay between Clk to Q of the last FF and the final output buffer,

rising edge

25

dCCTxEN₁₀

CC Sum of delay between Clk to Q of the last FF and the final output buffer,

falling edge

—

25

ns

1

TxEN pin load maximum 25 pF

MPC5777M Microcontroller Data Sheet, Rev. 6

114

NXP Semiconductors

Electrical characteristics

PE_Clk

TxEN

dCCTxEN₁₀

dCCTxEN₀₁

Figure 47. TxEN signal propagation delays

3.16.4.2 TxD

TxD

dCCTxD_50%

80 %

50 %

20 %

dCCTxD_RISE

dCCTxD_FALL

Figure 48. TxD signal

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

115

Electrical characteristics

1,2

Table 65. TxD output characteristics

Characteristic

Value

Min

Symbol

Unit

Max

dCCTxAsym

CC Asymmetry of sending CC at 25 pF load

–2.45

2.45

ns

(= dCCTxD_50% 100 ns)

dCCTxD_RISE25+dCCTxD_FALL25CC Sum of Rise and Fall time of TxD signal at the output

pin^3,4

—

9⁵

9⁶

25

dCCTxD₀₁

dCCTxD₁₀

CC Sum of delay between Clk to Q of the last FF and the

final output buffer, rising edge

ns

CC Sum of delay between Clk to Q of the last FF and the

final output buffer, falling edge

—

25

1

2

TxD pin load maximum 25 pF

Specifications valid according to FlexRay EPL 3.0.1 standard with 20%–80% levels and a 10pF load at the end of a

50 Ohm, 1 ns stripline. Please refer to the Very Strong I/O pad specifications.

3

4

Pad configured as VERY STRONG

Sum of transition time simulation is performed according to Electrical Physical Layer Specification 3.0.1 and the entire

temperature range of the device has been taken into account.

5

6

V_{DD_HV_IO}= 5.0 V ± 10%, Transmission line Z = 50 ohms, t_delay= 1 ns, C_L= 10 pF

V_{DD_HV_IO}= 3.3 V ± 10%, Transmission line Z = 50 ohms, t_delay= 0.6 ns, C_L= 10 pF

PE_Clk*

TxD

dCCTxD₁₀

dCCTxD₀₁

* FlexRay Protocol Engine Clock

Figure 49. TxD Signal propagation delays

MPC5777M Microcontroller Data Sheet, Rev. 6

116

NXP Semiconductors

Electrical characteristics

3.16.4.3 RxD

1

Table 66. RxD input characteristics

Characteristic

Value

Unit

Symbol

Min

Max

C_CCRxD

uCCLogic_1

uCCLogic_0

dCCRxD₀₁

CC Input capacitance on RxD pin

—

35

30

7

pF

%

CC Threshold for detecting logic high

CC Threshold for detecting logic low

70

65

%

CC Sum of delay from actual input to the D input of the first

FF, rising edge

—

10

44

43

ns

dCCRxD₁₀

CC Sum of delay from actual input to the D input of the first

FF, falling edge

dCCRxAsymAccept15 CC Acceptance of asymmetry at receiving CC with 15 pF

load

–31.5

–30.5

dCCRxAsymAccept25 CC Acceptance of asymmetry at receiving CC with 25 pF

load

1

FlexRay RxD timing is valid for Automotive input levels with hysteresis enabled (hysteresis permanently enabled in

Automotive input levels) and CMOS input levels with hysteresis disabled, 4.5 V  V_{DD_HV_IO} 5.5 V for both cases.

3.16.5 PSI5 timing

The following table describes the PSI5 timing.

Table 67. PSI5 timing

Value

Max

Symbol

Parameter

Unit

Min

t_{MSG_DLY}CC Delay from last bit of frame (CRC0) to assertion

of new message received interrupt

—

3

2

1

µs

t_{SYNC_DLY}CC Delay from internal sync pulse to sync pulse

trigger at the SDOUT_PSI5_n pin

—

t_{MSG_JIT}

CC Delay jitter from last bit of frame (CRC0) to

assertion of new message received interrupt

cycles¹

cycles

t_{SYNC_JIT}CC Delay jitter from internal sync pulse to sync pulse

trigger at the SDOUT_PSI5_n pin

±(1 PSI5_1µs_CLK +

1 PBRIDGEn_CLK)

1

Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.

3.16.6 UART timing

UART channel frequency support is shown in the following table.

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

117

Electrical characteristics

Table 68. UART frequency support

LINFlexD clock frequency

LIN_CLK (MHz)

Max usable frequency

(Mbaud)

Oversampling rate

Voting scheme

80

16

8

3:1 majority voting

5

10

6

Limited voting on one

sample with configurable

sampling point

13.33

16

5

4

20

100

16

8

3:1 majority voting

6.25

12.5

16.67

20

6

Limited voting on one

sample with configurable

sampling point

5

4

25

3.16.7 External Bus Interface (EBI) Timing

1

Table 69. Bus Operation Timing

66.7 MHz (Ext. Bus Freq)^{2 3}

Spec

Characteristic

Symbol

Unit

Min

Max

1

2

3

4

5

CLKOUT Period⁴

t_C

15.15

45%

—

ns

t_C

CLKOUT Duty Cycle

CLKOUT Rise Time

CLKOUT Fall Time

t_CDC

t_CRT

t_CFT

t_COH

55%

5

—

ns

5

—

CLKOUT Posedge to Output Signal Invalid or High Z

(Hold Time)⁶

1.0

—

ADDR[12:31]

ADDR[8:11]/WE[0:3]/BE[0:3]

BDIP

CS[0:3]

DATA[0:31]

OE

RD_WR

TS

6

CLKOUT Posedge to Output Signal Valid (Output

Delay)^7,8

t_COV

—

8.0

ns

ADDR[12:31]

ADDR[8:11]/WE[0:3]/BE[0:3]

BDIP

CS[0:3]

DATA[0:31]

OE

RD_WR

TS

MPC5777M Microcontroller Data Sheet, Rev. 6

118

NXP Semiconductors

Electrical characteristics

1

Table 69. Bus Operation Timing (continued)

66.7 MHz (Ext. Bus Freq)^{2 3}

Spec

Characteristic

Symbol

Unit

Min

Max

7

Input Signal Valid to CLKOUT Posedge (Setup Time)

t_CIS

7.0

—

ns

DATA[0:31]

8

CLKOUT Posedge to Input Signal Invalid (Hold Time)

t_CIH

1.0

—

ns

DATA[0:31]

1

EBI timing specified at V_{DD_HV_IO_EBI}and V_{DD_HV_IO_FLEXE}= 3.0 V to 3.6 V, T_A= T_Lto T_H, and C_L= 30 pF with

DSC = 0b10 for ADDR/CTRL and DSC = 0b11 for CLKOUT/DATA.

2

3

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including PLL jitter.

Depending on the internal bus speed, set the CGM_SC_DC4 register bits correctly not to exceed maximum

external bus frequency. The maximum external bus frequency is 66.7 MHz.

4

5

6

7

8

Signals are measured at 50% V_{DD_HV_IO_EBI}or V_{DD_HV_IO_FLEXE}

Refer to Fast pad timing in Table 18.

.

CLKOUT may be required at the highest drive strength in order to meet the hold time specification.

One wait state must be added for all write accesses to external memories at the maximum external bus frequency.

One wait state must be added to the outut signal valid delay for external writes.

V_{OH_F}

V_{DD_HV_IO_EBI}/ 2

V_{OL_F}

D_CLKOUT

2

3

2

4

1

Figure 50. D_CLKOUT Timing

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

119

Electrical characteristics

D_CLKOUT

V

_{DD_HV_IO_EBI}/ 2

6

5

Output

Bus

V_{DD_HV_IO_EBI}/ 2

6

5

Output

Signal

V_{DD_HV_IO_EBI}/ 2

6

Output

Signal

V_{DD_HV_IO_EBI}/ 2

Figure 51. Synchronous Output Timing

MPC5777M Microcontroller Data Sheet, Rev. 6

120

NXP Semiconductors

Electrical characteristics

D_CLKOUT

V_{DD_HV_IO_EBI}/ 2

7

8

V_{DD_HV_IO_EBI}/ 2

Input

Bus

7

8

Input

Signal

V_{DD_HV_IO_EBI}/ 2

Figure 52. Synchronous Input Timing

3.16.8

I²C timing

2

The I C AC timing specifications are provided in the following tables.

2

1

Table 70. I C input timing specifications — SCL and SDA

Value

Min Max

No.

Symbol

Parameter

Unit

1

2

3

4

—

CC Start condition hold time

CC Clock low time

2

—

PER_CLK Cycle²

8

PER_CLK Cycle

CC Bus free time between Start and Stop condition

CC Data hold time

4.7

0.0

µs

ns

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

121

Electrical characteristics

2

1

Table 70. I C input timing specifications — SCL and SDA (continued)

Value

No.

Symbol

Parameter

Unit

Min

Max

5

6

7

8

—

CC Clock high time

4

0.0

2

—

PER_CLK Cycle

ns

CC Data setup time

CC Start condition setup time (for repeated start condition only)

CC Stop condition setup time

PER_CLK Cycle

2

1

2

I²C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower

than 1 ns (10% – 90%).

PER_CLK is the SoC peripheral clock, which drives the I²C BIU and module clock inputs. See the Clocking chapter in

the device reference manual for more detail.

2

1,2 ,3,4

Table 71. I C output timing specifications — SCL and SDA

Value

No.

Symbol

Parameter

Unit

Min

Max

1

2

3

4

5

6

7

8

—

CC Start condition hold time

CC Clock low time

6

10

4.7

7

—

PER_CLK Cycle⁵

PER_CLK Cycle

µs

CC Bus free time between Start and Stop condition

CC Data hold time

PER_CLK Cycle

CC Clock high time

10

2

CC Data setup time

CC Start condition setup time (for repeated start condition only)

CC Stop condition setup time

20

10

1

All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

2

3

4

Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package

capacitance is accounted for, and does not need to be subtracted from the 25 pF value.

Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and

may cause incorrect operation.

Programming the IBFD register (I²C bus Frequency Divider) with the maximum frequency results in the minimum

output timings listed. The I²C interface is designed to scale the data transition time, moving it to the middle of the SCL

low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD

register.

5

PER_CLK is the SoC peripheral clock, which drives the I²C BIU and module clock inputs. See the Clocking chapter

in the device reference manual for more detail.

MPC5777M Microcontroller Data Sheet, Rev. 6

122

NXP Semiconductors

Electrical characteristics

2

5

SCL

SDA

8

6

4

3

1

7

2

Figure 53. I C input/output timing

3.16.9 GPIO delay timing

The GPIO delay timing specification is provided in the following table.

Table 72. GPIO delay timing

Value

Symbol

Parameter

Unit

Min

Max

IO_delay

CC

Delay from SIUL2 MSCR register bit update to pad function

enable at the input of the I/O pad

5

25

ns

3.16.10 Package characteristics

The following table lists the case numbers for each available package for the device.

Table 73. Package case numbers

Package Type

Device Type

Case Outline Number

416TEPBGA

512TEPBGA

Production

Emulation

98ARE10523D

98ASA00493D

98ASA00262D

Production or Emulation

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

123

Electrical characteristics

3.17 416 TEPBGA (production) case drawing

Figure 54. 416 TEPBGA (production) package mechanical drawing (Sheet 1 of 2)

MPC5777M Microcontroller Data Sheet, Rev. 6

124

NXP Semiconductors

Electrical characteristics

Figure 55. 416 TEPBGA (production) package mechanical drawing (Sheet 2 of 2)

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

125

Electrical characteristics

3.18 416 TEPBGA (emulation) case drawing

Figure 56. 416 TEPBGA (emulation) package mechanical drawing (Sheet 1 of 3)

MPC5777M Microcontroller Data Sheet, Rev. 6

126

NXP Semiconductors

Electrical characteristics

Figure 57. 416 TEPBGA (emulation) package mechanical drawing (Sheet 2 of 3)

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

127

Electrical characteristics

Figure 58. 416 TEPBGA (emulation) package mechanical drawing (Sheet 3 of 3)

MPC5777M Microcontroller Data Sheet, Rev. 6

128

NXP Semiconductors

Electrical characteristics

3.19 512 TEPBGA case drawing

2

Figure 59. 512 TEPBGA package mechanical drawing (Sheet 1 of 2)

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

129

Electrical characteristics

Figure 60. 512 TEPBGA package mechanical drawing (Sheet 2 of 2)

MPC5777M Microcontroller Data Sheet, Rev. 6

130

NXP Semiconductors

Electrical characteristics

3.20 Thermal characteristics

The following tables describe the thermal characteristics of the device.

.

Table 74. Thermal characteristics

416

Value Value

512

Symbol

Parameter

Conditions

Unit Notes

1,2

1,2,3

1,3

R_JA

Junction-to-Ambient, Natural

Convection

Single Layer board (1s)

Four layer board (2s2p)

25

24.1 °C/W

17.2 16.8

R_JMAJunction-to-Moving-Air, Ambient

@200 ft/min., single layer

board (1s)

18.1 16.6 °C/W

1,3

@200 ft/min., four layer board 13.4 12.4

(2s2p)

4

5

6

7

R_JB

R_JC

_JT

Junction-to-board

—

8.6

5.0

0.2

3.5

8.8

5.0

0.2

3.0

°C/W

Junction-to-case

Junction-to-package top

Natural convection

_JB

Junction-to-package bottom/solder Natural convection

balls

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance,

mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on

the board, and board thermal resistance.

2

3

4

Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

5

6

7

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2.

Thermal characterization parameter indicating the temperature difference between package bottom center and

the junction temperature per JEDEC JESD51-12.

3.20.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T , can be obtained from the equation:

J

T = T + (R

* P )

Eqn. 1

J

A

JA

D

where:

o

T = ambient temperature for the package ( C)

A

o

R

= junction-to-ambient thermal resistance ( C/W)

JA

P = power dissipation in the package (W)

D

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for

estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a

four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance

is not a constant. The thermal resistance depends on the:

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

131

Electrical characteristics

•

Construction of the application board (number of planes)

Effective size of the board which cools the component

Quality of the thermal and electrical connections to the planes

Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package

to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance

between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit

board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:

•

One oz. (35 micron nominal thickness) internal planes

Components are well separated

2

Overall power dissipation on the board is less than 0.02 W/cm

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the

ambient temperature varies widely within the application. For many natural convection and especially closed box applications,

the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the

device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the

local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

T = T + (R

* P )

Eqn. 2

J

B

JB

D

where:

o

T = board temperature for the package perimeter ( C)

B

o

R

= junction-to-board thermal resistance ( C/W) per JESD51-8

JB

P = power dissipation in the package (W)

D

When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable

if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal

resistance:

R

= R

+ R

CA

Eqn. 3

JA

JC

where:

o

R

= junction-to-ambient thermal resistance ( C/W)

JA

JC

CA

o

= junction-to-case thermal resistance ( C/W)

o

= case to ambient thermal resistance ( C/W)

R

is device related and is not affected by other factors. The thermal environment can be controlled to change the

JC

case-to-ambient thermal resistance, R

. For example, change the air flow around the device, add a heat sink, change the

CA

mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding

the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat

sink to ambient. For most packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the

junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a

substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the

thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple

estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be

generated upon request.

MPC5777M Microcontroller Data Sheet, Rev. 6

132

NXP Semiconductors

Ordering information

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization

parameter ( ) to determine the junction temperature by measuring the temperature at the top center of the package case using

JT

the following equation:

T = T + ( x P )

Eqn. 4

J

T

JT

D

where:

o

T = thermocouple temperature on top of the package ( C)

T

o



= thermal characterization parameter ( C/W)

JT

P = power dissipation in the package (W)

D

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests

on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from

the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling

effects of the thermocouple wire.

When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter

( ) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed

JPB

pad) using the following equation:

T = T + (

x P )

Eqn. 5

J

B

JPB

D

where:

o

T = thermocouple temperature on bottom of the package ( C)

T

o



= thermal characterization parameter ( C/W)

JT

P = power dissipation in the package (W)

D

4

Ordering information

Table 75 shows the orderable part numbers for the MPC5777M series.

Table 75. Orderable part number summary

Part Number

Device Type^1,2

Sample

Package

PPC5777MK0MVU8B

PPC5777MK0MVA8B

PPC5777M2K0MVU8B

PPC5777M2K0MVA8B

SPC5777MK0MVU8

SPC5777MK0MVU8R

416 TEPBGA

512 TEPBGA

416 TEPBGA

512 TEPBGA

416 TEPBGA

Sample

Sample ED

Production PD

416 TEPBGA

w/Tape and Reel

SPC5777MK0MVA8

SPC5777MK0MVA8R

Production PD

512 TEPBGA

w/Tape and Reel

1

“PD” refers to a production device, orderable in quantity

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

133

Ordering information

2

“ED" refers to an emulation device, orderable in limited quantities. An emulation

device (ED) is for use during system development only and is not to be used in

production. An ED is a Production PD chip combined with a companion chip to form

an Emulation and Debug Device (ED) and includes additional RAM memory and

debug features. EDs are provided “as is" without warranty of any kind. In the event

of a suspected ED failure, NXP agrees to exchange the suspected failing ED from

the customer at no additional charge; however, NXP will not analyze ED returns.

MPC5777M Microcontroller Data Sheet, Rev. 6

134

NXP Semiconductors

Ordering information

Example code:

M

PC

57

4

6

M

Q

F0

M

xx

5

R

MC Qualification Status

Power Architecture Core

Automotive Platform

Processor Core

Flash Memory Size

Product/Family Name

Miscellaneous (Optional)

Fab and Mask Revision

Temperature

Package Code

Maximum Frequency

Tape or Reel

Qualification Status

Flash Memory Size

Package Code

MPC = Full specification qualified

SPC = Mask specification qualified

PPC = Engineering samples

ZP = 416 PBGA SnPb

z0, z2

z4

z7

VA = 416 PBGA Pb-free

VA = 512 TEPBGA Pb-free

VU = 416 TEPBGA Pb-free

VF = 208 MAPBGA SnPb

VM = 208 MAPBGA Pb-free

ZQ = 324 PBGA SnPb

VZ = 324 PBGA Pb-free

LQ = 144 LQFP Pb-free

LU = 176 LQFP Pb-free

KU = 176 LQFP ep Pb-free

MP = 292 MAPBGA Pb-free

OU = 216 FQ (176 leads)

1

2

3

4

5

6

7

8

9

256 KB

1 MB

Automotive Platform

55 = PPC in 130 nm

56 = PPC in 90 nm

57 = PPC in 55 nm

384 KB 1.5 MB 1.5 MB

512 KB

2 MB

3 MB

4 MB

6 MB

8 MB

12 MB

16 MB

768 KB 2.5 MB

Processor Core

0 = e200z0

1 = e200z1

2 = e200z2

3 = e200z3

4 = e200z4

5 = e200z6 without VLE

6 = e200z6

1 MB

1.5 MB

2 MB

3 MB

4 MB

5 MB

6 MB

8 MB

Maximum Frequency

0 = 64 MHz

1 = 80 MHz

2 = 120 MHz

3 = 150 MHz

4 = 160 MHz

5 = 200 MHz

8 = 300 MHz

2.5 MB

3 MB

7 = e200z7

Miscellaneous

D = Dual Core

T = Triple Core

Q = Quad Core

S = Single Core

2 = Emulation Device

Temperature Specification

C = –40 °C to 85 °C

V = –40 °C to 105 °C

M = –40 °C to 125 °C

K = –40 °C to 135 °C

Suffix

A = cut2.0 revision

T = Tape

Fab and Mask Revision

F = ATMC

R = Reel

K = TSMC

0 = Revision

Figure 61. Product code structure

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

135

Document revision history

5

Document revision history

Table 76 summarizes revisions to this document.

Table 76. Revision history

Description of changes

Revision

Date

1

2

12/2011

4/2013

Initial release

Throughout

• Data sheet now includes both KGD (T_J165 °C) and non-KGD (T_J150 °C)

specifications

• The interfaces and components formerly including the name “DigRF” have been

renamed to “LFAST.”

Introduction

• Changed on-chip general-purpose SRAM to 404 KB (was 384 KB)

• Changed item describing Boot Assist Flash support to “Boot Assist Module (BAM)

supports factory programming using serial bootload through ’UART Serial Boot Mode

Protocol’. Physical interface (PHY) can be: UART/LIN, CAN, FlexRay”

Table 1 (Family comparison):

• Changed feature from “Zipwire/LFAST⁷bus” to “Zipwire (SIPI / LFAST⁷) Interprocessor

Communication Interface”

Figure 1 (Block diagram):

• Changed SRAM from 320 to 340 KB

• Changed figure to include “Triple INTC”

• Added “LFAST Switch” block to Computational Shell

• Added “Debug SIPI” block to the Peripheral Domain 50 MHz Concentrator

Figure 2 (Periphery allocation):

• Added PSI5_S_0 module

• Changed “Peripheral Cluster A” to “Peripheral Cluster B” and “Peripheral Cluster B” to

“Peripheral Cluster A”

• Added PSI5_S_0 module

Package pinouts and signal descriptions

Figure 3 (292-ball BGA production device pinout (top view))

Figure 4 (292-ball BGA emulation device pinout (top view))

Figure 5 (512-ball BGA production device pinout (top view))

Figure 8 (512-ball BGA emulation device pinout (top view)):

• Changed “VDD_HV_PMC_BYP” to “VDD_HV_IO_MAIN”

Table 2 (Power supply and reference pins):

• Removed V_{DD_HV_PMC_BYP}(PMC Voltage Supply Bypass Capacitor) row.

Table 3 (System pins):

• Clarification of TESTMODE pin definition: “TESTMODE pull-down is implemented to

prevent the device from entering TESTMODE. It is recommended to connect the

TESTMODE pin to VSS_HV_IO on the board. The value of the TESTMODE pin is

latched at the negation of reset and has no affect afterward. The device will not exit

reset with the TESTMODE pin asserted during power-up.” (Added detail regarding

when TESTMODE pin value is latched and that device will not exit reset when pin is

asserted during power-up)

MPC5777M Microcontroller Data Sheet, Rev. 6

136

NXP Semiconductors

Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Package pinouts and signal descriptions (con’t)

Table 4 (LVDS pin descriptions):

• In SIPI/LFAST, Differential DSPI2, and Differential DSPI 5 groups, changed port pin

“PF[7]” to “PD[7]”

• Changed the polarity of the signal assigned to several port pins. For example, the

signal for port pin PD[7] has been changed to “SIPI_RXP” (was SIPI_RXN) and

“Interprocessor Bus LFAST, LVDS Receive Positive Terminal” (was “Interprocessor

Bus LFAST, LVDS Receive Negative Terminal”). This change affects port pins PD[7],

PF[13], PA[14], PD[6], PA[7], PA[8], PD[2], PD[3], PD[0], PD[1], PF[10], PF[9], PF[11],

PF[12], PQ[8], PQ[9], PQ[10], PQ[11], PI[14], and PI[15].

• Added package ball locations

Electrical characteristics—Miscellaneous

Section 3, Electrical characteristics:

• Thermal characteristics section has been moved to Package characteristics section.

• Following note removed: “All parameter values in this document are tested with

nominal supply voltage values (VDD_LV = 1.25 V, VDD_HV = 5.0 V ± 10%,

VDD_HV_IO = 5.0 V ± 10% or 3.3 V ± 10%) and TA = –40 to 125 °C unless otherwise

specified.”. Operating conditions will appear elsewhere in the data sheet.

• Added VDD_HV_IO_FLEX before VDD_HV_FLA in the second note on the page

Electrical characteristics—Absolute maximum ratings

Table 6 (Absolute maximum ratings):

• I_MAXDspecification now given by pad type (Medium, Strong, and Very Strong)

• I_MAXAspecification deleted.

• New specification: I_INJD(Maximum DC injection current for digital pad)

• New specification: I_INJA(Maximum DC injection current for analog pad)

• New specification: I_MAXSEG(Maximum current per power segment)

• New specification: V_FERS(Flash erase acceleration supply)

• New specification: V_{DD_HV_IO_EBI}(External Bus Interface supply)

• Changed “Emulation module supply” to “BD supply” in the VDD_LV_BD – BDD_LV row

• Maximum junction temperature changed from 125 °C to 165 °C in cumulative time

limits on voltage levels for V_{DD_LV}and V_{DD_LV_BD}

• Footnote added to V_FERS: V_FERSis a factory test supply pin that is used to reduce the

erase time of the flash. It is only available in bare die devices. There is no V_FERSpin in

the packaged devices. The V_FERSsupply pad can be bonded to ground (V_{SS_HV}) to

disable, or connected to 5.0 V ± 5% to use the flash erase acceleration feature. Pad

can be left at 5 V ± 5% in normal operation.

• Footnote added to V_IN: “The maximum input voltage on an I/O pin tracks with the

associated I/O supply maximum. For the injection current condition on a pin, the

voltage will be equal to the supply plus the voltage drop across the internal ESD diode

from I/O pin to supply. The diode voltage varies greatly across process and

temperature, but a value of 0.3V can be used for nominal calculations.“

• Footnote V_{DD_LV}changed: “1.32 – 1.375 V range allowed periodically for supply with

sinusoidal shape and average supply value below 1.288 V at maximum TJ = 165 °C”

(was 1.275)

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

137

Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—Operating conditions

Table 8 (Device operating conditions)

• Changed VSTBY_BO minimum from 0.7V to 0.8V.

Electrical characteristics—DC electrical specifications

Table 10 (DC electrical specifications)

• Replaced table; significant changes throughout, including parameter names,

descriptions, and values.

MPC5777M Microcontroller Data Sheet, Rev. 6

138

NXP Semiconductors

Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—I/O pad specification

Table 11 (I/O pad specification descriptions)

• Revised “Very strong configuration” description to include EBI data bus.

• Added “EBI configuration” row.

• Changed “Input only pads” description to “These pads, which ensure low input leakage,

are associated with the ADC channels” (was “These pads are associated with the ADC

channels and 32 kHz low power external crystal oscillator providing low input leakage”)

• Changed note following table to “Each I/O pin on the device supports specific drive

configurations. See the signal description table in the device reference manual for the

available drive configurations for each I/O pin” (was “All pads can be configured in all

configurations”)

Table 12 (I/O input DC electrical characteristics)

• New specification: V_DRFTTTL(Input V_IL/V_IHtemperature drift TTL)

• New specification: V_DRFTAUT(Input V_IL/V_IHtemperature drift)

• New specification: V_DRFTCMOS(Input V_IL/V_IHtemperature drift CMOS)

• Conditions for V_{IHCMOS_H}, V_IHCMOS, V_{ILCMOS_H}, V_ILCMOS, V_HYSCMOS, V_DRFTCMOSare

now 3.0 V < V_{DD_HV_IO}< 3.6 V and 4.5 V < V_{DD_HV_IO}< 5.5 V (was 2.7 V < V_{DD_HV_IO}

< 3.6 V and 4.0 V < V_{DD_HV_IO}< 5.5 V)

• New specification: I_{LKG_MED}(Digital input leakage for MEDIUM pad)

• Footnotes give formulas for approximation of the variation of the minimum value with

supply of V_IHAUTand V_HYSAUT(previously stated formulas approximated upper value

instead of minimum value). Changed formula for V_IHAUTto “0.69 x VDD_HV_IO” (was

“0.69 supply”). Changed formula for V_HYSAUTto “0.11 x V_{DD_HV_IO}” (was “0.11

supply”).

• Footnote gives formula for approximation of the variation of the maximum value with

supply of V_ILAUT(previously stated formula approximated upper value instead of

maximum value). Changed formula for V_ILAUTto “0.49 x V_{DD_HV_IO}” (was “0.49

supply”).

• Added footnote: “In a 1 ms period, assuming stable voltage and a temperature

variation of ±30°C, VIL/VIH shift is within ±50 mV.”

• VHYSAUT conditions column: replaced dash with 4.5V < VDD_HV_IO < 5.5V

• CIN row, changed GPIO input pins conditions Max value from “10” to 7pF and EBI input

pins Max value from “8” to “7pF”

Table 13 (I/O pull-up/pull-down DC electrical characteristics)

• Significant revisions throughout this table, including new conditions for I_WPU and

I_WPD



• New specification: R_WPU(Weak pull-up resistance)

• New specification: R_WPD(Weak pull-down resistance)

• New figure: Figure 8 (Weak pull-up electrical characteristics definition)

• New figure: Figure 18 (I/O output DC electrical characteristics definition)

MPC5777M Microcontroller Data Sheet, Rev. 6

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—I/O pad specification (con’t)

Table 14 (WEAK configuration output buffer electrical characteristics)

• R_{OH_W}(PMOS output impedance weak configuration) condition is now 4.5 V <

V_{DD_HV_IO}< 5.9 V, Push pull I_OH< 0.5 mA (was 4.0 V < V_{DD_HV_IO}< 5.9 V). Removed

3.0 V < V_{DD_HV_IO}< 4.0 V condition.

• R_{OL_W}(NMOS output impedance WEAK configuration) condition is now 4.5 V <

V_{DD_HV_IO}< 5.9 V, Push pull I_OL< 0.5 mA (was 4.0 V < V_{DD_HV_IO}< 5.9 V). Removed

3.0 V < V_{DD_HV_IO}< 4.0 V condition.

• t_{TR_W}(Transition time output pin WEAK configuration) conditions changed for C_L= 25

pF, C_L= 50 pF, C_L= 200 pF: 4.5 V < V_{DD_HV_IO}< 5.9 V (was 4.0 V < VDD_HV_IO <

5.9 V)

• Specification change: t_{TR_W}, C_L= 200 pF, 4.5 V < V_{DD_HV_IO}< 5.9 V max value is

820 ns (was 1000)

• Specification change: t_{TR_W}, C_L= 25 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is 50 ns

(was TBD)

• Specification change: t_{TR_W}, C_L= 50 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is 100 ns

(was TBD)

• Specification change: t_{TR_W}, C_L= 200 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is

350 ns (was TBD) and max value is 1050 ns (was TBD)

• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to

5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid

for VSIO[VSIO_xx] = 0

Table 15 (MEDIUM configuration output buffer electrical characteristics)

• R_{OH_M}(PMOS output impedance MEDIUM configuration) condition is now 4.5 V <

V_{DD_HV_IO}< 5.9 V, Push pull I_OH< 2 mA (was 4.0 V < V_{DD_HV_IO}< 5.9 V). Removed

3.0 V < V_{DD_HV_IO}< 4.0 V condition.

• R_{OL_M}(NMOS output impedance MEDIUM configuration) condition is now 4.5 V <

V_{DD_HV_IO}< 5.9 V, Push pull I_OL< 2 mA (was 4.0 V < V_{DD_HV_IO}< 5.9 V). Removed

3.0 V < V_{DD_HV_IO}< 4.0 V condition.

• t_{TR_M}(Transition time output pin MEDIUM configuration) conditions changed for C_L=

25 pF, C_L= 50 pF, C_L= 200 pF: 4.5 V < V_{DD_HV_IO}< 5.9 V (was 4.0 V < VDD_HV_IO

< 5.9 V)

• Specification change: t_{TR_M}, C_L= 200 pF, 4.5 V < V_{DD_HV_IO}< 5.9 V max value is

200 ns (was 240)

• Specification change: t_{TR_M}, C_L= 25 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is 12 ns

(was TBD)

• Specification change: t_{TR_M}, C_L= 50 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is 24 ns

(was TBD)

• Specification change: t_{TR_M}, C_L= 200 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is 70 ns

(was TBD) and max value is 300 ns (was TBD)

• New specification: I_{DCMAX_M}(Maximum DC current)

• New specification: t_{SKEW_M}(Difference between rise and fall time)

• Formula given for transition time typical value changed to: t_{TR_M}(ns) = 5.6 ns+C_L(pF)

x 1.11 ns/pF (when 0 pF < C_L< 50 pF) and t_{TR_M}(ns) = 13 ns+C_L(pF) x 0.96 ns/pF

(when 50 pF < C_L< 200 pF)

• Footnote added: R_{OX_M}(min) may decrease by 10% at T_J= 165 °C.

• Footnote added: R_{OX_M}(max) may increase by 10% at T_J= 165 °C.

• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to

5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid

for VSIO[VSIO_xx] = 0

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Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—I/O pad specification (con’t)

Table 16 (STRONG configuration output buffer electrical characteristics)

• New specification: I_{DCMAX_S}(Maximum DC current)

• Renamed: R_{OH_F}(PMOS output impedance STRONG configuration) is now R_{OH_S}

• Renamed: R_{OL_F}(NMOS output impedance STRONG configuration) is now R_{OL_S}

• Renamed: f_{MAX_M}(Output frequency STRONG configuration) is now f_{MAX_S}

• R_{OH_S}condition is now 4.5 V < V_{DD_HV_IO}< 5.9 V, Push pull I_OH< 8 mA (was 4.0 V <

V_{DD_HV_IO}< 5.9 V). Removed 3.0 V < V_{DD_HV_IO}< 4.0 V condition.

• R_{OL_S}condition is now 4.5 V < V_{DD_HV_IO}< 5.9 V, Push pull I_OH< 8 mA (was 4.0 V <

V_{DD_HV_IO}< 5.9 V). Removed 3.0 V < V_{DD_HV_IO}< 4.0 V condition.

• t_{TR_S}conditions changed for C_L= 25 pF, C_L= 50 pF, C_L= 200 pF: 4.5 V < V_{DD_HV_IO}

< 5.9 V (was 4.0 V < VDD_HV_IO < 5.9 V)

• Specification change: f_{MAX_S}, C_L= 200 pF max value is 5 MHz (was “—”)

• Specification change: t_{TR_S}, C_L= 25 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is 4 ns

(was TBD) and max value is 15 ns (was TBD)

• Specification change: t_{TR_S}, C_L= 50 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is 6 ns

(was TBD) and max value is 27 ns (was TBD)

• Specification change: t_{TR_S}, C_L= 200 pF, 3.0 V < V_{DD_HV_IO}< 3.6 V min value is 20 ns

(was TBD) and max value is 83 ns (was TBD)

• Footnote added: R_{OX_S}(min) may decrease by 10% at T_J= 165 °C.

• Footnote added: R_{OX_S}(max) may increase by 10% at T_J= 165 °C.

• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to

5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid

for VSIO[VSIO_xx] = 0

Table 17 (VERY STRONG configuration output buffer electrical characteristics)

• New specification: I_{DCMAX_M}(Maximum DC current)

• New condition added to t_{TR_V:}V_{DD_HV_IO}= 5.0 V ± 10%, C_L= 200 pF

• Footnote added: R_{OX_V}(min) may decrease by 10% at T_J= 165 °C.

• Footnote added: R_{OX_V}(max) may increase by 10% at T_J= 165 °C.

• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to

5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid

for VSIO[VSIO_xx] = 0

Table 18 (EBI pad output electrical specification)

• Replaced this table “EBI output driver electrical characteristics” with new table “EBI pad

electrical specification”

Electrical characteristics—I/O pad current specification

New section

Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics

Section 3.8, Reset pad (PORST, ESR0) electrical characteristics:

• Added note on PORST and active control

Figure 11 (Noise filtering on reset signal):

• Replaced; significant detail added

• Clarification: V_ESR0is also described by V_PORSTbehavior shown in illustration.

• Figure prefaced with more detailed PORST description.

MPC5777M Microcontroller Data Sheet, Rev. 6

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics

(con’t)

Table 20 (Reset electrical characteristics)

• New specification: W_FNMI(ESR1 input filtered pulse)

• New specification: W_NFNMI(ESR1 input not filtered pulse)

• New specification: V_{DD_POR}(Minimum supply for strong pull-down activation)

• I_{OL_R}condition changed (V_{DD_HV_IO}= 1.0 V is now V_{DD_HV_IO}= V_{DD_POR}, V_{DD_HV_IO}

= 4.0 V is now 3.0 V < V_{DD_HV_IO}< 5.5 V, and V_OL= 0.35*V_{DD_HV_IO}is now V_OL

0.9 V)

>

• Specification change: I_{OL_R}(3.0 V < V_{DD_HV_IO}< 5.5 V, V_OL> 0.9 V) min value is

11 mA (was 15)

• Added footnote: An external 4.7 K pull-up resistor is recommended to be used with

the PORST and ESR0 pins for fast negation of the signals.

• Added footnote: I_{OL_R}applies to both PORST and ESR0: Strong pull-down is active on

PHASE0 for PORST. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and

the beginning of PHASE3 for ESR0.

• Added note on reset signal slew rate restrictions

Electrical characteristics—Oscillator and FMPLL

Section 3.12, Oscillator and FMPLL

Table 21 (PLL0 electrical characteristics)

• New specification: f_PLL0PHI0(PLL0 output frequency)

• Specification change: t_PLL0LOCK(PLL0 lock time) maximum is 100 µs (was

100–110 µs)

• _PLL0LTJspecification parameter and conditions change: “PLL0 output long term jitter,

f_PLL0IN= 20 MHz (resonator), VCO frequency = 800 MHz” (was “PLL0 output long term

jitter, f_PLL0IN= 20 MHz (resonator)”). Conditions significantly revised.

• Revised footnote: “VDD_LV noise due to application in the range V_{DD_LV}= 1.25 V ±5%

with frequency below PLL bandwidth (40 KHz) will be filtered” (was “1.25 V ±5%

application noise below 40kHz at VDD_LV pin”)

• Removed “F” from “FXOSC” in footnote 1

Table 22 (PLL1 electrical characteristics)

• Specification change: f_PLL1PHI(PLL1 output clock PHI) is now f_PLL1PHI0(PLL1 output

clock PHI0)

• Specification change: f_PLL1PHI0(PLL1 output clock PHI0) max is 200 MHz (was

625 MHz)

• fPLL1PHI parameter, Max column, changed 200MHz to 300MHz.

• Removed “F” from “FXOSC” in footnote 1

MPC5777M Microcontroller Data Sheet, Rev. 6

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Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—Oscillator and FMPLL (con’t)

Table 23 (External Oscillator electrical specifications):

• New specification: V_HYS(Comparator Hysteresis)

• New specification: V_EXTAL(Oscillation Amplitude on the EXTAL pin after startup)

• Specification change: f_XTALrange values changed: f_XTALranges are 4–8 MHz,

>8–20 MHz, and >20–40 MHz (previously stated as 4–8 MHz, 8–16 MHz, and

20–40 MHz

• Specification change t_cst(Crystal start-up time) is now specified by temperature range

• Specification change: V_IHEXTspecified at V_REF= 0.28 * V_{DD_HV_IO_JTAG}(previously

specified at V_DDOSC= 3.0 V and V_DDOSC= 5.5 V)

• Specification change: V_ILEXTspecified at V_REF= 0.28 * V_{DD_HV_IO_JTAG}(previously

specified at V_DDOSC= 3.0 V and V_DDOSC= 5.5 V)

• Specification change: C_{S_EXTAL}values specified by package (was previously based on

selected load capacitance value)

• Specification change: C_{S_XTAL}values specified by package (was previously based on

selected load capacitance value)

• Specification change: g_m(Oscillator Transconductance) is now specified by

temperature and frequency range conditions (was previously specified without

conditions)

• Footnote added: “All oscillator specifications are valid for

V_{DD_HV_IO_JTAG}= 3.0 V – 5.5 V.“

• Footnote added to C_{S_EXTAL}, C_{S_XTAL}to refer to crystal manufacturer's specifications

for load capacitance values.

• Footnote added: “Amplitude on the EXTAL pin after startup is determined by the ALC

block, i.e., the Automatic Level Control Circuit. The function of the ALC is to provide

high drive current during oscillator startup, but reduce current after oscillation in order

to reduce power, distortion, and RFI, and to avoid over-driving the crystal. The

operating point of the ALC is dependent on the crystal value and loading conditions.”

• Footnote added: “IXTAL is the oscillator bias current out of the XTAL pin with both

EXTAL and XTAL pins grounded. This is the maximum current during startup of the

oscillator. The current after oscillation is typically in the 2–3 mA range and is dependent

on the load and series resistance of the crystal.”

• VILEXT parameter, changed “External Reference” to “External Clock Input”

• VILEXT parameter, added footnote: This parameter is guaranteed by design rather than

100% tested.

Table 24 (Selectable load capacitance):

• Changed footnote 2 from “Values in this table do not include 8 pF routing and ESD

structure on die and package trace capacitance.” to "Values in this table do not include

the die and package capacitances given by Cs_xtal/Cs_extal in Table 23 (External

Oscillator electrical specifications).”

Electrical characteristics—ADC specifications

Section 3.10.1, ADC input description

Table 26 (ADC pin specification)

• I_LK__INspecification change: removed T_A= 125 °C row from (T_A= 125 °C)

• I_{LK_INUD}, I_{LK_INUSD}, I_{LK_INREF}, and I_{LK_INOUT}specification changes to parameters,

conditions, and values.

• Specification change: I_INJmin value is –3 mA (was –1)

• Specification change: C_Smax value is 8.5 pF (was 7)

• Specification change: R_SWnmax value for SARn channels is 1.1 k (was 0.6)

MPC5777M Microcontroller Data Sheet, Rev. 6

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—ADC specifications (con’t)

Section 3.10.1, ADC input description

Table 26 (ADC pin specification):

• Specification change: RSWn max value for SARB channels is 1.7 k (was 1.2)

• Specification change: RCMSW max value is 2.6 k(was 2)

• Removed VREF_BG specification

• Added VREF_BG_LR and VREF_BG_TC specifications

• Added footnote: Specifications in this table apply to both packaged parts and Known

Good Die (KGD) parts, except where noted.

• Added footnote: The temperature coefficient and line regulation specifications are

used to calculate the reference voltage drift at an operating point within the specified

voltage and temperature operating conditions.

• Parameter ILK_INOUT description column, changed MEDIUM output buffer with GPIO

output buffer.

Table 27 (SARn ADC electrical specification)

• Replaced table

Section 3.13.3, S/D ADC electrical specification

• Revised sentence to indicate that the ADCs are 14-bit (was 16-bit)

Table 28 (SDn ADC electrical specification)

• New specification: f_PASSBAND(Pass band)

• Removed V_DDand V_SSspecifications

• Removed f_INspecification

• Throughout table, appended _D to change to V_{DD_HV_ADV_D}(was V_{DD_HV_ADV}),

V_{SS_HV_ADV_D}(was V_{SS_HV_ADV}), V_{DD_HV_ADR_D}(was V_{DD_HV_ADR}), and

V_{SS_HV_ADR_D}(was V_{SS_HV_ADR}).

• V_{IN_PK2PK}(Input range peak to peak V_{IN_PK2PK}= V_INP– V_INM): single ended

specification extended to include multiple conditions

• Multiple condition changes for the _GAIN and SNR_DIFF150parameters

• _GAIN:changed maximum value for Before calibration condition to “1.5 %” (was 1 %).

• SFDR conditions revised to include different GAIN settings

• Specification change: V_BIASmin value is –2.5% (was –10) and the max value is +2.5%

(was +10)

• Significant revisions to footnotes, including one added to voltage range conditions in

all SNR specs: “In the range 3.6 V< V_{DD_HV_ADV}<4.0 V and

<3.0 V<V_{DD_HV_ADR_D}<4.0 V, SNR parameter degrades by 9 dB”

• fADCD_M, changed “S/D clock 3(4)” to “S/D Modulator Input Clock” and replaced “—”

with “4” in Min column

• fADCD_S changed “conversion rate'” to “output conversion rate”

• Changed SNR specifications Unit column from “dB” to “dBFS”

• Changed SFDR specification Unit column from “dB” to “dBc”

• Add to footnote: Input impedance is calculated in megaohms by the formula 25.6/(Gain

Fadcd_m)

• Changed Group delay, OSR = 75, Max value from “546” to “596”

• Added new specifications: SINADDIFF150, SINADDIFF333, SINADSE150, THDDIFF150,

THDDIFF333, THDSE150

Electrical characteristics—Temperature sensor specifications

Table 29 (Temperature sensor electrical characteristics)

• T_SENS, T_ACC, and I_{TEMP_SENS}added to Symbol column.

• Condition change for T_ACC(Accuracy): added 150 °C and 165 °C conditions

• Specification change: T_ACCmin value for T_J< 165°C is 7 °C (was –3) and max value

is 7 °C (was 3)

• Specification change: I_{TEMP_SENS}max value is 700 µA (was 600).

MPC5777M Microcontroller Data Sheet, Rev. 6

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Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—LFAST electrical specifications

Formerly named “DigRF interface electrical characteristics”; renamed to “LVDS Fast

Asynchronous Serial Transmission (LFAST) pad electrical characteristics. The change

from “DigRF” to “LFAST” applies throughout.

Figure 16 (LFAST and MSC/DSPI LVDS timing definition). Figure updated.

Section Table 30., LVDS pad startup and receiver electrical characteristics,

• Specification change: added I_{LVDS_BIAS}

• TRANSMITTER parameters moved to separate table: V_{OS_DRF}(Common mode

voltage), |D_{VOD_DRF}| (Differential output voltage swing (terminated)), t_{TR_DRF}

(Rise/Fall time (10%–90% of swing)), R_{OUT_DRF}(Terminating resistance), C_{OUT_DRF}

(Capacitance)

• Receiver requirement V_{ICOM_DRF}renamed to V_ICOM

• Receiver requirement |_{VI_DRF|}renamed to |_VI|

• Receiver specification V_{HYS_DRF}renamed to V_HYS

• Receiver specification R_{IN_DRF}renamed to R_IN

• Receiver specification C_{IN_DRF}renamed to C_IN

• Receiver specification L_{IN_DRF}deleted

• Extensive changes throughout table footnotes.

Table 31 (LFAST transmitter electrical characteristics,):

Differential output voltage swing parameter:

• Removed the delta symbol from |VOD|

• Changed Min = 100, Typ = 171, Max = 285. removed the “+/-” from each value.

Rise/Fall time parameter:

• Changed “(10%–90% of swing)” to (absolute value of the differential output voltage

swing

Table 32 (MSC/DSPI LVDS transmitter electrical characteristics ,):

Differential output voltage swing parameter:

• Removed the delta symbol from |VOD|

• Changed Min +/- 150 to 150

• Changed Typ +/- 200 to 214

• Changed Max +/- 400 to 400

Rise/Fall time parameter:

• Changed “(10%–90% of swing)” to (absolute value of the differential output voltage

swing)

Table 33 (LFAST PLL electrical characteristics)

• Changed footnote 2, from “320” to “640” MHz frequency

Table 34 (Aurora LVDS electrical characteristics,)

• Extensive changes throughout table

MPC5777M Microcontroller Data Sheet, Rev. 6

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—Power management: PMC, POR/LVD, sequencing

Table 40 (PMC operating conditions and external regulators supply voltage)

• Specification change: V_{DD_HV_PMC,}Reduced internal regulator output capacity max

value is 3.5 V (was 5.5)

• Specification change: V_{DD_HV_PMC}, Monitoring activity only min value is 2.7 V (was

3.0) and max value is 3.15 V (was 5.5)

Section 3.14.2, Power management integration

• Entire section replaced

Table 36 (Flash power supply):

• New

Section 3.14.4, Device voltage monitoring

• Added Figure 24 (Voltage monitor threshold definition)

Table 37 (Voltage monitor electrical characteristics)

• VPORUP_LV Added footnote2, “Hysteresis is only true with the High voltage Supplies for

the I/O Main and the ADC are connected together. (There is actually around 1V of

Hysteresis using these two supplies.)”

• New specification: V_POR240(HV supply power-on reset voltage monitoring)

• New specification: t_VDASSERT(Voltage detector threshold crossing assertion)

• New specification: t_VDRELEASE(Voltage detector threshold crossing deassertion)

• Specification change: V_{PORUP_LV}, Rising voltage max value is 1180 mV (was 1170)

• Specification change: V_{PORUP_LV}Falling voltage max value is 1100 mV

• Significant changes to footnotes for this table.

• V_LVD096(LV internal supply low voltage monitoring). Footnote added: “LV internal

supply levels are measured on device internal supply grid after internal voltage drop.“

• V_LVD108(LV internal supply low voltage monitoring). Footnote added: “LV internal

supply levels are measured on device internal supply grid after internal voltage drop.“

• Specification change: V_LVD112max value is 1180 mV (was 1190)

• Specification change: VHVD140 is 1440 mV (was 1420)

• Specification change: V_{PORUP_HV}Rising voltage max value is 4480 mV (was 4200);

min value is 4040. in addition, the Falling voltage min value is 2830 mV (was 2700) and

the max value of 3210 mV was added

• Specification change: V_LVD270max value is 2950 mV (was 2980)

• Specification change: V_LVD400max value is 4410 mV (was 4400); min value added for

Rising voltage. Also, changed min value for Falling voltage is 3970 mV (was 3980)

Specification change: V_HVD600min value is 5560 mV (was 5520) and max value is

6000 mV (was 5960)

Table 39 (Functional terminals state during power-up and reset)

• Corrected ESR1 RESET pad state to “Weak pull-up” (was “pull-down”) and DEFAULT

pad state to “Weak pull-up” (was “pull-down”)

• Corrected TMS RESET pad state to “Weak pull-up” (was “pull-down”) and DEFAULT

pad state to “Weak pull-up” (was “pull-down”)

• Changed TDO RESET pad state to “High impedance” (was “Weak pull-up”)

• Revised TESTMODE footnote: “An internal pull-down is implemented on the

TESTMODE pin to prevent the device from entering test mode if the package

TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin

to VSS_HV_IO on the board for maximum robustness, but not required. The value of

TESTMODE is latched at the negation of reset and has no affect afterward. The device

will not exit functional reset with the TESTMODE pin asserted during power-up. The

TESTMODE pin can be connected externally directly to ground without any other

components.”

MPC5777M Microcontroller Data Sheet, Rev. 6

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Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—Flash memory electrical characteristics

Section 3.15, Flash memory electrical characteristics

• This section completely revised.

Electrical characteristics—AC specifications—Debug and Calibration

Table 46 (JTAG pin AC electrical characteristics,):

• Specification change: t_JCYC(TCK cycle time) now consists of a single

specification—minimum value is 100 ns. Footnotes from previous entries have been

removed.

• Specification change: t_TDOHZ(TCK low to TDO high impedance) is now 15 ns (was 16)

• Classification change: All specifications are “D” (were “P” and “C”)

Table 47 (Nexus debug port timing)

• New specification: t_EVTIPW(EVTI pulse width)

• New specification: t_EVTOPW(EVTO pulse width)

• Clarification: footnote added to T_CYC, defining it as the system clock period

• Specification change: TDO propagation delay from falling edge of TCK max is 16 ns

(was 12.5 ns)

• Specification change: TCK cycle time is min value is 2 t_CYC(was 4)

• Specification change: Absolute minimum TCK cycle time min value is 40 ns (was 25)

• Specification change: TDI Data Hold Time min value is 5 ns (was 17.5)

• Specification change: TMS Data Hold Time min value is 5 ns (was 17.5)

• TDO propagation delay from falling edge of TCK max value is 16 ns (was 12.5)

• Specification change: t_TCYC(absolute minimum TCK cycle time) now consists of two

specifications—one with TDO sampled on posedge of TCK and one sampled with TDO

sampled on negedge of TCK.

Table 48 (Aurora LVDS interface timing specifications)

• Specification change: Data rate typ. value is undefined (was 1200 Mbps)

• Specification change: Data rate max. value is 1250 Mbps (was “Typ+1%”)

Table 49 (Aurora debug port timing)

• Specification change: t_REFCLK(Reference clock frequency) max value is 1250 MHz

(was 1200)

• Specification change: OUI (Aurora lane unit interval) is now specified by data rate

• Characteristic vs. Requirement change: J_D(Transmit lane deterministic jitter) is “SR”

(was “CC”)

• Characteristic vs. Requirement change: J_T(Transmit lane total jitter) is “SR” (was “CC”)

Electrical characteristics—AC specifications—DSPI

Section 3.19.2, DSPI timing with CMOS and LVDS pads: Substantive changes to entire

section, including reclassification of content as:

• Table 51 (DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0,

CPHA = 0 or 1)

• Table 52 (DSPI CMOS master modified timing (full duplex and output only) –

MTFE = 1, CPHA = 0 or 1)

• Table 54 (DSPI LVDS slave timing – full duplex – modified transfer format

(MTFE = 0/1))

• Table 55 (DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or

ITSB = 1, CPOL = 0 or 1, continuous SCK clock,)

• Table 56 (DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or

ITSB = 1, CPOL = 0 or 1, continuous SCK clock^,)

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—AC specifications—Fast Ethernet Controller (FEC)

Section 3.16.3, “FEC timing

Table 58 (MII receive signal timing)

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

Table 59 (MII transmit signal timing)

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

• Footnote added to max and min values columns: “Output parameters are valid for

C_L= 25 pF, where C_Lis the external load to the device. The internal package

capacitance is accounted for, and does not need to be subtracted from the 25 pF

value.”

Table 60 (MII async inputs signal timing)

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

Table 61 (MII serial management channel timing):

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

Table 62 (RMII receive signal timing):

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

Table 63 (RMII transmit signal timing,):

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

• Specification change: REF_CLK to TXD[1:0], TX_EN valid max value is 16 ns (was 14)

• Added footnote 2 to value column “Output parameters are valid for CL = 25 pF, where

CL is the external load to the device. The internal package capacitance is accounted

for, and does not need to be subtracted from the 25 pF value.”

Electrical characteristics—AC specifications—FlexRay

Section 3.16.4, FlexRay timing

Table 64 (TxEN output characteristics):

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

Table 65 (TxD output characteristics^,):

• t_TR20-80specification for V_{DD_HV_IO}= 5.0 V ± 10%, Transmission line Z = 50 ohms,

t_delay= 1 ns, C_L= 10 pF, moved from Table 17 (VERY STRONG configuration output

buffer electrical characteristics)

• t_TR20-80specification combined with dCCTxD_RISE25+dCCTxD_FALL25specification.

Footnotes added for conditions. 3.3V specification added.

• Footnote added: “Specifications valid according to FlexRay EPL 3.0.1 standard with

20%-80% levels and a 10pF load at the end of a 50ohm, 1ns stripline. Please refer to

the Very Strong I/O pad specifications.“

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Electrical characteristics—AC specifications—FlexRay (con’t)

Table 66 (RxD input characteristics):

• New specification: dCCRxAsymAccept15 (Acceptance of asymmetry at receiving CC

with 15 pF load)

• New specification: dCCRxAsymAccept25 (Acceptance of asymmetry at receiving CC

with 25 pF load)

• Column added: SR/CC (system requirement or controller characteristic)

• Column added: Classification (parameters are guaranteed by design)

Electrical characteristics—AC specifications—PSI5

Section 3.19.6, PSI5 timing

Table 67 (PSI5 timing):

• Specification description for t_{MSG_DLY}changed to, “Delay from last bit of frame (CRC0)

to assertion of new message received interrupt“ (was, “Delay from last bit of frame (end

of idle time) ...”)

• Specification description for t_{MSG_JIT}changed to, “Delay jitter from last bit of frame

(CRC0) to assertion of new message received interrupt“ (was, “Delay from last bit of

frame (end of idle time) ...”)

• Maximum value for t_{SYNC_JIT}changed to ±(1 PSI5_1µs_CLK + 1 PBRIDGEn_CLK);

was 1 cycle

• Footnote 2 (“Measured in PSI5 1 MHz clock cycles (PSI5_1us_CLK on the device).”)

on the unit for t_{SYNC_JIT}deleted

• Classification change: t_{MSG_DLY}(Delay from last bit of frame (CRC0) to assertion of

new message received interrupt) is “D” (was “C”)

• Classification change: t_{SYNC_DLY}(Delay from internal sync pulse to sync pulse trigger

at the SDOUT_PSI5_n pin) is “D” (was “C”)

• Classification change: t_{MSG_JIT}(Delay jitter from last bit of frame (CRC0) to assertion

of new message received interrupt) is “D” (was “C”)

• Classification change: t_{SYNC_JIT}(Delay jitter from internal sync pulse to sync pulse

trigger at the SDOUT_PSI5_n pin) is “D” (was “C”)

Electrical characteristics—AC specifications—UART

Section 3.18.7, UART timing

• New

Electrical characteristics—AC specifications—EBI

Section 3.16.7, External Bus Interface (EBI) Timing:

• New

Package characteristics

• 292 MAPBGA case drawing Rev. A included.

• 416 TEPBGA case drawing Rev. 0 included.

Electrical characteristics—Thermal Characteristics

Table 74 (Thermal characteristics)

• This table consolidates what were formerly separate thermal specifications tables for

each package. All values have been updated.

MPC5777M Microcontroller Data Sheet, Rev. 6

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

2

4/2013

Ordering Information

Section 4, Ordering information:

• New

3

3/2014

Throughout

• Changed document ID to “MPC5777M.”

• Updated the “e200_z720n3” cores to “e200_z710n3” and the “e200_z719” core to

“e200_z709.”

• Removed references to the 292 MAPBGA and LFBGA292 packages.

• Editorial (non-technical) changes and improvements.

• Removed references to KGD and 165^oC ratings.

Introduction

Table 1 (Family comparison):

• SPC5744K column, ADC (SD) feature, changed “3” to “2”.

• MPC5777M column, removed 292 MAPBGA.

• Changed feature from “SIPI/LFAST⁷bus” to “Zipwire^(SIPI / LFAST⁷) Interprocessor

Communication Interface”.

• Removed “To be confirmed for final silicon” footnote from Local RAM row for

SPC5744K.

• Removed “Only on the I/O processor core” footnote from LSP row for all devices.

• Changed System SRAM for MPC5777M to “404 KB” (was 384 KB).

• Changed Flash memory for MPC5777M to “8640 KB” (was 7.9 MB).

• Changed DMA Nexus Class for SPC5744K, MPC5746M, and MPC5777M to “3+” (was

3).

• Changed GTM RAM for MPC5777M to “58 KB” (was 52 KB).

• Changed Interrupt Controller entry for MPC5777M to “727 sources” (was 930 sources).

• Removed “Integrated switch mode voltage regulator” row.

• Removed “Degraded performance below 4.0 V” footnote from 5 V value in External

power supplies row.

Figure 1 (Block diagram):

• Updated the “e200_z720n3” cores to “e200_z710n3” and the “e200_z719” core to

“e200_z709”.

Section 1.5, Feature overview

• Changed item describing main CPUs to “single issue” (was “dual issue).

• Changed item describing on-chip flash memory to “8640 KB” (was “8528 KB”).

• Removed FlexRay as an option for BAM serial port.

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Package pinouts and signal descriptions

Section 2.1, Package pinouts:

• Removed “292” from the first sentence.

• Removed figure “292-ball BGA production device pinout (top view)” and figure

“292-ball BGA production device pinout (bottom view)”.

Table 2 (Power supply and reference pins) and Table 3 (System pins):

• Removed the “292PD” and 292ED” BGA ball columns.

• V_{SS_LV}: Added K13 and K14 for 416PD/416ED. Added M15 and M16 for

512PD/512ED.

• V_{DD_LV_BD}: R1/R4 now applies only to 416ED (416PD changed to “—”). M13/N12 now

applies only to 512ED (512PD changed to “—”).

• Removed V_{DD_HV_OSC}row.

• Changed V_{DD_HV_JTAG}Description to "JTAG/Oscillator power supply."

• V_DDSTBY: removed "Input" from descripion.

• Significantly revised V_{SS_HV_ADV_S}, V_{DD_HV_ADV_S}, V_{SS_HV_ADV_D}, and

V_{DD_HV_ADV_D}rows. Added rows for V_{SS_HV_ADR_S}, V_{DD_HV_ADR_S}, V_{SS_HV_ADR_D}

V_{DD_HV_ADR_D}

,

.

Table 4 (LVDS pin descriptions):

• Changed title to “LVDS pin descriptions” (was “LVDSM”).

• Removed the “292 PD, 292 ED” BGA ball column.

• In the BGA ball (416 PD,416 ED) column, added ball locations.

• In the BGA ball (512 PD, 512 ED) column, added ball locations.

• Changed SIPI_TXP to P25 for 512BGA (was T25).

• DSPI 4: Changed SCK_N to G17 for 512BGA (was G18).

• DSPI 2: Changed SIN_P to G23 for 416BGA (was D17).

• DSPI 5: For SCK_P, changed PI[15] to PF[10], G26 to J24, and P22 to W24.

• DSPI 5: For SCK_N, changed PI[15] to PF[9], J23 to K23, and R22 to W25.

• Added another pair of SIN_P/SIN_N rows for DSPI_5.

Electrical characteristics—Absolute maximum ratings

Section 3.1, Introduction:

• Added V_{DD_HV_IO_FLEXE}and V_{DD_HV_IO_EBI}to list in supply pins note.

Table 7 (Parameter classifications):

• Changed Tag description for C classification to “Parameters are guaranteed. . .” (was

“Those parameters are achieved. . .”

• Changed Tag description for T classification to “Parameters are guaranteed. . .” (was

“Those parameters are achieved. . .”

Table 6 (Absolute maximum ratings):

• Changed V_SSto V_{SS_HV}

.

• Removed “V_SS– V_{SS_HV_ADV}” parameter row.

• Removed V_FERSrow.

• Removed “VFERS is a factory test supply pin . . .” footnote.

• V_{SS_HV_ADR}: Added "Reference to V_{SS_HV}" to Conditions field.

• Removed V_SS–V_{SS_HV_ADR_D}and V_SS–V_{SS_HV_ADR_S}rows.

• In V_{DD_HV_IO}footnote, added V_{DD_HV_IO_JTAG}to list of power supplies to which

V

_{DD_HV_IO}applies.

• In ADC grounds footnote, removed V_{SS_HV_ADV_D2}

• In ADC supplies footnote, changed V_{DD_HV_ADV}to V_{DD_HV_ADV_S}

• In ADC low and high references footnote, removed V_{SS_HV_ADR_D2}and

V_{DD_HV_ADR_D2}

.

• In ADC supplies footnote, removed V_{DD_HV_ADV_D2}

.

Table 7 (ESD ratings,):

• Changed ESD for Human Body Model (HBM) parameter classification to “T” (was SR)

MPC5777M Microcontroller Data Sheet, Rev. 6

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—Electromagnetic Compatibility (EMC)

• Removed section.

Electrical characteristics—Operating conditions

Table 8 (Device operating conditions):

• V_DDSTBYadded new footnote: The VDDSTBY pin should be connected to ground in

the application when the standby RAM feature is not used.'

• Added “Vin” specification, Min = 0V, Max = 5.5 V.

• V_{DD_HV_ADV}changed Min value from 3.6 V to 3.7 V.

• V_{DD_HV_IO_MAIN}, LVD400/HVD 600 disabled and LVD360/HVD600 disabled

conditions: changed max to “5.5 V” (was “5.9 V”).

• V_{DD_HV_IO_MAIN}: Added footnote "VDD_HV_IO_MAIN range limited to 4.75–5.25 V

when FERS = 1 to enable the fast erase time of the flash memory."

• V_{DD_HV_ADR_D}: Changed Typ value from V_{DD_HV_ADV}to V_{DD_HV_ADV_D}

• Changed "V_{DD_HV_ADR_D}–V_{DD_HV_ADV}" parameter to

"V_{DD_HV_ADR_D}–V_{DD_HV_ADV_D}."

.

• V_{SS_HV_ADR_D}: Changed V_{SS_HV_ADV}to V_{SS_HV_ADV_D}

• Changed "V_{SS_HV_ADR_D}–V_{SS_HV_ADV}" parameter to

"V_{SS_HV_ADR_D}–V_{SS_HV_ADV_D}."

.

• V_{DD_HV_ADR_S}: Added typ value of V_{DD_HV_ADV_S}

• Added V_{SS_HV_ADR_S}parameter.

• Changed "V_{DD_HV_ADR_S}–V_{DD_HV_ADV}" parameter to "V_{DD_HV_ADR_S}–V_{DD_HV_ADV_S}

"

• Changed "V_{SS_HV_ADR_S}–V_{SS_HV_ADV}" parameter to "V_{SS_HV_ADR_S}–V_{SS_HV_ADV_S}

• For V_{DD_HV_ADV}specification, changed parameter to “SARADC, SDADC,

Temperature Sensor, and Bandgap Reference supply voltage” (was SARADC and

SDADC). For LVD400 disabled and LVD360 disabled conditions, referenced new

"

footnote: “V_{DD_HV_ADV_S}is required to be between 4.5V and 5.5V to read to read the

internal Temp Sensor and Bandgap Reference.”

• Changed V_RAMPto V_{RAMP_LV}, and changed parameter to “slew rate on core power

supply pins”.

• Added V_{RAMP_HV}specification, parameter “Slew rate on HV power supply pins”, max

value 500 V/ms.

• Changed V_{DD_HV_IO_JTAG}, V_{DD_HV_IO_FLEX}, and V_{DD_HV_IO_EBI}values from 4.0 V Min

to 4.5 V Min, and changed “5.9 V” Max to “5.5 V” Max.

• Moved V_{REF_BG_T}, V_{REF_BG_TC}and V_{REF_BG_LR}specifications from ADC pin

specification table to Device operating conditions table.

• Removed footnote “Maximum frequency for the 292BGA is TBD, and may be lower

due to package thermal considerations.” from f_SYSspecification, Max value “300” MHz.

• V_{DD_HV_ADV}changed “LVD400 disabled” condition to “LVD360 disabled” for the

3.7V-5.9 V case.

• V_{DD_HV_IO_FLEXE}added specification.

• V_{STBY_BO}and V_{DD_LV_STBY_SW}removed from the Device operating conditions table

and added to the DC electrical specifications table.

• V_{por_rel}and V_{por_hys}specifications added.

• Removed V_FERSrow and associated footnote.

Table 9 (Emulation (buddy) device operating conditions):

• Changed V_{DD_LV_BD}minimum value from blank to “1.2” V.

• V_{DD_LV_BD}: Maximum changed to 1.365 V (was 1.32 V).

• Changed V_{RAMP_BD}to V_{RAMP_LV_BD}and added specification V_{RAMP_HV_BD.}

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—DC electrical specification

Table 10 (DC electrical specifications):

• Changed footnote 11, to “The standby RAM regulator current is present on the

VDDSTBY pin whenever a voltage is applied to the pin. This also applies to normal

operation where the RAM is powered by the VDD_LV supply. Connecting the

VDDSTBY pin to ground when not using the standby RAM feature will remove the

leakage current on the VDDSTBY pin.”

• Moved V_{REF_BG_T}, V_{REF_BG_TC}and V_{REF_BG_LR}specifications from ADC pin

specification table to DC electrical specifications table.

• Removed I_FERSrow.

• V_{STBY_BO}and V_{DD_LV_STBY_SW}removed from the Device operating conditions table

and added to the DC electrical specifications table.

• Changed I_{DD_LV}maximum value to 850 mA (was 910).

Electrical characteristics—DC electrical specification (con’t)

Table 10 (DC electrical specifications):

• Changed I_{DD_LV}maximum value to 850 mA (was 910).\

• I_{DD_LV_BD,}changed “250” to “290” mA.

• I_{DD_BD_STBY}, 150 ^oC condition, changed “120” to “230” mA.

• I_{DD_MAIN_CORE_AC}: Added footnote "There is an additional 25mA when FERS=1 to

enable the fast erase time of the flash memory."

• In VDD_HV_PMC availability footnote, changed “QFP” to “416 BGA” and “BGA” to “512

BGA.”

• Revised footnote “If Aurora and JTAGM/LFAST not used, V_{DD_LV_BD}current is reduced

by ~20mA.”

• Removed silicon characterization footnote.

Table 12 (I/O input DC electrical characteristics):

• V_DRFTAUTspecification, conditions column, added “4.5 V < V_{DD_HV_IO}< 5.5 V”.

• V_DRFTCMOSspecification, added 3.0 V < V_{DD_HV_IO}< 3.6 V and 4.5 V < V_{DD_HV_IO}

5.5 V conditions.

<

• I_LKGspecification, entire row revised.

• Changed footnote 6 “n the range 4.5 V < VD_{D_HV_IO}< 5.9 V.” to “in the range 4.5 V <

V_{DD_HV_IO}< 5.5 V.

• V_HYSAUTconditions column: replaced dash with 4.5 V < V_{DD_HV_IO}< 5.5 V.

• C_INrow, changed GPIO input pins conditions Max value from “10” to “7” pF and EBI

input pins Max value from “8” to “7” pF.

• I_{LKG_EBI}removed “Vin = 10%/90%” from parameter column.

Figure 18 (I/O output DC electrical characteristics definition): Replaced figure.

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—I/O pad specification

Table 13 (I/O pull-up/pull-down DC electrical characteristics):

• I_WPU, I_WPD: substantially revised these specifications.

Table 14,Table 15,Table 16,Table 17:

• Added footnote to “C” classification header: "Once device characterization is

correlated to production I/O testing, the test classification of output resistance

parameters may be subject to change in future revisions of this document."

• R_{OH_W}, R_{OL_W,}R_{OH_M,}R_{OL_M,}R_{OH_S,}R_{OL_S,}R_{OH_V,}R_{OL_V}: Changed classification to

C (was P).

• Removed all VSIO conditions (VSIO[VSIO_xx] = 1 and VSIO[VSIO_xx] = 0) from

conditions column and added footnote: “All V_{DD_HV_IO}conditions for 4.5 V to 5.9 V are

valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0 V to 3.6 V are valid for

VSIO[VSIO_xx] = 0.”

• Removed T_PHL/PLHspecification from WEAK, MEDIUM, and STRONG configuration

output buffer electrical characteristics.

• Removed characterization and validation footnotes (total 2) for each table.

Table 14, Table 15, Table 16:

• R_{OH_}, R_{OL_}, t_{TR_}: Changed 5.9 V conditions to 5.5 V.

Table 15,Table 16,Table 17:

• Added t_TPD10-90specification.

Table 16, Table 17:

• In footnotes, changed 5.9 V to 5.5 V.

Table 18 (EBI pad output electrical specification):

• Replaced this table “EBI output driver electrical characteristics” with new table “EBI pad

electrical specification”.

Table 19 (I/O consumption)

• I_{RMS_EBI}: In Conditions column, changed 66MHz references to 66.7MHz. Removed

C_DRV= 6 pF condition row.

• I_{DYN_EBI}: revised specification.

Electrical characteristics—I/O pad current specification

Section 3.7, I/O pad current specification: Changed the first note: from “In order to ensure

correct functionality for SENT, the sum of all pad usage ratio within the SENT segment

should remain below 50%.” to “In order to maintain the required input thresholds for the

SENT interface, the sum of all I/O pad output percent IR drop as defined in the I/O Signal

Description table, must be below 50 %. See the I/O Signal Description attachment.”

Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics

Table 20 (Reset electrical characteristics):

• |IWPU| parameter, changed Min value from “25” to “23” and Max value from “100” to “82”

uA.

• |IWPD| parameter, changed Min value from “25” to “40” and Max value from “100” to

“130” uA.

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—Oscillator and FMPLL

Section 3.12, Oscillator and FMPLL

• Updated text to reflect that there is one FMPLL on the chip.

Table 22 (PLL1 electrical characteristics)

• f_PLL1PHIparameter, changed Max freq from “200” MHz to “600” MHz.

• First footnote, changed “FXOSC” to “XOSC”.

Table 23 (External Oscillator electrical specifications):

• Added footnote to both V_IHEXTand V_ILEXTparameter column “Applies to an external

clock input and not to crystal mode”.

• Added footnote to V_ILEXTparameter column “This parameter is guaranteed by design

rather than 100% tested.”

• V_ILEXTparameter, changed “External Reference” to “External Clock Input”.

• Combined C_{S_XTAL}and C_{S_EXTAL}parameters into one specification C_{S_xtal}, updated

Min and Max values and removed the “BG292” condition.

Table 24 (Selectable load capacitance):

• Removed last 16 rows “10000” to “11111”.

• Changed footnote 2 from “Values in this table do not include 8 pF routing and ESD

structure on die and package trace capacitance.” to “Values in this table do not include

the die and package capacitances given by Cs_xtal/Cs_extal in Table 23 (External

Oscillator electrical specifications).”

• Table 25 (Internal RC Oscillator electrical specifications): f_{var_SW}parameter added

footnote “IRC software trimmed accuracy is performed either with the CMU_0 clock

monitor, using the XOSC as a reference or through the CCCU (CAN clock control Unit),

extracting reference clock from CAN master clock. Software trim must be repeated as

the device operating temperature varies in order to maintain the specified accuracy.”

Electrical characteristics—ADC specifications

Table 36 (ADC pin specification^,):

• I_{LK_INUD}, I_{LK_INUSD}, I_{LK_INREF}, I_{LK_INOUT}: Removed footnote “Leakage current is a

parameter potentially showing variation with process maturity. This table is based on

current process model, and will be validated when preliminary silicon data of ADC

modules and I/O module is available.”

• Parameter I_{LK_INOUT}description column, changed “MEDIUM” output buffer with

“GPIO” output buffer.

Table 27 (SARn ADC electrical specification):

• Added new condition for “V_PRECH” - “V_PRECH= V_{DD_HV_ADR}/2 T_J< 150 °C

CTRn[PRECHG] > 2”

• I_ADCREFLspecification: added V_{DD_HV_ADR_S}<= 5.5 V to all modes in condition

column.

• D_NL, “Differential non-linearity” parameter, conditions column, replaced “—” with

“VDD_HV_ADV > 4V, VDD_HV_ADR_S > 4V”.

• I_NL: Conditions column, first row, removed T_J< 150C and added 4.0V <

V_{DD_HV_ADV_S}< 5.5V. Conditions column, second row, removed T_J< 150C and added

V_{DD_HV_ADV_S}= 2V.

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—ADC specifications (con’t)

Table 28 (SDn ADC electrical specification):

• Removed the I_{LK_IN}specification from table.

• For SNR_DIFF150, SNR_DIFF333, and SNR_SE150specifications, added reference to “S/D

ADC is functional in the range 3.0 V < VDD_HV_ADR_D , 4.0 V. . .” footnote.

• Moved V_{REF_BG_T}, V_{REF_BG_TC}and V_{REF_BG_LR}specifications from ADC pin

specification table to Device operating table.

• Removed I_BGspecification as it is already provided in the DC electrical table.

• Maximum value of parameter “GAIN” changed from “16” to “15”

Table 28 (SDn ADC electrical specification):

• Changed footnote from “The ±1% passband ripple specification is equivalent to 20 *

log₁₀(0.99) = 0.87 dB.” to “The ±1% passband ripple specification is equivalent to 20

* log₁₀(0.99) = 0.087 dB.”

• Max value of _GROUPmodified for all values of OSR.

• t_{LATENCY, SETTLING}

t

and t_ODRECOVERY:“HPF = ON” and “HPF = OFF” conditions added.

New max values.

• Added SINAD and THD specifications.

• RESOLUTION specification, added footnote “When using a GAIN setting of 16, the

conversion result will always have a value of zero in the least significant bit. The gives

an effective resolution of 15 bits.”

• _GAINspecification, changed Max value from ”1” % to “1.5” %, “0.1” % to “5” mV, “0.25”

% to “7.5” mV, and “0.5 %” to 10” mV”.

• VOFFSETspecification, added 3 “After calibration” conditions, _{VDD_HV_ADR_D}< 5%



_{VDD_HV_ADV_D}< 10% T_J< 50 °C, Max value of “5” mV, _{VDD_HV_ADR_D}< 5%

_{VDD_HV_ADV_D}< 10% T_J< 100 °C, Max value of “7.5” mV and “After calibration”

conditions, _{VDD_HV_ADR_D}< 5% _{VDD_HV_ADV_D}< 10% T_J< 150 °C, Max value of

“10” mV.

• Changed all SNR specification “Unit”s from “dB” to “dBFS”.

• Changed SFDR specification “Unit” from “dB” to “dBc”.

• Z_INspecification, changed footnote to “Input impedance is valid over the full input

frequency range.Input impedance is calculated in megaohms by the formula

25.6/(Gain * f_{ADCD_M}).

• Common mode rejection ratio parameter changed symbol from “—” to “V_cmrr”.

• Anti-aliasing filter parameter, changed symbol “—” to “R_Caaf”.

• Stop band attenuation parameter, changed symbol “—” to “F_rolloff”.

• Changed footnote in 13 “full input range (specified by Vin)” to “full input frequency

range.”

• Changed in footnote 15 “0.873” dB to “0.087” dB.

• f_{ADCD_M}, changed “S/D clock 3(4)” to “S/D Modulator Input Clock” and replaced “—”

with “4” in Min column.

• f_{ADCD_S}changed “conversion rate'” to “output conversion rate”.

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Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—LFAST electrical specifications

Table 30 (LVDS pad startup and receiver electrical characteristics,):

• |_VI| specification, Differential input voltage parameter, added footnote 12 “The

LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to

ensure proper LFAST receive timing.”

Table 31 (LFAST transmitter electrical characteristics,):

• |_VOD|: removed the delta from symbol. Changed values to Min = 110, Typ = 171, Max

= 285 and removed the “+/-” from each value.

• t_TR: changed “(10%–90% of swing)” to “(absolute value of the differential output

voltage swing).”

Table 32 (MSC/DSPI LVDS transmitter electrical characteristics ,):

• |_VOD|: removed the delta from symbol. Changed values to Min = 150, Typ = 214, Max

= 400 and removed the “+/-” from each value.

• t_TR: Changed “(10%–90% of swing)” to “(absolute value of the differential output

voltage swing).”

Table 33 (LFAST PLL electrical characteristics):

• |_VI| specification, Differential input voltage parameter, added footnote 12 “The

LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to

ensure proper LFAST receive timing.”

Table 32 (MSC/DSPI LVDS transmitter electrical characteristics ,), Rise/Fall time

parameter:

• Changed “(10%–90% of swing)” to (absolute value of the differential output voltage

swing).

Table 33 (LFAST PLL electrical characteristics):

• Changed footnote 2, from “320” to “640” MHz frequency.

Electrical characteristics—Aurora LVDS electrical characteristics

Table 34 (Aurora LVDS electrical characteristics,):

• Removed V_{DD_HV_IO_BD}and V_{DD_LV}specifications as they are supplied in the device

operating conditions table.

• Changed “C_AC” specification name to “C_{ac_clk}”.

• Added specification “C_{ac_tx}”.

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Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—Power management: PMC, POR/LVD, sequencing

Figure 20 (Recommended supply pin circuits):

• For VDD_LV supply: Changed "nxClv" to "Clv."

Table 35 (Device power supply integration):

• C_{HV_IO}removed footnote.

• C_{HV_FLA}parameter, added footnote “Start-up time of the internal flash regulator from

release of the LVD360 is worst case 500 us. This is based on the typical CHV_FLA bulk

capacitance value.”

• C_LV: Changed the 3 for Bypass capacitance at pin to "Note3." Changed parameter

"Bypass capacitance at pin" to "Total bypass capacitance at external pin."

• Significantly revised C_{HV_PMC_BYP}, including changing spec name to C_{HV_PMC}, min

value to 2.2 µF (was 200 nF), and typ value to 4.7 µF (was “—”). Added footnote "For

noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF

between VDD_HV_PMC and VSS_HV."

Table 36 (Flash power supply):

• V_{DD_HV_FLA}, after trimming, Min value “3.2” changed to “3.15”. Added two notes.

• Removed I_{REG_FLA}specification.

Table 39 (Functional terminals state during power-up and reset):

• Changed “TRST” to “JCOMP.”

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Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—Device voltage monitoring electrical characteristics

Table 37 (Voltage monitor electrical characteristics):

• V_{PORUP_LV}Rising voltage (power up) condition, changed Min value “1040” to “1111”

and Max value “1180” to “1235”.

• V_{PORUP_LV}Falling voltage (power down) condition, changed Min value “960” to “1015”

and Max value “1100” to “1125”. Added footnote.

• V_LVD096“960” to “1015” and Max value “1100” to “1145”.

• V_LVD108changed Min value “1080” to “1125” and Max value “1140” to “1235”.

• V_LVD112changed Min value “1110” to “1175 and Max value “1180” to “1235”.

• V_HVD140changed Min value “1320” to “1385” and Max value “1440” to “1475”.

• Added new specification V_HVD145

.

• Added “HVD140 does not cause reset” at end of footnote “HVD is released after

t_VDRELEASEtemporization when lower threshold is crossed, HVD is asserted

t

_VDASSERTafter detection when upper threshold is crossed.”

• ]V_{PORUP_HV}, added footnote “the PMC supply also needs to be below 5472 mV

(untrimmed HVD600)”. Added new conditions: Rising voltage (power up) on IO JTAG,

and Osc supply, Rising voltage (power up) on ADC supply, and Hysteresis on

Power-up.

• V_{PORUP_HV}: Changed Falling voltage (power down) minimum value to “2850” (was

“2680”) and maximum value to 3162 (was “2980”).

• Revised Falling voltage footnote to read “Untrimmed LVD300_A will be asserted first

on power down” (was “Assume all LVDs except LVD270 on HV supplies disabled”).

• V_LVD295Rising voltage condition changed Max value “3100” to “3120”.

• V_LVD295Falling voltage condition changed Min value “2950” to “2920” and Max value

“3080” to “3100”.

• V_HVD360Rising voltage condition changed Min value “3420” to “3435” and Max value

“3610” to “3650”.

• V_HVD360Falling voltage condition changed Min value “3400” to “3415”.

Electrical characteristics—Flash memory electrical characteristics

Section 3.15, Flash memory electrical characteristics:

• This section completely revised.

Electrical characteristics—AC specifications—Debug and Calibration

Table 46 (JTAG pin AC electrical characteristics,):

• Added footnote “JTAG timing specified at V_{DD_HV_IO_JTAG}= 4.0 V to 5.5 V, and

maximum loading per pad type as specified in the I/O section of the data sheet.”

Table 47 (Nexus debug port timing)

• Footnote 1 changed to “Nexus timing specified at V_{DD_HV_IO_JTAG}= 4.0 V to 5.5 V, and

maximum loading per pad type as specified in the I/O section of the data sheet.”

• Changed “TDI” to “TDI/TDIC,” “TMS” to “TMS/TMSC,” and “TDO” to “TDO/TDOC.”

Figure 27 (Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing):

• Changed “TDI” to “TDI/TDIC,” “TMS” to “TMS/TMSC,” and “TDO” to “TDO/TDOC.”

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Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Electrical characteristics—AC specifications—Fast Ethernet Controller (FEC)

Table 61 (MII serial management channel timing):

• Added footnote to “Value” column: “Output parameters are valid for C_L= 25 pF, where

C_Lis the external load to the device. The internal package capacitance is accounted

for, and does not need to be subtracted from the 25 pF value.”

Table 63 (RMII transmit signal timing,):

• Added footnote to “Value” column “Output parameters are valid for C_L= 25 pF, where

C_Lis the external load to the device. The internal package capacitance is accounted

for, and does not need to be subtracted from the 25 pF value.”

• Added footnote to table title: “RMII timing is valid only up to a maximum of 150 ^oC

junction temperature.”

Electrical characteristics—AC specifications—FlexRay

Section 3.16.4, FlexRay timing:

• Removed reference to “292 MAPBGA”.

• Removed “ . . . and subject to change per the final timing analysis of the device” from

FlexRay specification sentence.

Table 66 (RxD input characteristics):

• Added footnote: “FlexRay RxD timing is valid for all input levels and hysteresis

disabled."

Electrical characteristics—AC specifications—EBI

Table 69 (Bus Operation Timing):

• Changed bus frequency in table heading to “66.7 MHz” (was “66 MHz”).

• Footnote 1, added "with DSC = 0b10 for ADDR/CTRL and DSC = 0b11 for

CLKOUT/DATA."

• Footnote 3, changed “[Clock Register TBD]” TO “CGM_SC_DC4 register”.

• Footnote 4, changed "VDDE" to "VDD_HV_IO_EBI or VDD_HV_IO_FLEXE."

• Spec 5, Characteristic column, added “ADDR[8:11]/WE[0:3]/BE[0:3],” “BDIP,” and

overbar on CS, OE, and TS. Changed "ADDR[8:31]" to "ADDR[12:31]."

• Spec 6, Characteristic column, added “ADDR[8:11]/WE[0:3]/BE[0:3]”, “BDIP,” overbar

on CS, OE, TS, and footnote “One wait state must be added to the output signal valid

delay for external writes.” Changed "ADD[8:31]" to "ADDR[12:31]."

• Spec 7, change Min value from “6.0” to “7.0” ns.

• Spec 8, Characteristic column, changed to “DATA[0:31]”.

• Removed cut 1 footnotes associated with output delay and setup time (total 2).

Figure 50 (D_CLKOUT Timing)

Figure 51 (Synchronous Output Timing)

Figure 52 (Synchronous Input Timing):

• Changed “VDDE” to “VDD_HV_IO_EBI” throughout.

Electrical characteristics—AC specifications—I2C

Section 3.16.8, “I2C timing:

New section.

Electrical characteristics—AC specifications—GPIO delay

Section 3.19.10, GPIO delay timing

• New section

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Table 76. Revision history (continued)

Description of changes

Revision

Date

3

3/2014

Package characteristics

Section 4, Package characteristics:

• Removed the “292 MAPBGAcase drawing” figures.

• Table 73 (Package case numbers): Removed the 292MAPBGA row.

Electrical characteristics—Thermal Characteristics

Table 74 (Thermal characteristics):

• Removed “292 Value” column.

Ordering Information

Table 75 (Orderable part number summary)

• Changed Freescale part numbers: 416 MAPBGA PD to TEPBGA

“PPC5777MK0MVU8A” (was PPC5777MQK0MVU8), 512 TEPBGA PD to

“PPC5777MK0MVA8A” (was PPC5777MQK0MVA8), 416 MAPBGA ED to TEPBGA

“PPC5777M2K0MVU8A” (was PPC5777M2K0MVU8), and 512 TEPBGA ED to

“PPC5777M2K0MVA8A” (was PPC5777M2K0MVA8)

• Removed KGD and Production PD rows.

• Removed “Flash/SRAM,” “Emulation RAM,” and “Frequency” columns.

Figure 61 (Product code structure):

• Package Code, added “VA = 512 TEPBGA Pb-Free”.

• Package Code, added “VU = 416 TEPBGA Pb-Free”.

• Miscellaneous, added “2 = Emulation Device”.

• Changed “Tape and Reel” to “Suffix” and added “A = cut2.0 revision”.

• In “Fab and Mask Revision” codes, changed “K = TBD” to “K = TSMC.”

4

9/2014

Throughout

• Removed parameter classifications from specification tables.

• Editorial changes and improvements.

Introduction

• In Figure 1 (Block diagram), added “LFAST & SIPI” block to 50 MHz concentrator.

• In Figure 2 (Periphery allocation), changed block to “2 x SIPI” (was “SIPI_0)” and

removed double arrow on its right side.

Electrical characteristics—Operating conditions

• Extensive revisions to Table 8 (Device operating conditions).

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Table 76. Revision history (continued)

Description of changes

Revision

Date

4

9/2014

Electrical characteristics—DC electrical specification

• In Section 3.1, Introduction, added the following to note text: "V_{DD_HV_ADV}refers to

ADC supply pins V_{DD_HV_ADV_S}and V_{DD_HV_ADV_D}. V_{DD_HV_ADR}refers to ADC

reference pins V_{DD_HV_ADR_S}and V_{DD_HV_ADR_D}. V_{SS_HV_ADV}refers to ADC ground

pins V_{SS_HV_ADV_S}and V_{SS_HV_ADV_D}. V_{SS_HV_ADR}refers to ADC reference pins

V_{SS_HV_ADR_S}and V_{SS_HV_ADR_D}."

• In Table 10 (DC electrical specifications), changed I_{DD_HV_PMC}maximum for PMC only

condition (was 5 mA, is 25 mA). Added “This includes PMC consumption, LFAST PLL

regulator current, and Nwell bias regulator current” to footnote associated with this

value.

• In Table 10 (DC electrical specifications), changed I_{DD_LV}maximum to 1140 mA (was

600 mA) and added “V_{DD_LV}= 1.325 V” to conditions.

• In Table 10 (DC electrical specifications), added I_{DDAPP_LV}specification.

• In Table 10 (DC electrical specifications), changed the conditions for I_{DDSTBY_RAM}and

I_{DDSTBY_REG}(were “...to 6 V...”, are “...to 5.5 V...”).

• In Table 10 (DC electrical specifications), I_{DDSTBY_RAM}specification: changed max

value for 40°C condition to 60 µA (was 40). Changed max value for 85°C condition to

100 µA (was 60).

• In Table 10 (DC electrical specifications), V_{STBY_BO}specification: changed min value

to 0.9 V (was 0.8).

Electrical characteristics—I/O pad current specification

• Table 12 (I/O input DC electrical characteristics), Table 13 (I/O pull-up/pull-down DC

electrical characteristics), Table 14 (WEAK configuration output buffer electrical

characteristics), Table 15 (MEDIUM configuration output buffer electrical

characteristics), Table 16 (STRONG configuration output buffer electrical

characteristics), Table 17 (VERY STRONG configuration output buffer electrical

characteristics), Table 19 (I/O consumption) added the following footnote to Conditions

heading: “During power up operation, the minimum required voltage to come out of

reset state is determined by the V_{PORUP_HV}monitor, which is defined in the voltage

monitor electrical characterstics table. Note that the V_{PORUP_HV}monitor is connected

to the V_{DD_HV_IO_MAIN0}physical I/O segment.”

• Table 12 (I/O input DC electrical characteristics): V_HYSTTLspecification: changed min

value to 0.275 (was 0.3). V_HYSAUTspecification: changed min value to 0.4 (was 0.5).

• Table 12 (I/O input DC electrical characteristics), changed V_{IHCMOS_H}min value to

“0.70 * V_{DD_HV_IO}” (was 0.65 * V_{DD_HV_IO}).

• In Table 12 (I/O input DC electrical characteristics), changed V_IHAUTmin value to 3.9 V

(was 3.8).

• Table 12 (I/O input DC electrical characteristics), revised I_LKGand I_{LKG_EBI}rows.

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Table 76. Revision history (continued)

Description of changes

Revision

Date

4

9/2014

Electrical characteristics—I/O pad current specification

• Table 14 (WEAK configuration output buffer electrical characteristics), R_{OH_W}and

R_{OL_W}: changed min value to 517 (was 560) and max value to 1052 (was 1040).

• Table 15 (MEDIUM configuration output buffer electrical characteristics), R_{OH_M}and

R

_{OL_M}: changed min value to 135 (was 140).

• Table 16 (STRONG configuration output buffer electrical characteristics), R_{OH_S}and

R_{OL_S}: changed min value to 30 (was 35) and max value to 77 (was 65).

• Table 17 (VERY STRONG configuration output buffer electrical characteristics),

revised R_{OH_V}and R_{OL_V}conditions.

• Table 17 (VERY STRONG configuration output buffer electrical characteristics), R_{OH_V}

and R_{OL_V}: changed max values to 72 (was 60) and 90 (was 75).

• Table 18 (EBI pad output electrical specification), R_{OH_EBI_GPIO}and R_{OL_EBI_GPIO}

:

changed max value to 400 (was 260).

• In Table 18 (EBI pad output electrical specification): V_{IHCMOS_H_EBI}specification:

changed max value to “V_{DD_HV_IO_EBI}+ 0.3” (was “V_{DD_HV_IO}+ 0.3”). R_{OH_EBI_GPIO}

specification: changed condition to “4.5 V < V_{DD_HV_IO_EBI}< 5.5 V” (was “3.0 V <

V_{DD_HV_IO}< 3.6 V”). R_{OL_EBI_GPIO}specification: changed condition to “4.5 V <

V_{DD_HV_IO_EBI}< 5.5 V” (was “3.0 V < V_{DD_HV_IO}< 3.6 V”).

Electrical characteristics—Oscillator and FMPLL

• In Table 23 (External Oscillator electrical specifications), deleted the transconductance

specification (g_m).

Electrical characteristics—ADC specifications

• Table 26 (ADC pin specification), I_{LK_INUD}specification: changed T_J< 40 °C condition

max value to 50 nA (was 70). Changed T_J< 150 °C condition max value to 150 nA (was

220).

• In Table 27 (SARn ADC electrical specification): added condition rows for full and fast

precharge to t_ADCPRECH, revised condition entries for V_PRECH.

• In Table 28 (SDn ADC electrical specification), changed the max value for t_LATENCYat

HPF = OFF (was 2*_GROUP,, is _GROUP).

• In Table 28 (SDn ADC electrical specification), changed the max value for GAIN (was

15, is 16).

• Table 28 (SDn ADC electrical specification), SNR_SE150: changed GAIN=1 min value to

72 (was 74), GAIN=2 min value to 69 (was 71), GAIN=4 min value to 66 (was 68),

GAIN=8 min value to 63 (was 65), and GAIN=16 min value to 60 (was 62).

• Table 28 (SDn ADC electrical specification), _GROUPspecification: changed OSR = 75

max value to 696 Tclk (was 746), changed OSR = 96 max value to 946.5 Tclk (was

946.4).

• In Table 28 (SDn ADC electrical specification), added footnote to parameter column for

t_LATENCY

.

Electrical characteristics—Power management: PMC, POR/LVD, sequencing

• In Section 3.16, Power management: PMC, POR/LVD, sequencing, replaced PMC

operating conditions and external regulators supply voltage table with a cross

reference to Table 8 (Device operating conditions).

• In Table 35 (Device power supply integration), changed minimum VDD_LV external

capacitance footnote to “variation over voltage, temperature, and aging” (was

“variation over process, voltage, temperature, and aging.”)

• In Table 36 (Flash power supply), revised table footnotes and added new “After

trimming; 25°C < TJ  150°C” condition to V_{DD_HV_FLA}

.

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

4

9/2014

Electrical characteristics—Device voltage monitoring electrical characteristics

• In Table 37 (Voltage monitor electrical characteristics), revised the entries for V_LVD108

and V_LVD145

.

Electrical characteristics—Flash memory electrical characteristics

• Multiple changes throughout Section 3.15, Flash memory electrical characteristics.

Electrical characteristics—AC specifications—GPIO delay

• In Table 72, changed parameter to “Delay from SIUL2 MSCR register bit update to pad

function enable at the input of the I/O pad” (was “Delay from MSCR bit update to pad

function enable”).

Electrical characteristics—Thermal Characteristics

• Updated Table 74 (Thermal characteristics).

Ordering Information

• Revised Table 75 (Orderable part number summary).

Electrical characteristics—Absolute maximum ratings

5

6/2015

Table 6 (Absolute maximum ratings)

• V_{DD_LV_BD}: corrected footnote numbering.

• Revised footnote (“Allowed 1.38– 1.45 V...”) text to 1.38 (was 1.375). Revised footnote

(“1.32 – 1.38 V range...”) text to 1.38 (was 1.375) and “1.326 V at maximum” (was

“1.288 V at maximum”).

Electrical characteristics—Operating conditions

Table 8 (Device operating conditions)

• Consolidated duplicate footnotes throughout table.

• V_{DD_HV_ADV}: added footnote (“SAR ADC only...”) to LVD disabled conditions.

• Revised V_{DD_HV_ADR_D}row.

• Changed V_{RAMP_LV}max value to 100 V/mx (was 500).

• Revised footnote (“RAM data retention is guaranteed at a voltage...”) (was “RAM data

retention is not guaranteed below...”).

Table 9 (Emulation (buddy) device operating conditions)

• Changed V_{RAMP_LV_BD}max value to 100 V/ms (was 500).

Electrical characteristics—DC electrical specification

Table 10 (DC electrical specifications)

• I_{DD_MAIN_CORE_AC}: changed max value to 115 mA (was 105).

• I_{DD_CHKR_CORE_AC}: changed max value to 80 mA (was 45).

• I_{DDSTBY_REG}: changed max value to 50 µA (was 30).

• V_{STBY_BO}specification: changed minimum to no value (was 0.9 V) and maximum to

0.9 V (was no value) with footnote (“V_{STBY_BO}is the maximum voltage...”).

• V_{DD_LV_STBY_SW}: changed min value to 0.93 V (was 0.95).

Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics

Table 20 (Reset electrical characteristics)

• Changed V_IHmin value to 2.2 V (was 2.0).

• Changed W_FNMImax value to 15 ns (was 20).

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Table 76. Revision history (continued)

Description of changes

Revision

Date

5

6/2015

Electrical characteristics—I/O pad current specification

Replaced Figure 18 (I/O output DC electrical characteristics definition).

Table 12 (I/O input DC electrical characteristics)

• V_IHAUTspecification: changed min value to 3.8 V.

• V_HYSTTL: Changed min value to 0.250 V (was 0.275). Removed footnote (“Minimum

hysteresis...”) from min value.

Table 13 (I/O pull-up/pull-down DC electrical characteristics)

• Added “AUTO” and “CMOS” designations to conditions for |I_WPU| and |I_WPD|.

• |I_WPU| specification: changed final condition row to “V_IN= 0.35*V_{DD_HV_IO}” (was “V_IN

0.65*V_{DD_HV_IO}”).

=

Table 14 (WEAK configuration output buffer electrical characteristics)

• R_{OH_W}specification: changed min value to 520  (was 517).

• R_{OL_W}specification: changed min value to 520  (was 517).

Table 15 (MEDIUM configuration output buffer electrical characteristics), Table 16

(STRONG configuration output buffer electrical characteristics), and Table 17 (VERY

STRONG configuration output buffer electrical characteristics)

• Changed specification to t_TPD50-50and revised row.

Table 16 (STRONG configuration output buffer electrical characteristics)

• Added t_{SKEW_S} specification.

Table 17 (VERY STRONG configuration output buffer electrical characteristics)

• Added I_{DCMAX_VS}specification.

Table 18 (EBI pad output electrical specification)

• Removed all specifications in Input Specifications section and changed table title to

“EBI Pad Output Electrical Specifications.”

• t_{PD_EBI}: changed parameter to “50% – 50% threshold...” (was “50% - 10% 90%

threshold...”) and changed max value to 4.0 ns (was 5.5).

• R_{OH_EBI_GPIO}specification: change min value to 100  (was 150).

Electrical characteristics—Oscillator and FMPLL

Table 21 (PLL0 electrical characteristics)

• Added footnote (“f_PLL0INfrequency must be...”) to f_PLL0INparameter.

• Changed footnote text to “Noise on the V_{DD_LV}supply...” (was “VDD_LV noise due...”).

• Added footnote (“PLL jitter is guaranteed when...”) to PLL0PHISPJ|, PLL0PHI1SPJ|, and

^PLL0LTJspecifications.

• Added f_PLL0VCOFRspecification.

Table 22 (PLL1 electrical characteristics),

• Added f_PLL1VCOFRspecification.

Table 24 (Selectable load capacitance)

• Significant changes throughout table.

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Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

5

6/2015

Electrical characteristics—ADC specifications

In Table 27 (SARn ADC electrical specification)

• I_ADCREFHspecification: changed min value for Run mode t_conv 5 µs condition to 7 µA

(was 3.5). Changed max value for Power Down mode condition to 6 µA (was 1).

• I_{ADV_S}specification, Power Down mode: changed max value to 1.0 mA (was 0.04).

• INL and DNL rows: removed injection current footnote.

• TUE₁₂row: changed footnote text to “This parameter is guaranteed...” (was “TUE, INL,

and DNL are granted...”). Removed T_J< 150 °C, V_{DD_HV_ADV_S}> 4 V,

V_{DD_HV_ADR_S}> 4 V condition row.

In Table 28 (SDn ADC electrical specification)

• V_OFFSET: Changed parameter name to “Input Referred Offset Error” (was “Conversion

Offset”) and added footnote (“Conversion offset error must be...”).

• SNR_DIFF150, SNR_DIFF333, SNR_SE150: removed footnote (“SNR degraded by 3dB...”)

and changed conditions range to 4.5 (was 4.0).

• SNR_SE150specification: revised min values for each condition. Added footnote (“This

parameter is guaranteed...”).

• For first footnote “S/D ADC is functional in the range...” changed voltage range to

3.6 V–4.5 V (was 3.6 V < V_{DD_HV_ADV_D}< 4.0 V) and added “Degraded SNR value

based on simulation.”

• For second footnote “S/D ADC is functional in the range...” changed voltage range to

3.0 V–4.5 V and added “Degraded SNR value based on simulation.”

• V_cmrrspecification: changed min value to 54 dB (was 20 dB).

• _GROUPspecification: increased the max value for each condition by 3 Tclk.

• I_{ADR_D}specification: changed max value to 30 µA (was 20). Added “f_{ADCD_M}

=

14.4 MHz” to condition.

Electrical characteristics—LFAST electrical specifications

Table 30 (LVDS pad startup and receiver electrical characteristics,)

• Revised entire R_INspecification row.

Table 31 (LFAST transmitter electrical characteristics,)

• f_DATA: Changed max value to "312/320" (was 320) and added footnote.

Table 33 (LFAST PLL electrical characteristics)

• Changed ERR_REFand DC_REFparameter descriptions to “PLL input reference clock”

(was “PLL reference clock”).

Electrical characteristics—Power management: PMC, POR/LVD, sequencing

Table 36 (Flash power supply)

• Removed V_{DD_HV_PMC}row (this specification documented in Table 8 (Device

operating conditions).

Electrical characteristics—Flash memory electrical characteristics

• Added Section 3.15.7, Flash read wait state and address pipeline control settings.

Electrical characteristics—AC specifications—DSPI

• Substantial revisions to Section 3.16.2, DSPI timing with CMOS and LVDS pads.

Electrical characteristics—AC specifications—FlexRay

Table 66 (RxD input characteristics)

• Revised footnote (“FlexRay RxD timing is valid . . .”).

MPC5777M Microcontroller Data Sheet, Rev. 6

166

NXP Semiconductors

Document revision history

Table 76. Revision history (continued)

Description of changes

Revision

Date

5

6/2015

Ordering Information

Table 75 (Orderable part number summary)

• Revised ED footnote (“‘ED’ refers to . . .”).

6

6/2016

Introduction

Section 1.3, Device feature

• Changed the name of the section to Device feature.

• Table 1 (MPC5777M feature) Changed the name of the table to MPC5777M feature.

Figure 1

• Removed the 50 MHz from the concentrator box and added 50 MHz and 100 Mhz to

the connection arrows.

Electrical characteristics—I/O pad specification

Section 3.7, I/O pad current specification

• Added paragraph (In order to ensure device reliability....., and In order to ensure device

functionality....).

• Removed the entries I_{RMS_SEG}and I_{DYN_SEG}in Table 19 (I/O consumption).

Table 12 (I/O input DC electrical characteristics)

• V_HYSTTLspecification: Changed min value to 0.275 V (was 0.250 V)

Electrical characteristics—Oscillator and FMPLL

Table 25 (Internal RC Oscillator electrical specifications)

• Added f_TRIMspecification.

Electrical characteristics—ADC Specifications

Table 28 (SDn ADC electrical specification),

• Z_DIFF, Z_CMand V_INTCMspecifications added. R_BIASspecification has been updated.

Electrical characteristics—AC specifications—FlexRay

Table 66 (RxD input characteristics)

• Changed footnote (“FlexRay RxD timing is valid . . .”).

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors

167

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Document Number: MPC5777M

Rev. 6

06/2016


型号：	PPC5777MK0MVA8B
厂家：	NXP
描述：	Three main CPUs, single issue, 32-bit CPU core complexes
文件：	总168页 (文件大小：1592K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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