PPC5744PEK0MLQ9R [NXP]
32-bit MCU suitable for ISO26262 ASILD chassis and safety applications;
| 型号： | PPC5744PEK0MLQ9R |
| 厂家： | 
NXP |
| 描述： | 32-bit MCU suitable for ISO26262 ASILD chassis and safety applications |
| 文件： | 总115页 (文件大小：1776K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number MPC5744P
Rev. 6.1, 11/2017
NXP Semiconductors
Data Sheet: Technical Data
MPC5744P
MPC5744P Data Sheet
32-bit MCU suitable for ISO26262 ASIL-
D chassis and safety applications
Features
• This document provides electrical specifications, pin
assignments, and package diagram information for the
MPC5744P series of microcontroller units (MCUs).
For functional characteristics and the programming
model, see the MPC5744P Reference Manual.
• The MPC5744P microcontroller is based on the Power
Architecture® developed by NXP. It targets chassis
and safety applications and other applications requiring
a high Automotive Safety Integrity Level (ASIL). The
MPC5744P is a SafeAssure solution.
• Junction temperature: The upper limit is 150°C or
165°C depending on the device marking.
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Introduction.......................................................................................... 3
3.12 Main oscillator electrical characteristics................................... 69
3.13 PLLDIG electrical characteristics............................................. 72
3.14 16 MHz Internal RC Oscillator (IRCOSC) electrical
1.1 Features......................................................................................3
1.2 Block Diagram...........................................................................5
2 Pinouts..................................................................................................6
2.1 Package pinouts and ballmap.................................................... 6
2.2 Pin/ball descriptions ................................................................. 8
specifications............................................................................. 73
3.15 ADC electrical characteristics................................................... 74
3.16 Flash memory specifications..................................................... 77
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Pin/ball startup and reset states................................. 8
Power supply and reference voltage pins/balls.........9
System pins/balls.......................................................12
LVDS pins/balls........................................................13
Generic pins/balls......................................................14
Peripheral input muxing............................................43
3.16.1
3.16.2
3.16.3
Maximum junction temperature 150°C.....................77
Maximum junction temperature 165°C.....................80
Flash memory read wait-state and address-pipeline
control settings.......................................................... 84
3.17 SGEN electrical characteristics................................................. 85
3.18 RESET sequence duration.........................................................86
3.19 AC specifications.......................................................................86
3 Electrical characteristics.......................................................................55
3.1 Introduction............................................................................... 55
3.2 165°C junction temperature option........................................... 55
3.3 Absolute maximum ratings....................................................... 55
3.4 Recommended operating conditions......................................... 57
3.5 Thermal characteristics..............................................................58
3.19.1
Reset pad (EXT_POR, RESET) electrical
characteristics............................................................87
WKUP/NMI timing...................................................89
Debug/JTAG/Nexus/Aurora timing..........................89
External interrupt timing (IRQ pin).......................... 96
SPI timing................................................................. 97
LFAST...................................................................... 102
FlexRay..................................................................... 106
Ethernet switching specifications..............................109
3.19.2
3.19.3
3.19.4
3.19.5
3.19.6
3.19.7
3.19.8
3.5.1
General notes for specifications at maximum
junction temperature................................................. 59
3.6 Electromagnetic compatibility (EMC)...................................... 60
3.7 Electrostatic discharge (ESD) characteristics............................62
3.8 Voltage regulator electrical characteristics............................... 62
3.9 DC electrical characteristics......................................................65
3.10 Supply current characteristics....................................................67
3.11 Temperature sensor................................................................... 69
4 Obtaining package dimensions.............................................................111
5 Ordering information............................................................................112
6 Document revision history................................................................... 113
MPC5744P Data Sheet, Rev. 6.1, 11/2017
2
NXP Semiconductors
Introduction
1 Introduction
1.1 Features
The following table summarizes the features of the MPC5744P.
Table 1. MPC5744P feature summary
Feature
Details
CPU
Power Architecture
2 x e200z4 in delayed lock step
Architecture
Harvard
Execution speed
0 MHz to 200 MHz (+2% FM)
Embedded FPU
Yes
Core MPU
24 regions
No
Instruction Set PPC
Instruction Set VLE
Yes
Instruction cache
8 KB, EDC
4 KB, EDC
64 KB, ECC
Yes (16 regions)
Data cache
Data local memory
System MPU
Buses
Core bus
AHB, 32-bit address, 64-bit data, e2e ECC
32-bit address, 32-bit data
Internal periphery bus
Crossbar
Master x slave ports
4 x 5
Memory—see Table 2 for additional details
Code/data flash memory
2.5 MB, ECC, RWW
Supported with RWW
384 KB, ECC
Yes
Data flash memory
SRAM
Overlay access to SRAM from Flash Memory Controller
Modules
Interrupt controller
32 interrupt priority levels, 16 SW programmable interrupts
1 module with 4 channels
PIT
System Timer Module (STM)
1 module with 4 channels
Software Watchdog Timer (SWT)
Yes
eDMA
32 channels, in delayed lock step
1 module with 64 message buffer, dual channel
3 modules with 64 message buffer
2 modules
FlexRay
FlexCAN
LINFlexD (UART and LIN with DMA support)
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
3
Introduction
Table 1. MPC5744P feature summary (continued)
Feature
Details
Clockout
Yes
Fault Control and Collection Unit (FCCU)
Cross Triggering Unit (CTU)
eTimer
Yes
2 modules
3 modules with 6 channels
2 modules with 4 x (2+1) channels
FlexPWM
Analog-to-digital converter (ADC)
4 modules with 12-bit ADC, each with 16 channels (25
external channels including shared channels plus internal
channels)
Sine-wave generator (SGEN)
SPI
32 point
4 modules
As many as 8 chip selects
CRC Unit
Yes
SENT
2 modules with 2 channels
Interprocessor serial link interface (SIPI)
Junction temperature sensor
Digital I/Os
Yes
Yes (replicated module)
≥ 16
Yes
Yes
Yes
Peripheral register protection
Ethernet
Error Injection Module (EIM)
Supply
Device Power Supply
3.3 V with external ballast transistor
3.3 V with external 1.25 V low drop-out (LDO) regulator
3.15 V to 5.5 V
ADC Analog Reference voltage
Clocking
Phase Lock Loop (PLL)
Internal RC Oscillator
External Crystal Oscillator
Low power modes
HALT and STOP
1 x PLL and 1 coupled FMPLL
16 MHz
8 MHz to 40 MHz
Yes
Debug
Nexus
Level 3+, MDO and Aurora interface
Package
LQFP
144 pins, 0.5 mm pitch, 20 mm x 20 mm outline
MAPBGA
257 MAPBGA, 0.8 mm pitch, 14 mm x 14 mm outline
Temperature
Temperature range (junction)
Ambient temperature range (LQFP)
Ambient temperature range (BGA)
-40°C to +150°C, option for 165°C
-40°C to +125°C, 135°C option (with 165°C junction option)
-40°C to +125°C, 135°C option (with 165°C junction option)
MPC5744P Data Sheet, Rev. 6.1, 11/2017
4
NXP Semiconductors
Introduction
Table 2. Flash memory and SRAM sizes of MPC5744P, MPC5743P, MPC5742P, and
MPC5741P
Part number
Flash memory
SRAM
MPC5744P
2.5 MB
2.0 MB
1.5 MB
1.0 MB
384 KB
256 KB
192 KB
128 KB
MPC5743P
MPC5742P
MPC5741P
1.2 Block Diagram
The following figure is a top-level diagram that shows the functional organization of the
system.
Figure 1. System Block Diagram
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
5
Pinouts
2 Pinouts
2.1 Package pinouts and ballmap
The following figures show the LQFP pinout and the BGA ballmap.
Figure 2. 144LQFP pinout
MPC5744P Data Sheet, Rev. 6.1, 11/2017
6
NXP Semiconductors
Pinouts
Figure 3. 257MAPBGA ballmap
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
7
Pinouts
2.2 Pin/ball descriptions
The following sections provide signal descriptions and related information about the
functionality and configuration of the device. Note that this section is under development.
2.2.1 Pin/ball startup and reset states
The following table provides startup state and reset state information for device pins/
balls.
The startup state and subsequent states of the following pins/balls cannot be configured
by the user:
• JCOMP
• TMS
• TCK
• XTAL/EXTAL
• FCCU_F[0] and FCCU_F[1]
• EXT_POR_B
• RESET_B
The user can configure the state after reset of the following pins/balls by programming
the applicable MSCRs/IMCRs:
• GPIOs
• Analog inputs
• TDI
• TDO
• NMI_B
• FAB
• ABS[0]
• ABS[2]
Table 3. Pin/ball startup and reset states
Pin/ball
GPIOs
Analog inputs4
JCOMP (TRST)
TDI
Startup state1, 2
State during reset
hi-z
State after reset
hi-z
144LQFP
Note3
Note3
Note5
Note5
257MAPBGA
Note3
hi-z
hi-z
hi-z
hi-z
hi-z
hi-z
hi-z
hi-z
Note3
Note5
Note5
Note5
input, weak pull-down
input, weak pull-up
output, hi-z
input, weak pull-down
input, weak pull-up
output, hi-z
TDO
TMS6
Note5
Note5
input, weak pull-up
input, weak pull-up
Note5
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
8
NXP Semiconductors
Pinouts
Table 3. Pin/ball startup and reset states (continued)
Pin/ball
TCK6
Startup state1, 2
State during reset
input, weak pull-up
hi-z
State after reset
input, weak pull-up
hi-z
144LQFP
Note5
Note5
38
257MAPBGA
hi-z
hi-z
hi-z
hi-z
hi-z
hi-z
hi-z
hi-z
hi-z
hi-z
Note5
Note5
R2
XTAL/EXTAL
FCCU_F[0]6
FCCU_F[1]6
EXT_POR_B
RESET_B
NMI_B
input, hi-z
output/input, hi-z
input, hi-z
output/input, hi-z
141
C4
input, weak pull-down
input, weak pull-down
input, weak pull-up
input, weak pull-down
input, weak pull-down
input, weak pull-down
input, weak pull-down
input, weak pull-down
input,weak pull-up
input, weak pull-down
input, weak pull-down
input, weak pull-down
Note5
Note5
Note5
Note5
Note5
Note5
Note5
Note5
Note5
Note5
Note5
Note5
FAB
ABS[2]
ABS[0]
1. Startup state is exited when the core and high-voltage supplies reach minimum levels.
2. Pads marked “high impedance” for POR will be in either high-impedance or weak low drive state when VDD_LV_CORE is
off and HV_VDD_IO is below 1.5 V.
3. See Generic pins/balls.
4. Not all non-supply or reference pins on the device are explicitly defined in this table.
5. See System pins/balls.
6. This pin/ball is dedicated to and directly connected to a peripheral module pin.
2.2.2 Power supply and reference voltage pins/balls
Table 4. Power supply and reference voltage pins/balls
Supply
Package
257MAPBGA
Symbol
Type
Description
Low voltage power Supply
144LQFP
18
VDD_LV_COR
Power
F6
F7
39
70
F8
93
F9
131
135
F10
F11
F12
G6
G12
H6
H12
J6
J12
K6
K12
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
9
Pinouts
Table 4. Power supply and reference voltage pins/balls (continued)
Supply
Package
Symbol
Type
Description
144LQFP
257MAPBGA
L6
L12
M6
M7
M8
M9
M10
M11
M12
B1
VSS_LV_COR
Ground Low voltage ground. PLL Ground is also connected to low
voltage ground for core logic on 144LQFP (pin 35).
17
35
G7
G8
G9
G10
G11
H7
40
71
94
96
132
137
H8
H9
H10
H11
J7
J8
J9
J10
J11
K7
K8
K9
K10
K11
L7
L8
L9
L10
L11
P4
VDD_LV_PLL
VSS_LV_PLL
Power
Ground PLL low voltage Ground
Table continues on the next page...
PLL low voltage Supply
36
35
N4
MPC5744P Data Sheet, Rev. 6.1, 11/2017
10
NXP Semiconductors
Pinouts
Table 4. Power supply and reference voltage pins/balls (continued)
Supply
Package
257MAPBGA
Symbol
VDD_HV_IO
Type
Description
High voltage Power Supply for I/O
144LQFP
Power
6
21
A9
B2
72
B16
D8
91
126
D14
G2
M2
T2
T16
U14
A1
VSS_HV_IO
Ground High voltage Ground Supply for I/O
7
22
A2
90
A16
A17
B1
127
B9
B17
C3
C15
D9
H2
N2
R3
R15
T1
T17
U1
U2
U16
U17
U14
VDD_HV_PMU
VDD_HV_PMU_AUX
VDD_HV_OSC
VSS_HV_OSC
VDD_HV_FLA
VDD_HV_ADV
VSS_HV_ADV
Power
Power
PMU high voltage Supply
72
Power Supply for the oscillator
27
28
97
58
59
M1
P1
Ground Ground Supply for the oscillator
Power
Power
Power Supply and decoupling pin for flash memory
High voltage Supply for ADC, TSENS, SGEN (3.3 V)
H16
T10
U9
Ground High voltage Ground for ADC
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
11
Pinouts
Table 4. Power supply and reference voltage pins/balls (continued)
Supply
Package
Symbol
Type
Description
144LQFP
257MAPBGA
VDD_HV_ADRE0
VSS_HV_ADRE0
VDD_HV_ADRE1
VSS_HV_ADRE1
Supply
High voltage Supply for digital portion of ADC pads
Voltage reference of ADC/TSENS
50
R7
High voltage Supply for ADC0 pads and shared pads for
ADC0/1.
Ground High voltage Ground for digital portion of ADC pads
Voltage reference Ground of ADC/TSENS
51
56
57
T7
R9
T9
High voltage Ground for ADC0 pads and shared pads for
ADC0/1.
Supply
High voltage Supply for digital portion of ADC pads
Voltage reference of ADC/TSENS
High voltage Supply for ADC1 pads, shared pads for ADC1/3,
and shared pads for ADC2/3.
Ground High voltage Ground for digital portion of ADC pads
Voltage reference Ground of ADC/TSENS
High voltage Ground for ADC1 pads, shared pads for
ADC1/3, and shared pads for ADC2/3.
VDD_LV_LFAST
VSS_LV_LFAST
VDD_LV_NEXUS
VSS_LV_NEXUS
Supply
Ground LFAST PLL low voltage Ground
Supply Aurora LVDS Supply
Ground Aurora LVDS Ground
LFAST PLL low voltage Supply
—
—
—
—
N16
N17
J16
K16
2.2.3 System pins/balls
The following table contains information about system pin functions for the devices.
Table 5. System pins/balls
Symbol
NMI_B
Type
Input
Output
Input
Input
Input
Input
Input
Input
Input
Output
Description
Non-maskable Interrupt
144LQFP
1
257MAPBGA
E4
N1
XTAL
Output of the oscillator amplifier circuit
Crystal oscillator input/external clock input
Functional Reset
29
EXTAL
30
R1
RESET_B
EXT_POR_B
VPP_TEST1
JCOMP
TCK
31
P2
External Power On Reset
SoC Test Mode
130
107
123
88
D6
D15
A6
JTAGC, JTAG Compliance Enable
JTAGC, Test Clock Input
JTAGC, Test Mode Select
JTAGC, Test Data Out
H17
H15
G14
TMS
87
TDO
89
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
12
NXP Semiconductors
Pinouts
Table 5. System pins/balls (continued)
Symbol
Type
Input
Description
144LQFP
257MAPBGA
TDI
JTAGC, Test Data Input
86
9
J17
G1
MDO[0]
Output
NEXUS, Message data out pins; reflects the state of
the internal power on reset signal until RESET is
negated
MDO[3:1]
EVTO
Output
Output
Input
NEXUS, Message data out pins
NEXUS, Event Out Pin
4,5,8
24
E1, F1, E2
K2
EVTI
NEXUS, Event In Pin
25
L2
MCKO
Output
Output
Output
NEXUS, Message clock out pin
NEXUS, Message Start/End out pin
NEXUS, Read/Write Transfer completed
19
J4
MSEO[1:0]
RDY_B
20, 23
—
J3, K3
J2
16
K1
BCTRL
Output
--
Base control signal of external npn ballast
FSL Factory Test2
69
R13
J[11], J[10]
—
L17, K17
1. VPP_TEST must be connected to ground.
2. Do not connect on the board.
2.2.4 LVDS pins/balls
The following tables contain information on LVDS pin functions for the devices.
Table 6. SIPI LFAST LVDS pin descriptions
Functional
block
Port pin
I[5]
Signal
Signal description
Direction
257MAPBGA
N15
SIPI LFAST1, 2
LFAST_TX SIPI/ LFAST, LVDS Transmit Negative Terminal
N
O
O
I
C[12]3
I[6]
LFAST_TX SIPI/ LFAST, LVDS Transmit Positive Terminal
P
M14
LFAST_RX SIPI/ LFAST, LVDS Receive Negative Terminal
N
M15
G[7]3
LFAST_RX SIPI/ LFAST, LVDS Receive Positive Terminal
P
I
M16
1. DRCLK and TCK/DRCLK usage for SIPI LFAST are described in the reference manual's SIPI LFAST chapters.
2. For the MSCR SSS value of the port pin, see Table 1.
3. The 144LQFP package has G[7] and C[12] but no SIPI LFAST functionality.
CAUTION
SIPI LFAST pins are muxed with GPIOs. Do not use GPIO and
SIPI LFAST functionality in parallel.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
13
Pinouts
Table 7. Aurora LVDS pin descriptions
Functional block
Pad
Signal
Signal description
Direction
257MAPBGA1
Nexus Aurora High
Speed Trace
G[12]
TX0P
Nexus Aurora High Speed Trace Lane 0,
LVDS Positive Terminal
O
H14
G[13]
G[14]
G[15]
H[0]
TX0N
TX1P
TX1N
CLKP
CLKN
Nexus Aurora High Speed Trace Lane 0,
LVDS Negative Terminal
O
O
O
I
J14
L15
K14
K15
J15
Nexus Aurora High Speed Trace Lane 1,
LVDS Positive Terminal
Nexus Aurora High Speed Trace Lane 1,
LVDS Negative Terminal
Nexus Aurora High Speed Trace Clock,
LVDS Positive Terminal
H[1]
Nexus Aurora High Speed Trace Clock,
LVDS Negative Terminal
I
1. Nexus Aurora High Speed Trace is available only on the 257MAPBGA.
2.2.5 Generic pins/balls
The I/O signal descriptions for the device are in the following table. It contains the port
definition, multiplexing, direction, pad type, and package pin/ball numbers for each I/O
pin on the device.
MSCR registers are used for alternative (ALT) mode selection and programming of pad
control options.
IMCR registers are used to configure input muxing by peripheral. See Peripheral input
muxing for details.
For the pins which have Nexus functionality muxed with GPIO or other functions, the
Nexus functionality of such pins is automatically set when the Nexus tool is connected to
the device. The value in MSCR register may have value that does not correspond to
Nexus functionality.
Table 8. Pin muxing
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
A[0]
MSCR[0]
0000
GPIO[0]
SIUL2-GPIO[0] General Purpose IO A[0]
I/O
73
P12
(Default)2
0001
ETC0
SCK
eTimer_0
DSPI2
eTimer_0 Input/Output Data
Channel 0
I/O
I/O
0010
DSPI 2 Input/Output Serial
Clock
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
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NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0011-1111
0001
—
Reserved
—
—
IMCR[48]
IMCR[59]
IMCR[173]
MSCR[1]
SCK
DSPI2
DSPI 2 Input Serial Clock
I
0010
ETC0
eTimer_0
SIUL2
eTimer_0 Input Data Channel 0 I
0001
REQ0
GPIO[1]
SIUL2 External Interrupt 0
I
A[1]
0000
SIUL2-GPIO[1] General Purpose IO A[1]
I/O
74
T14
(Default)
0001
ETC1
eTimer_0
eTimer_0 Input/Output Data
Channel 1
I/O
0010
SOUT
—
DSPI2
DSPI 2 Serial Data Out
—
O
0011-1111
0010
Reserved
eTimer_0
SIUL2
—
IMCR[60]
ETC1
REQ1
eTimer_0 Input Data Channel 1 I
IMCR[174]
0001
SIUL2 External Interrupt
Source 1
I
A[2]
MSCR[2]
0000
(Default)
GPIO[2]
ETC2
SIUL2-GPIO[2] General Purpose IO A[2]
I/O
I/O
—
84
L14
0001
eTimer_0
eTimer_0 Input/Output Data
Channel 2
0010
0011
—
Reserved
—
A3
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 3
0100-1111
—
Reserved
MC_RGM
—
—
I
IMCR[169]
0000
ABS0
RGM external boot mode 1
(Default)
IMCR[47]
IMCR[61]
IMCR[97]
IMCR[175]
0010
0010
0001
0001
SIN
DSPI2
DSPI 2 Serial Data Input
I
ETC2
A3
eTimer_0
FlexPWM_0
SIUL2
eTimer_0 Input Data Channel 2 I
FlexPWM_0 Channel A Input 3
I
I
REQ2
SIUL2 External Interrupt
Source 2
A[3]
MSCR[3]
0000
(Default)
GPIO[3]
ETC3
CS0
SIUL2-GPIO[3] General Purpose IO A[3]
I/O
I/O
92
G15
0001
eTimer_0
DSPI2
eTimer_0 Input/Output Data
Channel 3
0010
DSPI 2 Peripheral Chip Select I/O
0
0011
B3
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 3
0100-1111
—
Reserved
MC_RGM
—
—
I
IMCR[171]
IMCR[62]
0000
ABS2
RGM external boot mode 2
(Default)
0010
ETC3
eTimer_0
eTimer_0 Input Data Channel 3 I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
15
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
IMCR[49]
0001
CS0
B3
DSPI2
DSPI 2 Peripheral Chip Select
0
I
IMCR[98]
0001
0001
FlexPWM_0
SIUL2
FlexPWM_0 Channel B Input 3
I
I
IMCR[176]
REQ3
GPIO[4]
ETC0
CS1
SIUL2 External Interrupt
Source 3
A[4]
MSCR[4]
0000
(Default)
SIUL2-GPIO[4] General Purpose IO A[4]
I/O
I/O
O
108 D16
0001
0010
0011
0100
eTimer_1
DSPI2
eTimer_1 Input/Output Data
Channel 0
DSPI 2 Peripheral Chip Select
1
ETC4
A2
eTimer_0
FlexPWM_1
eTimer_0 Input/Output Data
Channel 4
I/O
FlexPWM_1 Channel A Input/ I/O
Output 2
0101-1111
0001
—
Reserved
FlexPWM_1
SIUL2
—
—
IMCR[112]
IMCR[177]
A2
FlexPWM_1 Channel A Input 2
I
I
0001
REQ4
SIUL2 External Interrupt
Source 4
IMCR[172]
0000
(Default)
FAB
MC_RGM
RGM Force Alternate Boot
Mode
I
IMCR[65]
IMCR[63]
MSCR[5]
0001
0011
ETC0
eTimer_1
eTimer_0
eTimer_1 Input Data Channel 0 I
eTimer_0 Input Data Channel 4 I
ETC4
A[5]
0000
GPIO[5]
SIUL2-GPIO[5] General Purpose IO A[5]
I/O
14
H4
(Default)
0001
0010
0011
CS0
DSPI1
DSPI 1 Peripheral Chip Select I/O
0
ETC5
CS7
eTimer_1
DSPI0
eTimer_1 Input/Output Data
Channel 5
I/O
DSPI 0 Peripheral Chip Select
7
O
0100-1111
0001
—
Reserved
eTimer_1
SIUL2
—
—
IMCR[70]
ETC5
REQ5
eTimer_1 Input Data Channel 5 I
IMCR[178]
0001
SIUL2 External Interrupt
Source 5
I
A[6]
MSCR[6]
0000
(Default)
GPIO[6]
SCK
SIUL2-GPIO[6] General Purpose IO A[6]
I/O
I/O
I/O
—
2
D1
0001
DSPI1
DSPI 1 Input/Output Serial
Clock
0010
ETC2
—
eTimer_2
eTimer_2 Input/Output Data
Channel 2
0011-1111
Reserved
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
16
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
IMCR[73]
0001
0001
ETC2
eTimer_2
SIUL2
eTimer_2 Input Data Channel 2 I
IMCR[179]
REQ6
SIUL2 External Interrupt
Source 6
I
A[7]
MSCR[7]
0000
GPIO[7]
SIUL2-GPIO[7] General Purpose IO A[7]
I/O
10
G4
(Default)
0001
0010
SOUT
ETC3
DSPI1
DSPI 1 Serial Data Out
O
eTimer_2
eTimer_2 Input/Output Data
Channel 3
I/O
0011-1111
0001
—
Reserved
eTimer_2
SIUL2
—
—
IMCR[74]
ETC3
REQ7
eTimer_2 Input Data Channel 3 I
IMCR[180]
0001
SIUL2 External Interrupt
Source 7
I
A[8]
MSCR[8]
0000
GPIO[8]
SIUL2-GPIO[8] General Purpose IO A[8]
I/O
12
H1
(Default)
0001
0010
—
Reserved
eTimer_2
—
—
ETC4
eTimer_2 Input/Output Data
Channel 4
I/O
0011-1111
0001
—
Reserved
DSPI1
—
—
I
IMCR[44]
IMCR[75]
IMCR[181]
SIN
DSPI 1 Serial Data Input
0001
ETC4
REQ8
eTimer_2
SIUL2
eTimer_2 Input Data Channel 4 I
0001
SIUL2 External Interrupt
Source 8
I
A[9]
MSCR[9]
0000
(Default)
GPIO[9]
CS1
SIUL2-GPIO[9] General Purpose IO A[9]
I/O
O
134
A4
0001
0010
0011
DSPI2
DSPI 2 Peripheral Chip Select
1
ETC5
B3
eTimer_2
FlexPWM_0
eTimer_2 Input/Output Data
Channel 5
I/O
FlexPWM_0 Channel B Input/ I/O
Output 3
0100-1111
0001
—
Reserved
eTimer_2
FlexPWM_0
FlexPWM_0
SENT_0
—
—
IMCR[76]
IMCR[98]
IMCR[83]
IMCR[206]
ETC5
eTimer_2 Input Data Channel 5 I
0010
B3
FlexPWM_0 Channel B Input 3
FlexPWM_0 Fault Input 0
SENT 0 Receiver channel 1
General Purpose IO A[10]
I
0001
FAULT0
SENT_RX[1]
GPIO[10]
I
0011
I
A[10] MSCR[10]
0000
SIUL2-
I/O
118 B11
(Default)
GPIO[10]
0001
0010
CS0
B0
DSPI2
DSPI 2 Peripheral Chip Select
0
O
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 0
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
17
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0011
X2
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 2
I/O
0100-1111
0010
—
Reserved
DSPI2
—
—
IMCR[49]
CS0
DSPI 2 Peripheral Chip Select I/O
0
IMCR[89]
IMCR[96]
IMCR[182]
0001
0001
0001
B0
X2
FlexPWM_0
FlexPWM_0
SIUL2
FlexPWM_0 Channel B Input 0
FlexPWM_0 Auxiliary Input 2
I
I
I
REQ9
SIUL2 External Interrupt
Source 9
IMCR[214]
0011
SENT_RX[1]
GPIO[11]
SENT_1
SENT 1 Receiver channel 1
General Purpose IO A[11]
I
A[11] MSCR[11]
0000
SIUL2-
I/O
120 D10
(Default)
GPIO[11]
0001
0010
0011
SCK
A0
DSPI2
DSPI 2 Input/Output Serial
Clock
I/O
FlexPWM_0
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 0
A2
FlexPWM_0 Channel A Input/ I/O
Output 2
0100-1111
0010
—
Reserved
DSPI2
—
—
IMCR[48]
IMCR[88]
IMCR[94]
IMCR[183]
SCK
A0
DSPI 2 Input Serial Clock
FlexPWM_0 Channel A Input 0
FlexPWM_0 Channel A Input 2
I
I
I
I
0001
FlexPWM_0
FlexPWM_0
SIUL2
0001
A2
0001
REQ10
SIUL2 External Interrupt
Source 10
A[12] MSCR[12]
0000
(Default)
GPIO[12]
SIUL2-
GPIO[12]
General Purpose IO A[12]
I/O
O
122
D7
0001
0010
SOUT
A2
DSPI2
DSPI 2 Serial Data Out
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 2
0011
B2
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 2
0100-1111
0010
—
Reserved
FlexPWM_0
FlexPWM_0
SIUL2
—
—
IMCR[94]
IMCR[95]
IMCR[184]
A2
FlexPWM_0 Channel A Input 2
FlexPWM_0 Channel B Input 2
I
I
I
0001
B2
0001
REQ11
SIUL2 External Interrupt
Source 11
A[13] MSCR[13]
0000
(Default)
GPIO[13]
SIUL2-
GPIO[13]
General Purpose IO A[13]
I/O
—
136
C5
0001
0010
—
Reserved
—
B2
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 2
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
18
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0011-1111
0010
—
Reserved
—
—
IMCR[83]
IMCR[95]
IMCR[47]
IMCR[185]
FAULT0
B2
FlexPWM_0
FlexPWM_0
DSPI2
FlexPWM_0 Fault Input 0
FlexPWM_0 Channel B Input 2
DSPI 2 Serial Data Input
I
I
I
I
0010
0001
SIN
0001
REQ12
SIUL2
SIUL2 External Interrupt
Source 12
A[14] MSCR[14]
0000
GPIO[14]
SIUL2-
General Purpose IO A[14]
I/O
143
A3
(Default)
GPIO[14]
0001
0010
TXD
CAN1
CAN 1 Transmit Pin
O
ETC4
eTimer_1
eTimer_1 Input/Output Data
Channel 4
I/O
0011-1111
0001
—
Reserved
eTimer_1
SIUL2
—
—
IMCR[69]
ETC4
REQ13
eTimer_1 Input Data Channel 4 I
IMCR[186]
0001
SIUL2 External Interrupt
Source 13
I
A[15] MSCR[15]
0000
GPIO[15]
SIUL2-
General Purpose IO A[15]
I/O
144
D3
(Default)
GPIO[15]
0001
0010
—
Reserved
eTimer_1
—
—
ETC5
eTimer_1 Input/Output Data
Channel 5
I/O
0011-1111
0001
—
Reserved
CAN0
—
—
IMCR[32]
IMCR[33]
IMCR[70]
IMCR[187]
RXD
RXD
ETC5
REQ14
CAN 0 Receive Pin
CAN 1 Receive Pin
I
I
0001
CAN1
0010
eTimer_1
SIUL2
eTimer_1 Input Data Channel 5 I
0001
SIUL2 External Interrupt
Source 14
I
B[0]
MSCR[16]
0000
GPIO[16]
SIUL2-
General Purpose IO B[0]
I/O
109 C16
(Default)
GPIO[16]
0001
0010
TXD
CAN0
CAN 0 Transmit Pin
O
ETC2
eTimer_1
eTimer_1 Input/Output Data
Channel 2
I/O
0011
DEBUG0
—
SSCM
SSCM Debug Output 0
—
O
0100-1111
0001
Reserved
eTimer_1
SIUL2
—
IMCR[67]
ETC2
REQ15
eTimer_1 Input Data Channel 2 I
IMCR[188]
0001
SIUL2 External Interrupt
Source 15
I
B[1]
MSCR[17]
0000
GPIO[17]
SIUL2-
General Purpose IO B[1]
I/O
110 C14
(Default)
GPIO[17]
0001
0010
—
Reserved
eTimer_1
—
—
ETC3
eTimer_1 Input/Output Data
Channel 3
I/O
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
19
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0011
DEBUG1
SSCM
SSCM Debug Output 1
—
O
0100-1111
0010
—
Reserved
CAN0
—
IMCR[32]
IMCR[33]
IMCR[68]
IMCR[189]
RXD
RXD
ETC3
REQ16
CAN 0 Receive Pin
CAN 1 Receive Pin
I
I
0010
CAN1
0001
eTimer_1
SIUL2
eTimer_1 Input Data Channel 3 I
0001
SIUL2 External Interrupt
Source 16
I
B[2]
MSCR[18]
0000
GPIO[18]
SIUL2-
General Purpose IO B[2]
I/O
114 C12
(Default)
GPIO[18]
0001
0010
TXD
CS4
LIN0
LINFlexD 0 Transmit Pin
O
O
DSPI0
DSPI 0 Peripheral Chip Select
4
0011
DEBUG2
—
SSCM
SSCM Debug Output 2
—
O
—
I
0100-1111
0001
Reserved
SIUL2
IMCR[190]
MSCR[19]
REQ17
SIUL2 External Interrupt
Source 17
B[3]
0000
GPIO[19]
SIUL2-
General Purpose IO B[3]
I/O
116 B12
(Default)
GPIO[19]
0001
0010
—
Reserved
DSPI0
—
—
O
CS5
DSPI 0 Peripheral Chip Select
5
0011
0100-1111
0001
0
DEBUG3
—
SSCM
Reserved
LIN0
SSCM Debug Output 3
—
O
—
I
IMCR[165]
MSCR[20]
RXD
LIN 0 Receive Pin
General Purpose IO B[4]
B[4]
B[5]
GPIO[20]
SIUL2-
GPIO[20]
I/O
89
86
G14
J17
0001
(Default)
TDO
NPC_HNDSHK NPC_HNDSHK Test Data Out
(TDO)
O
0010-1111
—
Reserved
—
—
MSCR[21]
MSCR[22]
0000
(Default)
GPIO[21]
SIUL2-
GPIO[21]
JTAGC Test Data In (TDI)3
I/O
General Purpose IO B[5]
0001
CS7
DSPI0
DSPI 0 Peripheral Chip Select
7
O
0010-1111
—
Reserved
—
—
B[6]
0000
GPIO[22]
SIUL2-
General Purpose IO B[6]
I/O
138
B5
(Default)
GPIO[22]
0001
CLK_OUT
CS2
MC_CGM
CGM Clock out for off-chip use
and observation
O
O
—
0010
DSPI2
DSPI 2 Peripheral Chip Select
2
0011-1111
—
Reserved
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
20
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
IMCR[191]
MSCR[23]
0001
REQ18
SIUL2
SIUL2 External Interrupt
Source 18
I
I
B[7]
0000
(Default)
GPI[23]4
SIUL2-GPI[23] General Purpose Input B[7]
43
47
R5
P7
ADC0_AN[0]
0001
0010-1111
0010
0
—
Reserved
Reserved
LIN0
—
—
—
I
—
—
IMCR[165]
MSCR[24]
RXD
GPI[24]4
ADC0_AN[1]
LIN 0 Receive Pin
B[8]
B[9]
SIUL2-GPI[24] General Purpose Input B[8]
I
0001
—
Reserved
Reserved
eTimer_0
—
—
—
—
0010-1111
0001
—
IMCR[64]
MSCR[25]
ETC5
GPI[25]4
ADC0_ADC1_A
N[11]
eTimer_0 Input Data Channel 5 I
0000
(Default)
SIUL2-GPI[25] General Purpose Input B[9]
I
52
53
54
55
60
U7
R8
0001
—
—
GPI[26]4
ADC0_ADC1_A
N[12]
Reserved
Reserved
—
—
—
—
I
0010-1111
B[10] MSCR[26]
B[11] MSCR[27]
B[12] MSCR[28]
B[13] MSCR[29]
0000
(Default)
SIUL2-GPI[26] General Purpose Input B[10]
0001
—
—
GPI[27]4
ADC0_ADC1_A
N[13]
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
(Default)
SIUL2-GPI[27] General Purpose Input B[11]
T8
0001
—
—
GPI[28]4
ADC0_ADC1_A
N[14]
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
(Default)
SIUL2-GPI[28] General Purpose Input B[12]
U8
0001
—
—
GPI[29]4
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
SIUL2-GPI[29] General Purpose Input B[13]
R10
(Default)
ADC1_AN[0]
0001
—
Reserved
Reserved
LIN1
—
—
—
I
0010-1111
0001
—
—
IMCR[166]
RXD
LIN 1 Receive Pin
B[14] MSCR[30]
0000
GPI[30]4
SIUL2-GPI[30] General Purpose Input B[14]
I
64
P11
(Default)
ADC1_AN[1]
0001
—
—
Reserved
Reserved
—
—
—
—
0010-1111
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
21
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
IMCR[63]
0001
0001
ETC4
eTimer_0
SIUL2
eTimer_0 Input Data Channel 4 I
IMCR[192]
REQ19
SIUL2 External Interrupt
Source 19
I
B[15] MSCR[31]
0000
GPI[31]4
SIUL2-GPI[31] General Purpose Input B[15]
I
62
R11
(Default)
ADC1_AN[2]
0001
—
Reserved
Reserved
SIUL2
—
—
—
—
I
0010-1111
0001
—
IMCR[193]
REQ20
SIUL2 External Interrupt
Source 20
C[0]
C[1]
C[2]
C[4]
MSCR[32]
MSCR[33]
MSCR[34]
MSCR[36]
0000
(Default)
GPI[32]4
ADC1_AN[3]
SIUL2-GPI[32] General Purpose Input C[0]
I
66
41
45
11
R12
T4
0001
—
—
GPI[33]4
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
(Default)
SIUL2-GPI[33] General Purpose Input C[1]
ADC0_AN[2]
0001
—
—
GPI[34]4
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
(Default)
SIUL2-GPI[34] General Purpose Input C[2]
U5
H3
ADC0_AN[3]
0001
—
Reserved
Reserved
—
—
0010-1111
—
—
—
0000
GPIO[36]
SIUL2-
General Purpose IO C[4]
I/O
(Default)
GPIO[36]
0001
CS0
X1
DSPI0
DSPI 0 Peripheral Chip Select I/O
0
0010
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 1
I/O
0011
DEBUG4
—
SSCM
SSCM Debug Output 4
—
O
—
I
0100-1111
0001
Reserved
FlexPWM_0
SIUL2
IMCR[93]
X1
FlexPWM_0 Auxiliary Input 1
IMCR[195]
0001
REQ22
SIUL2 External Interrupt
Source 22
I
C[5]
MSCR[37]
0000
(Default)
GPIO[37]
SCK
SIUL2-
GPIO[37]
General Purpose IO C[5]
I/O
I/O
13
G3
0001
DSPI0
DSPI 0 Input/Output Serial
Clock
0010
—
Reserved
SSCM
—
—
O
—
I
0011
DEBUG5
—
SSCM Debug Output 5
—
0100-1111
0001
Reserved
FlexPWM_0
IMCR[86]
FAULT3
FlexPWM_0 Fault Input 3
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
22
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
IMCR[196]
MSCR[38]
0001
REQ23
SIUL2
SIUL2 External Interrupt
Source 23
I
C[6]
0000
(Default)
GPIO[38]
SIUL2-
GPIO[38]
General Purpose IO C[6]
I/O
O
142
D4
0001
0010
SOUT
B1
DSPI0
DSPI 0 Serial Data Out
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 1
0011
DEBUG6
—
SSCM
SSCM Debug Output 6
—
O
—
I
0100-1111
0001
Reserved
FlexPWM_0
SIUL2
IMCR[92]
B1
FlexPWM_0 Channel B Input 1
IMCR[197]
0001
REQ24
SIUL2 External Interrupt
Source 24
I
C[7]
MSCR[39]
0000
(Default)
GPIO[39]
SIUL2-
GPIO[39]
General Purpose IO C[7]
I/O
—
15
J1
0001
0010
—
Reserved
—
A1
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 1
0011
DEBUG7
—
SSCM
SSCM Debug Output 7
—
O
—
I
0100-1111
0001
Reserved
DSPI0
IMCR[41]
IMCR[91]
SIN
DSPI 0 Serial Data Input
FlexPWM_0 Channel A Input 1
General Purpose IO C[10]
0001
A1
FlexPWM_0
I
C[10] MSCR[42]
0000
GPIO[42]
SIUL2-
I/O
111 B14
(Default)
GPIO[42]
0001
CS2
DSPI2
DSPI 2 Peripheral Chip Select
2
O
0010
0011
—
Reserved
—
—
A3
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 3
0100-1111
0001
—
Reserved
—
—
I
IMCR[84]
IMCR[97]
FAULT1
A3
FlexPWM_0
FlexPWM_0
FlexPWM_0 Fault Input 1
FlexPWM_0 Channel A Input 3
General Purpose IO C[11]
0010
I
C[11] MSCR[43]
0000
GPIO[43]
SIUL2-
I/O
80
P16
(Default)
GPIO[43]
0001
ETC4
CS2
eTimer_0
eTimer_0 Input/Output Data
Channel 4
I/O
O
0010
DSPI2
DSPI 2 Peripheral Chip Select
2
0011
0100
TX_ER
CS0
ENET_0
DSPI3
Ethernet transmit Data Error
O
DSPI 3 Peripheral Chip Select I/O
0
0101-1111
—
Reserved
—
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
23
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
IMCR[52]
0001
CS0
DSPI3
DSPI 3 Peripheral Chip Select
0"
I
IMCR[63]
0100
ETC4
eTimer_0
eTimer_0 Input Data Channel 4 I
C[12]5 MSCR[44]
0000
GPIO[44]
SIUL2-
General Purpose IO C[12]
I/O
82
M14
(Default)
GPIO[44]
0001
0010
0011
0100
ETC5
eTimer_0
eTimer_0 Input/Output Data
Channel 56
I/O
CS3
DSPI2
DSPI 2 Peripheral Chip Select
3
O
O
O
LFAST_TXP
CS1
LFAST
DSPI3
SIPI/LFAST LVDS transmit
positive terminal
DSPI 3 Peripheral Chip Select
1
0101-1111
0100
—
Reserved
SENT1
—
—
I
IMCR[213]
IMCR[64]
SENT_RX[0]
ETC5
SENT 1 Receiver Channel 0
0011
eTimer_0
eTimer_0 Input Data Channel 5 I
C[13] MSCR[45]
0000
GPIO[45]
SIUL2-
General Purpose IO C[13]
I/O
101 E15
(Default)
GPIO[45]
0001
ETC1
eTimer_1
eTimer_1 Input/Output Data
Channel 1
I/O
—
0010-0011
0100
—
Reserved
—
A0
FlexPWM_1
FlexPWM_1 Channel A Input/ I/O
Output 0
0101-1111
0001
—
Reserved
CTU_0
—
—
I
IMCR[38]
IMCR[66]
IMCR[87]
EXT_IN
ETC1
CTU 0 External Trigger Input
0001
eTimer_1
FlexPWM_0
eTimer_1 Input Data Channel 1 I
0001
EXT_SYNC
FlexPWM_0 External Trigger
Input
I
IMCR[105]
0001
A0
FlexPWM_1
FlexPWM_1 Channel A Input 0
General Purpose IO C[14]
I
C[14] MSCR[46]
0000
GPIO[46]
SIUL2-
I/O
103 F14
(Default)
GPIO[46]
0001
ETC2
eTimer_1
eTimer_1 Input/Output Data
Channel 2
I/O
0010
0011
EXT_TGR
CS7
CTU_0
DSPI1
CTU0 External Trigger Output
O
O
DSPI 1 Peripheral Chip Select
7
0100
B0
FlexPWM_1
FlexPWM_1 Channel B Input/ I/O
Output 0
0101-1111
0010
—
Reserved
eTimer_1
—
—
IMCR[67]
ETC2
B0
eTimer_1 Input Data Channel 2 I
FlexPWM_1 Channel B Input 0
IMCR[106]
0001
FlexPWM_1
I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
24
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
C[15] MSCR[47]
0000
GPIO[47]
SIUL2-
General Purpose IO C[15]
I/O
124
A8
(Default)
GPIO[47]
0001
0010
0011
FR_A_TXEN
ETC0
FLEXRAY
FlexRay Transmit Enable
Channel A
O
eTimer_1
eTimer_1 Input/Output Data
Channel 0
I/O
A1
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 1
0100-1111
0010
—
Reserved
CTU_0
—
—
I
IMCR[38]
IMCR[65]
IMCR[87]
EXT_IN
ETC0
CTU 0 External Trigger Input
0010
eTimer_1
FlexPWM_0
eTimer_1 Input Data Channel 0 I
0010
EXT_SYNC
FlexPWM_0 External Sync
Input
I
IMCR[91]
0010
A1
FlexPWM_0
FlexPWM_0 Channel A Input 1
General Purpose IO D[0]
I
D[0]
MSCR[48]
0000
GPIO[48]
SIUL2-
I/O
125
B8
(Default)
GPIO[48]
0001
0010
0011
FR_A_TX
ETC1
B1
FLEXRAY
FlexRay Transmit Data
Channel A
O
eTimer_1
eTimer_1 Input/Output Data
Channel 1
I/O
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 1
0100-1111
0010
—
Reserved
eTimer_1
—
—
IMCR[66]
IMCR[92]
MSCR[49]
ETC1
B1
eTimer_1 Input Data Channel 1 I
0010
FlexPWM_0
FlexPWM_0 Channel B Input 1
General Purpose IO D[1]
I
D[1]
0000
GPIO[49]
SIUL2-
I/O
3
E3
B4
25
(Default)
GPIO[49]
0001
0010
—
Reserved
eTimer_1
—
—
ETC2
eTimer_1 Input/Output Data
Channel 2
I/O
0011
EXT_TGR
—
CTU_0
CTU 0 External Trigger Output
—
O
0100-1111
0011
Reserved
eTimer_1
FLEXRAY
—
IMCR[67]
ETC2
eTimer_1 Input Data Channel 2 I
IMCR[136]
0001
FR_A_RX
FlexRay Channel A Receive
Pin
I
D[2]
MSCR[50]
0000
(Default)
GPIO[50]
SIUL2-
GPIO[50]
General Purpose IO D[2]
I/O
140
0001
0010
—
Reserved
eTimer_1
—
—
ETC3
eTimer_1 Input/Output Data
Channel 3
I/O
0011
X3
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 3
I/O
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0100-1111
0010
—
Reserved
—
—
IMCR[68]
IMCR[99]
IMCR[137]
ETC3
X3
eTimer_1
eTimer_1 Input Data Channel 3 I
0001
FlexPWM_0
FLEXRAY
FlexPWM_0 Auxiliary Input 3
I
I
0001
FR_B_RX
FlexRay Channel B Receive
Pin
D[3]
D[4]
D[5]
MSCR[51]
0000
(Default)
GPIO[51]
FR_B_TX
ETC4
SIUL2-
GPIO[51]
General Purpose IO D[3]
I/O
O
128
129
33
A5
B7
M4
0001
0010
0011
FLEXRAY
FlexRay Transmit Data
Channel B
eTimer_1
eTimer_1 Input/Output Data
Channel 4
I/O
A3
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 3
0100-1111
0010
—
Reserved
eTimer_1
—
—
IMCR[69]
IMCR[97]
MSCR[52]
ETC4
A3
eTimer_1 Input Data Channel 4 I
0011
FlexPWM_0
FlexPWM_0 Channel A Input 3
General Purpose IO D[4]
I
0000
(Default)
GPIO[52]
SIUL2-
GPIO[52]
I/O
0001
0010
0011
FR_B_TXEN
ETC5
FLEXRAY
FlexRay Transmit Enable
Channel B
O
eTimer_1
eTimer_1 Input/Output Data
Channel 5
I/O
B3
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 3
0100-1111
0011
—
Reserved
eTimer_1
—
—
IMCR[70]
IMCR[98]
MSCR[53]
ETC5
B3
eTimer_1 Input Data Channel 5 I
0011
FlexPWM_0
FlexPWM_0 Channel B Input 3
General Purpose IO D[5]
I
0000
GPIO[53]
SIUL2-
I/O
(Default)
GPIO[53]
0001
CS3
DSPI0
DSPI 0 Peripheral Chip Select
3
O
0010
—
Reserved
DSPI3
—
—
O
—
I
0100
SOUT
—
DSPI 3 Serial Data Out
—
0101-1111
0001
Reserved
FlexPWM_0
SENT0
IMCR[85]
IMCR[205]
IMCR[227]
FAULT2
SENT_RX[0]
RX_D1
FlexPWM_0 Fault Input 2
SENT 0 Receiver channel 0
0001
I
0001
ENET_0
Ethernet MII/RMII receive data
1
I
D[6]
MSCR[54]
0000
GPIO[54]
SIUL2-
General Purpose IO D[6]
I/O
34
P3
(Default)
GPIO[54]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
26
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0001
CS2
DSPI0
DSPI 0 Peripheral Chip Select
2
O
0010
0011
—
Reserved
—
—
X3
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 3
I/O
0100
SCK
DSPI3
DSPI 3 Input/Output Serial
Clock
I/O
0101-1111
0001
—
Reserved
DSPI3
—
—
IMCR[51]
IMCR[84]
IMCR[99]
IMCR[226]
SCK
DSPI 3 Input Serial Clock
FlexPWM_0 Fault Input 1
FlexPWM_0 Channel X Input 3
I
I
I
I
0010
FAULT1
X3
FlexPWM_0
FlexPWM_0
ENET_0
0010
0001
RX_D0
Ethernet MII/RMII receive data
0
D[7]
MSCR[55]
0000
(Default)
GPIO[55]7
SGEN OUT8
CS3
SIUL2-
GPIO[55]
General Purpose IO D[7]
I/O
O
37
R4
0001
DSPI1
DSPI 1 Peripheral Chip Select
3
0010
0011
—
Reserved
DSPI0
—
—
O
CS4
DSPI 0 Peripheral Chip Select
4
0100-1111
0010
—
Reserved
DSPI3
—
—
IMCR[50]
IMCR[213]
IMCR[225]
MSCR[56]
SIN
DSPI 3 Serial Data Input
SENT 1 Receiver channel 0
Ethernet Receive data valid
General Purpose IO D[8]
I
0001
SENT_RX[0]
RX_DV
GPIO[56]
SENT1
ENET_0
I
0001
I
D[8]
0000
SIUL2-
I/O
32
L4
(Default)
GPIO[56]
0001
0010
0011
CS2
DSPI1
DSPI 1 Peripheral Chip Select
2
O
ETC4
CS5
eTimer_1
DSPI0
eTimer_1 Input/Output Data
Channel 4
I/O
O
DSPI 0 Peripheral Chip Select
5
0100-1111
0011
—
Reserved
eTimer_1
FlexPWM_0
ENET_0
—
—
IMCR[69]
IMCR[86]
IMCR[224]
MSCR[57]
ETC4
eTimer_1 Input Data Channel 4 I
0010
FAULT3
RX_CLK
GPIO[57]
FlexPWM_0 Fault Input 3
Ethernet Receive clock
General Purpose IO D[9]
I
0001
I
D[9]
0000
SIUL2-
I/O
26
N3
(Default)
GPIO[57]
0001
0010
X0
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 0
I/O
O
TXD
LIN1
LINFlexD 1 Transmit Pin
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
27
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0011-1111
—
Reserved
—
—
D[10] MSCR[58]
0000
GPIO[58]
SIUL2-
General Purpose IO D[10]
I/O
76
R16
(Default)
GPIO[58]
0001
A0
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 0
0010
0011
0100
—
Reserved
ENET_0
DSPI3
—
—
O
TX_D2
CS0
Ethernet MII transmit data
DSPI 3 Peripheral Chip Select I/O
0
0110-1111
0010
—
Reserved
DSPI3
—
—
IMCR[52]
IMCR[59]
CS0
DSPI 3 Peripheral chip Select 0 I
eTimer_0 Input Data Channel 0 I
0001
ETC0
A0
eTimer_0
FlexPWM_0
IMCR[88]
0010
FlexPWM_0 Channel A Input 0
General Purpose IO D[11]
I
D[11] MSCR[59]
0000
GPIO[59]
SIUL2-
I/O
78
P17
(Default)
GPIO[59]
0001
B0
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 0
0010
0011
—
Reserved
DSPI3
—
—
O
CS1
DSPI 3 Peripheral Chip Select
1
0100
SCK
DSPI3
DSPI 3 Input/Output Serial
Clock
I/O
0101-1111
0010
—
Reserved
DSPI3
—
—
I
IMCR[51]
IMCR[60]
SCK
ETC1
B0
DSPI 3 Input Serial Clock
0001
eTimer_0
FlexPWM_0
eTimer_0 Input Data Channel 1 I
IMCR[89]
0010
FlexPWM_0 Channel B Input 0
General Purpose IO D[12]
I
D[12] MSCR[60]
0000
GPIO[60]
SIUL2-
I/O
99
F15
(Default)
GPIO[60]
0001
0010
0011
X1
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 1
I/O
O
CS6
CS2
DSPI1
DSPI 1 Peripheral Chip Select
6
DSPI3
DSPI 3 Peripheral Chip Select
2
O
0100
SOUT
—
DSPI3
DSPI 3 Serial Data Output
—
O
—
I
0101-1111
0010
Reserved
FlexPWM_0
LIN1
IMCR[93]
IMCR[166]
X1
FlexPWM_0 Channel X Input 1
LIN 1 Receive Pin
0010
RXD
GPIO[62]
I
D[14] MSCR[62]
0000
SIUL2-
General Purpose IO D[14]
I/O
105 E17
(Default)
GPIO[62]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
28
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0001
B1
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 1
0010
0011
—
Reserved
DSPI3
—
—
O
CS3
DSPI 3 Peripheral Chip Select
3
0100-1111
0011
—
Reserved
DSPI3
—
—
I
IMCR[50]
IMCR[62]
IMCR[92]
MSCR[64]
SIN
DSPI 3 Serial Data Input
0001
ETC3
eTimer_0
FlexPWM_0
eTimer_0 Input Data Channel 3 I
0011
B1
GPI[64]4
FlexPWM_0 Channel B Input 1
I
I
E[0]
0000
SIUL2-GPI[64] General Purpose Input E[0]
68
T13
(Default)
ADC1_AN[5]/
ADC3_AN[4]
0001
—
—
GPI[66]4
Reserved
Reserved
—
—
—
—
I
0010-1111
E[2]
E[4]
E[5]
E[6]
MSCR[66]
MSCR[68]
MSCR[69]
MSCR[70]
0000
SIUL2-GPI[66] General Purpose Input E[2]
49
42
44
46
U6
U4
T5
R6
(Default)
ADC0_AN[5]
0001
—
—
GPI[68]4
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
(Default)
SIUL2-GPI[68] General Purpose Input E[4]
ADC0_AN[7]
0001
—
—
GPI[69]4
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
(Default)
SIUL2-GPI[69] General Purpose Input E[5]
ADC0_AN[8]
0001
—
—
GPI[70]4
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
SIUL2-GPI[70] General Purpose Input E[6]
(Default)
ADC0_ADC2_A
N[4]
0001
—
—
GPI[71]4
Reserved
Reserved
—
—
—
—
I
0010-1111
E[7]
E[9]
MSCR[71]
MSCR[73]
0000
SIUL2-GPI[71] General Purpose Input E[7]
48
61
T6
(Default)
ADC0_AN[6]
0001
—
—
GPI[73]4
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
SIUL2-GPI[73] General Purpose Input E[9]
U10
ADC1_AN[7]/
ADC3_AN[6]
0001
—
—
Reserved
Reserved
—
—
—
—
0010-1111
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
29
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
E[10] MSCR[74]
E[11] MSCR[75]
E[12] MSCR[76]
E[13] MSCR[77]
0000
(Default)
GPI[74]4
ADC1_AN[8]/
ADC3_AN[7]
SIUL2-GPI[74] General Purpose Input E[10]
I
63
65
67
T11
U11
T12
0001
—
—
GPI[75]4
ADC1_AN[4]/
ADC3_AN[3]
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
(Default)
SIUL2-GPI[75] General Purpose Input E[11]
0001
—
—
GPI[76]4
ADC1_AN[6]/
ADC3_AN[5]
Reserved
Reserved
—
—
—
—
I
0010-1111
0000
(Default)
SIUL2-GPI[76] General Purpose Input E[12]
0001
—
Reserved
Reserved
—
—
0010-1111
—
—
—
0000
GPIO[77]
SIUL2-
General Purpose IO E[13]
I/O
117 A11
(Default)
GPIO[77]
0001
0010
0011
0100
ETC5
CS3
CS4
SCK
eTimer_0
eTimer_0 Input/Output Data
Channel 5
I/O
O
DSPI2
DSPI 2 Peripheral Chip Select
3
DSPI1
DSPI 1 Peripheral Chip Select
4
O
DSPI3
DSPI 3 Input/Output Serial
Clock
I/O
0101-1111
0011
—
Reserved
DSPI3
—
—
IMCR[51]
SCK
REQ25
DSPI 3 Input Serial Clock
I
I
IMCR[198]
0001
SIUL2
SIUL2 External Interrupt
Source 25
IMCR[64]
0100
ETC5
eTimer_0
eTimer_0 Input Data Channel
General Purpose IO E[14]
I
E[14] MSCR[78]
0000
GPIO[78]
SIUL2-
I/O
119 B10
(Default)
GPIO[78]
0001
ETC5
eTimer_1
eTimer_1 Input/Output Data
Channel 5
I/O
0010
0011
SOUT
CS5
DSPI3
DSPI1
DSPI 3 Serial Data Out
O
O
DSPI 1 Peripheral Chip Select
5
0100
B2
FlexPWM_1
FlexPWM_1 Channel B Input/ I/O
Output 2
0101-1111
0100
—
Reserved
eTimer_1
—
—
IMCR[70]
ETC5
B2
eTimer_1 Input Data Channel 5 I
FlexPWM_1 Channel B Input 2
IMCR[113]
0001
FlexPWM_1
I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
30
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
IMCR[199]
0001
REQ26
SIUL2
SIUL2 External Interrupt
Source 26
I
E[15] MSCR[79]
0000
(Default)
GPIO[79]
CS1
SIUL2-
GPIO[79]
General Purpose IO E[15]
I/O
O
121
C8
0001
DSPI0
DSPI 0 Peripheral Chip Select
1
0010
0011
—
Reserved
ENET_0
—
—
O
TIMER1
Ethernet TIMER Outputs
(Output Compare Events)
0100-1111
0100
—
Reserved
DSPI3
—
—
IMCR[50]
SIN
DSPI 3 Serial Data Input
I
I
IMCR[200]
0001
REQ27
SIUL2
SIUL2 External Interrupt
Source 27
F[0]
MSCR[80]
0000
(Default)
GPIO[80]
A1
SIUL2-
GPIO[80]
General Purpose IO F[0]
I/O
133
B6
0001
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 1
0010
CS3
DSPI3
DSPI 3 Peripheral Chip Select
3
O
0011
MDC
—
ENET_0
Reserved
eTimer_0
FlexPWM_0
SIUL2
Ethernet MDIO clock output
—
O
0100-1111
0001
—
IMCR[61]
IMCR[91]
IMCR[201]
ETC2
A1
eTimer_0 Input Data Channel 2 I
0011
FlexPWM_0 Channel A Input 1
I
I
0001
REQ28
SIUL2 External Interrupt
Source 28
F[3]
MSCR[83]
0000
(Default)
GPIO[83]
CS6
SIUL2-
GPIO[83]
General Purpose IO F[3]
I/O
O
139
B3
0001
DSPI0
DSPI 0 Peripheral Chip Select
6
0010
0011
—
Reserved
DSPI3
—
—
O
CS2
DSPI 3 Peripheral Chip Select
2
0100
TIMER2
ENET_0
Ethernet TIMER Outputs 2
(Output Compare Events)
O
0101-1111
—
Reserved
—
—
F[4]
MSCR[84]
0000
GPIO[84]
SIUL2-
General Purpose IO F[4]
I/O
4
E1
(Default)
GPIO[84]
0001
0010
—
Reserved
—
O
MDO[3]
NPC_WRAPP Nexus - Message Data Out Pin O
ER
3
0011
CS1
DSPI3
DSPI 3 Peripheral Chip Select
1
O
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
31
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0100-1111
—
Reserved
—
—
F[5]
MSCR[85]
0000
GPIO[85]
SIUL2-
General Purpose IO F[5]
I/O
5
F1
(Default)
GPIO[85]
0001
0010
—
Reserved
—
O
MDO[2]
NPC_WRAPP Nexus Message Data Out Pin 2 O
ER
0011
CS0
DSPI3
DSPI 3 Peripheral Chip Select I/O
0
0100-1111
0011
—
Reserved
DSPI3
—
—
I
IMCR[52]
MSCR[86]
CS0
DSPI 3 Peripheral Chip Select
0
F[6]
F[7]
F[8]
F[9]
0000
(Default)
GPIO[86]
SIUL2-
GPIO[86]
General Purpose IO F[6]
I/O
I/O
8
E2
J4
J3
K3
K2
0001
0010
—
Reserved
—
MDO[1]
NPC_WRAPP Nexus Message Data Out Pin 1 O
ER
0011-1111
—
Reserved
—
—
MSCR[87]
MSCR[88]
MSCR[89]
0000
(Default)
GPIO[87]
SIUL2-
GPIO[87]
General Purpose IO F[7]
I/O
19
20
23
24
0001
0010
—
Reserved
—
I/O
O
MCKO
NPC_WRAPP Nexus Message Clock Out for
ER
development tools
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[88]
SIUL2-
GPIO[88]
General Purpose IO F[8]
I/O
0001
0010
—
Reserved
—
I/O
O
MSEO_B[1]
NPC_WRAPP Nexus Message Start/End Out
ER
Pin 1
0011-1111
—
Reserved
—
—
0000
(Default)
GPIO[89]
SIUL2-
GPIO[89]
General Purpose IO F[9]
I/O
0001
0010
—
Reserved
—
I/O
O
MSEO_B[0]
NPC_WRAPP Nexus Message Start/End Out
ER
Pin 0
0011-1111
—
Reserved
—
—
F[10] MSCR[90]
0000
GPIO[90]
SIUL2-
General Purpose IO F[10]
I/O
(Default)
GPIO[90]
0001
0010
—
Reserved
—
—
O
EVTO_B
NPC_WRAPP Nexus Event Out Pin
ER
0011-1111
—
Reserved
—
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
32
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
F[11] MSCR[91]
0000
(Default)
GPIO[91]
SIUL2-
GPIO[91]
General Purpose IO F[11]
—
I/O
25
L2
0001
0010
—
Reserved
—
I
EVTI_IN
NPC_WRAPP Nexus Event In Pin
ER
0011-1111
—
Reserved
—
—
F[12] MSCR[92]
0000
GPIO[92]
SIUL2-
General Purpose IO F[12]
I/O
106 D17
(Default)
GPIO[92]
0001
ETC3
eTimer_1
eTimer_1 Input/Output Data
Channel 3
I/O
0010-0011
0100
—
Reserved
—
—
A1
FlexPWM_1
FlexPWM_1 Channel A Input/ I/O
Output 1
0101-1111
0011
—
Reserved
eTimer_1
FlexPWM_1
SIUL2
—
—
IMCR[68]
IMCR[109]
IMCR[203]
ETC3
A1
eTimer_1 Input Data Channel 3 I
0001
FlexPWM_1 Channel A Input 1
I
I
0001
REQ30
SIUL2 External Interrupt
Source 30
F[13] MSCR[93]
0000
(Default)
GPIO[93]
ETC4
SIUL2-
GPIO[93]
General Purpose IO F[13]
I/O
I/O
—
112 A15
0001
eTimer_1
eTimer_1 Input/Output Data
Channel 4
0010-0011
0100
—
Reserved
—
B1
FlexPWM_1
FlexPWM_1 Channel A Input/ I/O
Output 1
0101-1111
0100
—
Reserved
eTimer_1
FlexPWM_1
SIUL2
—
—
IMCR[69]
IMCR[110]
IMCR[204]
ETC4
B1
eTimer_1 Input Data Channel 4 I
0001
FlexPWM_1 Channel B Input 1
I
I
0001
REQ31
SIUL2 External Interrupt
Source 31
F[14] MSCR[94]
0000
GPIO[94]
SIUL2-
General Purpose IO F[14]
I/O
115 D12
(Default)
GPIO[94]
0001
TXD
LIN1
LINFlexD 1 Transmit Pin
CAN 2 Transmit Pin
—
O
0010
TXD
CAN2
O
0011-1111
—
Reserved
—
I/O
F[15] MSCR[95]
0000
GPIO[95]
SIUL2-
General Purpose IO F[15]
113 A13
(Default)
GPIO[95]
0001
—
Reserved
Reserved
LIN1
—
—
—
I
0010-1111
0011
—
—
IMCR[166]
IMCR[34]
RXD
RXD
LIN1 RXD
CAN2 RXD
0001
CAN2
I
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
33
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
G[2]
MSCR[98]
0000
GPIO[98]
SIUL2-
General Purpose IO G[2]
I/O
102 F17
(Default)
GPIO[98]
0001
X2
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 2
I/O
O
0010
CS1
DSPI1
DSPI 1 Peripheral Chip Select
1
0011-1111
0010
—
Reserved
—
—
I
IMCR[96]
MSCR[99]
X2
FlexPWM_0
FlexPWM_0 Auxiliary Input 2
General Purpose IO G[3]
G[3]
G[4]
G[5]
0000
GPIO[99]
SIUL2-
I/O
104 E16
(Default)
GPIO[99]
0001
A2
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 2
0010-1111
0010
—
Reserved
eTimer_0
—
—
IMCR[63]
IMCR[94]
MSCR[100]
ETC4
A2
eTimer_0 Input Data Channel 4 I
0011
FlexPWM_0
FlexPWM_0 Channel A Input 2
General Purpose IO G[4]
I
0000
(Default)
GPIO[100]
SIUL2-
GPIO[100]
I/O
100 F16
0001
B2
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 2
0010-1111
0010
—
Reserved
eTimer_0
—
—
IMCR[64]
IMCR[95]
MSCR[101]
ETC5
B2
eTimer_0 Input Data Channel 5 I
0011
FlexPWM_0
FlexPWM_0 Channel B Input 2
General Purpose IO G[5]
I
0000
GPIO[101]
SIUL2-
I/O
85
M17
(Default)
GPIO[101]
0001
X3
FlexPWM_0
FlexPWM_0 Auxiliary Input/
Output 3
I/O
O
0010
CS3
DSPI2
DSPI 2 Peripheral Chip Select
3
0011
TX_EN
—
ENET_0
Ethernet Transmit Data Valid
—
O
—
I
0100-1111
0011
Reserved
FlexPWM_0
IMCR[99]
X3
FlexPWM_0 Auxiliary Input 3
General Purpose IO G[6]
G[6]
MSCR[102]
0000
GPIO[102]
SIUL2-
I/O
98
83
G17
M16
(Default)
GPIO[102]
0001
A3
FlexPWM_0
FlexPWM_0 Channel A Input/ I/O
Output 3
0010-1111
0100
—
Reserved
—
—
I
IMCR[97]
A3
FlexPWM_0
FlexPWM_0 Channel A Input 3
General Purpose IO G[7]9
G[7]5 MSCR[103]
0000
GPIO[103]
SIUL2-
I/O
(Default)
GPIO[103]
0001
B3
FlexPWM_0
FlexPWM_0 Channel B Input/ I/O
Output 3
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
34
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0010
0011
—
Reserved
—
—
LFAST_RXP
LFAST
SIPI/LFAST LVDS receive
positive terminal
I
0100-1111
0100
—
Reserved
—
—
I
IMCR[98]
B3
FlexPWM_0
FlexPWM_0 Channel B Input 3
General Purpose IO G[8]
G[8]
MSCR[104]
0000
GPIO[104]
SIUL2-
I/O
81
N14
(Default)
GPIO[104]
0001
0010
FR_DBG[0]
CS1
FLEXRAY
DSPI0
FlexRay Debug Strobe Signal 0 O
DSPI 0 Peripheral Chip Select
1
O
0011
RMII_CLK
ENET_0
Ethernet RMII Clock (used in
MII to RMII Gaskets)
O
0100-1111
0011
—
Reserved
FlexPWM_0
SIUL2
—
—
IMCR[83]
FAULT0
REQ21
FlexPWM_0 Fault Input 0
I
I
IMCR[194]
0001
SIUL2 External Interrupt
Source 21
IMCR[205]
IMCR[233]
MSCR[105]
0011
0001
SENT_RX[0]
TX_CLK
SENT_0
ENET_0
SENT 0 Receiver channel 0
Ethernet Transmit Clock
General Purpose IO G[9]
I
I
G[9]
0000
GPIO[105]
SIUL2-
I/O
79
P14
(Default)
GPIO[105]
0001
0010
FR_DBG[1]
CS1
FLEXRAY
DSPI1
FlexRay Debug Strobe Signal 1 O
DSPI 1 Peripheral Chip Select
1
O
0011
TX_D0
ENET_0
Ethernet MII/RMII transmit data O
0
0100-1111
0011
—
Reserved
FlexPWM_0
SIUL2
—
—
IMCR[84]
FAULT1
REQ29
FlexPWM_0 Fault Input 1
I
I
IMCR[202]
0001
SIUL2 External Interrupt
Source 29
IMCR[213]
0011
SENT_RX[0]
GPIO[106]
SENT_1
SENT 1 Receiver channel 0
General Purpose IO G[10]
I
G[10] MSCR[106]
0000
SIUL2-
I/O
77
R17
(Default)
GPIO[106]
0001
0010
FR_DBG[2]
CS3
FLEXRAY
DSPI2
FlexRay Debug Strobe Signal 2 O
DSPI 2 Peripheral Chip Select
3
O
0011
TX_D1
ENET_0
Ethernet MII/RMII transmit data O
1
0100-1111
0010
—
Reserved
FlexPWM_0
SENT_0
—
—
IMCR[85]
FAULT2
SENT_RX[1]
FlexPWM_0 Fault Input 2
SENT 0 Receiver channel 1
I
I
IMCR[206]
0100
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
35
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
G[11] MSCR[107]
0000
GPIO[107]
SIUL2-
General Purpose IO G[11]
I/O
75
T15
(Default)
GPIO[107]
FLEXRAY
Reserved
ENET_0
0001
0010
0011
FR_DBG[3]
—
FlexRay Debug Strobe Signal 3 O
—
—
TX_D3
Ethernet MII/RMII transmit data O
3
0100-1111
0011
—
Reserved
FlexPWM_0
SENT_1
—
—
I
IMCR[86]
FAULT3
SENT_RX[1]
GPIO[116]
FlexPWM_0 Fault Input 3
SENT 1 Receiver channel 1
General Purpose IO H[4]
IMCR[214]
0100
I
H[4]
MSCR[116]
0000
SIUL2-
I/O
F4
(Default)
GPIO[116]
0001
X0
FlexPWM_1
FlexPWM_1 Auxiliary Input/
Output 0
I/O
I/O
—
0010
ETC0
eTimer_2
eTimer_2 Input/Output Data
Channel 0
0011-1111
0001
—
Reserved
eTimer_2
ENET_0
—
IMCR[71]
ETC0
CRS
eTimer_2 Input Data Channel 0 I
IMCR[231]
MSCR[117]
0001
Ethernet MII Carrier Sense
General Purpose IO H[5]
I
H[5]
0000
GPIO[117]
SIUL2-
I/O
F3
(Default)
GPIO[117]
0001
A0
FlexPWM_1
FlexPWM_1 Channel A Input/ I/O
Output 0
0010
0011
—
Reserved
DSPI0
—
—
O
CS4
DSPI 0 Peripheral Chip Select
4
0100-1111
0010
—
Reserved
FlexPWM_1
ENET_0
—
—
I
IMCR[105]
IMCR[230]
MSCR[118]
A0
FlexPWM_1 Channel A Input 0
Ethernet MII Collision
General Purpose IO H[6]
0001
COL
I
H[6]
0000
GPIO[118]
SIUL2-
I/O
C13
(Default)
GPIO[118]
0001
B0
FlexPWM_1
FlexPWM_1 Channel B Input/ I/O
Output 0
0010
0011
—
Reserved
DSPI0
—
—
O
CS5
DSPI 0 Peripheral Chip Select
5
0100-1111
0010
—
Reserved
—
—
I
IMCR[106]
MSCR[119]
B0
FlexPWM_1
FlexPWM_1 Channel B Input 0
General Purpose IO H[7]
H[7]
0000
GPIO[119]
SIUL2-
I/O
F2
(Default)
GPIO[119]
0001
X1
FlexPWM_1
FlexPWM_1 Auxiliary Input/
Output 1
I/O
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
36
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0010
0011
ETC1
eTimer_2
eTimer_2 Input/Output Data
Channel 1
I/O
MDIO
ENET_0
Ethernet MDIO input/output
data
I/O
—
0100-1111
0001
—
Reserved
eTimer_2
—
IMCR[72]
ETC1
GPIO[120]
eTimer_2 Input Data Channel 1 I
H[8]
MSCR[120]
0000
SIUL2-
General Purpose IO H[8]
I/O
L1
(Default)
GPIO[120]
0001
A1
FlexPWM_1
FlexPWM_1 Channel A Input/ I/O
Output 1
0010
0011
—
Reserved
DSPI0
—
—
O
CS6
DSPI 0 Peripheral Chip Select
6
0100-1111
0010
—
Reserved
FlexPWM_1
ENET_0
—
—
I
IMCR[109]
IMCR[228]
MSCR[121]
A1
FlexPWM_1 Channel A Input 1
Ethernet MII Receive Data 2
General Purpose IO H[9]
0001
RX_D2
GPIO[121]
I
H[9]
0000
SIUL2-
I/O
B13
(Default)
GPIO[121]
0001
B1
FlexPWM_1
FlexPWM_1 Channel B Input/ I/O
Output 1
0010
0011
—
Reserved
DSPI0
—
—
O
CS7
DSPI 0 Peripheral Chip Select
7
0100-1111
0010
—
Reserved
—
—
I
IMCR[110]
B1
FlexPWM_1
FlexPWM_1 Channel B Input 1
General Purpose IO H[10]
H[10] MSCR[122]
0000
GPIO[122]
SIUL2-
I/O
C7
(Default)
GPIO[122]
0001
X2
FlexPWM_1
FlexPWM_1 Auxiliary Input/
Output 2
I/O
I/O
—
0010
ETC2
eTimer_2
eTimer_2 Input/Output Data
Channel 2
0011-1111
0010
—
Reserved
eTimer_2
—
IMCR[73]
ETC2
GPIO[123]
eTimer_2 Input Data Channel 2 I
H[11] MSCR[123]
0000
SIUL2-
General Purpose IO H[11]
I/O
C9
A7
37
(Default)
GPIO[123]
0001
A2
FlexPWM_1
FlexPWM_1 Channel A Input/ I/O
Output 2
0010-1111
0010
—
Reserved
—
—
I
IMCR[112]
A2
FlexPWM_1
FlexPWM_1 Channel A Input 2
General Purpose IO H[12]
H[12] MSCR[124]
0000
(Default)
GPIO[124]
SIUL2-
GPIO[124]
I/O
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0001
B2
FlexPWM_1
FlexPWM_1 Channel B Input/ I/O
Output 2
0010-1111
0010
—
Reserved
—
—
I
IMCR[113]
B2
FlexPWM_1
FlexPWM_1 Channel B Input 2
General Purpose IO H[13]
H[13] MSCR[125]
0000
GPIO[125]
SIUL2-
I/O
A14
P13
C17
C6
(Default)
GPIO[125]
0001
X3
FlexPWM_1
FlexPWM_1 Auxiliary Input/
Output 3
I/O
I/O
—
0010
ETC3
eTimer_2
eTimer_2 Input/Output Data
Channel 3
0011-1111
0010
—
Reserved
eTimer_2
—
IMCR[74]
ETC3
GPIO[126]
eTimer_2 Input Data Channel 3 I
H[14] MSCR[126]
0000
(Default)
SIUL2-
GPIO[126]
General Purpose IO H[14]
I/O
0001
A3
FlexPWM_1
FlexPWM_1 Channel A Input/ I/O
Output 3
0010
ETC4
eTimer_2
eTimer_2 Input/Output Data
Channel 4
I/O
0011-1111
0010
—
Reserved
eTimer_2
—
—
IMCR[75]
ETC4
GPIO[127]
eTimer_2 Input Data Channel 4 I
H[15] MSCR[127]
0000
(Default)
SIUL2-
GPIO[127]
General Purpose IO H[15]
I/O
0001
B3
FlexPWM_1
FlexPWM_1 Channel B Input/ I/O
Output 3
0010
ETC5
eTimer_2
eTimer_2 Input/Output Data
Channel 5
I/O
0011-1111
0010
—
Reserved
eTimer_2
—
—
IMCR[76]
ETC5
GPIO[128]
eTimer_2 Input Data Channel 5 I
I[0]
MSCR[128]
0000
SIUL2-
General Purpose IO I[0]
I/O
(Default)
GPIO[128]
0001
ETC0
CS4
eTimer_2
eTimer_2 Input/Output Data
Channel 0
I/O
O
0010
DSPI0
DSPI 0 Peripheral Chip Select
4
0011-1111
0010
—
Reserved
eTimer_2
—
—
IMCR[71]
ETC0
eTimer_2 Input Data Channel 0 I
IMCR[100]
MSCR[129]
0001
FAULT0
GPIO[129]
FlexPWM_1
FlexPWM_1 Fault Input 0
General Purpose IO I[1]
I
I[1]
0000
SIUL2-
I/O
T3
(Default)
GPIO[129]
0001
ETC1
eTimer_2
eTimer_2 Input/Output Data
Channel 1
I/O
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
38
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
0010
CS5
—
DSPI0
DSPI 0 Peripheral Chip Select
5
O
0011-1111
0010
Reserved
eTimer_2
FlexPWM_1
ENET_0
—
—
IMCR[72]
ETC1
eTimer_2 Input Data Channel 1 I
IMCR[101]
IMCR[232]
MSCR[130]
0001
FAULT1
RX_ER
GPIO[130]
FlexPWM_1 Fault Input 1
Ethernet Receive Data Error
General Purpose IO I[2]
I
0001
I
I[2]
0000
SIUL2-
I/O
D11
(Default)
GPIO[130]
0001
0010
ETC2
CS6
eTimer_2
DSPI0
eTimer_2 Input/Output Data
Channel 2
I/O
O
DSPI 0 Peripheral Chip Select
6
0011-1111
0011
—
Reserved
eTimer_2
—
—
IMCR[73]
ETC2
eTimer_2 Input Data Channel 2 I
IMCR[102]
MSCR[131]
0001
FAULT2
GPIO[131]
FlexPWM_1
FlexPWM_1 Fault Input 2
General Purpose IO I[3]
I
I[3]
0000
SIUL2-
I/O
A10
(Default)
GPIO[131]
0001
ETC3
CS7
eTimer_2
eTimer_2 Input/Output Data
Channel 3
I/O
O
0010
DSPI0
DSPI 0 Peripheral Chip Select
7
0011
0100
EXT_TGR
TIMER0
CTU_0
CTU0 External Trigger Output
O
O
ENET_0
Ethernet TIMER Outputs 0
(Output Compare Events)
0101-1111
0011
—
Reserved
eTimer_2
—
—
IMCR[74]
ETC3
eTimer_2 Input Data Channel 3 I
IMCR[103]
0001
FAULT3
GPIO[132]
FlexPWM_1
FlexPWM_1 Fault Input 3
General Purpose IO I[4]
I
RDY_ MSCR[132]
B/I[4]
0000
(Default)
SIUL2-
GPIO[132]
I/O
J2
0001
0010
—
Reserved
—
—
O
NEX_RDY_B
NPC_WRAPP Nexus data ready for transfer
ER
(RDY_B)
0011-1111
—
Reserved
—
—
I[5]5
MSCR[133]
0000
GPIO[133]
SIUL2-
General Purpose IO I[5]10
I/O
N15
(Default)
GPIO[133]
0001
0010
0011
TXD
CAN2
CAN 2 Transmit Pin
—
O
—
O
—
Reserved
LFAST
LFAST_TXN
SIPI/LFAST LVDS transmit
negative terminal
0100-1111
—
Reserved
—
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
39
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
I[6]5
MSCR[134]
0000
GPIO[134]
SIUL2-
General Purpose IO I[6]11
I/O
M15
(Default)
GPIO[134]
Reserved
Reserved
LFAST
0001
0010
0011
—
—
—
—
—
I
—
LFAST_RXN
SIPI/LFAST LVDS receive
negative terminal
0100-1111
0010
—
Reserved
CAN2
—
—
I
IMCR[34]
RXD
CAN 2 Receive Pin
General Purpose IO I[7]
I[7]
MSCR[135]
0000
GPIO[135]
SIUL2-
I/O
D2
(Default)
GPIO[135]
0001
LFAST_REF_C MC_CGM
LK
SIPI/LFAST Input/Output
reference clock
I/O
0010-1111
0010
—
Reserved
SENT0
—
—
I
IMCR[205]
MSCR[136]
SENT_RX[0]
GPIO[136]
SENT 0 Receiver channel 0
General Purpose IO I[8]
I[8]
I[9]
0000
SIUL2-
I/O
K4
L3
(Default)
GPIO[136]
0001
—
Reserved
Reserved
SENT1
—
—
—
I
0010-1111
0010
—
—
IMCR[213]
MSCR[137]
SENT_RX[0]
GPIO[137]
SENT 1 Receiver channel 0
General Purpose IO I[9]
0000
SIUL2-
I/O
(Default)
GPIO[137]
0001
ETC4
eTimer_2
eTimer_2 Input/Output Data
Channel 4
I/O
—
0010-1111
0011
—
Reserved
eTimer_2
—
IMCR[75]
ETC4
GPIO[138]
eTimer_2 Input Data Channel 4 I
I[10]
MSCR[138]
0000
SIUL2-
General Purpose IO I[10]
I/O
M3
(Default)
GPIO[138]
0001
ETC5
eTimer_2
eTimer_2 Input/Output Data
Channel 5
I/O
—
0010-1111
0011
—
Reserved
eTimer_2
—
IMCR[76]
ETC5
GPIO[139]
eTimer_2 Input Data Channel 5 I
I[11]
I[12]
MSCR[139]
0000
SIUL2-
General Purpose IO I[11]
I/O
U3
P5
(Default)
GPIO[139]
0001
—
Reserved
Reserved
SENT0
—
—
—
I
0010-1111
0001
—
—
IMCR[206]
MSCR[140]
SENT_RX[1]
GPIO[140]
SENT 0 Receiver channel 1
General Purpose IO I[12]
0000
SIUL2-
I/O
(Default)
GPIO[140]
0001
—
Reserved
Reserved
SENT1
—
—
—
I
0010-1111
0001
—
—
IMCR[214]
SENT_RX[1]
SENT 1 Receiver channel 1
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
40
NXP Semiconductors
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
I[13]
MSCR[141]
0000
GPIO[141]
SIUL2-
General Purpose IO I[13]
I/O
P6
GPIO[141]
0001
EXT_TGR
—
CTU_1
CTU1 External Trigger Output
—
O
0010-1111
Reserved
—
I/O
I[14]
MSCR[142]
0000
GPIO[142]
SIUL2-
General Purpose IO I[14]
C10
(Default)
GPIO[142]
0001
CS0
DSPI3
DSPI 3 Peripheral Chip Select I/O
0
0010-1111
0100
—
Reserved
DSPI3
—
—
I
IMCR[52]
CS0
DSPI 3 Peripheral Chip Select
0
I[15]
MSCR[143]
0000
(Default)
GPIO[143]
SCK
SIUL2-
GPIO[143]
General Purpose IO I[15]
I/O
I/O
C1
0001
DSPI3
DSPI 3 Input/Output Serial
Clock
0010-1111
0100
—
Reserved
DSPI3
—
—
I
IMCR[51]
SCK
DSPI 3 Input Peripheral Serial
Clock
J[0]
J[1]
MSCR[144]
0000
(Default)
GPIO[144]
SIUL2-
GPIO[144]
General Purpose IO J[0]
I/O
C2
0001
SOUT
—
DSPI3
DSPI 3 Serial Data Out
—
O
0010-1111
Reserved
—
I/O
MSCR[145]
0000
GPIO[145]
SIUL2-
General Purpose IO J[1]
A12
(Default)
GPIO[145]
0001
—
Reserved
Reserved
DSPI3
—
—
—
I
0010-1111
0001
—
—
IMCR[50]
SIN
DSPI 3 Serial Data Input
General Purpose IO J[2]
J[2]
J[3]
J[4]
MSCR[146]
0000
GPIO[146]
SIUL2-
I/O
C11
B15
D13
(Default)
GPIO[146]
0001
CS1
DSPI3
DSPI 3 Peripheral Chip Select
1
O
0010-1111
—
Reserved
—
—
MSCR[147]
MSCR[148]
0000
(Default)
GPIO[147]
SIUL2-
GPIO[147]
General Purpose IO J[3]
I/O
0001
CS2
DSPI3
DSPI 3 Peripheral Chip Select
2
O
0010-1111
—
Reserved
—
—
0000
GPIO[148]
SIUL2-
General Purpose IO J[4]
I/O
(Default)
GPIO[148]
0001
CS3
—
DSPI3
DSPI 3 Peripheral Chip Select
3
O
0010-1111
Reserved
—
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
41
Pinouts
Table 8. Pin muxing (continued)
SIUL2 MSCR/
IMCR
MSCR/
IMCR SSS
Value1
Port
Pin
Signal
Module
Short Signal Description
Dir
Number
IMCR[39]
0001
EXT_IN
GPI[149]4
CTU_1
SIUL2-
CTU 1 External Trigger Input
General Purpose Input J[5]
I
I
J[5]
MSCR[149]
0000
P8
P9
(Default)
ADC2_ADC3_A GPI[149]
N[0]
0001
—
Reserved
Reserved
SENT0
—
—
—
I
0010-1111
0010
—
—
IMCR[206]
MSCR[150]
SENT_RX[1]
GPI[150]4
SENT 0 Receiver channel 1
General Purpose Input J[6]
J[6]
0000
SIUL2-
I
(Default)
ADC2_ADC3_A GPI[150]
N[1]
0001
—
Reserved
Reserved
SENT1
—
—
—
I
0010-1111
0010
—
—
IMCR[214]
MSCR[151]
SENT_RX[1]
GPI[151]4
SENT 1 Receiver channel 1
General Purpose Input J[7]
J[7]
J[8]
0000
SIUL2-
I
P10
G16
(Default)
ADC2_ADC3_A GPI[151]
N[2]
0001
—
Reserved
Reserved
—
—
0010-1111
—
—
—
MSCR[152]
0000
GPIO[152]
SIUL2-
General Purpose IO J[8]
I/O
95
16
1
(Default)
GPIO[152]
0001
ETC4
ETC2
eTimer_2
eTimer_2 Input/Output Data
Channel 4
I/O
I/O
0010
eTimer_2
eTimer_2 Input/Output Data
Channel 2
0011-1111
0011
—
Reserved
CAN2
—
—
I
IMCR[34]
IMCR[73]
IMCR[75]
MSCR[153]
RXD
CAN 2 Receive Pin
0100
ETC2
ETC4
GPIO[153]
eTimer_2
eTimer_2
eTimer_2 Input Data Channel 2 I
eTimer_2 Input Data Channel 4 I
0100
J[9]
0000
(Default)
SIUL2-
GPIO[153]
General Purpose IO J[9]
I/O
K1
0001
ETC5
eTimer_2
eTimer_2 Input/Output Data
Channel 5
I/O
O
0010
NEX_RDY_B
NPC
Nexus data ready for transfer
(RDY_B)
0011-1111
0010
—
Reserved
CTU_1
—
—
I
IMCR[39]
IMCR[76]
IMCR[229]
EXT_IN
ETC5
RX_D3
NMI_B
CTU_1 External Trigger Input
0100
eTimer_2
ENET_0
Core
eTimer_2 Input Data Channel 5 I
0001
Ethernet MII Receive Data 3
Non-Maskable Interrupt
I
I
NMI_B MSCR[154]
0000
E4
(Default)
1. Selecting an alternative function with a "Reserved" source function causes the pin to enter a null state (input buffer and
output buffer enables are both 0).
MPC5744P Data Sheet, Rev. 6.1, 11/2017
42
NXP Semiconductors
Pinouts
2. (Default) = ALT mode configuration after reset.
3. Changing the B[5] configuration during debug might affect the availability of TDI.
4. ADC analog input: Program corresponding MSCR APC bit and enable ADC to switch on the analog input path.
5. When the LFAST interface is selected the other functionality of the MSCR register is not available.
6. Shared with SIPI LFAST transmit pad SIPI_TXP. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is
used for SIPI LFAST.
7. To operate D[7] as GPIO, disable the Sine Wave Generator (SGEN) and the peripheral bus clock of the SGEN: Program
the MC_ME_PCTL239 register to select an MC_ME_RUN_PCn (or MC_ME_LP_PCn) configuration where the field for the
desired mode is 0.
8. SGEN output if SGEN is enabled.
9. Shared with SIPI LFAST receive pad SIPI_RXP. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is
used for SIPI LFAST.
10. Shared with SIPI LFAST receive pad SIPI_TXN. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is
used for SIPI LFAST.
11. Shared with SIPI LFAST receive pad SIPI_RXN. Alternative modes and GPIO must be disabled (OBE=0, IBE=0) if port is
used for SIPI LFAST.
The following table list ports that are not implemented. The corresponding control and
data registers are not implemented.
Table 9. Ports - Not Implemented
Port Name
Port Index
3,8,9
C
D
E
F
13,15
1,3,8
1,2
G
H
J
0,1,[12:15]
[0:3]
[10:15]
Any attempt to access unimplemented MSCRs generates a bus error. The read value from
unimplemented ports must be masked in case of parallel port accesses.
2.2.6 Peripheral input muxing
The following table describes the peripheral muxing capabilities of the device.
Table 10. Peripheral muxing
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
FlexCAN_0
RXD
IMCR[32]
0000 (Default)1
0001
—
Disable
A[15]
I/O-Pad
I/O-Pad
—
0010
B[1]
Reserved2
0011-1111
0000 (Default)
FlexCAN_1
RXD
IMCR[33]
—
Disable
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
43
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0001
I/O-Pad
A[15]
0010
I/O-Pad
—
B[1]
0011-1111
0000 (Default)
0001
Reserved
Disable
F[15]
FlexCAN_2
RXD
IMCR[34]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
I[6]
0011
J[8]
0100-1111
0000 (Default)
0001
Reserved
Disable
C[13]
CTU_0
CTU_1
EXT_IN
EXT_IN
IMCR[38]
IMCR[39]
—
I/O-Pad
I/O-Pad
—
0010
C[15]
0011-1111
0000 (Default)
0001
Reserved
Disable
J[4]
—
I/O-Pad
I/O-Pad
—
0010
J[9]
0011-1111
0000 (Default)
0001
Reserved
Disable
C[7]
DSPI_0
DSPI_1
DSPI_2
SIN
SIN
SIN
IMCR[41]
IMCR[44]
IMCR[47]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[8]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[13]
—
I/O-Pad
I/O-Pad
—
0010
A[2]
0011-1111
0000 (Default)
0001
Reserved
Disable
A[0]
DSPI_2
DSPI_2
DSPI_3
SCK
SC0
SIN
IMCR[48]
IMCR[49]
IMCR[50]
—
I/O-Pad
I/O-Pad
—
0010
A[11]
0011-1111
0000 (Default)
0001
Reserved
Disable
A[3]
—
I/O-Pad
I/O-Pad
—
0010
A[10]
0011-1111
0000 (Default)
0001
Reserved
Disable
J[1]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
0010
D[7]
0011
D[14]
0100
E[15]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
44
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0101-1111
0000 (Default)
0001
—
—
Reserved
Disable
D[6]
DSPI_3
SCK
IMCR[51]
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
D[11]
0011
E[13]
0100
I[15]
0101-1111
0000 (Default)
0001
Reserved
Disable
C[11]
DSPI_3
CS0
IMCR[52]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
D[10]
0011
F[5]
0100
I[14]
0101-1111
0000 (Default)
0001
Reserved
Disable
D[10]
eTimer_0
eTimer_0
eTimer_0
eTimer_0
eTimer_0
ETC0
ETC1
ETC2
ETC3
ETC4
IMCR[59]
IMCR[60]
IMCR[61]
IMCR[62]
IMCR[63]
—
I/O-Pad
I/O-Pad
—
0010
A[0]
0011-1111
0000 (Default)
0001
Reserved
Disable
D[11]
—
I/O-Pad
I/O-Pad
—
0010
A[1]
0011-1111
0000 (Default)
0001
Reserved
Disable
F[0]
—
I/O-Pad
I/O-Pad
—
0010
A[2]
0011-1111
0000 (Default)
0001
Reserved
Disable
D[14]
—
I/O-Pad
I/O-Pad
—
0010
A[3]
0011-1111
0000 (Default)
0001
Reserved
Disable
B[14]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
G[3]
0011
A[4]
0100
C[11]
0101-1111
0000 (Default)
0001
Reserved
Disable
B[8]
eTimer_0
ETC5
IMCR[64]
—
I/O-Pad
I/O-Pad
I/O-Pad
0010
G[4]
0011
C[12]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
45
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0100
I/O-Pad
E[13]
0101-1111
0000 (Default)
0001
—
Reserved
Disable
A[4]
eTimer_1
ETC0
IMCR[65]
—
I/O-Pad
I/O-Pad
—
0010
C[15]
0011-1111
0000 (Default)
0001
Reserved
Disable
C[13]
eTimer_1
eTimer_1
ETC1
ETC2
IMCR[66]
IMCR[67]
—
I/O-Pad
I/O-Pad
—
0010
D[0]
0011-1111
0000 (Default)
0001
Reserved
Disable
B[0]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
C[14]
0011
D[1]
0100-1111
0000 (Default)
0001
Reserved
Disable
B[1]
eTimer_1
eTimer_1
ETC3
ETC4
IMCR[68]
IMCR[69]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
D[2]
0011
F[12]
0100-1111
0000 (Default)
0001
Reserved
Disable
A[14]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
D[3]
0011
D[8]
0100
F[13]
0101-1111
0000 (Default)
0001
Reserved
Disable
A[5]
eTimer_1
ETC5
IMCR[70]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
A[15]
0011
D[4]
0100
E[14]
0101-1111
0000 (Default)
0001
Reserved
Disable
H[4]
eTimer_2
eTimer_2
ETC0
ETC1
IMCR[71]
IMCR[72]
—
I/O-Pad
I/O-Pad
—
0010
I[0]
0011-1111
0000 (Default)
0001
Reserved
Disable
H[7]
—
I/O-Pad
I/O-Pad
0010
I[1]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
46
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0011-1111
0000 (Default)
0001
—
—
Reserved
Disable
A[6]
eTimer_2
ETC2
IMCR[73]
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
H[10]
0011
I[2]
0100
J[8]
0101-1111
0000 (Default)
0001
Reserved
Disable
A[7]
eTimer_2
eTimer_2
ETC3
ETC4
IMCR[74]
IMCR[75]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
H[13]
0011
I[3]
0100-1111
0000 (Default)
0001
Reserved
Disable
A[8]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
H[14]
0011
I[9]
0100
J[8]
0101-1111
0000 (Default)
0001
Reserved
Disable
A[9]
eTimer_2
ETC5
IMCR[76]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
H[15]
0011
I[10]
0100
J[9]
0101-1111
0000 (Default)
0001
Reserved
Disable
A[9]
FlexPWM_0
FlexPWM_0
FAULT0
FAULT1
IMCR[83]
IMCR[84]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
A[13]
0011
G[8]
0100-1111
0000 (Default)
0001
Reserved
Disable
C[10]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
D[6]
0011
G[9]
0100-1111
0000 (Default)
0001
Reserved
Disable
D[5]
FlexPWM_0
FlexPWM_0
FAULT2
FAULT3
IMCR[85]
IMCR[86]
—
I/O-Pad
I/O-Pad
—
0010
G[10]
Reserved
Disable
0011-1111
0000 (Default)
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
47
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0001
I/O-Pad
C[5]
0010
I/O-Pad
I/O-Pad
—
D[8]
0011
G[11]
0100-1111
0000 (Default)
0001
Reserved
Disable
C[13]
FlexPWM_0
EXT_SYNC
IMCR[87]
—
I/O-Pad
I/O-Pad
—
0010
C[15]
0011-1111
0000 (Default)
0001
Reserved
Disable
A[11]
FlexPWM_0
FlexPWM_0
FlexPWM_0
A0
B0
A1
IMCR[88]
IMCR[89]
IMCR[91]
—
I/O-Pad
I/O-Pad
—
0010
D[10]
0011-1111
0000 (Default)
0001
Reserved
Disable
A[10]
—
I/O-Pad
I/O-Pad
—
0010
D[11]
0011-1111
0000 (Default)
0001
Reserved
Disable
C[7]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
C[15]
0011
F[0]
0100-1111
0000 (Default)
0001
Reserved
Disable
C[6]
FlexPWM_0
B1
IMCR[92]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
D[0]
0011
D[14]
0100-1111
0000 (Default)
0001
Reserved
Disable
C[4]
FlexPWM_0
FlexPWM_0
X1
A2
IMCR[93]
IMCR[94]
—
I/O-Pad
I/O-Pad
—
0010
D[12]
0011-1111
0000 (Default)
0001
Reserved
Disable
A[11]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
A[12]
0011
G[3]
0100-1111
0000 (Default)
0001
Reserved
Disable
A[12]
FlexPWM_0
B2
IMCR[95]
—
I/O-Pad
I/O-Pad
I/O-Pad
0010
A[13]
0011
G[4]
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
48
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0100-1111
0000 (Default)
0001
—
—
Reserved
Disable
A[10]
FlexPWM_0
X2
A3
IMCR[96]
I/O-Pad
I/O-Pad
—
0010
G[2]
0011-1111
0000 (Default)
0001
Reserved
Disable
A[2]
FlexPWM_0
FlexPWM_0
FlexPWM_0
IMCR[97]
IMCR[98]
IMCR[99]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
C[10]
0011
D[3]
0100
G[6]
0101-1111
0000 (Default)
0001
Reserved
Disable
A[3]
B3
X3
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
A[9]
0011
D[4]
0100
G[7]
0101-1111
0000 (Default)
0001
Reserved
Disable
D[2]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
D[6]
0011
G[5]
0100-1111
0000 (Default)
0001
Reserved
Disable
I[0]
FlexPWM_1
FlexPWM_1
FlexPWM_1
FlexPWM_1
FlexPWM_1
FAULT0
FAULT1
FAULT2
FAULT3
A0
IMCR[100]
IMCR[101]
IMCR[102]
IMCR[103]
IMCR[105]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
I[1]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
I[2]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
I[3]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
C[13]
—
I/O-Pad
I/O-Pad
—
0010
H[5]
0011-1111
0000 (Default)
Reserved
Disable
FlexPWM_1
B0
IMCR[106]
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
49
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0001
I/O-Pad
C[14]
0010
I/O-Pad
—
H[6]
0011-1111
0000 (Default)
0001
Reserved
Disable
F[12]
FlexPWM_1
A1
B1
A2
B2
IMCR[109]
IMCR[110]
IMCR[112]
IMCR[113]
—
I/O-Pad
I/O-Pad
—
0010
H[8]
0011-1111
0000 (Default)
0001
Reserved
Disable
F[13]
FlexPWM_1
FlexPWM_1
FlexPWM_1
—
I/O-Pad
I/O-Pad
—
0010
H[9]
0011-1111
0000 (Default)
0001
Reserved
Disable
A[4]
—
I/O-Pad
I/O-Pad
—
0010
H[11]
0011-1111
0000
Reserved
Disable
E[14]
—
0001
I/O-Pad
I/O-Pad
—
0010
H[12]
0011-1111
0000 (Default)
0001
Reserved
Disable
D[1]
FlexRay
FlexRay
LIN_0
FR_A_RX
FR_B_RX
RXD
IMCR[136]
IMCR[137]
IMCR[165]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
D[2]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
B[3]
—
I/O-Pad
I/O-Pad
—
0010
B[7]
0011-1111
0000 (Default)
0001
Reserved
Disable
B[13]
LIN_1
RXD
IMCR[166]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
D[12]
0011
F[15]
0100-1111
0000 (Default)
0001
Reserved
A[2]
MC_RGM
MC_RGM
ABS0
ABS2
IMCR[169]
IMCR[171]
I/O-Pad
—
Disable
Reserved
A[3]
0010-1111
0000 (Default)
0001
—
I/O-Pad
—
Disable
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
50
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0010-1111
0000 (Default)
0001
—
Reserved
A[4]
MC_RGM
FAB
IMCR[172]
I/O-Pad
—
Disable
Reserved
Disable
A[0]
0010-1111
0000 (Default)
0001
—
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
REQ0
REQ1
REQ2
REQ3
REQ4
REQ5
REQ6
REQ7
REQ8
REQ9
REQ10
REQ11
IMCR[173]
IMCR[174]
IMCR[175]
IMCR[176]
IMCR[177]
IMCR[178]
IMCR[179]
IMCR[180]
IMCR[181]
IMCR[182]
IMCR[183]
IMCR[184]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[1]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[2]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[3]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[4]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[5]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[6]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[7]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[8]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[10]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[11]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[12]
—
I/O-Pad
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
51
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0010-1111
0000 (Default)
0001
—
—
Reserved
Disable
A[13]
SIUL
REQ12
IMCR[185]
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[14]
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
REQ13
REQ14
REQ15
REQ16
REQ17
REQ18
REQ19
REQ20
REQ21
REQ22
REQ23
REQ24
IMCR[186]
IMCR[187]
IMCR[188]
IMCR[189]
IMCR[190]
IMCR[191]
IMCR[192]
IMCR[193]
IMCR[194]
IMCR[195]
IMCR[196]
IMCR[197]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
A[15]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
B[0]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
B[1]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
B[2]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
B[6]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
B[14]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
B[15]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
G[8]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
C[4]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
C[5]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
C[6]
—
I/O-Pad
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
52
NXP Semiconductors
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
0010-1111
0000 (Default)
0001
—
—
Reserved
Disable
E[13]
SIUL
REQ25
IMCR[198]
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
E[14]
SIUL
SIUL
SIUL
SIUL
SIUL
SIUL
SENT_0
REQ26
IMCR[199]
IMCR[200]
IMCR[201]
IMCR[202]
IMCR[203]
IMCR[204]
IMCR[205]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
E[15]
REQ27
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
F[0]
REQ28
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
G[9]
REQ29
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
F[12]
REQ30
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
F[13]
REQ31
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
D[5]
SENT_RX[0]
—
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
I[7]
0011
G[8]
0100-1111
0000 (Default)
0001
Reserved
Disable
I[11]
SENT_0
SENT_1
SENT_RX[1]
SENT_RX[0]
IMCR[206]
IMCR[213]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
J[5]
0011
A[9]
0100
G[10]
0101-1111
0000 (Default)
0001
Reserved
Disable
D[7]
—
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
I[8]
0011
G[9]
0100
C[12]
0101-1111
Reserved
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
53
Pinouts
Table 10. Peripheral muxing (continued)
Destination
peripheral
Destination
functions
IMCR number
IMCR[SSS] field value
Source
peripherals
Source functions
SENT_1
SENT_RX[1]
IMCR[214]
0000 (Default)
0001
—
Disable
I[12]
I/O-Pad
I/O-Pad
I/O-Pad
I/O-Pad
—
0010
J[6]
0011
A[10]
0100
G[11]
0101-1111
0000 (Default)
0001
Reserved
Disable
D[8]
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
ENET_0
RX_CLK
RX_DV
RX_D0
RX_D1
RX_D2
RX_D3
COL
IMCR[224]
IMCR[225]
IMCR[226]
IMCR[227]
IMCR[228]
IMCR[229]
IMCR[230]
IMCR[231]
IMCR[232]
IMCR[233]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
D[7]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
D[6]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
D[5]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
H[8]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
J[9]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
H[5]
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
H[4]
CRS
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
I[1]
RX_ER
TX_CLK
—
I/O-Pad
—
0010-1111
0000 (Default)
0001
Reserved
Disable
G[8]
—
I/O-Pad
—
0010-1111
Reserved
1. (Default) = configuration after reset
2. Selecting an alternate function with a 'Reserved' source function causes the pin to enter a null state (Input buffer and
Output buffer enables both at 0).
MPC5744P Data Sheet, Rev. 6.1, 11/2017
54
NXP Semiconductors
Electrical characteristics
Table 11. Peripheral muxing example
SSS field value in IMCR[214]
Result
0001
0010
I/O-Pad I[12] is connected to SENT_1 Receive input SENT_RX[1]
I/O-Pad J[6] is connected to SENT_1 Receive input SENT_RX[1]
See Table 9 concerning the availability of port pins on the packages.
3 Electrical characteristics
3.1 Introduction
This section contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for this device.
This device is designed to operate at 200 MHz.
3.2 165°C junction temperature option
For orderable parts whose device marking shows they support this extended temperature
option:
• Operation at 150°C < TJ < 165°C is allowed for a maximum cumulative time of 200
hours over the device lifetime.
• Production parameters at 165°C reflect testing over an ambient temperature range of
–40°C to 150°C with appropriate guardbanding to guarantee operation at 165°C.
3.3 Absolute maximum ratings
NOTE
Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maximum values is not
guaranteed.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
55
Electrical characteristics
CAUTION
Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
Table 12. Absolute maximum ratings
Symbol
VDD_LV
Parameter
Conditions
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.1
–0.3
–0.1
–0.3
–0.1
–0.3
Max
1.5
Unit
V
1.25 V core supply voltage1, 2, 3
1.25 V PLL supply voltage1, 2, 3
1.25 V LFAST PLL supply voltage1, 2, 3
—
—
—
—
—
—
—
—
—
—
—
—
VDD_LV_PLL
VDD_LV_LFAST
1.5
V
1.5
V
VDD_LV_NEXUS 1.25 V Aurora LVDS supply voltage1, 2, 3
1.5
V
VDD_HV_PMU
VDD_HV_IO
3.3 V voltage regulator supply voltage
3.3 V input/output supply voltage
Input/output ground voltage
4.04, 5
3.634, 5
0.1
V
V
VSS_HV_IO
V
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_OSC
VSS_HV_OSC
VDD_HV_ADRE0
3.3 V flash supply voltage
3.634, 5
V
Flash memory ground
0.1
V
3.3 V crystal oscillator amplifier supply voltage
3.3 V crystal oscillator amplifier ground
3.3 V / 5.0 V ADC_0 high reference voltage
4.04, 5
0.1
V
V
6
6
V
VDD_HV_ADRE1 3.3 V / 5.0 V ADC_1 high reference voltage
VSS_HV_ADRE0 ADC_0 ground and low reference voltage
VSS_HV_ADRE1 ADC_1 ground and low reference voltage
—
–0.1
0.1
V
VDD_HV_ADV
VSS_HV_ADV
TVDD
3.3 V ADC supply voltage
3.3 V ADC supply ground
—
—
—
—
–0.3
–0.1
4.04, 5
0.1
V
V
Supply ramp rate
0.9 V/s
–0.3
0.06 V/µs
6
VINA
Voltage on analog pin with respect to ground
V
V
(VSS_HV_IO
Voltage on any digital pin with respect to ground
(VSS_HV_IO
)
VIN
Relative to
VDD_HV_IO
–0.3
VDD_HV_IO
0.3, 7
+
)
IINJ
Maximum DC injection current per pin, 5 V ADC pads
Note 8
–5
5
mA
mA
IINJPAD
Injected input current on any pin during overload
condition
—
–10
10
IINJSUM
TSTG
Absolute sum of all injected input currents during
overload condition
—
—
–50
–55
50
mA
°C
Storage temperature
165
1. 1.45 V to 1.5 V allowed for 60 seconds cumulative time at maximum TJ=165°C; remaining time as defined in note -1 and
note -1.
2. 1.375 V to 1.45 V allowed for 10 hours cumulative time at maximum TJ=165°C; remaining time as defined in note -1.
3. 1.32 V to 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at
maximum TJ=165°C.
4. 5.3 V for 10 hours cumulative over lifetime of device; 3.3 V +10% for time remaining.
5. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
6. VDD_HV_ADRE0 and VDD_HV_ADRE1 cannot be operated at different voltages and must be supplied by the same voltage
source.
7. Only when VDD_HV_IO < 3.63 V.
8. The following conditions apply:
• Absolute maximum supply: VDD_HV_ADREx = 6.0 V (60 seconds lifetime, no restrictions—part can switch)
MPC5744P Data Sheet, Rev. 6.1, 11/2017
56
NXP Semiconductors
Electrical characteristics
• Absolute maximum supply: VDD_HV_ADREx = 6.0 V (10 hours, device in reset—no switching)
• Absolute maximum supply: VDD_HV_ADREx = 5.5 V (always)
• Absolute maximum ADC input pin voltage = 7.0 V (60 seconds lifetime), when VDD_HV is connected to the 5 V
• Absolute maximum ADC input pin voltage = 6.5 V (always while respecting 5 mA maximum injection), when VDD_HV
is connected to the 5 V
3.4 Recommended operating conditions
NOTE
Full functionality cannot be guaranteed when voltage drops
below 3.0 V. In particular, ADC electrical characteristics and
DC electrical specifications for I/Os might not be guaranteed.
Table 13. Recommended operating conditions (VDD_HV_xx = 3.3 V)
Symbol
Parameter
Conditions
Min
3.15
3.15
0
Max
3.6
3.6
0
Unit
V
1
VDD_HV_PMU
3.3 V voltage regulator supply voltage
3.3 V input/output supply voltage
Input/output ground voltage
—
2
VDD_HV_IO
—
V
VSS_HV_IO
—
V
3
VDD_HV_FLA
3.3 V flash supply voltage
—
3.15
0
3.6
0
V
VSS_HV_FLA
Flash memory ground
—
V
4
VDD_HV_OSC
VSS_HV_OSC
3.3 V crystal oscillator amplifier supply voltage
3.3 V crystal oscillator amplifier ground
—
—
3.15
0
3.6
0
V
V
VDD_HV_ADRE0 3.3 V / 5.0 V ADC_0 high reference voltage
TJ ≤ 150°C
3.15 to 5.5
V
VDD_HV_ADRE1 3.3 V / 5.0 V ADC_1 high reference voltage
5
VDD_HV_ADRE0
3.3 V / 5.0 V ADC_0 high reference voltage
150°C < TJ < 165°C
(only for
3.15 to 5.25
V
V
VDD_HV_ADRE1 3.3 V / 5.0 V ADC_1 high reference voltage
corresponding
marked parts)
5
VSS_HV_ADRE0
ADC_0 ground and low reference voltage
—
0
0
VSS_HV_ADRE1 ADC_1 ground and low reference voltage
6
VDD_HV_ADV
3.3 V ADC supply voltage
3.3 V ADC supply ground
Core supply, 1.25 V +/-5%
Internal supply voltage
—
3.15
0
3.6
0
V
V
VSS_HV_ADV
—
7
VDD_LV_COR
VDD_LV_CORx
VSS_LV_CORx
VDD_LV_PLL
VSS_LV_PLL
—
1.19
—
1.32
—
V
—
V
Internal reference voltage
Internal PLL supply voltage
Internal PLL reference voltage
—
0
0
V
—
1.19
0
1.32
0
V
—
V
VDD_LV_NEXUS Aurora LVDS supply voltage
VSS_LV_NEXUS Aurora LVDS supply ground
—
1.19
0
1.32
0
V
—
—
V
VDD_LV_LFAST
VSS_LV_LFAST
IIC
LFAST PLL supply voltage
LFAST PLL supply ground
DC injection current per pin8, 9, 10
1.19
0
1.32
0
V
—
V
Digital pins
Analog pins
–3.0
–3.0
3.0
3.0
mA
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
57
Electrical characteristics
Table 13. Recommended operating conditions (VDD_HV_xx = 3.3 V) (continued)
Symbol
Parameter
Conditions
Shared analog pins
fCPU≤ 200MHz
—
Min
–3.6
–40
–40
Max
Unit
3.6
TA
TJ
Ambient temperature under bias
Junction temperature under bias
13511
16512, 13
°C
°C
1. The chip functions down to the point where LVD_PMC resets the chip. When the voltage drops below LVD_PMC, the chip
resets.
2. The chip functions down to the point where LVD_IO resets the chip. When the voltage drops below LVD_IO, the chip
resets.
3. The chip functions down to the point where LVD_FLASH resets the chip. When the voltage drops below LVD_FLASH, the
chip resets.
4. The chip functions down to the point where LVD_OSC resets the chip. When the voltage drops below LVD_OSC, the chip
resets.
5. VDD_HV_ADRE0 and VDD_HV_ADRE1 cannot be operated at different voltages and need to be supplied by the same voltage
source.
6. The chip functions down to the point where LVD_ADC resets the chip. When the voltage drops below LVD_ADC, the chip
resets.
7. The chip functions down to the point where LVD_CORE or up to the point where HVD_CORE resets the chip by default.
8. I/O and analog input specifications are valid only if the injection current on adjacent pins is within these limits. See the
absolute maximum ratings table for maximum input current for reliability requirements.
9. Full device lifetime without performance degradation.
10. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is
above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network
calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
11. For a maximum TJ of 150°C, the corresponding maximum TA is 125°C.
12. Some orderable parts have a maximum TJ value of 150°C. See the device marking for the applicable temperature range.
13. For devices supporting the 165°C junction temperature option: Operation at 150°C < TJ < 165°C is allowed for a maximum
cumulative time of 200 hours over the device lifetime.
3.5 Thermal characteristics
Table 14. Thermal characteristics for 144LQFP and 257MAPBGA packages
Symbol
Parameter
Conditions
144LQFP
257MAPBGA
Unit
RθJA
Thermal resistance, junction-to-ambient
natural convection2
Single layer board - 1s
39
31
31
25
18
8
45
25
36
21
13
8
°C/W
Four layer board - 2s2p
Single layer board - 1s3
Four layer board - 2s2p4
RθJMA
Thermal resistance, junction-to-ambient
forced convection at 200 ft/min1
°C/W
RθJB
RθJC
ΨJT
Thermal resistance junction-to-board5
Thermal resistance junction-to-case6
—
—
—
°C/W
°C/W
°C/W
Junction-to-package-top natural
convection7
2
2
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
4. Per JEDEC JESD51-6 with the board horizontal.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
58
NXP Semiconductors
Electrical characteristics
5. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package. Board temperature is measured on the top surface of the board near the package.
6. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
7. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
3.5.1 General notes for specifications at maximum junction
temperature
An estimation of the chip junction temperature, TJ, can be obtained from this equation:
TJ = TA + (RθJA × PD)
where:
• TA = ambient temperature for the package (°C)
• RθJA = junction to ambient thermal resistance (°C/W)
• PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which value is closer to the application depends on the power dissipated
by other components on the board. The value obtained on a single layer board is
appropriate for the tightly packed printed circuit board. The value obtained on the board
with the internal planes is usually appropriate if the board has low power dissipation and
the components are well separated.
When a heat sink is used, the thermal resistance is expressed in the following equation as
the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
• RθJA = junction to ambient thermal resistance (°C/W)
• RθJC = junction to case thermal resistance (°C/W)
• RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RθCA. For instance, the
user can change the size of the heat sink, the air flow around the device, the interface
material, the mounting arrangement on printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
59
Electrical characteristics
To determine the junction temperature of the device in the application when heat sinks
are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using this equation:
TJ = TT + (ΨJT × PD)
where:
• TT = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a
40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
3.5.1.1 References
Semiconductor Equipment and Materials International; 3081 Zanker Road; San Jose, CA
95134 USA; (408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global
Engineering Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the Web at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA
Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San
Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-
Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board
Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of
SemiTherm, San Diego, 1999, pp. 212–220.
3.6 Electromagnetic compatibility (EMC)
Tests were carried out in accordance with the International Electrotechnical Commission
specifications:
MPC5744P Data Sheet, Rev. 6.1, 11/2017
60
NXP Semiconductors
Electrical characteristics
• IEC 61967: Integrated Circuits, Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz
• IEC 61967-2: Measurement of radiated emissions – TEM-cell and wideband TEM-
cell method
Conditions1
Classification
Parameter
Test #
Unit
level2
Comm. modules3
GPIO
1
2
On
On
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off, input pull-up
L
L
L
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
dBμV
Off, input pull-up
3
Off, input pull-up
4
4
Off, input pull-up
—
5
Off, input pull-up
PG15 input, pull-up
L
L
L
L
L
L
I
6
7
PG15 output high, half drive
PG15 output high, full drive
PG15 output low, half drive
PG15 output low, full drive
All I/O tri-stated
VEME
8
9
10
11
12
13
14
15
PG26 toggle @ 5 kHz, half drive, SR off
PG26 toggle @ 5 kHz, half drive, SR on
PG26 toggle @ 5 kHz, full drive, SR off
PG26 toggle @ 5 kHz, full drive, SR on
L
L
L
I
1. All tests ran with core and bus frequency at 200 MHz. Test #2 had "weak" FM modulation and Test #3 had "strong" FM
modulation.
2. I = Class 1 (36 dBµV), L = Class 2 (24 dBµV), N = Class 3 (12 dBµV)
3. LINFlex0/1 running at 19.2 kbd, SPI0 running at 2.5 MHz, SPI1 running at 7.5 MHz, SPI2 running at 4.5 MHz, CAN0/1
running at 500 kbd
4. Test #4 values were slightly above class I level.
5. PG1 = port group 1: pins F[3:15]
6. PG2 = port group 2: pins A[2:4], C[11:14], D14, F12, G6, J8
Each of the tests ran once across each of the following frequency bands.
Sweep time
(ms/MHz)
Frequency band
RBW (kHz)
VBW (kHz)
Pre-amplifier
Detector
150 kHz to 30 MHz
9
30
5
ON (–20 dB)
Peak-Average
30 MHz to 1000 MHz
120
300
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61
Electrical characteristics
3.7 Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
NOTE
A device will be defined as a failure if after exposure to ESD
pulses the device no longer meets the device specification
requirements.
Table 15. ESD ratings
No.
Symbol
Parameter
Conditions1
Class
Max value
Unit
1
VESD(HBM) Electrostatic discharge
(Human Body Model)
TA = 25 °C
H1C
2000
V
conforming to AEC-Q100-002
TA = 25 °C
2
VESD(CDM) Electrostatic discharge
(Charged Device Model)
C3A
500
V
conforming to AEC-Q100-011
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
3.8 Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
• High power regulator (external NPN to support core current)
• Low voltage detector (LVD_IO) for 3.3 V supply to IO (VDD_HV_IO
• Low voltage detector (LVD_PMC) for 3.3 V supply (VDD_HV_PMU
• Low voltage detector (LVD_FLASH) for 3.3 V flash memory supply (VDD_HV_FLA
• Low voltage detector (LVD_ADC) for 3.3 V ADC supply (VDD_HV_ADV
• Low voltage detector (LVD_OSC) for 3.3 V OSC supply (VDD_HV_OSC
)
)
)
)
)
• Low voltage detector (LVD_CORE) for 1.25 V digital core supply (VDD_LV
• Low voltage detector (LVD_CORE_BK) for the self-test of LVD_CORE
)
• High voltage detector (HVD_CORE) for 1.25 V digital core supply (VDD_LV
)
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Electrical characteristics
• High voltage detector (HVD_CORE_BK) for the self-test of HVD_CORE
• Power on Reset (POR)
NOTE
When the external regulator mode is used either the
EXT_POR_B signal needs to be driven by external circuitry
until all power supplies are in recommended ranges or the
internal LVDs keep the device in POR until all power supply
are in recommended range. There needs to be used the external
over voltage detectors for all power supplies in both regulator
modes for safety operation.
The following bipolar transistor is supported:
• ON Semiconductor™ NJD2873 (requires a heat sink to operate up to 165 °C): See
Table 16.
Table 16. Recommended operating characteristics: NJD2873
Symbol
hFE
Parameter
Value
60-550
1.60
2.0
Unit
—
W
DC current gain (Beta)
PD
Absolute minimum power dissipation
Minimum peak collector current
Collector to emitter saturation voltage
Base to emitter voltage
ICMaxDC
VCESAT
VBE
A
300
mV
V
0.95
2.5
Vc
Minimum voltage at transistor collector
V
Table 17. Voltage regulator electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Cld
External decoupling / stability capacitor
Min value granted with
respect to tolerance, voltage,
temperature, and aging
variations. 4 capacitors are
recommended – one for each
side of the chip.
4
—
18.8
µF
—
Combined ESR of external capacitor
—
0.03
—
—
—
0.15
2.5
Ω
tSU
Start-up time after main supply
stabilization
Cld = 4 µF
ms
Lbw
Rbw
Rsd
Bonding inductance
—
—
—
—
—
—
—
—
—
13
0.5
0.1
nH
Ω
Bonding wire and pad resistance
Series resistance of on-chip power grid
Ω
Table continues on the next page...
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NXP Semiconductors
63
Electrical characteristics
Table 17. Voltage regulator electrical specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Cpd
Parallel decoupling capacitor
Per pin; must use at least 6
capacitors, but total of all
capacitors must be no more
than 300 nF
47
—
300
nF
—
Power supply rejection
(Cld = 4 µF)
@DC no load
@200 kHz no load
@DC 400 mA
@200 kHz 400 mA
Iload from 20% to 80%
Cld = 4 µF
—
—
–23
–23
–23
–23
—
dB
µs
—
—
—
Load current transient time
1.0
—
—
—
Supply ramp rate
VDD_LV_COR
Supply ramp rate
VDD_HV_PMU
POR_COR
—
0.01
V/ms
0.125
V/µs
—
0.9 V/s
0.06 V/
μs
—
—
—
—
—
—
—
—
—
—
—
—
—
0.98
2.4
1.02
2.59
1.15
1.36
3.02
3.02
3.02
3.02
3.02
10
1.08
2.76
1.18
1.40
3.13
3.13
3.13
3.13
3.13
—
V
V
POR_PMU
—
LVD_CORE, LVD_CORE_BK
HVD_CORE, HVD_CORE_BK
LVD_PMC
calibrated (trimmed)
calibrated (trimmed)
calibrated (trimmed)
calibrated (trimmed)
calibrated (trimmed)
calibrated (trimmed)
calibrated (trimmed)
—
1.12
1.32
2.93
2.93
2.93
2.93
2.93
—
V
V
V
LVD_IO
V
LVD_FLASH
V
LVD_ADC
V
LVD_OSC
V
Hysteresis LVD_CORE
Hysteresis HVD_CORE
mV
mV
mV
—
—
—
—
Hysteresis LVD_PMC, LVD_IO,
—
—
20
—
LVD_FLASH, LVD_ADC, LVD_OSC
—
TJ
LVD/HVD trimming
16 steps
—
—
5
—
mV
°C
Junction Temperature
–40
—
165
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Electrical characteristics
VDD_HV_PMU
Cld 4μ
BCTRL
Cpd
47n
Lbw
Package
Rbw
Cpd
47n
Rbw
Lbw
Lbw
Rbw
Rsd
Die
Cpd
47n
Rbw
Lbw
Cpd
47n
Figure 4. Core supply decoupling and parasitics
3.9 DC electrical characteristics
The following tables provide DC characteristics for bidirectional pads:
• Table 18 provides output driver characteristics FlexRay I/Os (SYM).
• Table 19 provides output driver characteristics for LFAST I/Os.
NOTE
See the FlexRay section for parameters dedicated to this
interface.
Table 18. FlexRay (SYM) configuration output buffer electrical characteristics
Symbol
ROH_Y
ROL_Y
Parameter
Conditions1
Value
Typ
50
Unit
Ω
Min
Max
PMOS output impedance
SYM configuration
Push Pull, IOH = 2 mA,
35
65
VOH = VDD_HV_IO–(0.28...0.52V)
Push Pull, IOL = 2 mA,
VOL = 0.28...0.52 V
PMOS output impedance
SYM configuration
35
50
65
Ω
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NXP Semiconductors
65
Electrical characteristics
Table 18. FlexRay (SYM) configuration output buffer electrical characteristics
(continued)
Symbol
Fmax_Y
Ttr_Y
Parameter
Conditions1
Value
Typ
—
Unit
MHz
ns
Min
Max
Output frequency
CL = 20 pF, VDD_HV_IO=3.3 V
–5%, +10%
—
50
SYM configuration
Transition time output pin
SYM configuration
CL = 20 pF, VDD_HV_IO=3.3 V
–5%, +10%
1
0
—
—
6
1
|Tskew_Y
|
Difference between rise
and fall time
—
ns
1. VDD_HV_IO = 3.3 V (–5%, +10%), TJ = –40 to 165 °C, unless otherwise specified.
NOTE
See the LFAST section for parameters dedicated to this
interface.
Table 19. LFAST output buffer electrical characteristics
Symbol
Parameter
Conditions1
Value
Typ
Unit
Min
Max
|ΔVO_L
|
Absolute value for differential output voltage
swing (terminated)
—
100
200
285
mV
VICOM_L Common mode voltage
Ttr_L Transition time output pin LVDS configuration
—
—
1.08
0.2
1.2
—
1.32
1.5
V
ns
1. VDD_HV_IO = 3.3 V (–5%, +10%), TJ = –40 to 165 °C, unless otherwise specified.
NOTE
Fast IOs must be specified only as fast (and not as high
current). See Table 20.
Table 20. DC electrical specifications
Symbol
Parameter
Conditions
Value
Typ
—
Unit
Min
1.19
3.15
Max
1.32
3.6
VDD_LV
VDD_HV_IO
VIH
LV (core) Supply Voltage
—
—
—
V
V
V
1
I/O Supply Voltage
—
CMOS Input Buffer High Voltage (with hysteresis
disabled)
0.55 *
VDD_HV_IO
—
VDD_HV_IO
+ 0.3
VIL
CMOS Input Buffer Low Voltage (with hysteresis
disabled)
—
—
Vss - 0.3
—
—
0.40 *
VDD_HV_IO
V
V
VHYS
CMOS Input Buffer Hysteresis
0.1 *
—
VDD_HV_IO
Pull_IOH
Pull_IOL
Weak Pullup Current2
Weak Pulldown Current3
—
—
10
10
—
—
80
80
µA
µA
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Electrical characteristics
Table 20. DC electrical specifications (continued)
Symbol
Parameter
Conditions
Value
Typ
—
Unit
Min
Max
2.5
—
IINACT_D
VOH
Digital Pad Input Leakage Current (weak pull inactive)4
Output High Voltage5
—
—
-2.5
µA
V
0.8 *
—
VDD_HV_IO
VOL
Output Low Voltage6
—
—
—
0.2 *
V
VDD_HV_IO
IOH_F
IOL_F
IOH_H
IOL_H
Full drive IOH (SIUL2_MSCRn's SRC[1:0] field is 11b)
Full drive IOL (SIUL2_MSCRn's SRC[1:0] field is 11b)
Half drive IOH (SIUL2_MSCRn's SRC[1:0] field is 10b)
Half drive IOL (SIUL2_MSCRn's SRC[1:0] field is 10b)
—
—
—
—
10
21
—
—
—
—
180
230
90
mA
mA
mA
mA
9
10.5
115
1. Max power supply ramp rate is 100 V / ms
2. Measured when pad = 0 V
3. Measured when pad = VDD_HV_IO
4. The specified values apply to all pads except D[7] (SGEN output pad). For D[7], leakage current specifications are -15μA
Min and 15μA Max.
5. Measured when pad is sourcing 2 mA
6. Measured when pad is sinking 2 mA
3.10 Supply current characteristics
Current consumption data is given in the following table.
Table 21. Current consumption characteristics
Symbol
IDD_LV
Parameter
Conditions1
Min Typ Max Unit
Operating current
TA = 25 °C
—
—
—
—
350 400 mA
2
+ IDD_LV_PLL
VDD_LV_COR = 1.32 V
TJ = 150 °C
440 570
VDD_LV_COR = 1.32 V
TJ = 165 °C
470 610
VDD_LV_COR = 1.32 V
Normal startup self-test
TA = 25 °C
IDD_LV_BIST
Operating current
340
—
mA
+ IDD_LV_PLL
VDD_LV_COR = 1.32 V
TJ = 150 °C
—
—
—
410
430
25
—
—
35
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
TA = 25 °C
IDD_LV_STOP
Operating current in
VDD STOP mode
mA
VDD_LV_COR = 1.32 V
Table continues on the next page...
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NXP Semiconductors
67
Electrical characteristics
Table 21. Current consumption characteristics (continued)
Symbol
Parameter
Conditions1
Min Typ Max Unit
90 230
TJ = 150 °C
—
—
—
—
—
—
—
—
—
—
VDD_LV_COR = 1.32 V
TJ = 165 °C
120 310
VDD_LV_COR = 1.32 V
TA = 25 °C
IDD_LV_HALT
Operating current in
VDD HALT mode
25
40
mA
VDD_LV_COR = 1.32 V
TJ = 150 °C
110 300
140 400
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
TJ = 150 °C
IDD_LV_LFAST
Operating current
Operating current
Operating current
—
—
6.6
6.8
mA
VDD_LV_COR = 1.32 V
TJ = 165 °C
VDD_LV_COR = 1.32 V
TJ = 150 °C
IDD_LV_NEXUS
—
12.1 mA
12.5
VDD_LV_COR = 1.32 V
TJ = 165 °C
—
VDD_LV_COR = 1.32 V
TJ = 150 °C
3
IDD_HV_ADV
3.4
4.2
4.5
mA
4 ADCs operating at 80 MHz
VDD_HV_ADV = 3.6 V
TJ = 165 °C
—
—
—
—
—
—
3.5
4 ADCs operating at 80 MHz
VDD_HV_ADV = 3.6 V
TJ = 150 °C
, 4
IDD_HV_ADRE
Operating current
0.20 0.28 mA
0.32 0.50
ADC operating at 80 MHz
VDD_HV_ADRE = 3.6 V
TJ = 150 °C
ADC operating at 80 MHz
VDD_HV_ADRE = 5.5 V
TJ = 165 °C
0.24 0.40
ADC operating at 80 MHz
VDD_HV_ADRE = 3.6 V
TJ = 165 °C
0.40 0.70
ADC operating at 80 MHz
VDD_HV_ADRE = 5.5 V
TJ = 150 °C
IDD_HV_OSC
Operating current
—
1.6
mA
3.3 V supplies
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Electrical characteristics
Table 21. Current consumption characteristics (continued)
Symbol
Parameter
Conditions1
Min Typ Max Unit
Frequency: 200MHz
TJ = 165 °C
3.3 V supplies
—
—
—
—
—
—
1.8
5.5
7.0
Frequency: 200MHz
TJ = 150 °C
IDD_HV_FLA
Operating current
mA
3.3 V supplies
Frequency: 200MHz
TJ = 165 °C
3.3 V supplies
Frequency: 200MHz
1. The content of the Conditions column identifies the components that draw the specific current.
2. Enabled modules: ADC0/1, FlexPWM0, eTimer0, two SPIs, two FlexCANs, FlexRay, one LINFlexD, DMA. At maximum
frequency. I/O supply current excluded.
3. Internal structures hold the input voltage less than VDD_HV_ADV + 1.0 V on all pads powered by VDDA supplies, if the
maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.
4. This value is the total current for two ADCs.
3.11 Temperature sensor
The following table describes the temperature sensor electrical characteristics.
Table 22. Temperature sensor electrical characteristics
Symbol
—
Parameter
Temperature monitoring range
Conditions
Min Typ Max
Unit
°C
—
—
–40
—
—
5.18
—
165
—
TSENS
TACC
Sensitivity
mV/°C
°C
Accuracy for linear temperature sensor
TJ = –40 to 150 °C
TJ = 150 to 165 °C
TJ = –40 to 150 °C
TJ = –40 to 150 °C
–3
+3
+5
+5
1.0
–5
—
—
—
Accuracy for temperature-threshold digital flags
–5
—
°C
°C
Temperature variation for each customer-adjustable
trim step
0.4
0.7
—
Operating current
TJ = –40 to 165 °C
—
—
675
µA
3.12 Main oscillator electrical characteristics
This device provides a driver for the oscillator in pierce configuration with amplitude
control. Controlling the amplitude allows a more sinusoidal oscillation, reducing EMI
and power consumption. This Loop Controlled Pierce (LCP mode) requires good
practices to reduce the stray capacitance of traces between the crystal and the MCU.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
69
Electrical characteristics
An operation in Full Swing Pierce (FSP mode), implemented by an inverter, is also
available in cases of parasitic capacitances that cannot be reduced or of using a crystal
with high equivalent series resistance. This mode requires special care regarding the
serial resistance used to avoid the crystal overdrive.
Two other provided modes are External (EXT Wave) and disable (OFF mode). For EXT
Wave, the drive is disabled and an external clock source within the CMOS level based in
the analog oscillator supply can be used. When OFF, the EXTAL is pulled down by a
240-kohm resistor and the feedback resistor remains active, connecting XTAL through
EXTAL by a 1M resistor.
The following figure describes a simple model of the internal oscillator driver and
provides an example of connections for an oscillator.
NOTE
When selecting C1 and C2 in your oscillator circuit, contact the
crystal manufacturer for their recommended values. Capacitor
loading of the oscillator must be fully characterized at the
system level to ensure proper operation.
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Electrical characteristics
Figure 5. Oscillator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external
circuits.
Table 23. Main oscillator electrical characteristics
Symbol
fXOSCHS
Parameter
Mode
FSP/LCP
LCP
Conditions1
Min
42
Typ
—
Max
40
Unit
MHz
Oscillator frequency
Driver transconductance
—
gmXOSCHS
VDD_HV_OSC = 3.3V
–5%, +10%
—
20
—
mA/V
FSP
—
30
—
VXOSCHS
Oscillation amplitude
Oscillator startup time
LCP
fOSC = 4, 8, 16 MHz
fOSC = 40 MHz
1.1
1.2
1.75
0.25
1.3
1.5
2.5
0.5
2.6
1.7
2.9
1.1
V
V
TXOSCHSSU
FSP/LCP3 fOSC = 4 MHz
ms
ms
fOSC = 8, 16, 40 MHz
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71
Electrical characteristics
Table 23. Main oscillator electrical characteristics (continued)
Symbol
Parameter
Mode
Conditions1
Min
Typ
Max
Unit
VIH
Input high level CMOS Schmitt EXT Wave Oscillator bypass mode
Trigger
—
1.48
—
V
VIL
Input low level CMOS Schmitt EXT Wave Oscillator bypass mode
Trigger
—
—
1.85
0.37
—
—
V
V
VHYS
Input low level CMOS Schmitt EXT Wave Oscillator bypass mode
hysteresis
1. VDD_HV_OSC = 3.3 V –5%, +10%, TJ = 27 °C, unless otherwise specified
2. When using XOSC as the source for PLL0IN, the minimum frequency requirement of the PLL must be fulfilled as stated in
the PLL0 electrical characteristics.
3. Values are very dependent on crystal or resonator used and parasitic capacitance observed in the board.
3.13 PLLDIG electrical characteristics
PLL0_PHI0
IRCOSC
PLL0
PLL0_PHI1
XOSC
PLL1_PHI0
PLL1
Figure 6. PLL integration
Table 24. PLL0 electrical characteristics
Symbol
fPLL0IN
Parameter
Conditions1
Min Typ Max
Unit
MHz
%
PLL0 input clock
PLL0 input clock duty cycle2
PLL0 VCO frequency
—
8
40
—
—
—
—
—
—
—
40
60
PLL0IN
—
fPLL0VCO
fPLL0PHI0
fPLL0PHI1
tPLL0LOCK
|PLL0PHISPJ
—
600
4.76
20
1250 MHz
PLL0 output clock PHI0
PLL0 output clock PHI1
PLL0 lock time
—
200
156
100
200
MHz
MHz
µs
—
—
—
|
PLL0_PHI single period jitter
fPLL0IN = 20 MHz (resonator)
PLL0_PHI1 single period jitter
fPLL0IN = 20 MHz (resonator)
PLL0 output long term jitter3
fPLL0PHI = 400 MHz, 6-sigma
—
ps
|PLL0PHI1SPJ
|
fPLL0PHI1 = 40 MHz, 6-sigma
—
—
—
—
300
250
ps
ps
PLL0LTJ
10 periods accumulated jitter (80 MHz
equivalent frequency), 6-sigma pk-pk
fPLL0IN = 20 MHz (resonator),
VCO frequency = 800 MHz
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
72
NXP Semiconductors
Electrical characteristics
Table 24. PLL0 electrical characteristics (continued)
Symbol
Parameter
Conditions1
Min Typ Max
Unit
16 periods accumulated jitter (50 MHz
equivalent frequency), 6-sigma pk-pk
—
—
—
—
—
—
300
500
5
ps
long term jitter (< 1 MHz equivalent
frequency), 6-sigma pk-pk)
ps
IPLL0
PLL0 consumption
FINE LOCK state
mA
1. VDD_LV =1.25 V 5%, TJ = -40 to 165 °C unless otherwise specified.
2. PLL0IN clock retrieved directly from either IRCOSC or external XOSC clock. Input characteristics are granted when using
IRCOSC or when external oscillator is used in functional mode.
3. VDD_LV noise due to application in the range VDD_LV = 1.25 V 5%, with frequency below PLL bandwidth (40 kHz) will be
filtered.
Table 25. FMPLL1 electrical characteristics
Symbol
fPLL1IN
Parameter
Conditions1
Min Typ Max
Unit
MHz
%
PLL1 input clock
—
38
35
—
—
—
—
—
—
—
—
—
78
65
PLL1IN
PLL0 input clock duty cycle2
PLL1 VCO frequency
—
fPLL1VCO
fPLL1PHI0
tPLL1LOCK
fPLL1MOD
|δPLL1MOD
—
600
4.76
—
1250 MHz
PLL1 output clock PHI0
PLL1 lock time
—
—
200
100
250
2
MHz
µs
PLL1 modulation frequency
PLL1 modulation depth (when enabled)
—
—
kHz
%
|
Center spread
Down spread
FINE LOCK state
0.25
0.5
—
4
%
IPLL1
PLL1 consumption
6
mA
1. VDD_LV = 1.25 V 5%, TJ = -40 to 165 °C unless otherwise specified.
2. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when
using internal PLL0 or when external oscillator is used in functional mode.
3.14 16 MHz Internal RC Oscillator (IRCOSC) electrical
specifications
NOTE
Unless stated otherwise, specifications in Table 26 assume the
following: VDD_HV_PMU=3.15V to 3.6V, VSS=0V,
VDD_LV=1.18V to 1.32V, VSS=0V, TJ=–40 to 165°C.
Table 26. Internal RC Oscillator electrical specifications
Symbol
fTarget
Parameter
IRCOSC target frequency
IRCOSC frequency (untrimmed)
Conditions
Min
—
Typ
16
Max
—
Unit
MHz
MHz
—
—
fUntrimmed
11
—
17
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
73
Electrical characteristics
Table 26. Internal RC Oscillator electrical specifications (continued)
Symbol
Parameter
Conditions
TJ < 150 °C
TJ < 165 °C
TJ < 150 °C
TJ < 165 °C
—
Min
Typ
—
—
—
—
—
—
—
Max
3
Unit
δfvar
IRC frequency variation with temperature and
voltage compensation
-3
%
-4
4
1
δfvar_noT
IRC frequency variation without temperature
compensation (only voltage compensation)
–8
–10
—
8
%
10
5
Tstartup
IVDD3
Startup time without temperature compensation
Current consumption on 3.3 V power supply
Current consumption on 1.2 V power supply
µs
µA
µA
After Tstartup
After Tstartup
—
55
270
IVDD12
—
1. The typical user trim step size (dfTRIM) is +48kHz for frequencies trimmed above nominal and -40kHz for frequencies
trimmed below nominal based on characterization results.
3.15 ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-
Digital Converter.
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
(2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
(5)
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal
)
Offset Error OSE
Figure 7. ADC characteristics and error definitions
MPC5744P Data Sheet, Rev. 6.1, 11/2017
74
NXP Semiconductors
Electrical characteristics
3.15.1 Input equivalent circuit and ADC conversion characteristics
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
DD_HV_ADREn
V
Channel
Selection
Sampling
Source
Filter
Current Limiter
R
R
R
R
R
S
F
L
SW1
AD
C
V
C
C
P1
C
S
A
F
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 8. Input equivalent circuit
NOTE
Unless noted otherwise, the specifications in Table 27 assume
the use of 12-bit resolution (high accuracy, recommended): In
ADC_CALBISTREG, set OPMODE to 110b.
Table 27. ADC conversion characteristics
Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
fCK
ADC Clock frequency (depends on ADC —
configuration) (The duty cycle depends
on AD_CK2 frequency.)
20
—
80
MHz
fs
Sampling frequency
Sample time3
—
—
—
—
—
1.00
—
MHz
ns
tsample
80 MHz, 12-bit resolution
250
250
80 MHz, 12-bit resolution
(high accuracy,
—
recommended)
tconv
Conversion time4
80 MHz, 12-bit resolution
650
700
—
—
—
—
ns
80 MHz, 12-bit resolution
(high accuracy,
recommended)
CS
ADC input sampling capacitance
ADC input pin capacitance 1
—
—
—
—
3
5
56
pF
pF
5
CP1
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
75
Electrical characteristics
Table 27. ADC conversion characteristics (continued)
Symbol
Parameter
Conditions1
Min
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Max
0.8
0.3
875
825
2
Unit
pF
5
CP2
ADC input pin capacitance 2
—
5
RSW1
Internal resistance of analog source
VREF range = 4.5 to 5.5 V
—
kΩ
VREF range = 3.15 to 3.6 V
—
Ω
5
RAD
INL
Internal resistance of analog source
Integral non-linearity
Differential non-linearity
Offset error
—
—
Ω
—
–2
–1
–4
–4
—
LSB
LSB
LSB
LSB
nA
DNL
OFS
GNE
—
1
—
4
Gain error
—
4
Input (single ADC Max leakage
channel)
150 °C
—
250
3
Max positive/negative injection
–3
—
mA
nA
Input (double
ADC channel)
Max leakage
150 °C
300
3.6
Max positive/negative injection
|VREF_AD0 - VREF_AD1| <
150mV
–3.6
mA
SNR
SNR7
Signal-to-noise ratio
VREF = 3.3 V, Fin < 125kHz
VREF = 5.0 V, Fin < 125kHz
Fin ≤ 125 kHz
67
69
—
—
70
—
—
—
—
—
dB
dB
Signal-to-noise ratio
THD
Total harmonic distortion
Effective number of bits
Signal-to-noise and distortion
65
dB
ENOB
Fin < 125 kHz
10.5
bits
dB
SINAD
TUEIS1WINJ
See ENOB
(6.02 * ENOB) + 1.76
Total unadjusted error for IS1WINJ
(single ADC channels)
Without current injection
–6
—
6
LSB
TUEIS1WINJ
Total unadjusted error for IS1WINJ
(single ADC channels)
Current injection: 3 mA for
each channel, max 3
channels
–8
—
8
LSB
1. VDD_HV_IO = 3.3 V -5%,+10%, TJ = –40 to +165 °C, unless otherwise specified, and analog input voltage from VAGND to
VAREF
2. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the
sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tsample depend on programming.
4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
5. See Figure 2.
6. For the 144-pin package.
7. Test conditions have an influence on the achieved performance. Please contact FSL personnel to share the conditions for
these results.
NOTE
The ADC performance specifications are not guaranteed if two
ADCs simultaneously sample the same shared channel.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
76
NXP Semiconductors
Flash memory specifications
3.16 Flash memory specifications
3.16.1 Maximum junction temperature 150°C
3.16.1.1 Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this
section are defined for a single embedded flash memory within
an SoC, and represent average currents for given supplies and
operations.
Table 28 shows the estimated Program/Erase times.
Table 28. Flash memory program and erase specifications
Symbol
Characteristic1
Typ2
Factory
Field Update
Unit
Programming3, 4
Initial
Max
Initial
Max, Full
Temp
Typical
End of
Life5
Lifetime Max6
20°C ≤TA -40°C ≤TJ -40°C ≤TJ ≤ 1,000 ≤ 250,000
≤30°C ≤150°C ≤150°C cycles cycles
tdwpgm
Doubleword (64 bits) program time 43
100 150 55 500
μs
tppgm
Page (256 bits) program time
73
200
800
300
108
396
500
μs
μs
tqppgm
Quad-page (1024 bits) program
time
268
1,200
2,000
t16kers
16 KB Block erase time
16 KB Block program time
32 KB Block erase time
32 KB Block program time
64 KB Block erase time
64 KB Block program time
256 KB Block erase time
256 KB Block program time
168
34
290
45
320
50
250
40
1,000
1,000
1,200
1,200
1,600
1,600
4,000
4,000
ms
ms
ms
ms
ms
ms
ms
ms
t16kpgm
t32kers
t32kpgm
t64kers
217
69
360
100
490
180
1,520
720
390
110
590
210
2,030
880
310
90
315
138
884
552
420
170
1,080
650
t64kpgm
t256kers
t256kpgm
—
—
1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: -40°C ≤ TJ ≤ 150°C, full spec voltage.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
77
Maximum junction temperature 150°C
3.16.1.2 Flash memory Array Integrity and Margin Read specifications
Table 29. Flash memory Array Integrity and Margin Read specifications
Symbol
Characteristic
Min
Typical
Max1
Units
2
tai16kseq
Array Integrity time for sequential sequence on 16 KB block.
—
—
512 x
Tperiod x
Nread
—
—
—
—
tai32kseq
Array Integrity time for sequential sequence on 32 KB block.
Array Integrity time for sequential sequence on 64 KB block.
Array Integrity time for sequential sequence on 256 KB block.
—
—
—
—
—
—
1024 x
Tperiod x
Nread
tai64kseq
2048 x
Tperiod x
Nread
8192 x
Tperiod x
Nread
tai256kseq
tmr16kseq
tmr32kseq
tmr64kseq
tmr256kseq
Margin Read time for sequential sequence on 16 KB block.
Margin Read time for sequential sequence on 32 KB block.
Margin Read time for sequential sequence on 64 KB block.
Margin Read time for sequential sequence on 256 KB block.
73.81
128.43
237.65
893.01
—
—
—
—
110.7
192.6
μs
μs
μs
μs
356.5
1,339.5
1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
3.16.1.3 Flash memory module life specifications
Table 30. Flash memory module life specifications
Symbol
Characteristic
Conditions
Min
Typical
Units
P/E
Array P/E
cycles
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.1
—
—
250,000
—
cycles
Number of program/erase cycles per block
for 256 KB blocks.2
1,000
250,000
P/E
cycles
Data
retention
Minimum data retention.
Blocks with 0 - 1,000 P/E 50
cycles.
—
—
—
Years
Years
Years
Blocks with 100,000 P/E
cycles.
20
Blocks with 250,000 P/E
cycles.
10
1. Program and erase supported across standard temperature specs.
2. Program and erase supported across standard temperature specs.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
78
NXP Semiconductors
Maximum junction temperature 150°C
3.16.1.4 Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the
following figure. The spec window represents qualified limits. The extrapolated dotted
line demonstrates technology capability, however is beyond the qualification limits.
3.16.1.5 Flash memory AC timing specifications
Table 31. Flash memory AC timing specifications
Symbol
Characteristic
Min
Typical
Max
Units
tpsus
Time from setting the MCR-PSUS bit until MCR-DONE bit is set
to a 1.
—
9.4
11.5
μs
plus four
system
clock
plus four
system
clock
periods
periods
tesus
Time from setting the MCR-ESUS bit until MCR-DONE bit is set
to a 1.
—
16
20.8
μs
plus four
system
clock
plus four
system
clock
periods
periods
tres
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low.
—
—
—
100
ns
ns
tdone
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—
5
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
79
Maximum junction temperature 165°C
Table 31. Flash memory AC timing specifications (continued)
Symbol
Characteristic
Min
Typical
Max
Units
tdones
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
—
16
20.8
μs
plus four
system
clock
plus four
system
clock
periods
periods
tdrcv
Time to recover once exiting low power mode.
16
—
45
μs
plus seven
system
clock
plus seven
system
clock
periods.
periods
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin Read
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP
—
—
—
5
ns
ns
taistop
Time from 1 to 0 transition of UT0-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request.
—
80
plus fifteen
system
clock
periods
tmrstop
Time from 1 to 0 transition of UT0-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request.
10.36
—
20.42
μs
plus four
system
clock
plus four
system
clock
periods
periods
3.16.2 Maximum junction temperature 165°C
3.16.2.1 Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this
section are defined for a single embedded flash memory within
an SoC, and represent average currents for given supplies and
operations.
Table 32 shows the estimated Program/Erase times.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
80
NXP Semiconductors
Maximum junction temperature 165°C
Table 32. Flash memory program and erase specifications
Symbol
Characteristic1
Typ2
Factory Programming3, 4
Field Update
Typical End of
Lifetime Max6
Units
Initial Max
Initial Max
Full Temp
Life5
20°C≤ TA ≤
30°C4
–40°C≤ TJ ≤
150°C4
–40°C≤ TJ ≤
165 °C
≤
≤
1,000 250,000
cycles cycles
tdwpgm
tppgm
Doubleword (64 bits)
program time
43
73
100
200
150
65
650
μs
Page (256 bits)
program time
300
145
540
650
μs
μs
tqppgm
Quad-page (1024 bits) 268 800
program time
1,200
2,700
t16kers
16 KB Block erase time 168 290
320
50
500
70
9,000
1,400
ms
ms
t16kpgm
16 KB Block program
time
34
45
t32kers
32 KB Block erase time 217 360
390
110
610
140
9,000
2,800
ms
ms
t32kpgm
32 KB Block program
time
69
100
t64kers
64 KB Block erase time 315 490
590
210
820
280
9,000
5,500
ms
ms
t64kpgm
64 KB Block program
time
138 180
t256kers
256 KB Code erase
time7
884 1,520
2,030
880
1,080
650
4,000
4,000
—
—
ms
ms
t256kpgm 256 KB Code program 552 720
time7
1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: –40°C ≤ TJ ≤ 165°C; full spec voltage. 16 KB, 32 KB and 64 KB blocks are allowed to be programmed or
erased up to TJ = 165°C with restrictions.
7. 256 KB blocks may be programmed or erased at TJ = 150°C maximum. Times listed on this row are TJ = 150°C times.
3.16.2.2 Flash memory Array Integrity and Margin Read specifications
Table 33. Flash memory Array Integrity and Margin Read specifications
Symbol
Characteristic
Min
Typical
Max1
Units
2
tai16kseq
Array Integrity time for sequential sequence on 16KB block.
—
—
512 x
Tperiod x
Nread
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
81
Maximum junction temperature 165°C
Table 33. Flash memory Array Integrity and Margin Read specifications (continued)
Symbol
Characteristic
Min
Typical
Max1
Units
2
tai32kseq
Array Integrity time for sequential sequence on 32KB block.
—
—
1024 x
Tperiod x
Nread
—
—
—
tai64kseq
Array Integrity time for sequential sequence on 64KB block.
Array Integrity time for sequential sequence on 256KB block.
—
—
—
—
2048 x
Tperiod x
Nread
8192 x
Tperiod x
Nread
tai256kseq
tmr16kseq
tmr32kseq
tmr64kseq
tmr256kseq
Margin Read time for sequential sequence on 16KB block.
Margin Read time for sequential sequence on 32KB block.
Margin Read time for sequential sequence on 64KB block.
Margin Read time for sequential sequence on 256KB block.
73.81
128.43
237.65
893.01
—
—
—
—
110.7
192.6
μs
μs
μs
μs
356.5
1,339.5
1. Array Integrity times need to be calculated and is dependant on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
3.16.2.3 Flash memory module life specifications
Table 34. Flash memory module life specifications
Symbol
Characteristic
Conditions
Min
Typical
Units
P/E
Array P/E
cycles
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.1
-
-
250,000
-
cycles
Number of program/erase cycles per block
for 256 KB blocks.2
1,000
250,000
P/E
cycles
Data
retention
Minimum data retention.
Blocks with 0 - 1,000 P/E 50
cycles.
-
-
-
Years
Years
Years
Blocks with 100,000 P/E
cycles.
20
Blocks with 250,000 P/E
cycles.
10
1. Program and erase supported across standard temperature specs. Up to 10,000 program and erase cycles may be done
between 150 °C and 165 °C out of the total specified number of cycles.
2. Program and erase supported across standard temperature specs.
3.16.2.4 Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the
following figure. The spec window represents qualified limits. The extrapolated dotted
line demonstrates technology capability, however is beyond the qualification limits.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
82
NXP Semiconductors
Maximum junction temperature 165°C
3.16.2.5 Flash memory AC timing specifications
Table 35. Flash memory AC timing specifications
Symbol
Characteristic
Min
Typical
Max
Units
tpsus
Time from setting the MCR-PSUS bit until MCR-DONE bit is set
to a 1.
—
9.4 plus
four
11.5 plus
four
μs
system
clock
system
clock
periods
periods
tesus
Time from setting the MCR-ESUS bit until MCR-DONE bit is set
to a 1.
—
16 plus
four
20.8 plus
four
μs
system
clock
system
clock
periods
periods
tres
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low.
—
—
—
—
100
ns
ns
μs
tdone
tdones
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—
5
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
16 plus
four
20.8 plus
four
system
clock
system
clock
periods
periods
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
83
Maximum junction temperature 165°C
Table 35. Flash memory AC timing specifications (continued)
Symbol
Characteristic
Min
Typical
Max
Units
tdrcv
Time to recover once exiting low power mode.
16 plus
seven
system
clock
—
45 plus
seven
system
clock
μs
periods.
periods
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin Read
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP
—
—
—
5
ns
ns
taistop
Time from 1 to 0 transition of UTO-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request.
—
80
plus fifteen
system
clock
periods
tmrstop
Time from 1 to 0 transition of UTO-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request.
10.36
—
20.42
μs
plus four
system
clock
plus four
system
clock
periods
periods
3.16.3 Flash memory read wait-state and address-pipeline control
settings
The following table describes the recommended settings of the Flash Memory
Controller's PFCR1[RWSC] and PFCR1[APC] fields at various operating frequencies,
based on specified intrinsic flash memory access times of the C55FMC array at 150°C.
NOTE
If the user does not follow these recommended settings, the user
must run the flash memory's array integrity (AI) check with
breakpoints disabled: Set the Array Integrity Break Point
Enable bit in the C55FMC's UTest 0 register
(C55FMC_UT0[AIBPE]) to 0.
Table 36. Flash memory read wait-state and address-pipeline control combinations
Operating frequency (fCPU = SYS_CLK)
Flash read latency Flash read latency
on mini-cache miss on mini-cache hit
RWSC APC
(# of fCPU clock
periods)
(# of fCPU clock
periods)
–40°C to 150°C
Max 165°C option
0 MHz < fCPU ≤ 33 MHz
33 MHz < fCPU ≤ 100 MHz
100 MHz < fCPU ≤ 133 MHz
0 MHz < fCPU ≤ 30 MHz
30 MHz < fCPU ≤ 90 MHz
90 MHz < fCPU ≤ 120 MHz
0
2
3
0
1
1
3
5
6
1
1
1
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
84
NXP Semiconductors
Maximum junction temperature 165°C
Table 36. Flash memory read wait-state and address-pipeline control combinations
(continued)
Operating frequency (fCPU = SYS_CLK)
Flash read latency Flash read latency
on mini-cache miss on mini-cache hit
RWSC APC
(# of fCPU clock
periods)
(# of fCPU clock
periods)
–40°C to 150°C
Max 165°C option
133 MHz < fCPU ≤ 167 MHz
167 MHz < fCPU ≤ 200 MHz
120 MHz < fCPU ≤ 150 MHz
150 MHz < fCPU ≤ 180 MHz
4
5
1
2
7
8
1
1
3.17 SGEN electrical characteristics
Table 37. SGEN electrical characteristics
Symbol Parameter
Min
Typ
Max
Unit
SGEN_CL Input clock
K
12
16
20
MHz
APP
Sine wave amplitude (peak to peak)1, 2
0.438
1.884
0.394
-10
—
2.093
0.438
—
2.093
2.302
0.482
10
V
V
MaxAPP Maximum Amplitude (peak - peak)1
MinAPP Minimum Amplitude (peak-peak)1
V
AV
CV
Amplitude variation3
Common voltage4
%
1.3
—
V
CVV
Common voltage variation
-6
45
1
6
%
SINAD Signal-to-noise ratio plus distortion5
60.5
—
—
dB
kHz
%
FREQ Frequency range of the sine wave
50
FRP
CLoad
RESD
IOUT
TJ
Frequency precision of the sine wave (peak to peak variation)
Load capacitance
ESD Pad Resistance6
–5
25
149
0
—
5
—
100
277
100
165
pF
Ω
213
—
Output current
µA
°C
Junction temperature
–40
—
1. Peak to Peak value is measured with no R or I load.
2. It is range of the typical values for room temperature.
3. Peak to Peak excludes noise, SINAD must be considered.
4. Common mode value is measured with no R or I load.
5. SINAD is measured at Max Peak-to-Peak voltage.
6. Internal device routing resistance. ESD pad resistance is in series and must be considered for max Peak-to-Peak voltages,
depending on application Iload and/or Rload.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
85
Maximum junction temperature 165°C
3.18 RESET sequence duration
This following table shows the duration of different reset sequences. See the chip's
Reference Manual for details about the reset sequences.
Table 38. RESET sequences
Symbol
Parameter
Conditions
TReset
Typ
—
Unit
Min
Max1
TDRB
'Destructive' reset sequence, BIST enabled
Self test clock in STCU is
the PLL generated clock.
Self test configuration as
per DCF record
—
18.0
ms
programming. For four
LBIST partitions in design,
two LBIST partitions are
run in parallel.
TDR
'Destructive' reset sequence, BIST disabled
External reset sequence—long, BIST enabled
—
—
—
440
—
480
μs
TERLB
Self test clock in STCU is
the PLL generated clock.
Self test configuration as
per DCF record
17.5
ms
programming. For four
LBIST partitions in design,
two LBIST partitions are
run in parallel.
TERL
TFRL
TFRS
External reset sequence—long, BIST disabled
Functional reset sequence—long
—
—
—
—
—
—
120
165
10.0
150
180
12.0
μs
μs
μs
Functional reset sequence—short
1. The maximum value applies only if the reset sequence duration is not prolonged by an extended assertion of RESET_B by
an external reset generator.
3.19 AC specifications
AC Parameters are specified over the full operating junction temperature range of -40°C
to +165°C and for the full operating range of the VDD_IO supply defined in DC electrical
characteristics.
Table 39. Functional Pad AC Specifications
Symbol
Prop. Delay (ns)1
Rise/Fall Edge (ns)
Drive Load
(pF)
SIUL2_MSCRn's
SRC[1:0] field
L>H/H>L
Min
Max
7.5/7.5
—
Min
0.9/0.9
—
Max
3/3
MSB,LSB
I/O (output)
2.5/2.5
—
50
11
12/12
200
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
86
NXP Semiconductors
Maximum junction temperature 165°C
Table 39. Functional Pad AC Specifications
(continued)
Symbol
Prop. Delay (ns)1
Rise/Fall Edge (ns)
Drive Load
(pF)
SIUL2_MSCRn's
SRC[1:0] field
L>H/H>L
Min
Max
8/8
Min
—
—
—
—
—
—
—
—
Max
3.5/3.5
6.5/6.5
30/30
25/25
30/30
40/40
50/50
0.5/0.5
MSB,LSB
—
—
—
—
—
—
—
—
25
50
10
11.5/11.5
—
200
50
45/45
65/65
75/75
110/110
1.5/1.5
01
002
NA
200
50
200
0.5
I/O (input)
1. As measured from 50% of core side input to Voh/Vol of the output
2. Slew rate control modes
3.19.1 Reset pad (EXT_POR, RESET) electrical characteristics
The device implements a dedicated bidirectional RESET pin.
V
DD_HV_
IO
V
DDMIN
PORST
V
IH
V
IL
device reset forced by PORST
device start-up phase
Figure 9. Start-up reset requirements
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
87
Maximum junction temperature 165°C
VPORST
hw_rst
‘1’
V
DD_HV_
IO
V
IH
V
IL
‘0’
filtered by
lowpass filter
unknown reset
state
filtered by
hysteresis
filtered by
lowpass filter
device under hardware reset
W
W
FRST
FRST
W
NFRST
Figure 10. Noise filtering on reset signal
Table 40. Reset (RESET) electrical characteristics
Symbol Parameter
Conditions
Value
Min Typ Max
Unit
VIH
Input high level TTL (Schmitt Trigger)
—
2.0
—
VDD_HV_IO
+ 0.4
0.8
V
VIL
Input low level TTL (Schmitt Trigger)
Input hysteresis TTL (Schmitt Trigger)
Strong pull-down current
—
–0.4 —
V
VHYS
IOL_R
—
300
0.2
—
—
—
mV
mA
Device under power-on reset
VDD_HV_A=1.0 V
VOL = 0.35*VDD_HV_IO
Device under power-on reset
VDD_HV_IO=3.0 V
VOL = 0.35*VDD_HV_IO
—
—
15
—
—
mA
WFRST
(RESET)-input filtered pulse
—
2
—
—
—
500
—
ns
µs
µA
WNFRST (RESET)-input not filtered pulse
|IWPD Weak pull-down current absolute value
—
|
RESET pin
30
80
VIN = VDD
MPC5744P Data Sheet, Rev. 6.1, 11/2017
88
NXP Semiconductors
Maximum junction temperature 165°C
Table 41. Reset (EXT_POR) electrical characteristics
Symbol Parameter
Conditions
Value
Unit
Min Typ Max
WFPORST PORST input filtered pulse
—
—
—
—
—
500
ns
ns
V
WNFPORST PORST input not filtered pulse
2000 —
—
WIH
WIL
Input high level
Input low level
2
—
—
VDD_HV_IO
+0.4
0.8
—
-0.4
V
3.19.2 WKUP/NMI timing
Table 42. WKUP/NMI glitch filter
Symbol
WFNMI
Parameter
Min
—
Typ
—
Max
20
Unit
NMI pulse width that is rejected
NMI pulse width that is passed
ns
ns
WNFNMI
400
—
—
3.19.3 Debug/JTAG/Nexus/Aurora timing
3.19.3.1 JTAG interface timing
Table 43. JTAG pin AC electrical characteristics 1
#
1
Symbol
tJCYC
Characteristic
Min
36
40
—
5
Max
—
Unit
ns
%
TCK Cycle Time
2
tJDC
TCK Clock Pulse Width
TCK Rise and Fall Times (40% - 70%)
60
3
3
tTCKRISE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
tTMSS, tTDIS TMS, TDI Data Setup Time
tTMSH, tTDIH TMS, TDI Data Hold Time
—
5
5
—
6
tTDOV
tTDOI
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
—
0
15
—
7
8
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
100
40
—
—
15
—
9
10
11
12
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
—
600
600
tBSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
13
14
15
tBSDHZ
tBSDST
tBSDHT
TCK Falling Edge to Output High Impedance
Boundary Scan Input Valid to TCK Rising Edge
TCK Rising Edge to Boundary Scan Input Invalid
—
15
15
600
—
ns
ns
ns
—
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
89
Maximum junction temperature 165°C
1. These specifications apply to JTAG boundary scan only.
TCK
2
3
3
2
1
Figure 11. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 12. JTAG test access port timing
MPC5744P Data Sheet, Rev. 6.1, 11/2017
90
NXP Semiconductors
Maximum junction temperature 165°C
TCK
10
JCOMP
9
Figure 13. JTAG JCOMP timing
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 14. JTAG boundary scan timing
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
91
Maximum junction temperature 165°C
3.19.3.2 Nexus timing
Table 44. Nexus debug port timing 1
No.
1
Symbol
tMCYC
tMDC
Parameter
Conditions
Min
15.6
40
Max
—
Unit
ns
MCKO Cycle Time
MCKO Duty Cycle
—
—
—
2
60
%
3
tMDOV
MCKO Low to MDO, MSEO, EVTO Data
Valid2
–0.1
0.25
tMCYC
4
5
tEVTIPW
tEVTOPW
tTCYC
EVTI Pulse Width
—
—
—
—
—
—
—
4
1
—
—
—
60
—
—
25
tTCYC
tMCYC
ns
EVTO Pulse Width
TCK Cycle Time3
6
62.5
40
8
7
tTDC
TCK Duty Cycle
%
8
tNTDIS, tNTMSS
tNTDIH, tNTMSH
tJOV
TDI, TMS Data Setup Time
TDI, TMS Data Hold Time
TCK Low to TDO/RDY Data Valid
ns
9
5
ns
10
0
ns
1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured
from 50% of MCKO and 50% of the respective signal.
2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3. The system clock frequency needs to be four times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
Figure 15. Nexus output timing
4
EVTI
Figure 16. Nexus EVTI Input Pulse Width
MPC5744P Data Sheet, Rev. 6.1, 11/2017
92
NXP Semiconductors
Maximum junction temperature 165°C
6
7
TCK
8
9
TMS, TDI
10
TDO/RDY
Figure 17. Nexus TDI, TMS, TDO timing
3.19.3.3 Aurora LVDS driver electrical characteristics
Table 45. Aurora LVDS driver electrical characteristics
Symbol
Parameter1
Value
Typ
Unit
Min
Max
Data Rate
STARTUP
DATARATE
Data rate
—
1250
Typ+0.1%
Mbps
TSTRT_BIAS
TSTRT_TX
TSTRT_RX
Bias startup time2
Transmitter startup time3
Receiver startup time4
—
—
—
—
—
—
5
5
4
µs
µs
µs
1. Conditions for these values are VDD_HV_IO = 3.3 V (–5%, +10%), TJ = –40 to 150 °C
2. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
93
Maximum junction temperature 165°C
3. Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is
guaranteed only after the startup time.
4. Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is
guaranteed only after the startup time.
3.19.3.4 Nexus Aurora debug port timing
Table 46. Nexus Aurora debug port timing
#
1
Symbol
tREFCLK
tRCDC
JRC
Characteristic
Min
625
45
—
Max
1250
55
Unit
MHz
%
Reference clock frequency
Reference Clock Duty Cycle
Reference Clock jitter
2
3
40
ps
4
tSTABILITY
BER
JD
Reference Clock Stability
Bit Error Rate
50
—
—
PPM
—
5
10-12
0.17
0.35
20
6
Transmit lane Deterministic Jitter
Transmit lane Total Jitter
Differential output skew
Lane to lane output skew
Aurora lane Unit Interval
—
OUI
OUI
ps
7
JT
—
8
SO
—
9
SMO
—
1000
1600
ps
10
UI
800
ps
MPC5744P Data Sheet, Rev. 6.1, 11/2017
94
NXP Semiconductors
Maximum junction temperature 165°C
1
2
2
CLOCKREF
Zero Crossover
CLOCKREF
-
+
8
8
8
Tx Data
-
Ideal Zero Crossover
Tx Data
+
Tx Data [n]
Zero Crossover
Tx Data [n+1]
Zero Crossover
Tx Data [m]
Zero Crossover
9
9
Figure 18. Nexus Aurora timings
Rise/fall timing for the Nexus Aurora debug port reference clock must conform to the
area between the minimum and maximum value ranges shown in the following receiver
"eye" diagram.
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
95
Maximum junction temperature 165°C
Figure 19. Nexus Aurora receiver "eye" diagram
3.19.4 External interrupt timing (IRQ pin)
Table 47. External interrupt timing
#
1
2
3
Symbol
tIPWL
Parameter
Conditions
Min
3
Max
—
Unit
tCYC
tCYC
tCYC
IRQ pulse width low
IRQ pulse width high
IRQ edge to edge time1
—
—
—
tIPWH
3
—
tICYC
6
—
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both
MPC5744P Data Sheet, Rev. 6.1, 11/2017
96
NXP Semiconductors
Maximum junction temperature 165°C
IRQ
1
2
3
Figure 20. External interrupt timing
3.19.5 SPI timing
Table 48. SPI timing
#
Symbol
Parameter
Conditions
Master (MTFE = 0)
Slave (MTFE = 0)
Min
Max
Unit
1
tSCK
SPI cycle time
40
—
ns
40
—
Slave Receive Only Mode1
16
—
2
3
4
5
6
tCSC
tASC
tSDC
tA
PCS to SCK delay
After SCK delay
SCK duty cycle
—
16
16
—
—
ns
ns
ns
ns
ns
—
—
tSCK/2 – 4
—
tSCK/2 + 4
40
Slave access time
SS active to SOUT valid
SS inactive to SOUT High-Z or invalid
tDIS
Slave SOUT disable
time
—
25
7
8
9
tPCSC
tPASC
tSUI
PCSx to PCSS time
PCSS to PCSx time
—
13
13
16
2
—
—
—
—
—
ns
ns
ns
—
Master (MTFE = 0)
Slave
Data setup time for
inputs
Master (MTFE = 1, CPHA = 0)
16 – (P2 x
, 3
tSYS
16
–3
4
)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
—
—
—
—
10
tHI
Data hold time for
inputs
ns
Slave
Master (MTFE = 1, CPHA = 0)
–3 + (P2 x
, 3
tSYS
–3
—
)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
—
4
11
12
tSUO
Data valid (after SCK
edge) time for outputs
ns
ns
—
17
3
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Master (MTFE = 0)
Slave
—
4 + tSYS
—
4
tHO
Data hold time for
outputs
–4
3.6
—
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
97
Maximum junction temperature 165°C
Table 48. SPI timing (continued)
#
Symbol
Parameter
Conditions
Min
–4
Max
—
Unit
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–4
—
1. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the SPI can receive data on SIN,
but no valid data is transmitted on SOUT.
2. P is the number of clock cycles added to delay the SPI input sample point and is software programmable.
3. tSYS is the period of the DSPI_CLKn clock, the input clock to the SPI module. Maximum frequency is 50 MHz (min tSYS
20 ns).
=
NOTE
For numbers shown in the following figures, see Table 48.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 21. DSPI classic SPI timing — master, CPHA = 0
MPC5744P Data Sheet, Rev. 6.1, 11/2017
98
NXP Semiconductors
Maximum junction temperature 165°C
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 22. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Figure 23. DSPI classic SPI timing — slave, CPHA = 0
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
99
Maximum junction temperature 165°C
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 24. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Figure 25. DSPI modified transfer format timing — master, CPHA = 0
MPC5744P Data Sheet, Rev. 6.1, 11/2017
100
NXP Semiconductors
Maximum junction temperature 165°C
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 26. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Figure 27. DSPI modified transfer format timing – slave, CPHA = 0
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
101
Maximum junction temperature 165°C
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
9
SIN
First Data
Last Data
Figure 28. DSPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
Figure 29. DSPI PCS strobe (PCSS) timing
3.19.6 LFAST
MPC5744P Data Sheet, Rev. 6.1, 11/2017
102
NXP Semiconductors
Maximum junction temperature 165°C
3.19.6.1 LFAST interface timing diagrams
Figure 30. LFAST timing definition
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
103
Maximum junction temperature 165°C
H
lfast_pwr_down
L
Tsu
Differential TX
Data Lines
pad_p/pad_n
Data Valid
Figure 31. Power-down exit time
V
IH
Differential TX
Data Lines
90%
10%
pad_p/pad_n
V
IL
Tfall
Trise
Figure 32. Rise/fall time
3.19.6.2 LFAST interface electrical characteristics
Table 49. LFAST electrical characteristics
Symbol
VDD_HV_IO
DATARATE
Parameter
Conditions1
Value
Typ
—
Unit
V
Min
Max
Operating supply conditions
Data rate
3.15
3.6
Data Rate
—
STARTUP
—
—
312/320
Typ+0.1%
Mbps
TSTRT_BIAS
TPD2NM_TX
Bias startup time2
—
—
0.5
0.2
3
2
µs
µs
Transmitter startup time (power
down to normal mode)3
—
TSM2NM_TX
Transmitter startup time (sleep
mode to normal mode)
—
—
—
—
—
—
0.2
20
20
0.5
40
50
µs
ns
ns
TPD2NM_RX Receiver startup time5 (Power down
to Normal mode)
TPD2SM_RX Receiver startup time4 (Power down
to Sleep mode)
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
104
NXP Semiconductors
Maximum junction temperature 165°C
Table 49. LFAST electrical characteristics
(continued)
Symbol
Parameter
Conditions1
Value
Typ
Unit
Min
Max
TRANSMITTER
VOS_DRF
Common mode voltage
—
—
1.18
100
—
1.32
285
V
|ΔVOD_DRF
|
Differential output voltage swing
(terminated)
200
mV
TTR_DRF
ROUT_DRF
COUT_DRF
Rise/Fall time (10% - 90% of swing)
Terminating resistance
Capacitance6
—
0.26
67
—
—
—
1.5
198
5
ns
Ω
—
—
—
pF
RECEIVER
VICOM_DRF
|DVI_DRF
Common mode voltage
Differential input voltage
Terminating resistance
Capacitance9
—
—
—
—
—
0.157
100
80
—
—
1.68
—
V
mV
Ω
|
RIN_DRF
CIN_DRF
LIN_DRF
115
3.5
5
150
6
—
pF
nH
Parasitic Inductance10
—
10
1. VDD_VH_IO = 3.3 V -5%,+10%, TJ = –40 to 165 °C, unless otherwise specified
2. Startup time is defined as the time taken by LFAST current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LFAST functionality is guaranteed only after the startup time.
3. Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the
startup time.
4. Startup time is defined as the time taken by LFAST transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the
startup time.
5. Startup time is defined as the time taken by LFAST receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable. LFAST functionality is guaranteed only after the
startup time.
6. Total lumped capacitance including silicon, package pin and bond wire. Application board simulation is needed to verify
LFAST template compliancy.
7. Absolute min = 0.15 V – (285 mV / 2) = 0 V
8. Absolute max = 1.6 V + (285 mV / 2) = 1.743 V
9. Total capacitance including silicon, package pin and bond wire
10. Total inductance including silicon, package pin and bond wire
Table 50. LFAST electrical characteristics1
Symbol Parameter
Conditions
Value
Unit
Min
10
-1
Nominal
Max
26
1
FRF_REF SysClk Frequency
—
—
—
—
—
—
—
—
—
MHz
%
ERRREF SysClk Frequency Error
DCREF
CLOAD
RLOAD
PN
SysClk Duty Cycle
—
45
—
55
10
—
%
Output Buffer Load Capacitance
Output Buffer Load Resistance
Integrated Phase Noise (single side band)
—
pF
—
10
—
kΩ
20 MHz
10 MHz
-58
-64
dBc
dBc
—
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
105
Maximum junction temperature 165°C
Table 50. LFAST electrical characteristics1 (continued)
Symbol Parameter
Conditions
Value
Nominal
320
Unit
Min
—
Max
—
FVCO
TLOCK
ΔPER
PLL VCO Frequency
—
—
—
MHz
µs
PLL Phase Lock
—
—
40
PLL Long Term Jitter (peak to peak)
—
—
600
ps
1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.
3.19.7 FlexRay
3.19.7.1 FlexRay timing parameters
This section provides the FlexRay interface timing characteristics for the input and output
signals. These numbers are recommended per the FlexRay Electrical Physical Layer
Specification, Version 3.0.1, and subject to change per the final timing analysis of the
device.
3.19.7.2 TxEN
TxEN
80 %
20 %
dCCTxEN
dCCTxEN
FALL
RISE
Figure 33. FlexRay TxEN signal
MPC5744P Data Sheet, Rev. 6.1, 11/2017
106
NXP Semiconductors
Maximum junction temperature 165°C
Table 51. TxEN output characteristics1
Name
Description
Min
Max
9
Unit
ns
dCCTxENRISE25
dCCTxENFALL25
dCCTxEN01
Rise time of TxEN signal at CC
Fall time of TxEN signal at CC
—
—
—
9
ns
Sum of delay between Clk to Q of the last FF and the final
output buffer, rising edge
25
ns
dCCTxEN10
Sum of delay between Clk to Q of the last FF and the final
output buffer, falling edge
—
25
ns
1. All parameters specified for VDD_HV_IO = 3.3 V -5%, +10%, TJ = –40 °C / 165 °C, TxEN pin load maximum 25 pF
PE_Clk
TxEN
dCCTxEN
dCCTxEN
10
01
Figure 34. FlexRay TxEN signal propagation delays
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
107
Maximum junction temperature 165°C
3.19.7.3 TxD
TxD
dCCTxD
50%
80 %
50 %
20 %
dCCTxD
dCCTxD
RISE
FALL
Figure 35. FlexRay TxD signal
Table 52. TxD output characteristics
Name
Description1
Min
Max
Unit
dCCTxAsym
Asymmetry of sending CC @ 25 pF load
(=dCCTxD50% - 100 ns)
–2.45
2.45
ns
dCCTxDRISE25+dCCTx Sum of Rise and Fall time of TxD signal at the output
DFALL25
—
—
—
9
ns
ns
ns
dCCTxD01
Sum of delay between Clk to Q of the last FF and the final
output buffer, rising edge
25
25
dCCTxD10
Sum of delay between Clk to Q of the last FF and the final
output buffer, falling edge
1. All parameters specified for VDD_HV_IO = 3.3 V -5%, +10%, TJ = –40 °C / 165 °C, TxD pin load maximum 25 pF
MPC5744P Data Sheet, Rev. 6.1, 11/2017
108
NXP Semiconductors
Maximum junction temperature 165°C
PE_Clk*
TxD
dCCTxD
10
dCCTxD
01
*FlexRay Protocol Engine Clock
Figure 36. FlexRay TxD signal propagation delays
3.19.7.4 RxD
Table 53. RxD input characteristic
Name
Description1
Min
—
Max
7
Unit
pF
%
C_CCRxD
uCCLogic_1
uCCLogic_0
dCCRxD01
Input capacitance on RxD pin
Threshold for detecting logic high
Threshold for detecting logic low
35
30
—
70
65
10
%
Sum of delay from actual input to the D
input of the first FF, rising edge
ns
dCCRxD10
Sum of delay from actual input to the D
input of the first FF, falling edge
—
10
ns
1. All parameters specified for VDD_HV_IO = 3.3 V -5%, +10%, TJ = –40 / 165 °C
3.19.7.5 Receiver asymmetry
Table 54. Receiver asymmetry
Name
Description
Min
Max
Unit
ns
dCCRxAsymAccept15
dCCRxAsymAccept25
Acceptance of asymmetry at receiving CC with 15 pF load (*)
Acceptance of asymmetry at receiving CC with 25 pF load (*)
–31.5
–30.5
+44.0
+43.0
ns
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
109
Maximum junction temperature 165°C
3.19.8 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
3.19.8.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 55. MII signal switching specifications
Symbol
—
Description
Min.
—
Max.
25
Unit
MHz
RXCLK frequency
RXCLK pulse width high
MII1
35%
65%
RXCLK
period
RXCLK
period
ns
MII2
RXCLK pulse width low
35%
65%
MII3
MII4
—
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
5
5
—
—
ns
—
25
MHz
MII5
TXCLK pulse width high
35%
65%
TXCLK
period
TXCLK
period
ns
MII6
TXCLK pulse width low
35%
65%
MII7
MII8
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
2
—
—
25
ns
MII6
MII5
MII7
TXCLK (input)
MII8
Valid data
TXD[n:0]
TXEN
Valid data
Valid data
TXER
Figure 37. RMII/MII transmit signal timing diagram
MPC5744P Data Sheet, Rev. 6.1, 11/2017
110
NXP Semiconductors
Obtaining package dimensions
MII2
MII3
MII1
MII4
RXCLK (input)
RXD[n:0]
RXDV
Valid data
Valid data
Valid data
RXER
Figure 38. RMII/MII receive signal timing diagram
3.19.8.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 56. RMII signal switching specifications
Num
—
Description
Min.
—
Max.
50
Unit
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
MHz
RMII1
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RMII4
RMII7
RMII8
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN invalid
4
2
—
—
—
15
ns
ns
ns
ns
4
RMII_CLK to TXD[1:0], TXEN valid
—
4 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
144-pin LQFP
Then use this document number
98ASS23177W
257-ball MAPBGA
98ASA00081D
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
111
Ordering information
5 Ordering information
G
9
M PC 5744P K0 K LQ
R
Qualification status
Core code (Power Architecture)
Device number
E = Ethernet
F = FlexRay
G = both
(blank) = neither
Fab and mask identifier
Temperature range
Package identifier
Operating frequency
Tape and reel status
Temperature range
Package identifier Operating frequency Qualification status
Tape and reel status
R = Tape and reel
(blank) = Trays
9 = 200 MHz
P = Pre-qualification
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
M = –40°C to +125°C LQ = 144 LQFP
K = –40°C to +135°C MM = 257 MAPBGA 8 = 180 MHz
for extended temp 5 = 150 MHz
(+165°C T )
J
Note: Not all options are available on all devices.
Table 57. Orderable part number examples
Part number1
Flash/SRAM
2.5 MB/384 KB
2.5 MB/384 KB
Package
Other features
-40 to +125 °C
Ethernet interface
LFAST interface
Nexus Aurora
SPC5744PFK1MLQ9
SPC5744PGK1MMM9
144 LQFP (Pb free)
257 MAPBGA (Pb free)
-40 to +125 °C
-40 to +125 °C
Ethernet interface
LFAST interface
Nexus Aurora
SPC5743PFK1MLQ9
SPC5743PGK1MMM9
2 MB/256 KB
2 MB/256 KB
144 LQFP (Pb free)
257 MAPBGA (Pb free)
-40 to +125 °C
-40 to +125 °C
Ethernet interface
LFAST interface
Nexus Aurora
SPC5742PFK1MLQ9
SPC5742PGK1MMM9
1.5 MB/192 KB
1.5 MB/192 KB
144 LQFP (Pb free)
257 MAPBGA (Pb free)
-40 to +125 °C
-40 to +125 °C
Ethernet interface
LFAST interface
Nexus Aurora
SPC5741PFK1MLQ9
SPC5741PGK1MMM9
1 MB/128 KB
1 MB/128 KB
144 LQFP (Pb free)
257 MAPBGA (Pb free)
-40 to +125 °C
MPC5744P Data Sheet, Rev. 6.1, 11/2017
112
NXP Semiconductors
Document revision history
1. All packaged devices are PPC, rather than MPC or SPC, until product qualifications are complete. Not all configurations
are available in the PPC parts.
6 Document revision history
The following table summarizes revisions to this document since the previous release.
Table 58. Revision history
Revision
Date
Description of changes
6
05/2017 Changed Freescale to NXP throughout the document.
Extensively updated Generic pins/balls.
Absolute maximum ratings
• In Table 12
• for row set IINJ changed "Maximum DC injection current per pin, 5 V pads" to "Maximum
DC injection current per pin, 5V ADC pads".
• For row set IINJ updated the footnote.
Voltage regulator electrical characteristics
• In Table 17
• Added the note, "The device has to..........which drives the EXT_POR".
• In existing row Cld added Maximum value 18.8.
• In existing row Cpd added Maximum value 300.
• Renamed parameter from "Load Current transient" to "Load current transient time" and
updated the Min and Max value.
• Renamed the following parameters:
• Supply ramp rate VDD12_CORE to Supply ramp rate VDD_LV_COR
• Supply ramp rate VDD33_REG to Supply ramp rate VDD_HV_PMU
• POR VDD12_CORE to POR_COR
• POR VDD33_REG to POR_PMU
• In Figure 4 changed VDD33_REG to VDD_HV_PMU.
16 MHz Internal RC Oscillator (IRCOSC) electrical specifications
• In Table 26
• Changed the Min and Max values for IRCOSC frequency (untrimmed) parameter.
• Added IRC frequency variation with temperature and voltage compensation parameter
row.
ADC electrical characteristics
• Changed the Note from "Unless noted otherwise, the specifications in Table 27 assume the
use of 13-bit resolution: In ADC_CALBISTREG, set OPMODE to 110b" to "Unless noted
otherwise, the specifications in Table 27 assume the use of 12-bit resolution (high accuracy,
recommended): In ADC_CALBISTREG, set OPMODE to 110b".
• In Table 27 for existing rows tsample and tconv changed the "13 bit resolution" to "12-bit
resolution (high accuracy, recommended)".
• In Flash memory program and erase specifications changed symbols for specifications:
• Quad-page (1024 bits) program time: Changed symbol from tqppgn to tqppgm
• 16 KB Block program time: Changed symbol from t16kpgn to t16kpgm
• In Flash memory Array Integrity and Margin Read specifications incorporated minor editorial
changes
• In Flash memory AC timing specifications for tpsus
:
Table continues on the next page...
MPC5744P Data Sheet, Rev. 6.1, 11/2017
NXP Semiconductors
113
Document revision history
Table 58. Revision history (continued)
Revision
Date
Description of changes
• Changed Typical from 7 µs plus four system clock periods to 9.4 µs plus four system
clock periods
• Changed Max from 9.1 µs plus four system clock periods to 11.5 µs plus four system
clock periods
SGEN electrical characteristics
• Extensively updated the Table 37
LFAST interface electrical characteristics
• In Table 49 for row set |ΔVOD_DRF| deleted the from the Max, Typ, and Min values.
• In Table 49, removed the row set VHYS_DRF
6.1
10/2017
• In Voltage regulator electrical characteristics changed the note, from "The device has
to..........which drives the EXT_POR" to "When the external regulator........regulator modes for
safety operation".
MPC5744P Data Sheet, Rev. 6.1, 11/2017
114
NXP Semiconductors
How to Reach Us:
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
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its products for any particular purpose, nor does NXP assume any liability arising
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damages. “Typical” parameters that may be provided in NXP data sheets and/or
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may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customerʼs technical experts. NXP
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WORLD, COOLFLUX, EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE,
JCOP, LIFE VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE
PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE,
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© 2011–2017 NXP B.V.
Document Number MPC5744P
Revision 6.1, 11/2017
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