PN5190B1HN/C121Y [NXP]
NFC frontend;
| 型号： | PN5190B1HN/C121Y |
| 厂家： | 
NXP |
| 描述： | NFC frontend |
| 文件： | 总308页 (文件大小：2447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PN5190
NFC frontend
Rev. 3.0 — 21 April 2021
662230
Product data sheet
COMPANY PUBLIC
1 General description
This document describes the functionality and electrical specification of the high-power
NFC-IC PN5190B1, silicon version B1, using firmware or V2.0 or higher.
Additional documents supporting a design-in of the PN5190B1 are available from NXP,
this additional design-in information is not part of this document.
The PN5190B1 supports highly innovative and unique features which do not require any
host controller interaction. These features include dynamic power control (DPC), adaptive
waveform control (AWC), and fully automatic EMD error handling.
The independence of real-time host controller interactions makes this product a good fit
for systems which operate a pre-emptive multitasking OS like Linux or Android.
In this document, the term „MIFARE card“ refers to a contactless card using an IC out
of the MIFARE Classic, MIFARE Plus, MIFARE Ultralight or MIFARE DESFire product
family.
NXP Semiconductors
PN5190
NFC frontend
2 Features and benefits
2.1 RF functionality
• As a highly integrated high performance full NFC Forum-compliant frontend IC for
contactless communication at 13.56 MHz, this NFC frontend IC utilizes an outstanding
modulation and demodulation concept completely integrated for relevant 13.56 MHz
based contactless communication methods and protocols.
PN5190B1 supports communication with all products of the MIFARE product-based
card family including MIFARE Ultralight, MIFARE Classic 1K/4K, MIFARE DESFire
EV1/EV2 and MIFARE Plus cards CRYPTO implemented in hardware for R/W of all
NXP MIFARE product-based cards (includes intellectual-property licensing rights for
NXP ISO/IEC 14443-A, Innovatron ISO/IEC 14443-B, and NXP MIFARE products).
The PN5190B1 frontend IC supports the following RF operating modes:
2.1.1 ISO/IEC14443-A
• Reader/writer mode supporting ISO/IEC 14443-A R/W up to 848 kBit/s
2.1.2 ISO/IEC14443-B
• Reader/writer mode supporting ISO/IEC 14443-B up to 848 kBit/s
2.1.3 FeliCa
• Reader/writer mode supporting FeliCa 212 kBit/s and 424 kBit/s(without crypto)
2.1.4 Tag type reading
• Supports reading of all NFC tag types (type 1, type 2, type 3, type 4A and type 4B, type
5)
2.1.5 MIFARE card reading
• Reader/writer communication mode for the MIFARE card family including MIFARE
Classic
2.1.6 ISO/IEC 15693
• Reader/writer mode supporting ISO/IEC 15693 (ICODE)
• Proprietary data rates based on ISO/IEC15693 with 106 kbit and 212 kbit/s (for NXP
NTAG 5 communication)
2.1.7 Peer to peer
• P2P Active 106 kbit/s TO 424 kbit/s, Initiator and Target
• P2P Active 106 kbit/s TO 424 kbit/s, Initiator and Target
• Proprietary passive communication for type A up to 848 kbit/s
• Functionality according to ISO/IEC 21481 (NFC-IP-2)
PN5190B1
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NXP Semiconductors
PN5190
NFC frontend
2.2 Host interface
• One host interface based on SPI is implemented:
– SPI interface with data rates up to 15 Mbit/s with MOSI, MISO, NSS and SCK signals
– Interrupt request line to inform host controller on events
– Independent TX and RX buffer for RF data with size of 1024 bytes each
PN5190B1
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NXP Semiconductors
PN5190
NFC frontend
3 Applications
• Payment
• Physical access
• eGov
PN5190B1
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NXP Semiconductors
PN5190
NFC frontend
4 Firmware versions
Firmware versions covered by this data sheet:
Version 2.0:
• This version cannot be replaced by FW versions using smaller version numbers (e.g.
replacing FW2.0 by FW1.9 is not possible)
• This FW version is not available on volume production devices, but can be installed by
the user
Before using this firmware in Peer to Peer target mode, for better communication
stability the EEPROM address 0x292 (default A6E813C0) shall be initialized with the
value (A6E813C1 - 0x292:0xC1 0x203: 0x13 0x294:0xE8 0x295:0xA6). This setting
has no influence on reader or card emulation modes.
Version 2.1:
• This version is functionally equivalent to Version FW2.0 but offers updated EEPROM
Settings compared to FW2.0
• This version cannot be replaced by FW versions using smaller version numbers (e.g.
replacing FW2.1 by FW1.9 is not possible)
• This FW version is installed by default on volume production devices of PN5190 B1
• This FW and all upcoming FW versions will use the EEPROM Setting at address 0x292
= A6E813C1 to configure the Peer to Peer target mode for better communication
stability.
PN5190B1
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NXP Semiconductors
PN5190
NFC frontend
5 Quick reference data
Table 1.ꢀQuick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD(VBAT)
supply voltage on pin VBAT
(analog and digital supply)
VBAT ≥ VDDIO
2.4
-
5.5
V
VDD(VDDIO)
supply voltage on pin VDDIO
1.8 V supply
3.3 V supply
1.62
2.4
-
-
1.98
3.6
V
V
(supply for host interface and
GPIO's)
Ipd
power-down current
VDD(VDDPA) = VDD(VDDIO)
=VDD(VDD) 3.0 V; hard power-
down state; pin VEN set LOW,
Tamb = 25 °C, External supply by
VDDIO
-
40
105
μA
Istb
standby current
Tamb = 25 °C
-
-
45
22
110
-
μA
μA
IULPCD
average ultra-low-power card Tamb = 25 °C, VDD(VDDPA) =
detection current
VDD(VDDIO) =VDD(VDD) 3.0
V, 330 ms Polling interval, 50 R
antenna matching
IDD(VDDPA)
supply current on pin VDDPA supplied via VUP_TX (TX_LDO
active)
-
-
-
-
-
-
-
350
400
2.0
mA
mA
W
supplied without DC-DC and
TXLDO active
-
P(PA)
Transmitter output power
supplied via VUP_TX (TX_LDO
active)
-
supplied without DC-DC and
TXLDO active
-
2.3
W
Tamb
ambient operating temperature in still air with exposed pins
soldered on a 4 layer JEDEC PCB,
-40
-40
+85
+105
°C
°C
in still air with exposed pins
soldered on a 4 layer JEDEC PCB,
HVQFN40 Package TX current =
120 mA @ VDDPA=3.6 V
Tstg
storage temperature
no supply voltage applied
-55
-
-
-
+150
+125
°C
°C
Tj_max
maximum junction temperature -
PN5190B1
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PN5190
NFC frontend
6 Ordering information
Table 2.ꢀOrdering information
Type number
Package
Name
Description
Version
PN5190B1HN/C121Y HVQFN40R
Plastic thermal enhanced very thin quad flat package; no leads; SOT2062-1
40 terminals + 1 central ground; body 5 x 5 x 1.0 mm; delivered
in one reel,
MSL=3. Minimum order quantity = 6000 pcs
The ending Y in the product name is indicating the packing
"reel"
Initialized with FW 2.1
PN5190B1HN/C121E HVQFN40R
Plastic thermal enhanced very thin quad flat package; no leads; SOT2062-1
40 terminals + 1 central ground; body 5 x 5 x 1.0 mm; delivered
in one tray, bakeable,
MSL=3. Minimum order quantity = 490 pcs
The ending E in the product name is indicating the packing
"single tray"
Initialized with FW 2.1
PN5190B1EV/C121Y VFBGA64
PN5190B1EV/C121E VFBGA64
Plastic thin fine-pitch ball grid array package; 64 balls, body 4.5 SOT1307-2
x 4.5 x 0.9 mm, delivered on reel 13", MSL = 3. Minimum order
quantity = 4000 pcs
The ending Y in the product name is indicating the packing
"reel"
Initialized with FW 2.1
Plastic thin fine-pitch ball grid array package; 64 balls, body 4.5 SOT1307-2
x 4.5 x 0.9 mm, delivered in one tray, MSL = 3. Minimum order
quantity = 490 pcs
The ending E in the product name is indicating the packing
"single tray"
Initialized with FW 2.1
PN5190B1
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PN5190
NFC frontend
7 Block diagram with VFBGA64 connections
optional 2.4 V.... 6.0 V supply (no DC-DC used)
3.3 V supply (with DC-DC used)
2
220
nF
1 µH
220 nF
1
1.8 V or 3.3 V pad supply (connect to host)
20
µF
IRQ
TXVCM
DC-DC
TX_LDO
TRANSMITTER
SPI_MISO
220 nF
220 nF
SPI_MOSI
INTERFACE
SPI_NSS
TX1
VMID
TX2
SPI_SCK
ANALOG/DIGITAL
VEN
VSS/PA
XTAL1
RXp
RXn
CLK/PLL
XTAL2
RECEIVER
AUX1
AUX2
VSS_PMU
VSS_DIG
VSS_NFC
AUX3/VTUNE0
MUX
PRD0
PRD1
DAC
220 nF
100 nF
220 nF
host interfaces
clock and reset
ground connections
power supply
out for stabilizing capacitors
out for stabilizing capacitors
antenna connection
digital/analog l/O
aaa-029370
Figure 1.ꢀBlock diagram
PN5190B1
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PN5190
NFC frontend
8 Pinning information
8.1 Pin description VFBGA64
ball A1
index area
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
aaa-035352
Transparent top view
Figure 2.ꢀ Pin configuration for VFBGA64
Table 3.ꢀPin description VFBGA64
Pin
Symbol
Type
Description PN5190
Description PN76 family (planned
Number
pinning of upcoming device)
Host Interface
E6
E5
D6
D5
B7
ATX_A
Output
Input
SPI slave data output
SPI clock input
UART RX / I³C SDA / SPI MISO / I2C
SDA
UART CTS / I³C SCL / SPI SCK / I2C
SCL
UART RTS / I3C Adr Bit 0 / SPI NSS / I2C
Adr Bit 0 / USB D+
UART TX / I3C Adr Bit 1 / SPI MOSI / I2C
Adr Bit 1 / USB D-
ATX_B
ATX_C
ATX_D
IRQ
Input
SPI slave select input
SPI slave data input
Input
Output
Host communication/ event interrupt
signal
Host communication / event interrupt
signal
F8
XTAL1
XTAL2
Input
Crystal / system clock input
Crystal / system clock input
G8
Output
Clock output (amplifier inverted signal
output) for crystal
Clock output (amplifier inverted signal
output) for crystal
B3
VEN
Input
Hardware reset, low active (independent Hardware reset, low active (independent
from VVDDIO from VVDDIO
)
)
Supply pins
H2
G3
A2
VSS_PA
Supply
GND
Transmitter ground
Transmitter ground
VSS_PLL
Supply
GND
PLL ground (low noise)
DC-DC boost ground
PLL ground (low noise)
DC-DC boost ground
VSS_PWR
Supply
GND
PN5190B1
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PN5190
NFC frontend
Table 3.ꢀPin description VFBGA64...continued
Pin
Symbol
Type
Description PN5190
Description PN76 family (planned
Number
pinning of upcoming device)
D3
VSS_REF
VSS_SUB
VSS_PMU
VSS_DIG
VSS_NFC
VBAT
Supply
GND
PMU ground
PMU ground
B2, E3
C3
Supply
GND
Substrate ground
PMU ground
Substrate ground
PMU ground
Supply
GND
F4
Supply
GND
Digital ground
NFC ground
Digital ground
NFC ground
F3
Supply
GND
E1
Supply
System supply, used to supply the analog System supply, used to supply the analog
and digital blocks, memory and internal
voltage references
and digital blocks, memory and internal
voltage references
A8
G1
F1
B1
A1
VDDIO
VDDPA
VUP_TX
Supply
Supply
Supply
IO pads power supply
Transmitter supply
IO pads power supply
Transmitter supply
Input supply voltage for transmitter LDO Input supply voltage for transmitter LDO
VDDBOOST Supply
DC-DC boost supply
DC-DC boost supply
BOOST_LX
Output
Boost inductance loopback, to be
connected to boost inductor
Boost inductance loopback, to be
connected to boost inductor
A3
VBATPWR
Supply
To be connected to boost inductor and
transmitter power supply
To be connected to boost inductor and
transmitter power supply
Outputs for stabilizing cap
A4
D2
C1
G2
VDDNV
Output
Output
Output
Output
Non-volatile memory power supply, to be Non-volatile memory power supply, to be
connected to ground via 220 nF blocking connected to ground via 220 nF blocking
cap
cap
VREF
High quiescent reference voltage, to be
High quiescent reference voltage, to be
connected to ground via 100 nF blocking connected to ground via 100 nF blocking
cap
cap
VDDC
Power supply for Digital Core, to be
Power supply for Digital Core, to be
connected to ground via 220 nF blocking connected to ground via 220 nF blocking
cap cap
TXVCM
Transmitter voltage common mode, to be Transmitter voltage common mode, to be
connected to ground via 220 nF blocking connected to ground via 220 nF blocking
cap
cap
F2
H6
TXVCASC
VMID
Output
Output
TX decoupling cap, to be connected to
VDDPA
TX decoupling cap, to be connected to
VDDPA
Stabilizing capacitor connection output,
to be connected to electrical symmetry
point of antenna (typically antenna
ground) by 100 nF blocking cap
Stabilizing capacitor connection output,
to be connected to electrical symmetry
point of antenna (typically antenna
ground) by 100 nF blocking cap
RF Debug signals
G7
F7
AUX_1
AUX_2
Output
Output
Test bus 1
Test bus 2
Test bus 1
Test bus 2
PN5190B1
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PN5190
NFC frontend
Table 3.ꢀPin description VFBGA64...continued
Pin
Symbol
Type
Description PN5190
Description PN76 family (planned
Number
pinning of upcoming device)
H8
AUX_3 /
VTUNE0
Output
Test bus 3 / VTUNE0 (Digital to analog
output 0)
Test bus 3 / VTUNE0 (Digital to analog
output 0)
Antenna connections
H5
H4
H1
H3
RXP
RXN
TX1
TX2
Input
Receiver input "Positive"
Receiver input "Negative"
Antenna driver output 1
Antenna driver output 2
Receiver input "Positive"
Receiver input "Negative"
Antenna driver output 1
Antenna driver output 2
Input
Output
Output
Analog/Digital inputs & outputs
H7
VTUNE1
Output
Digital to analog output 1 (not available
on HVQFN40)
Digital to analog output 1 (DAC 1)
General Purpose I/O 0
E8
GPIO0
Input/
General Purpose In/Out 0
General Purpose Output 1
General Purpose Output 2
General Purpose Output 3
Output
D8
E7
D7
GPIO1
GPIO2
GPIO3
Input/
General Purpose I/O 1
General Purpose I/O 2
General Purpose I/O 3
Output
Input/
Output
Input/
Output
If PN5190 is using the ULPCD, GPIO3
cannot be used for any other purpose
than aborting the ULPCD.
If PN76 is using the ULPCD, GPIO3
cannot be used for any other purpose
than aborting the ULPCD.
Security Feature
B4
PRD1
Input/
Package removal detection, internally
connected to PRD2 (not available on
HVQFN40)
Package removal detection, internally
connected to PRD2
Output
G4
PRD2
Input/
Package removal detection, internally
connected to PRD1 (not available on
HVQFN40)
Package removal detection, internally
connected to PRD1
Output
Pins connected on PN76 family only
A5
A6
PVDD_OUT
I2CM_SDA
Output
PN5190: Do not connect
PVDD LDO output
I2C master SDA
Input/Out Do not connect
put
A7
B5
DWL_REQ
GPIO5
Input
Do not connect
Download request (optional)
General Purpose I/O 5
Input/Out Do not connect
put
B6
B8
I2CM_SCL
SWDIO
Input
Do not connect
I2C master SCL
Input/Out Do not connect
put
Single Wire Debug Interface Data
C2
C4
TEST
Input/Out Internal test pin. Do not connect
put
Internal test pin. Do not connect.
Auxiliary Card Interrupt
ISO_INT_
AUX
Input/Out Do not connect
put
PN5190B1
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PN5190
NFC frontend
Table 3.ꢀPin description VFBGA64...continued
Pin
Symbol
Type
Description PN5190
Description PN76 family (planned
Number
pinning of upcoming device)
C5
C6
C7
GPIO4
Input/Out Do not connect
put
General Purpose I/O 5
HOST_IF_
SEL1
Input
Do not connect
Host interface select 1
Host interface select 0
HOST_IF_
SEL0
Input
Do not connect
C8
D1
D4
SWD_CLK
Input
Do not connect
Do not connect
Single Wire Debug Interface Clock
USB VBUS supply
USB_VBUS
Supply
ISO_IO_AUX Input/Out Do not connect
put
Auxiliary Card I/O
E2
E4
AD1
Input
Input
Do not connect
Do not connect
Analog/Digital Converter Input 1
Auxiliary Card Clock
ISO_CLK_
AUX
F5
F6
G5
G6
SPIM_MOSI Input
SPIM_MISO Output
SPIM_SCLK Input
Do not connect
Do not connect
Do not connect
Do not connect
SPI master MOSI
SPI master MISO
SPI master clock
SPI master NSS
SPIM_NSS
Input
For good RF performance, all blocking capacitors shall be placed on the same side of the
PCB, traces from pin to capacitor shall be as short as possible.
All Supply GND connections shall be connected by low-ohmic connections on the PCB.
PN76 is a planned product, the pin allocation is provided for information only. This
product PN76 will assign functionality to n.c. pins of the PN5190.
PN5190B1
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PN5190
NFC frontend
8.2 Pin description HVQFN40
terminal 1
index area
1
2
30
29
28
27
26
25
24
23
22
21
3
4
5
PN5190
6
7
central heatsink
connect to GND
8
9
10
Transparent top view
Figure 3.ꢀ Pin configuration for HVQFN40 (SOT2062-1)
Table 4.ꢀPin description HVQFN40
Pin
Symbol
Type
Description PN5190
Number
1
2
3
4
BOOST_LX
VDDBOOST
VSS_REF
VREF
Output
Boost inductance loopback, to be connected to boost inductor pin 1
Boosted supply voltage output
Supply
Supply GND
Output
PMU ground
High quiescent reference voltage, to be connected to ground via 100 nF
blocking cap
5
VBAT
Supply
System supply, used to supply the analog and digital blocks, memory and
internal voltage references
6
VUP_TX
TXVCASC
VSS
Supply
Input supply voltage for transmitter LDO
TX decoupling cap, to be connected to VDDPA
Ground
7
Output
8
Supply GND
Supply
9
VDDPA
TXVCM
Transmitter supply
10
Output
Transmitter voltage common mode, to be connected to ground via 220 nF
blocking cap
11
12
13
14
15
16
TX1
Output
Supply GND
Output
Input
Antenna driver output 1
Transmitter ground
VSS_PA
TX2
Antenna driver output 2
Receiver Input "Negative"
Receiver input "Positive"
RXN
RXP
Input
VMID
Output
Stabilizing capacitor connection output, to be connected to electrical
symmetry point of antenna (typically antenna ground)
PN5190B1
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PN5190
NFC frontend
Table 4.ꢀPin description HVQFN40...continued
Pin
Symbol
Type
Description PN5190
Number
17
18
19
20
21
22
23
VSS
Supply GND
Input
Ground
XTAL1
XTAL2
VTUNE1
AUX_1
AUX_2
Crystal / System clock input
Clock output (amplifier inverted signal output) for crystal
Digital to analog output 0
Output
Output
Output
Output
Output
Test bus 1
Test bus 2
AUX_3 /
VTUNE0
Test bus 3 / VTUNE0 Digital to analog output 1
24
25
26
27
28
29
30
31
32
33
34
35
36
ATX_A
ATX_B
ATX_C
ATX_D
IRQ
Input
SPI slave data output
SPI clock input
Input
Output
Input
SPI slave select input
SPI slave data input
Host communication/ event Interrupt signal
IO pads power supply
General Purpose Out 3
General Purpose Out 2
General Purpose Out 1
General Purpose Out 0
-
Output
Supply
Output
Output
Output
Output
-
VDDIO
GPIO3
GPIO2
GPIO1
GPIO0
n.c.
VSS
Supply GND
Output
Ground
VDDC
Power supply for Digital Core, to be connected to ground via 220 nF blocking
cap
37
38
VEN
Input
Hardware reset, low active (independent from VPVDD)
VDDNV
Output
Non-volatile memory power supply, to be connected to ground via 220 nF
blocking cap
39
40
VBATPWR
VSS_PWR
Supply
To be connected to boost inductor pin 2 and transmitter power supply
DC-DC boost ground
Supply GND
For best performance, all blocking capacitors shall be placed on the same side of the
PCB, traces from pin to capacitor shall be as short as possible.
Compared to the BGA package, all ground connections named VSS are connected
on the leadframe of the package. Therefore general VSS pins do exist, pins are not
distinguished by function like on the BGA package type e.g. VSS_PMU. The exceptions
are the pins VSS_PWR, VSS_PA and VSS_REF.
All Supply GND connections shall be connected by low-ohmic connections on the PCB.
PN5190B1
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PN5190
NFC frontend
9 Functional description
9.1 Functional overview
The PN5190B1 is an NFC frontend with high transmitter output power. It implements
the RF functionality like an antenna driving and receiver circuitry and all the low-level
functionality to realize an NFC Forum and EMVCo compliant reader.
Connection to host controller
The PN5190B1 connects to a host microcontroller with a fast SPI interface (15 Mbit/s)
for configuration, NFC data exchange and high-level NFC protocol implementation. An
optimized TLV-based framing is supported to reduce the command handling overhead on
the host controller and to reduce command-response latencies. Multiple commands are
allowed to be sent within a single frame and processed in sequential order. This reduces
the handshake overhead for a transaction significantly and by this shortens the overall
time of a transaction.
Clock supply
The PN5190B1 uses an external 27.12 MHz crystal as clock source for generating
the RF field and its internal digital logic. Alternatively, an internal PLL allows using an
accurate external clock source of either 24 MHz, 32 MHz and 48 MHz (configured in
EEPROM register CLK_INPUT_FREQ, 0012h)). This allows saving the 27.12 MHz
crystal in systems which implement one of the mentioned clock frequencies.
Integrated DC-DC
The integrated DC-DC allows a single supply voltage while delivering maximum RF
output power. Dependent on the application target either a direct transmitter supply
or a transmitter supply by the integrated DC-DC can be chosen. The usage of the
integrated DC-DC is the preferred choice for a stable RF performance, even in case of
a de-charged battery. Optimized usage of a battery charge can be achieved by directly
connecting the transmitters to the supply. The DC-DC is controlled by the Dynamic Power
Control 2.0 to keep the power dissipation of the chip minimized in antenna loading cases
which require a reduction of the RF output power.
The DC-DC is a step-up converter and is able to deliver an output voltage from approx.
2.8 V up to 6.0 V. The targeted output voltage can be configured by software.
The DC-DC clock is synchronized with the clock of the receiver - this avoids the typical
performance reduction by DC-DC noise which can be seen in systems using external
DC-DCs.
Transmitter LDO (VDDPALDO)
The Transmitter output drivers are supplied by a transmitter LDO which reduces external
noise and is used for the DPC functionality to lower the supply voltage of the transmitters.
The high granularity of 100 mV for setting the VDDPALDO output voltage together with a
sophisticated control loop and true current measurement ensures that a DPC regulation
is not accidentally treated as received data.
Low-power card detection
The low-power card detection (LPCD) allows saving battery charge during polling for
NFC counterparts like cards and mobile phones. In general, the low-power card detection
provides a functionality, which allows to power down the reader for a certain amount of
time to safe energy. After some time, the reader becomes active again to poll for cards. If
PN5190B1
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PN5190
NFC frontend
no card is detected, the reader can go back to the power down state. During the polling
time, a host controller can be set to a power-saving mode. An interrupt request from the
PN5190B1 allows waking up the host controller in case an antenna detuning by a card or
cell phone had been detected.
Two modes for the low-power card detection are available:
• LPCD (software based) which allows maximum detection range. For detecting a card
presence, I/Q channel information is used.
• ULPCD (hardware based) which offers maximum current savings. For detecting a card
presence, only the amplitude information is used.
Dynamic power control 2.0
The next generation Dynamic Power Control (DPC2.0) with true transmitter current
measurement works autonomous without host interaction. Avoiding additional host
controller processing load is important for time critical applications like payment. A fast
control response time of less than 1 ms allows using optimized antenna matchings.
Adaptive wave shape control
The Adaptive Wave Shape Control (AWC) helps to keep the waveshapes within
specification limits, even in case of antenna detuning. This simplifies the time-consuming
antenna matching procedure and does not require any matching compromises to be
taken.
Receiver signal level control
The receiver signal chain consists of an automatic controller RF input attenuator and
a true Baseband Amplifier (BBA). This feature delivers an outstanding communication
range with tags, labels, cards and mobile phones.
RF Debugging
Comprehensive and innovative debug features are implemented to support the NFC
reader development even for difficult and non-standard compliant cards and mobile
phones. An Integrated Chip scope allows performing a non-intrusive debugging of
receiver signals without the need of connecting additional wires to the chip. Capturing of
chip-internal signals is done by configuring flexible trigger conditions, sampled internal
data is stored in RAM memory, transferred by SPI to a host microcontroller and visualized
on a PC by the NFC Cockpit development tool. A virtual comfort interface (VCOM) is
supported by the NFC cockpit tool, which allows to use the NFC cockpit together with any
host microcontroller. Analog debug signals (AUX1, AUX2) are available as well and allow
the connection of an Oscilloscope for analog and digital signal debugging.
The receiver signal processing is optimized to cope with noisy environments. This is
beneficial, especially in case a TFT display or DC-DCs are part of the NFC system.
Automatic EMD error handling
An automatic EMD handling performed without host interaction relaxes the timing
requirements on the Host Controller. Automatic EMD error handling according to ISO/
IEC14443 and EMVCo 3.0 is supported. In addition, the EMD error handling is widely
configurable, which allows adaptions in case of future possible specification changes.
Automatic antenna tuning
Two analog outputs are available to connect variable capacitors for automatic antenna
tuning (AAT). The automatic antenna tuning allows compensating for production
tolerances or changing environments like surrounding metal. This is especially beneficial
PN5190B1
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PN5190
NFC frontend
for applications which make use of OEM NFC Modules which are finally used in an
unknown environment. The automatic antenna tuning is performed command triggered.
Firmware update
The PN5190B1 supports a secure update of the implemented firmware. The secure
firmware download mode is using a dedicated command set, but a framing which is
not different from the standard host interface commands used for NFC operation of
the device. In Secure Firmware update mode, the PN5190B1 requires no dedicated
physical handling of the SPI interface lines. The firmware download does not require
any additional hardware pin to be handled, instead the download mode is activated by a
command, followed by a hardware reset. After booting from reset, the PN5190B1 will be
in download mode.
Register configuration
Internal registers of the PN5190B1 store volatile configuration data and accessible by
the host interface. The internal registers are reset to configurable initial values in case of
powerON, hardware-reset and standby.
The configuration for dedicated RF protocols and antenna-dependent configuration is
defined in non-volatile memory. This configuration is typically done only once during
production, and is performed by a command issued from the host microcontroller.
EEPROM configuration
Non-Volatile EEPROM memory of the PN5190B1 is used to store configuration data that
needs to be preserved in case the PN5190B1 is not connected to any supply voltage.
The configuration for dedicated RF protocols and antenna-dependent configuration is
defined in this non-volatile memory and copied to volatile registers by a host interface
command. In addition, other configuration data which needs to be preserved during
power supply disconnect is stored in this EEPROM memory as well. Examples for this
are configurations for DPC, LPCD and ULPCD configurations.
RF configuration
The PN5190B1 allows a fast RF protocol selection based on the command
Load_RF_configuraton and pre-defined user configuration data in non-volatile memory
(EEPROM).
On the one hand, the configuration of modulation-related parameters can be done (e.f.
selection of ISO/IEC14443-A), on the other hand antenna-specific parameters can be
configured.
For more information see [1].
9.2 Endianness
The endianness describes the order of bytes or bits within a binary representation of a
value in the memory, which can be a register or EEPROM.
"Array size" defines the number of elements of "type size". Type size can be uint8 (8 bit),
uint16 (16 bit) or uint32 (32 bit).
The location of byte sized data (8 bit) with an array size of 2 is as follows:
Value hex: 0x1234
address x: 12
address x+1: 34
PN5190B1
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NFC frontend
The location of word sized data (16 bit) is as follows:
Value hex: 0x1234
address x: 34
address x+1: 12
The location of word sized data (16 bit) in an array size of 2 is as follows:
The placement of the array is large endian, the placement of nibbles of the variable is
small endian.
Value hex: 0xAABBCCDD
address x: BB
address x+1: AA
address x+2: DD
address x+3: CC
The location of double word sized data (32 bit) is as follows:
Value hex: 0xAABBCCDD
address x: DD
address x+1: CC
address x+2: BB
address x+3: AA
12
X
34
Byte sized data (8 bit) with an array size of 2
Data: 0x1234
Data in Memory
Address
X+1
34
X
12
Word sized data (16 bit) with an array size of 1
Data: 0x1234
Data in Memory
Address
X+1
BB
X
AA
DD
CC
Word sized data (16 bit) with an array size of 2
Data: 0xAABBCCDD
Data in Memory
Address
X+1
X+2
X+3
DD
X
CC
BB
AA
Dword sized data (32 bit)
Data: 0xAABBCCDD
Data in Memory
Address
X+1
X+2
X+3
aaa-036897
Figure 4.ꢀEndianness examples
Data from the EEPROM is read in little endian format - LSB first. This means that the
byte at the lower address is read first.
9.3 Initial calibration
The PN5190B1 requires a calibration before the RF field is switched on for the first time.
The calibration sequence is the following:
PN5190B1
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Write EEPROM CfgNovCal (0xC83) – 0x00
Write REGISTER TX_NOV_CALIBRATE_AND_STORE_VAL (addr: 0x5d) - 0x01
Write EEPROM CfgNovCal (0xC83) – 0x02
9.4 System power states
The PN5190B1 can operate in different power states. The functionality and current
consumption is dependent on the actual system power state.
Power states can be changed by the level on the pin VEN and by connecting/
disconnecting the power supply of VBAT.
In addition, state changes are triggered possible by host commands.
Disconnecting and connecting the power supply on VBAT restarts the PN5190B1 always
in Active State after releasing the pin VEN (transition low to high).
A transition of low to high on pin VEN restarts the PN5190B1 always in Active State.
The following power states are supported:
Power state
Description
typical current
consumption
Power OFF
The NFC system (supply pin VBAT, RF transmitter) is not supplied by a
battery/system PMU. Other domains might be supplied (for example, IO
pad interface on pin VDDIO).
-
Device is not functional
PMU OFF
The NFC system is disabled by the host via a low signal on pin VEN. No
internal clocks of the PN5190B1 are active. Wake-up events to change
PMU OFF state: Power reset on pin VBAT, VEN rising edge, RX ULPCD
detect, ULP abort signal on PIN3
5 µA
ULP standby
The host can set the PN5190B1 into Ultra-low power card detection state Variant 1: 5 µA
(ULP Standby state) via programming of the ULPCD bit.
Variant2: 22 µA
In the ULP Standby state, the PN5190B1 is able to activate the transmitter
and receiver after defined time (expiry of wake-up timer) to detect the card.
If a card is not detected, the transmitter and receiver is deactivated and
the wake-up timer restarted. Power consumption of ULP Standby mode
is much lower than Hard Power Down State and Standby State. Only the
wake-up timer is active during ULP Standby state
Wake-up events: Power reset on pin VBAT, VEN rising edge, Card
detected.
Variant 1: Configurable wake-up timer allows system to boot into active
Variant 2: Configurable wake-up timer allows checking regularly for a card
in the field.
Hard power down
The NFC system is disabled by the Host system via the reset/enable
signal on VEN or by detecting an external condition (for example, battery
voltage monitor). The power dissipation is reduced to a minimum. No
power dissipation or leakage is expected on the different interfaces. Low-
power resources are enabled (VDDC_LP, VHV_LP, LQ_REF, LQ-BIAS).
LFO clock is available. PCRM is supplied and is running in low-power
state. I/Os are supplied by VDDC_HP. Wake-up events: Power reset on
pin VBAT, VEN rising edge, RX ULP detect
40 µA
PN5190B1
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NFC frontend
Power state
Description
typical current
consumption
Standby
The NFC system can switch after a specific time of inactivity automatically 45 µA
into a low-power mode to minimize power dissipation. The state of external
interfaces is maintained properly. PMU operates in low-power state. Wake-
up counter clock is available. PCRM is supplied and running in low-power
mode. I/Os are supplied by VDDC_LP. PMU FSM in PCRM manages the
transition in power state. Wake-up sources: Activity on host IF, SWPM
communication, ULPDET, LPDET, wake-up counter, power loss on VDDIO,
GPIO, RxPROT, No High Temp on TX and so on.
Suspend
Active
All power sources are available. LFO and HFO clocks are available.
CPU subsystem clock sources are gated, except for the LFO. I/O's are
available.
2.5 mA
The PN5190B1 is able to process internal or external events or data. All
20 mA (system
external power supply sources and the external clock need to be available, without RF current)
and all internal clocks are active.
9.5 Power supply
The device allows to configure different power supply options for the transmitter power
amplifier. To make use of them, a combination of external connections and chip internal
configurations needs to be done. The following supply options are available:
• Internal VDDPA configuration: The TX power amplifier is supplied by the internal
voltage regulator (VDDPALDO). In this configuration the DPC, current measurement
and overcurrent protection is available. In addition, the VDDPALDO is adding an
improved rejection of noise on the supply lines.
• Direct VDDPA configuration: This configuration is recommended for applications
which require highest efficiency, like battery supplied devices. In this configuration, a
battery can be connected directly to the transmitter supply avoiding the voltage drop of
approximately 0.3 V caused by the VDDPALDO. A clean supply voltage without noise
is required to achieve a good RF performance.
In this configuration the DPC, current measurement and overcurrent protection is not
available.
9.5.1 System power supply overview
The PN5190B1 is using three different supplies each for the following functional blocks:
1. Supply for the host interface and GPIO's (VDDIO)
2. Supply for the analog and digital blocks (VBAT/VBAT_PWR)
3. Supply of the RF drivers (VDDPA), DC-DC (VBAT_PWR) and VDDPALDO (VUP)
The functionality of the GPIO's, Host Interface and internal analog and digital blocks
is independent from the supply of the RF Driver. This allows to configure a dedicated
transmitter supply configuration at any time. Care shall be taken to switch on the RF field
only after the transmitter-related power supply had been configured according to the
external physical supply connections (VDDPA, VBAT_PWR, VUP).
The power supply configuration is configured in EEPROM and therefore will not get
lost in case of power supply loss or reset of the chip. Typically, this configuration is only
performed once during the production of a reader.
PN5190B1
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PN5190
NFC frontend
RF field shall not be turned on without setting the correct power supply configuration in
the EEPROM.
Note: The Voltage on pin VDDIO must always be smaller or equal to the Voltage on pin
VBAT.
9.5.2 Connecting blocking capacitors
Some pins are connected to blocking supply capacitors. PCB traces to these capacitors
need to be as short as possible, and a low-ohmic grounding of the GND-side of the
capacitors is required for optimized RF performance.
0.22
F
TXVCASC
VDDPA
VDDC
TXVCM
VMID
0.22
0.22
F
0.22 F
VDDNV
F
100 nF
VREF
100 nF
aaa-035230
Figure 5.ꢀBlocking capacitors
9.5.3 Transmitter power supply
The PN5190B1 is configured by EEPROM for the different power supply options.
The following registers are used to configure the power supply of the transmitter:
DCDC_PWR_CONFIG (0004h) - Enables/disables and configures the DC-DC according
to the external supply connections.
DCDC_DELAY_TO_ON (0008h) -
DCDC_DELAY_TO_OFF (0009h) -
VDDPALDO_CONFIG (address 000Ch) - Enables/disables and configures the
TXPALDO.
VDDPALDO_VDDPA_HIGH (address 0010h) - out voltage when DC-DC or external
power source is used as supply.
VDDPALDO_VDDPA_LOW (address 0011h) - out voltage when VBAT is used as supply.
VDDPALDO_VDDPA_MAX_RDR (address 0012h) - maximum voltage to be set in reader
mode used by DPC.
VDDPALDO_VDDPA_MAX_CARD (address 0013h) - VDDPA maximum voltage to be set
in card mode used by DPC.
No specific registers are required to configure the pad supply (VDDIO) or the supply for
the analog and digital blocks (VUP).
PN5190B1
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PN5190
NFC frontend
9.5.3.1 VDDPALDO transmitter supply
VDDPALDO supplied VDDPA configuration: The TX power amplifier is supplied by the
internal voltage regulator (VDDPALDO).
In this configuration the DPC, current measurement and overcurrent protection is
available. In addition, the VDDPALDO is adding an improved rejection of noise on the
supply lines.
A decoupling cap is required on VDDPA pin.
Pad supply
(1.8 V or 2.4 to 3.6 V)
IOs
VBAT/VBATPWR
Cvbat
Battery/EXT supply/
USB supply
Connectto
VBAT/VBATPWR supply
or External supply
VUP_TX
Cvup_tx
VDDPALDO
DRIVER
VDDPA
Cvddpa
(a) Internal VDDPA configuration
aaa-035233
Figure 6.ꢀTransmitter supply
9.5.3.2 Direct transmitter supply
Direct VDDPA configuration:
VDDPALDO must be configured OFF by SW configuration. VUP_TX and VDDPA
connected to VBAT/VBATPWR.
PN5190B1
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Pad supply
(1.8 V or 2.4 to 3.6 V)
IOs
VBAT/VBATPWR
VUP_TX
Battery/EXT supply/
USB supply
Cvbat
VDDPALDO
(OFF)
VDDPA
Cvddpa
DRIVER
(a) Direct VDDPA configuration
aaa-035232
Figure 7.ꢀDirect transmitter supply
9.5.3.3 DC-DC (boost) supply
BOOST inductor
(1 H)
VBAT
2.4-5.5 V
BOOST capacitor
(20 F)
VDDBOOST
Decoupling caps
VBAT
Decoupling caps
VUP
Decoupling caps
VDDPA
aaa-035231
Figure 8.ꢀTransmitter supply by DC-DC
9.5.3.4 Configuration example 1: VDDPALDO transmitter supply - DC-DC active
VBAT is connected to VBATPWR.
PN5190B1
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NFC frontend
Vbat Supply
[VBAT]
VBAT
Battery/EXT supply
(2.4 to 5.5 V)
Cvbat
DCDC Supply
[VBATPWR]
VBATPWR
Battery/EXT supply
(2.4 to 4.8 V)
Cvbatpwr
BOOST_LX
DCDC
(SMPS_BOOST)
VDDBOOST
VUP
Cvddboost
Cvup
TXLDO
(VDDPA_LDO)
VDDPA
Cvddpa
Ctxvcasc
DRIVER
(TX_PA)
TXVCASC
aaa-035225
Figure 9.ꢀDC-DC active
9.5.3.5 Configuration example 2: VDDPALDO transmitter supply - DC-DC bypassed
VBAT is connected to VBATPWR.
Vbat Supply
[VBAT]
VBAT
Battery/EXT supply
(2.4 to 4.8 V)
Cvbat
DCDC Supply
[VBATPWR]
Battery/EXT supply
(2.4 to 4.8 V)
VBATPWR
bypass
Cvbatpwr
BOOST_LX
DCDC
(SMPS_BOOST)
VDDBOOST
VUP
Cvddboost
Cvup
TXLDO
(VDDPA_LDO)
VDDPA
Cvddpa
Ctxvcasc
DRIVER
(TX_PA)
TXVCASC
aaa-035226
Figure 10.ꢀDC-DC bypassed (in DCDC_PWR_CONFIG)
9.5.3.6 Configuration example 3: VDDPALDO transmitter supply connected to VBAT - no
DC-DC
VBAT is connected to VBATPWR.
PN5190B1
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NFC frontend
Vbat Supply
[VBAT]
Battery/EXT supply/
VBAT
USB supply
(2.4 to 5.5 V)
Cvbat
DCDC Supply
[VBATPWR]
Battery/EXT supply/
USB supply
VBATPWR
(2.4 to 5.5 V)
Cvbatpwr
BOOST_LX
DCDC
(SMPS_BOOST)
VDDBOOST
VUP
Cvup
TXLDO
(VDDPA_LDO)
VDDPA
Cvddpa
Ctxvcasc
DRIVER
(TX_PA)
TXVCASC
aaa-035229
Figure 11.ꢀNo DC-DC used
9.5.3.7 Configuration example 4: VDDPALDO supplied independent from VBAT - no DC-DC
VBAT is connected to VBATPWR.
Vbat Supply
Battery/EXT supply/
[VBAT]
VBAT
USB supply
(2.4 to 5.5 V)
Cvbat
DCDC Supply
[VBATPWR]
Battery/EXT supply/
USB supply
VBATPWR
(2.4 to VBAT)
Cvbatpwr
BOOST_LX
DCDC
(SMPS_BOOST)
VDDBOOST
VUP
EXT supply
(2.4 to 6.0 V)
Cvup
TXLDO
(VDDPA_LDO)
VDDPA
Cvddpa
Ctxvcasc
DRIVER
(TX_PA)
TXVCASC
aaa-035228
Figure 12.ꢀNo DC-DC used
9.5.3.8 Configuration example 5: VDDPALDO not used - no DC-DC
VBAT is connected to VBATPWR.
PN5190B1
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Vbat Supply
[VBAT]
Battery/EXT supply/
VBAT
USB supply
(2.4 to 5.5 V)
Cvbat
DCDC Supply
[VBATPWR]
Battery/EXT supply/
USB supply
VBATPWR
(2.4 to 5.5 V)
Cvbatpwr
BOOST_LX
DCDC
(SMPS_BOOST)
VDDBOOST
VUP
TXLDO
(VDDPA_LDO)
VDDPA
Cvddpa
Ctxvcasc
DRIVER
(TX_PA)
TXVCASC
aaa-035227
Figure 13.ꢀNo DC-DC used - no VDDPALDO
PN5190B1
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9.5.3.9 Supply voltage range for transmitter supply configuration examples
Table 5.ꢀSupply voltage range
Config1:
Config2:
Config3:
Config4:
Config5:
Supply
VDDPALDO transmitter VDDPALDO
VDDPALDO
VDDPALDO
supplied
VDDPALDO not
used - no DC-DC
supply - DC-DC active
transmitter supply - transmitter
DC-DC bypassed
supply connected independent from
to VBAT - no DC- VBAT - no DC-DC
DC
VBAT
2.8 V … 4.8 V
2.8 V … 4.8 V
2.8 V … 4.8 V
2.8 V … 6.0 V
2.4 V … 5.5 V
2.4 V … 5.5 V
2.4 V ... 6.0 V
2.4 V … 5.5 V
2.4 V ... 5.5 V
2.4 V … 6.0 V
2.4 V … 5.5 V
2.4 V … 5.5 V
2.4 V … 5.5 V
2.4 V … 5.5 V
VBATPWR 2.8 V ... 4.8 V
VUP
3.1 V … 6.0 V
VDDPA
VUP-0.3V drop of
VDDPALDO. max 5.7 V
VBATPWR - 0.5 V
voltage drop
internally
connected to
VDDPALDO
internally
connected to
VDDPALDO
9.6 Clock generation
The device supports the operation with two clock options, which is configured in EEprom
address CLK_INPUT_FREQ (0012h).
One option is clocking by a crystal (default), the other a clocking by an external clock
input frequency.
It is important to consider additional phase noise introduced e.g. by clock drivers in the
design. Phase noise of the external clock will have an impact on the RF performance
which can be achieved.
READER IC
XTAL1 XTAL2
27.12 MHz
001aam308
Figure 14.ꢀClocking by crystal
9.7 External interfaces
The PN5190B1 requires the connection of a power supply, and a clock source like crystal
or external clock and a host microcontroller connected by the SPI interface for operation.
Additional connections of the package require the connection of stabilizing capacitors
and ground.
The RF interface connects transmitter and receiver to the EMC filter of a connected
antenna matching network. Additional connections are available for the GPIO's (on
PN5190B1 only outputs are implemented) and 2x DAC functionality (analog outputs).
The GPIO's implement internal Pull-up/Pull-down resistors. The output of the GPIO's can
be configured in the pad configuration PAD_CONFIG (0052h).
For more information see [2].
PN5190B1
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9.8 Transmitter overcurrent and temperature protection 2
The PN5190B1 implements different mechanisms to protect the chip against damage.
On the one hand, an overcurrent protection exists which shuts down the Transmitter
Driver in case of a out of spec current. This can be enabled in TXPALDO_CONFIG
(000Ch), bit 11: overcurrent enable (0: disable, 1: enable)
On the other hand, an internal temperature sensor allows to monitor the temperature
of the chip. This is configured in the register TEMP_WARNING (0048h). Three
temperatures can be configured: 114 °C, 2:125 °C, 3:130 °C. GPIO1 is used to indicate
this temperature warning to a connected host.
This is a safety feature only. A design shall not functionally rely on this feature since the
operating conditions will be violated if the overcurrent detection becomes active.
9.9 Loading a dedicated RF configuration
The PN5190B1 allows an efficient selection of a dedicated RF protocol.
The selection of one RF protocol is done by sending a command to the PN5190B1. This
instruction is used to load the RF configuration from EEPROM into registers.
It is possible to configure RF technology, mode (target/initiator) and baud rate.
Configurations can be loaded separately for the receiver (RX configuration) and
transmitter (TX configuration).
The Command used for loading a dedicated RF protocol is
LOAD_RF_CONFIGURATION (0Dh).
9.10 Dynamic power control (DPC)
The DPC is used for a special antenna tuning, called "symmetric antenna tuning". For an
"asymmetric antenna tuning", the DPC is not required.
However, even for "asymmetric antenna tuning" with high output power needs, it might
turn out that the RF field is too strong in close proximity of the antenna to be compliant
with ISO/IEC14443 requirements. In this case, the DPC can be used as well to reduce
the RF output power dependent on the distance of the card from the reader antenna.
The DPC works very well with a tuning called "symmetric tuning". With symmetric tuning,
a detuning of the antenna is causing a reduction of the antenna impedance. This low
antenna impedance might lead to a current which is too high for the targeted application.
The DPC allows to limit the transmitter current even under antenna detuning conditions.
DPC is useful:
• To achieve EMVCo analog compliancy
• To achieve NFC Forum and ISO/IEC 14443 compliancy (e.g. NFC Forum Power
Transfer Maximum, ISO/IEC 14443 Field Emission Maximum)
• To improve interoperability
The Dynamic Power Control (DPC 2.0) allows controlling the transmitter driver voltage in
100 mV steps dependent on the actual transmitter current.
2
Please refer to the Errata sheet if the device is used with FW2.0 or FW2.1.
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A lookup table is used to configure the transmitter output voltage and by this control the
RF output power.
Features of the Dynamic power control (DPC 2.0):
• True current measurement provides maximum information for the regulation loop
• The transmitter current can be limited and additionally reduced according to detected
transmitter current condition / antenna detuning condition
• DPC works autonomous without host interaction causing no additional processing load
on the host
• Fastest response time of 1 ms for regulation
• Used for adaptive waveshape control (AWC)
• Used for adaptive RX sensitivity control (ARC)
The DPC is able to operate in two modes:
1. Current limiting mode
2. Current limiting + Current reduction mode
The DPC is configured in the EEPROM, this configuration is used after startup. This
avoids that the host needs to configure the chip after each reset or power-off.
The following EEPROM registers are most relevant for the DPC configuration:
0xF8: DPC_Config: Enables/Disables the DPC (enable: 0x39, disable: 0x00)
0xF9: DPC_TargetCurrent: Unloaded VDDPA target current in mA, the target current +/-
Hysteresis is limiting the current for the DPC.
• The DPC_TargetCurrent is the current which can be measured for the selected antenna
impedance and transmitter supply voltage in unloaded condition. This is the current the
system is designed to operate at.
0xFB: DPC_Hysteresis: Absolute difference to current target current in mA that triggers
a DPC update event.
• The configuration of the hysteresis ensures, that the DPC is not regulating if small
changes of the transmitter current occur due to external disturbances. A typical value
for the DPC_Hysteresis is e.g. 20 mA.
0x8B: DPC_Lookup_Table: configures the current reduction
The DPC_LOOKUP_TABLE allows in addition to the limitation of the current, to configure
• an additional current reduction on top of the current limitation, achieved by further
lowering the transmitter supply voltage
• a relative change of modulated amplitude level
• and a relative change of falling and raising edge time constant for ASK10% and
ASK100% modulations
This lookup table is initialized with 0x00 for devices delivered from the factory. (The
customer development board is already initialized with useful data in EEPROM which
work well with the antenna of the board).
The 0x00 entry in the DPC_LOOKUP_TABLE means that no additional function then the
current limitation takes place for the DPC.
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In order to achieve a limitation of the current even in the case of an antenna impedance
that is lowered, the Transmitter supply voltage is reduced accordingly.
This transmitter supply voltage reduction is now used as index for the
DPC_LOOKUP_TABLE.
For a specific transmitter supply voltage, it is possible to further reduce the current
below the value of DPC_TargetCurrent or to configure parameters for waveshaping and
modulation. All these entries are relative values, granularity of the entries dependent on
the transmitter supply voltage is 0.1 V, resulting in 42 table entries.
The DPC updates the content of the following register dependent on the antenna load /
lookup table configuration:
0x30 - DGRM_RSSI
IVDDPA
VDDPA
DPC Configuration Table
with PowerReduction for Hmax
VDDPA/VBOOST
Configuration
DPC
AWC
Loading strength
information
TX Signal Scalling
Only if VDDPA scaling not
possible any more
AWC Configuration Table
CLIF Signal Shaping
Load dependent offset reconfig
Falling/rising edges: Time Constant
Modulation index
Unloaded PCD Shaping
Configuration
FW- based TX edge
pattern generation
Level output stream
CLIF Receiver Gain and
Threshold Configuration
Load dependent
receiver settings
ARC Configuration Table
ARC
Host IF accessible configuration
Technology dependent
aaa-038384
Figure 15.ꢀSystem overview: DPC, AWC and ARC
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Type A-106
Type A-212
Type A-424
VDDPA LUT
ARC settings 0
ARC settings 1
ARC settings 2
ARC settings 3
ARC settings 4
VDDPA Voltage Entry 0
VDDPA Voltage Entry 1
Type A-424
VDDPA Voltage
Type A-848
DPC
VDDPA Voltage Entry 2
VDDPA Voltage Entry 3
VDDPA Voltage Entry 4
Type B-106
Type B-212
Type B-424
VDDPA index
(0,1,2,3,4)
Type B-848
Configure
protocol and
datarate
Type F-212
Receiver settings
Receiver settings
configuration
Type F-424
Type F-424
15693 26K
15693 53K
15693 106K
15693 212K
180003m3 SC424-Man2
180003m3 SC424-Man4
180003m3 SC848-Man2
180003m3 SC848-Man4
aaa-038526
Figure 16.ꢀSystem overview: DPC, AWC and ARC
Next DPC algorithm check
RF field envelope:
t
DPC,CurrMeas,GuardTime
t
DPC,VDDPAReconfig
t
t
DPC,Updateinterval
DPC,RegulationDone
Current
Meas
New
VDDPA
Update PCD
Shaping
Current
Meas
DPC algorithm:
Update VDDPA
aaa-038399
Figure 17.ꢀSystem overview: DPC, AWC and ARC
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Measured current I
not in target current range
VDDPA,mcas
Estimate load impedance Z
based ON
L,estimated
LDO_VDDPA_VOUT_SEL and l
n
VDDPA,mcas
Determine new LDO_VDDPA_VOUT_SEL
target current and est. load Impedance Z
based on
n+1
L,estimated
Find last active entry in reconfiguration table (index:
new VDDPA configuration)
Reconfiguration
changes
new target current?
yes
Determine new LDO_VDDPA_VOUT_SEL
n+1
new target current and est. load Impedance Z
based on
L,estimated
no
Find last active entry in reconfiguration table (index:
new VDDPA configuration)
Apply VDDPA voltage change LDO_VDDPA_VOUT_SEL
n+1
Apply PCD shaping for active technology based on
unloaded configuration and AWC re-config
DPC update completed
aaa-038400
Figure 18.ꢀSystem overview: DPC, AWC and ARC
9.10.1 DPC algorithm
The DPC algorithm is controlling the transmitter current. It is using the following states:
1. Current measurement: Performs VDDPA current measurement
2. New VDDPA: Determine new VDDPA configuration based on measured current
VDDPA New (for target current of Itarget) = VDDPA Voltage / VDDPA current * Itarget
3. Update VDDPA: Perform output power update
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4. Update PCD Shaping: Apply AWC configuration updates for active technology
5. Update RX sensitivity parameter only for short duration
Reconfiguration table includes Relative changes of target current and of waveform
parameters adaption for all VDDPA voltage configurations. The VDDPA configuration is
implicitly defined by the row index. The first row refers to LDO_VDDPA_VOUT_SEL=0
(represents 1V5).
EXAMPLE:
Unloaded configuration After Field ON:
VDDPA max set to 42 (5.7 V) ·Target current set to 280 mA
Technology B106: amp_mod=200
Falling edge time constant=rising edge time constant=3
Table 6.ꢀDPC_LOOKUP_TABLE element, defining the configuration for one dedicated VDDPA voltage
Function
Bit
Description
ENTRY 0
31:0
This is the entry for 1.5 V.
Target current
reduction
ENTRY 0 -LSB - byte 0
31:23
Voltage step between DPC entries = 100 mV. Voltage offset start = 1.5 V bEntry_00 =
1V5 ... bEntry_42 = 5V7
Bits[7:0] = Target current reduction in mA (unsigned)
AWC amp mod
change
23:16
15:8
ENTRY 0 - byte 1
Bits[7:0] = Relative change of modulated amplitude level (signed)
AWC edge time
ENTRY 0 - byte 2
constant for ASK100
Bits[3:0] = ASK100, Relative change of falling edge time constant (signed)
Bits[7:4] = ASK100, Relative change of rising edge time constant (signed)
AWC falling edge time 7:0
constant for ASK10
ENTRY 0 -MSB - byte 4
Bits[3:0] = ASK10, Relative change of falling edge time constant (signed)
Bits[7:4] = ASK10, Relative change of rising edge time constant (signed)
Loaded configuration After Field ON:
DPC regulates from unloaded VDDPA configuration 42 to 31. Consequently, new
configuration to be applied based on index entry 31.
Target current stays at 280 mA.
Technology B106: amp_mod=205, falling edge time constant=2, rising edge time
constant=0
9.10.2 DPC characteristics
Table 7.ꢀDynamic power control characteristics
Symbol Parameter Conditions
Minimum hysteresis configured Depends on
in EEPROM DPC_HYSTERESIS application target
(address 079h) current
Min
Typ
Max
Unit
ApplicationTargetCurrent -
* 0.0609 + 2 mA
-
mA
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Table 7.ꢀDynamic power control characteristics...continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Max target current
Hysteresis as
-
350-
mA
configured in EEPROM
DPC_TARGET_CURRENT
(077h)
configured in
DPC_HYSTERESIS
(address 079h)
Hysteresis
9.11 Adaptive waveshape control (AWC)
Depending on the level of detected detuning of the antenna, wave shaping related
register settings can be automatically updated.
Two different waveshaping mechanisms can be used:
1. Firmware based shaping (1,2,3)
2. Lookup table based shaping (4,5,6)
The Firmware based shaping allows to correct rise times and overshoot with linear
transition shapes.
The lookup table based shaping allows maximum flexibility and enables to configure
almost any possible correction.
Example: rising edge
RF amplitude
transition
2
unmodulated
3
Edge type
1
1 = linear
2 = 2x linear
3 = 3x linear
4, 5, 6 = any shape (look up table)
4, 5, 6
modulated
up to 16/fc
t
aaa-037863
Figure 19.ꢀWaveshaping transitions (example falling edge)
The shaping related register settings are stored in a lookup table located in EEPROM,
and selected dependent on the actual detected detuning condition.
Each lookup table entry allows the configuration not only of a dedicated wave shaping
configuration for the corresponding detuning condition. But allows in addition to configure
the wave shaping individually dependent on the actual protocol which is active.
Features of the Adaptive Waveshape Control:
• No external components required
• No need to compromise antenna matching to meet waveshape requirements
• Waveshapes automatically adapted according to detected detuning condition
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• RF standards define envelope timing and residual carrier parameters required for
compliance and interoperability.
The device supports the design of compliant antennas by allowing to actively shaping the
style of edge transition for falling and rising edges. The shaping of modulation edges is
achieved by selecting one from three edge transition styles:
1. Linear transition between two amplitude levels
2. Two linear transition´s between amplitude levels and
3. Three linear transitions between amplitude levels.
The type of the transition is selected in the EEPROM registers EDGE_TYPE_(protocol),
and can be defined independent for each RF protocol and data rate - for both falling and
rising edge.
The EEPROM registers EDGE_STYLE_(protocol) define the time constant "s" of falling/
rising edge (depends on edge style).
The EEPROM registers EDGE_LENGTH_(protocol) define the total length of the edge
pattern.
The figures below illustrate the edge type for the falling edge.
amplitude
CW
MOD
level a
k=-(a-b)/s
level b
time constant s
length of edge pattern l
start of
edge pattern
end of
edge pattern
time
aaa-035963
Figure 20.ꢀOne linear transition (example falling edge)
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amplitude
level a
CW
MOD
k1=-2(a-b)/(3s)
k2=k1/2
level b
time
constant s
length of edge pattern l
start of
edge pattern
end of
edge pattern
time
aaa-035964
Figure 21.ꢀTwo linear transitions (example falling edge)
amplitude
CW
MOD
level a
k1=-2(a-b)/(3s)
k2=k1/2
k3=k2/2
level b
time
constant s
s/2
length of edge pattern l
start of
edge pattern
end of
edge pattern
time
aaa-035965
Figure 22.ꢀThree linear transitions (example falling edge)
The transition patterns are used as implicit pre-distortion to compensate effects of TX
loading circuitry (e.g. resonant circuitry parameters) to the emitted RF envelope.
9.12 Adaptive receiver control (ARC)
Depending on the level of detected antenna detuning, receiver-related register settings
can be automatically updated. The receiver-related registers which are allowed to be
dynamically controlled are:
DGRM_RSSI_REG (30h) ->DGRM_SIGNAL_DETECT_TH_OVR_VAL
SIGPRO_RM_TECH_REG (22h) ->RM_MF_GAIN,
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The adaptive receiver control settings override the default RM_MF_GAIN and
DGRM_SIGNAL_DETECT_TH_OVR_VAL settings configured by the command
LOAD_RF_CONFIGURATION (0Dh).
The ARC algorithm is called when VDDPA voltage changes after DPC. There
are two lookup tables used in ARC algorithm i.e VDDPA lookup and ARC
lookup. In case of a VDDPA change, an EEPROM lookup (at current protocol
and baud rate) is performed. The receiver-related settings i.e RM_MF_GAIN,
DGRM_SIGNAL_DETECT_TH_OVR_VAL and IIR_ENABLE are read from EEPROM
lookup table and configured in registers.
VDDPA lookup table:
VDDPA lookup table define maximum five voltage ranges. Number of VDDPA
voltage ranges used in ARC algorithm is configured in bArcConfig[2:0]. VDDPA
voltage output from DPC algorithm is input to VDDPA lookup. VDDPA lookup returns
VDDPA_range_index (i.e 0,1,2,3,4).
Table 8.ꢀARC_VDDPA (0139Eh) EEPROM configuration bit description
Address Function
(hex)
Bit
Description
13D
ARC VDDPA
Setting
7:0
Byte[4] = ARC_VDDPA_0: ARC_VDDPA_3 > VDDPA < ARC_VDDPA_4
13C
13B
13A
139
7:0
7:0
7:0
7:0
Byte[3] = ARC_VDDPA_0: ARC_VDDPA_2 > VDDPA < ARC_VDDPA_3
Byte[2] = ARC_VDDPA_0: ARC_VDDPA_1 > VDDPA < ARC_VDDPA_2
Byte[1] = ARC_VDDPA_0: ARC_VDDPA_0 > VDDPA < ARC_VDDPA_1
Byte[0] = ARC_VDDPA_0: 1.5 > VDDPA < ARC_VDDPA_0
ARC lookup table:
VDDPA index and RF protocol/datarates are input to ARC lookup. There are five
Receiver settings entries for each protocol and data rates. ARC algorithm select one out
of five entries (at current protocol and baud rate) based on VDDPA_range_index.
Following table show ARC settings for Type A-106.
Table 9.ꢀARC_RM_A106 (address 013Eh) EEPROM configuration bit description
Address Function
(hex)
Bit
Description
146
RM_RX_ARC_4 15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT,
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 9.ꢀARC_RM_A106 (address 013Eh) EEPROM configuration bit description...continued
Address Function
(hex)
Bit
Description
144
142
140
13E
RM_RX_ARC_3 15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT,
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_2 15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT,
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1 15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT,
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0 15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: For ISO14443-A: In case ARC is disabled, it requires DPC_
SIGNAL_DETECT_TH_OVR_VAL larger than 0x50 (with MF_GAIN = 2 (default))
Note: For ISO14443-A: In case Bit[15] is configured to 0, it requires DPC_
SIGNAL_DETECT_TH_OVR_VAL larger than 0x50 (with MF_GAIN = 2 (default)) if the
ARC is enabled.
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9.13 Timer
PN5190
NFC frontend
The PN5190B1 implements three different types of timers: 2 general-purpose timers
(only general-purpose Timer0 is accessible by the user, Timer1 is used by the PN5190B1
as FDT Timer), 1 wake-up timer and 1 low frequency timer.
General-purpose timer
The PN5190B1 implements two 20-bit wide general-purpose timers - Timer0 and Timer1.
Timer0 can be configured by 2 registers each (TIMER0_CONFIG, TIMER0_RELOAD).
Timer 1 is typically used for as FDT and EMD timer configuration. Configuration can be
done from the host but the associated IRQ is handled by the firmware of the PN5190B1.
The Timer1 events are consumed by the PN5190B1 FW and respective Time-out status
is included as part of the command response.
The general-purpose Timer0 and the FTD Timer1 have a max count of 1.048.575.
The register TIMER0_CONFIG, TIMER0_RELOAD configure if either the 13.56 MHz
clock of the RF interface is used as Timer input, or if a divided clock frequency is used as
input. These registers configure as well the start conditions for the timer.
The following clock frequencies can be selected for the pre-scaler:
000b - 6.78 MHz counter
001b - 3.39 MHz counter
010b - 1.70 MHz counter
011b - 848 kHz counter
100b - 424 kHz counter
101b - 212 kHz counter
110b - 106 kHz counter
111b - 53 kHz counter
Wake-up timer
The PN5190B1 implements one 10-bit wide wake-up timer.
Max count of the wake-up timer is 1023, inout clock is the LFO CLK = 380 kHz. The max
timeout is 269 ms.
The wake-up time is configured via the SWITCH_MODE_STANDBY /
SWITCH_MODE_LPCD commands. There is no dedicated register available for
this timer. The PN5190B1 enters the standby state by the switch mode command
SWITCH_MODE_STANDBY/ SWITCH_MODE_LPCD. The counter value is part of the
command and has to be sent as one configuration parameter. The 2-byte parameter
value for the standby counter is indicating the counting time in milliseconds. The value
needs to be provided in little-endian format.
Low frequency timer
The wakeup-counter for the ULPCD mode has a width of 12bits.
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The input clock for this timer is 1 kHz. ULPCD uses the ULP_STANDBY command, and
for this the wake-up timer is feed by the 1 kHz clock. Count down value (12 bits counter;
ULFO CLK / 4096 = 0.244 Hz i.e. 1 ms per bit).
The max timeout is 4.096 s.
Timer for contactless interface
In addition to the timers above, to guarantee correct protocol timing, a guard period timer
is implemented for the RF_EXCHANGE command in reception and transmission mode
(TX_WAIT, RX_WAIT counting).
No configuration of this timer is available for the user, setup and counting is managed
completely by the hardware. Therefore this timer is not indicated in the timer overview.
Timer start
configuration
T0_PRESCALE_SEL
PRESCALER
User timer 0
20 Bit
13.56 MHz
Internally configured
PRESCALER
FDT timer 1
20 Bit
Internally configured
Timer events
Wakeup-timer (configured by command)
10 Bit
380 kHz
1 kHz
Low frequency timer (configured by command)
12 Bit
aaa-036459
Figure 23.ꢀTimer overview
9.14 Low-power card detection
The low-power card detection (LPCD) and ultra-low power card detection (ULPCD) are
an energy-saving card polling configuration for the PN5190B1. During LPCD, a host
microcontroller can be set into power-saving mode, as no host controller interaction is
required.
A low frequency timer is implemented to drive a wake-up counter, which triggers a
periodic activation of the antenna drivers to emit a short pulse which allows to detect
a detuning of the antenna. In case of a detected antenna detuning, the system is
woken up from power-saving mode. It sends an interrupt signal to the connected host
microcontroller to wake up the host microcontroller from power-saving mode and to
indicate a change of the antenna detuning condition.
There is no trimming for the Low Frequency Timer required.
The SWITCH_MODE instruction allows entering the LPCD mode with a given standby
duration value.
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SWITCH_MODE_LPCD
(ULPCD)
Configure measurement
interval, threshold
Enter Ultra low power card
detection mode and perform
card detection task at
Abs(ref-measured) <
threshold
configured time intervals
Event signaling card
detection
Active Mode
Low power mode
aaa-038408
Figure 24.ꢀLPCD configuration and card detection loop
9.14.1 Low-power card detection (LPCD)
The low-power card detection (LPCD) is an energy-saving card polling configuration for
the PN5190B1. During LPCD, a host microcontroller can be set into power-saving mode,
as no host controller interaction is required. The host microcontroller is woken up from
power-saving mode by an IRQ send by the PN5190B1.
The LPCD mode offers highest sensitivity at the cost of slightly higher current
consumption compared to the ULPCD mode.
A low frequency oscillator (there is no trimming for the low frequency oscillator required)
is implemented to drive a wake-up counter, which triggers a periodic activation of the
antenna drivers to emit a short RF pulse. This RF pulse allows to detect a detuning of the
antenna by presence of conductive objects in proximity of the antenna (card, cell phone,
metal).
In case of a detected antenna detuning, the system wakes up from power-saving
mode. It sends an interrupt signal to the connected host microcontroller to wake up the
host microcontroller from power-saving mode and to indicate a change of the antenna
detuning condition.
A low frequency oscillator (LFO) is implemented to drive a wake-up counter, waking-up
PN5190B1 from standby mode. This allows implementation of low-power card detection
polling loop at application level.
The host microcontroller can then perform a card polling sequence to verify if the
technology of the object causing the antenna detuning is supported by the system.
The SWITCH_MODE instruction allows entering the LPCD mode with a given standby
duration value.
PN5190B1
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SWITCH_MODE_LPCD
Enter standby with wakeup
counter configured
Field ON and perform
measurement of ADC_I and
ADC_Q values
no
Abs(Ref value - Measured
value) > Threshold
yes
Active Mode
Event signalling card detection
Low power mode
aaa-038409
Figure 25.ꢀLPCD configuration
The LPCD mode is entered by the host interface command SWITCH_MODE_LPCD
(23h), and terminated by the command SWITCH_MODE_NORMAL (20h). In addition,
terminating the LPCD mode is possible by toggling a GPIO, by a reset (VEN) of the
PN5190B1 or a signal of the RF Level detector.
Before entering the LPCD mode, ADC_I and ADC_Q reference value needs to be
determined. This is done during the so called calibration.
LPCD calibration phase
a) An initial calibration measurement is performed to set up the RX chain parameters
namely HFATT, DCO_DAC_I_CTRL and DCO_DAC_Q_CTRL values.
b) The next measurement is done using the RX chain parameters that are set up, to
arrive at the ADC_I and ADC_Q values which are used as reference values. All following
LPCD measurements are done relative to the LPCD calibration measurement.
The LPCD loop itself works in two phases:
First the standby phase is controlled by the wake-up counter (timing defined in the
instruction), which defines the duration of the standby of the PN5190B1.
Second phase is the detection-phase. The RF field is switched on for a defined time
(EEPROM configuration) and then the ADC_I and ADC_Q values are compared to a
reference value.
• If the ADC_I and ADC_Q values exceed the reference value, a LPCD_IRQ is raised
to the host. The register configurations done by the host to support a dedicated RF
protocol are not restored after wake-up command. The host has to configure the NFC
frontend for a dedicated protocol operation to allow a polling for a card.
• If the ADC_I and ADC_Q values do not exceed the thresholds of the reference value,
no LPC_IRQ is raised and the IC is set to the first phase (standby mode) again.
These two phases are executed in a loop until:
PN5190B1
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- Card / metal is detected (LPCD_IRQ is raised).
- Reset occurs, which resets all the system configurations. The LPCD is also terminated
in this case.
- NSS on host interface
- RF Level Detected
- GPIO toggle
As feature, the GPIO1 (general-purpose input/output) pin can be enabled to wake up an
external DC-DC from power down for the VDDPA supply. The GPO1 allows setting to
high before the transmitter is switched on. This allows the wake-up of an external DC-DC
from power down. The GPO1 can be set to low after the RF field is switched off to set an
external DC-DC into power-down mode. The time of toggling the GPO in relation to the
RF-on and RF-off timings can be configured in EEPROM addresses 0xXX and 0xXX.
The behavior of the generated field is different dependent on the activation state of the
DPC function:
• If the DPC feature is not active, the ISO/IEC14443 type A 106 kbit/s settings are used
during the sensing time.
• If the DPC is active, the RF_ON command is executed. The RF field is switched on
as soon as the timer configured by the SWITCH_MODE command elapses. The RF
field is switched on for a duration as defined for an activated DPC. The timer for the
LPCD_FIELD_ON_TIME starts to count as soon as the RF_ON command terminates.
Table 10.ꢀLow-Power Card Detection: relevant EEPROM configuration
EEPROM Name
address
Description
0492
LPCD_AVG_SAMPLES
Defines how many samples of the I and Q values are used for the averaging.
Used to optimize the system to achieve highest detection sensitivity versus false
alarms.
0494
LPCD_RSSI_TARGET
LPCD_RSSI_HYST
Value to be used as the RSSI target in the calibration phase to arrive at the RX
chain parameters.
This parameter is used to arrive at an optimal target voltage level at RXP.
0496
Value to be used as the RSSI hysteresis in the calibration phase to arrive at the
RX chain parameters.
This is used to avoid oscillations while arriving at the target voltage level at RXP.
049E
04B5
0013
LPCD_THRESHOLD
LPCD_VDDPA
If the difference between the measured value of I/Q and the reference value for I/
Q is greater than the threshold on either channels, then a card is detected.
VDDPA voltage when DC-DC (internal or external) or external power source is
used to feed TXLDO
XTAL_CHECK_DELAY
Interval which is used to check if XTAL is ready (unit is 256/fc, e.g. ~18.8 us).
For fastest startup this time, a check is performed at a time slightly higher than
the expected startup time of the crystal.
9.14.2 Semi-autonomous mode (LPCD)
LPCD semi-autonomous mode
The LPCD can be invoked by the host in the semi-autonomous mode wherein the ADC_I
and ADC_Q values that are measured is returned back to the host.
PN5190B1
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In this mode, standby is not entered and the difference between the measured and
reference values are not checked against the threshold. Nevertheless, the host
may check the measured values against a reference and threshold to detect a card
and also put the PN5190B1 in standby mode between measurements, using the
SWITCH_MODE_STANDBY command.
This mode is especially useful to find optimized settings for the LPCD, since it does not
offer no significant current saving.
Table 11.ꢀLow-Power Card Detection - semi-autonomous mode: relevant REGISTERS
REGISTER Name
address
Description
0050
LPCD_CALIBRATE_CTRL
Writing to this register triggers the LPCD calibration with the LPCD
RSSI_HYSTERESIS and LPCD RSSI_TARGET values. After
calibration is completed calibration status is available in LPCD_
CALIBRATE_STATUS. If the calibration is successful, the I/Q channel
values can be read from register IQ_CHANNEL_VALS
0051
0053
IQ_CHANNEL_VALS
Actual I/Q channel value
LPCD_CALIBRATE_STATUS
1: if successful - a new calibration clears this value
9.15 Automatic EMD error handling
The PN5190B1 supports a configurable EMD handling according to the ISO14443 or
EMVCo standard. To support further extensions or changes of these standards, the EMD
block is configurable.
After being configured, the PN5190B1 restarts both the receiver and a timeout timer
automatically without host interaction in case of a detected EMD event.
Features of the Automatic EMD Error Handling:
• No real-time constraints
• Less processing load on the host processor
• Configurable, anticipating future specification changes
In addition to the EMD error handling according to ISO14443 and EMVCo, the
PN5190B1 implements special features for FeliCaTM preamble processing.
Registers CLIF_RX_EMD_1_CONFIG(0x47) and CLIF_RX_EMD_0_CONFIG(0x48) hold
the configurations for the EMD configurations for ISO/IEC14443, and NFC Forum.
EMVCo EMD configuration is supported in the register EMVCO_EMD_CONTROL (0x3).
9.16 Autocoll (card emulation)
The Autocoll state machine performs the time critical activation for Type-A PICC and for
NFC-Forum Active and Passive Target activation (card emulation mode).
The PICC state machine supports three configurations:
• Autocoll mode0: Autocoll mode is left when no RF field is present
• Autocoll mode1: Autocoll mode is left when one technology is activated by an external
reader. During RFoff, the chip enters standby mode automatically
• Autocoll mode2: Autocoll mode is left when one technology is activated by an external
reader. During RFoff, the chip does not enter standby mode.
PN5190B1
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At start-up, the Autocoll state machine automatically performs a LOAD_RF_CONFIG
with the General Target Mode Settings. When a technology is detected during activation,
the Autocoll state machine performs an additional LOAD_RF_CONFIG with the
corresponding technology.
The card configuration for the activation is stored in EEPROM. If RandomUID is enabled
(EEPROM configuration), a random UID is generated after each RF-off.
For all active target modes, the own RF field is automatically switched on after the
initiator has switched off its own filed.
entry
IDLE
Frame received
SensF received
Frame received
no
no
no
and Passive
ReqA/WupA
yes
and no error
Target F enabled
yes
yes
Active Mode
enabled
SC = 0xFFFF or
EE-Value
Passive Target A
enabled?
no
no
Yes and
Autocoll_state_a** == HALT
Any CL
Error
SensFReq
received
yes
ISO14443-3A PICC
state machine
Send SensF
response
Yes and
Autocoll_state_a** == IDLE
any other frame
received
HALT
READY*
ACTIVE*
READY
ACTIVE
Passive Target F212/424*
IRQ line is asserted
Load Protocol PICC-F212
or PICC-F424 done
RX_IRQ and
Active Target A106/F212/F424*
IRQ line is asserted
Load Protocol AT106/AT212/
AT424 done
Passive Target A106
IRQ line is asserted
Load Protocol PICC-A106 done
RX_IRQ and
RX_IRQ is set
CARD_ACTIVATED_IRQ are set
CARD_ACTIVATED_IRQ are set
*the determined baudrate can be found in the SIGPRO_CONFIG register
** Autocoll_state_a is defined in the register SYSTEM_CONFIG
aaa-020625
Figure 26.ꢀ Autocall state machine
PN5190B1
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9.17 RF-level detection
The PN5190B1 implements an RF level detector (RFLD) and an NFC level detector
(NFCLD) which allows to detect the presence of an external RF field.
RF Level Detector:
During low-power card detection (LPCD), the RF level detector (RFLD) acts as wake-up
source from power-saving mode.
During ultra low-power card detection (ULPCD), a specific ultra low-power RF level
detector is used as RF level detector(RFLD). This can be enabled as wake-up source.
The purpose of the RFLD function is to detect any signal at 13.56 MHz in order to wake
up the PN5190B1 from power-saving mode.
NFC Level Detector:
The NFC Level detector (NFCLD) is used during full power mode. The NFCLD function is
required by NFC Forum to support the "RF collision avoidance".
The sensitivity of the NFCLD sensor can be configured by EEPROM register to meet the
NFC Forum requirements.
It can be used as well in card mode to detect an external field.
9.18 Antenna tuning with variable capacitors
The PN5190B1. allows the tuning of the connected antenna based on variable
capacitors.
Variable capacitors are devices which allow to change their capacity dependent on
a supplied control voltage. Typically, these capacitors are used as serial and parallel
capacitors in an antenna matching network.
The PN5190B1 allows to measure a detuning of the connected antenna caused e.g. by
surrounding metal and correct the actual detuning by applying an appropriate control
voltage on 2 analog outputs.
To correct a potential detuning of the connected antenna, a phase measurement needs
to be performed. The following sequence is required to read out the phase information:
Step 1: Disable DPC
Step 2: Perform Type A-106 load protocol
Step 3: Set the VDDPA Voltage as 푉ꢀ_푉((푑ꢁꢀ푝푝ꢂ푎
Step 4: Perform RF ON
Step 5: Read out RXM phase
Step 6: Perform RF OFF
Step 7: Enable DPC
For reading the RXM phase, refer to the related application note. Based on the phase
information, a host is able to calculate the DAC output voltages to correct a detuning.
The antenna tuning requires the DPC to be disabled, and is typically not suitable for
dynamic tuning e.g. during card communication.
PN5190B1
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VC
1
L
R
s
R
a
0
Tx1
C
1
C
C
C
C
VC
VC
0
0
2
2
2
2
C
L
a
a
GND
Tx2
C
1
L
R
s
0
EMC Filter
Antenna Coil
aaa-041704
VC
1
Matching Network
Figure 27.ꢀAntenna connection using variable capacitors
9.19 RF debug signals
The following signals are available for debugging purposes:
The test signals are selected by sending a command string to the
PN5190B1. The commands CONFIGURE_ TESTBUS_DIGITAL (12h) and
CONFIGURE_TESTBUS_ANALOG (13h) are used to configure the dedicated signal on
an output pin.
If used, ADC-Q needs to be routed always to AUX1, ADC-I needs to be routed
always to AUX2
The analog test signals are analog representation of an internal digital value. The internal
digital signal is converted by an 8-bit wide DAC to the analog signal.
This overview indicates the signals which are available for debugging purposes
(indicated by numbers):
1
3
MF
S0
A
RxP
IIR
M
D
10
15
-
5
6
15
15
MF
S0
CH
COMBINER
HF-
Attenuator
Data
SYNC
FILTER
DECODER
7
MF
S1
CH
COMBINER
10
15
MF
S1
A
IIR
M
RxN
D
2
4
aaa-037146
Figure 28.ꢀReceiver block diagram
Table 12.ꢀDEBUG SIGNALS
Signal REGISTER
SIGNAL BITS
NAME
Description
Unfiltered I channel signal
ADC Data I Channel (1) obs_clif_
tbcontrol_
adc_
9:2
data_i_i
upper 7 bit of the 10 bit signed unfiltered I channel
signal including sign (bit9)
patchbox0
PN5190B1
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Table 12.ꢀDEBUG SIGNALS ...continued
Signal
REGISTER
SIGNAL BITS
NAME
Description
obs_clif_
tbcontrol_
patchbox1
9; 6:0
Unfiltered I channel signal
lower 7 bit of the 10 bit signed unfiltered I channel
signal including sign (bit9)
ADC Data Q Channel (2) obs_clif_
tbcontrol_
adc_
data_q_i
9:2
Unfiltered Q channel signal
upper 7 bit of the 10 bit signed unfiltered Q channel
signal including sign (bit9)
patchbox2
obs_clif_
tbcontrol_
patchbox3
9; 6:0
Unfiltered Q channel signal
lower 7 bit of the 10 bit signed unfiltered Q channel
signal including sign (bit9)
Preprocessor Out I
Channel (3)
obs_clif_sigpro_ rm_cor_ 14:8
Pre-processed ADC data I channel
rm0
adc_i_o
upper 7bit of 15bit signed pre-processed ADC data I
channel, after IIR Filter and down-sampling including
sign (bit14) bit 15: RFU
obs_clif_sigpro_
rm1
7:0
Pre-processed ADC data I channel
lower 8bit of 15bit signed pre-processed ADC data I
channel, after IIR Filter and down-sampling
Preprocessor Out Q
Channel (4)
obs_clif_sigpro_ rm_cor_ 14:8
Pre-processed ADC data I channel
rm2
adc_q_o
upper 7bit of 15bit signed pre-processed ADC data Q
channel, after IIR Filter and down-sampling including
sign (bit14) bit 15: RFU
obs_clif_sigpro_
rm3
7:0
Pre-processed ADC data I channel
lower 8bit of 15bit signed pre-processed ADC data Q
channel, after IIR Filter and down-sampling
Output MF S0 (5)
obs_clif_sigpro_ mf_pt_
14:8
Delayed matched filter S0 output, after CH combiner
rm4
s0_d
upper 7 bit of the 15 bit signed delayed matched filter
S0 output, after Channel combiner including sign
(bit14) bit 15: RFU (ignore)
obs_clif_sigpro_
rm5
7:0
Delayed matched filter S0 output, after CH combiner
lower 8 bit of the 15 bit signed delayed matched filter
S0 output, after Channel combiner
Output MF S1 (6)
obs_clif_sigpro_ mf_pt_
14:8
Delayed matched filter S1 output, after CH combiner
rm6
s1_d
upper 7 bit of the 15 bit signed delayed matched
filter S1 output, after Channel combiner including
sign (bit14) bit 15: RFU (ignore) Remark: S1 is not
relevant for type A 106
obs_clif_sigpro_
rm7
7:0
Delayed matched filter S1 output, after CH combiner
lower 8 bit of the 15 bit signed delayed matched filter
S1 output, after Channel combiner Remark: S1 is not
relevant for type A 106
Output Synchronization
Filter (7)
obs_clif_sigpro_ sync_filt_ 14:8
Synchronization filter output
rm8
out
upper 7 bit of the 15 bit signed synchronization filter
output including sign (bit14) bit 15: RFU (ignore)
obs_clif_sigpro_
rm9
7:0
Synchronization filter output
lower 8 bit of the 15 bit signed synchronization filter
output
clif_status
transceive_state
7:5
PN5190B1
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Table 12.ꢀDEBUG SIGNALS ...continued
Signal
REGISTER
SIGNAL BITS
NAME
Description
rx_cl_error
4
3
2
1
0
7
6
5
4
3
2
1
0
tx_envelope
rx_enevelope
svalid
sdata
clif_transceive
rx_start_receive
rx_over_ok
rx_over_term
rx_resume
sgp_msg_busy
fig_reset_sigpro
fig_reset_rxdec
cfg_sw_reset_
sigpro
Table 13.ꢀTRIGGER SIGNALS
TRIGGER
TX Active
RX Enable
REGISTER
SIGNAL
NAME
BITS
Description
obs_clif_txenc1
tx_active_o
1
high level indicates transmission of data Remark: Falling
edge can be used to trigger on end of transmission.
obs_clif_sigpro_
rm15
rx_enable_o 1
rm_scoll_o
high level indicates that the reception is ongoing Remark:
can be used to trigger on the start /end of reception
RX collision
detected
obs_clif_sigpro_
rm14
1
high-level pulse indicates that the collision is detected during
reception
9.20 Secure firmware update
The PN5190B1 supports a secure update of the implemented firmware.
The secure firmware download mode is using dedicated commands, but does not require
a dedicated physical handling of the SPI interface lines.
The secure firmware download mode is entered by setting a register in non-volatile
memory followed by a trigger of the VEN pin.
The firmware binary file which is used to update the PN5190B1 is protected with an RSA
signature and AES encryption.
The key length of the RSA is 2048 bits, the public exponent supports any 32-bit integer
value.
A pre-computed Montgomery format of signature is used, and the signature hash
computation is based on SHA256 algorithm.
This prevents a download of any other software which is not released by NXP.
PN5190B1
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An anti-tearing function is implemented in order to detect supply voltage removal or
memory fault.
During the secure firmware download, the NFC operation is not available, only the
command set defined for the secure firmware download is valid.
Updating the PN5190B1 with the default firmware binaries programs the memories
for user configuration with default values. Any previous user configuration will be
overwritten. The user has to take care to restore the data of these memories after a
secure firmware update.
If this is not intended, special firmware versions are available which do not
overwrite the configuration. If the standard firmware file is named e.g. FW 2.00 , the
name of the firmware which does not overwrite existing settings is then FW 2.F0.
(The "F" is indicating the non overwrite version)
The PN5190B1 checks if the new major version number is equal or higher than the
current one. In case the major version number of the new firmware to be installed is
smaller than the already installed version number of the firmware, the secure firmware
update is rejected. Downgrading major firmware versions is therefore not possible.
Upgrading and therefore increasing major firmware versions is always possible.
In case of any failure or exception during the download (e.g. caused by a communication
error or power-off), the PN5190B1 remains in the secure firmware download mode until a
full firmware update sequence has been performed successfully.
Features of the automatic secure firmware update:
• Works without download request pin
• No special implementation of SPI interface handling
• Maximum integrity: Only encrypted and signed firmware images download possible
• Updating the firmware overwrites existing all previous EEPROM configurations.
9.21 SPI host interface
The interface of the PN5190B1 to a host microcontroller is based on a SPI interface.
The maximum SPI speed is 15 Mbit/s and fixed to CPOL = 0 and CPHA = 0. Only a half-
duplex data transfer is supported. There is no chaining allowed, meaning that the whole
instruction has to be sent or the whole receive buffer has to be read out. The whole
transmit buffer shall be written at once as well. No NSS assertion is allowed during data
transfer.
The SPI host interface is designed to support the typical interface supply voltages of 1.8
V and 3.3 V of CPUs. A dedicated supply input which defines the host interface supply
voltage independent from other supplies is available (pin VDDIO).
There is no external pull-up / pull-down resistor required, the SPI pads are automatically
configured by the PN5190B1.
Only a voltage of 1.8 V or 3.3 V is supported, but no voltage in the range of 1.95 V to 2.4
V.
Note: The Voltage on pin VDDIO must always be smaller or equal to the Voltage on pin
VBAT.
Master in slave out (MISO)
PN5190B1
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The MISO line is configured as an output in a slave device. It is used to transfer data
from the slave to the master, with the most significant bit sent first. The MISO signal is
put into 3-state mode when NSS is high.
Master out slave in (MOSI)
The MOSI line is configured as an input in a slave device. It is used to transfer data from
the master to a slave, with the most significant bit sent first.
Serial clock (SCK)
The serial clock is used to synchronize data movement both in and out of the device
through its MOSI and MISO lines.
Not slave select (NSS)
The slave select input (NSS) line is used to select a slave device. It shall be set to low
before any data transaction starts and must stay low during the transaction.
9.22 Host interface commands
9.22.1 Logical command layer
PN5190B1 has two main modes of operation to communicate with the host controller:
1. TLV-Command response-based communication
2. HDLL-Based communication, used when device is triggered to enter the “download
mode”, to update its firmware.
The description of the transport layer in the next chapters is limited to TLV-based
command-response communication.
For more information see [3].
9.22.1.1 Logical frame definition
A SPI frame starts with the falling edge of NSS and ends with the rising edge of NSS.
SPI is per physical definition full duplex but PN5190B1 uses SPI in a half-duplex mode.
SPI mode is limited to CPOL 0 and CPHA 0 with a max clock speed of 15 MHz.
Every SPI frame is composed of a 1-byte header and n-bytes of body.
9.22.1.2 Logical flow definition
The HOST always sends as a first byte the flow indication byte whether it wants to write
or read data from the PN5190B1.
In case of a read request and no data is available, the response contains 0xFF.
The data after the flow indication byte is one or several messages.
For every NSS assertion, the first byte is always a HEADER (flow indication byte), it can
be either 0x7F/0xFF with respect to write/read operation.
9.22.1.3 Logical message type definition
A host controller communicates with PN5190B1 using messages which are transported
within SPI frames.
PN5190B1
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There are three different message types:
• Command
• Response
• Event
Commands are only sent from host controller to PN5190B1 responses.
Events are only sent from PN5190B1 to host controller.
Allowed sequences and rules:
• Command is always acknowledged by a response
• Host Controller is not allowed to send another command before receiving a response to
a previous command, except in concatenation
• Events may be sent asynchronously at any time (NOT interleaved within a command/
response pair)
• EVENT messages are never combined with the RESPONSE messages within one
frame.
9.22.1.4 Logical message format
Type (T) => 1 byte
Bit[7] Message Type
0: COMMAND or RESPONSE message
1: EVENT message
Bit[6:0]: Instruction Code
Length (L) => 2 bytes (large endian format)
Length of the message body
Value (V) => N bytes
Value/data of the TLV (Command Parameters / Response data) based on Length field
(Large endian format)
9.22.1.5 Split frame definition
COMMAND message must be sent in one SPI frame RESPONSE and EVENT
messages can be read in multiple SPI frames, e.g., to read out the length byte.
RESPONSE and EVENT messages can be read in single SPI frame but delayed by NO-
CLOCK in between, e.g., to read out the length byte.
9.22.2 Host interface command list
PN5190B1 command/response list
Table 14.ꢀHost interface commands
Command code PN5180 legacy
command
Command
0x00
Yes
WRITE_REGISTER
PN5190B1
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Table 14.ꢀHost interface commands...continued
Command code PN5180 legacy
command
Command
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
WRITE_REGISTER_OR_MASK
WRITE_REGISTER_AND_MASK
WRITE_REGISTER_MULTIPLE
READ_REGISTER
READ_REGISTER_MULTIPLE
WRITE_EEPROM
READ_EEPROM
TRANSMIT_RF_DATA
RETRIEVE_RF_DATA
EXCHANGE_RF_DATA
MFC_AUTHENTICATE
EPC_GEN2_INVENTORY
LOAD_RF_CONFIGURATION
UPDATE_RF_CONFIGURATION
GET_ RF_CONFIGURATION
RF_ON
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RF_OFF
CONFIGURE_ TESTBUS_DIGITAL (not available for
engineering samples)
0x13
Yes
CONFIGURE_TESTBUS_ANALOG (not available for
engineering samples)
0x14
No
No
No
-
CTS_ENABLE
0x15
CTS_CONFIGURE
CTS_RETRIEVE_LOG
RFU
0x16
0x17 - 0x19
0x1A
RECEIVE_RF_DATA
RFU
0x1B-0x1F
0x20
Yes
Yes
Yes
No
No
No
No
No
-
SWITCH_MODE_NORMAL
SWITCH_MODE_AUTOCOLL
SWITCH_MODE_STANDBY
SWITCH_MODE_LPCD
SWITCH_MODE_SUSPEND
SWITCH_MODE_DOWNLOAD
GET_DIE_ID
0x21
0x22
0x23
0x24
0x25
0x26
0x27
GET_VERSION
0x28 - 0x3F
RFU
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Table 14.ꢀHost interface commands...continued
Command code PN5180 legacy
command
Command
0x40
-
RFU
0x41
No
-
PRBS_TEST
RFU
0x41 - 0x50
9.22.3 Command WRITE_REGISTER (00h)
Description
This instruction is used to write a 32-bit value (little endian) to a logical register.
Conditions
The address of the register must exist and the register must either have the READ-
WRITE or WRITE-ONLY attribute.
Event
There are no events for this command.
Command
Table 15.ꢀWRITE_REGISTER
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
4
1
0x00
Register address
Register content
Response
Status
0x00: STATUS_SUCCESS
0x018: STATUS_INSTR_ERROR
9.22.4 Command WRITE_REGISTER_OR_MASK (01h)
Description
This instruction is used to modify the content of register using a logical OR operation.
The content of the register is read and a logical OR operation is performed with the
provided mask. The modified content is written back to the register.
Conditions
The address of the register must exist and the register must either have the READ-
WRITE or WRITE-ONLY attribute.
Event
There are no events for this command.
Command
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Table 16.ꢀWRITE_REGISTER_OR_MASK
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
4
0x01
Register address
4 byte bitmask:
Bitmask used as operand for logical OR operation.
Response
1
Status
0x00: STATUS_SUCCESS
0x018: STATUS_INSTR_ERROR
9.22.5 Command WRITE_REGISTER_AND_MASK (02h)
Description
This instruction is used to modify the content of register using a logical AND operation.
The content of the register is read and a logical AND operation is performed with the
provided mask. The modified content is written back to the register.
Conditions
The address of the register must exist and the register must either have the READ-
WRITE or WRITE-ONLY attribute.
Event
There are no events for this command.
Command
Table 17.ꢀWRITE_REGISTER_AND_MASK
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
4
0x02
Register address
Bitmask
Bitmask used as operand for logical AND operation.
Response
1
Status
0x00: STATUS_SUCCESS
0x018: STATUS_INSTR_ERROR
9.22.6 Command WRITE_REGISTER_MULTIPLE (03h)
Description
This instruction behaves like WRITE_REGISTER, WRITE_REGISTER_OR_MASK and
WRITE_REGISTER_AND_MASK with the possibility to combine them. In fact, it takes
an array of register-type-value set and performs appropriate action. The type reflects
the action which is either write register, logical OR operation on a register or logical AND
operation on a register.
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Conditions
The respective logical address of the register within a set must exist. The register access
attribute must allow execution of required action (type):
• Write action: READ-WRITE or WRITE-ONLY attribute
• OR mask action: READ-WRITE attribute
• AND mask action: READ-WRITE attribute
The size of the parameter array must be in the range from 1 – 43, inclusive. Field ‘Type’
must be in the range of 1 – 3, inclusive.
In case of an exception, the operation is not rolled-back, i.e. registers which have been
modified until the exception occurs remain in modified state. Host has to take care to
recover a defined state.
Event
There are no events for this command.
Command
Table 18.ꢀWRITE_REGISTER_MULTIPLE
Payload
Length (byte)
Value/Description
Command
code
1
0x03
Parameter
6...258
Array of up to 43 {Register address element, Action element, Content element}
(6 x 1….6 x 43)
1 byte
1 byte
Register address element
Type
0x01: Write Register
0x02: Write Register OR Mask
0x03: Write Register AND Mask
4 bytes
Status:
Content element
32-bit register value which has to be written to register address, or 32-
bit bitmask used for logical operation with content available at register
address
Response
1
0x00: STATUS_SUCCESS
0x018: STATUS_INSTR_ERROR
9.22.7 Command READ_REGISTER (04h)
Description
This instruction is used to read a 32-bit value (little endian) to a register. The register
content is present in the response, as 4 byte value.
Conditions
The address of the register must exist.
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The register must either have the READ-WRITE or WRITE-ONLY attribute.
Event
There are no events for this command.
Command
Table 19.ꢀREAD_REGISTER
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x04
Register address
Address of the register to be read out
Response
1
4
Status
0x00: STATUS_SUCCESS
0x018: STATUS_INSTR_ERROR
Register content
32-bit register value which has been read out.
9.22.8 Command READ_REGISTER_MULTIPLE (05h)
Description
This instruction is used to read multiple logical registers at once. The result (content of
each register) is provided in the response to the instruction. The register address itself
is not included in the response. The order of the register contents within the response
corresponds to the order of the register addresses provided within the instruction.
Conditions
All register addresses within the instruction must exist. The access attribute for each
register must either be READ-WRITE or READ-ONLY. The size of ‘Register Address’
array must be in the range from 1 – 18, inclusive.
Event
There are no events for this command.
Command
Table 20.ꢀREAD_REGISTER_MULTIPLE
Payload
Length (byte) Value/Description
Command code
Parameter
1
0x05
1..18
Array of up to 18 elements {Register address element }
1
Register address element
Register address to be read out
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Table 20.ꢀREAD_REGISTER_MULTIPLE...continued
Payload
Length (byte) Value/Description
Response
1
Status
0x00: no error
0x01: error
4...72
Array of up to 18 {Register content element}
4..72
Register content element
Register content: n*4-Byte (32-bit) register data
9.22.9 Command WRITE_EEPROM (06h)
Description
The accessible area in EEPROM is 5119 bytes long and starts at EEPROM address 0.
This instruction is used to write one or more values to EEPROM. The field ‘Values’
contains the data to be written to EEPROM starting at the address given by field
‘EEPROM Address’. The data is written in sequential order.
This is a blocking command, the device is blocked during the write operation. This
will take approximately 2.85 ms, termination of the EEPROM write (programming) is
indicated by the response to the command.
Conditions
‘EEPROM Address’ field must be in the range from 0 – 5119, inclusive. Write operation
must not go beyond EEPROM address 5119. Error response will be sent to the host if
address exceeds 5119.
Event
There are no events for this command.
Command
Table 21.ꢀWRITE_EEPROM
Payload
length
(byte)
Value/Description
Command code
Parameter
1
2
0x06
EEPROM Address
Address in EEPROM from which write operation starts
{EEPROM Address}
1..5119
Array of up to 5119 {EEPROM content element}
EEPROM content
1..5119 Byte Values which have to be written to EEPROM in
sequential order
Response
-
Status
0x00: no error
0x01: ERROR due to wrong address
0x02: PROGRAMM ERROR
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9.22.10 Command READ_EEPROM (07h)
Description
This instruction is used to read back data from EEPROM memory area. The field
‘EEPROM Address’ indicates the start address of the read operation. The response
contains the data read from EEPROM.
Conditions
‘EEPROM Address’ field must be in the range from 0 – 5120, inclusive. Read operation
must not go beyond EEPROM address 5120. Error response shall be sent to the host if
the address exceeds 5120.
Event
There are no events for this command.
Command
Table 22.ꢀREAD_EEPROM
Payload
Length (byte) Value/Description
Command code
Parameter
1
2
0x07
Address in EEPROM from which read operation starts
(EEPROM Address)
2
1
Number of bytes to read from EEPROM
Response
0x00: no error
0x01: error
1...1024
Array of up to 1024 bytes {EEPROM content}
1
EEPROM content
9.22.11 Command TRANSMIT_RF_DATA (08h)
Description
This instruction is used to write data into the internal CLIF transmission buffer and start
transmission. The size of this buffer is limited to 1024 bytes. After this instruction has
been executed, an RF reception is started automatically.
The command returns immediately after Transmission is complete not waiting for the
reception completion.
Conditions
The number of bytes within the ‘TX Data’ field must be in the range from 1 – 1024,
inclusive.
The command must not be called during an ongoing RF transmission.
Event
There are no events for this command.
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Command
Table 23.ꢀTANSMIT_RF_DATA
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x08
Number of valid bits in last Byte:
0x00: All bits of last byte are transmitted
0x01....0x07: Number of bits within last byte to be transmitted
1-1024
1
TxData
Data which shall be used during next RF transmission
Response
Status
0x00 no error
0x01 error
0x02 RF Field is not switched on (if reader mode is active)
0x03 no RF Field present (if target mode is active)
9.22.12 Command RETRIEVE_RF_DATA (09h)
Description
This instruction is used to read data from the internal CLIF RX buffer, which
contains the RF response data (if any) posted to it from the previous execution of
EXCHANGE_RF_DATA with option not to include the received data in the response or
TRANSMIT_RF_DATA command.
Conditions
Event
There are no events for this command.
Command
Table 24.ꢀRETRIEVE_RF_DATA
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
0
1
0x09
Empty
Response
Status of the operation:
0x00: PN5190B1_STATUS_INSTR_SUCCESS
0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is
present)
1...1024
RX data which has been received during last successful RF
reception expected from executing the commands EXCHANGE_
RF_DATA or TRANSMIT_RF_DATA
9.22.13 Command EXCHANGE_RF_DATA (0Ah)
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Description
The RF exchange function performs a transmission of the TX data and is waiting for the
reception of any RX data.
The function returns in case of a reception (either erroneous or correct) or a timeout that
happened. The timer is started with the END of TRANSMISSION and stopped with the
START of RECEPTION. The timeout value pre-configured in EEPROM will be used.
If transceiver_state is
• IDLE: the Exchange Data mode is entered.
• WAIT_RECEIVE: the transceiver state is reset to Exchange Data Mode in case of
initiator bit is set
• WAIT_TRANSMIT: the transceiver state is reset to Exchange Data Mode in case
initiator bit is NOT set
The field ‘Number of valid bits in last Byte’ indicates the exact data length to be
transmitted. The command terminates after end of transmission and end of reception.
Conditions
Size of ‘TX Data’ field must be in the range from 0 – 1024, inclusive.
‘Number of valid bits in last Byte’ field must be in the range from 0 – 7.
The command must not be called during an ongoing RF transmission. Command shall
ensure the right state of the Transceiver for transmitting the data.
Event
There are no events for this command.
Command
Table 25.ꢀEXCHANGE_RF_DATA
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x0A
Number of valid bits in last Byte:
0: All bits of last byte are transmitted
1-7: Number of bits within last byte to be transmitted
1
RF Exchange Config
Configuration of the RFExchange function.
0 - 1024
TxData
Data which has to be sent out via CLIF using EXCHANGE_RF_
DATA command. Length = 0 – 1024 bytes
Response
1
4
Status
0x00 no error
0x01 Timeout
0x10 RF Field is not switched on (if reader mode is active)
0x18 error (in payload)
RX_STATUS
If RX_STATUS is requested in RF Exchange Config parameter
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Table 25.ꢀEXCHANGE_RF_DATA...continued
Payload
Length
(byte)
Value/Description
4
RF_STATUS
If RF_STATUS is requested in RF Exchange Config parameter
4
EVENT_STATUS
If EVENT_STATUS is requested in RF Exchange Config
parameter
1-1024
Rx_Data
RX data which has been received during last successful RF
reception.
Table 26.ꢀEXCHANGE_RF_DATA Parameter RF Exchange Config: Bitmask
Bitmask / Bit position
Description
B7 B6 B5 B4 B3 B2 B1 B0
X
X
X
X
RFU
X
Include RX Data in response based on RX_STATUS, if bit set to 1b.
Include EVENT_STATUS register in response, if bit set to 1b.
Include RF_STATUS register in response, if bit is set to 1b.
Include RX_STATUS register in response, if bit is set to 1b.
X
X
X
9.22.14 Command MFC_AUTHENTICATE (0Bh)
This command is used to perform a MIFARE Classic Authentication on an activated card.
It takes the key, card UID and the key type to authenticate at given block address. The
response contains one byte indicating the authentication status.
Conditions
Field ‘Key’ must be 6 bytes long. Field ‘Key Type’ must contain the value 0x60 or 0x61.
Block address may contain any address from 0x00 – 0xFF, inclusive. Field ‘UID’ must
be bytes long and should contain the 4 byte UID of the card. An ISO14443-3 MIFARE
Classic card should be put into state ACTIVE or ACTIVE* prior to execution of this
instruction.
In case of a runtime error related to the authentication, the field ‘Authentication Status’ is
set accordingly.
Event
There are no events for this command.
Command
Table 27.ꢀMFC_AUTHENTICATE
Payload
Length
(byte)
Value/Description
Command code
1
0x0B
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Table 27.ꢀMFC_AUTHENTICATE...continued
Payload
Length
(byte)
Value/Description
Parameter
6
Key
Authentication key to be used.
1
KeyType
0x60: Key Type A
0x61: Key Type B
1
Block Address
The address of the block for which the authentication has to be
performed.
4
1
UID
UID of the card.
Response
Status
0x00 no error (Authentication successful)
0x01 error (Authentication failed)
0x02 Timeout waiting for card response (card not present).
0x07 Authentication error: Indicates that MFC authentication
failed (permission denied)
9.22.15 Command EPC_GEN2_INVENTORY (0Ch)
This instruction is used to perform an inventory of ISO18000-3M3 tags. It implements
an autonomous execution of several commands according to ISO18000-3M3 in order to
guarantee the timings specified by that standard.
If present in payload of the instruction, first a "Select" command is executed followed by
a "BeginRound" command. If there is a valid response in the first timeslot (no timeout, no
collision), the instructions sends an ACK (acknowledge) and saves the received PC/XPC/
UII.
The instruction then performs an action according to the field ‘Timeslot Processed
Behavior’:
• if this field is set to 0 a NextSlot command is issued to handle the next timeslot. This is
repeated until the internal buffer is full
• If this field is set to 1 the algorithm pauses
• If this field is set to 2 a Req_Rn command is issued if, and only if, there has been a
valid tag response in this timeslot command.
Conditions
The field ‘Select Command Length’ must contain the length of the field ‘Select
Command’, which must be in the range from 1 – 39, inclusive. If ‘Select Command
Length’ is 0, the fields ‘Valid Bits in last Byte’ and ‘Select Command’ must not be present.
The field Bits in last Byte should contain the number of bits to be transmitted in the last
byte of the ‘Select Command’ field. The value must be in the range from 1 – 7, inclusive.
If the value is 0, all bits from last byte from ‘Select Command’ field are transmitted. The
field ‘Select Command’ should contain a Select command according to ISO18000-3M3
without trailing CRC-16c and must have the same length as indicated in field ‘Select
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Command Length’. Field ‘BeginRound Command’ should contain a BeginRound
command according to ISO18000-3M3 without trailing CRC-5. The last 7 bits of the last
byte of ‘BeginRound Command’ are ignored as the command has an actual length of 17
bits. ‘Timeslot Processed Behavior’ must contain a value from 0 – 2, inclusive.
Event
There are no events defined for this command.
Command
Table 28.ꢀEPC_GEN2_INVENTORY
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x0C
Resume Inventory:
00: Initial GEN2_INVENTORY
01: Resume the GEN2_INVENTORY command – the remaining
fields below are empty (any payload is ignored)
1
1
Select Command Length
0x00 No Select command is set prior to BeginRound command.
‘Valid Bits in last Byte’ field and ‘Select command’ field shall not
be present.
0x01...0x27: Length (1d...39d) of the ‘Select command’ field.
Valid Bits in last Byte
0: All bits of last byte of ‘Select command’ field are transmitted.
1-7: Number of bits to be transmitted in the last byte of ‘Select
command’ field.
0...39
3
If present, this field contains the Select command (according
to ISO18000-3, Table 47) which is sent prior to BeginRound
command. CRC-16c will not be included.
BeginRound Command
This field contains the BeginRound command (according to
ISO18000-3, Table 49). CRC-5 will not be included
1
Timeslot Processed Behavior
0x00: Response shall contain max. Number of timeslots which
may fit in response buffer.
0x01: Response shall contain only one timeslot.
0x02: Response shall contain only one timeslot. If timeslot
contains valid card response, also the card handle is included.
Response
1
Status
0x00 no error
0x01 syntax error (no further bytes)
3-69
Timeslot array {Timeslot status element, Tag reply length
element, Valid bits in last byte element}
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Table 28.ꢀEPC_GEN2_INVENTORY...continued
Payload
Length
(byte)
Value/Description
1
Timeslot status element
0x00: Tag response available. ‘Tag Reply Length’ field,
‘Valid bits in last byte’ field, and ‘Tag reply’ field present.
0x01: Tag response available.
0x02: No tag replied in timeslot. ‘Tag Reply Length’ field
and ‘Valid bits in last byte’ field, shall be set to zero. ‘Tag
reply’ field shall not be present.
0x03: Two or more tags responded in the timeslot.
(Collision). ‘Tag Reply Length’ field and ‘Valid bits in last
byte’ field, shall be set to zero. ‘Tag reply’ field shall not
be present.
1
1
Tag Reply Length element
0x00...0x42: Length of ‘Tag Reply’ field [0d...66d]. If Tag
Reply Length is 0x00, then the Tag Reply field is not
present.
Valid bits in last byte element
0: All bits of last byte of ‘Tag reply’ field are valid.
1: Number of valid bits of last byte of ‘Tag reply’ field. If
Tag Reply Length is zero, the value of this byte shall be
ignored.
n
Tag Reply
n-bytes reply of the tag according to ISO18000-3_2010, Table
56.
0 or 2
Tag Handle
2 byte handle of the tag, in case field ‘Timeslot Status’ is set to
‘1’. Otherwise field not present
9.22.16 Command LOAD_RF_CONFIGURATION (0Dh)
Description
This instruction is used to load the RF configuration from E2PROM into registers. It is
possible to configure RF technology, mode (target/initiator) and baud rate. Configurations
can be loaded separately for the receiver (RX configuration) and transmitter (TX
configuration). The value 0xFF has to be used if the existing configuration for either TX or
RX shall not be updated.
Conditions
Field ‘TX Configuration’ must be in the range from 0x0 – 0x2B, inclusive. If the value is
0xFF, TX configuration is not changed.
Field ‘RX Configuration’ must be in the range from 0x80 – 0xAB, inclusive. If the value is
0xFF, RX configuration is not changed.
A special configuration with TX Configuration = 0xFF and RX Configuration = 0xAC is
used load the Boot-up registers one time. This special configuration is required to update
the register configurations (both TX and RX) that are different from the IC reset values.
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Event
There are no events for this command.
Command
Table 29.ꢀLOAD_RF_CONFIGURATION
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x0D
TX Configuration (Transmitter)
0xFF: actual TX configuration not changed.
others: Corresponding TX configuration loaded.
1
1
RX Configuration (Receiver)
0xFF: actual RX configuration not changed.
others: Corresponding RX configuration loaded.
Response
Status of the operation:
0x00 STATUS_SUCCESS
0x08 STATUS_MEMORY_ERROR
0x18 STATUS_INSTR_ERROR
9.22.16.1 Parameter for command LOAD_RF_CONFIGURATION
Table 30.ꢀTX Parameter for command LOAD_RF_CONFIGURATION
TX
Setting
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
Protocol
ISO14443A
ISO14443A
ISO14443A
ISO14443A
ISO14443B
ISO14443B
ISO14443B
ISO14443B
FeliCa
alternate
Speed
Modulation
Miller
Miller
Miller
Miller
NRZ
PCD
NFC-PI-106, NFC-AI-106 106
-
-
-
-
-
-
-
212
424
848
106
212
424
848
NRZ
NRZ
NRZ
NFC-PI-212, NFC-AI-212 212
NFC-PI-424, NFC-AI-424 424
FeliCa
ISO15693_ASK100
ISO15693_ASK10
-
-
-
-
-
-
-
26
26
-
1out4/ASK100
1out4/ASK10
-
-
-
-
-
-
-
ISO180003m3
TARI=18_
88us
ASK
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Table 30.ꢀTX Parameter for command LOAD_RF_CONFIGURATION...continued
TX
Setting
Protocol
alternate
Speed
Modulation
0x10
ISO180003m3
-
TARI=9_
44us
ASK
0x11
-
-
-
-
0x12
-
-
-
-
PICC
0x13
ISO14443A-PICC
ISO14443A-PICC
ISO14443A-PICC
ISO14443A-PICC
NFC-PT-212
NFC-PT-424
NFC-AT-106
NFC-AT-212
NFC-AT-424
GTM
NFC-PT-106
106
212
424
848
212
424
106
212
424
All
Manch SubC
0x14
-
-
-
-
-
-
-
-
-
BPSK
0x15
BPSK
0x16
BPSK
0x17
-
0x18
-
0x19
-
0x1a
-
0x1B
0x1C
0x1D
0x1E..0xFE
0xFF
-
All
-
Idle_RF_Config
-
All
-
-
-
-
No change
-
-
Table 31.ꢀRX Parameter for command LOAD_RF_CONFIGURATION
RX
Setting
0x80
Protocol
alternate
Speed
Modulation
PCD
ISO14443A
NFC-PI-106, NFC- 106
AI-106
Manch SubC
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
ISO14443A
ISO14443A
ISO14443A
ISO14443B
ISO14443B
ISO14443B
ISO14443B
FeliCa
-
-
-
-
-
-
-
212
424
848
106
212
424
848
BPSK
BPSK
BPSK
BPSK
BPSK
BPSK
BPSK
NFC-PI-212, NFC- 212
AI-212
0x89
FeliCa
NFC-PI-424, NFC- 424
AI-424
0x8a
0x8b
ISO15693
ISO15693
-
-
6P6
26
Manch424
Manch424
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Table 31.ꢀRX Parameter for command LOAD_RF_CONFIGURATION...continued
RX
0x8c
0x8d
0x8e
0x8f
ISO15693
ISO15693
ISO15693
-
-
-
-
53
Manch424
106
212
106
-
-
ISO180003m3_
Manch424_4
Manch424/4 period
0x90
0x91
0x92
ISO180003m3_
Manch424_2
-
-
-
212
212
424
Manch424/2 period
Manch848/4 period
Manch848/2 period
ISO180003m3_
Manch848_4
ISO180003m3_
Manch848_2
PICC
0x93
ISO14443A-PICC NFC-PT-106
106
212
424
848
212
424
106
212
424
All
Miller
0x94
ISO14443A-PICC
ISO14443A-PICC
ISO14443A-PICC
NFC-PT-212
NFC-PT-424
NFC-AT-106
NFC-AT-212
NFC-AT-424
GTM
-
-
-
-
-
-
-
-
-
-
-
-
-
Miller
0x95
Miller
0x96
Miller
0x97
-
0x98
-
0x99
-
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F-0xFE
0xFF
-
-
All
-
Idle_RF_Config
Boot
All
All
-
-
-
-
no change
-
-
9.22.17 Command UPDATE_RF_CONFIGURATION (0Eh)
Description
This instruction is used to update the RF configuration within the EEPROM. The
instruction allows updating at register granularity value, i.e. not the complete register set
needs to be updated.
Conditions
The size of the field array must be in the range from 1 – n, inclusive. The field array
‘Configuration’ must contain a set of elements for ‘RF Configuration’, ‘Register Address’
and ‘Value’. The field ‘RF configuration’ must be in the range from 0x00 – 0x2B for the
TX configuration and 0x80 – 0xAB for the RX configuration, inclusive. The address within
field ‘Register Address’ must exist within the respective RF configuration. Field ‘Value’
should contain a value which has to be written into the given register and must be 4 bytes
long.
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Event
There are no events for this command.
Command
Table 32.ꢀUPDATE_RF_CONFIGURATION
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
n
0x0E
Array of n { RF configuration element, Register address element,
Value element }
1
RF configuration element
RF Configuration for which the register has to be
changed.
1
4
Register address element
Register Address within the given RF technology.
Value element
Value which has to be written into the register
Response
1
Status of the operation:
0x00 STATUS_SUCCESS
0x08 STATUS_MEMORY_ERROR
0x18 STATUS_INSTR_ERROR
9.22.18 Command GET_ RF_CONFIGURATION (0Fh)
Description
This instruction is used to read out an RF configuration. The register address-value-pairs
are available in the response. In order to know how many pairs are to be expected, first
size information can be retrieved from the first TLV, which indicates the total length of the
payload.
Conditions
The field ‘RF configuration’ must be in the range from 0x0 – 0x2B for TX Configuration
and 0x80 – 0xAB for the RX configuration, inclusive.
Event
There are no events for this command.
Command
Table 33.ꢀGET_RF_CONFIGURATION
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x1F
RF Configuration
RF Configuration for which the set of register value pairs have to
be retrieved.
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Table 33.ꢀGET_RF_CONFIGURATION...continued
Payload
Length
(byte)
Value/Description
Response
1
Status of the operation:
0x00 STATUS_SUCCESS
0x18 STATUS_INSTR_ERROR
n * 5
Array of n { Register address element, Register value element };
n defined by first TLV
1
Register Address element
Register Address within the given RF technology
4
Register value element
32-Bit register data content.
9.22.19 Command RF_ON (10h)
Description
This instruction is used to activate the transmitter output.
The RF_ON command shall be always sent with a guard time of at least 5.1 ms after a
previous RF_OFF command.
Conditions
The transmitter needs to be supplied to allow the emission of an RF field.
Event
There are no events for this command.
Command
Table 34.ꢀRF_ON
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x10
RF On
Bit 0 = 0: Use collision avoidance by RF Level detector
Bit 0 = 1: Disable collision avoidance by RF level detector
Bit 1 = 0 No P2P active
Bit 1 = 1 P2P active
Response
1
Status
0x00 no error (RF field switched on)
0x01 error (wrong payload of command)
0x02 RF Field not switched on due to detected RF collision.
9.22.20 Command RF_OFF (11h)
Description
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This instruction is used to de-activate the transmitter output.
Conditions
No conditions are required to execute this command.
Event
There are no events for this command.
Command
Table 35.ꢀRF_OFF
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
0
1
0x11
No payload
Response
Status
0x00 no error (RF field switched off)
0x01 error (wrong payload of command)
9.22.21 Command CONFIGURE_ TESTBUS_DIGITAL (12h)
Description
This instruction is used to route digital test bus signals to the available test buses TB0
(Testbus_0) and TB1 (Testbus_1).
Conditions
No conditions are required to execute this command.
Event
There are no events for this command.
Command
Table 36.ꢀRF_OFF
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
1
1
1
0x12
TB_SignalIndex
TB_BitIndex
TB_PadIndex
Response
Status
0x00 no error
0x018 Instruction error
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9.22.22 Command CONFIGURE_TESTBUS_ANALOG (13h)
Description
This instruction is used activate analog debug signals to the available test signal out pads
AUX1, AUX2.
Conditions
No conditions are required to execute this command.
If used, ADC-Q needs to be routed always to AUX1, ADC-I needs to be routed
always to AUX2
Event
There are no events for this command.
Command
Table 37.ꢀRF_OFF
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
1
0x12
Config: Configurable bits
Combined_Mode Signal:
0 – ADCI/ADCQ
1 – pcrm_if_rssi
2-0xFF – Reserved
1
1
1
TB_SignalIndex0
Signal index of the analog signal
TB_SignalIndex1
Signal index of the analog signal
Shift_Index0
DAC0 input shift positions. Direction will be decided by bit_0 in
Config
1
Shift_Index1
DAC1 input shift positions. Direction will be decided by bit_1 in
bConfig.
1
1
1
Mask0: DAC0 mask
Mask1: DAC1 mask
Response
Status
0x00 no error
0x018 Instruction error
9.22.23 Command CTS_ENABLE (14h)
Description
This instruction is used to enable/disable the CTS feature.
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Conditions
-
Event
In case a trigger condition is fulfilled, an event will be raised:
Payload
Length
(byte)
Value/Description
EVENT
1
00 … TRIGGER has occurred, data is ready for reception.
Command
Table 38.ꢀCTS_ENABLE
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x14
Enable
0x00: Disable the CTS Logging Feature
0x01: Enable the CTS Logging Feature
0x02-0xFF: RFU
Response
1
0x00 no error
0x01 error
9.22.24 Command CTS_CONFIGURE (15h)
Description
This instruction is used to configure the all the required CTS registers such as triggers,
test bus registers, sampling configuration etc.
The captured data to be sent as part of the response to CTS_RETRIEVE_LOG
command.
Event
There is no event for this instruction.
Command
Table 39.ꢀCTS_CONFIGURE
Payload
Length
(byte)
Value/Description
Command code
1
0x15
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Table 39.ꢀCTS_CONFIGURE ...continued
Payload
Length
(byte)
Value/Description
Parameter
1
PRE_TRIGGER_SHIFT
Defines the length of the after-trigger acquisition sequence in
256-bytes units.
0 means no shift;
n means n*256 bytes block shift.
Note: Valid only if TRIGGER_MODE is “PRE” or “COMB” trigger
mode
1
TRIGGER_MODE
Specifies Acquisition mode to be used.
0x00 - POST mode
0x01 - RFU
0x02 - PRE Mode
0x03 - 0xFF - Invalid
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Table 39.ꢀCTS_CONFIGURE ...continued
Payload
Length
(byte)
Value/Description
1
RAM_PAGE_WIDTH
Specifies the amount of on-chip memory that is covered by an
acquisition. Granularity is chosen by design as 256 Bytes (i.e. 64
32-bits words).
Valid values are as below:
0x00h - 256 bytes
0x01h - 512 bytes
0x02h - 768 bytes
0x03h - 1024 bytes
0x04h - 1280 bytes
0x05h - 1536 bytes
0x06h - 1792 bytes
0x07h - 2048 bytes
0x08h - 2304 bytes
0x09h - 2560 bytes
0x0Ah - 2816 bytes
0x0Bh - 3072 bytes
0x0Ch - 3328 bytes
0x0Dh - 3584 bytes
0x0Eh - 3840 bytes
0x0Fh - 4096 bytes
0x10h - 4352 bytes
0x11h - 4608 bytes
0x12h - 4864 bytes
0x13h - 5120 bytes
0x14h - 5376 bytes
0x15h - 5632 bytes
0x16h - 5888 bytes
0x17h - 6144 bytes
0x18h - 6400 bytes
0x19h - 6656 bytes
0x1Ah - 6912 bytes
0x1Bh - 7168 bytes
0x1Ch - 7424 bytes
0x1Dh - 7680 bytes
0x1Eh - 7936 bytes
0x1Fh - 8192 bytes
Note: if values provided is more than 0x1F, the value will be
masked with 0x1F and resultant value will be considered.
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Table 39.ꢀCTS_CONFIGURE ...continued
Payload
Length
(byte)
Value/Description
1
SAMPLE_CLK_DIV
The decimal value of this field specifies the clock rate division
factor to be used during acquisition. CTS clock = 13.56 MHz /
2SAMPLE_CLK_DIV
00 - 13560 kHz
01 - 6780 kHz
02 - 3390 kHz
03 - 1695 kHz
04 - 847.5 kHz
05 - 423.75 kHz
06 - 211.875 kHz
07 - 105.9375 kHz
08 - 52.96875 kHz
09 - 26.484375 kHz
10 - 13.2421875 kHz
11 - 6.62109375 kHz
12 - 3.310546875 kHz
13 - 1.6552734375 kHz
14 - 0.82763671875 kHz
15 - 0.413818359375 kHz
1
SAMPLE_BYTE_SEL
These bits are used to specify which bytes of the two 16-
bits input buses contribute to the interleave mechanism that
generates data to be transferred to the on-chip memory. The
meaning and usage of them is depending from the SAMPLE_
MODE_SEL values.
Note: Given value is always masked with 0x0F and then effective
value is considered.
1
SAMPLE_MODE_SEL
Selects the sampling interleave mode as described by the CTS
design specs. Decimal value 3 is reserved and will be treated
as 0. Note: Given value is always masked with 0x03, and then
effective value is considered.
1
1
1
1
TB0
Selects which test bus to be connected to TB0. Refer to list
below (TB_Signal_Index value)
TB1
Selects which test bus to be connected to TB1. Refer to list
below (TB_Signal_Index value)
TB2
Selects which test bus to be connected to TB2. Refer to list
below (TB_Signal_Index value)
TB3
Selects which test bus to be connected to TB3. Refer to list
below (TB_Signal_Index value)
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Table 39.ꢀCTS_CONFIGURE ...continued
Payload
Length
(byte)
Value/Description
1
TTB_SELECT
Selects which TB to be connected to the trigger sources. Refer to
list below (TB_Signal_Index value)
4
RFU
Send always 0x00000000
24
MISC_CONFIG
Trigger occurrences, polarity etc. Refer to (5) below for
understanding of CTS configuration to use.
Response
1
0x00 no error
0x01 error
9.22.25 Command CTS_RETRIEVE_LOG (16h)
Description
This instruction retrieves the data log of the captured test bus data samples stored in the
memory buffer.
CTS_RETREIVE_LOG is valid only if CTS_EVENT bit is set in the EVENT_STATUS
register.
Event
There are no events for this command.
Command
Table 40.ꢀCTS_RETRIEVE_LOG
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x16
ChunkSize
0x01-0xFF Contains the number of bytes of data expected.
Response
1
Status of the operation
Expected values:
- STATUS_SUCCESS
- STATUS_INSTR_ERROR (No further data is present)
- STATUS_SUCCSES_CHAINING
1..n
CTSRequest
Captured Samples Data chunk. Maximum size is depended upon
the ‘ChunkSize’ that has been provided as part of the command.
Total ChunkSize shall be available in the TLV header response.
9.22.26 Command RECEIVE_RF_DATA (1Ah)
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Description
This instruction waits for the command/data from the reader to be received. The
instruction returns in case of a reception (either erroneous or correct) and is blocking or a
timeout occurred. The timer is started with the END of TRANSMISSION and stopped with
the START of RECEPTION. The default timeout value preconfigured in EEPROM shall
be used.
Conditions
This instruction is valid only in “Card” mode or “Target” mode.
Error conditions for the reception are available in the register RX_STATUS_REG.
Event
There are no events for this command.
Command
Table 41.ꢀRECEIVE_RF_DATA
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x1A
7..4: RFU
3: Include RX Data in response based on RX_STATUS, if bit set
2: Include EVENT_STATUS register in response, if bit set
1: Include RF_STATUS register in response, if bit is set
0: Include RX_STATUS register in response, if bit is set
Response
1
Status of the operation:
0x00: PN5190B1_STATUS_INSTR_SUCCESS
0x01: PN5190B1_STATUS_TIMEOUT
0x0A: PN5190B1_STATUS_NO_RF_FIELD
0x10: PN5190B1_STATUS_NO_EXTERNAL_RF_FIELD
0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is
present)
4
If RX_STATUS is requested (little endian)
If RF_STATUS is requested (little endian)
If EVENT_STATUS is requested (little endian)
4
4
1-1024
RX data which has been received during last successful RF
reception.
9.22.27 Command SWITCH_MODE_NORMAL (20h)
Description
The Switch Mode Normal command is used to terminate one of the modes Standby,
LPCD (not ULPCD) or Autocoll. The response indicates that the normal mode is entered.
Conditions
-
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Event
Table 42.ꢀEVT_SWITCH_MODE_NORMAL
Payload
Length
(byte)
Value/Description
Event
1
Indicates that the normal mode is entered and PN5190B1 is able
to receive new commands.
Command
Table 43.ꢀSWITCH_MODE_NORMAL
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
0
0
0x20
- (no payload)
Response
- (No data in response. Instead the EVT_SWITCH_MODE_
NORMAL is used to indicate the successful operation mode-
switch)
9.22.28 Command SWITCH_MODE_AUTOCOLL (21h)
Description
The Switch Mode Autocoll automatically performs the card activation procedure in target
mode.
Conditions
In case field ‘Mode’ is set to 2 (Autocoll): Field ‘RF Technologies’ (Table 21) must contain
a bitmask indicating the RF Technologies to support during Autocoll, according to Table
22.
Field ‘Autocoll Mode’ must be in the range from 0 – 2, inclusive.
No instructions must be sent while being in this mode.
Termination of the command is indicated by an interrupt.
Event
The event notification is sent when the command has terminated and the normal mode
is entered. Host shall read-out the response bytes based on the event value. Technology
information is retrieved from the registers using the command READ_REGISTER or
READ_REGISTER_MULTIPLE.
Command
Table 44.ꢀEVT_SWITCH_MODE_AUTOCOLL
Payload
Length
(byte)
Value/Description
Event
1
0X00 … PN5190B1 has been activated as a card
0X01 … No RF field or RF field has vanished
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Table 44.ꢀEVT_SWITCH_MODE_AUTOCOLL...continued
Payload
Length
(byte)
Value/Description
Autocoll_resp
0...n
0 … if previous field is 01
1..n bytes ATR_RES / ATS_RES as per ISO18092 / ISO1443-4
Table 45.ꢀSWITCH_MODE_AUTOCOLL
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x21
RF Technologies: Bitmask indicating the RF technology to listen
for during Autocoll.
1
Autocoll Mode
0x00: Autonomous mode not used
i.e. Autocoll terminates when external RF field is not present.
Termination in case of
• NO RF FIELD or RF FIELD has disappeared
• PN5190B1 is ACTIVATED in TARGET mode
0x01Autonomous mode used.
When no RF field is present, Autocoll automatically enters
standby mode. Once RF external RF field is detected, PN5190B
1 enters again Autocoll mode.
Termination in case of
• PN5190B1 is ACTIVATED in TARGET mode
0x02 Autonomous mode without standby used.
When no RF field is present, PN5190B1 waits until RF field is
present before actually starting Autocoll algorithm. Standby is not
used in this case.
Termination in case of
• PN5190B1 is ACTIVATED in TARGET mode
Response
1
Status
0x00 no error
0x01 error (Switch mode has not been entered – due to wrong
settings or due to standby prevention)
Table 46.ꢀRF Technologies parameter: Bitmask
Bitmask / Bit position
Description
B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
RFU
X
listening for NFC-F Active is enabled
listening for NFC-A Active is enabled
listening for NFC-F is enabled
X
X
X
listening for NFC-A is enabled
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9.22.29 Command SWITCH_MODE_STANDBY (22h)
Description
The Switch Mode Standby automatically sets the IC into standby mode.
Conditions
-
Event
The event notification is sent when the command has finished and the normal mode is
entered.
Command
Table 47.ꢀEVT_SWITCH_MODE_STANDBY
Payload
Length
(byte)
Value/Description
Event
1
Indicates wake-up source
0x01 … WUC
0x02 … RF Level Detector
0x03 … NSS low transition (HOSTIF activity)
Table 48.ꢀSWITCH_MODE_STANDBY
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x22
Wake-up Control
Bitmask controlling the wake-up source to be used.
2
1
Counter Value
Used value for wake-up counter in msecs. Maximum supported
value is 2690
Response
Status
0x00 no error
0x01 error (Switch mode has not been entered – due to wrong
settings or due to standby prevention)
Table 49.ꢀSTANDBY control parameter: Bitmask
Bitmask / Bit position
Description
B7 B6 B5 B4 B3 B2 B1 B0
0
0
0
0
0
0
RFU
X
Wake-up on external RF field
Wake-up on wake-up counter expired
X
9.22.30 Command SWITCH_MODE_LPCD (23h)
PN5190B1
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Description
The Switch Mode LPCD performs a detuning detection on the antenna due to changing
environment around the antenna. There are 2 different modes of LPCD. The HW-
based solution offers a competitive power consumption with a reduced sensitivity. The
FW-based solution offers a higher sensitivity at the cost of a slightly increased power
consumption. The configuration of the LPCD is done in the EEPROM register settings
before the command is called.
Conditions
Before this command is issued, other configuration bits must be specified.
Event
The event notification is sent when the command has finished and the normal mode is
entered.
Command
Table 50.ꢀEVT_SWITCH_MODE_LPCD
Payload
Length
(byte)
Value/Description
Event
1
0x00: LPCD has detected a wake-up condition
Table 51.ꢀSWITCH_MODE_LPCD
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
1
0x 23
LPCD Type
0x00 Hardware-based ULPCD is used
0x01 Firmware-based LPCD is used
0x02-0xFF RFU
2
1
Counter Value
Used value for wake-up counter in msecs. Maximum supported
value is 4096 (12 Bit), the counter input clock is 1 kHz
Response
Status
0x00 no error
0x01 error (Switch mode has not been entered – due to wrong
settings)
9.22.31 Command SWITCH_MODE_DOWNLOAD (25h)
Description
The Switch Mode Download command enters the Firmware download mode.
Conditions
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The response signalizes that the command has been processed by the PN5190B1. After
the response is read by the host and no error is indicated in the response, the download
mode is entered.
Event
-
Command
Table 52.ꢀSWITCH_MODE_DOWNLOAD
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
0
0x25
- (SWITCH_MODE_DOWNLOAD command is called without any
parameter)
Response
1
Status
0x00 no error
0x01 error (Switch mode has not been entered)
9.22.32 Command GET_DIE_ID (26h)
Description
This instruction is used to read-out the Die ID of the PN5190B1 chip.
Conditions
No conditions are required to execute this command.
Event
There are no events for this command.
Command
Table 53.ꢀGET_DIE_ID
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
0
1
0x26
No payload
Response
Status of the operation:
0x00: PN5190B1_STATUS_INSTR_SUCCESS
0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is
present)
16
16 bytes DIE ID.
9.22.33 Command GET_VERSION (27h)
Description
PN5190B1
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This instruction is used to read-out the HW version, ROM version and the FW version of
the PN5190B1 chip.
Conditions
No conditions are required to execute this command.
Event
There are no events for this command.
Command
Table 54.ꢀGET_VERSION
Payload
Length
(byte)
Value/Description
Command code
Parameter
1
0
1
0x27
No payload
Response
Status of the operation:
0x00: PN5190B1_STATUS_INSTR_SUCCESS
0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is
present)
1
1
2
Hardware Version
ROM Code Version
Firmware version (used for secure firmware download)
Example:
Get Version with FW v2.0
[HOST] -> [0x00 0x04 0xE1 0x00 0x00 0x00 0x75 0x48]
[HOST] <- [0x00 0x08 STAT HW_V RO_V MODEL_ID FM1V FM2V RFU1 RFU2 CRC16]
o/p : 00 08 00 51 02 00 00 02 00 00 7F 10
HW_Version = x51, ROM_Version = x02, MODEL_ID = x00, FirmwareVersion = 02.00
9.22.34 Command PRBS_TEST (41h)
Description
This instruction is used to generate the PRBS sequence for the different configurations of
the reader mode protocols and bit-rates.
Conditions
This instruction is a blocking instruction and shall be terminated only with
SWITCH_MODE_NORMAL command.
Event
There are no events for this command.
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Command
Table 55.ꢀPRBS_TEST
Payload
Length
Value/Description
(byte)
Command code
Parameter
1
1
0x41
prbs_type
0x00: PRBS9 (default)
0x01: PRBS15
0x02-0xFF: RFU
1
1
prbs_techno
0x00: ISO14443-A
0x01: ISO1443-B
0x02: FeliCa
0x03: ISO15693
0x04-0xFF: RFU
prbs_baud
0x00: 106 kBit/s (default for type A,B,F)
0x01: 212 kBit/s
0x02: 424 kBit/s
0x03: 848 kBit/s
0x04: 26 kBit/s (default for ISO15693)
0x05-0xFF: RFU
2
1
prbs_length
2 bytes indicating the prbs length of 1 byte up to 510 bytes data
length of the transmission sequence
Response
Status of the operation:
0x00: PN5190B1_STATUS_INSTR_SUCCESS
0x0A: PN5190B1_STATUS_NO_RF_FIELD
0x18: PN5190B1_STATUS_INSTR_ERROR (No further data is
present)
9.22.35 RESPONSE STATUS CODES
Table 56.ꢀRESPONSE STATUS CODES LIST
RESPONSE STATUS
STATUS_SUCCESS
STATUS_TIMEOUT
VALUE
0x00
Value/Description
Indicates that operation completed successfully
Indicates that the operation of the command resulted in timeout
Indicates that the operation of the command resulted in RF data integrity error
0x01
STATUS_INTEGRITY_
ERROR
0x02
STATUS_RF_COLLISION_ 0x03
ERROR
Indicates that the operation of the command resulted in RF collision error
STATUS_RFU1
0x04
0x05
-
STATUS_INVALID_
COMMAND
Indicates that the given command is invalid/not implemented
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Table 56.ꢀRESPONSE STATUS CODES LIST...continued
RESPONSE STATUS
STATUS_RFU2
VALUE
0x06
Value/Description
-
STATUS_AUTH_ERROR
0x07
Indicates that MFC authentication failed (permission denied)
STATUS_MEMORY_
ERROR
0x08
Indicates that the operation of the command resulted in a programming error or
internal memory error
STATUS_RFU4
0x09
0x0A
-
STATUS_NO_RF_FIELD
Indicates that there are no or error in internal RF field presence (applicable only
if initiator/reader mode).
STATUS_RFU5
0x0B
0x0C
-
STATUS_SYNTAX_
ERROR
Indicates that invalid command frame length is received
STATUS_RESOURCE_
ERROR
0x0D
Indicates that an internal resource error occurred
STATUS_RFU6
STATUS_RFU7
0x0E
0x0F
0x10
-
-
STATUS_NO_
Indicates that no external RF field is present during the execution of the
command (Applicable only in card/target mode)
EXTERNAL_RF_FIELD
STATUS_RFU8
0x11
0x12
-
STATUS_USER_
CANCELLED
Indicates that the present command in-progress is aborted
STATUS_PREVENT_
STANDBY
0x13
Indicates that chip is prevented to go into standby mode
STATUS_RFU9
0x14
-
STATUS_CLOCK_ERROR 0x15
Indicates that clock to the CLIF did not start
STATUS_RFU10
0x16
0x17
-
STATUS_PRBS_ERROR
Indicates that the PRBS command returned an error
STATUS_INSTR_ERROR 0x18
Indicates that operation of the command is failed (it may include, the error in
instruction parameters, syntax error, error in operation itself, pre-requirements
for the instruction is not met etc.…)
STATUS_ACCESS_
DENIED
0x19
Indicates that access to internal memory is denied
STATUS_TX_FAILURE
STATUS_NO_ANTENNA
RFU
0x1A
Indicates that TX over RF is failed
Indicates that no antenna is connected/present
-
0x1B
0x1C-0x7E
0x7F
STATUS_INTERNAL_
ERROR
Indicates that the NVM operation failed
RFU
0x80-0xAE
0xAF
-
STATUS_SUCCSES_
CHAINING
Indicates that furthermore data is pending to be read
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9.22.36 EVENTS INDICATED BY INTERRUPT
Normal events are indicated over IRQ.
These normal events can be either
• always enabled - Host is always notified
• controlled by Host – Host is notified if the respective Event Enable bit is set in the
register (EVENT_ENABLE).
Low-level interrupts from the peripheral IPs including the CLIF are completely handled
within the firmware and host will be notified only of the events listed in the events section.
The Firmware implements two event registers as RAM registers that can be written /
Read using WRITE_REGISTER / READ_REGISTER commands.
Two registers do exist to handle the events from a host microcontroller: EVENT_ENABLE
and EVENT_STATUS:
• EVENT_ENABLE => register, enables/disables specific event notifications
• EVENT_STATUS => content of this register is part of the event message payload
Events are auto-cleared once the event message is read-out by the host.
Events are asynchronous in nature and are notified to the host if they are enabled within
event register.
Following is the list of events available to the host as part of event message:
Table 57.ꢀIRQ EVENT LIST
BIT
EVENT
Always
enabled
Value/Description
31..12
RFU
-
-
11
10
9
CTS_EVENT
N
Y
N
Y
Y
N
N
N
N
Y
Y
Y
IDLE_EVENT
LP_CALIBRATION_EVENT
LPCD_EVENT
8
7
AUTOCOLL_EVENT
TIMER0_EVENT
6
5
TX_OVERCURRENT_EVENT
RFON_DET_EVENT
RFOFF_DET_EVENT
STANDBY_PREV_EVENT
GENERAL_ERROR_EVENT
BOOT_EVENT
4
3
2
1
0
Note that no two events are clubbed except in case of errors. In case of errors during
the operation, functional event (e.g. BOOT_EVENT, AUTOCALL_EVENT etc.) and
GENERAL_ERROR_EVENT will be set.
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9.22.37 EVENTS INDICATED ON GPIO
Temperature events are possible to be indicated by a GPIO to speed up the notification
to a host.
The EEPROM register ENABLE_GPIO0_ON_OVERTEMP (0054h) allows enabling the
indication of a temperature event on GPIO0.
No other event can be routed to a GPIO.
9.23 Register description
The default setting of a bit within a register is indicated by the "*". Value indicates the
allowed range for the bits of a symbol.
9.23.1 Register overview
Table 58.ꢀRegister Overview
Address (HEX) Address (decimal) Name
0h
0
SYSTEM_CONFIG
EVENT_ENABLE
EVENT_STATUS
EMVCO_EMD_CONTROL
FELICA_EMD_CONTROL
RX_STATUS
1h
1
2h
2
3h
3
4h
4
5h
5
6h
6
RX_STATUS_ERROR
CLIF_STATUS
7h
7
8h
8
TRANSCEIVE_CONTROL
TX_SYMBOL01_MOD
TX_SYMBOL1_DEF
TX_SYMBOL0_DEF
TX_SYMBOL23_MOD
TX_SYMBOL23_DEF
TX_SYMBOL_CONFIG
TX_FRAME_CONFIG
TX_DATA_MOD
9h
9
Ah
Bh
Ch
Dh
Eh
Fh
10
11
12
13
14
15
16
17
18
19
20
21
22
23
10h
11h
12h
13h
14h
15h
16h
17h
TX_WAIT
TX_CRC_CONFIG
RFU
RFU
SS_TX_CONFIG
SS_TX1_RMCFG
SS_TX2_RMCFG
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Table 58.ꢀRegister Overview...continued
Address (HEX) Address (decimal) Name
18h
19h
1A-1C
1D
24
RFU
25
SS_TX_TRANS_CFG
RFU
26-28
29
PUBLIC RESERVED
RFU
1E
30
1F
31
PUBLIC_RESERVED
SIGPRO_RM_PATTERN
PUBLIC RESERVED
RFU
20
32
21
33
22
34
23-24
25
35-36
37
PUBLIC RESERVED
RFU
26
38
RX_FRAME_LENGTH
RX_ERROR_CONFIG
RX_CTRL_STATUS
PUBLIC RESERVED
SIGPRO_IIR_CONFIG0
PUBLIC RESERVED
RFU
27
39
28
40
29
41
2A
42
2B-2C
2Dh
2E
43-44
45
46
PUBLIC RESERVED
RFU
2Fh
30h
31h
32h
33
47
48
DGRM_RSSI
49
RX_CRC_CONFIG
RX_WAIT
50
51
PUBLIC RESERVED
RFU
34
52
35
53
RXM_CTRL
36
54
PUBLIC RESERVED
RFU
37
55
38-3A
3B
56-58
59
PUBLIC RESERVED
SS_TX1_CMCFG
SS_TX2_CMCFG
TIMER0_CONFIG
TIMER0_RELOAD
RFU
3C
60
3Dh
3Eh
3Fh
40h
41h-42h
61
62
63
64
RFU
65-66
RFU
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Table 58.ꢀRegister Overview...continued
Address (HEX) Address (decimal) Name
43
67
PUBLIC RESERVED
RFU
44-46
47h
48h
49-4F
50
68-70
71
EMD_1_CONFIG
72
EMD_0_CONFIG
73-79
80
RFU
LPCD_CALIBRATE_CTRL
IQ_CHANNEL_VALS
PAD_CONFIG
51
81
52
82
53
83
CALIBRATE_STATUS
TXLDO_VDDPA_CONFIG
GENERAL_ERROR_STATUS
TXLDO_VOUT_CURR
CLIF_DAC
54
84
55
85
56
86
57
87
58
88
PMU_ANA_SMPS_CTRL_REG
RXM_FREQ
59
89
5A
5B
5D
80
90
RXM_RSSI
91
TEMP_SENSOR
93
TX_NOV_CALIBRATE
SS_TX1_RTRANS0
SS_TX1_RTRANS1
SS_TX1_RTRANS2
SS_TX1_RTRANS3
SS_TX1_RTRANS4
SS_TX1_RTRANS5
SS_TX1_RTRANS6
SS_TX1_RTRANS7
SS_TX1_RTRANS8
SS_TX1_RTRANS9
SS_TX1_RTRANS10
SS_TX1_RTRANS11
SS_TX1_RTRANS12
SS_TX1_RTRANS13
SS_TX1_RTRANS14
SS_TX1_RTRANS15
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
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9.23.2 SYSTEM_CONFIG (0000h)
Table 59.ꢀSYSTEM_CONFIG register (address 0000h) bit description
Bit
31:9
8
Symbol
Access
r/w
Value
0*,1
Description
RFU
-
TX_NOV_CALIBRATION
r/w
0*,1
One time calibration when the host writes a 1 into this
register, a one time calibration will be performed.
Note:
The calibration is resulting a short RF-on. All the
power configurations shall the configured before
setting this bit.
7
RFU
r/w
r/w
0
-
6:5
15693_CHANGE_DATARATE
0*,1
15693_changedatarate
0 - RFU
1 - Change Data Rate to 53kB/sec
2 - Change Data Rate to 106kB/sec
3 - Change Data Rate to 212kB/sec
By default, the basic data rate of 26kB/sec will
be loaded, switching to a different higher data
rate requires this config register to be updated.
All relevant related registers will be updated
automatically.
4
3
RFU
r/w
r/w
0*,1
0*,1
-
AUTOCOLL STATE A
0: TypeA Card mode: Autocoll entry with IDLE state
of the card
1: TypeA Card mode: Autocoll entry with HALT state
of the card
2
1
0
SOFT RESET
MF CRYPTO ON
RFU
r/w
r/w
r/w
0*,1
0*,1
0*,1
Performs a soft reset of the system, all registers are
set to default values
If set to 1 the MIFARE - crypto bit is generated for
MIFARE Classic en-/de-cryption
-
9.23.3 EVENT_ENABLE (0001h)
Table 60.ꢀEVENT_ENABLE register (address 0001h) bit description
Bit
31:8
11
Symbol
Access Value
Description
RFU
r
0*,1
-
CTS_EVENT_ENABLE
IDLE_EVENT_ENABLE
Enable the corresponding event
Enable the corresponding event
Enable the corresponding event
10
9
LP_CALIBRATION_EVENT_
ENABLE
8
7
6
5
LPCD_EVENT_ENABLE
Enable the corresponding event
Enable the corresponding event
Enable the corresponding event
Enable the corresponding event
AUTOCOLL_EVENT_ENABLE
TIMER0_EVENT_ENABLE
TEMP_ERROR_EVENT_ENABLE
r/w
r/w
r/w
0*,1
0*,1
0*,1
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Table 60.ꢀEVENT_ENABLE register (address 0001h) bit description...continued
Bit
4
Symbol
Access Value
Description
RFON_DET_EVENT_ENABLE
RFOFF_DET_EVENT_ENABLE
r/w
r/w
0*,1
0*,1
0*,1
0*,1
Enable the corresponding event
Enable the corresponding event
Enable the corresponding event
Enable the corresponding event
3
2
STANDBY_PREV_EVENT_ENABLE r/w
1
GENERAL_ERROR_EVENT_
ENABLE
r/w
0
BOOT_EVENT_ENABLE
r/w
0*,1
Enable the corresponding event
9.23.4 EVENT_STATUS (0002h)
Table 61.ꢀEVENT_STATUS register (address 0002h) bit description
Bit
31:12
11
10
9
Symbol
Access Value
Description
RFU
r
0*,1
-
CTS_EVENT
Indicated the availability of CTS Event
Indicated the availability of IDLE event.
Indicated the availability of LP Calibration event
Indicated the availability of LPCD event.
Indicated the availability of Autocoll event
Indicated the availability of Timer0 event
Indicated the availability of Temp error
Indicated the availability of RF ON detected.
IDLE_EVENT
LP_CALIBRATION_EVENT
LPCD_EVENT
8
7
AUTOCOLL_EVENT
TIMER0_EVENT
TEMP_ERROR_EVENT
RFON_DET_EVENT
RFOFF_DET_EVENT
r/w
r/w
r/w
r/w
r/w
0*,1
0*,1
0*,1
0*,1
0*,1
6
5
4
3
Indicated the availability of Standby Prevention
reason.
2
STANDBY_PREV_EVENT
r/w
0*,1
Indicated the availability of Standby Prevention
reason.
1
0
GENERAL_ERROR_EVENT
BOOT_EVENT
r/w
r/w
0*,1
0*,1
Indicated the availability of General Error event.
Indicated the availability of Boot event.
9.23.5 EMVCO_EMD_CONTROL (0003h)
To activate the EMVCo EMD handling of the PN5190B1, the following bits of the register
need to be set as follows:
0001b: EMVCO_EMD_ENABLE
1b: EMD_TRANSMISSION_ERROR_ABOVE_NOISE_THRESHOLD_IS_NO_EMD
0001b: EMD_NOISE_BYTES_THRESHOLD
Table 62.ꢀEMVCO_EMD_CONTROL register (address 0003h) bit description
Bit
Symbol
Access Value
rw 0*,1
Description
31:12
RFU
-
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Table 62.ꢀEMVCO_EMD_CONTROL register (address 0003h) bit description...continued
Bit
Symbol
Access Value
Description
11:10
EMD_RM_EMD_SENSITIVITY
rw
0*,1
RM EMD SENSITIVITY value that will be applied
to SIGPRO_RM_CONFIG,
At layer 4, when EMD is enabled, the value
of EMD_RM_SENSITIVITY can be lowered
to ensure robust EMD suppression, if during
the layer 3 activation, the value of EMD_RM_
SENSITIVITY in the protocol area is set to a high
value to ensure collision detection and resolution
when multiple typeA cards are presented at close
distance to the antenna.
9:8
7
EMD_TRANSMISSION_TIMER_
USED
rw
rw
0*,1
0*,1
Timer used for RF communication.
EMD_MISSING_CRC_IS_
PROTOCOL_ERROR_TYPE_B
Missing CRC treated as protocol error in » case of
Type B based communication P » case of Type B
based communication
6
EMD_MISSING_CRC_IS_
PROTOCOL_ERROR_TYPE_A
rw
0*,1
0*,1
Missing CRC treated as protocol error in » case of
Type A based communication P » case of Type A
based communication
5:2
EMD_NOISE_BYTES_THRESHOLD rw
Defines the threshold under which transmission
errors are treated as noise.
Note: CRC bytes are NOT included/counted!
1
0
EMD_TRANSMISSION_ERROR_
ABOVE_NOISE_THRESHOLD_IS_
NO_EMD
rw
rw
0*,1
0*,1
Transmission errors with received byte length >=
EMD_NOISE_BYTES_THRESHOLD is never
treated as EMD (can be used for versions below
EMVCo3.0)
EMVCO_EMD_ENABLE
EMD handling enabled
If this register is enabled by setting EMVCO_
EMD_ENABLE=1, the registers EMD_0_CONFIG
and EMD_1_CONFIG is ignored for the EMVCO_
EMD function.
9.23.6 FELICA_EMD_CONTROL (0004h)
Table 63.ꢀFELICA_EMD_CONTROL register (address 0004h) bit description
Bit
Symbol
Access setting Value
Description
for
FeliCa
EMD
handlin
31:24
23:16
15:8
7:5
FELICA_EMD_RC_BYTE_
VALUE
rw
0
0
0
0
0*,1
0*,1
0*,1
0*,1
FeliCa RC byte value that needs to be received
does not treat the frame as EMD
FELICA_EMD_LENGTH_BYTE_ rw
MAX
Maximum Length byte value that needs to be
received does not treat the frame as EMD
FELICA_EMD_LENGTH_BYTE_ rw
MIN
Minimum Length byte value that needs to be
received does not treat the frame as EMD
RESERVED
rw
-
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Table 63.ꢀFELICA_EMD_CONTROL register (address 0004h) bit description...continued
Bit
Symbol
Access setting Value
Description
for
FeliCa
EMD
handlin
4
3
2
FELICA_EMD_INTEGRITY_
ERR_CHECK_ENABLE
rw
rw
rw
1
1
0
0*,1
0*,1
0*,1
FeliCa EMD handling enabled when integrity
error is set
FELICA_EMD_PROTOCOL_
ERR_CHECK_ENABLE
FeliCa EMD handling enabled when protocol
error is set
FELICA_EMD_RC_CHECK_
ENABLE
FeliCa RC byte check enabled for FeliCa EMD
handling
1
0
FELICA_EMD_LEN_CHECK_
ENABLE
rw
rw
0
1
0*,1
0*,1
FeliCa Length byte check enabled for FeliCa
EMD handling
FELICA_EMD_ENABLE
FeliCa EMD handling enabled
Recommended value for FeliCa EMD handling: 00FF0019h
9.23.7 RX_STATUS (0005h)
Table 64.ꢀRX_STATUS register (address 0005h) bit description
Bit
Symbol
Access Value
Description
31:27
26:20
RFU
r
r
0*,1
0*,1
-
RX_COLL_POS
Status indicating the bit position of the first collision
detected in the data bit. The value is valid only when
RX_COLLISION_DETECTED==1. The value of the
RX_BIT_ALIGN is also taken into account (RX_
COLL_POS = physical bit position in the flow + RX_
BIT_ALIGN value).
Indicates the collision position in the first 8 bytes
only. Can be used during the TypeA/ICODE/EPC
anti-collision procedure.0x00 - first bit 0x01 - second
bit...0x7F - 128th bit.
The status register is not updated by the collision
detected on stop or parity bit.
19:17
RX_NUM_LAST_BITS
r
0*,1
Indicating the number of valid bits in the last byte
received.
0: all bits are valid
1: 1 bit is valid
….
7: - 7 bits are valid
This is generally used during ISO/IEC14443 type A
anti-collision
16:13
RX_NUM_FRAMES_RECEIVED
RX_NUM_BYTES_RECEIVED
r
r
0*,1
0*,1
Indicates the number of frames received. The value
is updated after every normal frame reception in RX_
MULTIPLE mode.
The value is valid only if the bit RX_MULTIPLE_
ENABLE==’1’.
12:0
Number of bytes received on the RF interface
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9.23.8 RX_STATUS_ERROR (0006h)
Table 65.ꢀRX_STATUS_ERROR register (address 0006h) bit description
Bit
Symbol
Access
Value
0*,1
Description
31:30
29
RFU
r
EMD_DETECTED_IN_RXDEC
r/w
0*,1
The high level indicates that the EMD was detected
(in the SigPro or in the RxDecoder or in both) during
the reception.
28
EMD_DETECTED_IN_SIGPRO
r/w
0*,1
The high level indicates that the EMD was detected
on the Physical layer (in the SigPro) during the
reception.
27
26
EXT_RFOFF_DETECTED
RX_FRAME_MAXLEN_VIOL
r/w
r/w
0*,1
0*,1
The high level indicates that the received frame
length violated the configured minimum limit.
The high level indicates that the received frame
length is less or equal to the expected CRC field
length.
25
24
RX_FRAME_MINLEN_VIOL
RX_FRAME_LE_CRC
r/w
r/w
0*,1
0*,1
The high level indicates that the last received
character in the frame has less than 8 bits.
The high level indicates that the last received
character in the frame has 8 data bits but the
expected parity bit is absent.
23
RX_NOT_FULL_BYTE
r/w
0*,1
The high level indicates that the last received
character in the frame has 8 data bits but the
expected stop bit is absent.
22
21
20
19
RX_MISSING_PARBIT_
DETECTED
r/w
r/w
r/w
r/w
0*,1
0*,1
0*,1
0*,1
The high level indicates that the collision was
detected on the parity bit position.
RX_MISSING_STOPBIT_
DETECTED
The high level indicates that the collision was
detected on the stop bit position.
RX_COLLISION_PARBIT_
DETECTED
The high level indicates that the collision was
detected during the frame reception.
RX_COLLISION_STOPBIT_
DETECTED
The high level indicates that the frame reception
was stopped by SGP_MSG_RXOVER_* message
reception.
18
17
RX_COLLISION_DETECTED
RX_STOP_ON_RXOVER
r/w
r/w
0*,1
0*,1
The high level indicates that the collision was
detected during the frame reception.
The high level indicates that the frame reception
was stopped by SGP_MSG_RXOVER_* message
reception.
16
15
14
RX_STOP_ON_RFOFF
RX_STOP_ON_ERR
RX_STOP_ON_LEN
r/w
r/w
r/w
0*,1
0*,1
0*,1
The high level indicates that the frame reception
was interrupted by external RF-field vanishing
event.
The high level indicates that the frame reception
was stopped by detected communication error
event.
The high level indicates that the frame reception
was normally stopped by byte counter expiration
event. Relates to the protocols where the LEN field
is used in the frame format (FeliCa RM/CM, FWEC
RM/CM).
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Table 65.ꢀRX_STATUS_ERROR register (address 0006h) bit description...continued
Bit
Symbol
Access
Value
Description
13
RX_STOP_ON_INVPAR
r/w
0*,1
The high level indicates that the frame reception
was normally stopped by the inverted parity
detection event. Relates to the TypeA RM 212-848
kbit/s modes. 12 RX_STOP_ON_PATTERN R 0h
The high level indicates that the frame reception
was normally stopped by EOF pattern detection
event. Relates to the TypeB RM/CM, B prime RM/
CM modes.
12
11
RX_STOP_ON_PATTERN
RX_STOP_ON_ANTICOLL
r/w
r/w
0*,1
0*,1
The high level indicates that the frame reception
was normally stopped by EOF pattern detection
event. Relates to the TypeB RM/CM, B prime RM/
CM modes.
The high level indicates that the frame reception
was normally stopped by collision detected on
data bit position. Relates to the bit-oriented frame
reception in TypeA RM 106 kbit/s mode during the
anti-collision procedure.
10
9
RX_CRC_ERROR
RX_LEN_ERROR
r/w
r/w
0*,1
0*,1
The high level indicates that the CRC error is
detected in the received frame.
The high level is set if the received frame is shorter
than the length stated in the received frame LEN
field OR if the LEN parameter in the received frame
violates the configured [RX_FRAME_MINLEN:RX_
FRAME_MAX LEN] limits. Can assert only in the
mode where the LEN field is used in the frame
format (FeliCa RM/CM, FWEC RM/CM).
8
RX_SIGPRO_ERROR
r/w
0*,1
The high level indicates that the communication
error/errors were detected during the frame
reception on physical layer(in the SigPro).
7
6
RX_PARITY_ERROR
RX_STOPBIT_ERROR
r/w
r/w
0*,1
0*,1
The high level indicates that the parity error was
detected during the frame reception.
The high level indicates that the stop bit error (‘0’
level instead of ‘1’ on the stop bit position) was
detected during the frame reception.
5
4
3
2
RX_WRITE_ERROR
r/w
r/w
r/w
r/w
0*,1
0*,1
0*,1
0*,1
The high level indicates that the error acknowledge
status was received on the CLIF-system interface
during the received frame transmission to the
System RAM.
RX_BUFFER_OVFL_ERROR
RX_LATENCY_ERROR
The high level indicates that the data payload length
in the received frame exceeds the 28 bytes limit.
Relates to the PollReq procedure in the FeliCa RM
mode only.
The high level indicates that the write request
flow was corrupted due to traffic congestion on
the system interface during the received frame
transmission to the System RAM.
RX_DATA_INTEGRITY_ERROR
The high level indicates that the data integrity
corruption (parity/CRC/etc error) was detected in the
received frame.
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Table 65.ꢀRX_STATUS_ERROR register (address 0006h) bit description...continued
Bit
Symbol
Access
Value
Description
1
RX_PROTOCOL_ERROR
r/w
0*,1
The high level indicates that the protocol
requirements violation (stop bit error, missing parity
bit, not full byte received, etc) was detected in the
received frame.
0
RX_CL_ERROR
r/w
0*,1
The high level indicates that some protocol/data
integrity erorr/errors were detected during the frame
reception
9.23.9 CLIF_STATUS (0007h)
Table 66.ꢀCLIF_STATUS register (address 0007h) bit description
Bit
Symbol
RFU
Access
Value
0*,1
Description
31:30
29
r
r
-
CRC_OK
0*,1
This bit indicates the status of the actual CRC
calculation. If 1 the CRC is correct. meaning the
CRC register has the value 0 or the residue value if
inverted CRC is used. Note: This flag should only be
evaluated at the end of a communication
28
27
RX_SC_DETECTED
RX_SOF_DETECTED
r
r
0*,1
0*,1
Status signal indicating that a subcarrier is detected.
Status signal indicating that a SOF has been
detected.
26
25
24
23
TX_RF_STATUS
RF_DET_STATUS
ADC_Q_CLIPPING
ADC_I_CLIPPING
r
r
r
r
0*,1
0*,1
0*,1
0*,1
If set to 1 this bit indicates that the drivers are turned
on. meaning an RF-Field is created by the device
itself.
If set to 1 this bit indicates that an external RF-Field
is detected by the RF level detectors (after digital
filtering)
Indicates that the Q-Channel ADC has clipped
(value 0 or 63), This bit is reset with Rx-reset
(enabling of receiver).
Indicates that the I-Channel ADC has clipped (value
0 or 63), This bit is reset with Rx-reset (enabling of
receiver).
22:12
11
RFU
r
r
0*,1
0*,1
-
TX_NO_DATA_ERROR
This error flag is set to 1. in case a transmission
is started but no data is available (register
NumBytesToSend == 0).
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Table 66.ꢀCLIF_STATUS register (address 0007h) bit description...continued
Bit
Symbol
Access
Value
Description
10:8
RF_ACTIVE_ERROR_CAUSE
r
0*,1
This status flag indicates the cause of an NFC-
Active error.
Note: These bits are only valid when the RF_
ACTIVE_ERROR_IRQ is raised and will be cleared
as soon as the bit TX_RF_ENABLE is set to 1. 0*
No Error. reset value 1 External field was detected
on within TIDT timing 2 External field was detected
on within TADT timing 3 No external field was
detected within TADT timings 4 Peer did switch off
RF Field without but no RX event was raised (no
data received) 5 - 7 Reserved.
7:6
5
RFU
r
r
0*,1
0*,1
-
RX_ENABLE
This bit indicates if the RxDecoder is enabled. If 1
the RxDecoder was enabled and is now ready for
data reception
4
TX_ACTIVE
r
r
r
0*,1
0*,1
0*,1
This bit indicates activity of the TxEncoder. If 1 a
transmission is ongoing otherwise the TxEncoder is
in idle state.
3
RX_ACTIVE
This bit indicates activity of the RxDecoder. If 1 a
data reception is ongoing. otherwise the RxDecoder
is in idle state.
2:0
RF_EXCHANGE_STATE
These registers hold the command bits
0* IDLE state
1 WaitTransmit state
2 Transmitting state
3 WaitReceive state
4 WaitForData state
5 Receiving state
6 LoopBack state
7 reserved
9.23.10 RF_EXCHANGE_CONTROL (0008h)
To meet the ISO14443A FDT with an accuracy of 1 carrier clock cycle, there is support
implemented to synchronize the guard time pre-scaler to the modified Miller envelope
pulses (end of pulse). For adjustment, there is a 7-bit wide configuration register -
TX_BITPHASE - which is allows to adjust the FDT in the range of 0 to 128 carrier clock
cycles. As defined in the ISO14443 the adjustment is different, depending on the data
bit value of the data stream. For correct bit grid calculation, the pre-scaler must be set
to a value corresponding exactly to one etu - for 106 kbit/s this corresponds to 0x7F.
Otherwise the FdT will be incorrect.
Table 67.ꢀRF_EXCHANGE_CONTROL register (address 0008h) bit description
Bit
Symbol
Access Value
Description
31:16
15:8
RFU
r
0*,1
0*,1
-
TX_BITPHASE
r/w
Defines the number of 13.56 MHz cycles used for
adjustment of TX_WAIT to meet the FDT. This is
applicable for CardMode only.
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Table 67.ꢀRF_EXCHANGE_CONTROL register (address 0008h) bit description...continued
Bit
7:3
2
Symbol
Access Value
Description
RFU
r/w
r/w
0*,1
0*,1
-
RX_MULTIPLE_ENABLE
If this bit is set to 1. the receiver is reactivated after
the end of a reception.
1:0
RFU
r/w
0*,1
-
9.23.11 TX_SYMBOL01_MOD (0009h)
Table 68.ꢀTX_SYMBOL01_MOD register (address 0009h) bit description
Bit
Symbol
Access Value
Description
31:24
23:16
RFU
rw
rw
0*,1
0*,1
-
TX_S01_MODWIDTH
Specifies the length of a pulse for sending data of
symbol 0/1. The length is given by the number of
carrier clocks + 1.
15:9
8
RFU
rw
rw
0*,1
0*,1
-
TX_S01_MILLER_ENABLE
If set to 1. pulse modulation is applied according to
modified miller coding.
7:5
4
TX_S01_INV_ENV
rw
rw
0*,1
0*,1
If set to 1. the output envelope is inverted.
TX_S01_ENV_TYPE
Specifies the type of envelope used for transmission
of data packets. The selected envelope type is
applied to the pseudo bit stream. 000b Direct output
001b Manchester code 010b Manchester code with
subcarrier 011b BPSK 100b RZ (pulse of half bit
length at beginning of second half of bit) 101b RZ
(pulse of half bit length at beginning of bit) 110b
Manchester tupple 111b RFU.
3
TX_S01_SC_FREQ
TX_S01_BIT_FREQ
rw
rw
0*,1
0*,1
Specifies the frequency of the subcarrier. 0 424 kHz 1
848 kHz
2:0
Specifies the frequency of the bit-stream.
000b -> 1.695 MHz.
001b -> Reserved.
010b -> 26 kHz.
011b -> 53 kHz.
100b -> 106 kHz.
101b -> 212 kHz.
110b -> 424 kHz.
111b -> 848 kHz.
9.23.12 TX_SYMBOL1_DEF (000Ah)
Table 69.ꢀTX_SYMBOL1_DEF register (address 000Ah) bit description
Bit
Symbol
Access Value
RW 0*,1
Description
31:0
TX_SYMBOL1_DEF
Pattern definition for Symbol1
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9.23.13 TX_SYMBOL0_DEF (000Bh)
Table 70.ꢀTX_SYMBOL0_DEF register (address 000Bh) bit description
Bit
Symbol
Access Value
RW 0*,1
Description
31:0
TX_SYMBOL0_DEF
Pattern definition for Symbol0
9.23.14 TX_SYMBOL23_MOD (000Ch)
Table 71.ꢀTX_SYMBOL23_MOD register (address 000Ch) bit description
Bit
Symbol
Access Value
Description
31:24
23:16
RFU
r
0*,1
0*,1
-
TX_S23_MODWIDTH
r/w
Specifies the length of a pulse for sending data of
symbol 2/3. The length is given by the number of
carrier clocks + 1.
15:9
8
RFU
r/w
r/w
0*,1
0*,1
-
TX_S23_MILLER_ENABLE
If set to 1 pulse modulation is applied according to
modified miller coding
7
TX_S23_INV_ENV
r/w
r/w
0*,1
0*,1
If set to 1 the output envelope is inverted.
6:4
TX_S23_ENV_TYPE
Specifies the type of envelope used for transmission
of data packets. The selected envelope type is
applied to the pseudo bit stream. 000b Direct output
001b Manchester code 010b Manchester code with
subcarrier 011b BPSK 100b RZ (pulse of half bit
length at beginning of second half of bit) 101b RZ
(pulse of half bit length at beginning of bit) 110b
Manchester tupple 111b RFU
3
TX_S23_SC_FREQ
TX_S23_BIT_FREQ
r/w
r/w
0*,1
0*,1
Specifies the frequency of the subcarrier. 0 424 kHz 1
848 kHz
2:0
Specifies the frequency of the bit-stream. 000b ->
1.695 MHz. 001b -> Reserved. 010b -> 26 kHz. 011b
-> 53 kHz. 100b -> 106 kHz. 101b -> 212 kHz. 110b -
> 424 kHz. 111b -> 848 kHz.
9.23.15 TX_SYMBOL23_DEF (000Dh)
Table 72.ꢀTX_SYMBOL23_DEF register (address 000Dh) bit description
Bit
Symbol
Access Value
Description
31:24
23:16
15:8
7:0
RFU
r
0*,1
0*,1
0*,1
-
TX_SYMBOL3_DEF
RFU
r/w
r/w
r/w
Pattern definition for Symbol3
-
TX_SYMBOL2_DEF
00000h* - Pattern definition for Symbol2
FFFFFh
9.23.16 TX_SYMBOL_CONFIG (000Eh)
Table 73.ꢀTX_SYMBOL_CONFIG register (address 000Eh) bit description
Bit
Symbol
Access Value
Description
31
RFU
0*,1
-
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Table 73.ꢀTX_SYMBOL_CONFIG register (address 000Eh) bit description...continued
Bit
Symbol
Access Value
Description
30:27
TX_SYMBOL1_BURST_LEN
r/w
00000h* - Specifies the number of bits issued for symbol 1
FFFFFh burst. The 3 bits encode a range from 8 to 256 bit
length: 0000b 8 bit 0001b 12 bit 0010b 16 bit 0011b
24 bit 0100b 32 bit 0101b 40 bit 0110b 48 bit 0111b
64 bit 1000b 80 bit 1001b 96 bit 1010b 112 bit 1011b
128 bit 1100b 160 bit 1101b 192 bit 1110b 224 bit
1111b 256 bit
26
25
24
TX_SYMBOL1_BURST_TYPE
TX_SYMBOL1_BURST_ONLY
r/w
r/w
r/w
0*,1
0*,1
0*,1
Specifies the type of the burst of Symbol1 (logical
zero / logical one)
If set to 1. Symbol1 consists only of a burst and no
symbol pattern
TX_SYMBOL1_BURST_
ENABLE
If set to 1. the burst of Symbol0 of the length defined
in bit field SYMBOL1_BURST_LEN is enabled
23
RFU
r
0*,1
0*,1
-
22:19
TX_SYMBOL0_BURST_LEN
r/w
Specifies the number of bits issued for symbol 0
burst. The 3 bits encode a range from 8 to 256 bit
length: 0000b 8 bit 0001b 12 bit 0010b 16 bit 0011b
24 bit 0100b 32 bit 0101b 40 bit 0110b 48 bit 0111b
64 bit 1000b 80 bit 1001b 96 bit 1010b 112 bit 1011b
128 bit 1100b 160 bit 1101b 192 bit 1110b 224 bit
1111b 256 bit
18
TX_SYMBOL0_BURST_TYPE
TX_SYMBOL0_BURST_ONLY
r/w
r/w
r/w
r/w
0*,1
0*,1
0*,1
0*,1
Specifies the type of the burst of Symbol0 (logical
zero / logical one)
17
If set to 1. Symbol0 consists only of a burst and no
symbol pattern
16
TX_SYMBOL0_BURST_
ENABLE
If set to 1. the burst of Symbol0 of the length defined
in bit field SYMBOL0_BURST_LEN is enabled
15:13
TX_SYMBOL3_LEN
TX_SYMBOL2_LEN
TX_SYMBOL1_LEN
TX_SYMBOL0_LEN
Specifies the number of valid bits of the symbol
definition of Symbol3. The range is from 1 bit (value
0000) to 8 bit (value 111)
12:10
9:5
r/w
r/w
r/w
0*,1
0*,1
0*,1
Specifies the number of valid bits of the symbol
definition of Symbol2. The range is from 1 bit (value
0000) to 8 bit (value 111)
Specifies the number of valid bits of the symbol
definition of Symbol1. The range is from 1 bit (value
0000) to 31 bits (value 11110)
4:0
Specifies the number of valid bits of the symbol
definition of Symbol0. The range is from 1 bit (value
0000) to 31 bits (value 11110)
9.23.17 TX_FRAME_CONFIG (000Fh)
Table 74.ꢀTX_FRAME_CONFIG register (address 000Fh) bit description
Bit
Symbol
Access Value
0*,1
Description
31:19
RFU
r
-
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Table 74.ꢀTX_FRAME_CONFIG register (address 000Fh) bit description...continued
Bit
Symbol
Access Value
Description
18:16
TX_DATA_CODE_TYPE
r/w
0*,1
Specifies the type of encoding of data to be used
000b No special code 001b 1 out of 4 code [ICODE
SLI] 010b 1 out of 256 code [ICODE SLI] 011b Pulse
interval encoding (PIE) [ICODE EPC-V2] 100b 2bit
tupple code (intended only for test purpose) 101-111b
Reserved
15:13
TX_STOPBIT_TYPE
r/w
0*,1
Enables the stop bit (logic 1) and extra guard time
(logic 1). The value 0 disables transmission of stop-
bits. 000b no stop-bit. no EGT 001b stop-bit. no EGT
010b stop-bit + 1 EGT 011b stop-bit + 2 EGT 100b
stop-bit + 3 EGT 101b stop-bit + 4 EGT 110b stop-bit
+ 5 EGT 111b stop-bit + 6 EGT
12
11
TX_STARTBIT_ENABLE
TX_MSB_FIRST
r/w
r/w
0*,1
0*,1
If set to 1. a start-bit (logic 0) will be sent
If set to 1. data bytes are interpreted MSB first for
data transmission
10
9
TX_PARITY_LAST_INV_
ENABLE
r/w
r/w
r/w
0*,1
0*,1
0*,1
If set to 1. the parity bit of last sent data byte is
inverted
TX_PARITY_TYPE
Defines the type of the parity bit 0 Even Parity is
calculated 1 Odd parity is calculated
8
TX_PARITY_ENABLE
If set to 1. a parity bit is calculated and appended to
each byte transmitted. If the Transmission Of Data
Is Enabled and TX_NUM_BYTES_2_SEND is zero.
then a NO_DATA_ERROR occurs.
7:5
4
RFU
r
0*,1
0*,1
-
TX_DATA_ENABLE
r/w
If set to 1. transmission of data is enabled otherwise
only symbols are transmitted.
3:2
1:0
TX_STOP_SYMBOL
TX_START_SYMBOL
r/w
r/w
0*,1
0*,1
Defines which pattern symbol is sent as frame stop-
symbol 00b No symbol is sent 01b Symbol1 is sent
10b Symbol2 is sent 11b Symbol3 is sent
Defines which symbol pattern is sent as frame start-
symbol 00b No symbol pattern is sent 01b Symbol0 is
sent 10b Symbol1 is sent 11b Symbol2 is sent
9.23.18 TX_DATA_MOD (0010h)
Table 75.ꢀTX_DATA_MOD register (address 0010h) bit description
Bit
Symbol
Access Value
Description
31:25
24
RFU
r
0*,1
0*,1
-
TX_ICODE_DATA_MODWIDTH_ r/w
ENABLE
Enables modulation width of icode data. Width of
modulation is defined by the TX_DATA_MODWIDTH
field. When 1, we should have TX_DATA_ENV_
TYPE=0 and TX_DATA_INV_ENV=0
23:16
TX_DATA_MODWIDTH
RFU
r/w
r
0*,1
0*,1
Specifies the length of a pulse for sending data with
miller pulse modulation enabled. The length is given
by the number of carrier clocks + 1.
15:9
-
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Table 75.ꢀTX_DATA_MOD register (address 0010h) bit description...continued
Bit
Symbol
Access Value
Description
8
TX_DATA_MILLER_ENABLE
r/w
0*,1
If set to 1 pulse modulation is applied according to
modified miller coding
7
TX_DATA_INV_ENV
r/w
r/w
0*,1
0*,1
If set to 1 the output envelope is inverted
6:4
TX_DATA_ENV_TYPE
Specifies the type of envelope used for transmission
of data packets. The selected envelope type is
applied to the pseudo bit stream. 000b Direct output
001b Manchester code 010b Manchester code with
subcarrier 011b BPSK 100b RZ (pulse of half bit
length at beginning of second half of bit) 101b RZ
(pulse of half bit length at beginning of bit) 110b
Manchester tupple coding 111b RFU
3
TX_DATA_SC_FREQ
TX_DATA_BIT_FREQ
r/w
r/w
0*,1
0*,1
Specifies the frequency of the subcarrier. 0 424 kHz 1
848 kHz
2:0
Specifies the frequency of the bit-stream. 000b ->
1.695 MHz. 001b -> Reserved. 010b -> 26 kHz. 011b
-> 53 kHz. 100b -> 106 kHz. 101b -> 212 kHz. 110b -
> 424 kHz. 111b -> 848 kHz.
9.23.19 TX_WAIT (0011h)
To guarantee correct protocol timing a guard period timer is implemented for the
RF_EXCHANGE command in reception and transmission mode.
These guard times are not available for Transmit or Receive command.
The guard time TX_WAIT is started after the end of a reception no matter if the frame is
correct or erroneous.
It is not started in case the reception is restarted because of an EMD-event or in case the
RX_MULTIPLE_ENABLE bit is set to 1 the TX_WAIT.
In case the register flag TX_WAIT_RFON_ENABLE is set to 1 the guard time timer is
started when the devices own RF-Field was switched on.
It is possible to disable the guard time tx_wait by setting the register TX_WAIT_VALUE to
00h.
TX_WAIT can be used for 2 different purposes:
1. It can be used to prevent start of transmission before a certain period has expired -
even if FW already finished data processing and set the START_SEND bit. This behavior
is mainly intended for reader mode to guaranteed PICC to PCD frame delay time (FDT).
2. TX_WAIT time can be used to start the transmission at an exactly defined time.
Table 76.ꢀTX_CLIF_WAIT register (address 0011h) bit description
Bit
Symbol
Access Value
Description
31:28
27:8
RFU
r
0*,1
0*,1
-
TX_WAIT_VALUE
r/w
Defines the tx_wait timer reload value. Note: If set
to 00000h the tx_wait timer guard time is disabled
Note: This bit is set by HW a protocol is detected in
automatic mode detection
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Table 76.ꢀTX_CLIF_WAIT register (address 0011h) bit description...continued
Bit
Symbol
Access Value
r/w 0*,1
Description
0
TX_WAIT_PRESCALER
Defines the prescaler reload value for the tx_wait
timer. Note: This bit is set by HW a protocol is
detected in automatic mode detection
9.23.20 TX_CRC_CONFIG (0012h)
Table 77.ꢀTX_CRC_CONFIG (address 0012h) bit description
Bit
Symbol
Access Value
Description
31:16
TX_CRC_PRESET_VALUE
r/w
0*-FFFFh Arbitrary preset value for the TX-Encoder CRC
calculation.
15:7
6
RFU
r/w
r/w
0
Reserved
TX_CRC_BYTE2_ENABLE
0*,1
If set; the CRC is calculated from the second byte
onwards (intended for HID). This option is used in the
TX-Encoder.
5:3
TX_CRC_PRESET_SEL
r/w
000-101b Preset values of the CRC register for the TX-Encoder.
For a CRC calculation using 5 bits, only the LSByte is
used.
000b*
001b
010b
011b
100b
101b
110b
111b
0000h, reset value
6363h
A671h
FFFFh
0012h
E012h
RFU
Use arbitrary preset value TX_CRC_PRESET_
VALUE
2
1
0
TX_CRC_TYPE
TX_CRC_INV
r/w
r/w
r/w
0*,1
Controls the type of CRC calculation for the TX-
Encoder
0*
16-bit CRC calculation, reset value
5-bit CRC calculation
1
0*,1
Controls the sending of an inverted CRC value by the
TX-Encoder
0*
Not inverted CRC checksum, reset value
Inverted CRC checksum
1
TX_CRC_ENABLE
0*, 1
If set to one, the TX-Encoder computes and transmits
a CRC.
9.23.21 SS_TX_CONFIG (00015h)
Table 78.ꢀSS_TX_CONFIG register (address 0015h) bit description
Bit
Symbol
Access
Value
Description
31:14
RFU
r
0*,1
-
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Table 78.ꢀSS_TX_CONFIG register (address 0015h) bit description...continued
Bit
Symbol
Access
Value
Description
13
TX2_USE_TX1_CONF
r/w
0*,1
When 1, the tx1 configuration is used also for tx2: all
SS_TX2_* registers are discarded and configurations
from corresponding SS_TX1_* register is used.
12:6
5:3
RFU
r/w
r/w
r/w
0*,1
0*,1
0*,1
-
TX2_CLK_MODE_DEFAULT
TX1_CLK_MODE_DEFAULT
TX2 clk mode without field (RM and CM)
TX1 clk mode without field (RM and CM)
2:0
9.23.22 SS_TX1_RMCFG (00016h)
Table 79.ꢀSS_TX1_RMCFG register (address 0016h) bit description
Bit
Symbol
Access
Value
0*,1
Description
31:25
24:22
21:19
RFU
r
-
TX1_CLK_MODE_TRANS_RM
TX1_CLK_MODE_MOD_RM
r/w
r/w
0*,1
TX1 clock mode in RM during transition
0*,1
TX1 clock mode of modulated wave in RM
000: TX1=High-Z
001: TX1=VSS_PA
010 - 110: RFU
111: TX1 clocked normal operation
18:16
TX1_CLK_MODE_CW_RM
r/w
0*,1
TX1 clock mode of modulated wave in RM
000: TX1=High-Z
001: TX1=VSS_PA
010 - 110: RFU
111: TX1 clocked normal operation
15:8
7:0
TX1_AMP_MOD_RM
TX1_AMP_CW_RM
r/w
r/w
0*,1
0*,1
TX1 amplitude of modulated wave in RM ( 0x00 = 0%
modulaton, 0xFF: 100% modulation)
TX1 amplitude of unmodulated wave in RM ( 0x00 =
0% signal, 0xFF: 100% signal)
9.23.23 SS_TX2_RMCFG (00017h)
These settings for TX_2 are only applied, if the bit 13 in TX_CONFIG
(TX2_USE_TX1_CONF is set to 0.
Table 80.ꢀSS_TX2_RMCFG register (address 0017h) bit description
Bit
Symbol
Access
Value
0*,1
Description
31:25
24:22
21:19
RFU
r
-
TX2_CLK_MODE_TRANS_RM
TX2_CLK_MODE_MOD_RM
r/w
r/w
0*,1
TX2 clock mode in RM during transition
0*,1
TX2 clock mode of modulated wave in RM
000: TX2=High-Z
001: TX2=VSS_PA
010 - 110: RFU
111: TX2 clocked normal operation
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Table 80.ꢀSS_TX2_RMCFG register (address 0017h) bit description...continued
Bit
Symbol
Access
Value
Description
18:16
TX2_CLK_MODE_CW_RM
r/w
0*,1
TX2 clock mode of modulated wave in RM
000: TX2=High-Z
001: TX2=VSS_PA
010 - 110: RFU
111: TX2 clocked normal operation
15:8
7:0
TX2_AMP_MOD_RM
TX2_AMP_CW_RM
r/w
r/w
0*,1
0*,1
TX2 amplitude of modulated wave in RM ( 0x00 = 0%
modulaton, 0xFF: 100% modulation)
TX2 amplitude of unmodulated wave in RM ( 0x00 =
0% signal, 0xFF: 100% signal)
9.23.24 SS_TX_TRANS_CFG (00019h)
Table 81.ꢀSS_TX_TRANS_CFG register (address 0019h) bit description
Bit
Symbol
Access
Value
Description
31:12
11
RFU
-
TX2_SS_TRANS_RATE
TX2 shaping edge rate: 0: 1/fc, 1: 2/fc. 1/fc should be
selected for CM.
10
TX1_SS_TRANS_RATE
TX2_SS_TRANS_LENGTH
TX1_SS_TRANS_LENGTH
TX1 shaping edge rate: 0: 1/fc, 1: 2/fc. 1/fc should be
selected for CM
9:5
4:0
TX2 shaping edge length: from 0 (disable) to 16. for
CM, only 0 or 4 values are valid
TX1 shaping edge length: from 0 (disable) to 16. for
CM, only 0 or 4 values are valid
9.23.25 SIGPRO_RM_PATTERN (0020h)
Table 82.ꢀSIGPRO_RM_PATTERN register (address 0020h) bit description
Bit
31:16
15
Symbol
Access
r/w
Value
0*,1
0*,1
0*,1
0*,1
Description
RM_SYNC_PATTERN
RM_SYNC_PATTERN_EXT4
RM_SYNC_PATTERN_EXT2
RM_RECEIVE_TILL_END
Sync pattern for FeliCa. LSB transmitted last
Extend FeliCa sync pattern with 16 leading 0s
Extend FeliCa sync pattern with 8 leading 0s
r/w
14
r/w
13
r/w
Do not stop the reception before RxDecoder sends a
stop command.
12
RFU
r
0*,1
0*,1
-
11:0
RM_SOF_PATTERN
r/w
SOF pattern for Type B. LSB transmitted last or Start
Byte pattern for NFC passive.
9.23.26 SIGPRO_RM_TECH (0022h)
Table 83.ꢀSIGPRO_RM_TECH register (address 0022h) bit description
Bit
Symbol
Access Value
rw
Description
31:17
RFU
0
-
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Table 83.ꢀSIGPRO_RM_TECH register (address 0022h) bit description...continued
Bit
Symbol
Access Value
Description
16:15
RM_MF_GAIN
rw
0
Defines the gain of the Matched-Filters
00: Minimum Gain,
11: Maximum Gain
14:0
RFU
rw
0
-
9.23.27 RX_FRAME_LENGTH (0026h)
Table 84.ꢀRX_FRAME_LENGTH register (address 0026h) bit description
Bit
Symbol
Access Value
Description
31
RFU
r
0*,1
0*,1
-
30:16
RX_FRAME_MAXLEN
r/w
Maximal number of received [DATA + CRC] bits in
the frame. The violation of the maximum length limit
can be also configured as an Error/EMD condition.
If the max length violation is configured as error -
the frame reception is stopped in case of maximum
length limit exceeding. Otherwise the reception is
continued.0x0000 - 1 bit...0x7FFF - 32 kbit
15
RFU
r
0*,1
0*,1
-
14:0
RX_FRAME_MINLEN
r/w
Minimal number of received [DATA + CRC] bits in the
frame. The violation of the minimum length limit can
be also configured as an Error/EMD condition. The
parameter also defines the number of received[DATA
+ CRC] bits before which any of the EOF patterns or
INVPAR stop condition events are ignored.0x0000 - 1
bit...0x7FFF - 32 kbit
9.23.28 RX_ERROR_CONFIG (0027h)
Table 85.ꢀRX_ERROR_CONFIG register (address 0027h) bit description
Bit
Symbol
Access Value
Description
31:0
rw
xxx NFC FORUM-compliant error handling
yyy EMVCO-compliant error handling
zzz compliant error handling
9.23.29 RX_CTRL_STATUS (0028h)
Table 86.ꢀRX_CTRL_STATUS register (address 0028h) bit description
Bit
Symbol
Access Value
Description
31:9
8:3
RFU
r
r
dyn
dyn
-
RXCTRL_HF_
ATT_VAL
HF attenuator value
2:0
RFU
r
dyn
-
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9.23.30 SIGPRO_IIR_CONFIG0 (0002Ah)
Table 87.ꢀSIGPRO_IIR_CONFIG0 register (address 002Ah) bit description
Bit
31:1
0
Symbol
RFU
Access
Value
Description
-
IIR_ENABLE
Enable the IIR filter
9.23.31 DGRM_RSSI (0030h)
This register is updated dynamically by the firmware if the DPC is enabled.
Table 88.ꢀDGRM_RSSI register (address 0030h) bit description
Bit
Symbol
Access Value
Description
31:30
29
RFU
-
DGRM_SIGNAL_DETECT_TH_ r/w
OVR
0*,1
Enables the override of signal detect threshold.
Override value is set based on DGRM_SIGNAL_
DETECT_TH_OVR_VAL.
28:23
22:17
16:7
6:0
RFU
r/w
r/w
r/w
0*,1
0*,1
0*,1
0*,1
-
DGRM_RSSI_HYST
DGRM_RSSI_TARGET
Hysteresis value for RSSI target
RSSI target value
DGRM_SIGNAL_DETECT_TH_ r/w
OVR_VAL
Defines the override value for signal detect threshold
when DGRM_SIGNAL_DETECT_TH_OVR is set.
These bits are modified dynamically by the ARC
algorithm based on the DPC voltage.
Only if the ARC is disabled, the value written during
LOAD_RF_CONFIGURATION(0x0D) is retained
throughout the RF Field session.
9.23.32 RX_CRC_CONFIG (0031h)
Table 89.ꢀRX_CRC_CONFIG register (address 0031h) bit description
Bit
Symbol
Access
Value
Description
31:16
RX_CRC_PRESET_VALUE
r
0*,1
Arbitrary preset value for the Rx-Decoder CRC
calculation.
15:8
7
RFU
r/w
r/w
0*,1
0*,1
-
RX_FORCE_CRC_WRITE
If set. the Rx-Decoder will send to the RAM the CRC
bits as well.
6
RX_CRC_ALLOW_BITS
r/w
0*,1
If activated the frame with length =< CRC_length
will be always sent to the System RAM as is, without
CRC bits removal.
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Table 89.ꢀRX_CRC_CONFIG register (address 0031h) bit description...continued
Bit
Symbol
Access
Value
Description
5:3
RX_CRC_PRESET_SEL
r/w
0*,1
Preset value of the CRC register for the Rx-Decoder.
For a CRC calculation using 5bits only the LSByte is
used.
000b* 0000h reset value. Note that this configuration
is set by the Mode detector for FeliCa.
001b 6363h Note that this configuration is set by the
Mode detector for ISO14443 type A.
010b A671h
011b FFFFh Note that this configuration is set by the
Mode detector for ISO14443 type B.
100b
0012h
101b E012h
110b RFU 111b Use arbitrary preset value RX_CRC_
PRESET_VALUE
2
1
RX_CRC_TYPE
RX_CRC_INV
r/w
r/w
0*,1
0*,1
Controls the type of CRC calculation for the Rx-
Decoder 0* 16bit CRC calc
Controls the comparison of the CRC checksum for
the Rx-Decoder
0*: Not inverted CRC value: 0000h reset value.
Note that this bit is cleared by the Mode detector for
ISO14443 type A and FeliCa.
1: Inverted CRC value: F0B8h Note that this bit is set
by the Mode detector for ISO14443 type B
0
RX_CRC_ENABLE
If set. the Rx-Decoder will check the CRC for
correctness.
Note that this bit is set by the Mode Detector when
ISO14443 type B. or FeliCa (212 kBd or 424 kBd) is
detected.
9.23.33 RX_WAIT (0032h)
To guarantee correct protocol timing a guard period timer is implemented for the
RF_EXCHANGE command in reception and transmission mode.
These guard times are not available for Transmit or Receive command.
The guard time RX_WAIT is started after the end of a transmission. The guard time
RX_WAIT can be disabled by setting the register RX_WAIT_VALUE to 00h meaning the
receiver is immediately enabled.
Table 90.ꢀRX_WAIT register (address 0032h) bit description
Bit
Symbol
Access Value
Description
31:28
27:8
RFU
r
0*,1
0*,1
-
RX_WAIT_VALUE
r/w
Defines the rx_wait timer reload value. Note: If set to
00000h the rx_wait guard time is disabled
7:0
RX_WAIT_PRESCALER
r/w
0*,1
Defines the prescaler reload value for the rx_wait
timer.
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9.23.34 RXM_CTRL (0035h)
Table 91.ꢀRXM_CTRL register (address 0035h) bit description
Bit
31:3
2
Symbol
Access Value
Description
RFU
-
RXM_FRQ_CHECK_PCRM_
ENABLE
r/w
r/w
r/w
enable frequency check from PCRM
1
0
RXM_FRQ_CHECK_CORDIC_
ENABLE
enable precise frequency check from cordic phase
(+/- 1.7 MHz multiples)
RXM_ENABLE
enable the all RxMeasure module
9.23.35 SS_TX1_CMCFG (0003Bh)
Table 92.ꢀSS_TX1_CMCFG register (address 003Bh) bit description
Bit
Symbol
Access
Reset
Value
Description
31:22
21:19
18:16
15:8
RFU
rw
rw
rw
rw
rw
0
-
TX1_CLK_MODE_MOD_CM
TX1_CLK_MODE_CW_CM
TX1_AMP_MOD_CM
TX1_AMP_CW_CM
0
TX1 clock mode of modulated wave in CM
TX1 clock mode of unmodulated wave in CM
TX1 clock mode of modulated wave in CM
TX1 clock mode of unmodulated wave in CM
0
0
7:0
0xFF
9.23.36 SS_TX2_CMCFG (0003Ch)
Table 93.ꢀSS_TX2_CMCFG register (address 003Ch) bit description
Bit
Symbol
Access
Reset
Value
Description
31:22
21:19
18:16
15:8
RFU
rw
rw
rw
rw
rw
0
-
TX2_CLK_MODE_MOD_CM
TX2_CLK_MODE_CW_CM
TX2_AMP_MOD_CM
TX2_AMP_CW_CM
0
TX2 clock mode of modulated wave in CM
TX2 clock mode of unmodulated wave in CM
TX2 clock mode of modulated wave in CM
TX2 clock mode of unmodulated wave in CM
0
0
7:0
0xFF
9.23.37 TIMER0_CONFIG (003Dh)
Table 94.ꢀTIMER0_CONFIG register (address 003Dh) bit description
Bit
31:9
8
Symbol
Access Value
Description
RFU
r
0*,1
0*,1
-
T0_START_NOW
r/w
T0_START_EVENT: If set. the timer T0 is started
immediately
7
6
RFU
r
0*,1
0*,1
-
T0_ONE_SHOT_MODE
r/w
When set to 1, the counter value does not reload
again until the counter value has reached zero
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Table 94.ꢀTIMER0_CONFIG register (address 003Dh) bit description ...continued
Bit
Symbol
Access Value
Description
5:3
T0_PRESCALE_SEL
r/w
0*,1
Controls input frequency/period of the timer T0 when
the prescaler is activated in T0_MODE_SEL.
000b - 6.78 MHz counter
001b - 3.39 MHz counter
010b - 1.70 MHz counter
011b - 848 kHz counter
100b - 424 kHz counter
101b - 212 kHz counter
110b - 106 kHz counter
111b - 53 kHz counter
2
1
0
T0_MODE_SEL
T0_RELOAD_ENABLE
T0_ENABLE
r/w
r/w
r/w
0*,1
0*,1
0*,1
Configuration of the timer T0 clock.
0b - Prescaler is disabled: the timer frequency
matches CLIF clock frequency (13.56 MHz).
1b - Prescaler is enabled: the timer operates on
the prescaler signal frequency (chosen by T0_
PRESCALE_SEL).
If set to
0b - the timer T0 will stop on expiration. 0* After
expiration the timer T0 will stop counting. i.e. remain
zero. reset value.
1b - After expiration the timer T0 will reload its preset
value and continue counting down.
Enables the timer T0
9.23.38 TIMER0_RELOAD (003Eh)
Table 95.ꢀTIMER0_RELOAD register (address 003Eh) bit description
Bit
Symbol
Access Value
Description
31:20
19:0
RFU
r
0*,1
0*,1
-
T0_RELOAD_VALUE
r/w
Reload value of the timer T0.
9.23.39 TIMER1_CONFIG (003Fh)
Timer 1 is typically used for the FDT configuration. Configuration can be done from the
host but the associated IRQ is handled by the firmware of the PN5190B1.
Table 96.ꢀTIMER1_CONFIG register (address 003Fh) bit description
Bit
31
30
Symbol
Access Value
Description
RFU
r
0*,1
0*,1
-
T1_STOP_ON_RX_STARTED
r/w
T1_STOP_EVENT: If set. the timer T1 is stopped
when a data reception begins (1st bit is received).
29
28
T1_STOP_ON_TX_STARTED
T1_STOP_ON_RF_ON_EXT
r/w
r/w
0*,1
0*,1
T1_STOP_EVENT: If set. the timer T1 is stopped
when a data transmission begins.
T1_STOP_EVENT: If set. the timer T1 is stopped
when the external RF field is detected.
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Table 96.ꢀTIMER1_CONFIG register (address 003Fh) bit description ...continued
Bit
Symbol
Access Value
Description
27
T1_STOP_ON_RF_OFF_EXT
r/w
r/w
r/w
r/w
0*,1
0*,1
0*,1
0*,1
T1_STOP_EVENT: If set. the timer T1 is stopped
when the external RF field vanishes.
26
25
24
T1_STOP_ON_RF_ON_INT
T1_STOP_ON_RF_OFF_INT
T1_STOP_ON_RX_ENDED
T1_STOP_EVENT: If set. the timer T1 is stopped
when the internal RF field is turned on.
T1_STOP_EVENT: If set. the timer T1 is stopped
when the internal RF field is turned off.
T1_STOP_EVENT: If set the timer T1 is stopped
when an activity on RX is detected.
23:18
17
RFU
r
0*,1
0*,1
-
T1_START_ON_RX_STARTED
r/w
T1_START_EVENT: If set. the timer T1 is started
when a data reception begins (1st bit is received).
16
15
14
13
12
11
10
9
T1_START_ON_RX_ENDED
T1_START_ON_TX_STARTED
T1_START_ON_TX_ENDED
T1_START_ON_RF_ON_EXT
T1_START_ON_RF_OFF_EXT
T1_START_ON_RF_ON_INT
T1_START_ON_RF_OFF_INT
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
0*,1
0*,1
0*,1
0*,1
0*,1
0*,1
0*,1
0*,1
0*,1
T1_START_EVENT: If set. the timer T1 is started
when a data reception ends.
T1_START_EVENT: If set. the timer T1 is started
when a data transmission begins.
T1_START_EVENT: If set. the timer T1 is started
when a data transmission ends.
T1_START_EVENT: If set. the timer T1 is started
when the external RF field is detected.
T1_START_EVENT: If set. the timer T1 is started
when the external RF field is not detected anymore.
T1_START_EVENT: If set. the timer T1 is started
when an internal RF field is turned on.
T1_START_EVENT: If set. the timer T1 is started
when an internal RF field is turned off.
T1_START_ON_TX_
FRAMESTEP
T1_START_EVENT: If set. the timer T1 is started
when an activity on Frame step is detected.
8
T1_START_NOW
T1_START_EVENT: If set. the timer T1 is started
immediately.
7
6
RFU
r
0*,1
0*,1
-
T1_ONE_SHOT_MODE
r/w
When set to 1, the counter value does not reload
again until the counter value has reached zero
5:3
T1_PRESCALE_SEL
r/w
0*,1
Controls input frequency/period of the timer T0 when
the prescaler is activated in T1_MODE_SEL.
000b - 6.78 MHz counter
001b - 3.39 MHz counter
010b - 1.70 MHz counter
011b - 848 kHz counter
100b - 424 kHz counter
101b - 212 kHz counter
110b - 106 kHz counter
111b - 53 kHz counter
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Table 96.ꢀTIMER1_CONFIG register (address 003Fh) bit description ...continued
Bit
Symbol
Access Value
Description
2
T1_MODE_SEL
r/w
0*,1
If set. the timer T1 is started the prescaler for the
timer T1 is enabled. 0* Prescaler is disabled: the
timer frequency matches CLIF clock frequency (13.56
MHz). 1 Prescaler is enabled: the timer operates
on the prescaler signal frequency (chosen by T1_
PRESCALE_SEL).
1
0
T1_RELOAD_ENABLE
T1_ENABLE
r/w
r/w
0*,1
0*,1
If set to 0.the timer T1 will stop on expiration. 0* After
expiration the timer T1 will stop counting. i.e. remain
zero. reset value. 1 After expiration the timer T1 will
reload its preset value and continue counting down.
Enables the timer T1
9.23.40 TIMER1_RELOAD (0040h)
Table 97.ꢀTIMER1_RELOAD register (address 0040h) bit description
Bit
Symbol
Access Value
Description
31:20
19:0
RFU
r
0*,1
0*,1
-
T1_RELOAD_VALUE
r/w
Reload value of the timer T1.
9.23.41 EMD_1_CFG (0047h)
This register allows to configure the ISO14443 and NFC-Forum EMD handling.
This register shall not be modified in case EMVCO or FeliCa EMD is activated.
Table 98.ꢀEMD_1_CFG register (address 0047h) bit description
Bit
Symbol
AccessValue Value
Value
Description
for ISO/ for NFC
IEC14443 Forum
EMD
EMD
handling handling
31:0
EMD_1_Configuration
r/w
0000
0000
0000 FF03h EMD ISO
FF03h
FF04h
0000 FF04h EMD NFC Forum
9.23.42 EMD_0_CONFIG (0048h)
This register allows to configure the ISO14443 and NFC-Forum EMD handling.
This register shall not be modified in case EMVCO or FeliCa EMD is activated.
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Table 99.ꢀEMD_0_CONFIG register (address 0048h) bit description
Bit
Symbol
AccessValue
Value
Value Description
for ISO/ for
IEC14443NFC
EMD
Forum
handling EMD
handling
31:0
EMD_0_Configuration
176003 1F600 Default value for ISO14443 and NFC Forum
FFh 3FFh
9.23.43 LPCD_CALIBRATE_CTRL (00050h)
This register is used for LPCD semi autonomous mode. Writing to this register triggers
the LPCD calibration with the RSSI_HYSTERESIS and RSSI_TARGET values as given
in bits 23:16 and 15:0. After calibration is completed, calibration status is available in
LPCD_CALIBRATE_STATUS. If the calibration is successful, the I/Q channel values can
be read from register IQ_CHANNEL_VALS (51h).
Table 100.ꢀLPCD_CALIBRATE_CTRL register (address 0050h) bit description
Bit
Symbol
Access
Value
0*,1
Description
31:24
23:16
RFU
r
-
RSSI_HYSTERESIS
r/w
0*,1
Value to be set in DGRM_RSSI_HYST used for
calibration
15:0
RSSI_TARGET
r/w
0*,1
Value to be set in DGRM_RSSI_TARGET used for
calibration
9.23.44 IQ_CHANNEL_VALS (00051h)
Table 101.ꢀIQ_CHANNEL_VALS register (address 0051h) bit description
Bit
Symbol
Access
Value
Description
31:16
15:0
Q_CHANNEL_VAL
I_CHANNEL_VAL
r
r
-
-
Q Channel value
I Channel value
9.23.45 PAD_CONFIG (0052h)
Table 102.ꢀPAD_CONFIG register (address 0052h) bit description
Bit
31:7
6
Symbol
Access Value
Description
RFU
RW
RW
-
AUX3_OUTPUT_VAL
Output value for AUX3
0: Low
1: High
5
4
AUX2_OUTPUT_VAL
AUX1_OUTPUT_VAL
RW
RW
Output value for AUX2
0: Low
1: High
Output value for AUX1
0: Low
1: High
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Table 102.ꢀPAD_CONFIG register (address 0052h) bit description...continued
Bit
Symbol
Access Value
Description
3
GPIO3_OUTPUT_VAL
RW
Output value for GPIO3
0: Low
1: High
2
1
0
GPIO2_OUTPUT_VAL
GPIO1_OUTPUT_VAL
GPIO0_OUTPUT_VAL
RW
RW
RW
Output value for GPIO2
0: Low
1: High
Output value for GPIO1
0: Low
1: High
Output value for GPIO0
0: Low
1: High
On PN5190B1 only output functionality is available on GPIO's.
9.23.46 CALIBRATE_STATUS (00053h)
Table 103.ꢀCALIBRATE_STATUS register (address 0053h) bit description
Bit
Symbol
Access
Value
Description
31
LPCD_CALIBRATION_STATUS
r
-
Calibration Status
0 - Calibration Not Done,
1- Calibration Done
30:1
0
RFU
r
-
-
TXNOV_CALIBRATION_STATUS
Calibration Status
0 - Calibration Not Done,
1- Calibration Done
9.23.47 TXLDO_VDDPA_CONFIG (00054h)
If DPC is disabled, the VDDPA supply voltage can be set with this register. These register
settings are overruled by the DPC.
This register does allow to read the actual VDDPA supply voltage independent from
having the DPC enabled/disabled, this allows to read-out the actual transmitter supply
voltage.
Table 104.ꢀTXLDO_VDDPA_CONFIG register (address 0054h) bit description
Bit
Symbol
Access
Value
Description
31:8
RFU
rw
-
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Table 104.ꢀTXLDO_VDDPA_CONFIG register (address 0054h) bit description...continued
Bit
Symbol
Access
Value
Description
7:0
VDDPA CONFIG
rw
VDDPALDO output voltage
VDDPA_1V50 /* 0x00 */ VDDPA_1V60, /* 0x01 */
VDDPA_1V70, /* 0x02 */ VDDPA_1V80, /* 0x03 */
VDDPA_1V90, /* 0x04 */ VDDPA_2V00, /* 0x05 */
VDDPA_2V10, /* 0x06 */ VDDPA_2V20, /* 0x07 */
VDDPA_2V30, /* 0x08 */ VDDPA_2V40, /* 0x09 */
VDDPA_2V50, /* 0x0A */ VDDPA_2V60, /* 0x0B */
VDDPA_2V70, /* 0x0C */ VDDPA_2V80, /* 0x0D */
VDDPA_2V90, /* 0x0E */ VDDPA_3V00, /* 0x0F */
VDDPA_3V10, /* 0x10 */ VDDPA_3V20, /* 0x11 */
VDDPA_3V30, /* 0x12 */ VDDPA_3V40, /* 0x13 */
VDDPA_3V50, /* 0x14 */ VDDPA_3V60, /* 0x15 */
VDDPA_3V70, /* 0x16 */ VDDPA_3V80, /* 0x17 */
VDDPA_3V90, /* 0x18 */ VDDPA_4V00, /* 0x19 */
VDDPA_4V10, /* 0x1A */ VDDPA_4V20, /* 0x1B */
VDDPA_4V30, /* 0x1C */ VDDPA_4V40, /* 0x1D */
VDDPA_4V50, /* 0x1E */ VDDPA_4V60, /* 0x1F */
VDDPA_4V70, /* 0x20 */ VDDPA_4V80, /* 0x21 */
VDDPA_4V90, /* 0x22 */ VDDPA_5V00, /* 0x23 */
VDDPA_5V10, /* 0x24 */ VDDPA_5V20, /* 0x25 */
VDDPA_5V30, /* 0x26 */ VDDPA_5V40, /* 0x27 */
VDDPA_5V50, /* 0x28 */ VDDPA_5V60, /* 0x29 */
VDDPA_5V70, /* 0x2A */
9.23.48 GENERAL_ERROR_STATUS (0055h)
Table 105.ꢀGENERAL_ERROR_STATUS register (address 0055h) bit description
Bit
31:3
2
Symbol
Access Value
Description
RFU
r
r
r
r
0*,1
0*,1
0*,1
0*,1
-
TXLDO_ERROR
CLOCK_ERROR
GPADC_ERROR
TXLDO does not start
XTAL or PLL does not start
GPADC initialization fail
1
0
9.23.49 TXLDO_VOUT_CURR (0056h)
Table 106.ꢀTXLDO_VOUT_CURR register (address 0056h) bit description
Bit
Symbol
Access
Value
Description
31:24
23:8
RFU
r
r
-
TXLDO_CURRENT
Indicates the TXLDO Current, measured value is
indicated in mA (1 bit = 1 mA)
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Table 106.ꢀTXLDO_VOUT_CURR register (address 0056h) bit description...continued
Bit
Symbol
Access
Value
Description
7:0
VDDPA_VOUT
r
VDDPA output voltage
VDDPA_1V50 /* 0x00 */ VDDPA_1V60, /* 0x01 */
VDDPA_1V70, /* 0x02 */ VDDPA_1V80, /* 0x03 */
VDDPA_1V90, /* 0x04 */ VDDPA_2V00, /* 0x05 */
VDDPA_2V10, /* 0x06 */ VDDPA_2V20, /* 0x07 */
VDDPA_2V30, /* 0x08 */ VDDPA_2V40, /* 0x09 */
VDDPA_2V50, /* 0x0A */ VDDPA_2V60, /* 0x0B */
VDDPA_2V70, /* 0x0C */ VDDPA_2V80, /* 0x0D */
VDDPA_2V90, /* 0x0E */ VDDPA_3V00, /* 0x0F */
VDDPA_3V10, /* 0x10 */ VDDPA_3V20, /* 0x11 */
VDDPA_3V30, /* 0x12 */ VDDPA_3V40, /* 0x13 */
VDDPA_3V50, /* 0x14 */ VDDPA_3V60, /* 0x15 */
VDDPA_3V70, /* 0x16 */ VDDPA_3V80, /* 0x17 */
VDDPA_3V90, /* 0x18 */ VDDPA_4V00, /* 0x19 */
VDDPA_4V10, /* 0x1A */ VDDPA_4V20, /* 0x1B */
VDDPA_4V30, /* 0x1C */ VDDPA_4V40, /* 0x1D */
VDDPA_4V50, /* 0x1E */ VDDPA_4V60, /* 0x1F */
VDDPA_4V70, /* 0x20 */ VDDPA_4V80, /* 0x21 */
VDDPA_4V90, /* 0x22 */ VDDPA_5V00, /* 0x23 */
VDDPA_5V10, /* 0x24 */ VDDPA_5V20, /* 0x25 */
VDDPA_5V30, /* 0x26 */ VDDPA_5V40, /* 0x27 */
VDDPA_5V50, /* 0x28 */ VDDPA_5V60, /* 0x29 */
VDDPA_5V70, /* 0x2A */
9.23.50 CLIF_DAC (00057h)
This register allows to configure the output voltage of VTUNE1, VTUNE2.
Table 107.ꢀCLIF_DAC register (address 0057h) bit description
Bit
Symbol
Access
Value
Description
31:28
27:24
RFU
-
TUNING_DAC_2_RANGE
Reference voltage of the DAC, allows to increase the
resolution in case a limited output voltage is required.
For max output voltage, 0x000 need to be configured
(3.8 V)
x111=2 V
x110=3 V
x100=3.45 V
x000=3.8 V
23:17
TUNING_DAC_2_VALUE
Output voltage of DAC2 according to 1/128
*<TUNING_DAC_2_VALUE> * <Range in V>
16
TUNING_DAC_2_PD
RFU
0=DAC Turned off, 1=DAC enabled
-
15:12
11:8
TUNING_DAC_1_RANGE
Reference voltage of the DAC, allows to increase the
resolution in case a limited output voltage is required.
For max output voltage, 0x000 need to be configured
(3.8 V)
x111=2 V, x110=3 V
x100=3.45 V
x000=3.8 V
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Table 107.ꢀCLIF_DAC register (address 0057h) bit description...continued
Bit
Symbol
Access
Value
Description
7:1
TUNING_DAC_1_VALUE
Output voltage of DAC1 according to 1/128 *
<TUNING_DAC_1_VALUE> * <Range in V>
0
TUNING_DAC_1_PD
0=DAC Turned off, 1=DAC enabled
9.23.51 PMU_ANA_SMPS_CTRL_REG (00058h)
Table 108.ꢀPMU_ANA_SMPS_CTRL_REG register (address 0058h) bit description
Bit
Symbol
Access
Value
Description
31:30
29:27
RFU
-
SMPS_MAXDT_SEL
SMPS max duty cycle value, valid when SMPS_
MAX_DTC_BYPASS is set
26
SMPS_MAXDT_SEL_BYPASS
SMPS_GM
SMPS max duty cycle lookup table bypass
25:24
23:22
21:20
19:17
16:14
13:12
SMPS Gm setup
SMPS Rsense setup
SMPS Soft Start setup
SMPS Sawtooth generator setup
-
SMPS_RSENSE
SMPS_SOFT_START
SMPS_SAWTOOTHGEN
RFU
SMPS_PROT_UNDERSHOOT_
VTH
SMPS
11:10
9:7
6:1
0
SMPS_REG_SPARE_0
SMPS_PID
SMPS
SMPS PID filter setup
SMPS Output voltage selection
SMPS enable
SMPS_VDDBOOST_VOUT_SEL
SMPS_EN
9.23.52 RXM_FREQ (00059h)
Table 109.ꢀRXM_FREQ register (address 0059h) bit description
Bit
Symbol
Access
Value
Description
31
RXM_FREQ_REG_VALID
RFU
r
r
r
-
-
-
CLIF_RXM_FREQ_REG fields are valid
-
30:25
24:16
RXM_FREQ
frequence difference between the last two
consecutive measures at 1.7 MHz (multiple of
13.56MHz/4096). Signed. 2-Complement coded
15:9
0:8
RFU
r
r
-
-
-
RXM_PHASE
phase value
9.23.53 RXM_RSSI (0005Ah)
Table 110.ꢀRXM_RSSI register (address 005Ah) bit description
Bit
Symbol
Access
Reset
Value
Description
31
RFU
r
-
-
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Table 110.ꢀRXM_RSSI register (address 005Ah) bit description...continued
Bit
Symbol
Access
Reset
Value
Description
22
RXM_RSSI_FROZEN
RXM_FRQ_OK
r
r
r
r
r
-
-
-
-
-
The RSSI value is not currently updated
The carrier frequency detected is OK.
CLIF_RXM_RSSI_REG fields are valid
HFAtt latched with RSSI
21
20
RXM_RSSI_REG_VALID
RXM_HFATT
19:14
13:0
RXM_RSSI
RSSI value
9.23.54 TEMP_SENSOR (005Bh)
Table 111.ꢀTEMP_SENSOR register (address 005Bh) bit description
Bit
Symbol
Access Value
Description
31:16
15-0
-
R
R
0*,1
0*,1
RFU
TEMP_SENSOR_DATA
Indicates the current temperature of the chip in
degree celsius.
This is the actual temperature data of the sensor
which is used for the overheat protection.
Maximum temperature readable will be the maximum
temperature threshold configured in EEPROM
address 0x14.
9.23.55 TX_NOV_CALIBRATE (005Dh)
Table 112.ꢀTX_NOV_CALIBRATE register (address 005Dh) bit description
Bit
31:30
0
Symbol
Access Value
Description
RFU
RW
RW
0*,1
-
TX_NOV_CALIBRATE_AND_
STORE_VAL
Calibrates the TX NOV and stores the resulting value
in EEPROM
9.23.56 SS_TX1_RTRTRANS0 (00080h)
Table 113.ꢀSS_TX1_RTRTRANS0 register (address 0080h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX1_SS_RTRANS3
TX1_SS_RTRANS2
TX1_SS_RTRANS1
TX1_SS_RTRANS0
TX1 rising transition value 3
TX1 rising transition value 2
TX1 rising transition value 1
TX1 rising transition value 0
rw
rw
rw
9.23.57 SS_TX1_RTRTRANS1 (00081h)
Table 114.ꢀSS_TX1_RTRTRANS1 register (address 0081h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
TX1_SS_RTRANS7
TX1_SS_RTRANS6
TX1 rising transition value 7
TX1 rising transition value 6
rw
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Table 114.ꢀSS_TX1_RTRTRANS1 register (address 0081h) bit description...continued
Bit
Symbol
Access
rw
Value
Description
15:8
7:0
TX1_SS_RTRANS5
TX1_SS_RTRANS4
TX1 rising transition value 5
TX1 rising transition value 4
rw
9.23.58 SS_TX1_RTRTRANS2 (00082h)
Table 115.ꢀSS_TX1_RTRTRANS2 register (address 0082h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX1_SS_RTRANS11
TX1_SS_RTRANS10
TX1_SS_RTRANS9
TX1_SS_RTRANS8
TX1 rising transition value 11
TX1 rising transition value 10
TX1 rising transition value 9
TX1 rising transition value 8
rw
rw
rw
9.23.59 SS_TX1_RTRTRANS3 (00083h)
Table 116.ꢀSS_TX1_RTRTRANS0 register (address 0080h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX1_SS_RTRANS15
TX1_SS_RTRANS14
TX1_SS_RTRANS13
TX1_SS_RTRANS12
TX1 rising transition value 15
TX1 rising transition value 14
TX1 rising transition value 13
TX1 rising transition value 12
rw
rw
rw
9.23.60 SS_TX2_RTRTRANS0 (00084h)
Table 117.ꢀSS_TX2_RTRTRANS0 register (address 00804) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX2_SS_RTRANS3
TX2_SS_RTRANS2
TX2_SS_RTRANS1
TX2_SS_RTRANS0
TX2 rising transition value 3
TX2 rising transition value 2
TX2 rising transition value 1
TX2 rising transition value 0
rw
rw
rw
9.23.61 SS_TX2_RTRTRANS1 (00085h)
Table 118.ꢀSS_TX2_RTRTRANS1 register (address 0085h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX2_SS_RTRANS7
TX2_SS_RTRANS6
TX2_SS_RTRANS5
TX2_SS_RTRANS4
TX2 rising transition value 7
TX2 rising transition value 6
TX2 rising transition value 5
TX2 rising transition value 4
rw
rw
rw
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9.23.62 SS_TX2_RTRTRANS2 (00086h)
Table 119.ꢀSS_TX2_RTRTRANS2 register (address 0086h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX2_SS_RTRANS11
TX2_SS_RTRANS10
TX2_SS_RTRANS9
TX2_SS_RTRANS8
TX2 rising transition value 11
TX2 rising transition value 10
TX2 rising transition value 9
TX2 rising transition value 8
rw
rw
rw
9.23.63 SS_TX2_RTRTRANS3 (00087h)
Table 120.ꢀSS_TX2_RTRTRANS3 register (address 0087h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX2_SS_RTRANS15
TX2_SS_RTRANS14
TX2_SS_RTRANS13
TX2_SS_RTRANS12
TX2 rising transition value 15
TX2 rising transition value 14
TX2 rising transition value 13
TX2 rising transition value 12
rw
rw
rw
9.23.64 SS_TX1_FTRTRANS0 (00088h)
Table 121.ꢀSS_TX1_FTRTRANS0 register (address 0088h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX1_SS_FTRANS3
TX1_SS_FTRANS2
TX1_SS_FTRANS1
TX1_SS_FTRANS0
TX1 falling transition value 3
TX1 falling transition value 2
TX1 falling transition value 1
TX1 falling transition value 0
rw
rw
rw
9.23.65 SS_TX1_FTRTRANS1 (00089h)
Table 122.ꢀSS_TX1_FTRTRANS1 register (address 0089h) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX1_SS_FTRANS7
TX1_SS_FTRANS6
TX1_SS_FTRANS5
TX1_SS_FTRANS4
TX1 falling transition value 7
TX1 falling transition value 6
TX1 falling transition value 5
TX1 falling transition value 4
rw
rw
rw
9.23.66 SS_TX1_FTRTRANS2 (0008Ah)
Table 123.ꢀSS_TX1_FTRTRANS2 register (address 008Ah) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
TX1_SS_FTRANS11
TX1_SS_FTRANS10
TX1_SS_FTRANS9
TX1 rising transition value 11
TX1 rising transition value 10
TX1 rising transition value 9
rw
rw
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Table 123.ꢀSS_TX1_FTRTRANS2 register (address 008Ah) bit description...continued
Bit
Symbol
Access
Value
Description
7:0
TX1_SS_FTRANS8
rw
TX1 rising transition value 8
9.23.67 SS_TX1_FTRTRANS3 (0008Bh)
Table 124.ꢀSS_TX1_FTRTRANS3 register (address 008Bh) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX1_SS_FTRANS15
TX1_SS_FTRANS14
TX1_SS_FTRANS13
TX1_SS_FTRANS12
TX1 rising transition value 15
TX1 rising transition value 14
TX1 rising transition value 13
TX1 rising transition value 12
rw
rw
rw
9.23.68 SS_TX2_FTRTRANS0 (0008Ch)
Table 125.ꢀSS_TX2_FTRTRANS0 register (address 008Ch) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX2_SS_FTRANS3
TX2_SS_FTRANS2
TX2_SS_FTRANS1
TX2_SS_FTRANS0
TX2 falling transition value 3
TX2 falling transition value 2
TX2 falling transition value 1
TX2 falling transition value 0
rw
rw
rw
9.23.69 SS_TX2_FTRTRANS1 (0008Dh)
Table 126.ꢀSS_TX2_FTRTRANS1 register (address 008Dh) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX2_SS_FTRANS7
TX2_SS_FTRANS6
TX2_SS_FTRANS5
TX2_SS_FTRANS4
TX2 falling transition value 7
TX2 falling transition value 6
TX2 falling transition value 5
TX2 falling transition value 4
rw
rw
rw
9.23.70 SS_TX2_FTRTRANS2 (0008Eh)
Table 127.ꢀSS_TX2_FTRTRANS2 register (address 008Eh) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX2_SS_FTRANS11
TX2_SS_FTRANS10
TX2_SS_FTRANS9
TX2_SS_FTRANS8
TX2 falling transition value 11
TX2 falling transition value 10
TX2 falling transition value 9
TX2 falling transition value 8
rw
rw
rw
PN5190B1
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9.23.71 SS_TX2_FTRTRANS3 (0008Fh)
Table 128.ꢀSS_TX2_FTRTRANS3 register (address 008Fh) bit description
Bit
Symbol
Access
rw
Value
Description
31:24
23:16
15:8
7:0
TX2_SS_FTRANS15
TX2_SS_FTRANS14
TX2_SS_FTRANS13
TX2_SS_FTRANS12
TX2 falling transition value 15
TX2 falling transition value 14
TX2 falling transition value 13
TX2 falling transition value 12
rw
rw
rw
9.24 EEPROM configuration description
The settings done in EEPROM are used for basic configuration which does not change
frequently. Typically it is performed once during trimming or configuration of a product.
The EEPROM has a limited number of erase/write cycles that can be performed. This
means, that configurations that change frequently must be performed in standard
registers which do not keep their value during reset and power-off.
This section describes the EEPROM configuration of the PN5190B1.
Writing to the EEPROM has to be performed with Read-Modify-Write for all memory
addresses which contain RFU bits.
9.24.1 EEPROM configuration overview
Table 129.ꢀEEPROM CONFIGURATION REGISTER
Address Name
(HEX)
0
DCDC_PWR_CONFIG
DCDC_CONFIG
1
2
TXLDO_CONFIG
6
TXLDO_VDDPA_HIGH
TXLDO_VDDPA_LOW
TXLDO_VDDPA_MAX_RDR
TXLDO_VDDPA_HIGH_MAX_CARD
BOOST_DEFAULT_VOLTAGE
XTAL_CONFIG
7
8
9
A
10
11
12
13
14
15
16
17
18
XTAL_TIMEOUT
CLK_INPUT_FREQ
XTAL_CHECK_DELAY
TEMP_WARNING
RFU
ENABLE_GPIO0_ON_OVERTEMP
RFU
RFU
PN5190B1
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Table 129.ꢀEEPROM CONFIGURATION REGISTER...continued
Address Name
(HEX)
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RESIDUAL_AMP_LEVEL_A106
EDGE_TYPE_A106
EDGE_STYLE_A106
EDGE_LENGTH_A106
RESIDUAL_AMP_LEVEL_A212
EDGE_TYPE_A212
EDGE_STYLE_A212
EDGE_LENGTH_A212
RESIDUAL_AMP_LEVEL_A424
EDGE_TYPE_A424
EDGE_STYLE_A424
EDGE_LENGTH_A424
RESIDUAL_AMP_LEVEL_A848
EDGE_TYPE_A848
EDGE_STYLE_A848
EDGE_LENGTH_A848
RESIDUAL_AMP_LEVEL_B106
EDGE_TYPE_B106
EDGE_STYLE_B106
EDGE_LENGTH_B106
RESIDUAL_AMP_LEVEL_B212
EDGE_TYPE_B212
EDGE_STYLE_B212
EDGE_LENGTH_B212
RESIDUAL_AMP_LEVEL_B424
EDGE_TYPE_B424
EDGE_STYLE_B424
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Table 129.ꢀEEPROM CONFIGURATION REGISTER...continued
Address Name
(HEX)
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
EDGE_LENGTH_B424
RESIDUAL_AMP_LEVEL_B848
EDGE_TYPE_A848
EDGE_STYLE_A848
EDGE_LENGTH_A848
RESIDUAL_AMP_LEVEL_F212
EDGE_TYPE_F212
EDGE_STYLE_F212
EDGE_LENGTH_F212
RESIDUAL_AMP_LEVEL_F424
EDGE_TYPE_F424
EDGE_STYLE_F424
EDGE_LENGTH_F424
RESIDUAL_AMP_LEVEL_V100_26
EDGE_TYPE_V100_26
EDGE_STYLE_V100_26
EDGE_LENGTH_V100_26
RESIDUAL_AMP_LEVEL_V100_53
EDGE_TYPE_V100_53
EDGE_STYLE_V100_53
EDGE_LENGTH_V100_53
RESIDUAL_AMP_LEVEL_V100_106
EDGE_TYPE_V100_106
EDGE_STYLE_V100_106
EDGE_LENGTH_V100_106
RESIDUAL_AMP_LEVEL_V100_212
EDGE_TYPE_V100_212
EDGE_STYLE_V100_212
EDGE_LENGTH_V100_212
RESIDUAL_AMP_LEVEL_V10_26
EDGE_TYPE_V10_26
EDGE_STYLE_V10_26
EDGE_LENGTH_V10_26
RESIDUAL_AMP_LEVEL_V10_53
EDGE_TYPE_V10_53
EDGE_STYLE_V10_53
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Table 129.ꢀEEPROM CONFIGURATION REGISTER...continued
Address Name
(HEX)
61
62
63
64
65
66
67
68
69
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
79
7A
7B
7C
7D
7E
7F
80
81
EDGE_LENGTH_V10_53
RESIDUAL_AMP_LEVEL_V10_106
EDGE_TYPE_V10_106
EDGE_STYLE_V10_106
EDGE_LENGTH_V10_106
RESIDUAL_AMP_LEVEL_V10_212
EDGE_TYPE_V10_212
EDGE_STYLE_V10_212
EDGE_LENGTH_V10_212
RESIDUAL_AMP_LEVEL_V10_212
EDGE_TYPE_V10_212
EDGE_STYLE_V10_212
EDGE_LENGTH_V10_212
RESIDUAL_AMP_LEVEL_180003m3_tari18p88
EDGE_TYPE_180003m3_tari18p88
EDGE_STYLE_180003m3_tari18p88
EDGE_LENGTH_180003m3_tari18p88
RESIDUAL_AMP_LEVEL_180003m3_tari9p44
EDGE_TYPE_180003m3_tari9p44
EDGE_STYLE_180003m3_tari9p44
EDGE_LENGTH_180003m3_tari9p44
RESIDUAL_AMP_LEVEL_B_PRIME_106
EDGE_TYPE_B_PRIME_106
EDGE_STYLE_B_PRIME_106
EDGE_LENGTH_B_PRIME_106
DPC_CONFIG
DPC_TARGET_CURRENT
DPC_HYSTERESIS_LOADING
RFU
RFU
DPC_HYSTERESIS_UNLOADING
DPC_TXLDOVDDPALow
DPC_TXGSN
DPC_RDON_Control
DPC_InitialRDOn_RFOn
RFU
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Table 129.ꢀEEPROM CONFIGURATION REGISTER...continued
Address Name
(HEX)
83
RFU
85
RFU
87
DPC_GUARD_TIME
DPC_ENABLE_DURING_FDT
DPC_GUARD_TIME_AFTER_RX
RFU
88
89
8A
8B
DPC_LOOKUP_TABLE
ARC_CONFIG
137
139
13E
148
152
15C
166
170
17A
184
18E
198
1A2
1AC
1B6
1C0
1CA
1D4
1DE
1E8
1F2
1FC
206
210
2B2
2B3
2B5
2B8
2B9
ARC_VDDPA
ARC_RM_A106
ARC_RM_A212
ARC_RM_A424
ARC_RM_A848
ARC_RM_B106
ARC_RM_B212
ARC_RM_B424
ARC_RM_B848
ARC_RM_F212
ARC_RM_F424
ARC_RM_V6p6
ARC_RM_V26
ARC_RM_V53
ARC_RM_V106
ARC_RM_V212
ARC_RM_18003m3_SC424_4MAN
ARC_RM_18003m3_SC848_2MAN
ARC_RM_18003m3_SC848_4MAN
ARC_RM_18003m3_SC848_2MAN
ARC_RM_AI106
ARC_RM_AI212
ARC_RM_AI424
RF_DEBOUNCE_TIMEOUT
SENSE_RES
NFC_ID1
SEL_RES
FELICA_POLL_RES
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Table 129.ꢀEEPROM CONFIGURATION REGISTER...continued
Address Name
(HEX)
2CB
2CC
2DA
2DC
2DE
2DF
2E0
3A2
492
494
496
49B
49E
4B5
4BF
4C2
4C6
4C7
4C9
4CA
4CB
4CC
559
55D
561
RANDOM_UID_ENABLE
MFC_AUTH_TIMEOUT
RSSI_TIMER
RSSI_TIMER_FIRST_PERIOD
RSSI_CTRL_00_AB
RSSI_NB_ENTRIES_AB
RSSI_THRESHOLD_PHASE_TABLE
TX_PARAM_ENTRY_TABLE
LPCD_AVG_SAMPLES
LPCD_RSSI_TARGET
LPCD_RSSI_HYST
RFU
LPCD_THRESHOLD
LPCD_VDDPA
ULPCD_VDDPA_CTRL
ULPCD_TIMING_CTRL
ULPCD_VOLTAGE_CTRL
RFU
ULPCD_RSSI_GUARD_TIME
ULPCD_RSSI_SAMPLE_CFG
ULPCD_THRESH_LVL
ULPCD_GPIO3
TXIRQ_GUARDTIME
FDT_DEFAULTVAL
RXIRQ_GUARDTIME
562-6D2 RFU
6D3
NFCLD_RFLD_Valid
6D4-ABB RFU
ABC
CurrentSensorTrimConfig
ABD-BD9 RFU
BDA
C03
C83
C84
C85
C86
CORRECTION_ENTRY_TABLE
RTRANS_FRTANS_TABLE
CFG_NOV_CAL
NOV_CAL_VAL1
NOV_CAL_VAL2
NOV_CAL_THRESHOLD
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Table 129.ꢀEEPROM CONFIGURATION REGISTER...continued
Address Name
(HEX)
C87
C8B
C8F
C9D
NOV_CAL_OFFSET1
NOV_CAL_OFFSET2
VDDPA_DISCHARGE
ARC_RM_A106_FDT
CA8-CC4 RFU
CC5
CC9
CCD
CD1
CD5
CD9
Tx_Symbol23_Mod_Reg_BR_53
Tx_Data_Mod_Reg_BR_53
Tx_Symbol23_Mod_Reg_BR_106
Tx_Data_Mod_Reg_BR_106
Tx_Symbol23_Mod_Reg_BR_212
Tx_Data_Mod_Reg_BR_212
CDDh-14 DO NOT TOUCH OR OVERWRITE, INTERNAL SETTINGS
00h
9.24.2 DCDC_PWR_CONFIG (0000h)
Table 130.ꢀPWR_CONFIG (address 0000h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
0
DC-DC usage in
card mode
7
6
5
0b: DC-DC is not powered and set to bypass
1b: DC-DC is powered and not bypassed
DC-DC usage in
reader mode
0b: DC-DC is not powered and set to bypass
1b: DC-DC is powered and not bypassed
RFU
Do not touch, default value 01b
VUP input voltage 4..0 0x00: Not connected or 0 V
0x01: VUP supplied by PN5190B1 itself (pin VUP_TX connected to VBAT/VBATPWR)
0x02: Internal DC-DC with fixed VDDBOOST
0x04: Internal DC-DC with auto by pass and variable boost w.r.t VDDPA (internal DPC
controls VDDBOOST): DC-DC goes into pass through mode when the VDDPA goes
below 3.3 V. When VDDPA is greater than 3.3 V, the DC-DC is configured to boost
voltage in range of 3.3 V to 6 V.
0x05 - 0x09: RFU
0x10: external supply
9.24.3 DCDC_CONFIG (0001h)
Table 131.ꢀDCDC_CONFIG (address 0001h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
1
DC-DC
7:5 RFU
configuration
PN5190B1
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Table 131.ꢀDCDC_CONFIG (address 0001h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
4
3
DC-DC passthrough feature is:
0: Not supported (Vout = 0v or +5v)
1: Supported (Vout = 0v, Vin or +5v)
Use of DC-DC for LPCD (attention: not ULPCD)
1: enabled
0: disabled
2:0 RFU
9.24.4 TXLDO_CONFIG (0002h)
Table 132.ꢀTXLDO_CONFIG (address 0002h) EEPROM configuration bit description
Address Function
(hex)
Bit
Description
2
TXLDO
Configuration
31:12 RFU
11:10 RFU
9:4
TXLDO output voltage
VDDPA_1V50 /* 0x00 */
VDDPA_1V60, /* 0x01 */
VDDPA_1V70, /* 0x02 */ VDDPA_1V80, /* 0x03 */ VDDPA_1V90, /* 0x04 */ VDDPA_
2V00, /* 0x05 */ VDDPA_2V10, /* 0x06 */ VDDPA_2V20, /* 0x07 */ VDDPA_2V30, /*
0x08 */ VDDPA_2V40, /* 0x09 */ VDDPA_2V50, /* 0x0A */ VDDPA_2V60, /* 0x0B */
VDDPA_2V70, /* 0x0C */ VDDPA_2V80, /* 0x0D */ VDDPA_2V90, /* 0x0E */ VDDPA_
3V00, /* 0x0F */ VDDPA_3V10, /* 0x10 */ VDDPA_3V20, /* 0x11 */ VDDPA_3V30, /
* 0x12 */ VDDPA_3V40, /* 0x13 */ VDDPA_3V50, /* 0x14 */ VDDPA_3V60, /* 0x15 */
VDDPA_3V70, /* 0x16 */ VDDPA_3V80, /* 0x17 */ VDDPA_3V90, /* 0x18 */ VDDPA_
4V00, /* 0x19 */ VDDPA_4V10, /* 0x1A */ VDDPA_4V20, /* 0x1B */ VDDPA_4V30, /*
0x1C */ VDDPA_4V40, /* 0x1D */ VDDPA_4V50, /* 0x1E */ VDDPA_4V60, /* 0x1F */
VDDPA_4V70, /* 0x20 */ VDDPA_4V80, /* 0x21 */ VDDPA_4V90, /* 0x22 */ VDDPA_
5V00, /* 0x23 */ VDDPA_5V10, /* 0x24 */ VDDPA_5V20, /* 0x25 */ VDDPA_5V30, /
* 0x26 */ VDDPA_5V40, /* 0x27 */ VDDPA_5V50, /* 0x28 */ VDDPA_5V60, /* 0x29 */
VDDPA_5V70, /* 0x2A */
3:1
0
RFU
Enable TXLDO
0b: disabled - no voltage output of the TXLDO
1b: enabled - regulated output of the TXLDO according to bits 9:4
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9.24.5 TXLDO_VDDPA_HIGH (0006h)
Table 133.ꢀTXLDO_VDDPA_HIGH (address 0006h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
6
TXLDO output: initial voltage in case the DPC is used. Applies directly at the beginning of 7:0
the RF-field-on before any DPC regulation takes place.
0x00: 1V50
0x01: 1V60
0x02: 1V70
0x03: 1V80
0x04: 1V90
0x05: 2V00
0x06: 2V10
0x07: 2V20
0x08: 2V30
0x09: 2V40
0x0A: 2V50
0x0B: 2V60
0x0C: 2V70
0x0D: 2V80
0x0E: 2V90
0x0F: 3V00
0X10: 3V10
0x11: 3V20
0x12: 3V30
0x13: 3V40
0x14: 3V50
0x15: 3V60
0x16: 3V70
0x17: 3V80
0x18: 3V90
0x19: 4V00
0x1A: 4V10
0x1B: 4V20
0x1C: 4V30
0x1D: 4V40
0x1E: 4V50
0x1F: 4V60
0x20: 4V70
0x21: 4V80
0x22: 4V90
0x23: 5V00
0x24: 5V10
0x25: 5V20
0x26: 5V30
0x27: 5V40
0x28: 5V50
0x29: 5V60
0x2A: 5V70
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9.24.6 TXLDO_VDDPA_LOW (0007h)
Table 134.ꢀTXLDO_VDDPA_LOW (address 0007h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
7:0
7
TXLDO output voltage in case the DPC is disabled and not used.
0x00: 1V50
0x01: 1V60
0x02: 1V70
0x03: 1V80
0x04: 1V90
0x05: 2V00
0x06: 2V10
0x07: 2V20
0x08: 2V30
0x09: 2V40
0x0A: 2V50
0x0B: 2V60
0x0C: 2V70
0x0D: 2V80
0x0E: 2V90
0x0F: 3V00
0X10: 3V10
0x11: 3V20
0x12: 3V30
0x13: 3V40
0x14: 3V50
0x15: 3V60
0x16: 3V70
0x17: 3V80
0x18: 3V90
0x19: 4V00
0x1A: 4V10
0x1B: 4V20
0x1C: 4V30
0x1D: 4V40
0x1E: 4V50
0x1F: 4V60
0x20: 4V70
0x21: 4V80
0x22: 4V90
0x23: 5V00
0x24: 5V10
0x25: 5V20
0x26: 5V30
0x27: 5V40
0x28: 5V50
0x29: 5V60
0x2A: 5V70
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9.24.7 TXLDO_VDDPA_MAX_RDR (0008h)
Table 135.ꢀTXLDO_VDDPA_MAX_RDR (address 0008h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
8
VDDPA maximum output voltage in case the DPC is enabled in reader mode
7:0
0x00: 1V50
0x01: 1V60
0x02: 1V70
0x03: 1V80
0x04: 1V90
0x05: 2V00
0x06: 2V10
0x07: 2V20
0x08: 2V30
0x09: 2V40
0x0A: 2V50
0x0B: 2V60
0x0C: 2V70
0x0D: 2V80
0x0E: 2V90
0x0F: 3V00
0X10: 3V10
0x11: 3V20
0x12: 3V30
0x13: 3V40
0x14: 3V50
0x15: 3V60
0x16: 3V70
0x17: 3V80
0x18: 3V90
0x19: 4V00
0x1A: 4V10
0x1B: 4V20
0x1C: 4V30
0x1D: 4V40
0x1E: 4V50
0x1F: 4V60
0x20: 4V70
0x21: 4V80
0x22: 4V90
0x23: 5V00
0x24: 5V10
0x25: 5V20
0x26: 5V30
0x27: 5V40
0x28: 5V50
0x29: 5V60
0x2A: 5V70
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9.24.8 TXLDO_VDDPA_MAX_CARD (0009h)
Table 136.ꢀTXLDO_VDDPA_MAX_CARD (address 0009h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
9
VDDPA maximum output voltage in case the APC is enabled in card mode
7:0
0x00: 1V50
0x01: 1V60
0x02: 1V70
0x03: 1V80
0x04: 1V90
0x05: 2V00
0x06: 2V10
0x07: 2V20
0x08: 2V30
0x09: 2V40
0x0A: 2V50
0x0B: 2V60
0x0C: 2V70
0x0D: 2V80
0x0E: 2V90
0x0F: 3V00
0X10: 3V10
0x11: 3V20
0x12: 3V30
0x13: 3V40
0x14: 3V50
0x15: 3V60
0x16: 3V70
0x17: 3V80
0x18: 3V90
0x19: 4V00
0x1A: 4V10
0x1B: 4V20
0x1C: 4V30
0x1D: 4V40
0x1E: 4V50
0x1F: 4V60
0x20: 4V70
0x21: 4V80
0x22: 4V90
0x23: 5V00
0x24: 5V10
0x25: 5V20
0x26: 5V30
0x27: 5V40
0x28: 5V50
0x29: 5V60
0x2A: 5V70
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9.24.9 BOOST_DEFAULT_VOLTAGE (000Ah)
Table 137.ꢀBOOST_DEFAULT_VOLTAGE (address 000Ah) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
0A
DC-DC
configuration
7:0 VDDBOOST output voltage in case of DC-DC with fixed VDDBOOST is enabled (PWR_
CONFIG)
0x00: 3.1 V
0x01: 3.2 V
0x02: 3.3 V
0x03: 3.4 V
0x04: 3.5 V
0x05: 3.6 V
0x06: 3.7 V
0x07: 3.8 V
0x08: 3.9 V
0x09: 4.0 V
0x0A: 4.1 V
0x0B: 4.2 V
0x0C: 4.3 V
0x0D: 4.4 V
0x0E: 4.5 V
0x0F: 4.6 V
0x10: 4.7 V
0x11: 4.8 V
0x12: 4.9 V
0x13: 5.0 V
0x14: 5.1 V
0x15: 5.2 V
0x16: 5.3 V
0x17: 5.4 V
0x18: 5.5 V
0x19: 5.6 V
0x1A: 5.7 V
0x1B: 5.8 V
0x1C: 5.9 V
0x1D: 6.0 V
all other values: RFU
9.24.10 XTAL_CONFIG (0010h)
Table 138.ꢀXTAL_CONFIG (address 0010h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
10
Configuration for
7:1 RFU
the XTAL startup
procedure
0
Crystal recalibration start after wake-up from standby
1: enable
0: disable
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9.24.11 XTAL_TIMEOUT (0011h)
Table 139.ꢀXTAL_TIMEOUT (address 0011h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
11
Configuration for
the XTAL startup
procedure
7:0 Timeout for XTAL to be ready (in *128us), if the timeout happens, an XTAL error event
will be raised.
This configuration does not speed up the boot time.
9.24.12 CLK_INPUT_FREQ (0012h)
Table 140.ꢀCLK_INPUT_FREQ (address 0012h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
12
Configuration for
7:4 RFU
the PLL input clock
frequency
3:0 0010b: 24 MHz
0011b: 32 MHz
0100b: 48 MHz
1000b: XTAL 27.12 MHz
All others: RFU
9.24.13 XTAL_CHECK_DELAY (0013h)
Correct Crystal clocking is detected by locking the crystal to the PLL. This allows the
system to start quick independent from the crystal startup time. High-quality crystals
will start up typically fast and allow by this optimized current consumption, e.g, during
ULPCD.
A user needs to find an optimized balance between retry numbers of checking for a
proper locking and the interval for checking for a locked PLL.
This allows to configure a timeout value for locking the crystal to the PLL. The timeout
value is defined by Retry_number x Interval. If the timeout is reached, a clock error is
raised.
Table 141.ꢀXTAL_CHECK_DELAY (address 0013h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
13
Retry_number
Interval
7:5 Max Number of retries before a clock error is raised
4:0 Interval which is used to check if XTAL is ready (unit is 256/fc, e.g. ~18.8 us). This is the
time to try to lock the PLL, a stable crystal clock is required for locking. If the PLL is not
locked, a next retry to lock the PLL will be done after this interval.
This value can be used to optimize the startup time dependent on the crystal
characteristics. This is important, e.g., for optimization of the LPCD and ULPCD.
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9.24.14 TEMP_WARNING (0014h)
Table 142.ꢀTEMP_WARNING (address 0014h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
14
CLIF & PMU
temperature
warning
7:6 PMU high threshold (0: disabled, 1:114degC, 2:125degC, 3:130degC)
5:4 PMU low threshold (0: disabled, 1:114degC, 2:125degC, 3:130degC)
3:2 high threshold (0: disabled, 1:114 °C, 2:125 °C, 3:130 °C) -
in case temp sensor is triggered, transmitter and VDDPALDO are shut down, system
goes in low-power mode - default is 130 °C. This event is not indicated by an IRQ to the
host, instead GPIO0 with configurable high/low polarity is used to indicate this critical
event (Register PAD_CONFIG 0x4B).
To enable this event on GPIO0, the EEPROM register ENABLE_GPIO0_ON_
OVERTEMP (0054h) must be set.
1:0 low threshold (0: disabled, 1:114 °C, 2:125 °C, 3:130 °C) - in case temperature sensed
is lower than threshold, system wakes up from low-power mode, a temp wake-up event
is issued to the host - default is 114 °C. This event is not indicated by an IRQ to the host,
instead GPIO0 with configurable high/low polarity is used to indicate this critical event
(Register PAD_CONFIG 0x52).
To enable this event on GPIO0, the EEPROM register ENABLE_GPIO0_ON_
OVERTEMP (0054h) must be set.
9.24.15 ENABLE_GPIO0_ON_OVERTEMP (0016h)
Table 143.ꢀENABLE_GPIO0_ON_OVERTEMP (address 0016h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
16
RFU
7..1 -
Set/Clear GPIO0
during over
temperature.
0
If set, the GPIO0 is used to indicate a temperature event.
The temperature warning levels are configured in the EEPROM Register TEMP_
WARNING (0048h).
9.24.16 RESIDUAL_AMPL_LEVEL_A106 (0022h)
Table 144.ꢀRESIDUAL_AMPL_LEVEL_A106 (address 0022h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0% carrier
FF: 100% carrier
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9.24.17 EDGE_TYPE_A106 (0023h)
Table 145.ꢀEDGE_TYPE_A106 (address 0023h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.18 EDGE_STYLE_A106 (0024h)
Table 146.ꢀEDGE_STYLE_A106 (address 0024h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
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9.24.19 EDGE_LENGTH_A106 (0025h)
Table 147.ꢀEDGE_LENGTH_A106 (address 0025h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7
Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.20 RESIDUAL_AMPL_LEVEL_A212 (0026h)
Table 148.ꢀRESIDUAL_AMPL_LEVEL_A212 (address 0026h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.21 EDGE_TYPE_A212 (0027h)
Table 149.ꢀEDGE_TYPE_A212 (address 0027h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
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Table 149.ꢀEDGE_TYPE_A212 (address 0027h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.22 EDGE_STYLE_A212 (0028h)
Table 150.ꢀEDGE_STYLE_A212 (address 0028h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.23 EDGE_LENGTH_A212 (0029h)
Table 151.ꢀEDGE_LENGTH_A212 (address 0029h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
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9.24.24 RESIDUAL_AMPL_LEVEL_A424 (002Ah)
Table 152.ꢀRESIDUAL_AMPL_LEVEL_A424 (address 002Ah) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0% carrier
FF: 100% carrier
9.24.25 EDGE_TYPE_A424 (002Bh)
Table 153.ꢀEDGE_TYPE_A424 (address 002Bh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.26 EDGE_STYLE_A424 (002Ch)
Table 154.ꢀEDGE_STYLE_A424 (address 002Ch) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
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Table 154.ꢀEDGE_STYLE_A424 (address 002Ch) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.27 EDGE_LENGTH_A424 (002Dh)
Table 155.ꢀEDGE_LENGTH_A424 (address 002Ch) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.28 RESIDUAL_AMPL_LEVEL_A848 (002Eh)
Table 156.ꢀRESIDUAL_AMPL_LEVEL_A848 (address 002Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
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9.24.29 EDGE_TYPE_A848 (002Fh)
Table 157.ꢀEDGE_TYPE_A848 (address 002Fh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.30 EDGE_STYLE_A848 (0030h)
Table 158.ꢀEDGE_STYLE_A848 (address 0030h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
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9.24.31 EDGE_LENGTH_A848 (0031h)
Table 159.ꢀEDGE_LENGTH_A848 (address 0031h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7
Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.32 RESIDUAL_AMPL_LEVEL_B106 (0032h)
Table 160.ꢀRESIDUAL_AMPL_LEVEL_B106 (address 0032h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.33 EDGE_TYPE_B106 (0033h)
Table 161.ꢀEDGE_TYPE_B106 (address 0033h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
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Table 161.ꢀEDGE_TYPE_B106 (address 0033h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.34 EDGE_STYLE_B106 (0034h)
Table 162.ꢀEDGE_STYLE_B106 (address 0034h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.35 EDGE_LENGTH_B106 (0035h)
Table 163.ꢀEDGE_LENGTH_B106 (address 0035h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
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9.24.36 RESIDUAL_AMPL_LEVEL_B212 (0036h)
Table 164.ꢀRESIDUAL_AMPL_LEVEL_B212 (address 0036h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.37 EDGE_TYPE_B212 (0037h)
Table 165.ꢀEDGE_TYPE_B212 (address 0037h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.38 EDGE_STYLE_B212 (0038h)
Table 166.ꢀEDGE_STYLE_B212 (address 0038h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
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Table 166.ꢀEDGE_STYLE_B212 (address 0038h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.39 EDGE_LENGTH_B212 (0039h)
Table 167.ꢀEDGE_LENGTH_B212 (address 0039h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.40 RESIDUAL_AMPL_LEVEL_B424 (003Ah)
Table 168.ꢀRESIDUAL_AMPL_LEVEL_B424 (address 003Ah) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
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9.24.41 EDGE_TYPE_B424 (003Bh)
Table 169.ꢀEDGE_TYPE_B424 (address 003Bh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.42 EDGE_STYLE_B424 (003Ch)
Table 170.ꢀEDGE_STYLE_B424 (address 003Ch) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1,2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1,2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
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9.24.43 EDGE_LENGTH_B424 (003Dh)
Table 171.ꢀEDGE_LENGTH_B424 (address 003Dh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7
Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.44 RESIDUAL_AMPL_LEVEL_B848 (003Eh)
Table 172.ꢀRESIDUAL_AMPL_LEVEL_B848 (address 003Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.45 EDGE_TYPE_B848 (003Fh)
Table 173.ꢀEDGE_TYPE_B848 (address 003Fh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
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Table 173.ꢀEDGE_TYPE_B848 (address 003Fh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.46 EDGE_STYLE_B848 (0040h)
Table 174.ꢀEDGE_STYLE_B848 (address 0040h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.47 EDGE_LENGTH_B848 (0041h)
Table 175.ꢀEDGE_LENGTH_B848 (address 0041h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
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9.24.48 RESIDUAL_AMPL_LEVEL_F212 (0042h)
Table 176.ꢀRESIDUAL_AMPL_LEVEL_F212 (address 0042h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.49 EDGE_TYPE_F212 (0043h)
Table 177.ꢀEDGE_TYPE_F212 (address 0043h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.50 EDGE_STYLE_F212 (0044h)
Table 178.ꢀEDGE_STYLE_F212 (address 0044h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
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Table 178.ꢀEDGE_STYLE_F212 (address 0044h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.51 EDGE_LENGTH_F212 (0045h)
Table 179.ꢀEDGE_LENGTH_F212 (address 0045h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.52 RESIDUAL_AMPL_LEVEL_F424 (0046h)
Table 180.ꢀRESIDUAL_AMPL_LEVEL_F424 (address 0046h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
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9.24.53 EDGE_TYPE_F424 (0047h)
Table 181.ꢀEDGE_TYPE_F424 (address 0047h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.54 EDGE_STYLE_F424 (0048h)
Table 182.ꢀEDGE_STYLE_F424 (address 0048h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
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9.24.55 EDGE_LENGTH_F424 (0049h)
Table 183.ꢀEDGE_LENGTH_F424 (address 0049h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7
Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.56 RESIDUAL_AMPL_LEVEL_V100_26 (004Ah)
Table 184.ꢀRESIDUAL_AMPL_LEVEL_V100_26 (address 004Ah) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.57 EDGE_TYPE_V100_26 (004Bh)
Table 185.ꢀEDGE_TYPE_V100_26 (address 004Bh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
PN5190B1
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Table 185.ꢀEDGE_TYPE_V100_26 (address 004Bh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.58 EDGE_STYLE_V100_26 (004Ch)
Table 186.ꢀEDGE_STYLE_V100_26 (address 004Ch) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.59 EDGE_LENGTH_V100_26 (004Dh)
Table 187.ꢀEDGE_LENGTH_V100_26 (address 004Dh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
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9.24.60 RESIDUAL_AMPL_LEVEL_V100_53 (004Eh)
Table 188.ꢀRESIDUAL_AMPL_LEVEL_V100_53 (address 004Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.61 EDGE_TYPE_V100_53 (004Fh)
Table 189.ꢀEDGE_TYPE_V100_53 (address 004Fh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.62 EDGE_STYLE_V100_53 (0050h)
Table 190.ꢀEDGE_STYLE_A106 (address 0050h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
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Table 190.ꢀEDGE_STYLE_A106 (address 0050h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.63 EDGE_LENGTH_V100_53 (0051h)
Table 191.ꢀEDGE_LENGTH_V100_53 (address 0051h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.64 RESIDUAL_AMPL_LEVEL_V100_106 (0052h)
Table 192.ꢀRESIDUAL_AMPL_LEVEL_V100_106 (address 0052h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
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9.24.65 EDGE_TYPE_V100_106 (0053h)
Table 193.ꢀEDGE_TYPE_V100_106 (address 0053h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.66 EDGE_STYLE_V100_106 (0054h)
Table 194.ꢀEDGE_STYLE_V100_106 (address 0054h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
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9.24.67 EDGE_LENGTH_V100_106 (0055h)
Table 195.ꢀEDGE_LENGTH_V100_106 (address 0055h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7
Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.68 RESIDUAL_AMPL_LEVEL_100_212 (0056h)
Table 196.ꢀRESIDUAL_AMPL_LEVEL_100_212 (address 0056h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.69 EDGE_TYPE_V100_212 (0057h)
Table 197.ꢀEDGE_TYPE_V100_212 (address 0057h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
PN5190B1
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Table 197.ꢀEDGE_TYPE_V100_212 (address 0057h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.70 EDGE_STYLE_V100_212 (0058h)
Table 198.ꢀEDGE_STYLE_V100_212 (address 0058h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.71 EDGE_LENGTH_V100_212 (0059h)
Table 199.ꢀEDGE_LENGTH_V100_212 (address 0059h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
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9.24.72 RESIDUAL_AMPL_LEVEL_V10_26 (005Ah)
Table 200.ꢀRESIDUAL_AMPL_LEVEL_V10_26 (address 005Ah) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.73 EDGE_TYPE_V10_26 (005Bh)
Table 201.ꢀEDGE_TYPE_V10_26 (address 005Bh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.74 EDGE_STYLE_V10_26 (005Ch)
Table 202.ꢀEDGE_STYLE_V10_26 (address 005Ch) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
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Table 202.ꢀEDGE_STYLE_V10_26 (address 005Ch) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.75 EDGE_LENGTH_V10_26 (005Dh)
Table 203.ꢀEDGE_LENGTH_V10_26 (address 005Dh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.76 RESIDUAL_AMPL_LEVEL_V10_53 (005Eh)
Table 204.ꢀRESIDUAL_AMPL_LEVEL_V10_53 (address 005Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
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9.24.77 EDGE_TYPE_V10_53 (005Fh)
Table 205.ꢀEDGE_TYPE_V10_53 (address 005Fh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.78 EDGE_STYLE_V10_53 (0060h)
Table 206.ꢀEDGE_STYLE_V10_53 (address 0060h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
PN5190B1
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9.24.79 EDGE_LENGTH_V10_53 (0061h)
Table 207.ꢀEDGE_LENGTH_V10_53 (address 0061h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7
Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.80 RESIDUAL_AMPL_LEVEL_V10_106 (0062h)
Table 208.ꢀRESIDUAL_AMPL_LEVEL_V10_106 (address 0062h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.81 EDGE_TYPE_V10_106 (0063h)
Table 209.ꢀEDGE_TYPE_V10_106 (address 0063h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
PN5190B1
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Table 209.ꢀEDGE_TYPE_V10_106 (address 0063h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.82 EDGE_STYLE_V10_106 (0064h)
Table 210.ꢀEDGE_STYLE_V100_212 (address 0064h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.83 EDGE_LENGTH_V10_106 (0065h)
Table 211.ꢀEDGE_LENGTH_V10_106 (address 0065h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
PN5190B1
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9.24.84 RESIDUAL_AMPL_LEVEL_V10_212 (0066h)
Table 212.ꢀRESIDUAL_AMPL_LEVEL_V10_212 (address 0066h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.85 EDGE_TYPE_V10_212 (0067h)
Table 213.ꢀEDGE_TYPE_V10_212 (address 0067h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.86 EDGE_STYLE_V10_212 (0068h)
Table 214.ꢀEDGE_STYLE_V10_212 (address 0068h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
PN5190B1
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Table 214.ꢀEDGE_STYLE_V10_212 (address 0068h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.87 EDGE_LENGTH_V10_212 (0069h)
Table 215.ꢀEDGE_LENGTH_V100_212 (address 0069h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.88 RESIDUAL_AMPL_LEVEL_180003m3_tari18p88 (006Ah)
Table 216.ꢀRESIDUAL_AMPL_LEVEL_180003m3_tari18p88 (address 006Ah) EEPROM configuration bit
description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
PN5190B1
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9.24.89 EDGE_TYPE_180003m3_tari18p88 (006Bh)
Table 217.ꢀEDGE_TYPE_180003m3_tari18p88 (address 006Bh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.90 EDGE_STYLE_180003m3_tari18p88 (006Ch)
Table 218.ꢀEDGE_STYLE_180003m3_tari18p88 (address 006Ch) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
PN5190B1
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9.24.91 EDGE_LENGTH_180003m3_tari18p88 (006Dh)
Table 219.ꢀEDGE_LENGTH_180003m3_tari18p88 (address 006Dh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.92 RESIDUAL_AMPL_LEVEL_180003m3_tari9p44 (006Eh)
Table 220.ꢀRESIDUAL_AMPL_LEVEL_180003m3_tari9p44 (address 006Eh) EEPROM configuration bit
description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.93 EDGE_TYPE_180003m3_tari9p44 (006Fh)
Table 221.ꢀEDGE_TYPE_180003m3_tari9p44 (address 006Fh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
PN5190B1
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Table 221.ꢀEDGE_TYPE_180003m3_tari9p44 (address 006Fh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.94 EDGE_STYLE_180003m3_tari9p44 (0070h)
Table 222.ꢀEDGE_STYLE_180003m3_tari9p44 (address 0070h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.95 EDGE_LENGTH_180003m3_tari9p44 (0071h)
Table 223.ꢀEDGE_LENGTH_180003m3_tari9p44 (address 0071h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
PN5190B1
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9.24.96 RESIDUAL_AMPL_LEVEL_B_PRIME_106 (0072h)
Table 224.ꢀRESIDUAL_AMPL_LEVEL_180003m3_tari18p88 (address 0072h) EEPROM configuration bit
description
AddresFunction
(hex)
Bit Description
22
Transmitter
shaping
configuration
7:0 Residual amplitude level
00: 0 % carrier
FF: 100 % carrier
9.24.97 EDGE_TYPE_B_PRIME_106 (0073h)
Table 225.ꢀEDGE_TYPE_B_PRIME_106 (address 0073h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
23
Transmitter
shaping
configuration
7:4 Definition of edge transition style of falling edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
3:0 Definition of edge transition style of rising edge
Defines style of edge transition:
Firmware based shaping:
1: linear transition between two amplitude levels
2: two linear transitions between amplitude levels
3: three linear transitions between amplitude levels Others: RFU
Lookup table based shaping:
4: lookup table-based transition, no automatic adaptation based on VDDPA
5: lookup table-based transition, automatic adaptation based on VDDPA including
sCorrection
6: lookup table-based transition, automatic adaptation based on VDDPA but no
sCorrection
others: RFU
9.24.98 EDGE_STYLE_B_PRIME_106 (0074h)
Table 226.ꢀEDGE_STYLE_B_PRIME_106 (address 0074h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
24
RFU
7
-
PN5190B1
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Table 226.ꢀEDGE_STYLE_B_PRIME_106 (address 0074h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit Description
Transmitter
shaping
configuration
falling edge
6:4 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of falling edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of falling edge (0,1,2,3)
RFU
3
-
Transmitter
shaping
configuration rising
edge
2:0 If EDGE_TYPE is 1, 2 or 3:
Time constant configuration of rising edge (depends on edge style)
If EDGE_TYPE is 4,5,6:
This number is the lookup table which shall be used of rising edge (0,1,2,3)
9.24.99 EDGE_LENGTH_B_PRIME_106 (0075h)
Table 227.ꢀEDGE_LENGTH_B_PRIME_106 (address 0075h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
25
Transmitter
shaping
7 Scaling of edge transition by factor 2 of rising/falling edge (refers to both rising and falling
edge at the same time)
configuration
0=disabled (1 transition state = one carrier cycle)
1=enabled (1 transition state = two carrier cycles)
6:5 RFU
4:0 Number of active transition states in rising and falling edge pattern (refers to both rising
and falling edge at the same time)
9.24.100 DPC_CONFIG (0076h)
Table 228.ꢀDPC_CONFIG (address 0076h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
76
DPC Configuration 7:3 RFU
2
1
0
DPC in Active Target Mode:
0: disabled,
1: enabled
DPC in Active Initiator Mode:
0: disabled,
1: enabled
DPC in Reader/ Passive Initiator Mode:
0: disabled,
1: enabled
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9.24.101 DPC_TARGET_CURRENT (077h)
Table 229.ꢀDPC_TARGET_CURRENT (address 077h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
77
DPC Configuration 15:0 VDDPA target current in mA. The target current +/- hysteresis defines the limiting
maximum current for the DPC.
This configuration shall not exceed 350 mA - hysteresis.
Note: The resulting current that is driven by the transmitter can be further reduced
based on the current reduction lookup table entries.
9.24.102 DPC_HYSTERESIS_LOADING (079h)
The hysteresis (DPC_HYSTERESIS_LOADING, DPC_HYSTERESIS_UNLOADING)
together with the target current (DPC_TARGET_CURRENT) defines the current limit, at
which the DPC automatically decreases or increases the VDDPA.
The VDDPA is automatically reduced, as soon as the current exceeds the
DPC_TARGET_CURRENT + DPC_HYSTERESIS_LOADING, and the
VDDPA is automatically increased again, as soon as the current is below
DPC_TARGET_CURRENT – DPC_HYSTERESIS_UNLOADING.
Table 230.ꢀDPC_HYSTERESIS_LOADING (address 079h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
79
DPC Configuration 7:0 Absolute difference of measured transmitter current (target current incl. current reduction)
in mA that triggers a DPC update event during loading.
Note: If the hysteresis is configured too small, it might cause an oscillation of the
transmitted field.
Note: In most application, the default values work well and do not need to be modified.
9.24.103 DPC_HYSTERESIS_UNLOADING (07Ch)
The hysteresis (DPC_HYSTERESIS_LOADING, DPC_HYSTERESIS_UNLOADING)
together with the target current (DPC_TARGET_CURRENT) defines the current limit, at
which the DPC automatically decreases or increases the VDDPA.
The VDDPA is automatically reduced, as soon as the current exceeds the
DPC_TARGET_CURRENT + DPC_HYSTERESIS_LOADING, and the
VDDPA is automatically increased again, as soon as the current is below
DPC_TARGET_CURRENT – DPC_HYSTERESIS_UNLOADING.
Table 231.ꢀDPC_HYSTERESIS_UNLOADING (address 07Ch) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
7C
DPC Configuration 7:0 Absolute difference of measured transmitter current (target current incl. current reduction)
in mA that triggers a DPC update event during unloading.
Note: If the hysteresis is configured too small, it might cause an oscillation of the
transmitted field.
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Note: In most application, the default values work well and do not need to be modified.
9.24.104 DPC_TXLDOVDDPALow (007Dh)
Table 232.ꢀDPC_TXLDOVDDPALow (address 007Dh) EEPROM configuration register bit description
AddresFunction
(hex)
Bit Description
7D
DPC Configuration 7:0 VDDPA Low Limit for RDON
9.24.105 DPC_TXGSN (007Eh)
Table 233.ꢀDPC_TXGSN (address 007Eh) EEPROM configuration register bit description
AddresFunction
(hex)
Bit Description
7E
DPC Configuration 7:0 for tx1_gsn < 20: resistance = 10 Ohm / (tx1_gsn + 1)
for tx1_gsn >= 20: resistance = 0.5 Ohm
9.24.106 DPC_RDON_Control (007Fh)
Table 234.ꢀDPC_RDON_Control (address 007Fh) EEPROM configuration register bit description
AddresFunction
(hex)
Bit Description
7F
DPC Configuration 7:0 00: Disabled
01: RdON Control
02-FF: RFU
9.24.107 DPC_InitialRDOn_RFOn (0080h)
Table 235.ꢀDPC_InitialRDOn_RFOn (address 0080h) EEPROM configuration register bit description
AddresFunction
(hex)
Bit Description
80
DPC Configuration 7:0 Initial GSP TX1/TX2 value during FieldON
9.24.108 DPC_GUARD_TIME (087h)
Table 236.ꢀDPC_GUARD_TIME (address 087h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
87
DPC guard time
configuration
7:0 Guard time before TX and after RX. 1unit = 1us.
The DPC regulation is done once before TX and once after RX.
The guard time parameter is the time between DPC regulation completion and TX start.
The guard time parameter is the time between RX stop and DPC regulation start.
The guard time is always enabled for TX
Note: Recommendation is not to modify the default value.
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9.24.109 DPC_ENABLE_DURING_FDT (088h)
Table 237.ꢀDPC_ENABLE_DURING_FDT (address 088h) EEPROM configuration bit description
AddresFunction
Bit Description
(hex)
88
DPC Configuration 7 DPC regulation enable during FDT
0: DPC disabled during FDT (debug purpose only)
1: DPC enabled during FDT (recommendation)
9.24.110 DPC_GUARD_TIME_AFTER_RX (089h)
Table 238.ꢀDPC_GUARD_TIME_AFTER_RX (address 089h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
89
89
RFU
7:1 -
DPC Configuration 0
Enable DPC guard time after RX
0: disable (debug purposes)
1: enable (recommended)
The guard time can be configured in register DPC_GUARD_TIME
Note: The guard time is always enabled for TX and cannot be disabled.
9.24.111 DPC_LOOKUP_TABLE (008Bh-0133h)
Table 239.ꢀDPC_LOOKUP_TABLE (008Bh-0133h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
ENTRY 0
31:0
This is the entry for 1.5 V
ENTRY 0 -LSB - byte 0
08B
Target current
reduction
31:23
Voltage step between DPC entries = 100 mV. Voltage offset start = 1.5 V bEntry_00 =
1V5 ... bEntry_42 = 5V7
Bits[7:0] = Target current reduction in mA (unsigned)
08C
08D
AWC amp mod
change
23:16 ENTRY 0 - byte 1
Bits[7:0] = Relative change of modulated amplitude level (signed)
15:8 ENTRY 0 - byte 2
AWC edge time
constant for
ASK100
Bits[3:0] = ASK100, Relative change of falling edge time constant (signed)
Bits[7:4] = ASK100, Relative change of rising edge time constant (signed)
08E
AWC falling edge 7:0
time constant for
ASK10
ENTRY 0 -MSB - byte 4
Bits[3:0] = ASK10, Relative change of falling edge time constant (signed)
Bits[7:4] = ASK10, Relative change of rising edge time constant (signed)
08F
….
ENTRY 1
31:0
This is the entry for 1.6 V
….
093
…..
….
ENTRY 2
31:0
31:0
This is the entry for 1.7 V
….
This is the entry for 5.6 V
This is the entry for 5.7 V
0133 ENTRY 42
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9.24.112 ARC_CONFIG (0137h)
Table 240.ꢀARC_CONFIG (address 0137h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
137
ARC Setting
configuration
7 ARC algorithm enable
0: Disable
1: Enable
6:3 RFU
2:0 Number of entries in ARC table. (value between 0 to 4)
0: one entry
1: two entries
2: three entries
3: four entries
4: five entries
9.24.113 ARC_VDDPA (0139h)
Table 241.ꢀARC_VDDPA (0139Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
13D
13C
13B
13A
139
VDDPA_4
VDDPA_3
VDDPA_2
VDDPA_1
VDDPA_0
7:0 Byte[4] = VDDPA range_index 4: if VDDPA voltage between VDDPA_3 to ARC_VDDPA_
4
7:0 Byte[3] = VDDPA_range_index 3: if VDDPA voltage between VDDPA_2 to ARC_VDDPA_
3 - 0.1
7:0 Byte[2] = VDDPA_range_index 2: if VDDPA voltage between VDDPA_1 to ARC_VDDPA_
2 - 0.1
7:0 Byte[1] = VDDPA_range_index 1: if VDDPA voltage between VDDPA_0 to (ARC_
VDDPA_1 - 0.1)
7:0 Byte[0] = VDDPA_range_index 0: if VDDPA voltage between 1.5 to (VDDPA_0 - 0.1)
Note: VDDPA setting for Bytes 0...4:
0x00: 1V50
0x01: 1V60
0x02: 1V70
0x03: 1V80
0x04: 1V90
0x05: 2V00
0x06: 2V10
0x07: 2V20
0x08: 2V30
0x09: 2V40
0x0A: 2V50
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0x0B: 2V60
0x0C: 2V70
0x0D: 2V80
0x0E: 2V90
0x0F: 3V00
0X10: 3V10
0x11: 3V20
0x12: 3V30
0x13: 3V40
0x14: 3V50
0x15: 3V60
0x16: 3V70
0x17: 3V80
0x18: 3V90
0x19: 4V00
0x1A: 4V10
0x1B: 4V20
0x1C: 4V30
0x1D: 4V40
0x1E: 4V50
0x1F: 4V60
0x20: 4V70
0x21: 4V80
0x22: 4V90
0x23: 5V00
0x24: 5V10
0x25: 5V20
0x26: 5V30
0x27: 5V40
0x28: 5V50
0x29: 5V60
0x2A: 5V70
9.24.114 ARC_RM_A106 (013Eh)
This is the setting for type A-106.
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Table 242.ꢀARC_RM_A106 (address 013Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
146
144
142
140
RM_RX_ARC_4
15:0 Bit[15]
This setting is only taken into account if bit 14 of address 13E is set.
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits
0..9 of table ARC_RM_A106 are used
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0 Bit[15]
This setting is only taken into account if bit 14 of address 13E is set.
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits
0..9 of table ARC_RM_A106 are used
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
15:0 Bit[15]
This setting is only taken into account if bit 14 of address 13E is set.
0: ARC settings always apply, bits 0...9 from the table ARC_RM_106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits
0..9 of table ARC_RM_A106 are used
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
15:0 Bit[15]
This setting is only taken into account if bit 14 of address 13E is set.
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits
0..9 of table ARC_RM_A106 are used
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 242.ꢀARC_RM_A106 (address 013Eh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
13E
RM_RX_ARC_0
15:0 Bit[15]
This setting is only taken into account if bit 14 of address 13E is set.
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A106_FDT are used, else bits
0..9 of table ARC_RM_A106 are used
Bit [14]:
1: ARC enabled for this Tech and Baudrate.
0: ARC disabled for this Tech and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
9.24.115 ARC_RM_A212 (0148h)
This is the setting for type A-212.
Table 243.ꢀARC_RM_A212 (address 0148h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
150
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
14E
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 243.ꢀARC_RM_A212 (address 0148h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
14C
14A
148
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.116 ARC_RM_A424 (0152h)
This is the setting for type A-424.
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Table 244.ꢀARC_RM_A424 (address 0152h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
15A
RM_RX_ARC_4
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A424 are used, else settings
will be used from LoadProtocol A424
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and
Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
158
156
154
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A424 are used, else settings
will be used from LoadProtocol A424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A424 are used, else settings
will be used from LoadProtocol A424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A424 are used, else settings
will be used from LoadProtocol A424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 244.ꢀARC_RM_A424 (address 0152h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
152
RM_RX_ARC_0
15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.117 ARC_RM_A848 (015Ch)
This is the setting for type A-848.
Table 245.ꢀARC_RM_A848 (address 015Ch) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
164
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A848 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A848 are used, else settings
will be used from LoadProtocol A848
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
162
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A848 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A848 are used, else settings
will be used from LoadProtocol A848
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 245.ꢀARC_RM_A848 (address 015Ch) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
160
15E
15C
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A848 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A848 are used, else settings
will be used from LoadProtocol A848
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A848 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A848 are used, else settings
will be used from LoadProtocol A848
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.118 ARC_RM_B106 (0166h)
This is the setting for type B-106.
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Table 246.ꢀARC_RM_B106 (address 0166h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
16E
16C
16A
168
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B106 are used, else settings
will be used from LoadProtocol B106
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0
15:0
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B106 are used, else settings
will be used from LoadProtocol B106
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B106 are used, else settings
will be used from LoadProtocol B106
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B106 are used, else settings
will be used from LoadProtocol B106
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 246.ꢀARC_RM_B106 (address 0166h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
166
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.119 ARC_RM_B212 (0170h)
This is the setting for type B-212.
Table 247.ꢀARC_RM_B212 (address 0170h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
178
RM_RX_ARC_4
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B212 are used, else settings
will be used from LoadProtocol B212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
176
RM_RX_ARC_3
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B212 are used, else settings
will be used from LoadProtocol B212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 247.ꢀARC_RM_B212 (address 0170h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
174
172
170
RM_RX_ARC_2
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B212 are used, else settings
will be used from LoadProtocol B212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B212 are used, else settings
will be used from LoadProtocol B212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and
Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.120 ARC_RM_B424 (017Ah)
This is the setting for type B-424.
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Table 248.ꢀARC_RM_B424 (address 017Ah) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
182
180
17E
17C
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0
15:0
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 248.ꢀARC_RM_B424 (address 017Ah) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
17A
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.121 ARC_RM_B848 (0184h)
This is the setting for type B-848.
Table 249.ꢀARC_RM_B848 (address 0184h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
18C
RM_RX_ARC_4
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B848 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B848 are used, else settings
will be used from LoadProtocol B848
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
18A
RM_RX_ARC_3
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B848 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B848 are used, else settings
will be used from LoadProtocol B848
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 249.ꢀARC_RM_B848 (address 0184h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
188
186
184
RM_RX_ARC_2
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B848 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B848 are used, else settings
will be used from LoadProtocol B848
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_B848 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_B848 are used, else settings
will be used from LoadProtocol B848
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and
Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.122 ARC_RM_F212 (018Eh)
This is the setting for type F-212.
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Table 250.ꢀARC_RM_F212 (address 018Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
196
194
192
190
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_F212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_F212 are used, else settings
will be used from LoadProtocol F212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0
15:0
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_F212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_F212 are used, else settings
will be used from LoadProtocol F212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_F212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_F212 are used, else settings
will be used from LoadProtocol F212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_F212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_F212 are used, else settings
will be used from LoadProtocol F212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 250.ꢀARC_RM_F212 (address 018Eh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
18E
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.123 ARC_RM_F424 (0198h)
This is the setting for type F-424.
Table 251.ꢀARC_RM_F424 (address 0198h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1A0
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_F424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_F424 are used, else settings
will be used from LoadProtocol F424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
19E
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_F424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_F424 are used, else settings
will be used from LoadProtocol F424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 251.ꢀARC_RM_F424 (address 0198h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
19C
19A
198
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_F424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_F424 are used, else settings
will be used from LoadProtocol F424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_F424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_F424 are used, else settings
will be used from LoadProtocol F424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.124 ARC_RM_V_6p6 (01A2h)
This is the setting for type A-106.
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Table 252.ꢀARC_RM_V_6p6 (address 01A2h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1AA
1A8
1A6
1A4
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V6P6 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V6P6 are used, else settings
will be used from LoadProtocol V6P6
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0
15:0
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V6P6 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V6P6 are used, else settings
will be used from LoadProtocol V6P6
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V6P6 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V6P6 are used, else settings
will be used from LoadProtocol V6P6
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V6P6 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V6P6 are used, else settings
will be used from LoadProtocol V6P6
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 252.ꢀARC_RM_V_6p6 (address 01A2h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1A2
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.125 ARC_RM_V_26 (01ACh)
This is the setting for type V 26.
Table 253.ꢀARC_RM_V_26 (address 01ACh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1B4
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V26 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V26 are used, else settings
will be used from LoadProtocol V26
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
1B2
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V26 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V26 are used, else settings
will be used from LoadProtocol V26
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 253.ꢀARC_RM_V_26 (address 01ACh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1B0
1AE
1AC
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V26 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V26 are used, else settings
will be used from LoadProtocol V26
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V26 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V26 are used, else settings
will be used from LoadProtocol V26
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.126 ARC_RM_V53 (01B6h)
This is the setting for type V53.
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Table 254.ꢀARC_RM_V53(address 01B6h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1BE
1BC
1BA
1B8
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V53 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V53 are used, else settings
will be used from LoadProtocol V53
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0
15:0
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V53 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V53 are used, else settings
will be used from LoadProtocol V53
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V53 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V53 are used, else settings
will be used from LoadProtocol V53
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V53 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V53 are used, else settings
will be used from LoadProtocol V53
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 254.ꢀARC_RM_V53(address 01B6h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1B6
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.127 ARC_RM_V106 (01C0h)
This is the setting for type V106.
Table 255.ꢀARC_RM_V106(address 01C0h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1C8
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
1C6
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 255.ꢀARC_RM_V106(address 01C0h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1C4
1C2
1C0
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_A212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_A212 are used, else settings
will be used from LoadProtocol A212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.128 ARC_RM_V212 (01CAh)
This is the setting for type V212.
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Table 256.ꢀARC_RM_V212(address 01CAh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1D2
1D0
1CE
1CC
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V212 are used, else settings
will be used from LoadProtocol V212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0
15:0
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V212 are used, else settings
will be used from LoadProtocol V212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V212 are used, else settings
will be used from LoadProtocol V212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_V212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_V212 are used, else settings
will be used from LoadProtocol V212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 256.ꢀARC_RM_V212(address 01CAh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1CA
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.129 ARC_RM_180003m3_SC424_4Man (01D4h)
This is the setting for type 180003m3_SC424_4Man.
Table 257.ꢀARC_RM_180003m3_SC424_4Man (address 01D4h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1DC
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_
4MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_4MAN
are used, else settings will be used from LoadProtocol 180003M3_SC424_4MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
1DA
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_
4MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_4MAN
are used, else settings will be used from LoadProtocol 180003M3_SC424_4MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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NFC frontend
Table 257.ꢀARC_RM_180003m3_SC424_4Man (address 01D4h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1D8
1D6
1D4
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_
4MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_4MAN
are used, else settings will be used from LoadProtocol 180003M3_SC424_4MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_
4MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_4MAN
are used, else settings will be used from LoadProtocol 180003M3_SC424_4MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.130 ARC_RM_180003m3_SC424_2Man (01DEh)
This is the setting for type 180003m3_SC424_2Man.
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Table 258.ꢀARC_RM_180003m3_SC424_2Man (address 01DEh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1E6
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_
2MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_2MAN are
used, else settings will be used from LoadProtocol 180003M3_SC424_2MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
1E4
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_
2MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_2MAN are
used, else settings will be used from LoadProtocol 180003M3_SC424_2MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
1E2
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_
2MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_2MAN are
used, else settings will be used from LoadProtocol 180003M3_SC424_2MAN
Bits[14:9] = RFU
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
1E0
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC424_
2MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC424_2MAN are
used, else settings will be used from LoadProtocol 180003M3_SC424_2MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 258.ꢀARC_RM_180003m3_SC424_2Man (address 01DEh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1DE
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and
Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.131 ARC_RM_180003m3_SC848_4Man (01E8h)
This is the setting for type 180003m3_SC848_4Man.
Table 259.ꢀARC_RM_180003m3_SC848_4Man (address 01E8h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1F0
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_
4MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_4MAN
are used, else settings will be used from LoadProtocol 180003M3_SC848_4MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
1EE
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_
4MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_4MAN
are used, else settings will be used from LoadProtocol 180003M3_SC848_4MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 259.ꢀARC_RM_180003m3_SC848_4Man (address 01E8h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1EC
1EA
1E8
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_
4MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_4MAN
are used, else settings will be used from LoadProtocol 180003M3_SC848_4MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_
4MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_4MAN
are used, else settings will be used from LoadProtocol 180003M3_SC848_4MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.132 ARC_RM_180003m3_SC848_2Man (01F2h)
This is the setting for type 180003m3_SC848_2Man.
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Table 260.ꢀARC_RM_180003m3_SC848_2Man (address 01F2h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
1FA
1F8
1F6
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_
2MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_2MAN are
used, else settings will be used from LoadProtocol 180003M3_SC848_2MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_
2MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_2MAN are
used, else settings will be used from LoadProtocol 180003M3_SC848_2MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_
2MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_2MAN are
used, else settings will be used from LoadProtocol 180003M3_SC848_2MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
1F4
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_180003M3_SC848_
2MAN are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_180003M3_SC848_2MAN are
used, else settings will be used from LoadProtocol 180003M3_SC848_2MAN
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 260.ꢀARC_RM_180003m3_SC848_2Man (address 01F2h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
1F2
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and
Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.133 ARC_RM_AI106 (01FCh)
This is the setting for type AI106.
Table 261.ꢀARC_RM_AI106 (address 01FCh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
204
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI106 are used, else settings
will be used from LoadProtocol AI106
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
202
RM_RX_ARC_3
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI106 are used, else settings
will be used from LoadProtocol AI106
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 261.ꢀARC_RM_AI106 (address 01FCh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
200
1FE
1FC
RM_RX_ARC_2
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI106 are used, else settings
will be used from LoadProtocol AI106
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI106 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI106 are used, else settings
will be used from LoadProtocol AI106
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.134 ARC_RM_AI212 (0206h)
This is the setting for type AI212.
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Table 262.ꢀARC_RM_AI212 (0206h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
20E
20C
20A
208
RM_RX_ARC_4
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI212 are used, else settings
will be used from LoadProtocol AI212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_3
RM_RX_ARC_2
RM_RX_ARC_1
15:0
15:0
15:0
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI212 are used, else settings
will be used from LoadProtocol AI212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI212 are used, else settings
will be used from LoadProtocol AI212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI212 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI212 are used, else settings
will be used from LoadProtocol AI212
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 262.ꢀARC_RM_AI212 (0206h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
206
RM_RX_ARC_0
15:0
Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech
and Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.135 ARC_RM_AI424 (0210h)
This is the setting for type AI424.
Table 263.ꢀARC_RM_AI424 (0210h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
218
RM_RX_ARC_4
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI424 are used, else settings
will be used from LoadProtocol AI424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
216
RM_RX_ARC_3
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI424 are used, else settings
will be used from LoadProtocol AI424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
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Table 263.ꢀARC_RM_AI424 (0210h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
214
212
210
RM_RX_ARC_2
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI424 are used, else settings
will be used from LoadProtocol AI424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_1
15:0 Bit[15]
0: ARC settings always apply, bits 0...9 from the table ARC_RM_AI424 are used
1: ARC settings during FDT, bits 0..9 of table ARC_RM_AI424 are used, else settings
will be used from LoadProtocol AI424
Bits[14:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_0
15:0 Bit[15]
0: ARC settings always apply
1: ARC settings applicable during FDT and DPC change
Bit [14]: 1: ARC Enabled for this Tech and Baudrate. 0: ARC disabled for this Tech and
Baudrate
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
Note: Bit15 of all RM_RX_ARC_n is recommended to be "0" always.
9.24.136 RF_DEBOUNCE_TIMEOUT (02B2h)
Table 264.ꢀRF_DEBOUNCE_TIMEOUT (address 02B2h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
2B2
DEBOUNCE_
TIMEOUT
7:0 Timeout used after the RF detection during the AUTOCOLL to detect if there is a glitch or
continuous RF
Value is entered in micro seconds, each bit represents 1 micro second
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9.24.137 SENSE_RES (02B3h)
Table 265.ꢀSENSE_RES (address 02B3) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
2B3
AUTOCOLL
configuration
16:0
ATQA in order byte 0, byte 1
16:8
7:0
Byte1
Byte0
9.24.138 NFC_ID1 (02B5h)
Table 266.ꢀSIGNAL_SCALING_CONFIG (address 2B5h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
2B5
AUTOCOLL
configuration
If Random UID is disabled (EEPROM address 0x2CB), the content of these
addresses is used to generate a Fixed UID.
The order is byte 0, Byte 1, Byte 2; Byte3 - which is the first NFCID1 byte - is fixed to
08h, the check byte is calculated automatically
23:16
15:8
7:0
Byte2
Byte1:
Byte0:
9.24.139 SEL_RES (02B8h)
Table 267.ꢀSEL_RES (address 2B8h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
2B8
AUTOCOLL
configuration
7:0 Response to Select: SAK
9.24.140 FELICA_POLL_RES (02B9h)
The FeliCa response is configured by 18 bytes.
Table 268.ꢀFELICA_POLL_RES (address 02B9) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
2B9
AUTOCOLL
configuration
15:0
FeliCa Polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad
+ 2 bytes system code)
47:0
63:0
15:0
NFCID2
PAD
system code
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9.24.141 RANDOM_UID_ENABLE (02CBh)
Table 269.ꢀRANDOM_UID_ENABLE (address 2CBh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
2CB
RFU
7:1
0
-
Random UID
Enable
0: Use UID stored in EEPROM
1: Randomly generate the UID in which the first byte is fixed and the remaining 3
bytes are random
A new random number is generated after each RF-OFF to RF-ON.
9.24.142 MFC_AUTH_TIMEOUT (02CCh)
Table 270.ꢀMFC_AUTH_TIMEOUT (address 2CCh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
2CC
RFU
15:0
Timeout value in micro seconds used for Auth1 & Auth2 stages during MIFARE
Classic Authenticate
9.24.143 RSSI_TIMER (02DAh)
Configuration for Card Emulation mode only.
Table 271.ꢀRSSI_TIMER (address 2DAh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
2DA
RSSI_TIMER
15:0
Default: 423
9.24.144 RSSI_TIMER_FIRST_PERIOD (02DCh)
Table 272.ꢀRSSI_TIMER_FIRST_PERIOD (address 2DCh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
2DC
RSSI
15:0 First period duration after Rffield ON. Unit is 128/fc (106 kHz) if set to 0 it means that
feature is not used 0D2 => ~2 ms
9.24.145 RSSI_CTRL_00_AB (02DEh)
Table 273.ꢀRSSI_CTRL_00_AB (address 2DEh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
2DE
RSSI
7:6
5:0
Bits [6:7] = RFU
Bits [0:5] = (APC_ID_REF_AB) ID of APC_TX entry that is equiv to RSSI = 0 (for Type
AB)
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9.24.146 RSSI_NB_ENTRIES_AB (02DFh)
Table 274.ꢀRSSI_NB_ENTRIES_AB (address 2DFh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
2DF
RSSI
7:5 RFU
4:0 For Initial RF ON, CEA and CEB
Number of entries in RSSI lookup table (it refers to dwRssiEntryAB_01 to
dwRssiEntryAB_X);
9.24.147 RSSI_THRESHOLD_PHASE_TABLE (02E0h)
Table 275.ꢀRSSI_THRESHOLD_PHASE_TABLE (address 2E0h) EEPROM configuration bit description
Address Function
(hex)
Bit
Description
2E0
wRssiThresholdF_01 15:0
bit[0:12] - RSSI Value
bit[13:15] - RFU Note: dwRssiEntryAB_00 = 0 (not in EEPROM) Signed phase
compensation with 1/4 degree resolution: 16 bits signed value (using complement
of 2)
2E2
ArbPhaseF_01
15:0
wArbPhaseF_xx: Signed phase compensation with 1/4 degree resolution: 16 bits
signed value (using complement of 2)
RssiThresholdF_02 15:0
ArbPhaseF_02 15:0
RssiThresholdF_03 15:0
ArbPhaseF_03 15:0
RssiThresholdF_04 15:0
ArbPhaseF_04 15:0
RssiThresholdF_05 15:0
ArbPhaseF_05 15:0
RssiThresholdF_06 15:0
ArbPhaseF_06 15:0
RssiThresholdF_07 15:0
ArbPhaseF_07 15:0
RssiThresholdF_08 15:0
ArbPhaseF_08 15:0
RssiThresholdF_09 15:0
ArbPhaseF_09 15:0
RssiThresholdF_0A 15:0
ArbPhaseF_0A 15:0
RssiThresholdF_0B 15:0
ArbPhaseF_0B 15:0
RssiThresholdF_0C 15:0
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Table 275.ꢀRSSI_THRESHOLD_PHASE_TABLE (address 2E0h) EEPROM configuration bit description...continued
Address Function
(hex)
Bit
Description
ArbPhaseF_0C
15:0
RssiThresholdF_0D 15:0
ArbPhaseF_0D 15:0
RssiThresholdF_0E 15:0
ArbPhaseF_0E 15:0
RssiThresholdF_0F 15:0
ArbPhaseF_0F 15:0
RssiThresholdF_10 15:0
ArbPhaseF_10 15:0
RssiThresholdF_11 15:0
ArbPhaseF_11 15:0
RssiThresholdF_12 15:0
ArbPhaseF_12 15:0
RssiThresholdF_13 15:0
ArbPhaseF_13 15:0
RssiThresholdF_14 15:0
ArbPhaseF_14 15:0
RssiThresholdF_15 15:0
ArbPhaseF_15 15:0
RssiThresholdF_16 15:0
ArbPhaseF_16 15:0
RssiThresholdF_17 15:0
ArbPhaseF_17 15:0
RssiThresholdF_18 15:0
ArbPhaseF_18 15:0
9.24.148 TX_PARAM_ENTRY_TABLE (03A2h)
Table 276.ꢀTX_PARAM_ENTRY_TABLE (address 3A2h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
3A2
TxParamEntry_00_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
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Table 276.ꢀTX_PARAM_ENTRY_TABLE (address 3A2h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
bTxParamEntry_00_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_00_Tx2 7:0
3A5
3A8
3AB
TxParamEntry_01_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_01_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_01_Tx2 7:0
TxParamEntry_02_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_02_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_02_Tx2 7:0
TxParamEntry_03_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_03_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_03_Tx2 7:0
3AE
TxParamEntry_04_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
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Table 276.ꢀTX_PARAM_ENTRY_TABLE (address 3A2h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
bTxParamEntry_04_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_04_Tx2 7:0
3B1
3B4
3B7
TxParamEntry_05_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_05_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_05_Tx2 7:0
TxParamEntry_06_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_06_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_06_Tx2 7:0
TxParamEntry_07_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_07_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_07_Tx2 7:0
3BA
TxParamEntry_08_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
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Table 276.ꢀTX_PARAM_ENTRY_TABLE (address 3A2h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
bTxParamEntry_08_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_08_Tx2 7:0
3BD
3C1
3C3
TxParamEntry_09_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_09_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_09_Tx2 7:0
TxParamEntry_0A_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_0A_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_0A_Tx2 7:0
TxParamEntry_0B_ID
7
bit[7] Driver count (CLIF_TX_CONTROL_REG.TX_ALM_TYPE_SELECT):
0 - Dual driver,
1 - Single driver
6
BPSK mode (CLIF_TX_CONTROL_REG.TX_ALM_BPSK_ENABLE):
0 - Disabled,
1 - Enabled
5:0
ID
bTxParamEntry_0B_Tx1 7:6
5:0
RFU
PMU VDDPA setting: VDDPA(v) = (val*10)+1,5 0 = 1.50 V ... 2Ah = 5.70 V
Scaling factor for TX1 and TX2
bTxParamEntry_0B_Tx2 7:0
9.24.149 LPCD_AVG_SAMPLES (0492h)
Configuration for the Switch mode LPCD
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Table 277.ꢀLPCD_AVG_SAMPLES (address 0492h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
492
LPCD setting
7 Defining how many samples of the I and Q values are used for the averaging.
Average of samples in power of 2
0->1 sample
1->2 samples
2->4 samples
3->8 samples
4->16 samples
5-> 32 samples
9.24.150 LPCD_RSSI_TARGET (0494h)
Table 278.ꢀLPCD_RSSI_TARGET (address 0494h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
494
LPCD setting
7
Value to be set in register DGRM_RSSI_REG_DGRM_RSSI_TARGET
Typically the same values from the Type A106 LOAD_RF_CONFIGURATION(0x0D)
(DGRM_RSSI register) are used
9.24.151 LPCD_RSSI_HYST (0496h)
Table 279.ꢀLPCD_RSSI_HYST (address 0496h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
496
LPCD setting
7 Value to be set in CLIF_DGRM_RSSI_REG_DGRM_RSSI_HYST
Typically the same values from the Type A106 LOAD_RF_CONFIGURATION(0x0D)
(DGRM_RSSI register) are used
9.24.152 LPCD_CONFIG (0497h)
Table 280.ꢀLPCD_CONFIG (address 0497h) EEPROM configuration register bit description
AddresFunction
(hex)
Bit
Description
49B
RFU
15:6
5
-
Immediate RF OFF before TXLDO shutdown to save power 0 - Disable 1 - Enable
VDDPA fast discharge 0 - Disable 1 - Enable
TX Drivers 0 - Enable Single driver 1 - Enable both drivers
4
3
Acquisition
channels:
2:0
0:1 = RFU
2 = Magnitude
3 = I and Q
4 =M, I and Q
5:7 = RFU
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9.24.153 LPCD_THRESHOLD_COARSE (049Ah)
Table 281.ꢀLPCD_THRESHOLD_COARSE (address 049Ah) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
49E
LPCD Q channel
31:16
ADC LSB granularity of threshold depends on avg_samples_meas value
threshold
5: unit 1/32;
4: unit 1/16;
3: unit 1/8;
2: unit 1/4;
1: unit 1/2;
0: unit 1
LPCD I channel
threshold
0:15
ADC LSB granularity of threshold depends on avg_samples_meas value
5: unit 1/32;
4: unit 1/16;
3: unit 1/8;
2: unit 1/4;
1: unit 1/2;
0: unit 1
Note: If the difference between the measured value and the reference is greater than
the threshold on either channels, then a card is detected.
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9.24.154 LPCD_VDDPA (04B5h)
Table 282.ꢀLPCD_VDDPA (address 04B5h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
4B5
VDDPA voltage during LPCD when DC-DC
(internal or external) or external power source is
used to feed TXLDO
7:0 TXLDO output voltage:
0x00: 1V50
0x01: 1V60
0x02: 1V70
0x03: 1V80
0x04: 1V90
0x05: 2V00
0x06: 2V10
0x07: 2V20
0x08: 2V30
0x09: 2V40
0x0A: 2V50
0x0B: 2V60
0x0C: 2V70
0x0D: 2V80
0x0E: 2V90
0x0F: 3V00
0X10: 3V10
0x11: 3V20
0x12: 3V30
0x13: 3V40
0x14: 3V50
0x15: 3V60
0x16: 3V70
0x17: 3V80
0x18: 3V90
0x19: 4V00
0x1A: 4V10
0x1B: 4V20
0x1C: 4V30
0x1D: 4V40
0x1E: 4V50
0x1F: 4V60
0x20: 4V70
0x21: 4V80
0x22: 4V90
0x23: 5V00
0x24: 5V10
0x25: 5V20
0x26: 5V30
0x27: 5V40
0x28: 5V50
0x29: 5V60
0x2A: 5V70
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9.24.155 ULPCD_VDDPA_CTRL (04BFh)
Table 283.ꢀULPCD_VDDPA_CTRL (address 4BFh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
RFU
15:9
3-8
-
LDO_VDDPA_
VOUT_SEL
TXLDO output voltage during ULPCD polling
VDDPA_1V50 /* 0x00 */
VDDPA_1V60, /* 0x01 */
VDDPA_1V70, /* 0x02 */
VDDPA_1V80, /* 0x03 */
VDDPA_1V90, /* 0x04 */
VDDPA_2V00, /* 0x05 */
VDDPA_2V10, /* 0x06 */
VDDPA_2V20, /* 0x07 */
VDDPA_2V30, /* 0x08 */
VDDPA_2V40, /* 0x09 */
VDDPA_2V50, /* 0x0A */
VDDPA_2V60, /* 0x0B */
VDDPA_2V70, /* 0x0C */
VDDPA_2V80, /* 0x0D */
VDDPA_2V90, /* 0x0E */
VDDPA_3V00, /* 0x0F */
VDDPA_3V10, /* 0x10 */
VDDPA_3V20, /* 0x11 */
VDDPA_3V30, /* 0x12 */
VDDPA_3V40, /* 0x13 */
VDDPA_3V50, /* 0x14 */
VDDPA_3V60, /* 0x15 */
VDDPA_3V70, /* 0x16 */
VDDPA_3V80, /* 0x17 */
VDDPA_3V90, /* 0x18 */
VDDPA_4V00, /* 0x19 */
VDDPA_4V10, /* 0x1A */
VDDPA_4V20, /* 0x1B */
VDDPA_4V30, /* 0x1C */
VDDPA_4V40, /* 0x1D */
VDDPA_4V50, /* 0x1E */
VDDPA_4V60, /* 0x1F */
VDDPA_4V70, /* 0x20 */
VDDPA_4V80, /* 0x21 */
VDDPA_4V90, /* 0x22 */
VDDPA_5V00, /* 0x23 */
VDDPA_5V10, /* 0x24 */
VDDPA_5V20, /* 0x25 */
VDDPA_5V30, /* 0x26 */
VDDPA_5V40, /* 0x27 */
VDDPA_5V50, /* 0x28 */
VDDPA_5V60, /* 0x29 */
VDDPA_5V70, /* 0x2A */
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Table 283.ꢀULPCD_VDDPA_CTRL (address 4BFh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
4BF
RFU
2:0
-
9.24.156 ULPCD_TIMING_CTRL (04C2h)
Table 284.ꢀULPCD_TIMING_CTRL (address 4C2h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
4C2
RFON_GUARD_
TIME
7:4 RFON guard time: (RFON_GUARD_TIME + 2) * LFO-Freq (380 kHz)
Guard time: Time between RF-ON and first sampling of data
RFU
3:0 -
9.24.157 ULPCD_VOLTAGE_CTRL (04C6h)
Table 285.ꢀULPCD_VOLTAGE_CTRL (address 4C6h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
4C6
ULPCD
7:5 RFU
configuration
4:2 RFU
1
TX_SUPPLY by VUP_TX
0: VUP externally supplied (2.8 V to 6.0 V)
1: VUP supplied by PN5190B1 itself (pin VUP_TX connected to VBAT/VBATPWR)
0
RFU
9.24.158 ULPCD_RSSI_GUARD_TIME (04C9h)
Table 286.ꢀULPCD_RSSI_GUARD_TIME (address 4C9h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
4C9
ULPCD RSSI
15
RFU
sampling guard
time
14:0 This is the time between consecutive RSSI samples:
Range: 0 - 127 in micro seconds
9.24.159 ULPCD_RSSI_SAMPLE_CFG (04CAh)
Table 287.ꢀULPCD_RSSI_SAMPLE_CFG (address 4CAh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
4CA
ULPCD
15:0 Number of RSSI Samples which are internally averaged:
configuration
0: 4 samples,
1: 8 samples
2: 16 samples
3: 32 samples
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9.24.160 ULPCD_THRESH_LVL(04CBh)
Table 288.ꢀULPCD_THRESH_LVL (address 4CBh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
4CB
ULPCD
15:0 RSSI Threshold level Range 0 - 31
configuration
If the difference between the measured RSSI value and the reference (which is derived
during calibration) is greater than the threshold, then a card is detected.
9.24.161 ULPCD_GPIO3 (04CCh)
Table 289.ꢀULPCD_GPIO3 (address 4CCh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
4CC
4CC
RFU
7:1 -
ULPCD GPIO3
configuration
0
GPIO3 abort polarity configuration. If PN5190B1 is using the ULPCD, GPIO3 cannot be
used for any other purpose than aborting the ULPCD.
1: high-level abort ULPCD
0: low-level abort ULPCD
9.24.162 TXIRQ_GuardTime (0559h)
Table 290.ꢀFELICA_POLL_RES (address 0559) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
559
TXIRQ_
GuardTime
31:0 0 - Disabled
0x1-0xFFFFF (Enabled - 1 unit corresponds to 1 us) Maximum timeout of 1.048 s
9.24.163 FDT_default_val (055Dh)
Table 291.ꢀFDT_default_val (address 055D) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
55D
FDT_default_val
31:0 0x00 - Disabled
others - enabled (1 unit is 18.86us) Default fixed to 5.5 secs
9.24.164 RXIRQ_GuardTime (0561h)
Table 292.ꢀRXIRQ_GuardTime (address 0561h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
55D
RXIRQ_
GuardTime
31:0 0x00 Disabled
0x1-0xFFFFF (Enabled - 1 unit corresponds to 1 us) Maximum timeout of 1.048 s
Default value = 0xF4240 (1 s)
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9.24.165 NFCLD_RFLD_Valid (006D3h)
Table 293.ꢀNFCLD_RFLD_Valid (address 06D3h) EEPROM configuration register bit description
AddresFunction
(hex)
Bit Description
6D3
RFU
7:1 -
RFLD_
CALIBRATE
0
This bit allows to calibrate the RFLD / NFCLD.
This calibration is required only once in the lifetime of the chip for increased RFLD /
NFCLD accuracy, independent from the value of this bit (0 or 1).
Clearing this bit (0) will calibrate the RFLD /RFLD during the next boot-up, precondition
for the proper calibration is an unloaded condition and no external field applied.
After calibration this bit is set (1) and indicates that the RFLD /RFLD Threshold is a valid
data.
9.24.166 CurrentSensorTrimConfig (0ABCh)
Table 294.ꢀCurrentSensorTrimConfig (address 0CACh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
ABC
RFU
7:1 -
Current_Sensor_
Calib_Bypass
0
1: current sensor calibration offset is used by DPC;
0: Current sensor calibration offset is bypassed by DPC
Note: The default value should only be modified for debug purpose.
9.24.167 CORRECTION_ENTRY_TABLE (0BDAh)
Table 295.ꢀCORRECTION_ENTRY_TABLE (address 0BDAh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
0BDA sCorrection_Entry0
15:0 The correction that is applied when lookup table based shaping with
scaling is enabled.
Range is -128 to +127,
sCorrection_Entry0 corresponds to correction applied at VDDPA =
1V5,
Correction_Entry42 corresponds to correction applied at VDDPA =
5V7
For each entry:
BYTE 0: Bits[7:0] = define the correction which is applied for
ASK100
BYTE 1: Bits[15:8] = define the correction which is applied for
ASK10
BAF
BB1
BB3
BB5
BB7
sCorrection_Entry1
sCorrection_Entry2
sCorrection_Entry3
sCorrection_Entry4
sCorrection_Entry5
15:0
15:0
15:0
15:0
15:0
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Table 295.ꢀCORRECTION_ENTRY_TABLE (address 0BDAh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
BB9
BBB
BBD
BBF
BC1
BC3
BC5
BC7
BC9
BCB
BCD
BCF
BD1
BD3
BD5
BD7
BD9
BDB
BDD
BDF
BE1
BE3
BE5
BE7
BE9
BEB
BED
BEF
BF1
BF3
BF5
BF7
BF9
BFB
BFD
BFF
PN5190B1
sCorrection_Entry6
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
sCorrection_Entry7
sCorrection_Entry8
sCorrection_Entry9
sCorrection_Entry10
sCorrection_Entry11
sCorrection_Entry12
sCorrection_Entry13
sCorrection_Entry14
sCorrection_Entry15
sCorrection_Entry16
sCorrection_Entry17
sCorrection_Entry18
sCorrection_Entry19
sCorrection_Entry20
sCorrection_Entry21
sCorrection_Entry22
sCorrection_Entry23
sCorrection_Entry24
sCorrection_Entry25
sCorrection_Entry26
sCorrection_Entry27
sCorrection_Entry28
sCorrection_Entry29
sCorrection_Entry30
sCorrection_Entry31
sCorrection_Entry32
sCorrection_Entry33
sCorrection_Entry34
sCorrection_Entry35
sCorrection_Entry36
sCorrection_Entry37
sCorrection_Entry38
sCorrection_Entry39
sCorrection_Entry40
sCorrection_Entry41
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Table 295.ꢀCORRECTION_ENTRY_TABLE (address 0BDAh) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
C01
sCorrection_Entry42
15:0
9.24.168 RTRANS_FTRANS_TABLE (0C03h)
Table 296.ꢀRTRANS_FTRANS_TABLE (address C03h) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
C03
C07
C0B
C0F
C13
C17
C1B
C1F
C23
C27
C2B
C2F
C33
C37
C3B
C3F
C43
C47
C4B
C4F
C53
C57
C5B
C5F
C63
C67
C6B
C6F
C73
C77
RTRANS0
RTRANS1
RTRANS2
RTRANS3
FTRANS0
FTRANS1
FTRANS2
FTRANS3
RTRANS0
RTRANS1
RTRANS2
RTRANS03
FTRANS0
FTRANS1
FTRANS2
FTRANS3
RTRANS0
RTRANS1
RTRANS2
RTRANS03
FTRANS0
FTRANS1
FTRANS2
FTRANS3
RTRANS0
RTRANS1
RTRANS2
RTRANS03
FTRANS0
FTRANS1
31:0 These values apply in case EDGE_STYLE = 0 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 0 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 0 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 0 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 0 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 0 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 0 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 0 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 1 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 1 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 1 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 1 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 1 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 1 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 1 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 1 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 2 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 2 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 2 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 2 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 2 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 2 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 2 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 2 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 3 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 3 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 3 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 3 is configured for the rising edge
31:0 These values apply in case EDGE_STYLE = 3 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 3 is configured for the falling edge
PN5190B1
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Table 296.ꢀRTRANS_FTRANS_TABLE (address C03h) EEPROM configuration bit description...continued
AddresFunction
(hex)
Bit
Description
C7B
C7F
FTRANS2
FTRANS3
31:0 These values apply in case EDGE_STYLE = 3 is configured for the falling edge
31:0 These values apply in case EDGE_STYLE = 3 is configured for the falling edge
This table applies only, if the transmitter shaping configuration is (EDGE_TYPE_xx) 4, 5,
or 6.
Which of the entries RTRANS0..3 (rising transition) / FTRANS0..3 (falling transition) is
applied, is defined by the EDGE_STYLE.
9.24.169 CFG_NOV_CAL (0C83h)
TX non-overlap feature - defines the non-overlap time of TX1, TX2.
Table 297.ꢀCFG_NOV_CAL (address 0083h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
1
RFU
7:2 -
CALIBRATION_
TYPE
1:0 00 = No calibration performed, needs to be updated to 01 or 10 before the first RF on of
the chip is performed
01 = Enable FW calibration after every cold boot
10 = Use calibration value coming from EEPROM NOV_CAL_VAL1, NOV_CAL_VAL2 (D
efault)
11 = RFU
9.24.170 NOV_CAL_VAL1 (0C84h)
Table 298.ꢀNOV_CAL_VAL1 (address 0C84h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
1
VddpaCalVal1
7 It defines the VDDPA value that FW will use to perform NOV calibration group #1.
value = 03h (1.8 V)
value = 0Dh (2.8 V)
See "TxLdoVddpaHigh" parameter for list of voltage
9.24.171 NOV_CAL_VAL2 (0C85h)
Table 299.ꢀNOV_CAL_VAL2 (0C85h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
1
VddpaCalVal2
7 It defines the VDDPA value that FW will use to perform NOV calibration group #2.
default value = 15h (3.6 V)
default value = 24h (5.1 V)
See "TxLdoVddpaHigh" parameter for list of voltage
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9.24.172 NOV_CAL_THRESHOLD (0C86h)
Table 300.ꢀNOV_CAL_THRESHOLD (address 0C86h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
1
CfgThreshold
7
It defines VDDPA threshold that FW will use to select Group #1 or Group #2 NOV offset
values.
default value = 08h (2.3 V)
default value = 16h (3.7 V)
See "TxLdoVddpaHigh" parameter for list of voltage
9.24.173 NOV_CAL_OFFSET1 (0C87h)
Table 301.ꢀNOV_CAL_OFFSET1 (address 0C87h) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
1
UserOffsets1
7 It defines user static offsets applied if CfgNovCal[1:0] = 10b
bits[04:00] Group #2 (CfgThreshold to VDDPA max), offset_3l
bits[12:08] Group #2 (CfgThreshold to VDDPA max), offset_3l_p2
bits[20:16] Group #2 (CfgThreshold to VDDPA max), offset_2l<0>
bits[28:24] Group #2 (CfgThreshold to VDDPA max), offset_2l<1>
9.24.174 NOV_CAL_OFFSET2 (0C8Bh)
Table 302.ꢀNOV_CAL_OFFSET1 (address 0C8Bh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
1
UserOffsets2
7 It defines user static offsets applied if CfgNovCal[1:0] = 10b
bits[04:00] Group #2 (CfgThreshold to VDDPA max), offset_3l
bits[12:08] Group #2 (CfgThreshold to VDDPA max), offset_3l_p2
bits[20:16] Group #2 (CfgThreshold to VDDPA max), offset_2l<0>
bits[28:24] Group #2 (CfgThreshold to VDDPA max), offset_2l<1>
9.24.175 VDDPA_DISCHARGE (0C8Fh)
Table 303.ꢀVDDPA_DISCHARGE (address 0C8Fh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
C8F
RFU
7:1 RFU
EnableFastVDDP
ADischarge
0
1 - Enables fast discharge of VDDPA by setting VDDPA=5.7 and then to 1.5 V, during RF
OFF
0 - Enables fast discharge of VDDPA by setting VDDPA=5.7 and then to 1.5 V, during RF
OFF
9.24.176 ARC_RM_A106_FDT (0C9Dh)
This is the setting for type A-106.
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Table 304.ꢀARC_RM_A106_FDT (address 0C9Dh) EEPROM configuration bit description
AddresFunction
(hex)
Bit
Description
CA5
CA3
CA1
C9F
C9D
RM_RX_ARC_
FDT_4
15:0
Bit[15]: RFU
Bit [14]: Has to be always "0"
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_
FDT_3
15:0
15:0
15:0
15:0
Bit[15]: RFU
Bit [14]: Has to be always "0"
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_
FDT_2
Bit[15]: RFU
Bit [14]: Has to be always "0"
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_
FDT_1
Bit[15]: RFU
Bit [14]: Has to be always "0"
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
RM_RX_ARC_
FDT_0
Bit[15]: RFU
Bit [14]: Has to be always "0"
Bits[13:10] = RFU
Bit [9] = Enable the IIR filter.
Bits[8:7] = MF_GAIN (this value will be applied to the SIGPR_RM_TECH register,
applies as soon as the ARC is enabled)
Bits[6:0] = DPC_ SIGNAL_DETECT_TH_OVR_VAL (this value will be applied to the
DGRM_RSSI register, applies as soon as the ARC is enabled)
Note: For ISO14443-A: In case ARC is disabled, it requires DPC_
SIGNAL_DETECT_TH_OVR_VAL larger than 0x50 (with MF_GAIN = 2 (default))
Note: For ISO14443-A: In case Bit[15] is configured to 0, it requires DPC_
SIGNAL_DETECT_TH_OVR_VAL larger than 0x50 (with MF_GAIN = 2 (default)) if the
ARC is enabled.
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Note: The IIR settings define an all pass filter with approximately -10 dB gain. This can
be used to limit the LMA sensitivity of the RX.
9.24.177 Tx_Symbol23_Mod_Reg_BR_53 (0CC5h)
Table 305.ꢀTx_Symbol23_Mod_Reg_BR_53 (0CC5Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
CC5
15693_BR_CFG
31:0 CLIF_TX_SYMBOL23_MOD_REG value loaded for 15693 BR 53 kbit/s
9.24.178 Tx_Data_Mod_Reg_BR_53 (0CC9h)
Table 306.ꢀTx_Data_Mod_Reg_BR_53 (0CC9Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
CC9
15693_BR_CFG
31:0 CLIF_TX_Data_MOD_REG value loaded for 15693 BR 53 kbit/s
9.24.179 Tx_Symbol23_Mod_Reg_BR_106 (0CCDh)
Table 307.ꢀTx_Symbol23_Mod_Reg_BR_106 (0CCDEh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
CCD 15693_BR_CFG
31:0 CLIF_TX_Symbol23_MOD_REG value loaded for 15693 BR 106 kbit/s
9.24.180 Tx_Data_Mod_Reg_BR_106 (0CD1h)
Table 308.ꢀTx_Data_Mod_Reg_BR_106 (0CD1Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
CD1
15693_BR_CFG
31:0 CLIF_TX_Data_MOD_REG value loaded for 15693 BR 106 kbit/s
9.24.181 Tx_Symbol23_Mod_Reg_BR_212 (0CD5h)
Table 309.ꢀTx_Symbol23_Mod_Reg_BR_212 (0CD5Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
CD5
15693_BR_CFG
31:0 CLIF_TX_Symbol23_MOD_REG value loaded for 15693 BR 212 kbit/s
9.24.182 Tx_Data_Mod_Reg_BR_212 (0CD9h)
Table 310.ꢀTx_Data_Mod_Reg_BR_212 (0CD9Eh) EEPROM configuration bit description
AddresFunction
(hex)
Bit Description
CD9
15693_BR_CFG
31:0 CLIF_TX_Data_MOD_REG value loaded for 15693 BR 212 kbit/s
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10 Limiting values
Table 311.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
-0.3
-0.3
-0.3
Max
5.8
Unit
V
VDD(VUP_TX)
VDD(VBAT)
VDD(VDDIO)
supply voltage on pin VUP_TX
supply voltage on pin VBAT
supply voltage on pin VDDIO
-
-
5.8
V
on pin VDDIO, power supply for
host interface and GPIOs
3.8
V
VDD(VDDPA)
supply voltage on pin VDDPA
maximum limiting values for
-
6.0
V
IDD(VDDPA) and Tj(max) not violated
Vi(RXP)
Vi(RXN)
VESD
input voltage on pin RXP
input voltage on pin RXN
electrostatic discharge voltage human body model (HBM)[1]
charge device model (CDM)[2]
-
-0.3
-0.3
+ 2.0
+ 2.0
V
-
V
-2000 2000
V
-500
-
+500
125
V
Tj(max)
Tstg
junction temperature
storage temperature
-
°C
°C
no supply voltage applied
-55
+150
[1] According to ANSI/ESDA/JEDEC JS-001
[2] According to ANSI/ESDA/JEDEC JS-002
Stress above one or more of the limiting values may cause permanent damage to the
device or limit the lifetime.
Product might not behave according to specification.
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11 Characteristics
This chapter describes the electrical characteristics for the usage of the product.
Functionality according to this specification and compliancy to referred standards is
guaranteed if the device is operated within the limits.
For further information, refer to the PQP (product qualification package) which
summarizes the results of the characterization and qualification performed.
11.1 Thermal characteristics
Table 312.ꢀOperating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tamb
ambient operating temperature
in still air with
-40
+25
+85
°C
exposed pins
soldered on a 4
layer JEDEC PCB,
transmitter output
current up to 350 mA
depends on operating -40
condition: Supply
voltage, without DC-
DC, Transmitter
+25
+105
°C
current
Table 313.ꢀThermal characteristics HVQFN40 package
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
in free air with exposed pad
soldered on a 4 layer JEDEC
PCB, package HVQFN40
44.2
K/W
Rth(j-c)
thermal resistance from junction to case
-
24.2
K/W
Table 314.ꢀThermal characteristics VFBGA64 package
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
in free air with exposed pad
soldered on a 4 layer JEDEC
PCB, package VFBGA64
53
K/W
Rth(j-c)
thermal resistance from junction to case
-
22
K/W
Table 315.ꢀJunction Temperature
Symbol
Parameter
Conditions
Min
Max
Unit
Tj_max
maximum junction temperature
-
-
+125
°C
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Table 316.ꢀThermal Shutdown Temperature
Symbol
Parameter
Conditions
Typ
Unit
Tshutdown
shutdown of chip due to high temperature
detected by temp sensor
-
125
°C
11.2 Static characteristics
Table 317.ꢀSupply voltage
Symbol Parameter
Conditions
Min
2.4
2.8
2.4
Typ
Max
5.5
Unit
V
VDD(VBAT_PWR) supply voltage on pin VBAT_PWR DC-DC disabled
-
-
-
(DC-DC input pin)
DC-DC enabled
4.8
V
VDD(VUP_TX)
supply voltage on pin VUP_TX
(TX_LDO input pin)
Remark: If DC-DC
is used, its output
VDD(BOOST) Min is
limited to 3.1 V
6.0
V
VDD(VDDPA)
supply voltage on pin VDDPA
-
1.5
2.4
-
5.7
V
(input of the transmitter power
amplifier)
VDD(VBAT)
supply voltage on pin VBAT
(analog and digital supply)
VBAT >= VDDIO
-
-
-
5.5
V
V
V
VDD(VDDIO)
supply voltage on pin VDDIO
(supply for host interface and
GPIOs)
typical 1.8 V interface 1.62
supply voltage
1.98
3.6
typical 3.3 V interface 2.4
supply voltage
VI(RXP)
VI(RXN)
input voltage on pin RXP
input voltage on pin RXN
-
-
-0.5
-0.5
-
-
1.8
1.8
V
V
Note: The voltage on pin VDDIO must always be smaller or equal to the voltage on pin
VBAT.
Table 318.ꢀCurrent consumption in active mode
Symbol
IDD(VBAT)
IDD(VDDIO)
Parameter
Conditions
Min
Typ
Max
20
Unit
mA
mA
system supply
-
-
-
-
This current depends
on the output current
of peripherals. At
30
no time, the sum of
the maximum output
currents shall exceed
IDD(VDDIO) max
IDD(BOOST_IN)
DC-DC boost supply
average input current
-
-
-
-
1.0
1.7
A
A
peak input current
(short peak)
IDD(VUP_TX)
IDD(VDDPA)
input supply for transmitter
LDO
-
-
-
-
-
350
350
mA
mA
RF power amplifier
(transmitter) current
supplied via VUP_TX
(TX_LDO active)
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Table 318.ꢀCurrent consumption in active mode...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
supplied without DC-DC -
and TXLDO active
-
400
mA
Table 319.ꢀCurrent consumption during power-saving modes
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOFF Plus Mode
sum of supply current on pin 25 °C ambient
-
5
-
μA
VDDIO and VBAT in OFF
Plus mode
operating temperature
(VDDIO+VBAT)
IOFF Plus ULFO Mode sum of supply current on pin 25 °C ambient
-
5
-
μA
VDDIO and VBAT in OFF
Plus mode, ULFO active
(ULPCD during RF-OFF)
operating temperature
(VDDIO+VBAT)
Ihard power down
sum of supply current on pin 25 °C ambient
-
-
40
45
105
110
μA
μA
VDDIO and VBAT in hard
power-down mode
operating temperature
(VDDIO+VBAT)
Istandby (VDDIO
sum of supply current on pin 25 °C ambient
VDDIO and VBAT in standby operating temperature
mode
+VBAT)
Isuspend (VBAT)
supply current on pin VBAT in 25 °C ambient
-
-
2.5
22
-
-
mA
μA
suspend mode
operating temperature
IULPCD (VDDIO
sum of supply current on
pin VDDIO and VBAT in
ULPCD (Ultra Low-Power
Card Detection) mode
25 °C ambient
operating temperature,
VBAT supply voltage
3.3 V, antenna matching
50 R, 3.3 V antenna
supply voltage, 3x RF-
on per second
+VBAT)
ILPCD (VDDIO+VBAT) sum of supply current on
pin VDDIO and VBAT in
25 °C ambient
operating temperature,
-
240
-
μA
LPCD (Enhanced Low-Power VBAT supply voltage
Card Detection with highest 3.3 V, antenna matching
sensitivity) mode, without DC- 50 R, 3.3 V antenna
DC used
supply voltage, 3x RF-
on per second
Table 320.ꢀOvercurrent detection function [1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD(VUP_TX)
current of overcurrent
-
450
550
650
mA
detection becoming active
[1] Please refer to the Errata sheet if the device is used with smaller or equal than FW2.1.
This is a safety feature only. A design shall not functionally rely on this feature since the
operating conditions will be violated if the overcurrent detection becomes active.
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Table 321.ꢀVEN pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
VDD(VDDIO)<=
VDD(VBAT)
0.7 *
VDD(VDDIO)
-
VDD(VDDIO)
V
VIL
LOW-level input voltage
0
-
0.3 *
V
VDD(VDDIO)
IIH
HIGH-level input current
LOW-level input current
input capacitance
VI = VDD(VBAT)
VI = 0 V
-
-
1
-
μA
μA
pF
ms
IIL
-1
-
-
Ci
5
-
-
t(ULPCD_abort)
VEN time required to abort ULPCD
5
-
Table 322.ꢀGPIO (GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO4, GPIO5) pins
Symbol Parameter Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage VDD(VDDIO)<= VDD(VBAT) ; 1.62 <=
VDDIO <= 1.98 or
0.65x
VDDIO
-
VDDIO+0.5
V
2.4 <= VDDIO <= 3.6
VIL
LOW-level input voltage VDD(VDDIO)<= VDD(VBAT) ; 1.62 <=
VDDIO <= 1.98 or
- 0.5
-
0.35 ×
VDDIO
V
2.4 <= VDDIO <= 3.6
VOH
VOH
IOH
HIGH-level output
voltage
VDD(VDDIO) = 3.3 V
VDD(VDDIO) = 3.3 V
VDD(VDDIO) = 3.3 V
VDDIO -
0.4
-
-
-
VDDIO
0.4
V
LOW-level output
voltage
0
V
HIGH-level output
current
-
3
mA
IOL
LOW-level output current VDD(VDDIO) = 3.3 V
-
-
3
mA
kΩ
kΩ
RPU
RPD
Weak pullup resistor
-
-
40
40
50
50
62
62
Weak pull-down resistor
Table 323.ꢀCLK1, CLK2 pins
Symbol
Vi(p-p)
IIH
Parameter
Conditions
Min
Typ
Max
1.65
5
Unit
peak-to-peak input voltage
HIGH-level input current
-
0.4
-
-
-
V
VI= 1.65 V, no power
saving, active mode
μA
IIL
LOW-level input current
VI = 0 V, no power saving, -
active mode
-
1
μA
δ
duty cycle
-
35
-
65
-
%
Ci(CLK1)
input capacitance on pin CLK1
VDD = 1.8 V,
-
1
pF
VDC = 0.65 V,
VAC = 0.9 V (p-p)
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Table 323.ꢀCLK1, CLK2 pins ...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ci(CLK2)
input capacitance on pin CLK2
VDD = 1.8 V,
-
1
-
pF
VDC = 0.65 V,
VAC = 0.9 V (p-p)
Table 324.ꢀIRQ pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
IOH < 3 mA
VDD(VDDIO)
-0.4
-
VDD(VDDIO)
V
VOL
IOH
IOL
CL
tf
LOW-level output voltage
HIGH-level output current
LOW-level output current
load capacitance
fall time
IOL < 3 mA
0
-
-
-
-
-
-
-
-
0.4
3
V
mA
mA
pF
ns
-
3
-
10
3
CL = 12 pF max
CL = 12 pF max
1
1
40
tr
rise time
3
ns
Rpd
pull-down resistance
62
kΩ
Table 325.ꢀSCLK, MOSI, NSS pins
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
0.65 x
-
VDD(VDDIO)
V
VDD(VDDIO)
VIL
LOW-level input voltage
- 0.5
-
0.35 x
V
VDD(VDDIO)
IIH
IIL
Ci
HIGH-level input current
LOW-level input current
input capacitance
VI = VVDDIO
VI = 0 V
-
-
-
-
1
1
-
μA
μA
pF
-
5
Table 326.ꢀMISO pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
IOH < 3 mA
VDD(VDDIO)
-0.4
-
VDD(VDDIO)
V
VOL
IOH
IOL
CL
tf
LOW-level output voltage
HIGH-level output current
LOW-level output current
load capacitance
fall time
IOL < 3 mA
0
-
-
-
-
-
-
-
0.4
3
V
mA
mA
pF
ns
ns
-
3
-
10
3
CL = 12 pF max
CL = 12 pF max
1
1
tr
rise time
3
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Table 327.ꢀRXp, RXn pins
Symbol
Vi(dyn)
Ci
Parameter
Conditions
Min
Typ
Max
1.8
-
Unit
V
dynamic input voltage
input capacitance
-
-
-
-
1
-
pF
kΩ
Zi
input impedance from RXN, RXP
pins to VMID
Reader, card and
P2P modes
15
Table 328.ꢀTX1, TX2 pins
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level
output voltage
VDD(VDDPA)=5.0 V; with internal
VDDPA LDO
-
VDD(VDDPA) -150 VDD(VDDPA)
mV
V
VOL
LOW-level
output voltage
VDD(VDDPA)=5.0 V;with internal
VDDPA LDO
0
200
-
mV
Table 329.ꢀAUX1, AUX2, AUX3 pins (Debug output)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VAUX_OH
HIGH-level output voltage
pin used as debug
signal output
VDDIO
-0.4
-
VDDIO
V
VAUX_OL
LOW-level output voltage
pin used as debug
signal output
0
-
0.4
mV
IAUX_OH
IAUX_OL
CO_LOAD
HIGH-level output current
LOW-level output current
output capacitance load of pin
VDD(VDDIO) = 3.3 V
VDD(VDDIO) = 3.3 V
-
-
-
-
3.0
3.0
10
mA
mA
pF
-
5
Table 330.ꢀDAC_1, DAC_2 output pins (Tuning DAC)
Symbol
Parameter
Conditions
Min
Typ
VDD(VDDIO)
Max
Unit
VO_max
HIGH-level maximum
output voltage
connected to a variable
capacitor (varicap)
-
3.65
V
VO_min
LOW-level minimum output connected to a variable
- 0.3
0
200
mV
voltage
capacitor (varicap)
DAC resolution
-
-
-
8
4
bits
nF
CO_LOAD
output capacitance load of
pin
0
11.3 Timing characteristics
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t
rise_vbat
VBAT = VBATPWR
V
= V
>2.4 V
batpwr
bat
VDDIO
VEN
t
vbat_vddio
t
vbat_ven
t
vddio_ven
IRQ
t
boot
aaa-037021
Figure 29.ꢀ Startup timing
Table 331.ꢀPower supply connection timing
Symbol
trise_vbat
tvbat_vddio
Parameter
Conditions
Min
0
Typ
-
Max
2.75
1000
Unit
V/us
ms
VBAT supply ramp
VEN = Low
time between ramping up VBAT vddio condition:
0
500
and ramping VDDIO
VBAT>2.4 V,
VDDIO supply
(External), hpd_
off_sel = x
tvbat_ven
time between ramping VBAT
and VEN
vddio condition:
VBAT>2.4 V,
VDDIO supply
(External), hpd_
off_sel = x
0
500.5 1001
ms
ms
tboot
start-up time[1]
vddio condition: 3.2
VBAT>2.4 V,
3.27
dependent on
configuration of
VDDIO supply
(External), hpd_
off_sel = x
XTAL_BOOT_ TIME
in EEPROM. This
configuration can be
used to optimize the
boot time for crystals
which allow a fast
settling. This allows to
optimize the average
current consumption
during ULPCD and
LPCD.
default EEPROM
configuration: 3.4
[1] (PN5190B1 ready to receive commands on the host interface). The PN5190B1 indicates the ability to receive commands from a host by raising an IDLE
IRQ.
PN5190B1
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Table 332.ꢀPulse length
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t(VEN)
on Pin VEN, pulse width to
reset the chip or exit from
ULPCD / Hard Power Down
State
-
5
-
-
ms
t(wake-up)
on pin GPIOx, pulse width to
wake up
-
-
1
-
-
-
-
μs
tVEN(GPIO)
time from VEN high to GPIO’s
available for use
100
ms
Table 333.ꢀDAC1, DAC2 conversion timing (Tuning DAC)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tconversion
Conversion speed of 8-bit
DAC1, DAC2
1 LSB rising
falling,
-
-
0.15
ms
(depends on
capacitive load)
RF cut
resistance: 100
kOhm (max),
Cin: 8 nF (max)
Full signal rising
from 0.0 V to 3
V,
-
-
0.15
ms
(depends on
capacitive load)
RF cut
resistance: 100
kOhm (max),
Cin: 8 nF (max)
falling from 3 V
to 300 mV,
-
-
2
ms
(depends on
capacitive load)
RF cut
resistance: 100
kOhm (max),
Cin: 8 nF (max)
Table 334.ꢀSPI interface
Symbol
tSCKL
Parameter
Min
Typ
Max
Unit
ns
SCK LOW time
SCK HIGH time
25
-
-
-
-
-
-
tSCKH
25
-
ns
th(SCKH-D)
tsu(D-SCKH)
th(SCKL-Q)
SCK HIGH to data input hold time
data input to SCK HIGH set-up time
SCK LOW to data output hold time
12.5
12.5
-
-
ns
-
ns
25
ns
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Table 334.ꢀSPI interface...continued
Symbol
t(SCKL-NSSH)
tNSSH
Parameter
Min
0
Typ
Max
Unit
ns
SCK LOW to NSS HIGH time
NSS HIGH time
-
-
-
-
25
ns
Table 335.ꢀRF_ON command timing following a previous RF_OFF
Symbol
Parameter
Conditions Min
Typ Max
5.6
Unit
t(RF_OFF-
RF_ON command timing guard time
5.1
-
ms
between
command
sends for
RF_OFF and
command
send for
RF_ON,
capacitors
on
RF_ON)
transmitter
need to be
fully de-
charged
before
RF_ON
command is
sent
11.4 Clock input
Table 336.ꢀCrystal requirements for ISO/IEC14443 compliant operation
Symbol
Parameter
Conditions Min
Typ
Max
Unit
fxtal
crystal frequency
ISO/IEC
-
27.12
-
MHz
compliancy
delta fxtal
ESR
crystal frequency accuracy for full RF
-40
-
+40
100
ppm
Ω
operating
range
equivalent series
resistance
-
10
30
CL
load capacitance
-
-
-
6
-
8
-
10
1
pF
tstartupl
Pxtal
crystal startup time
crystal power dissipation
ms
μW
-
-
100
Table 337.ꢀFrequency requirements for a direct clock input (no crystal)
Symbol
Parameter
Conditions Min
Typ
24
Max
Unit
fclk
clock frequency
ISO/IEC
-
-
-
-
MHz
compliancy
32
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Table 337.ꢀFrequency requirements for a direct clock input (no crystal) ...continued
Symbol
Parameter
Conditions Min
Typ
48
-
Max
-
Unit
-
delta fclk
clock frequency accuracy
for full RF
operating
range
-40
-
+40
ppm
φn
phase noise
input phase
noise floor
at 100 kHz
offset
- 150
- 152
-145
-149
dBc/Hz
dBc/Hz
φn
phase noise
input phase
noise floor at
1 MHz offset
-
Vi
Input voltage boundary
sinus signal
0
-
-
-
1.8
1.8
V
V
V
Vi(p-p)
Vi(clk)
peak-to-peak Input voltage sinus signal 0.4
clock input voltage
square
signal
0
1.8
+/-10%
11.5 EEPROM characteristics
Table 338.ꢀEEPROM characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Nendu(W)
write endurance at ambient temperature
Ta = +25 °C
100
-
-
K cycles
tret
retention time
at ambient temperature
Ta =+25 °C
25
-
-
years
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12 Package outline
12.1 VFBGA64 package
Table 339.ꢀPackage outline VFBGA64 (SOT1307-2)
Figure 30.ꢀPackage outline VFBGA64 (SOT1307-2)
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Figure 31.ꢀPackage outline note VFBGA64 (SOT1307-2)
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12.2 HVQFN40 package
Figure 32.ꢀPackage outline HVQFN40, SOT2062-1
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Figure 33.ꢀPackage outline detail HVQFN40, SOT2062-1
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13 Package marking
13.1 Package marking drawing VFBGA64
Terminal 1 index area
A : 5
B : 5
C : 8
0
5
aaa-036197
Figure 34.ꢀ Marking VFBGA64 Package
Line A: 5 characters; "PN5190D" (FW2.0) or "5190E" (FW2.1)
Line B: 5 characters; contains the DB ID and AS ID
Line C: 8 characters; stDYYWW(X) - contains information assembly center, date code
and maturity level (“X” = engineering samples, “ “ = released product)
13.2 Package marking drawing HVQFN40
Terminal 1 index area
A : 5
B1 : 5
B2 : 7
C : 7
0
5
aaa-036198
Figure 35.ꢀ Marking HVQFN40 package SOT2062-1
Line A: 5 characters; "PN5190D" (FW2.0) or "5190E" (FW2.1)
Line B1: 5 characters; contains the DB ID
Line B2: 7 characters; contains the DB ID (continued) and AS ID (2 digits)
Line C: 7 characters; stDYYWW(X) - contains information assembly center, date code
and maturity level (“X” = engineering samples, “Y” = customer qualification samples, “ “ =
released product)
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14 Reflow soldering footprint VFBGA64
Figure 36.ꢀReflow soldering footprint part1 for VFBGA64 (SOT1307-2)
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Figure 37.ꢀReflow soldering footprint part2 for VFBGA64 (SOT1307-2)
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Figure 38.ꢀReflow soldering footprint part3 for VFBGA64 (SOT1307-2)
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OSP finishing
before reflow
Cu plating
laminate 2L
solder mask
ball
250 µm
solder mask opening
aaa-032325
350 µm
Figure 39.ꢀSoldering and footprint representative illustration for VFBGA64 (SOT1307-2)
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15 Reflow soldering footprint HVQFN40
Figure 40.ꢀPackage outline HVQFN40, SOT2062-1
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Figure 41.ꢀPackage outline HVQFN40, SOT2062-1
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Figure 42.ꢀPackage outline HVQFN40, SOT2062-1
PN5190B1
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Figure 43.ꢀPackage outline HVQFN40, SOT2062-1
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16 Surface mount reflow soldering
For information on surface mount, reflow soldering and component handling please refer
to the related application note.
This application note provides guidelines for the board mounting and handling of NXP
Semiconductor packages:
https://www.nxp.com/docs/en/application-note/AN10365.pdf
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17 Handling information
Moisture Sensitivity Level (MSL) evaluation has been performed according to SNW-
FQ-225B rev.04/07/07 (JEDEC J-STD-020C).
An MSL corresponds to a certain out-of-bag time (or floor life). If semiconductor
packages are removed from their sealed dry-bags and not soldered within their out-of-
bag time, they must be baked prior to reflow soldering, in order to remove any moisture
that might have soaked into the package.
For MSL3:
168h out-of-pack floor life at maximum ambient temperature, conditions < 30 °C / 60 %
RH.
For MSL2:
• 1 year out-of-pack floor life at maximum ambient temperature, conditions < 30 °C° / 60
% RH.
For MSL1:
• No out-of-pack floor live spec. required. Conditions: <30 °C° / 85 % RH.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.
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18 Appendix: EEPROM LOAD_RF_CONFIGURATION FW2.0
Firmware 2.0
<?xml version="1.0" encoding="utf-8"?>
<EEPROM>
<Region RegionName="USER_PMU" RegionAccess="RW" RegionType="DATA">
<Parameter Name="PwrConfig" Offset="0x00" Value="0xE4" />
<Parameter Name="DcdcConfig" Offset="0x01" Value="0x31" />
<Parameter Name="TxldoConfig" Offset="0x02" Value="0xFFFFAEA7" />
<Parameter Name="TxLdoVddpaHigh" Offset="0x06" Value="0x00" />
<Parameter Name="TxLdoVddpaLow" Offset="0x07" Value="0x00" />
<Parameter Name="TxLdoVddpaMaxRdr" Offset="0x08" Value="0x2A" />
<Parameter Name="TxLdoVddpaMaxCard" Offset="0x09" Value="0x2A" />
<Parameter Name="BoostDefaultVoltage" Offset="0x0A" Value="0x1D" />
</Region>
<Region RegionName="CLKGEN" RegionAccess="RW" RegionType="DATA">
<Parameter Name="XtalConfig" Offset="0x10" Value="0x00" />
<Parameter Name="XtalTimeOut" Offset="0x11" Value="0xFF" />
</Region>
<Region RegionName="RF_CLOCK_CFG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="PLLClkInputFrq" Offset="0x12" Value="0x08" />
<Parameter Name="XtalCheckDelay" Offset="0x13" Value="0xF6" />
</Region>
<Region RegionName="USER_SMU" RegionAccess="RW" RegionType="DATA">
<Parameter Name="TempWarning" Offset="0x14" Value="0x99" />
<Parameter Name="EnableGpio0OnOverTemp" Offset="0x16" Value="0x01" />
</Region>
<Region RegionName="RM_TECHNO_TX_SHAPING" RegionAccess="RW" RegionType="DATA">
<Parameter Name="ResidualAmplitudeLevel_A106" Offset="0x22" Value="0x00" />
<Parameter Name="EdgeType_A106" Offset="0x23" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_A106" Offset="0x24" Value="0x64" />
<Parameter Name="EdgeLength_A106" Offset="0x25" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_A212" Offset="0x26" Value="0x00" />
<Parameter Name="EdgeType_A212" Offset="0x27" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_A212" Offset="0x28" Value="0x44" />
<Parameter Name="EdgeLength_A212" Offset="0x29" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_A424" Offset="0x2A" Value="0x00" />
<Parameter Name="EdgeType_A424" Offset="0x2B" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_A424" Offset="0x2C" Value="0x24" />
<Parameter Name="EdgeLength_A424" Offset="0x2D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_A848" Offset="0x2E" Value="0x00" />
<Parameter Name="EdgeType_A848" Offset="0x2F" Value="0x11" />
<Parameter Name="EdgeStyleConfiguration_A848" Offset="0x30" Value="0x18" />
<Parameter Name="EdgeLength_A848" Offset="0x31" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B106" Offset="0x32" Value="0xC8" />
<Parameter Name="EdgeType_B106" Offset="0x33" Value="0x44" />
<Parameter Name="EdgeStyleConfiguration_B106" Offset="0x34" Value="0x00" />
<Parameter Name="EdgeLength_B106" Offset="0x35" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B212" Offset="0x36" Value="0xCF" />
<Parameter Name="EdgeType_B212" Offset="0x37" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_B212" Offset="0x38" Value="0x66" />
<Parameter Name="EdgeLength_B212" Offset="0x39" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B424" Offset="0x3A" Value="0xCF" />
<Parameter Name="EdgeType_B424" Offset="0x3B" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_B424" Offset="0x3C" Value="0x55" />
<Parameter Name="EdgeLength_B424" Offset="0x3D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B848" Offset="0x3E" Value="0xCE" />
<Parameter Name="EdgeType_B848" Offset="0x3F" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_B848" Offset="0x40" Value="0x34" />
<Parameter Name="EdgeLength_B848" Offset="0x41" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_F212" Offset="0x42" Value="0xCF" />
<Parameter Name="EdgeType_F212" Offset="0x43" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_F212" Offset="0x44" Value="0x65" />
<Parameter Name="EdgeLength_F212" Offset="0x45" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_F424" Offset="0x46" Value="0xCE" />
<Parameter Name="EdgeType_F424" Offset="0x47" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_F424" Offset="0x48" Value="0x55" />
<Parameter Name="EdgeLength_F424" Offset="0x49" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V100_26" Offset="0x4A" Value="0x00" />
<Parameter Name="EdgeType_V100_26" Offset="0x4B" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_V100_26" Offset="0x4C" Value="0x66" />
<Parameter Name="EdgeLength_V100_26" Offset="0x4D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V100_53" Offset="0x4E" Value="0x00" />
<Parameter Name="EdgeType_V100_53" Offset="0x4F" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_V100_53" Offset="0x50" Value="0x66" />
<Parameter Name="EdgeLength_V100_53" Offset="0x51" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V100_106" Offset="0x52" Value="0x00" />
<Parameter Name="EdgeType_V100_106" Offset="0x53" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_V100_106" Offset="0x54" Value="0x66" />
<Parameter Name="EdgeLength_V100_106" Offset="0x55" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V100_212" Offset="0x56" Value="0x00" />
<Parameter Name="EdgeType_V100_212" Offset="0x57" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_V100_212" Offset="0x58" Value="0x22" />
<Parameter Name="EdgeLength_V100_212" Offset="0x59" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V10_26" Offset="0x5A" Value="0xC0" />
<Parameter Name="EdgeType_V10_26" Offset="0x5B" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_V10_26" Offset="0x5C" Value="0x66" />
<Parameter Name="EdgeLength_V10_26" Offset="0x5D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V10_53" Offset="0x5E" Value="0xC0" />
<Parameter Name="EdgeType_V10_53" Offset="0x5F" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_V10_53" Offset="0x60" Value="0x23" />
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<Parameter Name="EdgeLength_V10_53" Offset="0x61" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V10_106" Offset="0x62" Value="0xC0" />
<Parameter Name="EdgeType_V10_106" Offset="0x63" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_V10_106" Offset="0x64" Value="0x23" />
<Parameter Name="EdgeLength_V10_106" Offset="0x65" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V10_212" Offset="0x66" Value="0xC0" />
<Parameter Name="EdgeType_V10_212" Offset="0x67" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_V10_212" Offset="0x68" Value="0x23" />
<Parameter Name="EdgeLength_V10_212" Offset="0x69" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_180003m3_tari18p88" Offset="0x6A" Value="0xC0" />
<Parameter Name="EdgeType_180003m3_tari18p88" Offset="0x6B" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_180003m3_tari18p88" Offset="0x6C" Value="0x66" />
<Parameter Name="EdgeLength_180003m3_tari18p88" Offset="0x6D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_180003m3_tari9p44" Offset="0x6E" Value="0xC0" />
<Parameter Name="EdgeType_180003m3_tari19p44" Offset="0x6F" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_180003m3_tari9p44" Offset="0x70" Value="0x66" />
<Parameter Name="EdgeLength_180003m3_tari9p44" Offset="0x71" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B_prime106" Offset="0x72" Value="0xCF" />
<Parameter Name="EdgeType_B_prime106" Offset="0x73" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_B_prime106" Offset="0x74" Value="0x67" />
<Parameter Name="EdgeLength_B_prime106" Offset="0x75" Value="0x10" />
</Region>
<Region RegionName="DPC_SETTINGS" RegionAccess="RW" RegionType="DATA">
<Parameter Name="Config" Offset="0x76" Value="0x77" />
<Parameter Name="TargetCurrent" Offset="0x77" Value="0x0132" />
<Parameter Name="Hysteresis" Offset="0x79" Value="0x14" />
<Parameter Name="Hysteresis_Unloading" Offset="0x7C" Value="0x0A" />
<Parameter Name="TXLDOVDDPALow" Offset="0x7D" Value="0x07" />
<Parameter Name="TXGSN" Offset="0x7E" Value="0x03" />
<Parameter Name="VDDPALowLimitcontrol" Offset="0x7F" Value="0x01" />
<Parameter Name="InitialRDOn_RFOn" Offset="0x80" Value="0x03" />
<Parameter Name="GuardTimeBeforeTx" Offset="0x87" Value="0x64" />
<Parameter Name="EnableDPCDuringFDT" Offset="0x88" Value="0x01" />
<Parameter Name="GuardTimeAfterRx" Offset="0x89" Value="0x01" />
<Parameter Name="Entry_00" Offset="0x8B" Value="0x0000137F" />
<Parameter Name="Entry_01" Offset="0x8F" Value="0x0000137F" />
<Parameter Name="Entry_02" Offset="0x93" Value="0x0000137F" />
<Parameter Name="Entry_03" Offset="0x97" Value="0x0000137F" />
<Parameter Name="Entry_04" Offset="0x9B" Value="0x0000137F" />
<Parameter Name="Entry_05" Offset="0x9F" Value="0x0000137F" />
<Parameter Name="Entry_06" Offset="0xA3" Value="0x0000007F" />
<Parameter Name="Entry_07" Offset="0xA7" Value="0x0000007F" />
<Parameter Name="Entry_08" Offset="0xAB" Value="0x0000007F" />
<Parameter Name="Entry_09" Offset="0xAF" Value="0x0000007F" />
<Parameter Name="Entry_10" Offset="0xB3" Value="0x0000007F" />
<Parameter Name="Entry_11" Offset="0xB7" Value="0x0000007F" />
<Parameter Name="Entry_12" Offset="0xBB" Value="0x0000007F" />
<Parameter Name="Entry_13" Offset="0xBF" Value="0x0000007F" />
<Parameter Name="Entry_14" Offset="0xC3" Value="0x0000007F" />
<Parameter Name="Entry_15" Offset="0xC7" Value="0x0000007F" />
<Parameter Name="Entry_16" Offset="0xCB" Value="0x0000007F" />
<Parameter Name="Entry_17" Offset="0xCF" Value="0x0000007F" />
<Parameter Name="Entry_18" Offset="0xD3" Value="0x0000007F" />
<Parameter Name="Entry_19" Offset="0xD7" Value="0x0000007F" />
<Parameter Name="Entry_20" Offset="0xDB" Value="0x0000007F" />
<Parameter Name="Entry_21" Offset="0xDF" Value="0x0000007F" />
<Parameter Name="Entry_22" Offset="0xE3" Value="0x0000007F" />
<Parameter Name="Entry_23" Offset="0xE7" Value="0x0000007D" />
<Parameter Name="Entry_24" Offset="0xEB" Value="0x0000007B" />
<Parameter Name="Entry_25" Offset="0xEF" Value="0x00000079" />
<Parameter Name="Entry_26" Offset="0xF3" Value="0x00000077" />
<Parameter Name="Entry_27" Offset="0xF7" Value="0x00000075" />
<Parameter Name="Entry_28" Offset="0xFB" Value="0x00000073" />
<Parameter Name="Entry_29" Offset="0xFF" Value="0x00000071" />
<Parameter Name="Entry_30" Offset="0x103" Value="0x0000006F" />
<Parameter Name="Entry_31" Offset="0x107" Value="0x0000006E" />
<Parameter Name="Entry_32" Offset="0x10B" Value="0x0000006C" />
<Parameter Name="Entry_33" Offset="0x10F" Value="0x0000006A" />
<Parameter Name="Entry_34" Offset="0x113" Value="0x00000068" />
<Parameter Name="Entry_35" Offset="0x117" Value="0x00000066" />
<Parameter Name="Entry_36" Offset="0x11B" Value="0x00000057" />
<Parameter Name="Entry_37" Offset="0x11F" Value="0x0000004B" />
<Parameter Name="Entry_38" Offset="0x123" Value="0x0000003F" />
<Parameter Name="Entry_39" Offset="0x127" Value="0x0000002D" />
<Parameter Name="Entry_40" Offset="0x12B" Value="0x00000000" />
<Parameter Name="Entry_41" Offset="0x12F" Value="0x00000000" />
<Parameter Name="Entry_42" Offset="0x133" Value="0x00000000" />
</Region>
<Region RegionName="ARC_SETTINGS" RegionAccess="RW" RegionType="DATA">
<Parameter Name="ArcConfig" Offset="0x137" Value="0x00E4" />
<Parameter Name="ArcVddpa" Offset="0x139" Value="0x2A24130E07" />
<Parameter Name="RmArcA_106" Offset="0x13E" Value="0x81348015802A8220C250" />
<Parameter Name="RmArcA_212" Offset="0x148" Value="0x001A00200030007F407F" />
<Parameter Name="RmArcA_424" Offset="0x152" Value="0x001A00200040007F407F" />
<Parameter Name="RmArcA_848" Offset="0x15C" Value="0x001A00200040007F407F" />
<Parameter Name="RmArcB_106" Offset="0x166" Value="0x001A0020003000404050" />
<Parameter Name="RmArcB_212" Offset="0x170" Value="0x001A002000400050407F" />
<Parameter Name="RmArcB_424" Offset="0x17A" Value="0x001A002000400050407F" />
<Parameter Name="RmArcB_848" Offset="0x184" Value="0x001A002000400050407F" />
<Parameter Name="RmArcF_212" Offset="0x18E" Value="0x001A00200040007F407F" />
<Parameter Name="RmArcF_424" Offset="0x198" Value="0x001A00200040007F407F" />
<Parameter Name="RmArcV_6p6" Offset="0x1A2" Value="0x000A000A000A000A400A" />
<Parameter Name="RmArcV_26" Offset="0x1AC" Value="0x000A000A002F002F402F" />
<Parameter Name="RmArcV_53" Offset="0x1B6" Value="0x010A010A011F011F411F" />
<Parameter Name="RmArcV_106" Offset="0x1C0" Value="0x000A000A002F002F402F" />
<Parameter Name="RmArcV_212" Offset="0x1CA" Value="0x000A000A002F002F402F" />
<Parameter Name="RmArc180003m3_SC424_4Man" Offset="0x1D4" Value="0x0114011F011F001F401F" />
<Parameter Name="RmArc180003m3_SC424_2Man" Offset="0x1DE" Value="0x0014001F003F004F404F" />
<Parameter Name="RmArc180003m3_SC848_4Man" Offset="0x1E8" Value="0x0114011F011F001F401F" />
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<Parameter Name="RmArc180003m3_SC848_2Man" Offset="0x1F2" Value="0x0014001F003F004F404F" />
<Parameter Name="RmArc_AI_106" Offset="0x1FC" Value="0x000A000A000A000A400A" />
<Parameter Name="RmArc_AI_212" Offset="0x206" Value="0x000A000A000A000A400A" />
<Parameter Name="RmArc_AI_424" Offset="0x210" Value="0x000A000A000A000A400A" />
</Region>
<Region RegionName="RF_CLOCK_DPLL_COM" RegionAccess="RW" RegionType="DATA">
<Parameter Name="DPLL_INIT_Default" Offset="0x2A6" Value="0x002D1327" />
<Parameter Name="DPLL_GEAR_Default" Offset="0x2AA" Value="0x04C1FEFE" />
<Parameter Name="DPLL_CONTROL" Offset="0x2AE" Value="0x00000C03" />
</Region>
<Region RegionName="AUTOCOLL_CFG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RfDebounceTimeout" Offset="0x2B2" Value="0x10" />
<Parameter Name="SensRes" Offset="0x2B3" Value="0x0042" />
<Parameter Name="NfcID1" Offset="0x2B5" Value="0xCCBBAA" />
<Parameter Name="SelRes" Offset="0x2B8" Value="0x60" />
<Parameter Name="PollRes" Offset="0x2B9" Value="0xFFD08584424B0B100814119814011401FE01" />
<Parameter Name="RandomUIDEnable" Offset="0x2CB" Value="0x00" />
</Region>
<Region RegionName="MFC_CFG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="MfcAuthTimeout" Offset="0x2CC" Value="0x0500" />
</Region>
<Region RegionName="APC_RSSI" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RssiTimer" Offset="0x2DA" Value="0x0423" />
<Parameter Name="RssiTimerFirstPeriod" Offset="0x2DC" Value="0x013D" />
<Parameter Name="RssiCtrl_00_AB" Offset="0x2DE" Value="0x09" />
<Parameter Name="RssiNbEntriesAB" Offset="0x2DF" Value="0x16" />
<Parameter Name="RssiThresholdAB_01" Offset="0x2E0" Value="0x2816" />
<Parameter Name="ArbPhaseAB_01" Offset="0x2E2" Value="0x0000" />
<Parameter Name="RssiThresholdAB_02" Offset="0x2E4" Value="0x3215" />
<Parameter Name="ArbPhaseAB_02" Offset="0x2E6" Value="0x0000" />
<Parameter Name="RssiThresholdAB_03" Offset="0x2E8" Value="0x3B6E" />
<Parameter Name="ArbPhaseAB_03" Offset="0x2EA" Value="0x0000" />
<Parameter Name="RssiThresholdAB_04" Offset="0x2EC" Value="0x456A" />
<Parameter Name="ArbPhaseAB_04" Offset="0x2EE" Value="0x0000" />
<Parameter Name="RssiThresholdAB_05" Offset="0x2F0" Value="0x4FDC" />
<Parameter Name="ArbPhaseAB_05" Offset="0x2F2" Value="0x0000" />
<Parameter Name="RssiThresholdAB_06" Offset="0x2F4" Value="0x5983" />
<Parameter Name="ArbPhaseAB_06" Offset="0x2F6" Value="0x0000" />
<Parameter Name="RssiThresholdAB_07" Offset="0x2F8" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_07" Offset="0x2FA" Value="0x0000" />
<Parameter Name="RssiThresholdAB_08" Offset="0x2FC" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_08" Offset="0x2FE" Value="0x0000" />
<Parameter Name="RssiThresholdAB_09" Offset="0x300" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_09" Offset="0x302" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0A" Offset="0x304" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0A" Offset="0x306" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0B" Offset="0x308" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0B" Offset="0x30A" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0C" Offset="0x30C" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0C" Offset="0x30E" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0D" Offset="0x310" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0D" Offset="0x312" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0E" Offset="0x314" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0E" Offset="0x316" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0F" Offset="0x318" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0F" Offset="0x31A" Value="0x0000" />
<Parameter Name="RssiThresholdAB_10" Offset="0x31C" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_10" Offset="0x31E" Value="0x0000" />
<Parameter Name="RssiThresholdAB_11" Offset="0x320" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_11" Offset="0x322" Value="0x0000" />
<Parameter Name="RssiThresholdAB_12" Offset="0x324" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_12" Offset="0x326" Value="0x0000" />
<Parameter Name="RssiThresholdAB_13" Offset="0x328" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_13" Offset="0x32A" Value="0x0000" />
<Parameter Name="RssiThresholdAB_14" Offset="0x32C" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_14" Offset="0x32E" Value="0x0000" />
<Parameter Name="RssiThresholdAB_15" Offset="0x330" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_15" Offset="0x332" Value="0x0000" />
<Parameter Name="RssiThresholdAB_16" Offset="0x334" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_16" Offset="0x336" Value="0x0000" />
<Parameter Name="RssiThresholdAB_17" Offset="0x338" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_17" Offset="0x33A" Value="0x0000" />
<Parameter Name="RssiThresholdAB_18" Offset="0x33C" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_18" Offset="0x33E" Value="0x0000" />
<Parameter Name="RssiCtrl_00_F" Offset="0x340" Value="0x09" />
<Parameter Name="RssiNbEntriesF" Offset="0x341" Value="0x16" />
<Parameter Name="RssiThresholdF_01" Offset="0x342" Value="0x2816" />
<Parameter Name="ArbPhaseF_01" Offset="0x344" Value="0x0000" />
<Parameter Name="RssiThresholdF_02" Offset="0x346" Value="0x3215" />
<Parameter Name="ArbPhaseF_02" Offset="0x348" Value="0x0000" />
<Parameter Name="RssiThresholdF_03" Offset="0x34A" Value="0x3B6E" />
<Parameter Name="ArbPhaseF_03" Offset="0x34C" Value="0x0000" />
<Parameter Name="RssiThresholdF_04" Offset="0x34E" Value="0x456A" />
<Parameter Name="ArbPhaseF_04" Offset="0x350" Value="0x0000" />
<Parameter Name="RssiThresholdF_05" Offset="0x352" Value="0x4FDC" />
<Parameter Name="ArbPhaseF_05" Offset="0x354" Value="0x0000" />
<Parameter Name="RssiThresholdF_06" Offset="0x356" Value="0x5983" />
<Parameter Name="ArbPhaseF_06" Offset="0x358" Value="0x0000" />
<Parameter Name="RssiThresholdF_07" Offset="0x35A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_07" Offset="0x35C" Value="0x0000" />
<Parameter Name="RssiThresholdF_08" Offset="0x35E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_08" Offset="0x360" Value="0x0000" />
<Parameter Name="RssiThresholdF_09" Offset="0x362" Value="0x96F9" />
<Parameter Name="ArbPhaseF_09" Offset="0x364" Value="0x0000" />
<Parameter Name="RssiThresholdF_0A" Offset="0x366" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0A" Offset="0x368" Value="0x0000" />
<Parameter Name="RssiThresholdF_0B" Offset="0x36A" Value="0x96F9" />
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
259 / 308
NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="ArbPhaseF_0B" Offset="0x36C" Value="0x0000" />
<Parameter Name="RssiThresholdF_0C" Offset="0x36E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0C" Offset="0x370" Value="0x0000" />
<Parameter Name="RssiThresholdF_0D" Offset="0x372" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0D" Offset="0x374" Value="0x0000" />
<Parameter Name="RssiThresholdF_0E" Offset="0x376" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0E" Offset="0x378" Value="0x0000" />
<Parameter Name="RssiThresholdF_0F" Offset="0x37A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0F" Offset="0x37C" Value="0x0000" />
<Parameter Name="RssiThresholdF_10" Offset="0x37E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_10" Offset="0x380" Value="0x0000" />
<Parameter Name="RssiThresholdF_11" Offset="0x382" Value="0x96F9" />
<Parameter Name="ArbPhaseF_11" Offset="0x384" Value="0x0000" />
<Parameter Name="RssiThresholdF_12" Offset="0x386" Value="0x96F9" />
<Parameter Name="ArbPhaseF_12" Offset="0x388" Value="0x0000" />
<Parameter Name="RssiThresholdF_13" Offset="0x38A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_13" Offset="0x38C" Value="0x0000" />
<Parameter Name="RssiThresholdF_14" Offset="0x38E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_14" Offset="0x390" Value="0x0000" />
<Parameter Name="RssiThresholdF_15" Offset="0x392" Value="0x96F9" />
<Parameter Name="ArbPhaseF_15" Offset="0x394" Value="0x0000" />
<Parameter Name="RssiThresholdF_16" Offset="0x396" Value="0x96F9" />
<Parameter Name="ArbPhaseF_16" Offset="0x398" Value="0x0000" />
<Parameter Name="RssiThresholdF_17" Offset="0x39A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_17" Offset="0x39C" Value="0x0000" />
<Parameter Name="RssiThresholdF_18" Offset="0x39E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_18" Offset="0x3A0" Value="0x0000" />
</Region>
<Region RegionName="APC_TX" RegionAccess="RW" RegionType="DATA">
<Parameter Name="TxParamEntry_00_ID" Offset="0x3A2" Value="0x40" />
<Parameter Name="TxParamEntry_00_Tx1" Offset="0x3A3" Value="0x00" />
<Parameter Name="TxParamEntry_00_Tx2" Offset="0x3A4" Value="0x64" />
<Parameter Name="TxParamEntry_01_ID" Offset="0x3A5" Value="0x41" />
<Parameter Name="TxParamEntry_01_Tx1" Offset="0x3A6" Value="0x00" />
<Parameter Name="TxParamEntry_01_Tx2" Offset="0x3A7" Value="0x64" />
<Parameter Name="TxParamEntry_02_ID" Offset="0x3A8" Value="0x42" />
<Parameter Name="TxParamEntry_02_Tx1" Offset="0x3A9" Value="0x00" />
<Parameter Name="TxParamEntry_02_Tx2" Offset="0x3AA" Value="0x64" />
<Parameter Name="TxParamEntry_03_ID" Offset="0x3AB" Value="0x43" />
<Parameter Name="TxParamEntry_03_Tx1" Offset="0x3AC" Value="0x00" />
<Parameter Name="TxParamEntry_03_Tx2" Offset="0x3AD" Value="0x64" />
<Parameter Name="TxParamEntry_04_ID" Offset="0x3AE" Value="0x44" />
<Parameter Name="TxParamEntry_04_Tx1" Offset="0x3AF" Value="0x00" />
<Parameter Name="TxParamEntry_04_Tx2" Offset="0x3B0" Value="0x64" />
<Parameter Name="TxParamEntry_05_ID" Offset="0x3B1" Value="0x45" />
<Parameter Name="TxParamEntry_05_Tx1" Offset="0x3B2" Value="0x00" />
<Parameter Name="TxParamEntry_05_Tx2" Offset="0x3B3" Value="0x64" />
<Parameter Name="TxParamEntry_06_ID" Offset="0x3B4" Value="0x46" />
<Parameter Name="TxParamEntry_06_Tx1" Offset="0x3B5" Value="0x00" />
<Parameter Name="TxParamEntry_06_Tx2" Offset="0x3B6" Value="0x64" />
<Parameter Name="TxParamEntry_07_ID" Offset="0x3B7" Value="0x47" />
<Parameter Name="TxParamEntry_07_Tx1" Offset="0x3B8" Value="0x00" />
<Parameter Name="TxParamEntry_07_Tx2" Offset="0x3B9" Value="0x64" />
<Parameter Name="TxParamEntry_08_ID" Offset="0x3BA" Value="0x48" />
<Parameter Name="TxParamEntry_08_Tx1" Offset="0x3BB" Value="0x00" />
<Parameter Name="TxParamEntry_08_Tx2" Offset="0x3BC" Value="0x64" />
<Parameter Name="TxParamEntry_09_ID" Offset="0x3BD" Value="0x49" />
<Parameter Name="TxParamEntry_09_Tx1" Offset="0x3BE" Value="0x00" />
<Parameter Name="TxParamEntry_09_Tx2" Offset="0x3BF" Value="0x64" />
<Parameter Name="TxParamEntry_0A_ID" Offset="0x3C0" Value="0x4A" />
<Parameter Name="TxParamEntry_0A_Tx1" Offset="0x3C1" Value="0x00" />
<Parameter Name="TxParamEntry_0A_Tx2" Offset="0x3C2" Value="0x5D" />
<Parameter Name="TxParamEntry_0B_ID" Offset="0x3C3" Value="0x4B" />
<Parameter Name="TxParamEntry_0B_Tx1" Offset="0x3C4" Value="0x00" />
<Parameter Name="TxParamEntry_0B_Tx2" Offset="0x3C5" Value="0x56" />
<Parameter Name="TxParamEntry_0C_ID" Offset="0x3C6" Value="0x4C" />
<Parameter Name="TxParamEntry_00C_Tx1" Offset="0x3C7" Value="0x00" />
<Parameter Name="TxParamEntry_00C_Tx2" Offset="0x3C8" Value="0x4F" />
<Parameter Name="TxParamEntry_0D_ID" Offset="0x3C9" Value="0x4D" />
<Parameter Name="TxParamEntry_0D_Tx1" Offset="0x3CA" Value="0x00" />
<Parameter Name="TxParamEntry_0D_Tx2" Offset="0x3CB" Value="0x47" />
<Parameter Name="TxParamEntry_0E_ID" Offset="0x3CC" Value="0x4E" />
<Parameter Name="TxParamEntry_0E_Tx1" Offset="0x3CD" Value="0x00" />
<Parameter Name="TxParamEntry_0E_Tx2" Offset="0x3CE" Value="0x3F" />
<Parameter Name="TxParamEntry_0F_ID" Offset="0x3CF" Value="0x4F" />
<Parameter Name="TxParamEntry_0F_Tx1" Offset="0x3D0" Value="0x00" />
<Parameter Name="TxParamEntry_0F_Tx2" Offset="0x3D1" Value="0x37" />
<Parameter Name="TxParamEntry_10_ID" Offset="0x3D2" Value="0x50" />
<Parameter Name="TxParamEntry_10_Tx1" Offset="0x3D3" Value="0x00" />
<Parameter Name="TxParamEntry_10_Tx2" Offset="0x3D4" Value="0x37" />
<Parameter Name="TxParamEntry_11_ID" Offset="0x3D5" Value="0x51" />
<Parameter Name="TxParamEntry_11_Tx1" Offset="0x3D6" Value="0x00" />
<Parameter Name="TxParamEntry_11_Tx2" Offset="0x3D7" Value="0x37" />
<Parameter Name="TxParamEntry_12_ID" Offset="0x3D8" Value="0x52" />
<Parameter Name="TxParamEntry_12_Tx1" Offset="0x3D9" Value="0x00" />
<Parameter Name="TxParamEntry_12_Tx2" Offset="0x3DA" Value="0x37" />
<Parameter Name="TxParamEntry_13_ID" Offset="0x3DB" Value="0x53" />
<Parameter Name="TxParamEntry_13_Tx1" Offset="0x3DC" Value="0x00" />
<Parameter Name="TxParamEntry_13_Tx2" Offset="0x3DD" Value="0x37" />
<Parameter Name="TxParamEntry_14_ID" Offset="0x3DE" Value="0x54" />
<Parameter Name="TxParamEntry_14_Tx1" Offset="0x3DF" Value="0x00" />
<Parameter Name="TxParamEntry_14_Tx2" Offset="0x3E0" Value="0x37" />
<Parameter Name="TxParamEntry_15_ID" Offset="0x3E1" Value="0x55" />
<Parameter Name="TxParamEntry_15_Tx1" Offset="0x3E2" Value="0x00" />
<Parameter Name="TxParamEntry_15_Tx2" Offset="0x3E3" Value="0x37" />
<Parameter Name="TxParamEntry_16_ID" Offset="0x3E4" Value="0x56" />
<Parameter Name="TxParamEntry_16_Tx1" Offset="0x3E5" Value="0x00" />
<Parameter Name="TxParamEntry_16_Tx2" Offset="0x3E6" Value="0x37" />
<Parameter Name="TxParamEntry_17_ID" Offset="0x3E7" Value="0x57" />
<Parameter Name="TxParamEntry_17_Tx1" Offset="0x3E8" Value="0x00" />
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
260 / 308
NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="TxParamEntry_17_Tx2" Offset="0x3E9" Value="0x37" />
<Parameter Name="TxParamEntry_18_ID" Offset="0x3EA" Value="0x58" />
<Parameter Name="TxParamEntry_18_Tx1" Offset="0x3EB" Value="0x00" />
<Parameter Name="TxParamEntry_18_Tx2" Offset="0x3EC" Value="0x37" />
<Parameter Name="TxParamEntry_19_ID" Offset="0x3ED" Value="0x59" />
<Parameter Name="TxParamEntry_19_Tx1" Offset="0x3EE" Value="0x00" />
<Parameter Name="TxParamEntry_19_Tx2" Offset="0x3EF" Value="0x37" />
<Parameter Name="TxParamEntry_1A_ID" Offset="0x3F0" Value="0x5A" />
<Parameter Name="TxParamEntry_1A_Tx1" Offset="0x3F1" Value="0x00" />
<Parameter Name="TxParamEntry_1A_Tx2" Offset="0x3F2" Value="0x37" />
<Parameter Name="TxParamEntry_1B_ID" Offset="0x3F3" Value="0x5B" />
<Parameter Name="TxParamEntry_1B_Tx1" Offset="0x3F4" Value="0x00" />
<Parameter Name="TxParamEntry_1B_Tx2" Offset="0x3F5" Value="0x37" />
<Parameter Name="TxParamEntry_1C_ID" Offset="0x3F6" Value="0x5C" />
<Parameter Name="TxParamEntry_1C_Tx1" Offset="0x3F7" Value="0x00" />
<Parameter Name="TxParamEntry_1C_Tx2" Offset="0x3F8" Value="0x37" />
<Parameter Name="TxParamEntry_1D_ID" Offset="0x3F9" Value="0x5D" />
<Parameter Name="TxParamEntry_1D_Tx1" Offset="0x3FA" Value="0x00" />
<Parameter Name="TxParamEntry_1D_Tx2" Offset="0x3FB" Value="0x37" />
<Parameter Name="TxParamEntry_1E_ID" Offset="0x3FC" Value="0x5E" />
<Parameter Name="TxParamEntry_1E_Tx1" Offset="0x3FD" Value="0x00" />
<Parameter Name="TxParamEntry_1E_Tx2" Offset="0x3FE" Value="0x37" />
<Parameter Name="TxParamEntry_1F_ID" Offset="0x3FF" Value="0x5F" />
<Parameter Name="TxParamEntry_1F_Tx1" Offset="0x400" Value="0x00" />
<Parameter Name="TxParamEntry_1F_Tx2" Offset="0x401" Value="0x37" />
<Parameter Name="TxParamEntry_20_ID" Offset="0x402" Value="0x60" />
<Parameter Name="TxParamEntry_20_Tx1" Offset="0x403" Value="0x00" />
<Parameter Name="TxParamEntry_20_Tx2" Offset="0x404" Value="0x37" />
<Parameter Name="TxParamEntry_21_ID" Offset="0x405" Value="0x61" />
<Parameter Name="TxParamEntry_21_Tx1" Offset="0x406" Value="0x00" />
<Parameter Name="TxParamEntry_21_Tx2" Offset="0x407" Value="0x37" />
<Parameter Name="TxParamEntry_22_ID" Offset="0x408" Value="0x62" />
<Parameter Name="TxParamEntry_22_Tx1" Offset="0x409" Value="0x00" />
<Parameter Name="TxParamEntry_22_Tx2" Offset="0x40A" Value="0x37" />
<Parameter Name="TxParamEntry_23_ID" Offset="0x40B" Value="0x63" />
<Parameter Name="TxParamEntry_23_Tx1" Offset="0x40C" Value="0x00" />
<Parameter Name="TxParamEntry_23_Tx2" Offset="0x40D" Value="0x37" />
<Parameter Name="TxParamEntry_24_ID" Offset="0x40E" Value="0x64" />
<Parameter Name="TxParamEntry_24_Tx1" Offset="0x40F" Value="0x00" />
<Parameter Name="TxParamEntry_24_Tx2" Offset="0x410" Value="0x37" />
<Parameter Name="TxParamEntry_25_ID" Offset="0x411" Value="0x65" />
<Parameter Name="TxParamEntry_25_Tx1" Offset="0x412" Value="0x00" />
<Parameter Name="TxParamEntry_25_Tx2" Offset="0x413" Value="0x37" />
<Parameter Name="TxParamEntry_26_ID" Offset="0x414" Value="0x66" />
<Parameter Name="TxParamEntry_26_Tx1" Offset="0x415" Value="0x00" />
<Parameter Name="TxParamEntry_26_Tx2" Offset="0x416" Value="0x37" />
<Parameter Name="TxParamEntry_27_ID" Offset="0x417" Value="0x67" />
<Parameter Name="TxParamEntry_27_Tx1" Offset="0x418" Value="0x00" />
<Parameter Name="TxParamEntry_27_Tx2" Offset="0x419" Value="0x37" />
<Parameter Name="TxParamEntry_28_ID" Offset="0x41A" Value="0x68" />
<Parameter Name="TxParamEntry_28_Tx1" Offset="0x41B" Value="0x00" />
<Parameter Name="TxParamEntry_28_Tx2" Offset="0x41C" Value="0x37" />
<Parameter Name="TxParamEntry_29_ID" Offset="0x41D" Value="0x69" />
<Parameter Name="TxParamEntry_29_Tx1" Offset="0x41E" Value="0x00" />
<Parameter Name="TxParamEntry_29_Tx2" Offset="0x41F" Value="0x37" />
<Parameter Name="TxParamEntry_2A_ID" Offset="0x420" Value="0x6A" />
<Parameter Name="TxParamEntry_2A_Tx1" Offset="0x421" Value="0x00" />
<Parameter Name="TxParamEntry_2A_Tx2" Offset="0x422" Value="0x37" />
<Parameter Name="TxParamEntry_2B_ID" Offset="0x423" Value="0x6B" />
<Parameter Name="TxParamEntry_2B_Tx1" Offset="0x424" Value="0x00" />
<Parameter Name="TxParamEntry_2B_Tx2" Offset="0x425" Value="0x37" />
<Parameter Name="TxParamEntry_2C_ID" Offset="0x426" Value="0x6C" />
<Parameter Name="TxParamEntry_2C_Tx1" Offset="0x427" Value="0x00" />
<Parameter Name="TxParamEntry_2C_Tx2" Offset="0x428" Value="0x37" />
<Parameter Name="TxParamEntry_2D_ID" Offset="0x429" Value="0x6D" />
<Parameter Name="TxParamEntry_2D_Tx1" Offset="0x42A" Value="0x00" />
<Parameter Name="TxParamEntry_2D_Tx2" Offset="0x42B" Value="0x37" />
<Parameter Name="TxParamEntry_2E_ID" Offset="0x42C" Value="0x6E" />
<Parameter Name="TxParamEntry_2E_Tx1" Offset="0x42D" Value="0x00" />
<Parameter Name="TxParamEntry_2E_Tx2" Offset="0x42E" Value="0x37" />
<Parameter Name="TxParamEntry_2F_ID" Offset="0x42F" Value="0x6F" />
<Parameter Name="TxParamEntry_2F_Tx1" Offset="0x430" Value="0x00" />
<Parameter Name="TxParamEntry_2F_Tx2" Offset="0x431" Value="0x37" />
<Parameter Name="TxParamEntry_30_ID" Offset="0x432" Value="0x70" />
<Parameter Name="TxParamEntry_30_Tx1" Offset="0x433" Value="0x00" />
<Parameter Name="TxParamEntry_30_Tx2" Offset="0x434" Value="0x37" />
<Parameter Name="TxParamEntry_31_ID" Offset="0x435" Value="0x71" />
<Parameter Name="TxParamEntry_31_Tx1" Offset="0x436" Value="0x00" />
<Parameter Name="TxParamEntry_31_Tx2" Offset="0x437" Value="0x37" />
<Parameter Name="TxParamEntry_32_ID" Offset="0x438" Value="0x72" />
<Parameter Name="TxParamEntry_32_Tx1" Offset="0x439" Value="0x00" />
<Parameter Name="TxParamEntry_32_Tx2" Offset="0x43A" Value="0x37" />
<Parameter Name="TxParamEntry_33_ID" Offset="0x43B" Value="0x73" />
<Parameter Name="TxParamEntry_33_Tx1" Offset="0x43C" Value="0x00" />
<Parameter Name="TxParamEntry_33_Tx2" Offset="0x43D" Value="0x37" />
<Parameter Name="TxParamEntry_34_ID" Offset="0x43E" Value="0x74" />
<Parameter Name="TxParamEntry_34_Tx1" Offset="0x43F" Value="0x00" />
<Parameter Name="TxParamEntry_34_Tx2" Offset="0x440" Value="0x37" />
<Parameter Name="TxParamEntry_35_ID" Offset="0x441" Value="0x75" />
<Parameter Name="TxParamEntry_35_Tx1" Offset="0x442" Value="0x00" />
<Parameter Name="TxParamEntry_35_Tx2" Offset="0x443" Value="0x37" />
<Parameter Name="TxParamEntry_36_ID" Offset="0x444" Value="0x76" />
<Parameter Name="TxParamEntry_36_Tx1" Offset="0x445" Value="0x00" />
<Parameter Name="TxParamEntry_36_Tx2" Offset="0x446" Value="0x37" />
<Parameter Name="TxParamEntry_37_ID" Offset="0x447" Value="0x77" />
<Parameter Name="TxParamEntry_37_Tx1" Offset="0x448" Value="0x00" />
<Parameter Name="TxParamEntry_37_Tx2" Offset="0x449" Value="0x37" />
<Parameter Name="TxParamEntry_38_ID" Offset="0x44A" Value="0x78" />
<Parameter Name="TxParamEntry_38_Tx1" Offset="0x44B" Value="0x00" />
<Parameter Name="TxParamEntry_38_Tx2" Offset="0x44C" Value="0x37" />
<Parameter Name="TxParamEntry_39_ID" Offset="0x44D" Value="0x79" />
PN5190B1
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© NXP B.V. 2021. All rights reserved.
Product data sheet
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Rev. 3.0 — 21 April 2021
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NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="TxParamEntry_39_Tx1" Offset="0x44E" Value="0x00" />
<Parameter Name="TxParamEntry_39_Tx2" Offset="0x44F" Value="0x37" />
<Parameter Name="TxParamEntry_3A_ID" Offset="0x450" Value="0x7A" />
<Parameter Name="TxParamEntry_3A_Tx1" Offset="0x451" Value="0x00" />
<Parameter Name="TxParamEntry_3A_Tx2" Offset="0x452" Value="0x37" />
<Parameter Name="TxParamEntry_3B_ID" Offset="0x453" Value="0x7B" />
<Parameter Name="TxParamEntry_3B_Tx1" Offset="0x454" Value="0x00" />
<Parameter Name="TxParamEntry_3B_Tx2" Offset="0x455" Value="0x37" />
<Parameter Name="TxParamEntry_3C_ID" Offset="0x456" Value="0x7C" />
<Parameter Name="TxParamEntry_3C_Tx1" Offset="0x457" Value="0x00" />
<Parameter Name="TxParamEntry_3C_Tx2" Offset="0x458" Value="0x37" />
<Parameter Name="TxParamEntry_3D_ID" Offset="0x459" Value="0x7D" />
<Parameter Name="TxParamEntry_3D_Tx1" Offset="0x45A" Value="0x00" />
<Parameter Name="TxParamEntry_3D_Tx2" Offset="0x45B" Value="0x37" />
<Parameter Name="TxParamEntry_3E_ID" Offset="0x45C" Value="0x7E" />
<Parameter Name="TxParamEntry_3E_Tx1" Offset="0x45D" Value="0x00" />
<Parameter Name="TxParamEntry_3E_Tx2" Offset="0x45E" Value="0x37" />
<Parameter Name="TxParamEntry_3F_ID" Offset="0x45F" Value="0x7F" />
<Parameter Name="TxParamEntry_3F_Tx1" Offset="0x460" Value="0x00" />
<Parameter Name="TxParamEntry_3F_Tx2" Offset="0x461" Value="0x37" />
<Parameter Name="TxParamEntry_40_ID" Offset="0x462" Value="0x7F" />
<Parameter Name="TxParamEntry_40_Tx1" Offset="0x463" Value="0x00" />
<Parameter Name="TxParamEntry_40_Tx2" Offset="0x464" Value="0x37" />
<Parameter Name="TxParamEntry_41_ID" Offset="0x465" Value="0x7F" />
<Parameter Name="TxParamEntry_41_Tx1" Offset="0x466" Value="0x00" />
<Parameter Name="TxParamEntry_41_Tx2" Offset="0x467" Value="0x37" />
<Parameter Name="TxParamEntry_42_ID" Offset="0x468" Value="0x7F" />
<Parameter Name="TxParamEntry_42_Tx1" Offset="0x469" Value="0x00" />
<Parameter Name="TxParamEntry_42_Tx2" Offset="0x46A" Value="0x37" />
<Parameter Name="TxParamEntry_43_ID" Offset="0x46B" Value="0x7F" />
<Parameter Name="TxParamEntry_43_Tx1" Offset="0x46C" Value="0x00" />
<Parameter Name="TxParamEntry_43_Tx2" Offset="0x46D" Value="0x37" />
<Parameter Name="TxParamEntry_44_ID" Offset="0x46E" Value="0x7F" />
<Parameter Name="TxParamEntry_44_Tx1" Offset="0x46F" Value="0x00" />
<Parameter Name="TxParamEntry_44_Tx2" Offset="0x470" Value="0x37" />
<Parameter Name="TxParamEntry_45_ID" Offset="0x471" Value="0x7F" />
<Parameter Name="TxParamEntry_45_Tx1" Offset="0x472" Value="0x00" />
<Parameter Name="TxParamEntry_45_Tx2" Offset="0x473" Value="0x37" />
<Parameter Name="TxParamEntry_46_ID" Offset="0x474" Value="0x7F" />
<Parameter Name="TxParamEntry_46_Tx1" Offset="0x475" Value="0x00" />
<Parameter Name="TxParamEntry_46_Tx2" Offset="0x476" Value="0x37" />
<Parameter Name="TxParamEntry_47_ID" Offset="0x477" Value="0x7F" />
<Parameter Name="TxParamEntry_47_Tx1" Offset="0x478" Value="0x00" />
<Parameter Name="TxParamEntry_47_Tx2" Offset="0x479" Value="0x37" />
<Parameter Name="TxParamEntry_48_ID" Offset="0x47A" Value="0x7F" />
<Parameter Name="TxParamEntry_48_Tx1" Offset="0x47B" Value="0x00" />
<Parameter Name="TxParamEntry_48_Tx2" Offset="0x47C" Value="0x37" />
<Parameter Name="TxParamEntry_49_ID" Offset="0x47D" Value="0x7F" />
<Parameter Name="TxParamEntry_49_Tx1" Offset="0x47E" Value="0x00" />
<Parameter Name="TxParamEntry_49_Tx2" Offset="0x47F" Value="0x37" />
<Parameter Name="TxParamEntry_4A_ID" Offset="0x480" Value="0x7F" />
<Parameter Name="TxParamEntry_4A_Tx1" Offset="0x481" Value="0x00" />
<Parameter Name="TxParamEntry_4A_Tx2" Offset="0x482" Value="0x37" />
<Parameter Name="TxParamEntry_4B_ID" Offset="0x483" Value="0x7F" />
<Parameter Name="TxParamEntry_4B_Tx1" Offset="0x484" Value="0x00" />
<Parameter Name="TxParamEntry_4B_Tx2" Offset="0x485" Value="0x37" />
<Parameter Name="TxParamEntry_4C_ID" Offset="0x486" Value="0x7F" />
<Parameter Name="TxParamEntry_4C_Tx1" Offset="0x487" Value="0x00" />
<Parameter Name="TxParamEntry_4C_Tx2" Offset="0x488" Value="0x37" />
<Parameter Name="TxParamEntry_4D_ID" Offset="0x489" Value="0x7F" />
<Parameter Name="TxParamEntry_4D_Tx1" Offset="0x48A" Value="0x00" />
<Parameter Name="TxParamEntry_4D_Tx2" Offset="0x48B" Value="0x37" />
<Parameter Name="TxParamEntry_4E_ID" Offset="0x48C" Value="0x7F" />
<Parameter Name="TxParamEntry_4E_Tx1" Offset="0x48D" Value="0x00" />
<Parameter Name="TxParamEntry_4E_Tx2" Offset="0x48E" Value="0x37" />
<Parameter Name="dummy" Offset="0x48F" Value="0x000000" />
</Region>
<Region RegionName="LPCD_SETTINGS" RegionAccess="RW" RegionType="DATA">
<Parameter Name="avg_samples" Offset="0x492" Value="0x06" />
<Parameter Name="lpcd_rssi_target" Offset="0x494" Value="0x02A3" />
<Parameter Name="lpcd_rssi_hyst" Offset="0x496" Value="0x1F" />
<Parameter Name="Config" Offset="0x497" Value="0x003B" />
<Parameter Name="lpcd_threshold_coarse" Offset="0x49A" Value="0x00500050" />
<Parameter Name="lpcd_threshold_fine" Offset="0x49E" Value="0x7FFF7FFF" />
</Region>
<Region RegionName="ULPCD_CONFIG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="Voltage_Ctrl" Offset="0x4C6" Value="0x6A" />
</Region>
<Region RegionName="ULPCD_SETTINGS" RegionAccess="RW" RegionType="DATA">
<Parameter Name="rssi_nsp" Offset="0x4C9" Value="0x10" />
<Parameter Name="rssi_no_samples" Offset="0x4CA" Value="0x00" />
<Parameter Name="thresh_lvl" Offset="0x4CB" Value="0x0C" />
<Parameter Name="polarity" Offset="0x4CC" Value="0x01" />
</Region>
<Region RegionName="TXIRQ_GUARD" RegionAccess="RW" RegionType="DATA">
<Parameter Name="TXIRQ_GuardTime" Offset="0x559" Value="0x000FFFFF" />
</Region>
<Region RegionName="FDT_DEFAULT" RegionAccess="RW" RegionType="DATA">
<Parameter Name="FDT_DefaultVal" Offset="0x55D" Value="0x000472AC" />
</Region>
<Region RegionName="RXIRQ_GUARD" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RXIRQ_GuardTime" Offset="0x561" Value="0x000F4240" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_CORR" RegionAccess="RW" RegionType="DATA">
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
262 / 308
NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="Correction_Entry0" Offset="0xBAD" Value="0x0000" />
<Parameter Name="Correction_Entry1" Offset="0xBAF" Value="0x0000" />
<Parameter Name="Correction_Entry2" Offset="0xBB1" Value="0x0000" />
<Parameter Name="Correction_Entry3" Offset="0xBB3" Value="0x0000" />
<Parameter Name="Correction_Entry4" Offset="0xBB5" Value="0x0000" />
<Parameter Name="Correction_Entry5" Offset="0xBB7" Value="0x0000" />
<Parameter Name="Correction_Entry6" Offset="0xBB9" Value="0x0000" />
<Parameter Name="Correction_Entry7" Offset="0xBBB" Value="0x0000" />
<Parameter Name="Correction_Entry8" Offset="0xBBD" Value="0x0000" />
<Parameter Name="Correction_Entry9" Offset="0xBBF" Value="0x0000" />
<Parameter Name="Correction_Entry10" Offset="0xBC1" Value="0x0000" />
<Parameter Name="Correction_Entry11" Offset="0xBC3" Value="0x0000" />
<Parameter Name="Correction_Entry12" Offset="0xBC5" Value="0x0000" />
<Parameter Name="Correction_Entry13" Offset="0xBC7" Value="0x0000" />
<Parameter Name="Correction_Entry14" Offset="0xBC9" Value="0x0000" />
<Parameter Name="Correction_Entry15" Offset="0xBCB" Value="0x0000" />
<Parameter Name="Correction_Entry16" Offset="0xBCD" Value="0x0000" />
<Parameter Name="Correction_Entry17" Offset="0xBCF" Value="0x0000" />
<Parameter Name="Correction_Entry18" Offset="0xBD1" Value="0x0000" />
<Parameter Name="Correction_Entry19" Offset="0xBD3" Value="0x0000" />
<Parameter Name="Correction_Entry20" Offset="0xBD5" Value="0x0000" />
<Parameter Name="Correction_Entry21" Offset="0xBD7" Value="0x0000" />
<Parameter Name="Correction_Entry22" Offset="0xBD9" Value="0x0000" />
<Parameter Name="Correction_Entry23" Offset="0xBDB" Value="0x0000" />
<Parameter Name="Correction_Entry24" Offset="0xBDD" Value="0x0000" />
<Parameter Name="Correction_Entry25" Offset="0xBDF" Value="0x0000" />
<Parameter Name="Correction_Entry26" Offset="0xBE1" Value="0x0000" />
<Parameter Name="Correction_Entry27" Offset="0xBE3" Value="0x0000" />
<Parameter Name="Correction_Entry28" Offset="0xBE5" Value="0x0000" />
<Parameter Name="Correction_Entry29" Offset="0xBE7" Value="0x0000" />
<Parameter Name="Correction_Entry30" Offset="0xBE9" Value="0x0000" />
<Parameter Name="Correction_Entry31" Offset="0xBEB" Value="0x0000" />
<Parameter Name="Correction_Entry32" Offset="0xBED" Value="0x0000" />
<Parameter Name="Correction_Entry33" Offset="0xBEF" Value="0x0000" />
<Parameter Name="Correction_Entry34" Offset="0xBF1" Value="0x0000" />
<Parameter Name="Correction_Entry35" Offset="0xBF3" Value="0x0000" />
<Parameter Name="Correction_Entry36" Offset="0xBF5" Value="0x0000" />
<Parameter Name="Correction_Entry37" Offset="0xBF7" Value="0x0000" />
<Parameter Name="Correction_Entry38" Offset="0xBF9" Value="0x0000" />
<Parameter Name="Correction_Entry39" Offset="0xBFB" Value="0x0000" />
<Parameter Name="Correction_Entry40" Offset="0xBFD" Value="0x0000" />
<Parameter Name="Correction_Entry41" Offset="0xBFF" Value="0x0000" />
<Parameter Name="Correction_Entry42" Offset="0xC01" Value="0x0000" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_1" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RTRANS0" Offset="0xC03" Value="0xDFD9D3CD" />
<Parameter Name="RTRANS1" Offset="0xC07" Value="0xF1EEEBE5" />
<Parameter Name="RTRANS2" Offset="0xC0B" Value="0xFDFAF7F4" />
<Parameter Name="RTRANS3" Offset="0xC0F" Value="0xFFFFFFFF" />
<Parameter Name="FTRANS0" Offset="0xC13" Value="0xE7EDF3F9" />
<Parameter Name="FTRANS1" Offset="0xC17" Value="0xD4D8DBE1" />
<Parameter Name="FTRANS2" Offset="0xC1B" Value="0xC8CACDD1" />
<Parameter Name="FTRANS3" Offset="0xC1F" Value="0xC7C7C7C7" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_2" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RTRANS0" Offset="0xC23" Value="0xF0EAE3DA" />
<Parameter Name="RTRANS1" Offset="0xC27" Value="0xFAF9F6F4" />
<Parameter Name="RTRANS2" Offset="0xC2B" Value="0xFEFDFDFC" />
<Parameter Name="RTRANS3" Offset="0xC2F" Value="0xFFFFFFFE" />
<Parameter Name="FTRANS0" Offset="0xC33" Value="0xFEFFFFFF" />
<Parameter Name="FTRANS1" Offset="0xC37" Value="0xFCFDFDFE" />
<Parameter Name="FTRANS2" Offset="0xC3B" Value="0xF4F6F9FA" />
<Parameter Name="FTRANS3" Offset="0xC3F" Value="0xDAE3EAF0" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_3" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RTRANS0" Offset="0xC43" Value="0x00000000" />
<Parameter Name="RTRANS1" Offset="0xC47" Value="0x00000000" />
<Parameter Name="RTRANS2" Offset="0xC4B" Value="0x00000000" />
<Parameter Name="RTRANS3" Offset="0xC4F" Value="0x00000000" />
<Parameter Name="FTRANS0" Offset="0xC53" Value="0x00000000" />
<Parameter Name="FTRANS1" Offset="0xC57" Value="0x00000000" />
<Parameter Name="FTRANS2" Offset="0xC5B" Value="0x00000000" />
<Parameter Name="FTRANS3" Offset="0xC5F" Value="0x00000000" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_4" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RTRANS0" Offset="0xC63" Value="0x00000000" />
<Parameter Name="RTRANS1" Offset="0xC67" Value="0x00000000" />
<Parameter Name="RTRANS2" Offset="0xC6B" Value="0x00000000" />
<Parameter Name="RTRANS3" Offset="0xC6F" Value="0x00000000" />
<Parameter Name="FTRANS0" Offset="0xC73" Value="0x00000000" />
<Parameter Name="FTRANS1" Offset="0xC77" Value="0x00000000" />
<Parameter Name="FTRANS2" Offset="0xC7B" Value="0x00000000" />
<Parameter Name="FTRANS3" Offset="0xC7F" Value="0x00000000" />
</Region>
<Region RegionName="TX_DRIVER_NOV" RegionAccess="RW" RegionType="DATA">
<Parameter Name="CfgNovCal" Offset="0xC83" Value="0x42" />
<Parameter Name="VddpaCalVal1" Offset="0xC84" Value="0x03" />
<Parameter Name="VddpaCalVal2" Offset="0xC85" Value="0x15" />
<Parameter Name="CfgThreshold" Offset="0xC86" Value="0x08" />
<Parameter Name="UserOffsets1" Offset="0xC87" Value="0x8A0A0C00" />
<Parameter Name="UserOffsets2" Offset="0xC8B" Value="0x09080D03" />
</Region>
<Region RegionName="USER_PMU_INT_1" RegionAccess="RW" RegionType="DATA">
<Parameter Name="EnableFastVDDPADischarge" Offset="0xC8F" Value="0x00" />
</Region>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
263 / 308
NXP Semiconductors
PN5190
NFC frontend
<Region RegionName="ARC_SETTINGS_1" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RmArcA_106_FDT" Offset="0xC9D" Value="0x8040804080608060C060" />
</Region>
<Region RegionName="RF_CLOCK_ACTIVE_DPLL_COM" RegionAccess="RW" RegionType="DATA">
<Parameter Name="DPLL_INIT_ActiveInitiator" Offset="0xCA8" Value="0x20050530" />
<Parameter Name="DPLL_GEAR_ActiveInitiator" Offset="0xCAC" Value="0x0FFDFEFF" />
</Region>
<Region RegionName="RegisterValuePair" RegionOffset="0x74" RegionType="PROTOCOL" RegionAccess="INDIRECT">
<Protocol ProtocolName="TX ISO14443A 106" ProtocolIndex="0x00" ProtocolOffset="0x74">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000F00FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00003D41"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00220104"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00220104"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A 212" ProtocolIndex="0x01" ProtocolOffset="0xA1">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00110105"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00110105"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A 424" ProtocolIndex="0x02" ProtocolOffset="0xCE">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00060106"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00060106"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A 848" ProtocolIndex="0x03" ProtocolOffset="0xFB">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00020107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00020107"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443B 106" ProtocolIndex="0x04" ProtocolOffset="0x128">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00030107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000084"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443B 212" ProtocolIndex="0x05" ProtocolOffset="0x155">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00030107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000085"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443B 424" ProtocolIndex="0x06" ProtocolOffset="0x182">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00030107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000086"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443B 848" ProtocolIndex="0x07" ProtocolOffset="0x1AF">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00030107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000087"></Register>
</Protocol>
<Protocol ProtocolName="TX Felica 212" ProtocolIndex="0x08" ProtocolOffset="0x1DC">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
264 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000015"></Register>
</Protocol>
<Protocol ProtocolName="TX Felica 424" ProtocolIndex="0x09" ProtocolOffset="0x209">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000016"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO15693 ASK100" ProtocolIndex="0x0A" ProtocolOffset="0x236">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000F00FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000004"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00020084"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000043"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO15693 ASK10" ProtocolIndex="0x0B" ProtocolOffset="0x263">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000004"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00020084"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000043"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO180003m3 TARI=18.88us" ProtocolIndex="0x0F" ProtocolOffset="0x290">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000F00FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000004"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00020084"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000043"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO180003m3 TARI=9.44us" ProtocolIndex="0x10" ProtocolOffset="0x2BD">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000004"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00020084"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000043"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A-PICC 106" ProtocolIndex="0x13" ProtocolOffset="0x2EA">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x001F002E"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00008002"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x0000002C"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000002C"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A-PICC 212" ProtocolIndex="0x14" ProtocolOffset="0x317">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00007402"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000003D"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A-PICC 424" ProtocolIndex="0x15" ProtocolOffset="0x344">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00007402"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x0000002E"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000003E"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A-PICC 848" ProtocolIndex="0x16" ProtocolOffset="0x371">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
265 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00007402"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x0000002F"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000003F"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-PT-212 212" ProtocolIndex="0x17" ProtocolOffset="0x39E">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000015"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-PT-424 424" ProtocolIndex="0x18" ProtocolOffset="0x3CB">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000016"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-AT-106 106" ProtocolIndex="0x19" ProtocolOffset="0x3F8">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000F00FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00003D41"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00220104"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00220104"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-AT-212 212" ProtocolIndex="0x1A" ProtocolOffset="0x425">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000015"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-AT-424 424" ProtocolIndex="0x1B" ProtocolOffset="0x452">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000016"></Register>
</Protocol>
<Protocol ProtocolName="TX GTM All" ProtocolIndex="0x1C" ProtocolOffset="0x47F">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x001F002E"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00008002"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x0000002C"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000002C"></Register>
</Protocol>
<Protocol ProtocolName="TX B_Prime All" ProtocolIndex="0x1D" ProtocolOffset="0x4AC">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000084"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A 106" ProtocolIndex="0x80" ProtocolOffset="0x506">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0202"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x09BDB07F"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x500800B0"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0810203F"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
266 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00080808"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4D24A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x7B75FFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F51AA"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x4A8B60A7"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A 212" ProtocolIndex="0x81" ProtocolOffset="0x57E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x10F8024C"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800C0"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x8A866150"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A 424" ProtocolIndex="0x82" ProtocolOffset="0x5F6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x14F80228"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401000D0"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x383F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x88046548"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A 848" ProtocolIndex="0x83" ProtocolOffset="0x66E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x28F80209"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401000E0"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x40026508"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443B 106" ProtocolIndex="0x84" ProtocolOffset="0x6E6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x3E380248"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000045"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000B6"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
267 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x95086250"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443B 212" ProtocolIndex="0x85" ProtocolOffset="0x75E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x10380248"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000045"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000C6"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x94866248"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443B 424" ProtocolIndex="0x86" ProtocolOffset="0x7D6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x20380248"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000045"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000D6"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x94046650"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443B 848" ProtocolIndex="0x87" ProtocolOffset="0x84E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x0A380209"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000045"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000E6"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x5C026608"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX Felica 212" ProtocolIndex="0x88" ProtocolOffset="0x8C6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x10780203"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
268 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x110000C4"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x0088D238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x01806100"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX Felica 424" ProtocolIndex="0x89" ProtocolOffset="0x93E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x10780203"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x010000D4"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x0088D238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x48826548"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 6P6" ProtocolIndex="0x8A" ProtocolOffset="0x9B6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x40080088"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0xDB0660FF"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 26" ProtocolIndex="0x8B" ProtocolOffset="0xA2E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x40080098"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x8B1660F7"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 53" ProtocolIndex="0x8C" ProtocolOffset="0xAA6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
269 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800A8"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x432B609F"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 Plutus 106" ProtocolIndex="0x8D" ProtocolOffset="0xB1E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401000B8"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x42A2689F"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 Plutus 212" ProtocolIndex="0x8E" ProtocolOffset="0xB96">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401800C8"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x422C689F"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO180003m3 Manch424_4 53" ProtocolIndex="0x8F" ProtocolOffset="0xC0E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815077D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800AA"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000017FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFE"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F5194"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x6B3B60AB"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO180003m3 Manch424_2 106" ProtocolIndex="0x90" ProtocolOffset="0xC86">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
270 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815077D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800BC"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000017FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFE"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F5194"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x23406053"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO180003m3 Manch848_4 106" ProtocolIndex="0x91" ProtocolOffset="0xCFE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815077D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800BA"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000017FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFE"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F5194"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x6ABB60AB"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO180003m3 Manch424_2 212" ProtocolIndex="0x92" ProtocolOffset="0xD76">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815077D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401000CC"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000017FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFE"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F5194"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x6A3264AB"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A-PICC 106" ProtocolIndex="0x93" ProtocolOffset="0xDEE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000B1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000037FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79600A0"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A-PICC 212" ProtocolIndex="0x94" ProtocolOffset="0xE66">
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
271 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00000032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000C1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79700A0"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A-PICC 424" ProtocolIndex="0x95" ProtocolOffset="0xEDE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00000032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000D1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79700A0"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A-PICC 848" ProtocolIndex="0x96" ProtocolOffset="0xF56">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00000032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000E1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79700A0"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-PT-212 212" ProtocolIndex="0x97" ProtocolOffset="0xFCE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000C5"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
272 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x20100000"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-PT-424 424" ProtocolIndex="0x98" ProtocolOffset="0x1046">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000D5"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x20060200"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-AT-106 106" ProtocolIndex="0x99" ProtocolOffset="0x10BE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000B1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000037FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79600A0"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-AT-212 212" ProtocolIndex="0x9A" ProtocolOffset="0x1136">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000C5"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x20100000"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-AT-424 424" ProtocolIndex="0x9B" ProtocolOffset="0x11AE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000D5"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
273 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x20060200"></Register>
</Protocol>
<Protocol ProtocolName="RX GTM All" ProtocolIndex="0x9C" ProtocolOffset="0x1226">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x00600081"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000037FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xBF9600A0"></Register>
</Protocol>
<Protocol ProtocolName="RX B_Prime All" ProtocolIndex="0x9D" ProtocolOffset="0x129E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x02380248"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000BE"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00085510"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x95086250"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
</Region>
</EEPROM>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
274 / 308
NXP Semiconductors
PN5190
NFC frontend
19 Appendix: EEPROM LOAD_RF_CONFIGURATION FW2.1
Firmware 2.1
<?xml version="1.0" encoding="utf-8"?>
<EEPROM>
<Region RegionName="USER_PMU" RegionAccess="RW" RegionType="DATA">
<Parameter Name="PwrConfig" Offset="0x00" Value="0xE4" />
<Parameter Name="DcdcConfig" Offset="0x01" Value="0x31" />
<Parameter Name="TxldoConfig" Offset="0x02" Value="0xFFFFAEA7" />
<Parameter Name="TxLdoVddpaHigh" Offset="0x06" Value="0x00" />
<Parameter Name="TxLdoVddpaLow" Offset="0x07" Value="0x00" />
<Parameter Name="TxLdoVddpaMaxRdr" Offset="0x08" Value="0x2A" />
<Parameter Name="TxLdoVddpaMaxCard" Offset="0x09" Value="0x2A" />
<Parameter Name="BoostDefaultVoltage" Offset="0x0A" Value="0x1D" />
</Region>
<Region RegionName="CLKGEN" RegionAccess="RW" RegionType="DATA">
<Parameter Name="XtalConfig" Offset="0x10" Value="0x00" />
<Parameter Name="XtalTimeOut" Offset="0x11" Value="0xFF" />
</Region>
<Region RegionName="RF_CLOCK_CFG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="PLLClkInputFrq" Offset="0x12" Value="0x08" />
<Parameter Name="XtalCheckDelay" Offset="0x13" Value="0xF6" />
</Region>
<Region RegionName="USER_SMU" RegionAccess="RW" RegionType="DATA">
<Parameter Name="TempWarning" Offset="0x14" Value="0x99" />
<Parameter Name="EnableGpio0OnOverTemp" Offset="0x16" Value="0x01" />
</Region>
<Region RegionName="RM_TECHNO_TX_SHAPING" RegionAccess="RW" RegionType="DATA">
<Parameter Name="ResidualAmplitudeLevel_A106" Offset="0x22" Value="0x00" />
<Parameter Name="EdgeType_A106" Offset="0x23" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_A106" Offset="0x24" Value="0x64" />
<Parameter Name="EdgeLength_A106" Offset="0x25" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_A212" Offset="0x26" Value="0x00" />
<Parameter Name="EdgeType_A212" Offset="0x27" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_A212" Offset="0x28" Value="0x44" />
<Parameter Name="EdgeLength_A212" Offset="0x29" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_A424" Offset="0x2A" Value="0x00" />
<Parameter Name="EdgeType_A424" Offset="0x2B" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_A424" Offset="0x2C" Value="0x24" />
<Parameter Name="EdgeLength_A424" Offset="0x2D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_A848" Offset="0x2E" Value="0x00" />
<Parameter Name="EdgeType_A848" Offset="0x2F" Value="0x11" />
<Parameter Name="EdgeStyleConfiguration_A848" Offset="0x30" Value="0x18" />
<Parameter Name="EdgeLength_A848" Offset="0x31" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B106" Offset="0x32" Value="0xCA" />
<Parameter Name="EdgeType_B106" Offset="0x33" Value="0x44" />
<Parameter Name="EdgeStyleConfiguration_B106" Offset="0x34" Value="0x00" />
<Parameter Name="EdgeLength_B106" Offset="0x35" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B212" Offset="0x36" Value="0xCF" />
<Parameter Name="EdgeType_B212" Offset="0x37" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_B212" Offset="0x38" Value="0x66" />
<Parameter Name="EdgeLength_B212" Offset="0x39" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B424" Offset="0x3A" Value="0xCF" />
<Parameter Name="EdgeType_B424" Offset="0x3B" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_B424" Offset="0x3C" Value="0x55" />
<Parameter Name="EdgeLength_B424" Offset="0x3D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B848" Offset="0x3E" Value="0xCE" />
<Parameter Name="EdgeType_B848" Offset="0x3F" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_B848" Offset="0x40" Value="0x34" />
<Parameter Name="EdgeLength_B848" Offset="0x41" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_F212" Offset="0x42" Value="0xCF" />
<Parameter Name="EdgeType_F212" Offset="0x43" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_F212" Offset="0x44" Value="0x65" />
<Parameter Name="EdgeLength_F212" Offset="0x45" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_F424" Offset="0x46" Value="0xCE" />
<Parameter Name="EdgeType_F424" Offset="0x47" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_F424" Offset="0x48" Value="0x55" />
<Parameter Name="EdgeLength_F424" Offset="0x49" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V100_26" Offset="0x4A" Value="0x00" />
<Parameter Name="EdgeType_V100_26" Offset="0x4B" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_V100_26" Offset="0x4C" Value="0x66" />
<Parameter Name="EdgeLength_V100_26" Offset="0x4D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V100_53" Offset="0x4E" Value="0x00" />
<Parameter Name="EdgeType_V100_53" Offset="0x4F" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_V100_53" Offset="0x50" Value="0x66" />
<Parameter Name="EdgeLength_V100_53" Offset="0x51" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V100_106" Offset="0x52" Value="0x00" />
<Parameter Name="EdgeType_V100_106" Offset="0x53" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_V100_106" Offset="0x54" Value="0x66" />
<Parameter Name="EdgeLength_V100_106" Offset="0x55" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V100_212" Offset="0x56" Value="0x00" />
<Parameter Name="EdgeType_V100_212" Offset="0x57" Value="0x33" />
<Parameter Name="EdgeStyleConfiguration_V100_212" Offset="0x58" Value="0x22" />
<Parameter Name="EdgeLength_V100_212" Offset="0x59" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V10_26" Offset="0x5A" Value="0xC0" />
<Parameter Name="EdgeType_V10_26" Offset="0x5B" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_V10_26" Offset="0x5C" Value="0x66" />
<Parameter Name="EdgeLength_V10_26" Offset="0x5D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V10_53" Offset="0x5E" Value="0xC0" />
<Parameter Name="EdgeType_V10_53" Offset="0x5F" Value="0x22" />
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
275 / 308
NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="EdgeStyleConfiguration_V10_53" Offset="0x60" Value="0x23" />
<Parameter Name="EdgeLength_V10_53" Offset="0x61" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V10_106" Offset="0x62" Value="0xC0" />
<Parameter Name="EdgeType_V10_106" Offset="0x63" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_V10_106" Offset="0x64" Value="0x23" />
<Parameter Name="EdgeLength_V10_106" Offset="0x65" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_V10_212" Offset="0x66" Value="0xC0" />
<Parameter Name="EdgeType_V10_212" Offset="0x67" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_V10_212" Offset="0x68" Value="0x23" />
<Parameter Name="EdgeLength_V10_212" Offset="0x69" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_180003m3_tari18p88" Offset="0x6A" Value="0xC0" />
<Parameter Name="EdgeType_180003m3_tari18p88" Offset="0x6B" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_180003m3_tari18p88" Offset="0x6C" Value="0x66" />
<Parameter Name="EdgeLength_180003m3_tari18p88" Offset="0x6D" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_180003m3_tari9p44" Offset="0x6E" Value="0xC0" />
<Parameter Name="EdgeType_180003m3_tari19p44" Offset="0x6F" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_180003m3_tari9p44" Offset="0x70" Value="0x66" />
<Parameter Name="EdgeLength_180003m3_tari9p44" Offset="0x71" Value="0x10" />
<Parameter Name="ResidualAmplitudeLevel_B_prime106" Offset="0x72" Value="0xCF" />
<Parameter Name="EdgeType_B_prime106" Offset="0x73" Value="0x22" />
<Parameter Name="EdgeStyleConfiguration_B_prime106" Offset="0x74" Value="0x67" />
<Parameter Name="EdgeLength_B_prime106" Offset="0x75" Value="0x10" />
</Region>
<Region RegionName="DPC_SETTINGS" RegionAccess="RW" RegionType="DATA">
<Parameter Name="DPC_CONFIG" Offset="0x76" Value="0x77" />
<Parameter Name="DPC_TARGET_CURRENT" Offset="0x77" Value="0x0132" />
<Parameter Name="DPC_HYSTERESIS_LOADING" Offset="0x79" Value="0x14" />
<Parameter Name="DPC_HYSTERESIS_UNLOADING" Offset="0x7C" Value="0x0A" />
<Parameter Name="DPC_TXLDOVDDPALow" Offset="0x7D" Value="0x07" />
<Parameter Name="DPC_TXGSN" Offset="0x7E" Value="0x03" />
<Parameter Name="DPC_RDON_Control" Offset="0x7F" Value="0x01" />
<Parameter Name="DPC_InitialRDOn_RFOn" Offset="0x80" Value="0x03" />
<Parameter Name="DPC_GAURD_TIME" Offset="0x87" Value="0x64" />
<Parameter Name="DPC_ENABLE_DURING_FDT" Offset="0x88" Value="0x01" />
<Parameter Name="DPC_GAURD_TIME_AFTER_RX" Offset="0x89" Value="0x01" />
<Parameter Name="Entry_00" Offset="0x8B" Value="0x0000137F" />
<Parameter Name="Entry_01" Offset="0x8F" Value="0x0000137F" />
<Parameter Name="Entry_02" Offset="0x93" Value="0x0000137F" />
<Parameter Name="Entry_03" Offset="0x97" Value="0x0000137F" />
<Parameter Name="Entry_04" Offset="0x9B" Value="0x0000137F" />
<Parameter Name="Entry_05" Offset="0x9F" Value="0x0000137F" />
<Parameter Name="Entry_06" Offset="0xA3" Value="0x0000007F" />
<Parameter Name="Entry_07" Offset="0xA7" Value="0x0000007F" />
<Parameter Name="Entry_08" Offset="0xAB" Value="0x0000007F" />
<Parameter Name="Entry_09" Offset="0xAF" Value="0x0000007F" />
<Parameter Name="Entry_10" Offset="0xB3" Value="0x0000007F" />
<Parameter Name="Entry_11" Offset="0xB7" Value="0x0000007F" />
<Parameter Name="Entry_12" Offset="0xBB" Value="0x0000007F" />
<Parameter Name="Entry_13" Offset="0xBF" Value="0x0000007F" />
<Parameter Name="Entry_14" Offset="0xC3" Value="0x0000007F" />
<Parameter Name="Entry_15" Offset="0xC7" Value="0x0000007F" />
<Parameter Name="Entry_16" Offset="0xCB" Value="0x0000007F" />
<Parameter Name="Entry_17" Offset="0xCF" Value="0x0000007F" />
<Parameter Name="Entry_18" Offset="0xD3" Value="0x0000007F" />
<Parameter Name="Entry_19" Offset="0xD7" Value="0x0000007F" />
<Parameter Name="Entry_20" Offset="0xDB" Value="0x0000007F" />
<Parameter Name="Entry_21" Offset="0xDF" Value="0x0000007F" />
<Parameter Name="Entry_22" Offset="0xE3" Value="0x0000007F" />
<Parameter Name="Entry_23" Offset="0xE7" Value="0x0000007D" />
<Parameter Name="Entry_24" Offset="0xEB" Value="0x0000007B" />
<Parameter Name="Entry_25" Offset="0xEF" Value="0x00000079" />
<Parameter Name="Entry_26" Offset="0xF3" Value="0x00000077" />
<Parameter Name="Entry_27" Offset="0xF7" Value="0x00000075" />
<Parameter Name="Entry_28" Offset="0xFB" Value="0x00000073" />
<Parameter Name="Entry_29" Offset="0xFF" Value="0x00000071" />
<Parameter Name="Entry_30" Offset="0x103" Value="0x0000006F" />
<Parameter Name="Entry_31" Offset="0x107" Value="0x0000006E" />
<Parameter Name="Entry_32" Offset="0x10B" Value="0x0000006C" />
<Parameter Name="Entry_33" Offset="0x10F" Value="0x0000006A" />
<Parameter Name="Entry_34" Offset="0x113" Value="0x00000068" />
<Parameter Name="Entry_35" Offset="0x117" Value="0x00000066" />
<Parameter Name="Entry_36" Offset="0x11B" Value="0x00000057" />
<Parameter Name="Entry_37" Offset="0x11F" Value="0x0000004B" />
<Parameter Name="Entry_38" Offset="0x123" Value="0x0000003F" />
<Parameter Name="Entry_39" Offset="0x127" Value="0x0000002D" />
<Parameter Name="Entry_40" Offset="0x12B" Value="0x00000000" />
<Parameter Name="Entry_41" Offset="0x12F" Value="0x00000000" />
<Parameter Name="Entry_42" Offset="0x133" Value="0x00000000" />
</Region>
<Region RegionName="ARC_SETTINGS" RegionAccess="RW" RegionType="DATA">
<Parameter Name="ArcConfig" Offset="0x137" Value="0x00E4" />
<Parameter Name="ArcVddpa" Offset="0x139" Value="0x2A24130E07" />
<Parameter Name="RmArcA_106" Offset="0x13E" Value="0x81348015802A8220C250" />
<Parameter Name="RmArcA_212" Offset="0x148" Value="0x001A00200030007F407F" />
<Parameter Name="RmArcA_424" Offset="0x152" Value="0x001A00200040007F407F" />
<Parameter Name="RmArcA_848" Offset="0x15C" Value="0x001A00200040007F407F" />
<Parameter Name="RmArcB_106" Offset="0x166" Value="0x001A0020003000404050" />
<Parameter Name="RmArcB_212" Offset="0x170" Value="0x001A002000400050407F" />
<Parameter Name="RmArcB_424" Offset="0x17A" Value="0x001A002000400050407F" />
<Parameter Name="RmArcB_848" Offset="0x184" Value="0x001A002000400050407F" />
<Parameter Name="RmArcF_212" Offset="0x18E" Value="0x001A00200040007F407F" />
<Parameter Name="RmArcF_424" Offset="0x198" Value="0x001A00200040007F407F" />
<Parameter Name="RmArcV_6p6" Offset="0x1A2" Value="0x000A000A000A000A400A" />
<Parameter Name="RmArcV_26" Offset="0x1AC" Value="0x000A000A002F002F402F" />
<Parameter Name="RmArcV_53" Offset="0x1B6" Value="0x010A010A011F011F411F" />
<Parameter Name="RmArcV_106" Offset="0x1C0" Value="0x000A000A002F002F402F" />
<Parameter Name="RmArcV_212" Offset="0x1CA" Value="0x000A000A002F002F402F" />
<Parameter Name="RmArc180003m3_SC424_4Man" Offset="0x1D4" Value="0x0114011F011F001F401F" />
<Parameter Name="RmArc180003m3_SC424_2Man" Offset="0x1DE" Value="0x0014001F003F004F404F" />
PN5190B1
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© NXP B.V. 2021. All rights reserved.
Product data sheet
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NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="RmArc180003m3_SC848_4Man" Offset="0x1E8" Value="0x0114011F011F001F401F" />
<Parameter Name="RmArc180003m3_SC848_2Man" Offset="0x1F2" Value="0x0014001F003F004F404F" />
<Parameter Name="RmArc_AI_106" Offset="0x1FC" Value="0x000A000A000A000A400A" />
<Parameter Name="RmArc_AI_212" Offset="0x206" Value="0x000A000A000A000A400A" />
<Parameter Name="RmArc_AI_424" Offset="0x210" Value="0x000A000A000A000A400A" />
</Region>
<Region RegionName="AUTOCOLL_CFG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RfDebounceTimeout" Offset="0x2B2" Value="0x10" />
<Parameter Name="SensRes" Offset="0x2B3" Value="0x0042" />
<Parameter Name="NfcID1" Offset="0x2B5" Value="0xCCBBAA" />
<Parameter Name="SelRes" Offset="0x2B8" Value="0x60" />
<Parameter Name="PollRes" Offset="0x2B9" Value="0xFFD08584424B0B100814119814011401FE01" />
<Parameter Name="RandomUIDEnable" Offset="0x2CB" Value="0x00" />
</Region>
<Region RegionName="MFC_CFG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="MfcAuthTimeout" Offset="0x2CC" Value="0x0500" />
</Region>
<Region RegionName="APC_RSSI" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RssiTimer" Offset="0x2DA" Value="0x0423" />
<Parameter Name="RssiTimerFirstPeriod" Offset="0x2DC" Value="0x013D" />
<Parameter Name="RssiCtrl_00_AB" Offset="0x2DE" Value="0x09" />
<Parameter Name="RssiNbEntriesAB" Offset="0x2DF" Value="0x16" />
<Parameter Name="RssiThresholdAB_01" Offset="0x2E0" Value="0x2816" />
<Parameter Name="ArbPhaseAB_01" Offset="0x2E2" Value="0x0000" />
<Parameter Name="RssiThresholdAB_02" Offset="0x2E4" Value="0x3215" />
<Parameter Name="ArbPhaseAB_02" Offset="0x2E6" Value="0x0000" />
<Parameter Name="RssiThresholdAB_03" Offset="0x2E8" Value="0x3B6E" />
<Parameter Name="ArbPhaseAB_03" Offset="0x2EA" Value="0x0000" />
<Parameter Name="RssiThresholdAB_04" Offset="0x2EC" Value="0x456A" />
<Parameter Name="ArbPhaseAB_04" Offset="0x2EE" Value="0x0000" />
<Parameter Name="RssiThresholdAB_05" Offset="0x2F0" Value="0x4FDC" />
<Parameter Name="ArbPhaseAB_05" Offset="0x2F2" Value="0x0000" />
<Parameter Name="RssiThresholdAB_06" Offset="0x2F4" Value="0x5983" />
<Parameter Name="ArbPhaseAB_06" Offset="0x2F6" Value="0x0000" />
<Parameter Name="RssiThresholdAB_07" Offset="0x2F8" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_07" Offset="0x2FA" Value="0x0000" />
<Parameter Name="RssiThresholdAB_08" Offset="0x2FC" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_08" Offset="0x2FE" Value="0x0000" />
<Parameter Name="RssiThresholdAB_09" Offset="0x300" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_09" Offset="0x302" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0A" Offset="0x304" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0A" Offset="0x306" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0B" Offset="0x308" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0B" Offset="0x30A" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0C" Offset="0x30C" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0C" Offset="0x30E" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0D" Offset="0x310" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0D" Offset="0x312" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0E" Offset="0x314" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0E" Offset="0x316" Value="0x0000" />
<Parameter Name="RssiThresholdAB_0F" Offset="0x318" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_0F" Offset="0x31A" Value="0x0000" />
<Parameter Name="RssiThresholdAB_10" Offset="0x31C" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_10" Offset="0x31E" Value="0x0000" />
<Parameter Name="RssiThresholdAB_11" Offset="0x320" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_11" Offset="0x322" Value="0x0000" />
<Parameter Name="RssiThresholdAB_12" Offset="0x324" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_12" Offset="0x326" Value="0x0000" />
<Parameter Name="RssiThresholdAB_13" Offset="0x328" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_13" Offset="0x32A" Value="0x0000" />
<Parameter Name="RssiThresholdAB_14" Offset="0x32C" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_14" Offset="0x32E" Value="0x0000" />
<Parameter Name="RssiThresholdAB_15" Offset="0x330" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_15" Offset="0x332" Value="0x0000" />
<Parameter Name="RssiThresholdAB_16" Offset="0x334" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_16" Offset="0x336" Value="0x0000" />
<Parameter Name="RssiThresholdAB_17" Offset="0x338" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_17" Offset="0x33A" Value="0x0000" />
<Parameter Name="RssiThresholdAB_18" Offset="0x33C" Value="0x96F9" />
<Parameter Name="ArbPhaseAB_18" Offset="0x33E" Value="0x0000" />
<Parameter Name="RssiCtrl_00_F" Offset="0x340" Value="0x09" />
<Parameter Name="RssiNbEntriesF" Offset="0x341" Value="0x16" />
<Parameter Name="RssiThresholdF_01" Offset="0x342" Value="0x2816" />
<Parameter Name="ArbPhaseF_01" Offset="0x344" Value="0x0000" />
<Parameter Name="RssiThresholdF_02" Offset="0x346" Value="0x3215" />
<Parameter Name="ArbPhaseF_02" Offset="0x348" Value="0x0000" />
<Parameter Name="RssiThresholdF_03" Offset="0x34A" Value="0x3B6E" />
<Parameter Name="ArbPhaseF_03" Offset="0x34C" Value="0x0000" />
<Parameter Name="RssiThresholdF_04" Offset="0x34E" Value="0x456A" />
<Parameter Name="ArbPhaseF_04" Offset="0x350" Value="0x0000" />
<Parameter Name="RssiThresholdF_05" Offset="0x352" Value="0x4FDC" />
<Parameter Name="ArbPhaseF_05" Offset="0x354" Value="0x0000" />
<Parameter Name="RssiThresholdF_06" Offset="0x356" Value="0x5983" />
<Parameter Name="ArbPhaseF_06" Offset="0x358" Value="0x0000" />
<Parameter Name="RssiThresholdF_07" Offset="0x35A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_07" Offset="0x35C" Value="0x0000" />
<Parameter Name="RssiThresholdF_08" Offset="0x35E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_08" Offset="0x360" Value="0x0000" />
<Parameter Name="RssiThresholdF_09" Offset="0x362" Value="0x96F9" />
<Parameter Name="ArbPhaseF_09" Offset="0x364" Value="0x0000" />
<Parameter Name="RssiThresholdF_0A" Offset="0x366" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0A" Offset="0x368" Value="0x0000" />
<Parameter Name="RssiThresholdF_0B" Offset="0x36A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0B" Offset="0x36C" Value="0x0000" />
<Parameter Name="RssiThresholdF_0C" Offset="0x36E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0C" Offset="0x370" Value="0x0000" />
<Parameter Name="RssiThresholdF_0D" Offset="0x372" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0D" Offset="0x374" Value="0x0000" />
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
277 / 308
NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="RssiThresholdF_0E" Offset="0x376" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0E" Offset="0x378" Value="0x0000" />
<Parameter Name="RssiThresholdF_0F" Offset="0x37A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_0F" Offset="0x37C" Value="0x0000" />
<Parameter Name="RssiThresholdF_10" Offset="0x37E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_10" Offset="0x380" Value="0x0000" />
<Parameter Name="RssiThresholdF_11" Offset="0x382" Value="0x96F9" />
<Parameter Name="ArbPhaseF_11" Offset="0x384" Value="0x0000" />
<Parameter Name="RssiThresholdF_12" Offset="0x386" Value="0x96F9" />
<Parameter Name="ArbPhaseF_12" Offset="0x388" Value="0x0000" />
<Parameter Name="RssiThresholdF_13" Offset="0x38A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_13" Offset="0x38C" Value="0x0000" />
<Parameter Name="RssiThresholdF_14" Offset="0x38E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_14" Offset="0x390" Value="0x0000" />
<Parameter Name="RssiThresholdF_15" Offset="0x392" Value="0x96F9" />
<Parameter Name="ArbPhaseF_15" Offset="0x394" Value="0x0000" />
<Parameter Name="RssiThresholdF_16" Offset="0x396" Value="0x96F9" />
<Parameter Name="ArbPhaseF_16" Offset="0x398" Value="0x0000" />
<Parameter Name="RssiThresholdF_17" Offset="0x39A" Value="0x96F9" />
<Parameter Name="ArbPhaseF_17" Offset="0x39C" Value="0x0000" />
<Parameter Name="RssiThresholdF_18" Offset="0x39E" Value="0x96F9" />
<Parameter Name="ArbPhaseF_18" Offset="0x3A0" Value="0x0000" />
</Region>
<Region RegionName="APC_TX" RegionAccess="RW" RegionType="DATA">
<Parameter Name="TxParamEntry_00_ID" Offset="0x3A2" Value="0x40" />
<Parameter Name="TxParamEntry_00_Tx1" Offset="0x3A3" Value="0x00" />
<Parameter Name="TxParamEntry_00_Tx2" Offset="0x3A4" Value="0x64" />
<Parameter Name="TxParamEntry_01_ID" Offset="0x3A5" Value="0x41" />
<Parameter Name="TxParamEntry_01_Tx1" Offset="0x3A6" Value="0x00" />
<Parameter Name="TxParamEntry_01_Tx2" Offset="0x3A7" Value="0x64" />
<Parameter Name="TxParamEntry_02_ID" Offset="0x3A8" Value="0x42" />
<Parameter Name="TxParamEntry_02_Tx1" Offset="0x3A9" Value="0x00" />
<Parameter Name="TxParamEntry_02_Tx2" Offset="0x3AA" Value="0x64" />
<Parameter Name="TxParamEntry_03_ID" Offset="0x3AB" Value="0x43" />
<Parameter Name="TxParamEntry_03_Tx1" Offset="0x3AC" Value="0x00" />
<Parameter Name="TxParamEntry_03_Tx2" Offset="0x3AD" Value="0x64" />
<Parameter Name="TxParamEntry_04_ID" Offset="0x3AE" Value="0x44" />
<Parameter Name="TxParamEntry_04_Tx1" Offset="0x3AF" Value="0x00" />
<Parameter Name="TxParamEntry_04_Tx2" Offset="0x3B0" Value="0x64" />
<Parameter Name="TxParamEntry_05_ID" Offset="0x3B1" Value="0x45" />
<Parameter Name="TxParamEntry_05_Tx1" Offset="0x3B2" Value="0x00" />
<Parameter Name="TxParamEntry_05_Tx2" Offset="0x3B3" Value="0x64" />
<Parameter Name="TxParamEntry_06_ID" Offset="0x3B4" Value="0x46" />
<Parameter Name="TxParamEntry_06_Tx1" Offset="0x3B5" Value="0x00" />
<Parameter Name="TxParamEntry_06_Tx2" Offset="0x3B6" Value="0x64" />
<Parameter Name="TxParamEntry_07_ID" Offset="0x3B7" Value="0x47" />
<Parameter Name="TxParamEntry_07_Tx1" Offset="0x3B8" Value="0x00" />
<Parameter Name="TxParamEntry_07_Tx2" Offset="0x3B9" Value="0x64" />
<Parameter Name="TxParamEntry_08_ID" Offset="0x3BA" Value="0x48" />
<Parameter Name="TxParamEntry_08_Tx1" Offset="0x3BB" Value="0x00" />
<Parameter Name="TxParamEntry_08_Tx2" Offset="0x3BC" Value="0x64" />
<Parameter Name="TxParamEntry_09_ID" Offset="0x3BD" Value="0x49" />
<Parameter Name="TxParamEntry_09_Tx1" Offset="0x3BE" Value="0x00" />
<Parameter Name="TxParamEntry_09_Tx2" Offset="0x3BF" Value="0x64" />
<Parameter Name="TxParamEntry_0A_ID" Offset="0x3C0" Value="0x4A" />
<Parameter Name="TxParamEntry_0A_Tx1" Offset="0x3C1" Value="0x00" />
<Parameter Name="TxParamEntry_0A_Tx2" Offset="0x3C2" Value="0x5D" />
<Parameter Name="TxParamEntry_0B_ID" Offset="0x3C3" Value="0x4B" />
<Parameter Name="TxParamEntry_0B_Tx1" Offset="0x3C4" Value="0x00" />
<Parameter Name="TxParamEntry_0B_Tx2" Offset="0x3C5" Value="0x56" />
<Parameter Name="TxParamEntry_0C_ID" Offset="0x3C6" Value="0x4C" />
<Parameter Name="TxParamEntry_00C_Tx1" Offset="0x3C7" Value="0x00" />
<Parameter Name="TxParamEntry_00C_Tx2" Offset="0x3C8" Value="0x4F" />
<Parameter Name="TxParamEntry_0D_ID" Offset="0x3C9" Value="0x4D" />
<Parameter Name="TxParamEntry_0D_Tx1" Offset="0x3CA" Value="0x00" />
<Parameter Name="TxParamEntry_0D_Tx2" Offset="0x3CB" Value="0x47" />
<Parameter Name="TxParamEntry_0E_ID" Offset="0x3CC" Value="0x4E" />
<Parameter Name="TxParamEntry_0E_Tx1" Offset="0x3CD" Value="0x00" />
<Parameter Name="TxParamEntry_0E_Tx2" Offset="0x3CE" Value="0x3F" />
<Parameter Name="TxParamEntry_0F_ID" Offset="0x3CF" Value="0x4F" />
<Parameter Name="TxParamEntry_0F_Tx1" Offset="0x3D0" Value="0x00" />
<Parameter Name="TxParamEntry_0F_Tx2" Offset="0x3D1" Value="0x37" />
<Parameter Name="TxParamEntry_10_ID" Offset="0x3D2" Value="0x50" />
<Parameter Name="TxParamEntry_10_Tx1" Offset="0x3D3" Value="0x00" />
<Parameter Name="TxParamEntry_10_Tx2" Offset="0x3D4" Value="0x37" />
<Parameter Name="TxParamEntry_11_ID" Offset="0x3D5" Value="0x51" />
<Parameter Name="TxParamEntry_11_Tx1" Offset="0x3D6" Value="0x00" />
<Parameter Name="TxParamEntry_11_Tx2" Offset="0x3D7" Value="0x37" />
<Parameter Name="TxParamEntry_12_ID" Offset="0x3D8" Value="0x52" />
<Parameter Name="TxParamEntry_12_Tx1" Offset="0x3D9" Value="0x00" />
<Parameter Name="TxParamEntry_12_Tx2" Offset="0x3DA" Value="0x37" />
<Parameter Name="TxParamEntry_13_ID" Offset="0x3DB" Value="0x53" />
<Parameter Name="TxParamEntry_13_Tx1" Offset="0x3DC" Value="0x00" />
<Parameter Name="TxParamEntry_13_Tx2" Offset="0x3DD" Value="0x37" />
<Parameter Name="TxParamEntry_14_ID" Offset="0x3DE" Value="0x54" />
<Parameter Name="TxParamEntry_14_Tx1" Offset="0x3DF" Value="0x00" />
<Parameter Name="TxParamEntry_14_Tx2" Offset="0x3E0" Value="0x37" />
<Parameter Name="TxParamEntry_15_ID" Offset="0x3E1" Value="0x55" />
<Parameter Name="TxParamEntry_15_Tx1" Offset="0x3E2" Value="0x00" />
<Parameter Name="TxParamEntry_15_Tx2" Offset="0x3E3" Value="0x37" />
<Parameter Name="TxParamEntry_16_ID" Offset="0x3E4" Value="0x56" />
<Parameter Name="TxParamEntry_16_Tx1" Offset="0x3E5" Value="0x00" />
<Parameter Name="TxParamEntry_16_Tx2" Offset="0x3E6" Value="0x37" />
<Parameter Name="TxParamEntry_17_ID" Offset="0x3E7" Value="0x57" />
<Parameter Name="TxParamEntry_17_Tx1" Offset="0x3E8" Value="0x00" />
<Parameter Name="TxParamEntry_17_Tx2" Offset="0x3E9" Value="0x37" />
<Parameter Name="TxParamEntry_18_ID" Offset="0x3EA" Value="0x58" />
<Parameter Name="TxParamEntry_18_Tx1" Offset="0x3EB" Value="0x00" />
<Parameter Name="TxParamEntry_18_Tx2" Offset="0x3EC" Value="0x37" />
<Parameter Name="TxParamEntry_19_ID" Offset="0x3ED" Value="0x59" />
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
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Rev. 3.0 — 21 April 2021
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NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="TxParamEntry_19_Tx1" Offset="0x3EE" Value="0x00" />
<Parameter Name="TxParamEntry_19_Tx2" Offset="0x3EF" Value="0x37" />
<Parameter Name="TxParamEntry_1A_ID" Offset="0x3F0" Value="0x5A" />
<Parameter Name="TxParamEntry_1A_Tx1" Offset="0x3F1" Value="0x00" />
<Parameter Name="TxParamEntry_1A_Tx2" Offset="0x3F2" Value="0x37" />
<Parameter Name="TxParamEntry_1B_ID" Offset="0x3F3" Value="0x5B" />
<Parameter Name="TxParamEntry_1B_Tx1" Offset="0x3F4" Value="0x00" />
<Parameter Name="TxParamEntry_1B_Tx2" Offset="0x3F5" Value="0x37" />
<Parameter Name="TxParamEntry_1C_ID" Offset="0x3F6" Value="0x5C" />
<Parameter Name="TxParamEntry_1C_Tx1" Offset="0x3F7" Value="0x00" />
<Parameter Name="TxParamEntry_1C_Tx2" Offset="0x3F8" Value="0x37" />
<Parameter Name="TxParamEntry_1D_ID" Offset="0x3F9" Value="0x5D" />
<Parameter Name="TxParamEntry_1D_Tx1" Offset="0x3FA" Value="0x00" />
<Parameter Name="TxParamEntry_1D_Tx2" Offset="0x3FB" Value="0x37" />
<Parameter Name="TxParamEntry_1E_ID" Offset="0x3FC" Value="0x5E" />
<Parameter Name="TxParamEntry_1E_Tx1" Offset="0x3FD" Value="0x00" />
<Parameter Name="TxParamEntry_1E_Tx2" Offset="0x3FE" Value="0x37" />
<Parameter Name="TxParamEntry_1F_ID" Offset="0x3FF" Value="0x5F" />
<Parameter Name="TxParamEntry_1F_Tx1" Offset="0x400" Value="0x00" />
<Parameter Name="TxParamEntry_1F_Tx2" Offset="0x401" Value="0x37" />
<Parameter Name="TxParamEntry_20_ID" Offset="0x402" Value="0x60" />
<Parameter Name="TxParamEntry_20_Tx1" Offset="0x403" Value="0x00" />
<Parameter Name="TxParamEntry_20_Tx2" Offset="0x404" Value="0x37" />
<Parameter Name="TxParamEntry_21_ID" Offset="0x405" Value="0x61" />
<Parameter Name="TxParamEntry_21_Tx1" Offset="0x406" Value="0x00" />
<Parameter Name="TxParamEntry_21_Tx2" Offset="0x407" Value="0x37" />
<Parameter Name="TxParamEntry_22_ID" Offset="0x408" Value="0x62" />
<Parameter Name="TxParamEntry_22_Tx1" Offset="0x409" Value="0x00" />
<Parameter Name="TxParamEntry_22_Tx2" Offset="0x40A" Value="0x37" />
<Parameter Name="TxParamEntry_23_ID" Offset="0x40B" Value="0x63" />
<Parameter Name="TxParamEntry_23_Tx1" Offset="0x40C" Value="0x00" />
<Parameter Name="TxParamEntry_23_Tx2" Offset="0x40D" Value="0x37" />
<Parameter Name="TxParamEntry_24_ID" Offset="0x40E" Value="0x64" />
<Parameter Name="TxParamEntry_24_Tx1" Offset="0x40F" Value="0x00" />
<Parameter Name="TxParamEntry_24_Tx2" Offset="0x410" Value="0x37" />
<Parameter Name="TxParamEntry_25_ID" Offset="0x411" Value="0x65" />
<Parameter Name="TxParamEntry_25_Tx1" Offset="0x412" Value="0x00" />
<Parameter Name="TxParamEntry_25_Tx2" Offset="0x413" Value="0x37" />
<Parameter Name="TxParamEntry_26_ID" Offset="0x414" Value="0x66" />
<Parameter Name="TxParamEntry_26_Tx1" Offset="0x415" Value="0x00" />
<Parameter Name="TxParamEntry_26_Tx2" Offset="0x416" Value="0x37" />
<Parameter Name="TxParamEntry_27_ID" Offset="0x417" Value="0x67" />
<Parameter Name="TxParamEntry_27_Tx1" Offset="0x418" Value="0x00" />
<Parameter Name="TxParamEntry_27_Tx2" Offset="0x419" Value="0x37" />
<Parameter Name="TxParamEntry_28_ID" Offset="0x41A" Value="0x68" />
<Parameter Name="TxParamEntry_28_Tx1" Offset="0x41B" Value="0x00" />
<Parameter Name="TxParamEntry_28_Tx2" Offset="0x41C" Value="0x37" />
<Parameter Name="TxParamEntry_29_ID" Offset="0x41D" Value="0x69" />
<Parameter Name="TxParamEntry_29_Tx1" Offset="0x41E" Value="0x00" />
<Parameter Name="TxParamEntry_29_Tx2" Offset="0x41F" Value="0x37" />
<Parameter Name="TxParamEntry_2A_ID" Offset="0x420" Value="0x6A" />
<Parameter Name="TxParamEntry_2A_Tx1" Offset="0x421" Value="0x00" />
<Parameter Name="TxParamEntry_2A_Tx2" Offset="0x422" Value="0x37" />
<Parameter Name="TxParamEntry_2B_ID" Offset="0x423" Value="0x6B" />
<Parameter Name="TxParamEntry_2B_Tx1" Offset="0x424" Value="0x00" />
<Parameter Name="TxParamEntry_2B_Tx2" Offset="0x425" Value="0x37" />
<Parameter Name="TxParamEntry_2C_ID" Offset="0x426" Value="0x6C" />
<Parameter Name="TxParamEntry_2C_Tx1" Offset="0x427" Value="0x00" />
<Parameter Name="TxParamEntry_2C_Tx2" Offset="0x428" Value="0x37" />
<Parameter Name="TxParamEntry_2D_ID" Offset="0x429" Value="0x6D" />
<Parameter Name="TxParamEntry_2D_Tx1" Offset="0x42A" Value="0x00" />
<Parameter Name="TxParamEntry_2D_Tx2" Offset="0x42B" Value="0x37" />
<Parameter Name="TxParamEntry_2E_ID" Offset="0x42C" Value="0x6E" />
<Parameter Name="TxParamEntry_2E_Tx1" Offset="0x42D" Value="0x00" />
<Parameter Name="TxParamEntry_2E_Tx2" Offset="0x42E" Value="0x37" />
<Parameter Name="TxParamEntry_2F_ID" Offset="0x42F" Value="0x6F" />
<Parameter Name="TxParamEntry_2F_Tx1" Offset="0x430" Value="0x00" />
<Parameter Name="TxParamEntry_2F_Tx2" Offset="0x431" Value="0x37" />
<Parameter Name="TxParamEntry_30_ID" Offset="0x432" Value="0x70" />
<Parameter Name="TxParamEntry_30_Tx1" Offset="0x433" Value="0x00" />
<Parameter Name="TxParamEntry_30_Tx2" Offset="0x434" Value="0x37" />
<Parameter Name="TxParamEntry_31_ID" Offset="0x435" Value="0x71" />
<Parameter Name="TxParamEntry_31_Tx1" Offset="0x436" Value="0x00" />
<Parameter Name="TxParamEntry_31_Tx2" Offset="0x437" Value="0x37" />
<Parameter Name="TxParamEntry_32_ID" Offset="0x438" Value="0x72" />
<Parameter Name="TxParamEntry_32_Tx1" Offset="0x439" Value="0x00" />
<Parameter Name="TxParamEntry_32_Tx2" Offset="0x43A" Value="0x37" />
<Parameter Name="TxParamEntry_33_ID" Offset="0x43B" Value="0x73" />
<Parameter Name="TxParamEntry_33_Tx1" Offset="0x43C" Value="0x00" />
<Parameter Name="TxParamEntry_33_Tx2" Offset="0x43D" Value="0x37" />
<Parameter Name="TxParamEntry_34_ID" Offset="0x43E" Value="0x74" />
<Parameter Name="TxParamEntry_34_Tx1" Offset="0x43F" Value="0x00" />
<Parameter Name="TxParamEntry_34_Tx2" Offset="0x440" Value="0x37" />
<Parameter Name="TxParamEntry_35_ID" Offset="0x441" Value="0x75" />
<Parameter Name="TxParamEntry_35_Tx1" Offset="0x442" Value="0x00" />
<Parameter Name="TxParamEntry_35_Tx2" Offset="0x443" Value="0x37" />
<Parameter Name="TxParamEntry_36_ID" Offset="0x444" Value="0x76" />
<Parameter Name="TxParamEntry_36_Tx1" Offset="0x445" Value="0x00" />
<Parameter Name="TxParamEntry_36_Tx2" Offset="0x446" Value="0x37" />
<Parameter Name="TxParamEntry_37_ID" Offset="0x447" Value="0x77" />
<Parameter Name="TxParamEntry_37_Tx1" Offset="0x448" Value="0x00" />
<Parameter Name="TxParamEntry_37_Tx2" Offset="0x449" Value="0x37" />
<Parameter Name="TxParamEntry_38_ID" Offset="0x44A" Value="0x78" />
<Parameter Name="TxParamEntry_38_Tx1" Offset="0x44B" Value="0x00" />
<Parameter Name="TxParamEntry_38_Tx2" Offset="0x44C" Value="0x37" />
<Parameter Name="TxParamEntry_39_ID" Offset="0x44D" Value="0x79" />
<Parameter Name="TxParamEntry_39_Tx1" Offset="0x44E" Value="0x00" />
<Parameter Name="TxParamEntry_39_Tx2" Offset="0x44F" Value="0x37" />
<Parameter Name="TxParamEntry_3A_ID" Offset="0x450" Value="0x7A" />
<Parameter Name="TxParamEntry_3A_Tx1" Offset="0x451" Value="0x00" />
<Parameter Name="TxParamEntry_3A_Tx2" Offset="0x452" Value="0x37" />
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
279 / 308
NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="TxParamEntry_3B_ID" Offset="0x453" Value="0x7B" />
<Parameter Name="TxParamEntry_3B_Tx1" Offset="0x454" Value="0x00" />
<Parameter Name="TxParamEntry_3B_Tx2" Offset="0x455" Value="0x37" />
<Parameter Name="TxParamEntry_3C_ID" Offset="0x456" Value="0x7C" />
<Parameter Name="TxParamEntry_3C_Tx1" Offset="0x457" Value="0x00" />
<Parameter Name="TxParamEntry_3C_Tx2" Offset="0x458" Value="0x37" />
<Parameter Name="TxParamEntry_3D_ID" Offset="0x459" Value="0x7D" />
<Parameter Name="TxParamEntry_3D_Tx1" Offset="0x45A" Value="0x00" />
<Parameter Name="TxParamEntry_3D_Tx2" Offset="0x45B" Value="0x37" />
<Parameter Name="TxParamEntry_3E_ID" Offset="0x45C" Value="0x7E" />
<Parameter Name="TxParamEntry_3E_Tx1" Offset="0x45D" Value="0x00" />
<Parameter Name="TxParamEntry_3E_Tx2" Offset="0x45E" Value="0x37" />
<Parameter Name="TxParamEntry_3F_ID" Offset="0x45F" Value="0x7F" />
<Parameter Name="TxParamEntry_3F_Tx1" Offset="0x460" Value="0x00" />
<Parameter Name="TxParamEntry_3F_Tx2" Offset="0x461" Value="0x37" />
<Parameter Name="TxParamEntry_40_ID" Offset="0x462" Value="0x7F" />
<Parameter Name="TxParamEntry_40_Tx1" Offset="0x463" Value="0x00" />
<Parameter Name="TxParamEntry_40_Tx2" Offset="0x464" Value="0x37" />
<Parameter Name="TxParamEntry_41_ID" Offset="0x465" Value="0x7F" />
<Parameter Name="TxParamEntry_41_Tx1" Offset="0x466" Value="0x00" />
<Parameter Name="TxParamEntry_41_Tx2" Offset="0x467" Value="0x37" />
<Parameter Name="TxParamEntry_42_ID" Offset="0x468" Value="0x7F" />
<Parameter Name="TxParamEntry_42_Tx1" Offset="0x469" Value="0x00" />
<Parameter Name="TxParamEntry_42_Tx2" Offset="0x46A" Value="0x37" />
<Parameter Name="TxParamEntry_43_ID" Offset="0x46B" Value="0x7F" />
<Parameter Name="TxParamEntry_43_Tx1" Offset="0x46C" Value="0x00" />
<Parameter Name="TxParamEntry_43_Tx2" Offset="0x46D" Value="0x37" />
<Parameter Name="TxParamEntry_44_ID" Offset="0x46E" Value="0x7F" />
<Parameter Name="TxParamEntry_44_Tx1" Offset="0x46F" Value="0x00" />
<Parameter Name="TxParamEntry_44_Tx2" Offset="0x470" Value="0x37" />
<Parameter Name="TxParamEntry_45_ID" Offset="0x471" Value="0x7F" />
<Parameter Name="TxParamEntry_45_Tx1" Offset="0x472" Value="0x00" />
<Parameter Name="TxParamEntry_45_Tx2" Offset="0x473" Value="0x37" />
<Parameter Name="TxParamEntry_46_ID" Offset="0x474" Value="0x7F" />
<Parameter Name="TxParamEntry_46_Tx1" Offset="0x475" Value="0x00" />
<Parameter Name="TxParamEntry_46_Tx2" Offset="0x476" Value="0x37" />
<Parameter Name="TxParamEntry_47_ID" Offset="0x477" Value="0x7F" />
<Parameter Name="TxParamEntry_47_Tx1" Offset="0x478" Value="0x00" />
<Parameter Name="TxParamEntry_47_Tx2" Offset="0x479" Value="0x37" />
<Parameter Name="TxParamEntry_48_ID" Offset="0x47A" Value="0x7F" />
<Parameter Name="TxParamEntry_48_Tx1" Offset="0x47B" Value="0x00" />
<Parameter Name="TxParamEntry_48_Tx2" Offset="0x47C" Value="0x37" />
<Parameter Name="TxParamEntry_49_ID" Offset="0x47D" Value="0x7F" />
<Parameter Name="TxParamEntry_49_Tx1" Offset="0x47E" Value="0x00" />
<Parameter Name="TxParamEntry_49_Tx2" Offset="0x47F" Value="0x37" />
<Parameter Name="TxParamEntry_4A_ID" Offset="0x480" Value="0x7F" />
<Parameter Name="TxParamEntry_4A_Tx1" Offset="0x481" Value="0x00" />
<Parameter Name="TxParamEntry_4A_Tx2" Offset="0x482" Value="0x37" />
<Parameter Name="TxParamEntry_4B_ID" Offset="0x483" Value="0x7F" />
<Parameter Name="TxParamEntry_4B_Tx1" Offset="0x484" Value="0x00" />
<Parameter Name="TxParamEntry_4B_Tx2" Offset="0x485" Value="0x37" />
<Parameter Name="TxParamEntry_4C_ID" Offset="0x486" Value="0x7F" />
<Parameter Name="TxParamEntry_4C_Tx1" Offset="0x487" Value="0x00" />
<Parameter Name="TxParamEntry_4C_Tx2" Offset="0x488" Value="0x37" />
<Parameter Name="TxParamEntry_4D_ID" Offset="0x489" Value="0x7F" />
<Parameter Name="TxParamEntry_4D_Tx1" Offset="0x48A" Value="0x00" />
<Parameter Name="TxParamEntry_4D_Tx2" Offset="0x48B" Value="0x37" />
<Parameter Name="TxParamEntry_4E_ID" Offset="0x48C" Value="0x7F" />
<Parameter Name="TxParamEntry_4E_Tx1" Offset="0x48D" Value="0x00" />
<Parameter Name="TxParamEntry_4E_Tx2" Offset="0x48E" Value="0x37" />
<Parameter Name="dummy" Offset="0x48F" Value="0x000000" />
</Region>
<Region RegionName="LPCD_SETTINGS" RegionAccess="RW" RegionType="DATA">
<Parameter Name="avg_samples" Offset="0x492" Value="0x06" />
<Parameter Name="lpcd_rssi_target" Offset="0x494" Value="0x02A3" />
<Parameter Name="lpcd_rssi_hyst" Offset="0x496" Value="0x1F" />
<Parameter Name="Config" Offset="0x497" Value="0x003B" />
<Parameter Name="lpcd_threshold_coarse" Offset="0x49A" Value="0x00500050" />
<Parameter Name="lpcd_threshold_fine" Offset="0x49E" Value="0x7FFF7FFF" />
</Region>
<Region RegionName="ULPCD_CONFIG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="Vddpa_Ctrl" Offset="0x4BF" Value="0x0206" />
<Parameter Name="Timing_Ctrl" Offset="0x4C2" Value="0x3D" />
<Parameter Name="Voltage_Ctrl" Offset="0x4C6" Value="0x6A" />
</Region>
<Region RegionName="ULPCD_SETTINGS" RegionAccess="RW" RegionType="DATA">
<Parameter Name="rssi_nsp" Offset="0x4C9" Value="0x10" />
<Parameter Name="rssi_no_samples" Offset="0x4CA" Value="0x00" />
<Parameter Name="thresh_lvl" Offset="0x4CB" Value="0x0C" />
<Parameter Name="polarity" Offset="0x4CC" Value="0x01" />
</Region>
<Region RegionName="TXIRQ_GUARD" RegionAccess="RW" RegionType="DATA">
<Parameter Name="TXIRQ_GuardTime" Offset="0x559" Value="0x000FFFFF" />
</Region>
<Region RegionName="FDT_DEFAULT" RegionAccess="RW" RegionType="DATA">
<Parameter Name="FDT_DefaultVal" Offset="0x55D" Value="0x000472AC" />
</Region>
<Region RegionName="RXIRQ_GUARD" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RXIRQ_GuardTime" Offset="0x561" Value="0x000F4240" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_CORR" RegionAccess="RW" RegionType="DATA">
<Parameter Name="Correction_Entry0" Offset="0xBAD" Value="0x0000" />
<Parameter Name="Correction_Entry1" Offset="0xBAF" Value="0x0000" />
<Parameter Name="Correction_Entry2" Offset="0xBB1" Value="0x0000" />
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
280 / 308
NXP Semiconductors
PN5190
NFC frontend
<Parameter Name="Correction_Entry3" Offset="0xBB3" Value="0x0000" />
<Parameter Name="Correction_Entry4" Offset="0xBB5" Value="0x0000" />
<Parameter Name="Correction_Entry5" Offset="0xBB7" Value="0x0000" />
<Parameter Name="Correction_Entry6" Offset="0xBB9" Value="0x0000" />
<Parameter Name="Correction_Entry7" Offset="0xBBB" Value="0x0000" />
<Parameter Name="Correction_Entry8" Offset="0xBBD" Value="0x0000" />
<Parameter Name="Correction_Entry9" Offset="0xBBF" Value="0x0000" />
<Parameter Name="Correction_Entry10" Offset="0xBC1" Value="0x0000" />
<Parameter Name="Correction_Entry11" Offset="0xBC3" Value="0x0000" />
<Parameter Name="Correction_Entry12" Offset="0xBC5" Value="0x0000" />
<Parameter Name="Correction_Entry13" Offset="0xBC7" Value="0x0000" />
<Parameter Name="Correction_Entry14" Offset="0xBC9" Value="0x0000" />
<Parameter Name="Correction_Entry15" Offset="0xBCB" Value="0x0000" />
<Parameter Name="Correction_Entry16" Offset="0xBCD" Value="0x0000" />
<Parameter Name="Correction_Entry17" Offset="0xBCF" Value="0x0000" />
<Parameter Name="Correction_Entry18" Offset="0xBD1" Value="0x0000" />
<Parameter Name="Correction_Entry19" Offset="0xBD3" Value="0x0000" />
<Parameter Name="Correction_Entry20" Offset="0xBD5" Value="0x0000" />
<Parameter Name="Correction_Entry21" Offset="0xBD7" Value="0x0000" />
<Parameter Name="Correction_Entry22" Offset="0xBD9" Value="0x0000" />
<Parameter Name="Correction_Entry23" Offset="0xBDB" Value="0x0000" />
<Parameter Name="Correction_Entry24" Offset="0xBDD" Value="0x0000" />
<Parameter Name="Correction_Entry25" Offset="0xBDF" Value="0x0000" />
<Parameter Name="Correction_Entry26" Offset="0xBE1" Value="0x0000" />
<Parameter Name="Correction_Entry27" Offset="0xBE3" Value="0x0000" />
<Parameter Name="Correction_Entry28" Offset="0xBE5" Value="0x0000" />
<Parameter Name="Correction_Entry29" Offset="0xBE7" Value="0x0000" />
<Parameter Name="Correction_Entry30" Offset="0xBE9" Value="0x0000" />
<Parameter Name="Correction_Entry31" Offset="0xBEB" Value="0x0000" />
<Parameter Name="Correction_Entry32" Offset="0xBED" Value="0x0000" />
<Parameter Name="Correction_Entry33" Offset="0xBEF" Value="0x0000" />
<Parameter Name="Correction_Entry34" Offset="0xBF1" Value="0x0000" />
<Parameter Name="Correction_Entry35" Offset="0xBF3" Value="0x0000" />
<Parameter Name="Correction_Entry36" Offset="0xBF5" Value="0x0000" />
<Parameter Name="Correction_Entry37" Offset="0xBF7" Value="0x0000" />
<Parameter Name="Correction_Entry38" Offset="0xBF9" Value="0x0000" />
<Parameter Name="Correction_Entry39" Offset="0xBFB" Value="0x0000" />
<Parameter Name="Correction_Entry40" Offset="0xBFD" Value="0x0000" />
<Parameter Name="Correction_Entry41" Offset="0xBFF" Value="0x0000" />
<Parameter Name="Correction_Entry42" Offset="0xC01" Value="0x0000" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_1" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RTRANS0" Offset="0xC03" Value="0xEAE6DCCD" />
<Parameter Name="RTRANS1" Offset="0xC07" Value="0xFAF6F2EE" />
<Parameter Name="RTRANS2" Offset="0xC0B" Value="0xFFFFFFFF" />
<Parameter Name="RTRANS3" Offset="0xC0F" Value="0xFFFFFFFF" />
<Parameter Name="FTRANS0" Offset="0xC13" Value="0xCACACACA" />
<Parameter Name="FTRANS1" Offset="0xC17" Value="0xCACACAD8" />
<Parameter Name="FTRANS2" Offset="0xC1B" Value="0xCACACACA" />
<Parameter Name="FTRANS3" Offset="0xC1F" Value="0xCACACACA" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_2" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RTRANS0" Offset="0xC23" Value="0xF0EAE3DA" />
<Parameter Name="RTRANS1" Offset="0xC27" Value="0xFAF9F6F4" />
<Parameter Name="RTRANS2" Offset="0xC2B" Value="0xFEFDFDFC" />
<Parameter Name="RTRANS3" Offset="0xC2F" Value="0xFFFFFFFE" />
<Parameter Name="FTRANS0" Offset="0xC33" Value="0xFEFFFFFF" />
<Parameter Name="FTRANS1" Offset="0xC37" Value="0xFCFDFDFE" />
<Parameter Name="FTRANS2" Offset="0xC3B" Value="0xF4F6F9FA" />
<Parameter Name="FTRANS3" Offset="0xC3F" Value="0xDAE3EAF0" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_3" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RTRANS0" Offset="0xC43" Value="0x00000000" />
<Parameter Name="RTRANS1" Offset="0xC47" Value="0x00000000" />
<Parameter Name="RTRANS2" Offset="0xC4B" Value="0x00000000" />
<Parameter Name="RTRANS3" Offset="0xC4F" Value="0x00000000" />
<Parameter Name="FTRANS0" Offset="0xC53" Value="0x00000000" />
<Parameter Name="FTRANS1" Offset="0xC57" Value="0x00000000" />
<Parameter Name="FTRANS2" Offset="0xC5B" Value="0x00000000" />
<Parameter Name="FTRANS3" Offset="0xC5F" Value="0x00000000" />
</Region>
<Region RegionName="TX_SHAPING_PROPRIETARY_4" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RTRANS0" Offset="0xC63" Value="0x00000000" />
<Parameter Name="RTRANS1" Offset="0xC67" Value="0x00000000" />
<Parameter Name="RTRANS2" Offset="0xC6B" Value="0x00000000" />
<Parameter Name="RTRANS3" Offset="0xC6F" Value="0x00000000" />
<Parameter Name="FTRANS0" Offset="0xC73" Value="0x00000000" />
<Parameter Name="FTRANS1" Offset="0xC77" Value="0x00000000" />
<Parameter Name="FTRANS2" Offset="0xC7B" Value="0x00000000" />
<Parameter Name="FTRANS3" Offset="0xC7F" Value="0x00000000" />
</Region>
<Region RegionName="TX_DRIVER_NOV" RegionAccess="RW" RegionType="DATA">
<Parameter Name="CfgNovCal" Offset="0xC83" Value="0x42" />
<Parameter Name="VddpaCalVal1" Offset="0xC84" Value="0x03" />
<Parameter Name="VddpaCalVal2" Offset="0xC85" Value="0x15" />
<Parameter Name="CfgThreshold" Offset="0xC86" Value="0x08" />
<Parameter Name="UserOffsets1" Offset="0xC87" Value="0x8A0A0C00" />
<Parameter Name="UserOffsets2" Offset="0xC8B" Value="0x09080D03" />
</Region>
<Region RegionName="USER_PMU_INT_1" RegionAccess="RW" RegionType="DATA">
<Parameter Name="EnableFastVDDPADischarge" Offset="0xC8F" Value="0x00" />
</Region>
<Region RegionName="ARC_SETTINGS_1" RegionAccess="RW" RegionType="DATA">
<Parameter Name="RmArcA_106_FDT" Offset="0xC9D" Value="0x812A805080508050C050" />
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
281 / 308
NXP Semiconductors
PN5190
NFC frontend
</Region>
<Region RegionName="HIF_DELAY_CFG" RegionAccess="RW" RegionType="DATA">
<Parameter Name="HifDelay" Offset="0xCDD" Value="0x32" />
</Region>
<Region RegionName="RegisterValuePair" RegionOffset="0x74" RegionType="PROTOCOL" RegionAccess="INDIRECT">
<Protocol ProtocolName="TX ISO14443A 106" ProtocolIndex="0x00" ProtocolOffset="0x74">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000F00FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00003D41"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00220104"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00220104"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A 212" ProtocolIndex="0x01" ProtocolOffset="0xA1">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00110105"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00110105"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A 424" ProtocolIndex="0x02" ProtocolOffset="0xCE">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00060106"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00060106"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A 848" ProtocolIndex="0x03" ProtocolOffset="0xFB">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00020107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00020107"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443B 106" ProtocolIndex="0x04" ProtocolOffset="0x128">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00030107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000084"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443B 212" ProtocolIndex="0x05" ProtocolOffset="0x155">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00030107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000085"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443B 424" ProtocolIndex="0x06" ProtocolOffset="0x182">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00030107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000086"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443B 848" ProtocolIndex="0x07" ProtocolOffset="0x1AF">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00030107"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000087"></Register>
</Protocol>
<Protocol ProtocolName="TX Felica 212" ProtocolIndex="0x08" ProtocolOffset="0x1DC">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
282 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000015"></Register>
</Protocol>
<Protocol ProtocolName="TX Felica 424" ProtocolIndex="0x09" ProtocolOffset="0x209">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000016"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO15693 ASK100" ProtocolIndex="0x0A" ProtocolOffset="0x236">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000F00FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000004"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00020084"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000043"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO15693 ASK10" ProtocolIndex="0x0B" ProtocolOffset="0x263">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000004"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00020084"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000043"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO180003m3 TARI=18.88us" ProtocolIndex="0x0F" ProtocolOffset="0x290">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000F00FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000004"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00020084"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000043"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO180003m3 TARI=9.44us" ProtocolIndex="0x10" ProtocolOffset="0x2BD">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000004"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00020084"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000043"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A-PICC 106" ProtocolIndex="0x13" ProtocolOffset="0x2EA">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x001F002E"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00008002"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x0000002C"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000002C"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A-PICC 212" ProtocolIndex="0x14" ProtocolOffset="0x317">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00007402"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000003D"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A-PICC 424" ProtocolIndex="0x15" ProtocolOffset="0x344">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00007402"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x0000002E"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000003E"></Register>
</Protocol>
<Protocol ProtocolName="TX ISO14443A-PICC 848" ProtocolIndex="0x16" ProtocolOffset="0x371">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00007402"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x0000002F"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
283 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000003F"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-PT-212 212" ProtocolIndex="0x17" ProtocolOffset="0x39E">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000015"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-PT-424 424" ProtocolIndex="0x18" ProtocolOffset="0x3CB">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000016"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-AT-106 106" ProtocolIndex="0x19" ProtocolOffset="0x3F8">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000F00FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00003D41"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00220104"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00220104"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-AT-212 212" ProtocolIndex="0x1A" ProtocolOffset="0x425">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000015"></Register>
</Protocol>
<Protocol ProtocolName="TX NFC-AT-424 424" ProtocolIndex="0x1B" ProtocolOffset="0x452">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000016"></Register>
</Protocol>
<Protocol ProtocolName="TX GTM All" ProtocolIndex="0x1C" ProtocolOffset="0x47F">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000700FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x001F002E"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00008002"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x0000002C"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x0000002C"></Register>
</Protocol>
<Protocol ProtocolName="TX B_Prime All" ProtocolIndex="0x1D" ProtocolOffset="0x4AC">
<Register RegisterName="CLIF_SS_TX1_CMCFG" RegisterLogicalAddress="0x3B" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_SS_TX2_CMCFG" RegisterLogicalAddress="0x3C" RegisterValue="0x000900FF"></Register>
<Register RegisterName="CLIF_TX_UNDERSHOOT_CONFIG" RegisterLogicalAddress="0x13" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_OVERSHOOT_CONFIG" RegisterLogicalAddress="0x14" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TRANSCEIVE_CONTROL" RegisterLogicalAddress="0x08" RegisterValue="0x00000001"></Register>
<Register RegisterName="CLIF_SS_TX_CFG" RegisterLogicalAddress="0x15" RegisterValue="0x00002289"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_MOD" RegisterLogicalAddress="0x0C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_SYMBOL23_DEF" RegisterLogicalAddress="0x0D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_TX_DATA_MOD" RegisterLogicalAddress="0x10" RegisterValue="0x00000084"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A 106" ProtocolIndex="0x80" ProtocolOffset="0x506">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0202"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x09BD307F"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x500800B0"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0810203F"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00080808"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4D24A4"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
284 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x7B75FFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F51AA"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x4A8B60A7"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A 212" ProtocolIndex="0x81" ProtocolOffset="0x57E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x10F8024C"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800C0"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x8A866150"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A 424" ProtocolIndex="0x82" ProtocolOffset="0x5F6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x14F80228"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401000D0"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x383F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x88046548"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A 848" ProtocolIndex="0x83" ProtocolOffset="0x66E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x28F80209"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401000E0"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x40026508"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443B 106" ProtocolIndex="0x84" ProtocolOffset="0x6E6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x3E380248"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000045"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000B6"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
285 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x95086250"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443B 212" ProtocolIndex="0x85" ProtocolOffset="0x75E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x10380248"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000045"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000C6"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x94866248"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443B 424" ProtocolIndex="0x86" ProtocolOffset="0x7D6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x20380248"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000045"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000D6"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x94046650"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443B 848" ProtocolIndex="0x87" ProtocolOffset="0x84E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x0A380209"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000045"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000E6"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D23400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x5C026608"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX Felica 212" ProtocolIndex="0x88" ProtocolOffset="0x8C6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x10780203"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x110000C4"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
286 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x0088D238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D27400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x01806100"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX Felica 424" ProtocolIndex="0x89" ProtocolOffset="0x93E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x10780203"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x010000D4"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x0088D238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00D27400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x48826548"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 6P6" ProtocolIndex="0x8A" ProtocolOffset="0x9B6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x40080088"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0xDB0660FF"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 26" ProtocolIndex="0x8B" ProtocolOffset="0xA2E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x40080098"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x8B1660F7"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 53" ProtocolIndex="0x8C" ProtocolOffset="0xAA6">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800A8"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
287 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x432B609F"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 Plutus 106" ProtocolIndex="0x8D" ProtocolOffset="0xB1E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401000B8"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x42A2689F"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO15693 Plutus 212" ProtocolIndex="0x8E" ProtocolOffset="0xB96">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815307D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401800C8"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x422C689F"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO180003m3 Manch424_4 53" ProtocolIndex="0x8F" ProtocolOffset="0xC0E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815077D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800AA"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000017FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFE"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F5194"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x6B3B60AB"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO180003m3 Manch424_2 106" ProtocolIndex="0x90" ProtocolOffset="0xC86">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
288 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815077D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800BC"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000017FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFE"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F5194"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x23406053"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO180003m3 Manch848_4 106" ProtocolIndex="0x91" ProtocolOffset="0xCFE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815077D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400800BA"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000017FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFE"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F5194"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x6ABB60AB"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO180003m3 Manch424_2 212" ProtocolIndex="0x92" ProtocolOffset="0xD76">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x000A0200"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x0815077D"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x401000CC"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000017FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x0D81830E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xAD4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x6A8FFFFE"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F5194"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x6A3264AB"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A-PICC 106" ProtocolIndex="0x93" ProtocolOffset="0xDEE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000B1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000037FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79600A0"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A-PICC 212" ProtocolIndex="0x94" ProtocolOffset="0xE66">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00000032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
289 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000C1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79700A0"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A-PICC 424" ProtocolIndex="0x95" ProtocolOffset="0xEDE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00000032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000D1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79700A0"></Register>
</Protocol>
<Protocol ProtocolName="RX ISO14443A-PICC 848" ProtocolIndex="0x96" ProtocolOffset="0xF56">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00000032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000E1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79700A0"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-PT-212 212" ProtocolIndex="0x97" ProtocolOffset="0xFCE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000C5"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x20100000"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-PT-424 424" ProtocolIndex="0x98" ProtocolOffset="0x1046">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
290 / 308
NXP Semiconductors
PN5190
NFC frontend
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000D5"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x20060200"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-AT-106 106" ProtocolIndex="0x99" ProtocolOffset="0x10BE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000B1"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000037FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xB79600A0"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-AT-212 212" ProtocolIndex="0x9A" ProtocolOffset="0x1136">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000C5"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x20100000"></Register>
</Protocol>
<Protocol ProtocolName="RX NFC-AT-424 424" ProtocolIndex="0x9B" ProtocolOffset="0x11AE">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x000000D5"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x20060200"></Register>
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</Protocol>
<Protocol ProtocolName="RX GTM All" ProtocolIndex="0x9C" ProtocolOffset="0x1226">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0700E437"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x00100032"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0004C935"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00A24820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x4000003F"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00A93979"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x00600081"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x000037FF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x00280200"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x00000000"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x00000003"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0xBF9600A0"></Register>
</Protocol>
<Protocol ProtocolName="RX B_Prime All" ProtocolIndex="0x9D" ProtocolOffset="0x129E">
<Register RegisterName="CLIF_ANA_RX_CTRL" RegisterLogicalAddress="0x43" RegisterValue="0x0000E407"></Register>
<Register RegisterName="CLIF_DCOC_CONFIG" RegisterLogicalAddress="0x33" RegisterValue="0x000000F4"></Register>
<Register RegisterName="CLIF_RXM_CTRL" RegisterLogicalAddress="0x35" RegisterValue="0x0044893E"></Register>
<Register RegisterName="CLIF_GCM_CONFIG2" RegisterLogicalAddress="0x38" RegisterValue="0x00024820"></Register>
<Register RegisterName="CLIF_GCM_CONFIG1" RegisterLogicalAddress="0x39" RegisterValue="0x00000FC0"></Register>
<Register RegisterName="CLIF_GCM_CONFIG0" RegisterLogicalAddress="0x3A" RegisterValue="0x00D03939"></Register>
<Register RegisterName="CLIF_ANA_AGC_DCO_CTRL" RegisterLogicalAddress="0x36" RegisterValue="0x01000008"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_CONFIG" RegisterLogicalAddress="0x1F" RegisterValue="0x02380248"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_ENABLES" RegisterLogicalAddress="0x21" RegisterValue="0x00000055"></Register>
<Register RegisterName="CLIF_SIGPRO_CONFIG" RegisterLogicalAddress="0x1D" RegisterValue="0x400000BE"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG1" RegisterLogicalAddress="0x23" RegisterValue="0x0C082155"></Register>
<Register RegisterName="CLIF_SIGPRO_NOISE_CONFIG2" RegisterLogicalAddress="0x24" RegisterValue="0x00085510"></Register>
<Register RegisterName="CLIF_RX_ERROR_CONFIG" RegisterLogicalAddress="0x27" RegisterValue="0x00003FFF"></Register>
<Register RegisterName="CLIF_RX_EMD_0_CONFIG" RegisterLogicalAddress="0x48" RegisterValue="0x1F200000"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG1" RegisterLogicalAddress="0x29" RegisterValue="0x01B0618E"></Register>
<Register RegisterName="CLIF_SIGPRO_IIR_CONFIG0" RegisterLogicalAddress="0x2A" RegisterValue="0x000A85CC"></Register>
<Register RegisterName="CLIF_DGRM_DAC_FILTER" RegisterLogicalAddress="0x2B" RegisterValue="0x00889238"></Register>
<Register RegisterName="CLIF_DGRM_CONFIG" RegisterLogicalAddress="0x2C" RegisterValue="0x00E63400"></Register>
<Register RegisterName="CLIF_DGRM_BBA" RegisterLogicalAddress="0x2D" RegisterValue="0xED4C64A4"></Register>
<Register RegisterName="CLIF_DGRM_DCO" RegisterLogicalAddress="0x2E" RegisterValue="0xC0F7C1F0"></Register>
<Register RegisterName="CLIF_DGRM_HF_ATT" RegisterLogicalAddress="0x2F" RegisterValue="0x2A8FFFFF"></Register>
<Register RegisterName="CLIF_DGRM_RSSI" RegisterLogicalAddress="0x30" RegisterValue="0x393F518A"></Register>
<Register RegisterName="CLIF_SIGPRO_RM_TECH" RegisterLogicalAddress="0x22" RegisterValue="0x95086250"></Register>
<Register RegisterName="CLIF_SIGPRO_CM_CONFIG" RegisterLogicalAddress="0x37" RegisterValue="0x1FE00001"></Register>
</Protocol>
</Region>
</EEPROM>
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20 Abbreviations
Table 340.ꢀAbbreviations
Acronym
ADC
Description
analog-to-digital converter
automatic gain control
adaptive receiver control
adaptive waveshape control
contactless interface
AGC
ARC
AWC
CLIF
DAC
digital-to-analog converter
DC-DC
switch-mode voltage regulator which uses an inductor to store and transfer
energy to the output, used for a power supply voltage conversion. PN5190B1
integrates a step-up/boost converter
DPC
EMD
GPIO
HPD
LDO
LPCD
MISO
MOSI
NSS
OS
dynamic power control
electromagnetic disturbance
general-purpose input output
hard power down
low dropout regulator
low-power card detection
SPI interface Master In Slave Out
SPI interface Master Out Slave In
SPI interface active-low slave-select signal
operating system
PCB
PCD
PICC
RF
printed-circuit board
power card detection
proximity inductive coupling card
radio frequency
RSSI
SCK
SCL
SPI
receiver signal strength indicator
SPI interface serial clock
I2C interface serial clock
serial peripheral interface
display technology: thin-film transistor-display
transmit
TFT
TX
UID
Unique identifier of a card, used during anti-collision sequence to select one
out of multiple cards.
ULPCD
ultra low-power card detection
PN5190B1
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21 References
[1] Application note - AN12551 PN5190 Design-in document
[2] Application note - AN12549 PN5190 Antenna design guide
[3] Product data sheet addendum - AD PN5190 Instruction layer
PN5190B1
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22 Revision history
Table 341.ꢀRevision history
Document ID
Release date Data sheet status
Supersedes
PN5190B1 v. 3.0 20210421
Product data sheet
PN5190B1 v. 1.0
Modifications:
• General update
• Data sheet status changed to "Product data sheet"
PN5190B1 v. 1.0 20210322
Objective data sheet
-
Modifications:
• First official released version
PN5190B1
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23 Legal information
23.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
23.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
23.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
23.4 Licenses
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
This NXP Semiconductors IC is ISO/IEC
14443 Type B software enabled and is
licensed under Innovatron’s Contactless
Card patents license for ISO/IEC 14443 B.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
The license includes the right to use the IC
in systems and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the
Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/
IEC 21481 does not convey an implied license under any patent right
infringed by implementation of any of those standards. Purchase of NXP
Semiconductors IC does not include a license to any NXP patent (or other
IP right) covering combinations of those products with other products,
whether hardware or software.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
23.5 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
for the design and operation of its applications and products throughout
their lifecycles to reduce the effect of these vulnerabilities on customer’s
applications and products. Customer’s responsibility also extends to other
open and/or proprietary technologies supported by NXP products for use
in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up
appropriately. Customer shall select products with security features that best
meet rules, regulations, and standards of the intended application and make
the ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may
be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
reporting, and solution release to security vulnerabilities of NXP products.
I2C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
DESFire — is a trademark of NXP B.V.
ICODE and I-CODE — are trademarks of NXP B.V.
MIFARE Plus — is a trademark of NXP B.V.
MIFARE Ultralight — is a trademark of NXP B.V.
MIFARE Classic — is a trademark of NXP B.V.
NTAG — is a trademark of NXP B.V.
NXP — wordmark and logo are trademarks of NXP B.V.
FeliCa — is a trademark of Sony Corporation.
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NXP Semiconductors
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NFC frontend
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Quick reference data .........................................6
Tab. 48. SWITCH_MODE_STANDBY ...........................81
Tab. 49. STANDBY control parameter: Bitmask ............81
Tab. 50. EVT_SWITCH_MODE_LPCD ......................... 82
Tab. 51. SWITCH_MODE_LPCD .................................. 82
Tab. 52. SWITCH_MODE_DOWNLOAD .......................83
Tab. 53. GET_DIE_ID ....................................................83
Tab. 54. GET_VERSION ...............................................84
Tab. 55. PRBS_TEST ....................................................85
Tab. 56. RESPONSE STATUS CODES LIST ............... 85
Tab. 57. IRQ EVENT LIST ............................................87
Tab. 58. Register Overview ...........................................88
Tab. 59. SYSTEM_CONFIG register (address
0000h) bit description ......................................91
Tab. 60. EVENT_ENABLE register (address 0001h)
bit description ..................................................91
Tab. 61. EVENT_STATUS register (address 0002h)
bit description ..................................................92
Tab. 62. EMVCO_EMD_CONTROL register
Ordering information ..........................................7
Pin description VFBGA64 ................................. 9
Pin description HVQFN40 ............................... 13
Supply voltage range ...................................... 27
DPC_LOOKUP_TABLE element, defining
the configuration for one dedicated VDDPA
voltage .............................................................33
Dynamic power control characteristics ............33
ARC_VDDPA (0139Eh) EEPROM
Tab. 7.
Tab. 8.
configuration bit description ............................ 37
ARC_RM_A106 (address 013Eh)
EEPROM configuration bit description ............ 37
Tab. 9.
Tab. 10. Low-Power Card Detection: relevant
EEPROM configuration ................................... 43
Tab. 11. Low-Power Card Detection - semi-
autonomous mode: relevant REGISTERS ...... 44
Tab. 12. DEBUG SIGNALS ...........................................47
Tab. 13. TRIGGER SIGNALS ....................................... 49
Tab. 14. Host interface commands ............................... 52
Tab. 15. WRITE_REGISTER .........................................54
Tab. 16. WRITE_REGISTER_OR_MASK ..................... 55
Tab. 17. WRITE_REGISTER_AND_MASK ...................55
Tab. 18. WRITE_REGISTER_MULTIPLE ..................... 56
Tab. 19. READ_REGISTER .......................................... 57
Tab. 20. READ_REGISTER_MULTIPLE .......................57
Tab. 21. WRITE_EEPROM ........................................... 58
Tab. 22. READ_EEPROM .............................................59
Tab. 23. TANSMIT_RF_DATA ....................................... 60
Tab. 24. RETRIEVE_RF_DATA .....................................60
Tab. 25. EXCHANGE_RF_DATA ...................................61
Tab. 26. EXCHANGE_RF_DATA Parameter RF
(address 0003h) bit description .......................92
Tab. 63. FELICA_EMD_CONTROL register
(address 0004h) bit description .......................93
Tab. 64. RX_STATUS register (address 0005h) bit
description ....................................................... 94
Tab. 65. RX_STATUS_ERROR register (address
0006h) bit description ......................................95
Tab. 66. CLIF_STATUS register (address 0007h) bit
description ....................................................... 97
Tab. 67. RF_EXCHANGE_CONTROL register
(address 0008h) bit description .......................98
Tab. 68. TX_SYMBOL01_MOD register (address
0009h) bit description ......................................99
Tab. 69. TX_SYMBOL1_DEF register (address
000Ah) bit description ..................................... 99
Tab. 70. TX_SYMBOL0_DEF register (address
000Bh) bit description ................................... 100
Tab. 71. TX_SYMBOL23_MOD register (address
000Ch) bit description ................................... 100
Tab. 72. TX_SYMBOL23_DEF register (address
000Dh) bit description ................................... 100
Tab. 73. TX_SYMBOL_CONFIG register (address
000Eh) bit description ................................... 100
Tab. 74. TX_FRAME_CONFIG register (address
000Fh) bit description ....................................101
Tab. 75. TX_DATA_MOD register (address 0010h)
bit description ................................................102
Tab. 76. TX_CLIF_WAIT register (address 0011h)
bit description ................................................103
Tab. 77. TX_CRC_CONFIG (address 0012h) bit
description ..................................................... 104
Tab. 78. SS_TX_CONFIG register (address 0015h)
bit description ................................................104
Tab. 79. SS_TX1_RMCFG register (address 0016h)
bit description ................................................105
Tab. 80. SS_TX2_RMCFG register (address 0017h)
bit description ................................................105
Exchange Config: Bitmask .............................. 62
Tab. 27. MFC_AUTHENTICATE ....................................62
Tab. 28. EPC_GEN2_INVENTORY ...............................64
Tab. 29. LOAD_RF_CONFIGURATION ........................ 66
Tab. 30. TX Parameter for command LOAD_RF_
CONFIGURATION ...........................................66
Tab. 31. RX Parameter for command LOAD_RF_
CONFIGURATION ...........................................67
Tab. 32. UPDATE_RF_CONFIGURATION ....................69
Tab. 33. GET_RF_CONFIGURATION ...........................69
Tab. 34. RF_ON ............................................................ 70
Tab. 35. RF_OFF ...........................................................71
Tab. 36. RF_OFF ...........................................................71
Tab. 37. RF_OFF ...........................................................72
Tab. 38. CTS_ENABLE ................................................. 73
Tab. 39. CTS_CONFIGURE ..........................................73
Tab. 40. CTS_RETRIEVE_LOG ....................................77
Tab. 41. RECEIVE_RF_DATA .......................................78
Tab. 42. EVT_SWITCH_MODE_NORMAL ................... 79
Tab. 43. SWITCH_MODE_NORMAL ............................ 79
Tab. 44. EVT_SWITCH_MODE_AUTOCOLL ............... 79
Tab. 45. SWITCH_MODE_AUTOCOLL ........................ 80
Tab. 46. RF Technologies parameter: Bitmask ..............80
Tab. 47. EVT_SWITCH_MODE_STANDBY ..................81
PN5190B1
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Product data sheet
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NXP Semiconductors
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NFC frontend
Tab. 81. SS_TX_TRANS_CFG register (address
0019h) bit description ....................................106
Tab. 82. SIGPRO_RM_PATTERN register (address
0020h) bit description ....................................106
Tab. 83. SIGPRO_RM_TECH register (address
0022h) bit description ....................................106
Tab. 84. RX_FRAME_LENGTH register (address
0026h) bit description ....................................107
Tab. 85. RX_ERROR_CONFIG register (address
0027h) bit description ....................................107
Tab. 86. RX_CTRL_STATUS register (address
0028h) bit description ....................................107
Tab. 87. SIGPRO_IIR_CONFIG0 register (address
002Ah) bit description ................................... 108
Tab. 88. DGRM_RSSI register (address 0030h) bit
description ..................................................... 108
Tab. 89. RX_CRC_CONFIG register (address
0031h) bit description ....................................108
Tab. 90. RX_WAIT register (address 0032h) bit
description ..................................................... 109
Tab. 91. RXM_CTRL register (address 0035h) bit
description ..................................................... 110
Tab. 92. SS_TX1_CMCFG register (address 003Bh)
bit description ................................................110
Tab. 93. SS_TX2_CMCFG register (address 003Ch)
bit description ................................................110
Tab. 94. TIMER0_CONFIG register (address
003Dh) bit description ................................... 110
Tab. 95. TIMER0_RELOAD register (address
003Eh) bit description ................................... 111
Tab. 96. TIMER1_CONFIG register (address
003Fh) bit description ....................................111
Tab. 97. TIMER1_RELOAD register (address
0040h) bit description ....................................113
Tab. 98. EMD_1_CFG register (address 0047h) bit
description ..................................................... 113
Tab. 99. EMD_0_CONFIG register (address 0048h)
bit description ................................................114
Tab. 100. LPCD_CALIBRATE_CTRL register
(address 0050h) bit description .....................114
Tab. 101. IQ_CHANNEL_VALS register (address
0051h) bit description ....................................114
Tab. 102. PAD_CONFIG register (address 0052h) bit
description ..................................................... 114
Tab. 103. CALIBRATE_STATUS register (address
0053h) bit description ....................................115
Tab. 104. TXLDO_VDDPA_CONFIG register
(address 0054h) bit description .....................115
Tab. 105. GENERAL_ERROR_STATUS register
(address 0055h) bit description .....................116
Tab. 106. TXLDO_VOUT_CURR register (address
0056h) bit description ....................................116
Tab. 107. CLIF_DAC register (address 0057h) bit
description ..................................................... 117
Tab. 108. PMU_ANA_SMPS_CTRL_REG register
(address 0058h) bit description .....................118
Tab. 109. RXM_FREQ register (address 0059h) bit
description ..................................................... 118
Tab. 110. RXM_RSSI register (address 005Ah) bit
description ..................................................... 118
Tab. 111. TEMP_SENSOR register (address 005Bh)
bit description ................................................119
Tab. 112. TX_NOV_CALIBRATE register (address
005Dh) bit description ................................... 119
Tab. 113. SS_TX1_RTRTRANS0 register (address
0080h) bit description ....................................119
Tab. 114. SS_TX1_RTRTRANS1 register (address
0081h) bit description ....................................119
Tab. 115. SS_TX1_RTRTRANS2 register (address
0082h) bit description ....................................120
Tab. 116. SS_TX1_RTRTRANS0 register (address
0080h) bit description ....................................120
Tab. 117. SS_TX2_RTRTRANS0 register (address
00804) bit description ....................................120
Tab. 118. SS_TX2_RTRTRANS1 register (address
0085h) bit description ....................................120
Tab. 119. SS_TX2_RTRTRANS2 register (address
0086h) bit description ....................................121
Tab. 120. SS_TX2_RTRTRANS3 register (address
0087h) bit description ....................................121
Tab. 121. SS_TX1_FTRTRANS0 register (address
0088h) bit description ....................................121
Tab. 122. SS_TX1_FTRTRANS1 register (address
0089h) bit description ....................................121
Tab. 123. SS_TX1_FTRTRANS2 register (address
008Ah) bit description ................................... 121
Tab. 124. SS_TX1_FTRTRANS3 register (address
008Bh) bit description ................................... 122
Tab. 125. SS_TX2_FTRTRANS0 register (address
008Ch) bit description ................................... 122
Tab. 126. SS_TX2_FTRTRANS1 register (address
008Dh) bit description ................................... 122
Tab. 127. SS_TX2_FTRTRANS2 register (address
008Eh) bit description ................................... 122
Tab. 128. SS_TX2_FTRTRANS3 register (address
008Fh) bit description ....................................123
Tab. 129. EEPROM CONFIGURATION REGISTER .....123
Tab. 130. PWR_CONFIG (address 0000h) EEPROM
configuration bit description ...........................129
Tab. 131. DCDC_CONFIG (address 0001h)
EEPROM configuration bit description .......... 129
Tab. 132. TXLDO_CONFIG (address 0002h)
EEPROM configuration bit description .......... 130
Tab. 133. TXLDO_VDDPA_HIGH (address 0006h)
EEPROM configuration bit description .......... 131
Tab. 134. TXLDO_VDDPA_LOW (address 0007h)
EEPROM configuration bit description .......... 132
Tab. 135. TXLDO_VDDPA_MAX_RDR (address
0008h) EEPROM configuration bit
description ..................................................... 133
Tab. 136. TXLDO_VDDPA_MAX_CARD (address
0009h) EEPROM configuration bit
description ..................................................... 134
Tab. 137. BOOST_DEFAULT_VOLTAGE (address
000Ah) EEPROM configuration bit
description ..................................................... 135
PN5190B1
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Product data sheet
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NXP Semiconductors
PN5190
NFC frontend
Tab. 138. XTAL_CONFIG (address 0010h) EEPROM
configuration bit description ...........................135
Tab. 139. XTAL_TIMEOUT (address 0011h)
EEPROM configuration bit description .......... 136
Tab. 140. CLK_INPUT_FREQ (address 0012h)
EEPROM configuration bit description .......... 136
Tab. 141. XTAL_CHECK_DELAY (address 0013h)
EEPROM configuration bit description .......... 136
Tab. 142. TEMP_WARNING (address 0014h)
EEPROM configuration bit description .......... 137
Tab. 143. ENABLE_GPIO0_ON_OVERTEMP
(address 0016h) EEPROM configuration bit
Tab. 164. RESIDUAL_AMPL_LEVEL_B212 (address
0036h) EEPROM configuration bit
description ..................................................... 146
Tab. 165. EDGE_TYPE_B212 (address 0037h)
EEPROM configuration bit description .......... 146
Tab. 166. EDGE_STYLE_B212 (address 0038h)
EEPROM configuration bit description .......... 146
Tab. 167. EDGE_LENGTH_B212 (address 0039h)
EEPROM configuration bit description .......... 147
Tab. 168. RESIDUAL_AMPL_LEVEL_B424 (address
003Ah) EEPROM configuration bit
description ..................................................... 147
Tab. 169. EDGE_TYPE_B424 (address 003Bh)
EEPROM configuration bit description .......... 148
Tab. 170. EDGE_STYLE_B424 (address 003Ch)
EEPROM configuration bit description .......... 148
Tab. 171. EDGE_LENGTH_B424 (address 003Dh)
EEPROM configuration bit description .......... 149
Tab. 172. RESIDUAL_AMPL_LEVEL_B848 (address
003Eh) EEPROM configuration bit
description ..................................................... 149
Tab. 173. EDGE_TYPE_B848 (address 003Fh)
EEPROM configuration bit description .......... 149
Tab. 174. EDGE_STYLE_B848 (address 0040h)
EEPROM configuration bit description .......... 150
Tab. 175. EDGE_LENGTH_B848 (address 0041h)
EEPROM configuration bit description .......... 150
Tab. 176. RESIDUAL_AMPL_LEVEL_F212 (address
0042h) EEPROM configuration bit
description ..................................................... 151
Tab. 177. EDGE_TYPE_F212 (address 0043h)
EEPROM configuration bit description .......... 151
Tab. 178. EDGE_STYLE_F212 (address 0044h)
EEPROM configuration bit description .......... 151
Tab. 179. EDGE_LENGTH_F212 (address 0045h)
EEPROM configuration bit description .......... 152
Tab. 180. RESIDUAL_AMPL_LEVEL_F424 (address
0046h) EEPROM configuration bit
description ..................................................... 152
Tab. 181. EDGE_TYPE_F424 (address 0047h)
EEPROM configuration bit description .......... 153
Tab. 182. EDGE_STYLE_F424 (address 0048h)
EEPROM configuration bit description .......... 153
Tab. 183. EDGE_LENGTH_F424 (address 0049h)
EEPROM configuration bit description .......... 154
Tab. 184. RESIDUAL_AMPL_LEVEL_V100_26
(address 004Ah) EEPROM configuration
bit description ................................................154
Tab. 185. EDGE_TYPE_V100_26 (address 004Bh)
EEPROM configuration bit description .......... 154
Tab. 186. EDGE_STYLE_V100_26 (address 004Ch)
EEPROM configuration bit description .......... 155
Tab. 187. EDGE_LENGTH_V100_26 (address
004Dh) EEPROM configuration bit
description ..................................................... 137
Tab. 144. RESIDUAL_AMPL_LEVEL_A106 (address
0022h) EEPROM configuration bit
description ..................................................... 137
Tab. 145. EDGE_TYPE_A106 (address 0023h)
EEPROM configuration bit description .......... 138
Tab. 146. EDGE_STYLE_A106 (address 0024h)
EEPROM configuration bit description .......... 138
Tab. 147. EDGE_LENGTH_A106 (address 0025h)
EEPROM configuration bit description .......... 139
Tab. 148. RESIDUAL_AMPL_LEVEL_A212 (address
0026h) EEPROM configuration bit
description ..................................................... 139
Tab. 149. EDGE_TYPE_A212 (address 0027h)
EEPROM configuration bit description .......... 139
Tab. 150. EDGE_STYLE_A212 (address 0028h)
EEPROM configuration bit description .......... 140
Tab. 151. EDGE_LENGTH_A212 (address 0029h)
EEPROM configuration bit description .......... 140
Tab. 152. RESIDUAL_AMPL_LEVEL_A424 (address
002Ah) EEPROM configuration bit
description ..................................................... 141
Tab. 153. EDGE_TYPE_A424 (address 002Bh)
EEPROM configuration bit description .......... 141
Tab. 154. EDGE_STYLE_A424 (address 002Ch)
EEPROM configuration bit description .......... 141
Tab. 155. EDGE_LENGTH_A424 (address 002Ch)
EEPROM configuration bit description .......... 142
Tab. 156. RESIDUAL_AMPL_LEVEL_A848 (address
002Eh) EEPROM configuration bit
description ..................................................... 142
Tab. 157. EDGE_TYPE_A848 (address 002Fh)
EEPROM configuration bit description .......... 143
Tab. 158. EDGE_STYLE_A848 (address 0030h)
EEPROM configuration bit description .......... 143
Tab. 159. EDGE_LENGTH_A848 (address 0031h)
EEPROM configuration bit description .......... 144
Tab. 160. RESIDUAL_AMPL_LEVEL_B106 (address
0032h) EEPROM configuration bit
description ..................................................... 144
Tab. 161. EDGE_TYPE_B106 (address 0033h)
EEPROM configuration bit description .......... 144
Tab. 162. EDGE_STYLE_B106 (address 0034h)
EEPROM configuration bit description .......... 145
Tab. 163. EDGE_LENGTH_B106 (address 0035h)
EEPROM configuration bit description .......... 145
description ..................................................... 155
Tab. 188. RESIDUAL_AMPL_LEVEL_V100_53
(address 004Eh) EEPROM configuration
bit description ................................................156
PN5190B1
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Product data sheet
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NXP Semiconductors
PN5190
NFC frontend
Tab. 189. EDGE_TYPE_V100_53 (address 004Fh)
EEPROM configuration bit description .......... 156
Tab. 190. EDGE_STYLE_A106 (address 0050h)
EEPROM configuration bit description .......... 156
Tab. 191. EDGE_LENGTH_V100_53 (address
0051h) EEPROM configuration bit
Tab. 213. EDGE_TYPE_V10_212 (address 0067h)
EEPROM configuration bit description .......... 166
Tab. 214. EDGE_STYLE_V10_212 (address 0068h)
EEPROM configuration bit description .......... 166
Tab. 215. EDGE_LENGTH_V100_212 (address
0069h) EEPROM configuration bit
description ..................................................... 157
Tab. 192. RESIDUAL_AMPL_LEVEL_V100_106
(address 0052h) EEPROM configuration bit
description ..................................................... 167
Tab. 216. RESIDUAL_AMPL_LEVEL_180003m3_
tari18p88 (address 006Ah) EEPROM
description ..................................................... 157
Tab. 193. EDGE_TYPE_V100_106 (address 0053h)
EEPROM configuration bit description .......... 158
Tab. 194. EDGE_STYLE_V100_106 (address 0054h)
EEPROM configuration bit description .......... 158
Tab. 195. EDGE_LENGTH_V100_106 (address
0055h) EEPROM configuration bit
description ..................................................... 159
Tab. 196. RESIDUAL_AMPL_LEVEL_100_212
(address 0056h) EEPROM configuration bit
description ..................................................... 159
Tab. 197. EDGE_TYPE_V100_212 (address 0057h)
EEPROM configuration bit description .......... 159
Tab. 198. EDGE_STYLE_V100_212 (address 0058h)
EEPROM configuration bit description .......... 160
Tab. 199. EDGE_LENGTH_V100_212 (address
0059h) EEPROM configuration bit
description ..................................................... 160
Tab. 200. RESIDUAL_AMPL_LEVEL_V10_26
(address 005Ah) EEPROM configuration
bit description ................................................161
Tab. 201. EDGE_TYPE_V10_26 (address 005Bh)
EEPROM configuration bit description .......... 161
Tab. 202. EDGE_STYLE_V10_26 (address 005Ch)
EEPROM configuration bit description .......... 161
Tab. 203. EDGE_LENGTH_V10_26 (address 005Dh)
EEPROM configuration bit description .......... 162
Tab. 204. RESIDUAL_AMPL_LEVEL_V10_53
(address 005Eh) EEPROM configuration
bit description ................................................162
Tab. 205. EDGE_TYPE_V10_53 (address 005Fh)
EEPROM configuration bit description .......... 163
Tab. 206. EDGE_STYLE_V10_53 (address 0060h)
EEPROM configuration bit description .......... 163
Tab. 207. EDGE_LENGTH_V10_53 (address 0061h)
EEPROM configuration bit description .......... 164
Tab. 208. RESIDUAL_AMPL_LEVEL_V10_106
(address 0062h) EEPROM configuration bit
description ..................................................... 164
Tab. 209. EDGE_TYPE_V10_106 (address 0063h)
EEPROM configuration bit description .......... 164
Tab. 210. EDGE_STYLE_V100_212 (address 0064h)
EEPROM configuration bit description .......... 165
Tab. 211. EDGE_LENGTH_V10_106 (address
0065h) EEPROM configuration bit
description ..................................................... 165
Tab. 212. RESIDUAL_AMPL_LEVEL_V10_212
(address 0066h) EEPROM configuration bit
configuration bit description ...........................167
Tab. 217. EDGE_TYPE_180003m3_tari18p88
(address 006Bh) EEPROM configuration
bit description ................................................168
Tab. 218. EDGE_STYLE_180003m3_tari18p88
(address 006Ch) EEPROM configuration
bit description ................................................168
Tab. 219. EDGE_LENGTH_180003m3_tari18p88
(address 006Dh) EEPROM configuration
bit description ................................................169
Tab. 220. RESIDUAL_AMPL_LEVEL_180003m3_
tari9p44 (address 006Eh) EEPROM
configuration bit description ...........................169
Tab. 221. EDGE_TYPE_180003m3_tari9p44
(address 006Fh) EEPROM configuration bit
description ..................................................... 169
Tab. 222. EDGE_STYLE_180003m3_tari9p44
(address 0070h) EEPROM configuration bit
description ..................................................... 170
Tab. 223. EDGE_LENGTH_180003m3_tari9p44
(address 0071h) EEPROM configuration bit
description ..................................................... 170
Tab. 224. RESIDUAL_AMPL_LEVEL_180003m3_
tari18p88 (address 0072h) EEPROM
configuration bit description ...........................171
Tab. 225. EDGE_TYPE_B_PRIME_106 (address
0073h) EEPROM configuration bit
description ..................................................... 171
Tab. 226. EDGE_STYLE_B_PRIME_106 (address
0074h) EEPROM configuration bit
description ..................................................... 171
Tab. 227. EDGE_LENGTH_B_PRIME_106 (address
0075h) EEPROM configuration bit
description ..................................................... 172
Tab. 228. DPC_CONFIG (address 0076h) EEPROM
configuration bit description ...........................172
Tab. 229. DPC_TARGET_CURRENT (address 077h)
EEPROM configuration bit description .......... 173
Tab. 230. DPC_HYSTERESIS_LOADING (address
079h) EEPROM configuration bit
description ..................................................... 173
Tab. 231. DPC_HYSTERESIS_UNLOADING
(address 07Ch) EEPROM configuration bit
description ..................................................... 173
Tab. 232. DPC_TXLDOVDDPALow (address 007Dh)
EEPROM configuration register bit
description ..................................................... 174
Tab. 233. DPC_TXGSN (address 007Eh) EEPROM
configuration register bit description ..............174
description ..................................................... 166
PN5190B1
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Product data sheet
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Rev. 3.0 — 21 April 2021
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NXP Semiconductors
PN5190
NFC frontend
Tab. 234. DPC_RDON_Control (address 007Fh)
EEPROM configuration register bit
description ..................................................... 174
Tab. 235. DPC_InitialRDOn_RFOn (address 0080h)
EEPROM configuration register bit
description ..................................................... 174
Tab. 236. DPC_GUARD_TIME (address 087h)
EEPROM configuration bit description .......... 174
Tab. 237. DPC_ENABLE_DURING_FDT (address
088h) EEPROM configuration bit
description ..................................................... 175
Tab. 238. DPC_GUARD_TIME_AFTER_RX (address
089h) EEPROM configuration bit
Tab. 260. ARC_RM_180003m3_SC848_2Man
(address 01F2h) EEPROM configuration bit
description ..................................................... 205
Tab. 261. ARC_RM_AI106 (address 01FCh)
EEPROM configuration bit description .......... 206
Tab. 262. ARC_RM_AI212 (0206h) EEPROM
configuration bit description ...........................208
Tab. 263. ARC_RM_AI424 (0210h) EEPROM
configuration bit description ...........................209
Tab. 264. RF_DEBOUNCE_TIMEOUT (address
02B2h) EEPROM configuration bit
description ..................................................... 210
Tab. 265. SENSE_RES (address 02B3) EEPROM
configuration bit description ...........................211
Tab. 266. SIGNAL_SCALING_CONFIG (address
2B5h) EEPROM configuration bit
description ..................................................... 211
Tab. 267. SEL_RES (address 2B8h) EEPROM
configuration bit description ...........................211
Tab. 268. FELICA_POLL_RES (address 02B9)
EEPROM configuration bit description .......... 211
Tab. 269. RANDOM_UID_ENABLE (address 2CBh)
EEPROM configuration bit description .......... 212
Tab. 270. MFC_AUTH_TIMEOUT (address 2CCh)
EEPROM configuration bit description .......... 212
Tab. 271. RSSI_TIMER (address 2DAh) EEPROM
configuration bit description ...........................212
Tab. 272. RSSI_TIMER_FIRST_PERIOD (address
2DCh) EEPROM configuration bit
description ..................................................... 212
Tab. 273. RSSI_CTRL_00_AB (address 2DEh)
EEPROM configuration bit description .......... 212
Tab. 274. RSSI_NB_ENTRIES_AB (address 2DFh)
EEPROM configuration bit description .......... 213
Tab. 275. RSSI_THRESHOLD_PHASE_TABLE
(address 2E0h) EEPROM configuration bit
description ..................................................... 175
Tab. 239. DPC_LOOKUP_TABLE (008Bh-0133h)
EEPROM configuration bit description .......... 175
Tab. 240. ARC_CONFIG (address 0137h) EEPROM
configuration bit description ...........................176
Tab. 241. ARC_VDDPA (0139Eh) EEPROM
configuration bit description ...........................176
Tab. 242. ARC_RM_A106 (address 013Eh)
EEPROM configuration bit description .......... 178
Tab. 243. ARC_RM_A212 (address 0148h) EEPROM
configuration bit description ...........................179
Tab. 244. ARC_RM_A424 (address 0152h) EEPROM
configuration bit description ...........................181
Tab. 245. ARC_RM_A848 (address 015Ch)
EEPROM configuration bit description .......... 182
Tab. 246. ARC_RM_B106 (address 0166h) EEPROM
configuration bit description ...........................184
Tab. 247. ARC_RM_B212 (address 0170h) EEPROM
configuration bit description ...........................185
Tab. 248. ARC_RM_B424 (address 017Ah)
EEPROM configuration bit description .......... 187
Tab. 249. ARC_RM_B848 (address 0184h) EEPROM
configuration bit description ...........................188
Tab. 250. ARC_RM_F212 (address 018Eh)
EEPROM configuration bit description .......... 190
Tab. 251. ARC_RM_F424 (address 0198h) EEPROM
configuration bit description ...........................191
Tab. 252. ARC_RM_V_6p6 (address 01A2h)
EEPROM configuration bit description .......... 193
Tab. 253. ARC_RM_V_26 (address 01ACh)
EEPROM configuration bit description .......... 194
Tab. 254. ARC_RM_V53(address 01B6h) EEPROM
configuration bit description ...........................196
Tab. 255. ARC_RM_V106(address 01C0h) EEPROM
configuration bit description ...........................197
Tab. 256. ARC_RM_V212(address 01CAh) EEPROM
configuration bit description ...........................199
Tab. 257. ARC_RM_180003m3_SC424_4Man
(address 01D4h) EEPROM configuration
description ..................................................... 213
Tab. 276. TX_PARAM_ENTRY_TABLE (address
3A2h) EEPROM configuration bit
description ..................................................... 214
Tab. 277. LPCD_AVG_SAMPLES (address 0492h)
EEPROM configuration bit description .......... 218
Tab. 278. LPCD_RSSI_TARGET (address 0494h)
EEPROM configuration bit description .......... 218
Tab. 279. LPCD_RSSI_HYST (address 0496h)
EEPROM configuration bit description .......... 218
Tab. 280. LPCD_CONFIG (address 0497h) EEPROM
configuration register bit description ..............218
Tab. 281. LPCD_THRESHOLD_COARSE (address
049Ah) EEPROM configuration bit
description ..................................................... 219
Tab. 282. LPCD_VDDPA (address 04B5h) EEPROM
configuration bit description ...........................220
Tab. 283. ULPCD_VDDPA_CTRL (address 4BFh)
EEPROM configuration bit description .......... 221
Tab. 284. ULPCD_TIMING_CTRL (address 4C2h)
EEPROM configuration bit description .......... 222
Tab. 285. ULPCD_VOLTAGE_CTRL (address 4C6h)
EEPROM configuration bit description .......... 222
bit description ................................................200
Tab. 258. ARC_RM_180003m3_SC424_2Man
(address 01DEh) EEPROM configuration
bit description ................................................202
Tab. 259. ARC_RM_180003m3_SC848_4Man
(address 01E8h) EEPROM configuration
bit description ................................................203
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NFC frontend
Tab. 286. ULPCD_RSSI_GUARD_TIME (address
4C9h) EEPROM configuration bit
Tab. 307. Tx_Symbol23_Mod_Reg_BR_106
(0CCDEh) EEPROM configuration bit
description ..................................................... 222
Tab. 287. ULPCD_RSSI_SAMPLE_CFG (address
4CAh) EEPROM configuration bit
description ..................................................... 230
Tab. 308. Tx_Data_Mod_Reg_BR_106 (0CD1Eh)
EEPROM configuration bit description .......... 230
description ..................................................... 222
Tab. 288. ULPCD_THRESH_LVL (address 4CBh)
EEPROM configuration bit description .......... 223
Tab. 289. ULPCD_GPIO3 (address 4CCh) EEPROM
configuration bit description ...........................223
Tab. 290. FELICA_POLL_RES (address 0559)
EEPROM configuration bit description .......... 223
Tab. 291. FDT_default_val (address 055D) EEPROM
configuration bit description ...........................223
Tab. 292. RXIRQ_GuardTime (address 0561h)
EEPROM configuration bit description .......... 223
Tab. 293. NFCLD_RFLD_Valid (address 06D3h)
EEPROM configuration register bit
description ..................................................... 224
Tab. 294. CurrentSensorTrimConfig (address
0CACh) EEPROM configuration bit
description ..................................................... 224
Tab. 295. CORRECTION_ENTRY_TABLE (address
0BDAh) EEPROM configuration bit
Tab. 309. Tx_Symbol23_Mod_Reg_BR_212
(0CD5Eh) EEPROM configuration bit
description ..................................................... 230
Tab. 310. Tx_Data_Mod_Reg_BR_212 (0CD9Eh)
EEPROM configuration bit description .......... 230
Tab. 311. Limiting values .............................................. 231
Tab. 312. Operating conditions ..................................... 232
Tab. 313. Thermal characteristics HVQFN40 package . 232
Tab. 314. Thermal characteristics VFBGA64 package ..232
Tab. 315. Junction Temperature ....................................232
Tab. 316. Thermal Shutdown Temperature ................... 233
Tab. 317. Supply voltage ...............................................233
Tab. 318. Current consumption in active mode .............233
Tab. 319. Current consumption during power-saving
modes ............................................................234
Tab. 320. Overcurrent detection function ...................... 234
Tab. 321. VEN pin .........................................................235
Tab. 322. GPIO (GPIO_0, GPIO_1, GPIO_2, GPIO_
3, GPIO4, GPIO5) pins ................................. 235
description ..................................................... 224
Tab. 296. RTRANS_FTRANS_TABLE (address
C03h) EEPROM configuration bit
Tab. 323. CLK1, CLK2 pins .......................................... 235
Tab. 324. IRQ pin ..........................................................236
Tab. 325. SCLK, MOSI, NSS pins ................................ 236
Tab. 326. MISO pin ....................................................... 236
Tab. 327. RXp, RXn pins .............................................. 237
Tab. 328. TX1, TX2 pins ............................................... 237
Tab. 329. AUX1, AUX2, AUX3 pins (Debug output) ......237
Tab. 330. DAC_1, DAC_2 output pins (Tuning DAC) .... 237
Tab. 331. Power supply connection timing ....................238
Tab. 332. Pulse length .................................................. 239
Tab. 333. DAC1, DAC2 conversion timing (Tuning
DAC) ..............................................................239
Tab. 334. SPI interface ..................................................239
Tab. 335. RF_ON command timing following a
previous RF_OFF ..........................................240
Tab. 336. Crystal requirements for ISO/IEC14443
compliant operation .......................................240
description ..................................................... 226
Tab. 297. CFG_NOV_CAL (address 0083h)
EEPROM configuration bit description .......... 227
Tab. 298. NOV_CAL_VAL1 (address 0C84h)
EEPROM configuration bit description .......... 227
Tab. 299. NOV_CAL_VAL2 (0C85h) EEPROM
configuration bit description ...........................227
Tab. 300. NOV_CAL_THRESHOLD (address 0C86h)
EEPROM configuration bit description .......... 228
Tab. 301. NOV_CAL_OFFSET1 (address 0C87h)
EEPROM configuration bit description .......... 228
Tab. 302. NOV_CAL_OFFSET1 (address 0C8Bh)
EEPROM configuration bit description .......... 228
Tab. 303. VDDPA_DISCHARGE (address 0C8Fh)
EEPROM configuration bit description .......... 228
Tab. 304. ARC_RM_A106_FDT (address 0C9Dh)
EEPROM configuration bit description .......... 229
Tab. 305. Tx_Symbol23_Mod_Reg_BR_53
(0CC5Eh) EEPROM configuration bit
Tab. 337. Frequency requirements for a direct clock
input (no crystal) ........................................... 240
Tab. 338. EEPROM characteristics ...............................241
Tab. 339. Package outline VFBGA64 (SOT1307-2) ......242
Tab. 340. Abbreviations .................................................293
Tab. 341. Revision history .............................................295
description ..................................................... 230
Tab. 306. Tx_Data_Mod_Reg_BR_53 (0CC9Eh)
EEPROM configuration bit description .......... 230
PN5190B1
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NFC frontend
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Block diagram ................................................... 8
Pin configuration for VFBGA64 .........................9
Pin configuration for HVQFN40
(SOT2062-1) ....................................................13
Endianness examples ..................................... 18
Blocking capacitors ......................................... 21
Transmitter supply ...........................................22
Direct transmitter supply ................................. 23
Transmitter supply by DC-DC ......................... 23
DC-DC active .................................................. 24
Fig. 24. LPCD configuration and card detection
loop ..................................................................41
Fig. 25. LPCD configuration ......................................... 42
Fig. 26. Autocall state machine ....................................45
Fig. 27. Antenna connection using variable
capacitors ........................................................ 47
Fig. 28. Receiver block diagram ...................................47
Fig. 29. Startup timing ................................................238
Fig. 30. Package outline VFBGA64 (SOT1307-2) ......242
Fig. 31. Package outline note VFBGA64
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10. DC-DC bypassed (in DCDC_PWR_
CONFIG) ......................................................... 24
(SOT1307-2) ..................................................243
Fig. 32. Package outline HVQFN40, SOT2062-1 .......244
Fig. 33. Package outline detail HVQFN40,
Fig. 11.
No DC-DC used ..............................................25
Fig. 12. No DC-DC used ..............................................25
Fig. 13. No DC-DC used - no VDDPALDO .................. 26
Fig. 14. Clocking by crystal ..........................................27
Fig. 15. System overview: DPC, AWC and ARC ..........30
Fig. 16. System overview: DPC, AWC and ARC ..........31
Fig. 17. System overview: DPC, AWC and ARC ..........31
Fig. 18. System overview: DPC, AWC and ARC ..........32
Fig. 19. Waveshaping transitions (example falling
edge) ............................................................... 34
Fig. 20. One linear transition (example falling edge) .... 35
Fig. 21. Two linear transitions (example falling
edge) ............................................................... 36
Fig. 22. Three linear transitions (example falling
SOT2062-1 ....................................................245
Fig. 34. Marking VFBGA64 Package ......................... 246
Fig. 35. Marking HVQFN40 package SOT2062-1 ...... 246
Fig. 36. Reflow soldering footprint part1 for
VFBGA64 (SOT1307-2) ................................ 247
Fig. 37. Reflow soldering footprint part2 for
VFBGA64 (SOT1307-2) ................................ 248
Fig. 38. Reflow soldering footprint part3 for
VFBGA64 (SOT1307-2) ................................ 249
Fig. 39. Soldering and footprint representative
illustration for VFBGA64 (SOT1307-2) .......... 250
Fig. 40. Package outline HVQFN40, SOT2062-1 .......251
Fig. 41. Package outline HVQFN40, SOT2062-1 .......252
Fig. 42. Package outline HVQFN40, SOT2062-1 .......253
Fig. 43. Package outline HVQFN40, SOT2062-1 .......254
edge) ............................................................... 36
Fig. 23. Timer overview ................................................40
PN5190B1
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PN5190
NFC frontend
Contents
1
2
2.1
General description ............................................ 1
9.14
Low-power card detection ............................... 40
Low-power card detection (LPCD) ...................41
Semi-autonomous mode (LPCD) .....................43
Automatic EMD error handling ........................ 44
Autocoll (card emulation) .................................44
RF-level detection ............................................46
Antenna tuning with variable capacitors .......... 46
RF debug signals ............................................ 47
Secure firmware update .................................. 49
SPI host interface ............................................50
Host interface commands ................................51
Logical command layer ....................................51
Features and benefits .........................................2
RF functionality ..................................................2
ISO/IEC14443-A ................................................ 2
ISO/IEC14443-B ................................................ 2
FeliCa .................................................................2
Tag type reading ................................................2
MIFARE card reading ........................................ 2
ISO/IEC 15693 .................................................. 2
Peer to peer ...................................................... 2
Host interface .................................................... 3
Applications .........................................................4
Firmware versions .............................................. 5
Quick reference data .......................................... 6
Ordering information .......................................... 7
Block diagram with VFBGA64 connections ......8
Pinning information ............................................ 9
Pin description VFBGA64 ..................................9
Pin description HVQFN40 ............................... 13
Functional description ......................................15
Functional overview .........................................15
Endianness ...................................................... 17
Initial calibration ...............................................18
System power states ....................................... 19
Power supply ...................................................20
System power supply overview ....................... 20
Connecting blocking capacitors .......................21
Transmitter power supply ................................ 21
VDDPALDO transmitter supply ........................22
Direct transmitter supply ..................................22
DC-DC (boost) supply ..................................... 23
Configuration example 1: VDDPALDO
9.14.1
9.14.2
9.15
9.16
9.17
9.18
9.19
9.20
9.21
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.2
3
4
5
6
7
8
8.1
8.2
9
9.1
9.2
9.3
9.22
9.22.1
9.22.1.1 Logical frame definition ....................................51
9.22.1.2 Logical flow definition ...................................... 51
9.22.1.3 Logical message type definition ...................... 51
9.22.1.4 Logical message format .................................. 52
9.22.1.5 Split frame definition ........................................52
9.22.2
9.22.3
9.22.4
Host interface command list ............................ 52
Command WRITE_REGISTER (00h) ..............54
Command WRITE_REGISTER_OR_MASK
(01h) .................................................................54
Command WRITE_REGISTER_AND_
MASK (02h) .....................................................55
Command WRITE_REGISTER_MULTIPLE
(03h) .................................................................55
Command READ_REGISTER (04h) ................56
Command READ_REGISTER_MULTIPLE
9.22.5
9.22.6
9.4
9.5
9.5.1
9.5.2
9.5.3
9.5.3.1
9.5.3.2
9.5.3.3
9.5.3.4
9.22.7
9.22.8
(05h) .................................................................57
Command WRITE_EEPROM (06h) .................58
9.22.9
9.22.10 Command READ_EEPROM (07h) .................. 59
9.22.11 Command TRANSMIT_RF_DATA (08h) ..........59
9.22.12 Command RETRIEVE_RF_DATA (09h) .......... 60
9.22.13 Command EXCHANGE_RF_DATA (0Ah) ........60
9.22.14 Command MFC_AUTHENTICATE (0Bh) .........62
9.22.15 Command EPC_GEN2_INVENTORY (0Ch) ....63
9.22.16 Command LOAD_RF_CONFIGURATION
(0Dh) ................................................................65
9.22.16.1 Parameter for command LOAD_RF_
transmitter supply - DC-DC active ................... 23
Configuration example 2: VDDPALDO
transmitter supply - DC-DC bypassed ............. 24
Configuration example 3: VDDPALDO
transmitter supply connected to VBAT - no
DC-DC ............................................................. 24
Configuration example 4: VDDPALDO
9.5.3.5
9.5.3.6
9.5.3.7
CONFIGURATION ........................................... 66
9.22.17 Command UPDATE_RF_
supplied independent from VBAT - no DC-
DC ....................................................................25
Configuration example 5: VDDPALDO not
used - no DC-DC ............................................ 25
Supply voltage range for transmitter supply
configuration examples ....................................27
Clock generation ..............................................27
External interfaces ...........................................27
Transmitter overcurrent and temperature
CONFIGURATION (0Eh) ................................. 68
9.22.18 Command GET_ RF_CONFIGURATION
(0Fh) ................................................................ 69
9.22.19 Command RF_ON (10h) ................................. 70
9.22.20 Command RF_OFF (11h) ................................70
9.22.21 Command CONFIGURE_ TESTBUS_
9.5.3.8
9.5.3.9
9.6
9.7
9.8
DIGITAL (12h) ..................................................71
9.22.22 Command CONFIGURE_TESTBUS_
protection ......................................................... 28
Loading a dedicated RF configuration ............. 28
Dynamic power control (DPC) .........................28
DPC algorithm ................................................. 32
DPC characteristics ......................................... 33
Adaptive waveshape control (AWC) ................ 34
Adaptive receiver control (ARC) ...................... 36
Timer ................................................................39
ANALOG (13h) ................................................ 72
9.22.23 Command CTS_ENABLE (14h) ...................... 72
9.22.24 Command CTS_CONFIGURE (15h) ............... 73
9.22.25 Command CTS_RETRIEVE_LOG (16h) ......... 77
9.22.26 Command RECEIVE_RF_DATA (1Ah) ............77
9.22.27 Command SWITCH_MODE_NORMAL
(20h) .................................................................78
9.9
9.10
9.10.1
9.10.2
9.11
9.12
9.13
PN5190B1
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NFC frontend
9.22.28 Command SWITCH_MODE_AUTOCOLL
(21h) .................................................................79
9.22.29 Command SWITCH_MODE_STANDBY
9.23.46 CALIBRATE_STATUS (00053h) .................... 115
9.23.47 TXLDO_VDDPA_CONFIG (00054h) ..............115
9.23.48 GENERAL_ERROR_STATUS (0055h) ..........116
9.23.49 TXLDO_VOUT_CURR (0056h) ..................... 116
9.23.50 CLIF_DAC (00057h) ......................................117
9.23.51 PMU_ANA_SMPS_CTRL_REG (00058h) .....118
9.23.52 RXM_FREQ (00059h) ................................... 118
9.23.53 RXM_RSSI (0005Ah) .....................................118
9.23.54 TEMP_SENSOR (005Bh) ..............................119
9.23.55 TX_NOV_CALIBRATE (005Dh) .....................119
9.23.56 SS_TX1_RTRTRANS0 (00080h) ...................119
9.23.57 SS_TX1_RTRTRANS1 (00081h) ...................119
9.23.58 SS_TX1_RTRTRANS2 (00082h) ...................120
9.23.59 SS_TX1_RTRTRANS3 (00083h) ...................120
9.23.60 SS_TX2_RTRTRANS0 (00084h) ...................120
9.23.61 SS_TX2_RTRTRANS1 (00085h) ...................120
9.23.62 SS_TX2_RTRTRANS2 (00086h) ...................121
9.23.63 SS_TX2_RTRTRANS3 (00087h) ...................121
9.23.64 SS_TX1_FTRTRANS0 (00088h) ................... 121
9.23.65 SS_TX1_FTRTRANS1 (00089h) ................... 121
9.23.66 SS_TX1_FTRTRANS2 (0008Ah) ...................121
9.23.67 SS_TX1_FTRTRANS3 (0008Bh) ...................122
9.23.68 SS_TX2_FTRTRANS0 (0008Ch) ...................122
9.23.69 SS_TX2_FTRTRANS1 (0008Dh) ...................122
9.23.70 SS_TX2_FTRTRANS2 (0008Eh) ...................122
9.23.71 SS_TX2_FTRTRANS3 (0008Fh) ...................123
(22h) .................................................................81
9.22.30 Command SWITCH_MODE_LPCD (23h) ........81
9.22.31 Command SWITCH_MODE_DOWNLOAD
(25h) .................................................................82
9.22.32 Command GET_DIE_ID (26h) .........................83
9.22.33 Command GET_VERSION (27h) .................... 83
9.22.34 Command PRBS_TEST (41h) .........................84
9.22.35 RESPONSE STATUS CODES ........................ 85
9.22.36 EVENTS INDICATED BY INTERRUPT ........... 87
9.22.37 EVENTS INDICATED ON GPIO ......................88
9.23
Register description .........................................88
Register overview ............................................ 88
SYSTEM_CONFIG (0000h) .............................91
EVENT_ENABLE (0001h) ............................... 91
EVENT_STATUS (0002h) ................................92
EMVCO_EMD_CONTROL (0003h) .................92
FELICA_EMD_CONTROL (0004h) ................. 93
RX_STATUS (0005h) .......................................94
RX_STATUS_ERROR (0006h) ........................95
CLIF_STATUS (0007h) ....................................97
9.23.1
9.23.2
9.23.3
9.23.4
9.23.5
9.23.6
9.23.7
9.23.8
9.23.9
9.23.10 RF_EXCHANGE_CONTROL (0008h) ............. 98
9.23.11 TX_SYMBOL01_MOD (0009h) ........................99
9.23.12 TX_SYMBOL1_DEF (000Ah) .......................... 99
9.23.13 TX_SYMBOL0_DEF (000Bh) ........................ 100
9.23.14 TX_SYMBOL23_MOD (000Ch) .....................100
9.23.15 TX_SYMBOL23_DEF (000Dh) ...................... 100
9.23.16 TX_SYMBOL_CONFIG (000Eh) ....................100
9.23.17 TX_FRAME_CONFIG (000Fh) ...................... 101
9.23.18 TX_DATA_MOD (0010h) ............................... 102
9.23.19 TX_WAIT (0011h) .......................................... 103
9.23.20 TX_CRC_CONFIG (0012h) ........................... 104
9.23.21 SS_TX_CONFIG (00015h) ............................ 104
9.23.22 SS_TX1_RMCFG (00016h) ...........................105
9.23.23 SS_TX2_RMCFG (00017h) ...........................105
9.23.24 SS_TX_TRANS_CFG (00019h) .................... 106
9.23.25 SIGPRO_RM_PATTERN (0020h) ..................106
9.23.26 SIGPRO_RM_TECH (0022h) ........................ 106
9.23.27 RX_FRAME_LENGTH (0026h) ..................... 107
9.23.28 RX_ERROR_CONFIG (0027h) ......................107
9.23.29 RX_CTRL_STATUS (0028h) ......................... 107
9.23.30 SIGPRO_IIR_CONFIG0 (0002Ah) .................108
9.23.31 DGRM_RSSI (0030h) ....................................108
9.23.32 RX_CRC_CONFIG (0031h) ...........................108
9.23.33 RX_WAIT (0032h) ......................................... 109
9.23.34 RXM_CTRL (0035h) ......................................110
9.23.35 SS_TX1_CMCFG (0003Bh) ...........................110
9.23.36 SS_TX2_CMCFG (0003Ch) .......................... 110
9.23.37 TIMER0_CONFIG (003Dh) ............................110
9.23.38 TIMER0_RELOAD (003Eh) ........................... 111
9.23.39 TIMER1_CONFIG (003Fh) ............................ 111
9.23.40 TIMER1_RELOAD (0040h) ............................113
9.23.41 EMD_1_CFG (0047h) ....................................113
9.23.42 EMD_0_CONFIG (0048h) ............................. 113
9.23.43 LPCD_CALIBRATE_CTRL (00050h) .............114
9.23.44 IQ_CHANNEL_VALS (00051h) ......................114
9.23.45 PAD_CONFIG (0052h) .................................. 114
9.24
EEPROM configuration description ............... 123
EEPROM configuration overview ...................123
DCDC_PWR_CONFIG (0000h) .....................129
DCDC_CONFIG (0001h) ............................... 129
TXLDO_CONFIG (0002h) ..............................130
TXLDO_VDDPA_HIGH (0006h) .................... 131
TXLDO_VDDPA_LOW (0007h) ..................... 132
TXLDO_VDDPA_MAX_RDR (0008h) ............133
TXLDO_VDDPA_MAX_CARD (0009h) ..........134
BOOST_DEFAULT_VOLTAGE (000Ah) ........ 135
9.24.1
9.24.2
9.24.3
9.24.4
9.24.5
9.24.6
9.24.7
9.24.8
9.24.9
9.24.10 XTAL_CONFIG (0010h) .................................135
9.24.11 XTAL_TIMEOUT (0011h) ...............................136
9.24.12 CLK_INPUT_FREQ (0012h) ..........................136
9.24.13 XTAL_CHECK_DELAY (0013h) .....................136
9.24.14 TEMP_WARNING (0014h) ............................ 137
9.24.15 ENABLE_GPIO0_ON_OVERTEMP
(0016h) ...........................................................137
9.24.16 RESIDUAL_AMPL_LEVEL_A106 (0022h) .... 137
9.24.17 EDGE_TYPE_A106 (0023h) ..........................138
9.24.18 EDGE_STYLE_A106 (0024h) ........................138
9.24.19 EDGE_LENGTH_A106 (0025h) .................... 139
9.24.20 RESIDUAL_AMPL_LEVEL_A212 (0026h) .... 139
9.24.21 EDGE_TYPE_A212 (0027h) ..........................139
9.24.22 EDGE_STYLE_A212 (0028h) ........................140
9.24.23 EDGE_LENGTH_A212 (0029h) .................... 140
9.24.24 RESIDUAL_AMPL_LEVEL_A424 (002Ah) ....141
9.24.25 EDGE_TYPE_A424 (002Bh) ......................... 141
9.24.26 EDGE_STYLE_A424 (002Ch) .......................141
9.24.27 EDGE_LENGTH_A424 (002Dh) ....................142
9.24.28 RESIDUAL_AMPL_LEVEL_A848 (002Eh) ....142
9.24.29 EDGE_TYPE_A848 (002Fh) ......................... 143
9.24.30 EDGE_STYLE_A848 (0030h) ........................143
9.24.31 EDGE_LENGTH_A848 (0031h) .................... 144
PN5190B1
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Product data sheet
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NXP Semiconductors
PN5190
NFC frontend
9.24.32 RESIDUAL_AMPL_LEVEL_B106 (0032h) .... 144
9.24.33 EDGE_TYPE_B106 (0033h) ..........................144
9.24.34 EDGE_STYLE_B106 (0034h) ........................145
9.24.35 EDGE_LENGTH_B106 (0035h) .................... 145
9.24.36 RESIDUAL_AMPL_LEVEL_B212 (0036h) .... 146
9.24.37 EDGE_TYPE_B212 (0037h) ..........................146
9.24.38 EDGE_STYLE_B212 (0038h) ........................146
9.24.39 EDGE_LENGTH_B212 (0039h) .................... 147
9.24.40 RESIDUAL_AMPL_LEVEL_B424 (003Ah) ....147
9.24.41 EDGE_TYPE_B424 (003Bh) ......................... 148
9.24.42 EDGE_STYLE_B424 (003Ch) .......................148
9.24.43 EDGE_LENGTH_B424 (003Dh) ....................149
9.24.44 RESIDUAL_AMPL_LEVEL_B848 (003Eh) ....149
9.24.45 EDGE_TYPE_B848 (003Fh) ......................... 149
9.24.46 EDGE_STYLE_B848 (0040h) ........................150
9.24.47 EDGE_LENGTH_B848 (0041h) .................... 150
9.24.48 RESIDUAL_AMPL_LEVEL_F212 (0042h) .....151
9.24.49 EDGE_TYPE_F212 (0043h) ..........................151
9.24.50 EDGE_STYLE_F212 (0044h) ........................151
9.24.51 EDGE_LENGTH_F212 (0045h) .....................152
9.24.52 RESIDUAL_AMPL_LEVEL_F424 (0046h) .....152
9.24.53 EDGE_TYPE_F424 (0047h) ..........................153
9.24.54 EDGE_STYLE_F424 (0048h) ........................153
9.24.55 EDGE_LENGTH_F424 (0049h) .....................154
9.24.56 RESIDUAL_AMPL_LEVEL_V100_26
9.24.84 RESIDUAL_AMPL_LEVEL_V10_212
(0066h) ...........................................................166
9.24.85 EDGE_TYPE_V10_212 (0067h) ....................166
9.24.86 EDGE_STYLE_V10_212 (0068h) ..................166
9.24.87 EDGE_LENGTH_V10_212 (0069h) .............. 167
9.24.88 RESIDUAL_AMPL_LEVEL_180003m3_
tari18p88 (006Ah) ..........................................167
9.24.89 EDGE_TYPE_180003m3_tari18p88
(006Bh) .......................................................... 168
9.24.90 EDGE_STYLE_180003m3_tari18p88
(006Ch) ..........................................................168
9.24.91 EDGE_LENGTH_180003m3_tari18p88
(006Dh) ..........................................................169
9.24.92 RESIDUAL_AMPL_LEVEL_180003m3_
tari9p44 (006Eh) ............................................169
9.24.93 EDGE_TYPE_180003m3_tari9p44 (006Fh) ..169
9.24.94 EDGE_STYLE_180003m3_tari9p44
(0070h) ...........................................................170
9.24.95 EDGE_LENGTH_180003m3_tari9p44
(0071h) ...........................................................170
9.24.96 RESIDUAL_AMPL_LEVEL_B_PRIME_106
(0072h) ...........................................................171
9.24.97 EDGE_TYPE_B_PRIME_106 (0073h) .......... 171
9.24.98 EDGE_STYLE_B_PRIME_106 (0074h) ........ 171
9.24.99 EDGE_LENGTH_B_PRIME_106 (0075h) ..... 172
9.24.100 DPC_CONFIG (0076h) ..................................172
9.24.101 DPC_TARGET_CURRENT (077h) ................ 173
9.24.102 DPC_HYSTERESIS_LOADING (079h) ......... 173
9.24.103 DPC_HYSTERESIS_UNLOADING (07Ch) ... 173
9.24.104 DPC_TXLDOVDDPALow (007Dh) .................174
9.24.105 DPC_TXGSN (007Eh) ...................................174
9.24.106 DPC_RDON_Control (007Fh) ........................174
9.24.107 DPC_InitialRDOn_RFOn (0080h) ..................174
9.24.108 DPC_GUARD_TIME (087h) .......................... 174
9.24.109 DPC_ENABLE_DURING_FDT (088h) ...........175
9.24.110 DPC_GUARD_TIME_AFTER_RX (089h) ......175
9.24.111 DPC_LOOKUP_TABLE (008Bh-0133h) ........ 175
9.24.112 ARC_CONFIG (0137h) ..................................176
9.24.113 ARC_VDDPA (0139h) ....................................176
9.24.114 ARC_RM_A106 (013Eh) ............................... 177
9.24.115 ARC_RM_A212 (0148h) ................................179
9.24.116 ARC_RM_A424 (0152h) ................................180
9.24.117 ARC_RM_A848 (015Ch) ............................... 182
9.24.118 ARC_RM_B106 (0166h) ................................183
9.24.119 ARC_RM_B212 (0170h) ................................185
9.24.120 ARC_RM_B424 (017Ah) ............................... 186
9.24.121 ARC_RM_B848 (0184h) ................................188
9.24.122 ARC_RM_F212 (018Eh) ................................189
9.24.123 ARC_RM_F424 (0198h) ................................ 191
9.24.124 ARC_RM_V_6p6 (01A2h) ............................. 192
9.24.125 ARC_RM_V_26 (01ACh) ...............................194
9.24.126 ARC_RM_V53 (01B6h) ................................. 195
9.24.127 ARC_RM_V106 (01C0h) ............................... 197
9.24.128 ARC_RM_V212 (01CAh) ...............................198
9.24.129 ARC_RM_180003m3_SC424_4Man
(004Ah) .......................................................... 154
9.24.57 EDGE_TYPE_V100_26 (004Bh) ................... 154
9.24.58 EDGE_STYLE_V100_26 (004Ch) .................155
9.24.59 EDGE_LENGTH_V100_26 (004Dh) ..............155
9.24.60 RESIDUAL_AMPL_LEVEL_V100_53
(004Eh) .......................................................... 156
9.24.61 EDGE_TYPE_V100_53 (004Fh) ................... 156
9.24.62 EDGE_STYLE_V100_53 (0050h) ..................156
9.24.63 EDGE_LENGTH_V100_53 (0051h) .............. 157
9.24.64 RESIDUAL_AMPL_LEVEL_V100_106
(0052h) ...........................................................157
9.24.65 EDGE_TYPE_V100_106 (0053h) ..................158
9.24.66 EDGE_STYLE_V100_106 (0054h) ................158
9.24.67 EDGE_LENGTH_V100_106 (0055h) .............159
9.24.68 RESIDUAL_AMPL_LEVEL_100_212
(0056h) ...........................................................159
9.24.69 EDGE_TYPE_V100_212 (0057h) ..................159
9.24.70 EDGE_STYLE_V100_212 (0058h) ................160
9.24.71 EDGE_LENGTH_V100_212 (0059h) .............160
9.24.72 RESIDUAL_AMPL_LEVEL_V10_26
(005Ah) .......................................................... 161
9.24.73 EDGE_TYPE_V10_26 (005Bh) ..................... 161
9.24.74 EDGE_STYLE_V10_26 (005Ch) ...................161
9.24.75 EDGE_LENGTH_V10_26 (005Dh) ................162
9.24.76 RESIDUAL_AMPL_LEVEL_V10_53
(005Eh) .......................................................... 162
9.24.77 EDGE_TYPE_V10_53 (005Fh) ..................... 163
9.24.78 EDGE_STYLE_V10_53 (0060h) ....................163
9.24.79 EDGE_LENGTH_V10_53 (0061h) ................ 164
9.24.80 RESIDUAL_AMPL_LEVEL_V10_106
(0062h) ...........................................................164
(01D4h) ..........................................................200
9.24.81 EDGE_TYPE_V10_106 (0063h) ....................164
9.24.82 EDGE_STYLE_V10_106 (0064h) ..................165
9.24.83 EDGE_LENGTH_V10_106 (0065h) .............. 165
9.24.130 ARC_RM_180003m3_SC424_2Man
(01DEh) ..........................................................201
PN5190B1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.0 — 21 April 2021
662230
307 / 308
NXP Semiconductors
PN5190
NFC frontend
9.24.131 ARC_RM_180003m3_SC848_4Man
(01E8h) .......................................................... 203
9.24.132 ARC_RM_180003m3_SC848_2Man
11
Characteristics ................................................ 232
Thermal characteristics ..................................232
Static characteristics ......................................233
Timing characteristics .................................... 237
Clock input .....................................................240
EEPROM characteristics ............................... 241
Package outline ...............................................242
VFBGA64 package ........................................242
HVQFN40 package ........................................244
Package marking .............................................246
Package marking drawing VFBGA64 ............ 246
Package marking drawing HVQFN40 ............246
Reflow soldering footprint VFBGA64 ............ 247
Reflow soldering footprint HVQFN40 ............ 251
Surface mount reflow soldering .................... 255
Handling information ...................................... 256
Appendix: EEPROM LOAD_RF_
11.1
11.2
11.3
11.4
11.5
12
12.1
12.2
13
13.1
13.2
14
15
16
(01F2h) .......................................................... 204
9.24.133 ARC_RM_AI106 (01FCh) .............................. 206
9.24.134 ARC_RM_AI212 (0206h) ...............................207
9.24.135 ARC_RM_AI424 (0210h) ...............................209
9.24.136 RF_DEBOUNCE_TIMEOUT (02B2h) ............210
9.24.137 SENSE_RES (02B3h) ................................... 211
9.24.138 NFC_ID1 (02B5h) ..........................................211
9.24.139 SEL_RES (02B8h) .........................................211
9.24.140 FELICA_POLL_RES (02B9h) ........................211
9.24.141 RANDOM_UID_ENABLE (02CBh) ................ 212
9.24.142 MFC_AUTH_TIMEOUT (02CCh) ...................212
9.24.143 RSSI_TIMER (02DAh) ...................................212
9.24.144 RSSI_TIMER_FIRST_PERIOD (02DCh) .......212
9.24.145 RSSI_CTRL_00_AB (02DEh) ........................212
9.24.146 RSSI_NB_ENTRIES_AB (02DFh) ................. 213
9.24.147 RSSI_THRESHOLD_PHASE_TABLE
17
18
CONFIGURATION FW2.0 .................................257
Appendix: EEPROM LOAD_RF_
19
(02E0h) .......................................................... 213
CONFIGURATION FW2.1 .................................275
Abbreviations .................................................. 293
References .......................................................294
Revision history .............................................. 295
Legal information ............................................296
9.24.148 TX_PARAM_ENTRY_TABLE (03A2h) ...........214
9.24.149 LPCD_AVG_SAMPLES (0492h) ....................217
9.24.150 LPCD_RSSI_TARGET (0494h) ..................... 218
9.24.151 LPCD_RSSI_HYST (0496h) ..........................218
9.24.152 LPCD_CONFIG (0497h) ................................218
9.24.153 LPCD_THRESHOLD_COARSE (049Ah) ...... 219
9.24.154 LPCD_VDDPA (04B5h) ................................. 220
9.24.155 ULPCD_VDDPA_CTRL (04BFh) ................... 221
9.24.156 ULPCD_TIMING_CTRL (04C2h) ...................222
9.24.157 ULPCD_VOLTAGE_CTRL (04C6h) ...............222
9.24.158 ULPCD_RSSI_GUARD_TIME (04C9h) .........222
9.24.159 ULPCD_RSSI_SAMPLE_CFG (04CAh) ........222
9.24.160 ULPCD_THRESH_LVL(04CBh) .....................223
9.24.161 ULPCD_GPIO3 (04CCh) ............................... 223
9.24.162 TXIRQ_GuardTime (0559h) ...........................223
9.24.163 FDT_default_val (055Dh) .............................. 223
9.24.164 RXIRQ_GuardTime (0561h) .......................... 223
9.24.165 NFCLD_RFLD_Valid (006D3h) ......................224
9.24.166 CurrentSensorTrimConfig (0ABCh) ............... 224
9.24.167 CORRECTION_ENTRY_TABLE (0BDAh) .....224
9.24.168 RTRANS_FTRANS_TABLE (0C03h) .............226
9.24.169 CFG_NOV_CAL (0C83h) .............................. 227
9.24.170 NOV_CAL_VAL1 (0C84h) ..............................227
9.24.171 NOV_CAL_VAL2 (0C85h) ..............................227
9.24.172 NOV_CAL_THRESHOLD (0C86h) ................ 228
9.24.173 NOV_CAL_OFFSET1 (0C87h) ......................228
9.24.174 NOV_CAL_OFFSET2 (0C8Bh) ......................228
9.24.175 VDDPA_DISCHARGE (0C8Fh) ..................... 228
9.24.176 ARC_RM_A106_FDT (0C9Dh) ......................228
9.24.177 Tx_Symbol23_Mod_Reg_BR_53 (0CC5h) ....230
9.24.178 Tx_Data_Mod_Reg_BR_53 (0CC9h) ............ 230
9.24.179 Tx_Symbol23_Mod_Reg_BR_106 (0CCDh) . 230
9.24.180 Tx_Data_Mod_Reg_BR_106 (0CD1h) .......... 230
9.24.181 Tx_Symbol23_Mod_Reg_BR_212 (0CD5h) ..230
9.24.182 Tx_Data_Mod_Reg_BR_212 (0CD9h) .......... 230
20
21
22
23
10
Limiting values ................................................231
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 21 April 2021
Document identifier: PN5190B1
Document number: 662230
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