PM908E624ACDWB_技术文档

Freescale Semiconductor, Inc.

Order this document from Analog Marketing: MM908E624/D

MOTOROLA

Rev 1.0, 09/2003

SEMICONDUCTOR TECHNICAL DATA

Preliminary Information

908E624

Integrated Triple High-Side Switch

with Embedded MCU and LIN Serial

Communication for Relay Drivers

TRIPLE HIGH-SIDE SWITCH WITH

EMBEDDED MCU AND LIN

The 908E624 is a highly integrated single-package solution that includes a

high-performance HC08 microcontroller with a SMARTMOS^TManalog control

IC. The HC08 includes flash memory, a timer, enhanced serial

communications interface (ESCI), an analog-to-digital converter (ADC), serial

peripheral interface (SPI), and an internal clock generator module. The analog

control die provides three high-side outputs with diagnostic functions, voltage

regulator, watchdog, operational amplifier, and local interconnect network

(LIN) physical layer.

The 908E624 has been developed as a highly integrated and cost-effective

solution for driving loads using relays within a LIN architecture. It is especially

suited for the control of automotive high-current motors applications using

relays (e.g., window lifts, fans, and sun roofs).

DWB SUFFIX

CASE 1365-01

54-TERMINAL SOICWB

Features

• High-Performance M68HC08 Core

• 16 K Bytes of On-Chip Flash Memory

• 512 Bytes of RAM

ORDERING INFORMATION

Temperature

Package

Device

• Two 16-Bit, 2-Channel Timers

• 10-Bit Analog-to-Digital Converter (ADC)

• LIN Physical Layer Interface

• Low Drop Voltage Regulator

• Three High-Side Outputs

• Two Wake-Up Inputs

Range (T )

A

54 SOIC

WB

PM908E624ACDWB/R2 -40°C to 85°C

• 16 Microcontroller I/Os

908E624 Simplified Application Diagram

908E624 Simp_Sli_imfi_pe_lifd_iedA_App_pp_licl_ai_tc_ioa_nt_Di_iao_gn_ramDiagram

VBAT

908E624

VSUP1

VSUP2

HS3

LIN

Interface

LIN

VREFH

VDDA

EVDD

VCC

+5.0 V

L1

L2

VDD

VREFL

VSSA

EVSS

AGND

GND

HS1

RxD

PTE1/RxD

M

RSTB

RSTB_A

HS2

+E

IRQB

IRQB_A

PTD0/TACH0

PWMin

To Microcontroller A/D Channel

PTA0−4

OUT

-E

PTB1;3−7

PTC2−4

Microcontroller

Ports

PTD1/TACH1

WDCONF

This document contains information on a product under development.

Motorola reserves the right to change or discontinue this product without notice.

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D

G N

GND

r

i e i l f p m A

P U V S

2

VSUP2

P U V S

1

VSUP1

A _ B T R S

RSTB_A

A _ B Q I R

IRQB_A

F N O C W D

WDCONF

N I

M P W

PWMIN

D R x

RxD

D x R / E 1 P T

PTE1/RxD

0 H A C T / 0 D P T

PTD0/TACH0

B Q I R

IRQB

B T R S

RSTB

Tell Dana

Figure 1. 908E624 Simplified Block Diagram

908E624

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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1

2

3

4

5

6

7

8

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQB

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

FLSVPP

PTA3/KBD3

PTA4/KBD4

VREFH

VDDA

9

EVDD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

RSTB

EVSS

VSSA

PTB1/AD1

PTD0/TACH0

PTD1/TACH1

NC

VREFL

PTE1/RxD

NC

RxD

WDCONF

+E

PWMIN

RSTB_A

IRQB_A

NC

-E

OUT

VCC

NC

AGND

VDD

NC

L1

NC

L2

VSUP1

GND

HS3

HS2

LIN

HS1

VSUP2

TERMINAL FUNCTION DESCRIPTION

Terminal Name

Die

Description

Terminal

1

PTB7/AD7/

TBCH1

MCU

Port B, Terminal 7 (shared with ADC and Timer Channel B)

2

PTB6/AD6/

TBCH0

MCU

Port B, Terminal 6 (shared with ADC and Timer Channel B)

3

4

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQB

MCU

–

Port C, Terminal 4

Port C, Terminal 3

5

Port C, Terminal 2

6

Port B, Terminal 5 (shared with ADC)

Port B, Terminal 4 (shared with ADC)

Port B, Terminal 3 (shared with ADC)

Interrupt Input Terminal

7

8

9

10

11

12

13

RSTB

Reset Terminal

PTB1/AD1

PTD0/TACH0

PTD1/TACH1

NC

Port B, Terminal 1 (shared with ADC)

Port D, Terminal 0 (shared with ADC and Timer Channel A)

Port D, Terminal 1 (shared with ADC and Timer Channel A)

Not Connected

14, 15, 16

20–22, 32, 41

17

18

PWMIN

Analog

Direct Input Terminal for High-Side Control

Reset Terminal

RSTB_A

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

908E624

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TERMINAL FUNCTION DESCRIPTION (continued)

Terminal Name

IRQB_A

L1, L2

Die

Description

Terminal

19

Analog

MCU

Interrupt Output Terminal

23, 24

25, 26, 27

28, 31

29

40 V-Rated Wake-Up Inputs L1 and L2

High-Side Outputs 3 to 1

HS3, HS2, HS1

VSUP2, VSUP1

LIN

Supply Voltage Terminals 2 and 1

LIN Physical Layer

30

GND

GND Supply Terminal

33

VDD

Voltage Regulator (+5.0 V) Output Terminal

GND Supply Terminal

34

AGND

35

VCC

+5.0 V Supply Input of the Sense Amplifier

Output of the Sense Amplifier

36

OUT

37

-E

Inverted Input of the Sense Amplifier

Noninverted Input of the Sense Amplifier

Watchdog Configuration Terminal

LIN Receiver Output

38

+E

39

WDCONF

RxD

40

42

PTE1/RxD

VREFL

Port E, Terminal 1 (shared with SCI RX Line)

ADC Supply Terminal

43

MCU

44

VSSA

MCU

GND Supply Terminal

45

EVSS

MCU

GND Supply Terminal

46

EVDD

MCU

+5.0 V Supply Terminal

47

VDDA

MCU

+5.0 V Supply Terminal

48

VREFH

PTA4/KBD4

PTA3/KBD3

FLSVPP

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

MCU

ADC Supply Terminal

49

MCU

Port A, Terminal 4 (shared with Keyboard Module)

Port A, Terminal 3 (shared with Keyboard Module)

Test Terminal

50

MCU

51

MCU

52

MCU

Port A, Terminal 2 (shared with Keyboard Module)

Port A, Terminal 1 (shared with Keyboard Module)

Port A, Terminal 0 (shared with Keyboard Module)

53

MCU

54

MCU

908E624

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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MAXIMUM RATINGS

All voltages are with respect to ground unless otherwise noted.

Rating

Symbol

Value

Unit

ELECTRICAL RATINGS

Supply Voltage

V

-0.3 to 27

-0.3 to 40

-0.3 to 6.0

SUP(ss)

Analog Chip Supply Voltage under Normal Operation (Steady-State)

Analog Chip Supply Voltage under Transient Conditions

MCU Chip Supply Voltage

SUP(pk)

V_DD

Logic Input Terminal Voltage

Analog Chip

V

-0.3 to V +0.3

DD

IN(ANALOG)

V

-0.3 to V +0.3

MCU Chip

IN(MCU)

SS

DD

Maximum MCU Current per Terminal

mA

I

±15

±25

(1)

All Terminals except VDD/VSS/PTA0–PTA6/PTC0–PTC1

Terminals PTA0–PTA6 and PTC0–PTC1

pin(2)

Maximum MCU VSS Output Current

Maximum MCU VDD Input Current

E+, E- Input Voltage

I

100

mA

V

MVSS

MVDD

I

V

-0.3 to 7.0

20

E+E-

E+ E- Input Current

I

mA

V

E+E-

Output Voltage

V

-0.3 to V +0.3

DD

OUT

Output Current

I

20

OUT

LIN Supply Voltage

Normal Operation with a 33 kΩ resistor (Steady-State)

V

-18 to 40

BUS(ss)

Transient Input Voltage (according to ISO7637 Specification) and with

V

-100 to 100

BUS(dynamic)

External Components

L1 and L2

V

Normal Operation (Steady-State)

V

-18 to 40

BUS(ss)

Transient Input Voltage (according to ISO7637 Specification) and with

-150 to 100

BUS(dynamic)

External Components

ESD Voltage

V

ESD1

ESD2

ESD3

Human Body Model L1, L2, and LIN / All Other Terminals (Note 1)

Machine Model (Note 2)

Charge Device Model

±4000/±2000

±200

±500

Notes

1. ESD1 testing is performed in accordance with the Human Body Model (C_ZAP= 100 pF, R_ZAP= 1500 Ω).

2. ESD2 testing is performed in accordance with the Machine Model (C_ZAP=200 pF, R_ZAP= 0 Ω).

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

908E624

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MAXIMUM RATINGS (continued)

All voltages are with respect to ground unless otherwise noted.

Rating

Symbol

Value

Unit

THERMAL RATINGS

Storage Temperature

T

-40 to 150

°C

STG

Operating Junction Temperature (Note 3)

T

-40 to 150

-40 to 125

JAnalog

°C

Analog

MCU

T

JMCU

Terminal Soldering Temperature (Note 4)

Thermal Resistance (Junction to Ambient)

Notes

T

TBD

°C

SOLDER

R

°C/ W

θJA

3. Die temperature of analog and MCU is linked via the package. High temperature on analog die can lead to a high MCU temperature.

4. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

908E624

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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STATIC ELECTRICAL CHARACTERISTICS

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for MCU characteristics. Characteristics

noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect the approximate

parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SUPPLY VOLTAGE RANGE

Nominal DC Voltage Range

V

5.5

–

18

40

27

6.6

–

V

SUP

Input Voltage During Load Dump

V

SUPLD

Input Voltage During Jump Start (Note 5)

Supply Voltage Fail Early Warning Threshold

Supply Voltage Fail Flag Hysteresis

Supply Voltage Overvoltage Warning Threshold

Supply Voltage Overvoltage Flag Hysteresis

V

–

V

SUPJS

SUVew

V

5.7

–

6.0

1.0

19.25

220

V

SUVhyst

V

18

–

20.5

–

V

SOVw

mV

SOVhyst

SUPPLY CURRENT RANGE

Supply Current in Normal Mode (Note 6), (Note 7)

I

–

7.0

40

mA

SUP(norm)

Supply Current in SLEEP Mode (Note 6)

I

µA

SLEEP

V

= 13.5 V

35

SUP

Supply Current in STOP Mode (Note 6)

= 13.5 V

I

µA

STOP

V

–

55

70

SUP

DIGITAL INTERFACE RATINGS

Reset Terminal (Output Terminal Only) in Normal and STOP Mode (RSTB_A)

Reset Threshold

V

TBD

–

4.6

TBD

–

V

RSTth1

High-Level Output Current

I

µA

OL

0 V < V

< 0.7V

-250

OUT

DD

Low-Level Output Voltage

= 1.5 mA

V

OL

I

0

–

0.9

O

Reset Pull-Down Current

I

1.5

–

8.0

mA

ms

pdw

Reset Duration After V

High

t

0.65

1.0

1.35

DD

RST

Logic Input: PWMIN

High-Level Input Voltage

Low-Level Input Voltage

Input Current

V

0.7

–

V +0.3

DD

V

IH

VDD

V

-0.3

0.3V

DD

IL

I

µA

IN

0 V < V < V

-10

–

10

IN

DD

Notes

5. Device is fully functional. All functions are operating. Overtemperature may occur.

6. Total current (I + I ) measured at GND terminal.

VSUP1

VSUP2

7. Supply current of the analog die, microcontroller supply current. Refer to the MC68HC908EY16 specification.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

908E624

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for MCU characteristics. Characteristics

noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect the approximate

parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

DIGITAL INTERFACE RATINGS (continued)

Logic Input: TxD

High-Level Input Voltage

V

3.5

–

V

IH

Low-Level Input Voltage

Input Threshold Hysteresis

Pull-Up Current Source

V

1.5

800

-20

IL

I

50

550

–

mV

µA

IN

I

-100

S

Logic Output: IRQB_A

High-Level Output Voltage

V

OH

I

= -250 µA

V

-0.9

–

V

DD

O

DD

Low-Level Output Voltage

= 1.5 mA

V

OL

I

0

0.9

O

WDCONFIG: WINDOW WATCHDOG CONFIGURATION TERMINAL

External Resistor Range

R

10

–

100

kΩ

EXT

Watchdog Period Accuracy with External Resistor (Excluding Resistor

Accuracy) (Note 8)

WD

%

CACC

-15

–

15

–

Watchdog Period; R = 10 kΩ (1%)

Watchdog Period; R = 100 kΩ (1%)

Watchdog Period Without External Resistor, WDCONF Terminal Open

Notes

Pwd10

Pwd100

Pwdoff

10.558

99.748

150

ms

–

97

205

8. Watchdog timing period calculation formula: Twd = 0.991 R+0.648 (R in kΩ and Twd in ms).

*

908E624

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for MCU characteristics. Characteristics

noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect the approximate

parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

VOLTAGE REGULATOR

Specification with external capacitor 1.0 µF< C < 10 µF and 200 mΩ ≤ ESR ≤ 1.0 Ω. Capacitor value up to 47 µF can be used.

VDD Output Voltage

2.0 mA < I < 50 mA, 5.5 V < V

VDD

V

OUT

DROP

OUTex1

< 27 V

SUP

4.75

–

5.0

0.1

–

5.25

0.25

5.25

DD

Dropout Voltage (Note 9)

= 50 mA

VDD

I

DD

VDD Output Voltage Extended Range

TBD < V < 5.5 V

VDD

TBD

SUP

VDD Output Voltage During STOP Mode (Note 10)

STOP Mode Regulator Current Limitation

VDD

4.75

–

5.0

8.0

110

5.25

–

V

STOP

OUT

I

mA

DDS

I

Output Current Limitation (Note 11)

IDD

60

200

DD

Overtemperature Pre-Warning (Junction)

Thermal Shutdown (Junction)

T

130

165

–

160

–

°C

PRE

T

SD

TSD-TPRE

Temperature Threshold Difference

∆

T

-T

20

30

–

40

–

SD PRE

VSUP Range for Reset Active

Line Regulation

V

3.5

V

SUPr

LR

mV

5.5 V < V

< 27 V, I = 10 mA

–

20

40

10

40

150

100

150

SUP

DD

Load Regulation

LD

mV

1.0 mA < I < 50 mA

DD

Line Regulation

LR-s

LD-s

5.5 V < V

< 27 V, I = 2.0 mA

DD

SUP

Load Regulation

1.0 mA < I

< 10 mA

DD

Notes

9. Measured when voltage has dropped 100 mV below its nominal value.

10. When switching from Normal to STOP mode or from STOP mode to Normal mode, the output voltage can vary within the output voltage

specification.

11. Total VDD regulator current. A 5.0 mA current for operational amplifier is included. Digital output supplied from VDD.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

908E624

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for MCU characteristics. Characteristics

noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect the approximate

parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

PHYSICAL LAYER

Output Low Level

V

LIN-LOW

Tx Low, Rext-Pull-up = 500 Ω

–

1.4

Output High Level

V

LIN-HIGH

Tx High, I

= 1.0 µA

V_SUP-1

20

–

OUT

Pull-Up Resistor to V_SUP

R

30

47

kΩ

PU

Pull-Up Current Source

I

–

50

–

10

75

10

–

150

–

µA

mA

µs

PU

Output Current Shutdown Threshold

Output Current Shutdown Delay

Leakage Current to GND

I

OV-CUR

I

OV-DELAY

I

µA

BUS-PAS-REC

Recessive State, V

8.0 V to 18 V, V

8.0 V to 18 V

LIN

0

-1.0

–

3.0

–

SUP

Leakage Current

I

mA

BUS-NOGND

GND Disconnected, V

= V

, V at -18 V

SUP LIN

1.0

10

GND

Leakage Current to GND

I

µA

BUS

VSUP Disconnected, V

at 18 V

1.0

LIN

LIN Receiver

Recessive

V

0.6V

BUS

–

0.5

–

V_SUP

V

IH

Dominant

Threshold

Input Hysteresis

V

IL

0.4V_BUS

0

0.475

–

V

SUP

V

ITH

0.525

0.175

VIH

V

LIN Wake-Up Threshold

V

WTH

V

= 14 V

–

0.5V

–

SUP

HIGH-SIDE OUTPUTS HS1 AND HS2

Switch On Resistance

Ω

R

T_J= 25°C, I_LOAD= 150 mA, V

> 9.0 V

–

2.0

–

2.5

4.5

–

DS(ON)25

SUP

R

T_J= 125°C, I_LOAD= 150 mA, V

> 9.0 V

DS(ON)125

SUP

3.0

R

T_J= 125°C, I_LOAD= 120 mA, 5.5 V < V

> 9.0 V

DS(ON)3

SUP

Output Current Limitation

Overtemperature Shutdown (Note 9)

Leakage Current

I

200

155

–

500

190

10

mA

°C

µA

V

LIM

Ovt

I

LEAK

Output Clamp Voltage

V

CL

I

= -100 mA

-6.0

–

OUT

Energy Clamp

Notes

E

TBD

mJ

12. When overtemperature occurs, switch is turned off and latched off. Flag is set in SP.I

908E624

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for MCU characteristics. Characteristics

noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect the approximate

parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

HIGH-SIDE OUTPUT HS3

Switch On Resistance

Ω

R

T_J= 25°C, I_LOAD= 50m A, V

> 9.0 V

–

7.0

10

14

DS(ON)25

SUP

R

T_J= 125°C, I_LOAD= 50 mA, V

DS(ON)125

SUP

R

T_J= 125°C, I_LOAD= 30 mA, 5.5 V < V

> 9.0 V

DS(ON)3

SUP

Output Current Limitation

Overtemperature Shutdown

Leakage Current

I

60

155

–

mA

°C

LIM

Ovt

190

10

I

µA

LEAK

SENSE CURRENT AMPLIFIER

Rail to Rail Input Voltage

V

-0.1

0.1

–

V

+0.1

DD

V

IMC

Output Voltage Range (I = 1.0 mA)

V

-0.1

-0.3

O

OUT1

DD

Output Voltage Range (Output Current ±5.0 mA)

Input Bias Current

0.3

–

V

nA

OUT2

I

250

B

Input Offset Current

I

-100

-15

60

–

100

15

–

nA

O

Input Offset Voltage

V

–

mV

dB

IO

Supply Voltage Rejection Ratio (Note 13)

Common Mode Rejection Ratio (Note 13)

Gain Bandwidth (Note 13)

SVR

CMR

GBP

SR

–

70

–

dB

1.0

0.5

40

–

MHz

V/µs

°

Slew Rate

–

Phase Margin (for Gain = 1, Load 100 pF//5.0 kΩ (Note 13)

Open Loop Gain

PHMO

OLG

–

TBD

–

dB

Notes

13. Guaranteed by design.

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STATIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for MCU characteristics. Characteristics

noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect the approximate

parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

L1 AND L2 INPUTS

Negative Switching Threshold

V

thn

thp

5.5 V < V

6.0 V < V

< 6.0 V

< 18 V

< 27 V

2.0

2.5

2.7

2.5

3.0

3.2

3.0

3.5

3.6

SUP

18 V < V

Positive Switching Threshold

V

5.5 V < V

6.0 V < V

< 6.0 V

< 18 V

< 27 V

2.7

3.0

3.5

3.3

4.0

4.2

3.8

4.5

4.7

SUP

18 V < V

Hysteresis

V

HYST

5.5 V < V

< 27 V

0.5

–

1.3

SUP

Input Current

I

µA

µs

IN

-0.2 V < V < 40 V

-10

8.0

–

10

38

IN

Wake-Up Filter Time (Note 14)

t

20

WUF

Notes

14. Guaranteed by design.

908E624

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DYNAMIC ELECTRICAL CHARACTERISTICS

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the MCU chip.

Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect

the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

PHYSICAL LAYER

Driver Characteristics for Normal Slew Rate (Note 15)

Dominant Propagation Delay Tx to LIN (Measurement Threshold 58.1% V

)

t

–

50

µs

SUP

DOM-min

Dominant Propagation Delay Tx to LIN (Measurement Threshold 28.4% V

t

–

SUP

DOM-max

Recessive Propagation Delay Tx to LIN (Measurement Threshold 42.2% V

Recessive Propagation Delay Tx to LIN (Measurement Threshold 74.4% V

)

t

50

SUP

REC-min

)

t

–

50

REC-max

dt1

Propagation Delay Symmetry: t

- t

-10.44

8.12

DOM-min REC-max

dt2

- t

DOM-max REC-min

Driver Characteristics for Slow Slew Rate (Note 15)

Dominant Propagation Delay Tx to LIN (Measurement Threshold 61.1% V

)

t

–

100

µs

SUP

DOM-min

Dominant Propagation Delay Tx to LIN (Measurement Threshold 25.1% V

t

–

SUP

DOM-max

Recessive Propagation Delay Tx to LIN (Measurement Threshold 38.9% V

Recessive Propagation Delay Tx to LIN (Measurement Threshold 77.8% V

)

t

100

SUP

REC-min

)

t

–

100

REC-max

dt1s

Propagation Delay Symmetry: t

- t

-21.88

17.44

DOM-min REC-max

dt2s

- t

DOM-max REC-min

Driver Characteristics for Fast Slew Rate

LIN High Slew Rate (Programming Mode)

Receiver Characteristics and Wake-Up Timings

Receiver Dominant Propagation Delay (Note 16)

Receiver Recessive Propagation Delay (Note 16)

Receiver Propagation Delay Symmetry

Bus Wake-Up Deglitcher

SR

–

20

–

V/µs

FAST

t

–

3.5

–

6.0

2.0

80

–

µs

rL

t

rH

t

-2.0

30

–

r-Sym

t

50

20

propWL

Bus Wake-Up Event Reported Note

t

wake

HIGH-SIDE OUTPUTS HS1 AND HS2

Turn On Time Delay (Note 18)

t

–

10

µs

don

doff

Turn Off Time Delay (Note 18)

Notes

15.

V

from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k, 6.8 nF/660, 10 nf/500. Measurement thresholds: 50% of Tx signal to LIN signal

SUP

threshold defined at each parameter.

16. Measured between LIN signal threshold V or V and 50% of Rx signal.

IL

IH

17.

t

is typically 2 internal clock cycles after LIN rising edge detected. Refer to “LIN Bus Wake-Up Behavior” figure. In SLEEP mode the V

wake

rise time is strongly dependant upon the decoupling capacitor at VDD terminal.

DD

18. Delay between turn on or turn off command and high-side on or high-side off, excluding rise or fall time due to external load.

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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the MCU chip.

Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40°C ≤ T_J≤ 125°C unless otherwise noted. Typical values noted reflect

the approximate parameter mean at T_A= 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

HIGH-SIDE OUTPUTS HS3

Turn On Time Delay (Note 19)

t

–

20

µs

don

doff

Turn Off Time Delay (Note 19)

SPI INTERFACE TIMING

SPI Operating Recommended Frequency

f

0.25

–

4.0

MHz

SPIOP

STATE MACHINE TIMING

Delay Between SSB Low to High Transition (at End of SPI STOP Command)

and STOP Mode Activation (Note 20)

t_SSB-STOP

µs

TBD

7.0

-35

97

TBD

10

–

TBD

13

Interrupt Low-Level Duration

t_INT

µs

%

Internal Oscillator Frequency Accuracy (Note 21)

Normal Request Mode Timeout

OSC-f1

NR_TOUT

35

150

–

205

40

ms

µs

Delay Between SPI Command and HS1/HS2 Turn On (Note 22)

Delay Between SPI Command and HS1/HS2 Turn Off (Note 22)

Delay Between Normal Request and Normal Mode After W/D Trigger Command

t_S-HS

10

on

off

t_S-HS

10

–

48

t_S-NR2N

15

35

70

Delay Between SSB Wake-Up (SSB Low to High) and Normal Request Mode

(VDD On and Reset High)

t

-SSB

w

15

40

80

Delay Between SSB Wake-Up (SSB Low to High) and First Accepted SPI

Command

t_S-SPI

µs

90

30

–

N/A

Delay Between Interrupt Pulse and First SPI Command Accepted

Minimum Time Between Two Rising Edges on SSB

Notes

t_S-1STSPI

t_2SSB

µs

15

–

19. Delay between turn on or turn off command and high-side on or high-side off, excluding rise or fall time due to external load.

20. Guaranteed by design.

21. For information only.

22. Delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation.

908E624

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.

MICROCONTROLLER

For a detailed microcontroller description, refer to the MC68HC908EY16 specification.

Module

Description

Core

Timer

Flash

RAM

ADC

SPI

High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz

Two 16-Bit Timers with 2 Channels (TIM A and TIM B)

16 K Bytes

512 Bytes

10-Bit Analog-to-Digital Converter (4 Channels External Available, 1 Channel Reserved for Analog Die)

SPI Module

ESCI

Standard SCI Module

Bit-Time Measurement

Arbitration

Prescaler with Fine Baud-Rate Adjustment

ICG

Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%)

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TIming Diagrams

Vrec

TXD

Vrec-200mV

LIN

0.4VSUP

Trec-max

Vrec

Tdom-min

58.1% Vsup

Dominant level

74.4% Vsup

60% Vsup

40% Vsup

28.4% Vsup

LIN

VDD

42.2% Vsup

Tdom-max

TpropWL

Twake

Figure 4. Wake-Up SLEEP Mode Timing

Trec-min

RXD

Vrec

TrL

TrH

Figure 2. LIN Timing Measurements for Normal Slew Rate

LIN

0.4VSUP

Dominant level

TXD

IRQB_A

Vrec-200mV

TpropWL

Twake

Trec-max

Vrec

Tdom-min

Figure 5. Wake-Up STOP Mode Timing

61.6% Vsup

77.8% Vsup

60% Vsup

40% Vsup

LIN

25.1% Vsup

38.9% Vsup

Tdom-max

Trec-min

RXD

TrL

TrH

Figure 3. LIN Timing Measurements for Normal Slew Rate

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SYSTEM/APPLICATION INFORMATION

INTRODUCTION

The 908E624 was designed and developed as a highly

output. Other ports are also provided, which include

Operational Amplifier port and two wake-up terminals. An

internal voltage regulator provides power to the MCU chip.

integrated and cost-effective solution for automotive and

industrial applications. For automotive body electronics, the

908E624 is well suited to perform relay control in applications

like window lift, sunroof, etc., via a three-wire LIN bus.

Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables this device to

be compatible with three-wire bus systems, where one wire is

used for communication, one for battery, and the third for

ground.

The 908E624 combines an HC08 MCU core with flash

memory together with a SmartMOS IC chip. The SmartMOS IC

chip combines power and control in one chip. Power switches

are provided on the SmartMOS IC configured as high-side

STATE MACHINE DESCRIPTION

Figure 6 describes how transitions are done between the

different operating modes.

V

Low (150 ms) expired and V

= 0 V

SUV

DD

V

High and Reset counter (1.0 ms) expired and WD not selected

VDD high & Reset counter (1ms) expired & W/D not selected

DD

V

High and Reset counter

V DDHigh and Reset counter

DD

(1.0 ms) expired and

(1 ms) expired and

WD not selected

Normal

Reset

RESET

Request

V

Low OR (NR time-out

DD

occurs (150 ms) and

WD selected)

V

Low and WD fail

DD

and WD selected

Power

Down

Normal

NORMAL

V

Low

DD

STOP

Wake-Up

SLEEP

WD = Watchdog

NR = Normal Request

WD selected means external resistor between WDCONF pin and GND or WDCONF pin open.

WD not selected means WDCONF pin connected to GND.

WD fail means WD trigger occurs in closed window or no SPI WD trigger command.

STOP command means STOP command sent via SPI.

SLEEP command means SPI sleep request followed by SPI SLEEP command.

Wake-up means L1 or L2 state change or LIN bus wake-up or SSB rising edge.

Figure 6. State Machine

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FUNCTIONAL TERMINAL DESCRIPTION

Power Supply Terminals (VSUP1and VSUP2)

VSUP1

Sense Amplifier E+, E-, OUT, AGND, VCC

E+, E-, and OUT are the three terminals of the current sense

amplifier. In addition, the amplifier has its dedicated ground,

AGND, and supply input, VCC. The operational amplifier is only

operating in device Normal mode. It is not operating in SLEEP

or STOP modes.

This power supply terminal supplies the voltage regulator

and the internal logic.

VSUP2

5.0 V Supply Output Terminal (VDD)

This power supply terminal is the positive supply for the high-

side switches.

VDD is the voltage regulator output terminal. This terminal

needed to place an external capacitor to stabilize the regulated

output voltage. The terminal is protected against shorts to GND

with an integrated current limitation (temperature shutdown

could occur).

The 908E624 can be supplied from the battery line through

VSUP1and VSUP2. An external diode is required to protect

against negative transients and reverse battery. It can operate

from 4.5 V and under the jump start condition at 27 V DC.

Device functionality is guaranteed down to 4.5 V at VSUP1 and

VSUP2 terminals. These terminals sustain standard automotive

voltage conditions such as load dump at 40 V.

Receiver Terminal (RxD)

This terminal is the receiver terminal from the LIN physical

layer. It must be connected externally to the RxD terminal of the

MCU.

Overvoltage and Undervoltage Pre-Warning

If the voltage at VSUP1 exceeds 20 V typical or falls below

6.0 V typical, the device generates an interrupt. VSOV or VSUV

bits are set in the SPI register. Information is latched until the bit

is read AND the fault has disappeared. The interrupt is not

maskable.

Interrupt Terminal (IRQB_A)

This terminal is the interrupt output terminal of the analog

die. It must be connected to the IRQB terminal of the MCU.

Reset Terminal (RSTB_A)

Ground Terminal (GND)

This terminal is the reset terminal of the analog die. It must

be connected to the RSTB terminal of the MCU.

GND is the device ground connection.

High-Side Output Terminals (HS1 and HS2)

Test Terminal (FLSVPP)

This is a test terminal. In the application leave this terminal

open.

These are two high-side switches to drive loads such as

relays or lamps. They are protected against overcurrent and

overtemperature and include internal clamp circuitry for

inductive load drive. Control is done through SPI. PWM

capability is offered through the PWMIN input.

PWMIN Terminal

This terminal is the direct PWM input for high-side outputs 1

and 2 (HS1 and HS2). If no PWM control is required, PWMIN

must be connected to VDD in order to have a high level on this

input.

High-Side Output HS3

This high-side switch can be used to drive small lamps, Hall-

effect sensors, or switch pull-up resistors. Control is done

through SPI.

WDCONF Terminal

This terminal is the configuration terminal for the internal

watchdog. A resistor is connected to this terminal. The resistor

value defines the watchdog period. If the terminal is open, the

W/D period is fixed (default value). If this terminal is tied to

GND, the watchdog is disabled (for programming/debug).

LIN Bus Terminal (LIN)

This terminal represents the single-wire bus transmitter and

receiver. It is suited for automotive bus systems and is based

on the LIN Bus Specification.

Wake Up Terminals (L1 and L2)

Port A I/O Terminals

These terminals are high-voltage inputs used to sense

external switches and to wake up the device from SLEEP or

STOP mode. During Normal mode the state of these terminals

can be read through SPI.

Port A input /output (I/O) terminals (PTA6/SS, PTA5/

SPSCK, PTA4/KDB4, PTA3/KBD3, PTA2/KBD2, PTA1/

KBD1, and PTA0/KBD0) are special-function, bidirectional I/O

port terminals. PTA5 and PTA6 are shared with the serial

peripheral interface (SPI). PTA4–PTA0 can be programmed to

serve as keyboard interrupt terminals.

908E624

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PTA5 is shared with the serial peripheral interface (SPI) but

Port E I/O Terminals (PTE1/RxD and PTE0/TxD)

PTE1/RxD and PTE0/TxD are special-function, bidirectional

I/O port terminals that can also be programmed to be enhanced

serial communication.

is not accessible in the multichip approach. This terminal is

internally connected to the SPI clock of the analog die.

PTA6 is shared with the serial peripheral interface (Slave

Select) but is not accessible in the multi-die approach. This

terminal is internally connected to the SSB terminal of the

analog die. In order to get the slave select functionality, this

terminal must be used as standard output.

PTE0/TxD is internally connected to the TxD terminal of the

analog die. The connection for the receiver functionality has to

be done externally.

For details refer to the 68HC908EY16 specification.

External Reset Terminal (RSTB)

A logic [0] on the RSTB terminal forces the MCU to a known

startup state. RSTB is bidirectional, allowing a reset of the

entire system. It is driven low when any internal reset source is

asserted. This terminal contains an internal pull-up resistor that

is always activated, even when the reset terminal is pulled low.

Port B I/O Terminals

PTB7/AD7/TBCH1, PTB6/AD6/TBCH0, and PTB5/AD5–

PTB0/AD0 are special-function, bidirectional I/O port terminals

that can also be used for ADC inputs. PTB7/AD7/TBCH1 and

PTB6/AD6/TBCH0 are special function.

For details refer to the 68HC908EY16 specification.

PTB2 and PTB0 are not accessible in the multi-die approach.

For details refer to the 68HC908EY16 specification.

External Interrupt Terminal (IRQB)

IRQB is an asynchronous external interrupt terminal. This

terminal contains an internal pull-up resistor that is always

activated, even when the IRQB terminal is pulled low.

Port C I/O Terminals

PTC1/MOSI and PTC0/MISO are special-function,

bidirectional I/O port terminals. PTC3/OSC2 and PTC4/OSC1

are shared with the on-chip oscillator circuit through

configuration options.

For details refer to the 68HC908EY16 specification.

Power Supply Terminals (EVDD and EVSS)

For details refer to the 68HC908EY16 specification.

EVDD and EVSS are the power supply and ground

terminals. The MCU operates from a single power supply.

Depending on the application requirements:

• PTC3/OSC2 can be programmed to be OSC2.

• PTC4/OSC1 can be programmed to be OSC1.

• PTC2/MCLK is software selectable to be MCLK, or bus

clock out.

Fast signal transitions on MCU terminals place high, short-

duration current demands on the power supply. To prevent

noise problems, take special care to provide power supply

bypassing at the MCU.

For details refer to the 68HC908EY16 specification.

PTC0 and PTC1 are not directly accessible in the multi-die

approach. These terminals are internally connected to the

MISO and MOSI SPI terminals of the analog die.

Analog Power Supply/Reference Terminals (VDDA,

VREFH, VSSA, and VREFL)

VDDA and VSSA are the power supply terminals for the

analog-to-digital converter (ADC).

Port D I/O Terminals (PTD1/TACH1, PTD0/TACH0/

BEMF)

PTD1/TACH1 and PTD0/TACH0 are special-function,

bidirectional I/O port terminals that can also be programmed to

be timer terminals.

Note VREFH is the high-reference supply for the ADC.

VDDA should be tied to the same potential as VDD via separate

traces. VREFL is the low-reference supply for the ADC. VSSA

should be tied to the same potential as VSS via separate traces.

For details refer to the 68HC908EY16 specification.

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ANALOG DIE DESCRIPTION

Table 1. Operation Modes (continued)

General Description

Normal

Request and

Normal

The 908E624 analog die is an integrated circuit dedicated to

automotive applications. It includes the following functions:

Mode

Reset

STOP

SLEEP

• One fully protected voltage regulator with 50 mA total

output current capability available at the VDD terminal

• Voltage reset function

HS1, HS2,

HS3

OFF

ON or OFF

OFF

• Configurable window watchdog function

• Interrupt output report fault or wake-up

• Wake-up from Lx wake input and LIN bus

• LIN physical interface

LIN

Recessive

only

Tx/Rx

Recessive

state with

wake

Recessive

state with

wake

capability

• Two 150 mA high-side protected switches PWM capable

for relay or lamp drive

To safely enter SLEEP or STOP mode and to ensure that

these modes are not affected by noise issue during SPI

transmission, a dedicated sequence must be send twice:

• One 50 mA high-side protected switch for Hall-effect

sensor, etc.

• Operational amplifier

Enter SLEEP Mode

Two identical SPI commands with:

Operation Modes

D6 = 1, D7 = 1: for low-power (SLEEP or STOP) request.

D5: “1” for LIN pull-up disabled or “0” for pull-up enabled.

D1 = 0, D0 = 0: for SLEEP mode.

Operating modes are controlled by the MODE1 and MODE2

bits in the SPI register. Three modes are available: Normal,

STOP, and SLEEP. Operation modes are described in Table 1.

Table 1. Operation Modes

Normal

Enter STOP Mode

Two identical SPI commands with:

Mode

Reset

Request and

Normal

STOP

SLEEP

D6 = 1, D7 = 1: for low-power (SLEEP or STOP) request.

D5: “1” for LIN pull-up disabled or “0” for pull-up enabled.

D1 = 0, D0 = 1: for STOP mode.

Voltage

Regulator

VDD on

VDD on.

Limited

current

VDD off. Set

to 5.0 V

after wake-

up to enter

Normal

capability

SLEEP or STOP mode is entered after the second SPI

command.

request

Wake-Up

N/A

LIN, state

change on

Lx inputs,

rising edge

on SSB

LIN, state

change on

Lx inputs,

rising edge

on SSB

Capabilities

Interrupts

The IRQB_A terminal is used to report a fault to the MCU. An

interrupt pulse is generated in case of any of the following: VDD

regulator temperature pre-warning, high-side switch 1, 2, or 3

thermal shutdown, V_SUPovervoltage (19.25 V typ), and V_SUP

Reset

Terminal

(RSTB_A)

Low

(1.0 ms)

after VDD

high

Normally

high. Active

low if VDD

Normally

Low. Go to

high after

high. Active

undervoltage (6.0 V typ).

low if VDD walk-up and

undervoltage undervoltage VDD within

This terminal reports to the MCU the L1, L2, or LIN bus wake-

up event when the product is in STOP mode.

occurs or if

WD fail (if WD

is enabled

occurs

specification

After an Interrupt or a wake-up, the register bit INT SOURCE

is set, indicating the source of the event. The SPI data register

will be transferred once.

Watchdog

Not

running

Running if

enabled.

Period

Not running Not running

selected by

resistor at

WDCONF

terminal. WD

cleared by

MODE1/

High-Side Outputs

High-Side Output Terminals HS1 and HS2

These are two high-side switches to drive load such as

relays or lamps. They are protected against over current and

over temperature and include internal clamp circuitry for

inductive load drive. Control is done through SPI. PWM

capability is offered through the PWMIN input.

MODE2 bits

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If PWM control is required, the internal circuitry which drive

The watchdog is cleared by an SPI write to the MODE1 and

MODE2 bits (refer to Table 2).

the internal high-side switch is an AND function between the

SPI bit HS1 (or HS2) and the PWMIN input. In order to have

HS1 on PWMIN must be high and bit HS1 must be set. The

same applies to the HS2 output.

Table 2. Mode Selection Bits

MODE2

MODE1

Description

SLEEP mode (Note 23)

STOP mode

If no PWM control is required, PWMIN must be connected to

the VDD terminal.

0

1

0

1

0

1

If overtemperature occurs on any of the three high-side

switches, the faulty switch is turned off and latched off until the

HS1 (or HS2 or HS3) bit is set to “1” in the SPI register. The

failure is reported through SPI by HSST bit.

Normal mode + watchdog clear (Note 24)

Normal mode

Notes

High-Side Output HS3

23. Special SPI command and sequence is implemented in order to

avoid to go into SLEEP or STOP mode with a single 8-bit SPI

command.

24. When a zero is written to MODE1 bit while MODE2 bit is written

as a one, after the SPI command is completed MODE1 bit is set

to one and product stays in Normal mode. In order to set the

product in SLEEP mode, both MODE1 and MODE2 bits must

be written in the same 8-bit SPI command.

This high-side switch can be used to drive small lamps, Hall-

effect sensors, or switch pull-up resistors. Control is done

through SPI. No PWM control is possible on this terminal.

Window Watchdog

The window watchdog is configurable using the external

resistor at the WDCONF terminal. The watchdog is cleared

through an SPI write operation (MODE1 and MODE2 bit). If the

WDCONF terminal is left open, a fixed watchdog period is

selected (typ. 150 ms). If no watchdog function is required, the

WDCONF terminal must be connected to GND. The watchdog

period is calculated using the following formula:

The watchdog clear on Normal request mode (150 ms) has

no window.

SPI Interface and Register Description

The SPI is an 8-bit SPI. All bits are in a one-data byte. The

MSB (bit 7) is send first (see Figure 8). The minimum time

between two rising edges on the SSB terminal is 15 µs.

Twd [ms] = 0.991 R [kΩ] + 0.648

*

Window closed.

Window open

Window closed

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

No watchdog (WD) clear allowed

no watch dog clear allowed

for watchdog clear

for watch dog clear

MISO

MOSI

D7

D6

D5

D4

D3

D2

D1

D0

Figure 8. Data Format Description

WD timing x 50%

During an SPI communication, the state of MISO reports the

state of the product at time of SSB high-to-low transitions. The

status flag is latched at SSB high-to-low transitions.

WD period (Twd)

WD timing selected by resistor on WDCONF terminal

WD timing selected by resistor on WDConf pin

The following tables describe the SPI register bit meaning,

reset value, and bit reset condition.

Figure 7. Window Watchdog Operation

Table 3. SPI Register Overview

D7

D6

D5

D4

D3

D2

D1

D0

LINSL2

LINSL1

LIN-PU

HS3ON

HS2ON

HS1ON

MODE2

MODE1

W

R

SPI

LINWU

or

VSUV

Register

INT

VSOV

BATFAIL

VDDT

0

HSST

0

L2

L1

SOURCE

LINFAIL

(note 1)

(Note 25)

Write Reset

Value

–

-

–

-

0

POR,

Write Reset

Condition

POR

–

RESET

Notes

25. The first SPI read after reset returns the BATFAIL flag state on bit D4. D7 signals INT SOURCE.

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Table 4. Control Bits Function (Write Operation)

L2—Input L2 Status Flag Bit

This flag reflects the status of the L2 input terminal and

indicates the wake-up source.

D7

D6

D5

D4

D3

D2

D1

D0

LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1

• 1 = L2 input high or wake-up by L2 (first register read after

wake-up indicated with INT SOURCE = 1).

• 0 = L2 input low.

Table 5. Control Bits Function (Read Operation)

D7

D6

D5

D4

D3

D2

D1

D0

INT

LINWU

or

VSOV

VSUV

VDDT

HSST

L2

L1

HSST—High-Side Status Flag Bit

SOURCE

BATFAIL

LINFAIL

This flag is set on overtemperature conditions on one of the

high-side outputs.

HSxON—High-Side x Enable Bit

• 1 = HSx off due to overtemperature.

• 0 = No overtemperature.

This bit enables HSx. Reset clears the HSx bit.

• 1 = HSx switched on (refer to Note below).

• 0 = HSx switched off.

VDDT—Voltage Regulator Status Flag Bit

This flag is set as pre-warning in case of an over-

temperature condition on the voltage regulator.

Note If no PWM on HS1 and HS2 is required, the PWMIN

terminal must be connected to the VDD terminal.

• 1 = Voltage regulator overtemperature condition, pre-

warning.

• 0 = No overtemperature detected.

LIN-PU—LIN Pull-UP Enable Bit

This bit controls the LIN pull-up resistor during SLEEP and

STOP modes.

VSUV/BATFAIL—Undervoltage Status Flag Bit

• 1 = Pull-up disconnected in SLEEP and STOP modes.

• 0 = Pull-up connected in SLEEP and STOP modes.

This flag is set on a V_SUPundervoltage condition.

• 1 = Undervoltage detected. V_SUPbelow 6.0 V

• 0 = No undervoltage detected. V_SUPabove 6.0 V.

Note This bit is only available on the final product. All

versions before MC-Qualification will not include this function.

VSOV—Overvoltage Status Flag Bit

LINSL1 and LINSL2—LIN Baud Rate and Low-Power Mode

Selection Bits

This flag is set on a V_SUPovervoltage condition.

• 1 = Overvoltage detected, V_SUPabove 19 V.

• 0 = No overvoltage detected, V_SUPbelow 18 V.

These bits select the LIN slew rate and requested low-power

mode in accordance with Table 6. Reset clears the LINSL1 and

LINSL2 bits.

LINWU/LINFAIL—LIN Status Flag Bit

Table 6. LIN Baud Rate and Low-Power Mode

Selection Bits

This bit indicates a LIN wake-up condition.

LINSL2

LINSL1

Description

• 1 = LIN bus wake-up occurred or LIN over- current/

temperature occurred.

0

1

0

1

0

Baud Rate up to 20 kbps (normal)

Baud Rate up to 10 kbps (slow)

• 0 = No LIN bus wake-up occurred.

INT SOURCE—Register Content Flags or Interrupt

Fast Program Download

Baud Rate up to 100 kbps

This bit indicates if the register contents reflect the flags or

the wake-up source.

1

Low-Power Mode (SLEEP or STOP) Request

• 1 = SPI word reflects the interrupt or wake-up source.

• 0 = No interrupt occurred. Other SPI bits report real time

status.

L1—Input L1 Status Flag Bit

This flag reflects the status of the L1 input terminal and

indicates the wake-up source.

• 1 = L1 input high or wake-up by L1 (first register read after

wake-up indicated with INT SOURCE = 1).

• 0 = L1 input low.

908E624

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

For More Information On This Product,

22

Go to: www.freescale.com

Freescale Semiconductor, Inc.

PACKAGE DIMENSIONS

DWB SUFFIX

54-TERMINAL SOIC WIDE BODY

PLASTIC PACKAGE

CASE 1365-01

ISSUE O

10.3

5

C

9

7.6

7.4

2.65

2.35

B

52X

0.65

NOTES:

1

54

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

3. DATUMS B AND C TO BE DETERMINED AT THE PLANE

WHERE THE BOTTOM OF THE LEADS EXIT THE

PLASTIC BODY.

PIN 1 INDEX

4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,

PROTRUSION OR GATE BURRS. MOLD FLASH,

PROTRUSION OR GATE BURRS SHALL NOT EXCEED

0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED

AT THE PLANE WHERE THE BOTTOM OF THE LEADS

EXIT THE PLASTIC BODY.

5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSIONS. INTERLEAD FLASH AND

PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER

SIDE. THIS DIMENSION IS DETERMINED AT THE

PLANEWHERETHEBOTTOMOFTHELEADSEXITTHE

PLASTIC BODY.

4

9

18.0

17.8

C

L

6. THIS DIMENSION DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALLNOTCAUSETHELEADWIDTHTOEXCEED0.46

MM. DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN

PROTRUSIONANDADJACENTLEADSHALLNOTLESS

THAN 0.07 MM.

B

7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

8. THESE DIMENSIONS APPLY TO THE FLAT SECTION

OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM

THE LEAD TIP.

9. THE PACKAGE TOP MAY BE SMALLER THAN THE

PACKAGE BOTTOM. THIS DIMENSION IS

27

28

SEATING

A

PLANE

DETERMINED AT THE OUTERMOST EXTREMES OF

THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE

BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,

BUT INCLUDING ANY MISMATCH BETWEEN THE TOP

AND BOTTOM OF THE PLASTIC BODY.

5.15

54X

2X 27 TIPS

0.10

A

0.3

A B C

(0.29)

BASE METAL

R0.08 MIN

°

MIN

0

A

0.30

0.25

(0.25)

0.25

0.29

0.13

GAUGE PLANE

0.38

0.22

PLATING

6

M

0.9

0.5

0.13

A B C

8

°

8

0

SECTION A-A

SECTION B-B

ROTATED 90 CLOCKWISE

°

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

908E624

23

For More Information On This Product,

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Freescale Semiconductor, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee

regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product

or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do

vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer

application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or

sustain life, or for any other appl ication in which the failure of the Motorola product could create a situation where personal injury or death may occur.

Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its

officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Opportunity/Affirmative Action Employer.

MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their

respective owners.

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217.

1-303-675-2140 or 1-800-441-2447

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan.

81-3-3440-3569

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T.,

Hong Kong. 852-26668334

TECHNICAL INFORMATION CENTER: 1-800-521-6274

For More Information On This Product,

Go to: www.freescale.com

MM908E624/D


型号：	PM908E624ACDWB
厂家：	NXP
描述：	8-BIT, FLASH, 8MHz, MICROCONTROLLER, PDSO54, PLASTIC, SOIC-54 光电二极管外围集成电路
文件：	总24页 (文件大小：538K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PM908E624ACDWB [NXP]

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