PIP8000FHN/N1 [NXP]
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC28, 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT788-1, HVQFN-28, Power Management Circuit;
| 型号： | PIP8000FHN/N1 |
| 厂家： | 
NXP |
| 描述： | IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC28, 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT788-1, HVQFN-28, Power Management Circuit |
| 文件： | 总26页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIP8000FHN
PMBus compliant digital power supervisor
Rev. 02 — 6 July 2009
Preliminary data sheet
1. General description
The PIP8000FHN is a Power Management Bus (PMBus) protocol compliant, digital power
supervisor IC, configurable through a host system to meet dynamic converter
performance for a multitude of power supply applications. It is also able to manage power
supply operating conditions as well as to monitor and report the status back to a host
system using the PMBus protocol.
The PMBus standard uses the widely accepted Inter-Integrated Circuit (I2C)
communication protocol for the hardware interface. A number of additional features are
added to enhance the basic I2C communication protocol. These are described in the
System Management Bus (SMBus) protocol and include SMAlert.
2. Features
I PMBus serial interface:
N Query I/O voltage, I/O current, warnings, faults
N Query temperature for up to two temperature sensors
N Configure and measure RPM for up to two fans
N Sequence start-up and turn-off
I Configurable 7-channel A/D with calibration factors
I I2C device-address pin stripping
I Compatible with most analog controllers
I Power-on reset
I I2C-bus up to 400 kHz
I 2.4 V to 3.6 V VDD operating range
I 5 V tolerant I/O pins
I Thermal sense capabilities
I 28 pin HVQFN package, 6 mm × 6 mm
3. Applications
I PMBus compliant low voltage, high current density applications
I DC power distributed systems
I Networking applications
I Servers and server accessories
I Telecommunication systems
I Industrial / ATE power applications
I Storage systems
PIP8000FHN
NXP Semiconductors
Digital power supervisor
I AC/DC and DC-to-DC applications
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PIP8000FHN/N1
HVQFN28 plastic thermal enhanced very thin quad flat package; no leads;
SOT788-1
28 terminals; body 6 × 6 × 0.85 mm
5. Block diagram
A/D V
A/D I
o
FAN CONTROL 1
PROCESSOR
out
FAN CONTROL 2
USER I/O
A/D I
IN
A/D V
IN
FAULT (LED CAPABLE)
ENABLE/DISABLE
A/D TEMP 1
PIP8000
A/D TEMP 2
PWM V set
ALERT
A/D USER DEFINE
FAN SENSOR 1
FAN SENSOR 2
PMBUS
COMMAND
INTERPRETER
CONTROL
2
I C PORT
WRITE PROTECT
014aaa585
Fig 1. Block diagram
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
2 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
6. Pinning information
6.1 Pinning
terminal 1
index area
1
2
3
4
5
6
7
21
20
19
18
17
16
15
PMBUS_CTRL
RESET
SAMPLE_IIN
TEMP1
V
SS
USER_A_D
GPIO
FAULT_LED
PMBUS_ALERT
WRITE_PROTECT
PMBUS_SDA
PIP8000
V
DD
FAN_CONTROL1
FAN_CONTROL2
014aaa583
Transparent top view
Fig 2. Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
PMBUS_CTRL
1
I
An input line from the host controller used to control the
device in conjunction with commands over PMBus. Can
be configured active HIGH or LOW through the
ON_OFF_Config command.
RESET
2
3
4
5
Active LOW reset
VSS
Ground: 0 V reference.
FAULT_LED
PMBUS_ALERT
O
O
I
User configurable. Used to enable/disable green/red LED.
Interrupt line to SMBbus host controller
WRITE_PROTECT 6
When this pin is HIGH or n.c., only the PMBus command
Write Protect can be read. Used to protect PoL data
settings. Ground to Write.
PMBUS_SDA
PMBUS_SCL
ADDRESS0
ADDRESS1
ADDRESS2
7
I/O
I/O
O
Data and clock lines of the I2C/SMBus v 1.1 standard
Data and clock lines of the I2C/SMBus v 1.1 standard
I2C subaddress selection line 0
I2C subaddress selection line 1
I2C subaddress selection line 2
8
9
10
11
O
O
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
3 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
ENABLE
12
O
A default but configurable pin dedicated to controlling the
on/off operation of the power train. May be set either
HIGH or LOW to enable.
RXD_ALERT
TXD
13
14
O
O
O
O
FAN_CONTROL2 15
FAN_CONTROL1 16
User configurable active HIGH/LOW fan 1 on off.
User configurable active HIGH/LOW fan 2 on off.
VDD
17
This is the power supply for normal operation as well as
Idle mode and Power-down mode.
GPIO
18
19
I/O
I
General Purpose Input/Output
User_A_D
Readable User A/D. Coefficients can be set for a
particular calibration/scale factor configuration.
TEMP1
20
I
Common analog temperature sensors connection, the
output of which is typically 25 mV / °C. Coefficients can be
set for a particular calibration/scale factor configuration.
SAMPLE_IIN
SAMPLE_VIN
21
22
I
I
Current sense amplifier connection. Coefficients can be
set for a particular calibration/scale factor configuration.
Connection for either directly to VIN if less than VDD or
through a resistor divider if higher than VDD. Coefficients
can be set for a particular calibration/scale factor
configuration.
VOUT_TRIM
23
O
This is a 20 kHz PWM square wave with a duty cycle that
is directly controlled by the PMBus Vout command. This
waveform is externally integrated to develop a DC level,
buffered, and then driven through a series scaling resistor
to become a current source into the analog controller
voltage feedback pin, which then changes the output
voltage of the power train. The scaling resistor can scale
the duty cycle change at pin 23 so that the power train
output voltage may be varied from V to mV. Coefficients
can be set for a particular calibration/scale factor
configuration.
FAN_SPEED1,
FAN_SPEED2
24, 25
I
Read-only pins connected as a 16-bit counter and used to
count fan RPM in certain applications. This requires fans
with three-pin wiring.
TEMP2
26
27
I
I
See pin 20, TEMP1.
SAMPLE_IOUT
Current sense amp connection. Coefficients can be set
for a particular calibration/scale factor configuration.
SAMPLE_VOUT
28
I
Connected either directly to Vo if less than VDD or through
a resistor divider if higher than VDD. Coefficients can be
set for a particular calibration/scale factor configuration.
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
4 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
7. Functional description
7.1 System interfaces
There are several interfaces:
• PMBus - Two lines consisting of a serial clock and serial data, conforming to
SMBus V. 2.0, including digital lines called control and one SMAlert.
• Seven channels of 10-bit resolution A/D for measurement of temperatures and I/O
volts and current with one channel user definable.
• Two channels of low frequency 16-bit counters for fan speed measurement.
• Pulse Width Modulation (PWM) output with 10 bits of duty cycle resolution for setting
a DC level to adjust analog PWM controllers and hence the power supply output
voltage.
7.2 Operations
PMBus defines that a compliant device must start and operate stably without PMBus
communications. When a module implementing the PIP8000FHN is powered up, the
PIP8000FHN goes through several levels of configuration, finishing by loading the end
user operating parameters from NVRAM, measuring input voltage, checking the power
train for proper operating environment and, when configured, enables the output voltage.
It may operate without any host interaction. If commanded, it can deliver status
information. This will allow the host controller to collect data at the system designer's
initiative, including long term data for system reliability purposes. Finally, it will issue
warnings if operating margins are exceeded or perform selected actions if actual
operating Fault limits are exceeded.
7.3 Product functions
• PMBus compliant, support commands are listed in Table 10
• Configurable overvoltage/undervoltage, overcurrent, and temperature protection
• Configurable response to fault events and warnings
• Configurable sequencing
• Wide range output voltage
• Configurable output voltage ramping
• Non-volatile memory for storing configuration values, device specifications, etc.
7.4 Host interface
The PIP8000FHN can run stand-alone or a host controller can be connected using the
I2C interface. With a host controller the PIP8000FHN can be controlled and monitored
using the PMBus commands as listed in Section 10.
7.4.1 I2C slave address
Any device that exists on the System Management Bus (SMB) as a slave has a unique
address called the slave address. For reference, the following addresses are reserved and
must not be used by or assigned to any SMBus slave device.
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
5 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 3.
Overview slave addresses
Slave address R/W number bit Description
bits 7-1
bit 0
0
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1XX
0101 000
0110 111
1111 0XX
1111 1XX
0001 000
0001 100
1100 001
General call address
START byte
1
X
CBUS address
X
Address reserved for different bus format
Reserved for future use
X
X
Reserved for future use
X
Reserved for ACCESS.bus host
Reserved for ACCESS.bus default address
10-bit slave addressing
X
X
X
Reserved for future use
X
SMBus host
X
SMBus alert response address
SMBus device default address
X
The I2C slave address can be set using the manufacturer specific command
I2C_ADDRESS and pin stripping the I2C subaddress pins. When the I2C slave address is
changed during operation the STORE_DEFAULT_ALL or STORE_USER_ALL command
must be issued to save the I2C slave address in NVRAM and then a software reset needs
to be issued to activate the new I2C address:
I2C address = I2C_ADDRESS + (pin strip bit[A2]bit[A1]bit[A0] < 1)
If an invalid I2C_ADDRESS is read from I2C during start-up the I2C address will be set to
the SMBus device default address. And the CONFIG_COMMAND bit[7] will be set. This
bit indicates if the PMBus state machine will not start. This is done to prevent wrong
coefficients or other configuration settings to be used in the PMBus state machine.
The LSB of I2ADR is the general call bit. When this bit is set, the general call address
(00h) is recognized.
7.4.2 ALERT functionality
The PIP8000FHN supports the SMBus SMAlert line. The alert protocol creates a method
for an I2C slave device to signal the I2C host device. The host can identify the slave with
the fault.
Alter signaling the host the PIP8000FHN will change its slave address to 0x18h (ARA).
The host responds to the SMAlert signal by reading a byte from 0x18h. The slave will
respond with its original slave address and return to that address. The SMAlert line can be
used as a wired system or in a power supply system with multiple PIP8000FHN
supervisor chips.
Fault and warning notification using SMAlert can be configured as described in
Section 7.7.
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
6 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
7.4.3 Packet Error Check (PEC)
The PIP8000FHN supports SMBus PEC protocol dynamically. If a write command is sent
including a PEC the PIP8000FHN will use it to determine if the command was received
correctly. If no PEC is available it will check if the command is supported according to
Section 10.2 and processes it. If a read command is sent the PIP8000FHN will append
the PEC byte when the host reads more bytes than the return data.
7.4.4 Data formats
The PIP8000FHN supports Linear mode and Direct mode data formats. These modes can
be switched real time. However, they are typically selected at the beginning of the
application and stored in NVRAM. Table 4 shows which commands are affected by the
mode setting. From the table it can be noted that three modes are supported:
• All data formats in Direct mode.
• All data in Linear mode not using VOUT_MODE.
• All data in Linear mode using VOUT_MODE for the VOUT related commands.
Table 4.
Modes for data formats
VOUT_MODE
CONFIG_COMMAND Mode
Bit[1] = 0 Direct mode for all commands
Don’t care
bits[7...5] NOT 000 Bit[1] = 1
Linear mode NOT using VOUT_MODE 5-bit
mantissa. Commands in Linear mode are:
PMBUS_VOUT_COMMAND
PMBUS_VOUT_MAX
PMBUS_VOUT_MARGIN_HIGH
PMBUS_VOUT_MARGIN_LOW
PMBUS_READ_VOUT
PMBUS_VOUT_TRIM
PMBUS_VOUT_CAL_OFFSET
PMBUS_VOUT_TRANSITION_RATE
PMBUS_VOUT_SCALE_LOOP
PMBUS_VOUT_SCALE_MONITOR
PMBUS_VOUT_OV_FAULT_LIMIT
PMBUS_VOUT_OV_WARN_LIMIT
PMBUS_VOUT_UV_WARN_LIMIT
PMBUS_VOUT_UV_FAULT_LIMIT
PMBUS_READ_IOUT
PMBUS_IOUT_CAL_GAIN
PMBUS_IOUT_CAL_GAIN
PMBUS_IOUT_CAL_OFFSET
PMBUS_IOUT_OC_FAULT_LIMIT
PMBUS_IOUT_OC_LV_FAULT_LIMIT
PMBUS_IOUT_OC_WARN_LIMIT
PMBUS_READ_VIN
PMBUS_VIN_ON
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
7 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 4.
Modes for data formats …continued
VOUT_MODE
CONFIG_COMMAND Mode
PMBUS_VIN_OFF
PMBUS_VIN_OV_FAULT_LIMIT
PMBUS_VIN_OV_WARN_LIMIT
PMBUS_VIN_UV_WARN_LIMIT
PMBUS_VIN_UV_FAULT_LIMIT
PMBUS_READ_IIN
PMBUS_IIN_OC_FAULT_LIMIT
PMBUS_IIN_OC_WARN_LIMIT
PMBUS_READ_TEMPERATURE_1
PMBUS_OT_FAULT_LIMIT
PMBUS_OT_WARN_
PMBUS_READ_TEMPERATURE_
PMBUS_READ_USER_AD
Linear bits[7..5] 000 Bit[1] = 1
Linear mode using VOUT_MODE 5 bit mantissa.
Commands in Linear mode for:
PMBUS_VOUT_COMMAND
PMBUS_VOUT_MAX
PMBUS_VOUT_MARGIN_HIGH
PMBUS_VOUT_MARGIN_LOW
PMBUS_READ_VOUT
PMBUS_READ_VOUT
PMBUS_VOUT_TRIM
PMBUS_VOUT_CAL_OFFSET
PMBUS_VOUT_TRANSITION_RATE
PMBUS_VOUT_SCALE_LOOP
PMBUS_VOUT_SCALE_MONITOR
PMBUS_VOUT_OV_FAULT_LIMIT
PMBUS_VOUT_OV_WARN_LIMIT
PMBUS_VOUT_UV_WARN_LIMIT
PMBUS_VOUT_UV_FAULT_LIMIT
Linear mode NOT using VOUT_MODE 5 bit
mantissa (normal linear_mode):
PMBUS_READ_IOUT
PMBUS_IOUT_CAL_GAIN
PMBUS_IOUT_CAL_OFFSET
PMBUS_IOUT_OC_FAULT_LIMIT
PMBUS_IOUT_OC_LV_FAULT_LIMIT
PMBUS_IOUT_OC_WARN_LIMIT
PMBUS_READ_VIN
PMBUS_VIN_ON
PMBUS_VIN_OFF
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
8 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 4.
Modes for data formats …continued
VOUT_MODE
CONFIG_COMMAND Mode
PMBUS_VIN_OV_FAULT_LIMIT
PMBUS_VIN_OV_WARN_LIMIT
PMBUS_VIN_UV_WARN_LIMIT
PMBUS_VIN_UV_FAULT_LIMIT
PMBUS_READ_IIN
PMBUS_IIN_OC_FAULT_LIMIT
PMBUS_IIN_OC_WARN_LIMIT
PMBUS_READ_TEMPERATURE_1
PMBUS_OT_FAULT_LIMIT
PMBUS_OT_WARN_
PMBUS_READ_TEMPERATURE_
PMBUS_READ_USER_AD
7.4.5 Coefficients and query
The coefficients and query commands uses the block-write-block-read process call as
described in the SMBus specification, version 2.0.
1
7
1
1
8
1
8
1
SLAVE
ADDRESS
COEFFICIENTS
COMMAND CODE
S
BYTE COUNT = 2
A
A
W
A
...
8
1
8
1
PARAMETER
CODE - LOW BYTE
PARAMETER
CODE - HIGH BYTE
A
A
...
1
7
1
1
8
1
8
1
7
1
SLAVE
ADDRESS
R
A
A
Sr
BYTE COUNT = 5
m: Low Byte
A
A
m: High Byte
...
8
1
8
1
8
1
8
1
1
A
P
b: Low Byte
b: High Byte
A
NA
A
R: One Byte
PEC
014aaa586
Fig 3. Block-write-block-read example for coefficients
7.5 Power-up /power-down
Controlling the power train can be accomplished in the following three ways:
• VIN controls power-up and power-down based on the VIN value passing through
required threshold,
• OPERATION and ON_OFF_CONFIG commands controls on/off switch of the power
train.
• CTL-pin is the on/off switch. It can be configured to assert HIGH or LOW.
7.6 OPERATION and ON_OFF_CONFIG
PIP8000FHN supports the following power-up/power-down process. See Table 5 and
Table 6.
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
9 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
• ON_OFF_CONFIG = 0x00: Power-up when VCC is valid. Uses OPERATION for
margin and normal power-down.
• ON_OFF_CONFIG = 0x04: OPERATION controls everything for normal
power-up/power-down.
• ON_OFF_CONFIG = [0x10, 0x11, 0x12, 0x13]: Control pin initiates everything except
OPERATION-margin. 0x10, 0x11 are assert LOW and 0x12, 0x13 are assert HIGH.
Table 5.
ON_OFF_CONFIG
ON_OFF_CONFIG
Hex
VIN > VIN_on = power-up;
0x00
VIN < VIN_fault/VIN_off = power-down
OPERATION controls power-up/power-down
CTL on active LOW, soft off
0x04
0x10
0x11
0x12
0x13
CTL on active LOW, hard off
CTL on active HIGH, soft off
CTL on active HIGH, hard off
Table 6.
Operation
Operation
Mask
& C0
& C0
& F0
& FC
& FC
& FC
& FC
Hex
0
Immediate OFF
Soft off
40
81
94
98
A4
A8
Unit on no margin
Margin low ignore fault
Margin low faults enabled
Margin high ignore fault
Margin high fault enabled
Margin-no-margin 0x(81,94, 98, A4, A8) always works, regardless of on_off_config
setting.
7.7 ALERT_CONFIG
The byte specifies for which fault condition the SMBus SMAlert protocol will be initiated.
This setting influences only the SMAlert protocol and not the detection and handling of
fault conditions by the PIP8000FHN. When set to 0x00 SMAlert will not signal any
condition. Bit fields are:
Table 7.
ALERT CONFIG
Bits [7..0]
SMAlert protocol used to signal
VOUT_UV_FAULT
VOUT_OV_FAULT
IOUT_OV_FAULT
TON_MAX_FAULT
VIN_OV_FAULT
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
VIN_UV_FAULT
IIN_OV_FAULT
OT_FAULT
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
10 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
8. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Tamb
Tstg
Parameter
Conditions
Min
Max
+125
+150
20
Unit
°C
ambient temperature
storage temperature
HIGH-level output current
LOW-level output current
operating bias
−55
−65
°C
IOH
per I/O pin
-
-
-
-
mA
mA
mA
W
IOL
per I/O pin
20
II/O(tot)(max) maximum total I/O current
Ptot total power dissipation
maximum total I/O current
100
1.5
based on package heat
transfer, not device power
consumption
[1] The following applies to Table 8:
a) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any conditions other than those described in Table 9, Characteristics and Table 8, Limiting values of this
specification are not implied.
b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions will be taken to avoid exceeding the rated maximum.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
9. Characteristics
Table 9.
VDD = 2.4 V to 3.6 V unless otherwise specified.
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
DC electrical characteristics
T
Symbol
Parameter
Conditions
Min
Typ[1]
14
Max
23
7
Unit
mA
mA
µA
IDD
supply current
VDD = 3.6 V
-
-
-
VDD = 3.6 V, Idle mode
5
VDD = 3.6 V, Power-down
mode
55
80
[2]
IDD(tot)
total supply current
VDD = 3.6 V, Power-down
mode
-
1
5
µA
(dV/dt)r
(dV/dt)f
VDDR
rise rate of change of voltage of VDD
fall rate of change of voltage of VDD
data retention voltage
-
-
2
50
-
mV/µs
mV/µs
V
-
-
1.5
-
Vth(HL)
HIGH to LOW threshold
voltage
except SCL, SDA
0.22VDD
0.4VDD
-
V
VIL
LOW-level input voltage
SCL, SDA only
−0.5
-
0.3VDD
0.7VDD
V
V
Vth(LH)
LOW to HIGH threshold
voltage
except SCL, SDA
-
0.6VDD
VIH
HIGH-level input voltage
hysteresis voltage
SCL, SDA only
port 1
0.7VDD
-
-
5.5
-
V
V
Vhys
0.2VDD
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
11 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 9.
DC electrical characteristics …continued
VDD = 2.4 V to 3.6 V unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
VOL
Parameter
Conditions
Min
Typ[1]
Max
Unit
[3]
LOW-level output voltage
IOL = 20 mA;
-
0.6
1.0
V
VDD = 2.4 V − 3.6 V;
all ports;
all modes except Hi-Z
[3]
I
V
OL = 3.2 mA;
DD = 2.4 V − 3.6 V;
-
0.2
0.3
-
V
V
all ports,
all modes except Hi-Z
VOH
HIGH-level output voltage
IOH = −20 µA;
V
DD − 0.3
VDD − 0.2
VDD = 2.4 V − 3.6 V;
Quasi-bidirectional mode;
all ports
I
V
OH = −3.2 mA;
DD = 2.4 V − 3.6 V;
Push-pull mode; all ports
V
DD − 0.7
DD − 1.0
V
DD − 0.4
-
-
V
V
IOH = −20 mA;
V
-
VDD = 2.4 V − 3.6 V;
Push-pull mode; all ports
[4]
[5]
[6]
[7]
Ciss
IIL
input capacitance
-
-
-
-
-
-
-
15
pF
µA
µA
µA
LOW-level input current
input leakage current
VI = 0.4 V
−80
±10
−450
ILI
VI = VIL, VIH, Vth(HL)
VI = 1.5 V at VDD = 3.6 V
IT(HL)
HIGH to LOW transition
current
−30
[1] Typical ratings are not guaranteed. The values listed are at room temperature, VDD = 3 V.
[2] The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock,
brownout detect, and watchdog timer.
[3] See Section 8 for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related
specification.
[4] Pin capacitance is characterized but not tested.
[5] Measured with port in Quasi-bidirectional mode.
[6] Measured with port in High-impedance mode.
[7] Port pins source a transition current when used in Quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when VI is approximately 2 V.
Table 10. AC electrical characteristics
VDD = 2.4 V to 3.6 V unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified [1]
Symbol
Parameter
Conditions
Variable clock
Min Max
Unit
fosc(int)
fosc(wd)
internal oscillator frequency
watchdog oscillator frequency
7.189
320
7.557
520
MHz
kHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
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PIP8000FHN
NXP Semiconductors
Digital power supervisor
10. PMBus
10.1 Introduction
The PIP8000FHN supports the PMBus Power System Management Protocol
Specifications, revision 1.1. In Table 11 below all supported commands are marked grey.
Table 11 shows all supported commands including PIP8000FHN manufacturer specific
commands.
The fan monitor counts the LOW to HIGH transitions from the fan tachometer. There are
two fan inputs. The fan tachometer must produce a voltage swing with a LOW below
0.75 V and a HIGH above 2.5 V. The peak transition should be limited to 3.3 V to protect
the PIP8000FHN measurement inputs.
10.2 Non-volatile memory
The PIP8000FHN has on board non-volatile memory to store:
• Configurable settings like VO(max), and VO.
• Warning and fault thresholds for overvoltage, overcurrent, and overtemperature.
• Calibration information like coefficients.
During start-up the RESTORE_USER_ALL command is called to store all USER
parameters into the running configuration. When settings are changed
STORE_USER_ALL can be used to store the changed settings into the USER NVRAM
storage area. RESTORE_DEFAULT_ALL and STORE_DEFAULT_ALL can be used to
change parameters in the DEFAULT storage area. The running configuration needs to be
used to swap between USER and DEFAULT storage area.
10.3 PMBus commands
Table 11 contains a list of the PMBus commands.
Hex = PMBus command hex value, Command Name = PMBus command name,
# = Number of Data Bytes. R/W/C = Read / Write / Command. Some commands are R/W
where they are only defined as Read in the PMBus. The Write is supported to enable
factory programming.
Table 11. PMBus commands
Hex Command name
#
SMBus
transaction value
type
Default
Supported Comments
range
ON, OFF, and margin testing
00
01
02
03
04
05
06
PAGE
1
1
1
0
R/W
OPERATION[1]
ON_OFF CONFIG[1]
CLEAR_FAULTS[1]
PHASE
R/W
R/W
C
0x80
0x18
Reserved
Reserved
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
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PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 11. PMBus commands …continued
Hex Command name
#
SMBus
transaction value
type
Default
Supported Comments
range
07
08
09
Reserved
Reserved
Reserved
0A Reserved
0B Reserved
0C Reserved
0D Reserved
0E Reserved
0F
Reserved
Address and memory related commands
10
11
12
13
14
15
16
17
18
19
WRITE_PROTECT[1]
1
0
0
1
1
0
0
1
1
1
1
R/W
C
0x00
STORE_DEFAULT_ALL[1]
RESTORE_DEFAULT_ALL[1]
STORE_DEFAULT_CODE
RESTORE_DEFAULT_CODE
STORE_USER_ALL[1]
RESTORE_USER_ALL[1]
STORE_USER_CODE
RESTORE_USER_CODE
CAPABILITY[1]
C
W
W
C
C
W
W
R
1A QUERY[1]
1B Reserved
1C Reserved
1D Reserved
1E Reserved
R
1F
Reserved
Output voltage related commands
20
21
22
23
24
25
26
27
28
29
VOUT_MODE[1]
VOUT_COMMAND[1]
1
2
2
2
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x40
0xD101
VOUT_TRIM
VOUT_CAL
VOUT_MAX[1]
VOUT_MARGIN_HIGH[1]
VOUT_MARGIN_LOW[1]
VOUT_TRANSITION_RATE
VOUT_DROOP
0x7303
0x4502
0x1701
VOLTAGE_SCALE_LOOP
2
2
R/W
R/W
2A VOLTAGE_SCALE_MONITOR
2B Reserved
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
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PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 11. PMBus commands …continued
Hex Command name
#
SMBus
transaction value
type
Default
Supported Comments
range
2C Reserved
2D Reserved
2E Reserved
2F
Reserved
Other commands
30
31
32
33
34
35
36
37
38
39
COEFFICIENTS[1]
5
2
2
2
R/W
R/W
R/W
R/W
POUT_MAX
MAX_DUTY
FREQUENCY_SWITCH
Reserved
VIN_ON[1]
VIN_OFF[1]
2
2
R/W
R/W
0x6E02
0x6803
INTERLEAVE
IOUT_CAL_GAIN
IOUT_CAL_OFFSET
2
2
1
2
R/W
R/W
R/W
R/W
3A FAN_CONFIG_1_2[1]
3B FAN_COMMAND_1[1]
0xFF
0xFFFF
x x x x x x 1 0 fan1 is off by setting
P0.6 LOW
x x x x x x 1 1 fan1 is on by setting
P0.6 HIGH
x x x x x x 0 0 fan1 is off by setting
P0.6 HIGH
x x x x x x 0 1 fan1 is on by setting
P0.6 LOW
3C FAN_COMMAND_2[1]
2
R/W
0xFFFF
x x x x x x 1 0 fan1 is off by setting
P0.7 LOW
x x x x x x 1 1 fan1 is on by setting
P0.7 HIGH
x x x x x x 0 0 fan1 is off by setting
P0.7 HIGH
x x x x x x 0 1 fan1 is on by setting
P0.7 LOW
3D FAN_CONFIG_3_4
3E FAN_COMMAND_3
1
2
2
R/W
R/W
R/W
3F
FAN_COMMAND_4
Fault related commands
40
41
42
43
44
45
46
VOUT_OV_FAULT_LIMIT[1]
VOUT_OV_FAULT_RESPONSE[1]
VOUT_OV_WARN_LIMIT[1]
VOUT_UV_WARN_LIMIT[1]
VOUT_UV_FAULT_LIMIT[1]
VOUT_UV_FAULT_RESPONSE[1]
IOUT_OC_FAULT_LIMIT[1]
2
1
2
2
2
1
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x2703
0xBA
0x8002
0x3201
0x8B00
0x00
0x1805
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
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PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 11. PMBus commands …continued
Hex Command name
#
SMBus
transaction value
type
Default
Supported Comments
range
47
48
49
IOUT_OC_FAULT_RESPONSE[1]
IOUT_OC_LV_FAULT_LIMIT
1
2
1
2
2
1
R/W
R/W
R/W
R/W
R/W
R/W
0x00
IOUT_OC_LV_FAULT_RESPONSE
4A IOUT_OC_WARN_LIMIT[1]
4B IOUT_UC_FAULT_LIMIT
4C IOUT_UC_FAULT_RESPONSE
4D Reserved
0x9504
4E Reserved
4F
50
51
52
53
54
55
56
57
58
59
OT_FAULT_LIMIT[1]
OT_FAULT_RESPONSE[1]
OT_WARN_LIMIT[1]
2
1
2
2
2
1
2
1
2
2
2
1
2
1
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0002
0x00
0x0002
UT_WARN_LIMIT
UT_FAULT_LIMIT
UT_FAULT_RESPONSE
VIN_OV_FAULT_LIMIT[1]
VIN_OV_FAULT_RESPONSE[1]
VIN_OV_WARN_LIMIT[1]
VIN_UV_WARN_LIMIT[1]
VIN_UV_FAULT_LIMIT[1]
0x6803
0x00
0x2903
0x02AC
0x6E02
0x00
5A VIN_UV_FAULT_RESPONSE[1]
5B IIN_OC_FAULT_LIMIT[1]
5C IIN_OC_FAULT_RESPONSE[1]
5D IIN_OC_WARN_LIMIT[1]
5E POWER_GOOD_ON
0x8E02
0x00
0xEB01
5F
POWER_GOOD_OFF
Output voltage sequencing commands
60
61
62
63
64
65
66
67
68
69
TON_DELAY[1]
TON_RISE[1]
TON_MAX_FAULT_LIMIT[1]
TON_MAX_FAULT_RESPONSE[1]
TOFF_DELAY[1]
2
2
2
1
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0005
0x0000
0x6400
0x00
0x0000
0x0000
TOFF_FALL[1]
TOFF_MAX_WARN_LIMIT
Reserved
POUT_OP_FAULT_LIMIT
POUT_OP_FAULT_RESPONSE
2
1
2
2
R/W
R/W
R/W
R/W
6A POUT_OP_WARN_LIMIT
6B PIN_OP_WARN_LIMIT
6C Reserved
PIP8000FHN_2
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Preliminary data sheet
Rev. 02 — 6 July 2009
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PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 11. PMBus commands …continued
Hex Command name
#
SMBus
transaction value
type
Default
Supported Comments
range
6D Reserved
6E Reserved
6F
Reserved
Unit status commands
70
71
72
73
74
75
76
77
78
79
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
STATUS_BYTE[1]
STATUS_WORD[1]
1
2
1
1
1
1
1
1
1
1
1
R
R
R
R
R
R
R
R
R
R
R
0x00
0x0000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
7A STATUS_VOUT[1]
7B STATUS_IOUT[1]
7C STATUS_INPUT[1]
7D STATUS_TEMPERATURE[1]
7E STATUS_CML[1]
7F
80
81
82
83
84
85
86
87
STATUS_OTHER[1]
STATUS_MFR_SPECIFIC[1]
STATUS_FANS_1_2[1]
STATUS_FANS_3_4
Reserved
Reserved
Reserved
Reserved
Reserved
Reading parametric information
88
89
READ_VIN[1]
READ_IIN[1]
2
2
R
R
8A READ_VCAP
8B READ_VOUT[1]
8C READ_IOUT[1]
8D READ_TEMPERATURE_1[1]
8E READ_TEMPERATURE_2[1]
2
2
2
2
R
R
R
R
8F
90
91
READ_TEMPERATURE_3
READ_FANSPEED_1[1]
READ_FANSPEED_2[1]
2
2
R
R
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
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PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 11. PMBus commands …continued
Hex Command name
#
SMBus
transaction value
type
Default
Supported Comments
range
92
93
94
95
96
97
READ_FANSPEED_3
READ_FANSPEED_4
READ_DUTY_CYCLE
READ_FREQUENCY
READ_POUT
2
2
2
2
2
2
R
R
R
R
R
R
READ_PIN
Manufacturers information
98
PMBUS REVISION[1]
Inventory information
99
MFR_ID[1]
9A MFR_MODEL[1]
9B MFR_REVISION[1]
9C MFR_LOCATION[1]
9D MFR_DATE[1]
1
R
2
2
2
2
4
2
R/W
R/W
R/W
R/W
R/W
R/W
0x0100
0x0300
0x01BA
0x565F
0xFF00
0xFFFF
9E MFR_SERIAL[1]
9F
Reserved
Manufacturer ratings
A0 MFR_VIN_MIN[1]
A1 MFR_VIN_MAX[1]
A2 MFR_IIN_MAX[1]
A3 MFR_PIN_MAX[1]
A4 MFR_VOUT_MIN[1]
A5 MFR_VOUT_MAX[1]
A6 MFR_IOUT_MAX[1]
A7 MFR_POUT_MAX[1]
A8 MFR_TAMBIENT_MAX[1]
A9 MFR_TAMBIENT_MIN[1]
AA MFR_EFFICIENCY_LL
AB MFR_EFFICIENCY_HL
AC Reserved
2
2
2
2
2
2
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x02FF
0xFF05
0x44FF
0xFFFF
0x3000
0x0066
0xFFFF
0xFFFF
0xFFFF
0x10FF
AD Reserved
AE Reserved
AF Reserved
User data and configuration
B0 USER_DATA_00[1]
B1 USER_DATA_01
B2 USER_DATA_02
B3 USER_DATA_03
B4 USER_DATA_04
2
R/W
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
18 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 11. PMBus commands …continued
Hex Command name
#
SMBus
transaction value
type
Default
Supported Comments
range
B5 USER_DATA_05
B6 USER_DATA_06
B7 USER_DATA_07
B8 USER_DATA_08
B9 USER_DATA_09
BA USER_DATA_10
BB USER_DATA_11
BC USER_DATA_12
BD USER_DATA_13
BE USER_DATA_14
BF USER_DATA_15
C0 Reserved
C1 Reserved
C2 Reserved
C3 Reserved
C4 Reserved
C5 Reserved
C6 Reserved
C7 Reserved
C8 Reserved
C9 Reserved
CA Reserved
CB Reserved
CC Reserved
CD Reserved
CE Reserved
CF Reserved
Manufacturer specific commands
D0 FAN_1_UNDERSPEED
WARN_LIMIT[1]
2
2
2
2
R/W
R/W
R/W
R/W
D1 FAN_1_UNDERSPEED
FAULT_LIMIT[1]
D2 FAN_2_UNDERSPEED
WARN_LIMIT[1]
D3 FAN_2_UNDERSPEED
FAULT_LIMIT[1]
D4 MFR_SPECIFIC_4
D5 MFR_SPECIFIC_5
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
19 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 11. PMBus commands …continued
Hex Command name
#
SMBus
Default
Supported Comments
transaction value
type
range
D6 RETRY_TIME_MS[1]
1
R/W
0x0A
This is the fault response retry VO
high time. It is used in Fault
response mode to enable the VO
to check if an error condition is
resolved. RETRY_TIME_MS is
specified in units of 10 ms. Default
value is 0x0A, corresponding to a
100 ms delay.
D7 READ_USER_AD[1]
D8 TIME_UP[1]
2
4
R
R
The PIP8000FHN has a user
defined analog / digital converter.
The value of the AD can be read
with this command.
0x00
0x00
0x00
Seconds
0-60
Total power uptime of the device.
Byte 1 = Seconds,
Byte 2 = Minutes,
Minutes
0-60
Byte 3 and 4 = Hours
Hours
0-43800
D9 TIME_RESET[1]
DA CONFIG_COMMAND[1]
0
1
C
Resets TIME_UP to zero
bit[0] = 1; GPIO output HIGH
bit[1] = 1; Linear mode
0x00
0x00 to
0x03
bit[7] = 1 PMBus state machine
off. PMBUS_READ commands
can be used to determine correct
configuration parameters before
enabling the PMBus state
machine.
DB MFR_SPECIFIC_11
DC MFR_SPECIFIC_12
DD ALERT_CONFIG[1]
1
1
R/W
R/W
0x00
0x26
0x00 -
0xFF
The byte specifies for which fault
condition the SMBus SMAlert
protocol will be initiated.
The byte specifies the I2C
address. If Bit[0] is the general call
bit. When set, the general call
address (00H) is recognized.
Otherwise it is ignored.
DE I2C_ADDRESS[1]
0x01 -
0xFF
DF VERSION[1]
2
R
0x1222
PIP version number x.x.x.x. a
nibble for each position
E0 RESET[1]
Software reset
E1 MFR_SPECIFIC_17
E2 MFR_SPECIFIC_18
E3 MFR_SPECIFIC_19
E4 MFR_SPECIFIC_20
E5 MFR_SPECIFIC_21
E6 MFR_SPECIFIC_22
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
20 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
Table 11. PMBus commands …continued
Hex Command name
#
SMBus
transaction value
type
Default
Supported Comments
range
E7 MFR_SPECIFIC_23
E8 MFR_SPECIFIC_24
E9 MFR_SPECIFIC_25
EA MFR_SPECIFIC_26
EB MFR_SPECIFIC_27
EC MFR_SPECIFIC_28
ED MFR_SPECIFIC_29
EE MFR_SPECIFIC_30
EF MFR_SPECIFIC_31
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
MFR_SPECIFIC_32
MFR_SPECIFIC_33
MFR_SPECIFIC_34
MFR_SPECIFIC_35
MFR_SPECIFIC_36
MFR_SPECIFIC_37
MFR_SPECIFIC_38
MFR_SPECIFIC_39
MFR_SPECIFIC_40
MFR_SPECIFIC_41
FA MFR_SPECIFIC_42
FB MFR_SPECIFIC_43
FC MFR_SPECIFIC_44
FD MFR_SPECIFIC_45
FE MFR_SPECIFIC_COMMAND_EXT
FF PMBUS_COMMAND_EXT
[1] Supported command
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
21 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
11. Application information
V
IN
V
POWERTRAIN
PIP8000
DD
Disable
(PIP2××)
V
o
TXD
PMBUS_SCL
PMBUS_SDA
PMBUS_CTRL
PMBUS_ALERT
WRITE_PROTECT
SUBADDRESS (0, 1, 2)
TEMP1, TEMP2
FAN_CONTROL1
FAN_CONTROL2
FAN_SPEED1
PWM
CONTROLLER
VOUT_TRIM
FAN_SPEED2
USER_A_D
GPIO
FAULT_LED
sense
V
IN
SAMPLE_VOUT
V sense
o
SAMPLE_VIN
SAMPLE_IIN
I sense
I
V
SS
SAMPLE_IOUT
R
R
SENSE
SENSE
V
RTN
V
RNT
o
IN
I
sense
out
014aaa584
Fig 4. Application diagram
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
22 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
12. Package outline
HVQFN28: plastic thermal enhanced very thin quad flat package; no leads;
28 terminals; body 6 x 6 x 0.85 mm
SOT788-1
D
B
A
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
e
v
M
M
C
1
b
C
C
A B
8
14
w
L
7
15
e
e
E
2
h
21
1
terminal 1
index area
28
22
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
e
2
y
D
D
E
L
v
w
y
1
h
h
max.
0.05 0.35
0.00 0.25
6.1 4.25 6.1 4.25
5.9 3.95 5.9 3.95
0.75
0.50
mm
0.2
0.05 0.1
1
0.65
3.9
3.9
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
SOT788-1
- - -
MO-220
- - -
02-10-22
Fig 5. Package outline SOT788-1 (HVQFN28)
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
23 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
13. Revision history
Table 12. Revision history
Document ID
PIP8000FHN_2
Modifications
Release date
20090706
Data sheet status
Change notice
Supersedes
Preliminary data sheet
-
PIP8000FHN_1
• Figure 2 “Pin configuration” package outline updated.
PIP8000FHN_1
20090312
Preliminary data sheet
-
-
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
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PIP8000FHN
NXP Semiconductors
Digital power supervisor
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PIP8000FHN_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 6 July 2009
25 of 26
PIP8000FHN
NXP Semiconductors
Digital power supervisor
16. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
7.3
Functional description . . . . . . . . . . . . . . . . . . . 5
System interfaces . . . . . . . . . . . . . . . . . . . . . . . 5
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Product functions . . . . . . . . . . . . . . . . . . . . . . . 5
Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I2C slave address . . . . . . . . . . . . . . . . . . . . . . . 5
ALERT functionality . . . . . . . . . . . . . . . . . . . . . 6
Packet Error Check (PEC) . . . . . . . . . . . . . . . . 7
Data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Coefficients and query . . . . . . . . . . . . . . . . . . . 9
Power-up /power-down . . . . . . . . . . . . . . . . . . . 9
OPERATION and ON_OFF_CONFIG . . . . . . . 9
ALERT_CONFIG . . . . . . . . . . . . . . . . . . . . . . 10
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.6
7.7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 11
10
PMBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Non-volatile memory. . . . . . . . . . . . . . . . . . . . 13
PMBus commands . . . . . . . . . . . . . . . . . . . . . 13
10.1
10.2
10.3
11
12
13
Application information. . . . . . . . . . . . . . . . . . 22
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.1
14.2
14.3
14.4
15
16
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 July 2009
Document identifier: PIP8000FHN_2
相关型号：
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