PHP45N03LT [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | PHP45N03LT |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总8页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
VDSS = 30 V
ID = 45 A
R
DS(ON) ≤ 24 mΩ (VGS = 5 V)
g
RDS(ON) ≤ 21 mΩ (VGS = 10 V)
s
GENERAL DESCRIPTION
PINNING
SOT78 (TO220AB)
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope
using ’trench’ technology. The
device has very low on-state
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
PIN
DESCRIPTION
tab
1
2
gate
drain
3
source
drain
tab
1 2 3
ThePHP45N03LT issuppliedin the
SOT78 (TO220AB) conventional
leaded package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
-
-
-
-
-
-
-
-
30
30
15
45
36
180
86
175
V
V
V
A
A
A
W
˚C
RGS = 20 kΩ
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
Ptot
Tstg, Tj
- 55
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Thermal resistance junction to
mounting base
-
-
1.75
K/W
Rth j-a
Thermal resistance junction to
ambient
in free air
60
-
K/W
November 1997
1
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
30
27
1
0.5
-
-
-
-
-
-
-
-
-
-
-
2
V
V
V
V
Tj = -55˚C
VDS = VGS; ID = 1 mA
1.5
-
-
0.05
-
10
20
16
-
Tj = 175˚C
Tj = -55˚C
-
2.3
10
500
100
24
21
45
IDSS
Zero gate voltage drain current VDS = 30 V; VGS = 0 V;
µA
µA
nA
mΩ
mΩ
mΩ
Tj = 175˚C
IGSS
RDS(ON)
Gate source leakage current
Drain-source on-state
resistance
VGS = ±5 V; VDS = 0 V
VGS = 5 V; ID = 25 A
VGS = 10 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
DYNAMIC CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 25 V; ID = 25 A
8
16
-
S
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 40 A; VDD = 24 V; VGS = 5 V
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
23
3
12
-
-
-
nC
nC
nC
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
2000 2500
380
250
pF
pF
pF
450
300
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 25 A;
VGS = 5 V; RG = 5 Ω
Resistive load
-
-
-
-
30
80
95
40
45
130
135
55
ns
ns
ns
ns
Ld
Ld
Ls
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
-
3.5
4.5
7.5
-
-
-
nH
nH
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
-
-
45
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
180
1.2
-
A
V
IF = 25 A; VGS = 0 V
IF = 40 A; VGS = 0 V
0.95
1.0
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 40 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 25 V
-
-
52
0.08
-
-
ns
µC
November 1997
2
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 25 A; VDD ≤ 25 V;
-
-
60
mJ
VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
November 1997
3
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT
Normalised Power Derating
PD%
Zth j-mb / (K/W)
D =
120
110
100
90
80
70
60
50
40
30
20
10
0
10
1
0.5
0.2
0.1
0.1
0.01
p
t
0.05
p
t
P
D
D =
T
0.02
0
t
T
0
20
40
60
80
Tmb /
100 120 140 160 180
C
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID / A
120
110
100
90
80
70
60
50
40
30
20
10
0
80
60
40
20
0
4.5
10
5
6
4
VGS / V =
3.5
3
2.5
0
20
40
60
80
100 120 140 160 180
0
2
4
6
8
10
Tmb /
C
VDS / V
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
4.5
ID / A
RDS(ON) / mOhm
40
30
20
10
0
1000
100
10
4
5
tp = 10 us
100 us
6
RDS(ON) = VDS / ID
10
1 ms
VGS / V =
DC
10 ms
1
1
10
VDS / V
100
0
20
40
ID / A
60
80
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
November 1997
4
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT
VGS(TO) / V
max.
ID / A
60
2.5
2
50
Tj / C = 25
175
typ.
40
1.5
1
30
20
10
0
min.
0.5
0
0
1
2
3
4
5
6
-100
-50
0
50
Tj / C
100
150
200
VGS / V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
Sub-Threshold Conduction
gfs / S
25
20
15
10
5
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
Tj / C = 25
175
2%
typ
98%
0
0
10
20
30
ID / A
40
50
60
0
0.5
1
1.5
2
2.5
3
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
a
C / pF
10000
1000
100
2
1.5
1
Ciss
0.5
Coss
Crss
0
-100
0
100
200
-50
50
Tj / C
150
0.1
1
10
100
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
November 1997
5
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT
WDSS%
VGS / V
5
120
110
100
90
80
70
60
50
40
30
20
10
0
VDS / V = 6
24
4
3
2
1
0
0
5
10
15
20
25
20
40
60
80
100
120
140
160
180
QG / nC
Tmb /
C
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 40 A; parameter VDS
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 25 A
IF / A
60
50
40
30
20
10
0
VDD
+
L
VDS
Tj / C = 175
25
-
VGS
-ID/100
T.U.T.
0
R 01
RGS
shunt
0
0.5
1
1.5
2
VSDS / V
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
)
VDD
+
-
RD
VDS
VGS
0
RG
T.U.T.
Fig.17. Switching test circuit.
November 1997
6
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
4,5
max
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
1 2 3
max
(2x)
0,9 max (3x)
0,6
2,4
2,54 2,54
Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
November 1997
7
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
November 1997
8
Rev 1.200
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