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PHD37N06LT/T3 [NXP]

TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power;
PHD37N06LT/T3
型号： PHD37N06LT/T3
厂家： NXP    NXP
描述：

TRANSISTOR 37 A, 55 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power

开关 脉冲 晶体管
文件： 总12页 (文件大小：115K)
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Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
FEATURES  
SYMBOL  
QUICK REFERENCE DATA  
• ’Trench’ technology  
• Very low on-state resistance  
• Fast switching  
• Stable off-state characteristics  
• High thermal cycling performance  
• Low thermal resistance  
VDSS = 55 V  
d
ID = 37 A  
R
DS(ON) ≤ 35 mΩ (VGS = 5 V)  
g
RDS(ON) ≤ 32 mΩ (VGS = 10 V)  
s
GENERAL DESCRIPTION  
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.  
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching  
applications.  
The PHP37N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.  
The PHB37N06LT is supplied in the SOT404 surface mounting package.  
The PHD37N06LT is supplied in the SOT428 surface mounting package.  
PINNING  
SOT78 (TO220AB)  
SOT404  
SOT428  
PIN  
1
DESCRIPTION  
tab  
tab  
tab  
gate  
2
drain1  
source  
3
2
2
tab drain  
1
3
1
3
1 2 3  
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDSS  
VDGR  
VGS  
ID  
Drain-source voltage  
Drain-gate voltage  
Gate-source voltage  
Continuous drain current  
Tj = 25 ˚C to 175˚C  
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ  
-
-
-
-
-
-
-
55  
55  
± 13  
37  
V
V
V
A
A
A
W
˚C  
Tmb = 25 ˚C  
Tmb = 100 ˚C  
Tmb = 25 ˚C  
Tmb = 25 ˚C  
26  
IDM  
PD  
Tj, Tstg  
Pulsed drain current  
Total power dissipation  
Operating junction and  
storage temperature  
148  
100  
175  
- 55  
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.  
September 1998  
1
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
THERMAL RESISTANCES  
SYMBOL PARAMETER  
CONDITIONS  
TYP.  
MAX.  
UNIT  
Rth j-mb  
Thermal resistance junction  
to mounting base  
-
1.5  
K/W  
Rth j-a  
Thermal resistance junction SOT78 package, in free air  
to ambient SOT404 and SOT428 packages, pcb  
60  
50  
-
-
K/W  
K/W  
mounted, minimum footprint  
ESD LIMITING VALUE  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VC  
Electrostatic discharge  
capacitor voltage, all pins  
Human body model (100 pF, 1.5 kΩ)  
-
2
kV  
ELECTRICAL CHARACTERISTICS  
Tj= 25˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
V(BR)DSS  
V(BR)GSS  
VGS(TO)  
Drain-source breakdown  
voltage  
Gate-source breakdown  
voltage  
VGS = 0 V; ID = 0.25 mA;  
55  
50  
10  
-
-
-
-
-
-
V
V
V
Tj = -55˚C  
IG = ±1 mA;  
Gate threshold voltage  
VDS = VGS; ID = 1 mA  
1.0  
0.5  
-
-
-
-
12  
-
-
-
1.5  
-
-
28  
26  
-
40  
0.02  
-
2.0  
-
2.3  
35  
32  
74  
-
V
V
V
Tj = 175˚C  
Tj = -55˚C  
RDS(ON)  
Drain-source on-state  
resistance  
VGS = 5 V; ID = 17 A  
VGS = 10 V; ID = 17 A  
mΩ  
mΩ  
mΩ  
S
µA  
µA  
µA  
µA  
Tj = 175˚C  
gfs  
IGSS  
Forward transconductance  
Gate source leakage current VGS = ±5 V; VDS = 0 V  
VDS = 25 V; ID = 15 A  
1
Tj = 175˚C  
Tj = 175˚C  
20  
10  
500  
IDSS  
Zero gate voltage drain  
current  
VDS = 55 V; VGS = 0 V;  
0.05  
-
-
Qg(tot)  
Qgs  
Qgd  
Total gate charge  
Gate-source charge  
Gate-drain (Miller) charge  
ID = 30 A; VDD = 44 V; VGS = 5 V  
-
-
-
22.5  
6
11  
-
-
-
nC  
nC  
nC  
td on  
tr  
td off  
tf  
Turn-on delay time  
Turn-on rise time  
Turn-off delay time  
Turn-off fall time  
VDD = 30 V; ID = 25 A;  
VGS = 5 V; RG = 10 Ω  
Resistive load  
-
-
-
-
14  
77  
55  
48  
21  
110  
80  
ns  
ns  
ns  
ns  
65  
Ld  
Ld  
Internal drain inductance  
Internal drain inductance  
Measured from tab to centre of die  
Measured from drain lead to centre of die  
(SOT78 package only)  
-
-
3.5  
4.5  
-
-
nH  
nH  
Ls  
Internal source inductance  
Measured from source lead to source  
bond pad  
-
7.5  
-
nH  
Ciss  
Coss  
Crss  
Input capacitance  
Output capacitance  
Feedback capacitance  
VGS = 0 V; VDS = 25 V; f = 1 MHz  
-
-
-
1050 1400  
pF  
pF  
pF  
205  
245  
150  
113  
September 1998  
2
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS  
Tj = 25˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
IS  
Continuous source current  
(body diode)  
Pulsed source current (body  
diode)  
Diode forward voltage  
-
-
-
-
37  
A
A
ISM  
VSD  
148  
IF = 25 A; VGS = 0 V  
IF = 34 A; VGS = 0 V  
-
-
0.95  
1.0  
1.2  
-
V
V
trr  
Qrr  
Reverse recovery time  
Reverse recovery charge  
IF = 34 A; -dIF/dt = 100 A/µs;  
VGS = -10 V; VR = 30 V  
-
-
40  
0.16  
-
-
ns  
µC  
AVALANCHE LIMITING VALUE  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
45  
UNIT  
WDSS  
Drain-source non-repetitive ID = 20 A; VDD ≤ 25 V; VGS = 5 V;  
unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C  
energy  
-
mJ  
Normalised Power Derating  
PD%  
Normalised Current Derating  
ID%  
120  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0
20  
40  
60  
80  
Tmb /  
100 120 140 160 180  
C
0
20  
40  
60  
80  
100 120 140 160 180  
Tmb /  
C
Fig.1. Normalised power dissipation.  
PD% = 100 PD/PD 25 ˚C = f(Tmb)  
Fig.2. Normalised continuous drain current.  
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V  
September 1998  
3
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
1000  
ID/A  
RDS(ON)/mOhm  
45  
VGS/V =  
4
4.2  
40  
tp =  
RDS(ON) = VDS/ID  
100  
4.4  
1 us  
10us  
4.6  
35  
4.8  
100 us  
5
DC  
10  
1 ms  
30  
10ms  
100ms  
1
25  
1
10  
100  
0
10  
20  
30  
40  
50  
60  
VDS/V  
ID/A  
Fig.3. Safe operating area. Tmb = 25 ˚C  
ID & IDM = f(VDS); IDM single pulse; parameter tp  
Fig.6. Typical on-state resistance, Tj = 25 ˚C.  
RDS(ON) = f(ID); parameter VGS  
ZTH/ (K/W)  
10  
70  
ID/A  
60  
50  
40  
30  
20  
10  
0
1
0.5  
0.2  
p
t
0.1  
t
p
P
D
D =  
T
0.05  
0.1  
t
T
0.02  
0
Tj/C =  
175  
25  
0.01  
1.0E-06  
0.0001  
0.01  
t/s  
1
100  
0
1
2
3
4
5
6
7
VGS/V  
Fig.4. Transient thermal impedance.  
Zth j-mb = f(t); parameter D = tp/T  
Fig.7. Typical transfer characteristics.  
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj  
Drain current, ID (A)  
Transconductance, gfs (S)  
30  
100  
80  
60  
40  
20  
0
10  
VGS = 6.0 V  
5.6  
7
25  
20  
15  
10  
5
5.0  
4.6  
4.0  
3.6  
3.0  
0
2
4
6
8
10  
0
10  
20  
30  
40  
50  
60  
70  
Drain-source voltage, VDS (V)  
Drain current, ID (A)  
Fig.5. Typical output characteristics, Tj = 25 ˚C.  
ID = f(VDS); parameter VGS  
Fig.8. Typical transconductance, Tj = 25 ˚C.  
gfs = f(ID); conditions: VDS = 25 V  
September 1998  
4
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
2.5  
2.0  
1.5  
Rds(on) normlised to 25degC  
a
2.5  
2
1.5  
1
Ciss  
1.0  
0.5  
0
hTounsadFp  
Coss  
Crss  
0.5  
-100  
-50  
0
50  
Tmb / degC  
100  
150  
200  
0.01  
0.1  
1
10  
100  
VDS/V  
Fig.9. Normalised drain-source on-state resistance.  
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 17 A; VGS = 5 V  
Fig.12. Typical capacitances, Ciss, Coss, Crss.  
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz  
6
VGS(TO) / V  
max.  
2.5  
2
VGS/V  
5
VDS = 14V  
4
3
2
1
0
typ.  
VDS = 44V  
1.5  
1
min.  
0.5  
0
-100  
-50  
0
50  
Tj / C  
100  
150  
200  
0
5
10  
15  
20  
25  
QG/nC  
Fig.10. Gate threshold voltage.  
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS  
Fig.13. Typical turn-on gate-charge characteristics.  
VGS = f(QG); conditions: ID = 30 A; parameter VDS  
100  
IF/A  
Sub-Threshold Conduction  
1E-01  
80  
1E-02  
1E-03  
1E-04  
1E-05  
1E-05  
60  
2%  
typ  
98%  
Tj/C =  
175  
25  
40  
20  
0
0
0.5  
1
1.5  
0
0.5  
1
1.5  
2
2.5  
3
VSDS/V  
Fig.11. Sub-threshold drain current.  
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS  
Fig.14. Typical reverse diode current.  
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj  
September 1998  
5
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
WDSS%  
120  
VDD  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
+
L
VDS  
-
VGS  
-ID/100  
T.U.T.  
0
R 01  
RGS  
shunt  
20  
40  
60  
80  
100  
120  
140  
160  
180  
Tmb /  
C
Fig.16. Avalanche energy test circuit.  
Fig.15. Normalised avalanche energy rating.  
WDSS% = f(Tmb); conditions: ID = 20 A  
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD  
)
September 1998  
6
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
MECHANICAL DATA  
Dimensions in mm  
Net Mass: 2 g  
4,5  
max  
10,3  
max  
1,3  
3,7  
2,8  
5,9  
min  
15,8  
max  
3,0 max  
not tinned  
3,0  
13,5  
min  
1,3  
1 2 3  
max  
(2x)  
0,9 max (3x)  
0,6  
2,4  
2,54 2,54  
Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base.  
Notes  
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent  
damage to MOS gate oxide.  
2. Refer to mounting instructions for SOT78 (TO220) envelopes.  
3. Epoxy meets UL94 V0 at 1/8".  
September 1998  
7
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
MECHANICAL DATA  
Dimensions in mm  
Net Mass: 1.4 g  
4.5 max  
1.4 max  
10.3 max  
11 max  
15.4  
2.5  
0.85 max  
0.5  
(x2)  
2.54 (x2)  
Fig.18. SOT404 : centre pin connected to mounting base.  
MOUNTING INSTRUCTIONS  
Dimensions in mm  
11.5  
9.0  
17.5  
2.0  
3.8  
5.08  
Fig.19. SOT404 : soldering pattern for surface mounting.  
Notes  
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent  
damage to MOS gate oxide.  
2. Epoxy meets UL94 V0 at 1/8".  
September 1998  
8
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
MECHANICAL DATA  
Dimensions in mm : Net Mass: 1.4 g  
seating plane  
1.1  
2.38 max  
0.93 max  
5.4  
6.73 max  
tab  
4 min  
6.22 max  
0.5 min  
10.4 max  
4.6  
0.5  
2
0.3  
0.5  
3
1
0.8 max  
(x2)  
2.285 (x2)  
Fig.20. SOT428 : centre pin connected to mounting base.  
MOUNTING INSTRUCTIONS  
Dimensions in mm  
7.0  
7.0  
2.15  
2.5  
1.5  
4.57  
Fig.21. SOT428 : soldering pattern for surface mounting.  
Notes  
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent  
damage to MOS gate oxide.  
2. Epoxy meets UL94 V0 at 1/8".  
September 1998  
9
Rev 1.400  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Logic level FET  
PHP37N06LT, PHB37N06LT, PHD37N06LT  
DEFINITIONS  
Data sheet status  
Objective specification  
This data sheet contains target or goal specifications for product development.  
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.  
Product specification  
This data sheet contains final product specifications.  
Limiting values  
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and  
operation of the device at these or at any other conditions above those given in the Characteristics sections of  
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
Philips Electronics N.V. 1998  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the  
copyright owner.  
The information presented in this document does not form part of any quotation or contract, it is believed to be  
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any  
consequence of its use. Publication thereof does not convey nor imply any license under patent or other  
industrial or intellectual property rights.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices or systems where malfunction of these  
products can be reasonably expected to result in personal injury. Philips customers using or selling these products  
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting  
from such improper use or sale.  
September 1998  
10  
Rev 1.400  
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N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very  
low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.  
PC/PC-peripherals  
The PHP37N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.  
The PHB37N06LT is supplied in the SOT404 surface mounting package.  
The PHD37N06LT is supplied in the SOT428 surface mounting package.  
Cross reference  
Models  
Packages  
Application notes  
Selection guides  
Other technical documentation  
End of Life information  
Datahandbook system  
Features  
l ’Trench’ technology  
l Very low on-state resistance  
l Fast switching  
l Stable off-state characteristics  
l High thermal cycling performance  
l Low thermal resistance  
Relevant Links  
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Datasheet  
PHP37N06LT,  
PHB37N06LT, PHD37N06LT  
PHP37N06LT,  
PHB37N06LT, PHD37N06LT  
File  
size  
(kB)  
Publication  
release date Datasheet status  
Page  
count  
Type nr.  
Title  
Datasheet  
Download  
PHP37N06LT,  
PHB37N06LT,  
PHD37N06LT  
01-Sep-98  
Product  
Specification  
10  
79  
TrenchMOSÔ transistor Logic level  
FET  
Products, packages, availability and ordering  
North American  
Partnumber  
Order code  
(12nc)  
Partnumber  
marking/packing  
package device status buy online  
SOT404 Full production  
Standard Marking * Reel Pack,  
SMD, 13"  
PHB37N06LT PHB37N06LT T/R  
PHD37N06LT PHD37N06LT /T3  
PHP37N06LT PHP37N06LT  
9340 545 30118  
Standard Marking * Reel Pack,  
SMD, 13"  
9340 553 50118  
9340 545 20127  
SOT428 Full production  
Standard Marking * Horizontal,  
Rail Pack  
SOT78 Full production  
Find similar products:  
PHP37N06LT, PHB37N06LT, PHD37N06LT links to the similar products page containing an overview of products that are similar in  
function or related to the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) ,  
relevant selection guides and products from the same functional category.  
Copyright © 2000  
Royal Philips Electronics  
All rights reserved.  
Terms and conditions.  

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