PHB24N03LT [NXP]

TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管


型号：	PHB24N03LT
厂家：	NXP
描述：	TrenchMOS transistor Logic level FET 的TrenchMOS晶体管逻辑电平场效应管晶体晶体管
文件：	总6页 (文件大小：58K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP24N03LT, PHB24N03LT

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

• Fast switching

• Stable off-state characteristics

• High thermal cycling performance

• Low thermal resistance

V_DSS= 30 V

I_D= 24 A

_DS(ON)≤ 56 mΩ (V_GS= 5 V)

_DS(ON)≤ 50 mΩ (V_GS= 10 V)

GENERAL DESCRIPTION

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.

The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching

applications.

The PHP24N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB24N03LT is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404

DESCRIPTION

tab

gate

drain¹

source

drain

tab

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

I_D

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Continuous drain current

T_j= 25 ˚C to 175˚C

T_j= 25 ˚C to 175˚C; R_GS= 20 kΩ

± 13

˚C

T_mb= 25 ˚C; V_GS= 5 V

T_mb= 100 ˚C; V_GS= 5 V

T_mb= 25 ˚C

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

T_mb= 25 ˚C

175

- 55

1 It is not possible to make connection to pin 2 of the SOT404 package.

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP24N03LT, PHB24N03LT

ESD LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_C

Electrostatic discharge

capacitor voltage, all pins

Human body model (100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

Thermal resistance junction

to mounting base

2.5

K/W

R_{th j-a}

Thermal resistance junction SOT78 package, in free air

to ambient SOT404 package, pcb mounted, minimum

footprint

K/W

ELECTRICAL CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

V_(BR)GSS

V_GS(TO)

Drain-source breakdown

voltage

Gate-source breakdown

voltage

Gate threshold voltage

V_GS= 0 V; I_D= 0.25 mA;

T_j= -55˚C

I_G= 1 mA

V_DS= V_GS; I_D= 1 mA

0.5

1.5

0.02

0.05

2.3

104

T_j= 175˚C

T_j= -55˚C

R_DS(ON)

Drain-source on-state

resistance

V_GS= 5 V; I_D= 25 A

V_GS= 10 V; I_D= 25 A

V_GS= 5 V; I_D= 12 A; T_j= 175˚C

V_DS= 25 V; I_D= 12 A

mΩ

µA

g_fs

I_GSS

Forward transconductance

Gate-source leakage current V_GS= ±5 V; V_DS= 0 V;

T_j= 175˚C

500

I_DSS

Zero gate voltage drain

current

V_DS= 30 V; V_GS= 0 V;

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 10 A; V_DD= 30 V; V_GS= 5 V

2.3

5.4

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 30 V; I_D= 25 A;

V_GS= 5 V; R_G= 10 Ω

Resistive load

L_d

Internal drain inductance

Measured tab to centre of die

Measured from drain lead to centre of die

(SOT78 package only)

3.5

4.5

L_s

Internal source inductance

Measured from source lead to source

bond pad

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

460

144

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP24N03LT, PHB24N03LT

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

(body diode)

Pulsed source current (body

diode)

Diode forward voltage

I_SM

V_SD

I_F= 25 A; V_GS= 0 V

1.05

1.5

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= 12 A; -dI_F/dt = 100 A/µs;

V_GS= -10 V; V_R= 25 V

0.1

µC

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

W_DSS

Drain-source non-repetitive I_D= 12 A; V_DD≤ 15 V;

unclamped inductive turn-off V_GS= 5 V; R_GS= 50 Ω; T_mb= 25 ˚C

energy

Normalised Power Derating

PD%

Normalised Current Derating

ID%

120

110

100

110

100

Tmb /

100 120 140 160 180

Tmb /

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 5 V

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP24N03LT, PHB24N03LT

PHP24N03LT

RDS(on), Drain-Source on resistance (Ohms)

PHP24N03T

ID, Drain current (Amps)

100

0.12

0.1

3 V

VGS = 2.5 V

10 us

0.08

0.06

0.04

0.02

100 us

3.5 V

5 V

1 ms

15 V

10 ms

Tmb = 25 C

Tj = 25 C

VDS, Drain-source voltage (Volts)

100

ID, Drain current (Amps)

Fig.3. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance, T_j= 25 ˚C.

R_DS(ON)= f(I_D); parameter V_GS

Transient thermal impedance, Zth j-mb (K/W) PHP24N03T

Drain current, ID (A)

VDS = 25 V

PHP24N03LT

D =

0.5

0.2

0.1

0.05

0.1

0.02

D =

Tj = 25 C

175 C

0.01

1us 10us 100us 1ms 10ms 0.1s

pulse width, tp (s)

10s

Gate-source voltage, VGS (V)

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Fig.7. Typical transfer characteristics.

I_D= f(V_GS); parameter T_j

PHP24N03LT

3.5 V

PHP24N03LT

ID, Drain current (Amps)

Transconductance, gfs (S)

VDS = 25 V

5 V

15 V

Tj = 25 C

175 C

3 V

VGS = 2.5 V

Tj = 25 C

Drain current, ID (A)

VDS, Drain-Source voltage (Volts)

Fig.5. Typical output characteristics, T_j= 25 ˚C.

I_D= f(V_DS); parameter V_GS

Fig.8. Typical transconductance, T_j= 25 ˚C.

g_fs= f(I_D)

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP24N03LT, PHB24N03LT

Capacitances Ciss, Coss, Crss (pF)

PHP24N03LT

30V TrenchMOS

1000

100

Ciss

1.5

Coss

Crss

0.5

Tj = 25 C

-100

100

200

100

1000

-50

Tj / C

150

Drain-source voltage, VDS (V)

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j); I_D= 12 A; V_GS= 5 V

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

BUK959-60

VGS(TO) / V

max.

VGS, Gate-Source voltage (Volts)

PHP24N03LT

2.5

VDD = 30 V

ID = 10 A

Tj = 25 C

typ.

1.5

min.

0.5

-100

-50

Tj / C

100

150

200

Qg, Gate charge (nC)

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G); parameter V_DS

Sub-Threshold Conduction

PHP24N03LT

Source-Drain diode current, IF(A)

VGS = 0 V

1E-01

1E-02

1E-03

1E-04

1E-05

typ

98%

175 C

Tj = 25 C

0.2

0.4

0.6

0.8

1.2

1.4

Source-Drain voltage, VSDS (V)

0.5

1.5

2.5

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Fig.14. Typical reverse diode current.

I_F= f(V_SDS); parameter T_j

January 1998

Rev 1.300

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP24N03LT, PHB24N03LT

WDSS%

120

VDD

110

100

VDS

VGS

-ID/100

T.U.T.

R 01

RGS

shunt

100

120

140

160

180

Tmb /

Fig.16. Avalanche energy test circuit.

Fig.15. Normalised avalanche energy rating.

W_DSS% = f(T_mb)

W_DSS= 0.5 LI_D²BV_DSS/(BV_DSS− V_DD

)

January 1998

Rev 1.300

PHB24N03LT [NXP]

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