PCA9518AD_技术文档

PCA9518A

Expandable 5-channel I²C-bus hub

Rev. 03 — 3 December 2008

Product data sheet

1. General description

The PCA9518A is a CMOS integrated circuit intended for application in I²C-bus and

SMBus systems.

While retaining all the operating modes and features of the I²C-bus system, it permits

extension of the I²C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus

enabling virtually an unlimited number of buses of 400 pF.

The I²C-bus capacitance limit of 400 pF restricts the number of devices and bus length.

Using the PCA9518A enables the system designer to divide the bus into an unlimited

number of segments off of a hub where any segment to segment transition sees only one

repeater delay and is multiple master capable on each segment.

Using multiple PCA9518A parts, any width hub (in multiples of ﬁve)¹can be implemented

using the expansion pins.

The PCA9518A is a wider voltage range (2.3 V to 3.6 V) version of the PCA9518 and also

improves partial power-down performance, keeping I²C-bus I/O pins in high-impedance

state when V_DDis below 2.0 V.

A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another

PCA9518 cluster. Multiple PCA9518 devices can be grouped with other PCA9518

devices into any size cluster thanks to the EXPxxxn pins that allow the I²C-bus signals to

be sent/received from/to one PCA9518 to/from another PCA9518 within the cluster. Since

there is no direction pin, slightly different ‘legal’ low voltage levels are used to avoid

lock-up conditions between the input and the output of individual repeaters in the cluster.

A ‘regular LOW’ applied at the input of any of the PCA9518 devices will then be

propagated as a ‘buffered LOW’ with a slightly higher LOW value to all enabled outputs in

the PCA9518 cluster. When this ‘buffered LOW’ is applied to a PCA9515 and PCA9516 or

separate PCA9518 cluster (not connected via the EXPxxxn pins) in series, the second

PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a ‘regular LOW’ and

will not propagate it as a ‘buffered LOW’ again. The PCA9510/9511/9513/9514 and

PCA9512 cannot be used in series with the PCA9515 and PCA9516 or PCA9518 either,

but can be used in series with themselves since they use shifting instead of static offsets

to avoid lock-up conditions. This note is applicable to the ‘A’ versions of these devices

also.

1. Only four ports per device are available if individual Enable is required.

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

2. Features

I Expandable 5 channel, bidirectional buffer

I I²C-bus and SMBus compatible

I Active HIGH individual repeater enable inputs

I Open-drain input/outputs

I Lock-up free operation

I Supports arbitration and clock stretching across the repeater

I Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple masters

I Powered-off high-impedance I²C-bus pins

I Operating supply voltage range of 2.3 V to 3.6 V

I 5 V tolerant I²C-bus and enable pins

I 0 Hz to 400 kHz clock frequency²

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

I Package offerings: SO20 and TSSOP20

3. Ordering information

Table 1.

Ordering information

T_amb= −40 °C to +85 °C

Type number

Topside mark Package

Name

Description

Version

PCA9518AD

PA9518A

SO20

plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

SOT360-1

PCA9518APW

TSSOP20

plastic thin shrink small outline package; 20 leads;

body width 4.4 mm

2. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

2 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

4. Block diagram

V

DD

EXPSCL1

EXPSCL2

PCA9518A

SCL0

SCL1

SCL2

BUFFER

SCL4

HUB

LOGIC

SCL3

EXPSDA1

EXPSDA2

SDA0

SDA1

SDA2

BUFFER

SDA4

SDA3

HUB

LOGIC

EN1

EN2

EN4

EN3

002aac530

V

SS

Fig 1. Block diagram of PCA9518A

A more detailed view of Figure 1 buffer is shown in Figure 2.

to output

data

in

inc

enable

002aac531

Fig 2. Buffer detail

The output pull-down voltage of each internal buffer is set for approximately 0.5 V, while

the input threshold of each internal buffer is set about 0.07 V lower, when the output is

internally driven LOW. This prevents a lock-up condition from occurring.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

3 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

5. Pinning information

5.1 Pinning

1

2

20

19

18

17

16

15

14

13

12

11

1

2

20

19

18

17

16

15

14

13

12

11

EXPSCL1

EXPSCL2

SCL0

V

EXPSCL1

EXPSCL2

SCL0

V

DD

EXPSDA2

EXPSDA1

EN4

EXPSDA2

EXPSDA1

EN4

3

4

SDA0

5

SCL1

SDA4

SCL4

SCL1

SDA4

SCL4

PCA9518AD

PCA9518APW

6

SDA1

7

EN1

EN3

EN1

EN3

8

SCL2

SDA3

SCL3

SCL2

SDA3

SCL3

9

SDA2

10

SS

V

SS

EN2

V

EN2

002aac528

002aac529

Fig 3. Pin conﬁguration for SO20

Fig 4. Pin conﬁguration for TSSOP20

5.2 Pin description

Table 2.

Pin description

Symbol

EXPSCL1

EXPSCL2

SCL0

1

Description

expandable serial clock pin 1

expandable serial clock pin 2

serial clock bus 0

2

3

SDA0

SCL1

4

serial data bus 0

5

serial clock bus 1

SDA1

EN1

6

serial data bus 1

7

active HIGH bus 1 enable input

serial clock bus 2

SCL2

8

SDA2

V_SS

9

serial data bus 2

10

11

12

13

14

15

16

17

18

19

20

supply ground

EN2

active HIGH bus 2 enable input

serial clock bus 3

SCL3

SDA3

EN3

serial data bus 3

active HIGH bus 3 enable input

serial clock bus 4

SCL4

SDA4

EN4

serial data bus 4

active HIGH bus 4 enable input

expandable serial data pin 1

expandable serial data pin 2

supply voltage

EXPSDA1

EXPSDA2

V_DD

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

4 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

6. Functional description

The PCA9518A CMOS integrated circuit is a ﬁve-way hub repeater, which enables

I²C-bus and similar bus systems to be expanded in increments of ﬁve with only one

repeater delay and no functional degradation of system performance.

The PCA9518A CMOS integrated circuit contains ﬁve multi-directional, open-drain buffers

speciﬁcally designed to support the standard low-level contention arbitration of the

I²C-bus. Except during arbitration or clock stretching, the PCA9518A acts like a pair of

non-inverting, open-drain buffers, one for SDA and one for SCL.

Refer to Figure 1 “Block diagram of PCA9518A”.

6.1 Enable

The enable pins EN1 through EN4 are active HIGH and have internal pull-up resistors.

Each enable pin ENn controls its associated SDAn and SCLn ports. When LOW, the ENn

pin blocks the inputs from SDAn and SCLn, as well as disabling the output drivers on the

SDAn and SCLn pins. The enable pins should only change state when both the global bus

and the local port are in an idle state to prevent system failures.

The active HIGH enable pins allow the use of open-drain drivers which can be wire-ORed

to create a distributed enable where either centralized control signal (master) or spoke

signal (sub-master) can enable the channel when it is idle.

Unused channels must have pull-up resistors unless their enable pin (ENn) is always

LOW. Port 0 must always have pull-up resistors since it is always present in the bus and

cannot be disabled.

6.2 Expansion

The PCA9518A includes 4 open-drain I/O pins used for expansion. Two expansion pins,

EXPSDA1 and EXPSDA2 are used to communicate the internal state of the serial data

within each hub to the other hubs. The EXPSDA1 pins of all hubs are connected together

to form an open-drain bus. Similarly, all EXPSDA2 pins, EXPSCL1 pins, and all EXPSCL2

pins are connected together forming a 4-wire bus between hubs.

When it is necessary to be able to deselect every port, each expansion device only

contributes 4 ports which can be enabled or disables because the ﬁfth does not have an

enable pin.

Pull-up resistors are required on the EXPxxxn³pins even if only one PCA9518A is used.

6.3 I²C-bus systems

As with the standard I²C-bus system, pull-up resistors are required to provide the logic

HIGH levels on the buffered bus. (Standard open-collector or open-drain conﬁguration of

the I²C-bus). The size of these pull-up resistors depends on the system, but each side of

the repeater must have a pull-up resistor. This part is designed to work with

Standard-mode (0 Hz to 100 kHz) and Fast-mode (0 Hz to 400 kHz) I²C-bus devices in

addition to SMBus devices. Standard-mode I²C-bus devices only specify 3 mA output

drive; this limits the termination current to 3 mA in a generic I²C-bus system where

3. ‘xxxn’ is SDA1, SDA2, SCL1 or SCL2. ‘xxx’ is SDA or SCL.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

5 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

Standard-mode devices and multiple masters are possible. Please see application note

AN255, I²C/SMBus Repeaters, Hubs and Expanders for additional information on sizing

resistors.

7. Application design-in information

A typical application is shown in Figure 5. In this example, the system master is running

on a 3.3 V I²C-bus while the slaves are connected to a 3.3 V or 5 V bus. All buses run at

100 kHz unless slave 3, slave 4 and slave 5 are isolated from the bus. Then the master

bus and slave 1, slave 2 and slave 6 can run at 400 kHz.

Any segment of the hub can talk to any other segment of the hub. Bus masters and slaves

can be located on any segment with 400 pF load allowed on each segment.

The PCA9518A is 5 V tolerant, so it does not require any additional circuitry to translate

between the different bus voltages.

When one port of the PCA9518A is pulled LOW by a device on the I²C-bus, a CMOS

hysteresis type input detects the falling edge and drives the EXPxxx1 line LOW, when the

EXPxxx1 voltage is less than 0.5V_DD, the other ports are pulled down to the V_OLof the

PCA9518A which is typically 0.5 V.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

6 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

5 V

3.3 V

5 V

V

DD

SDA

SCL

SUBSYSTEM 5

100 kHz

SDA1

EXPSDA1

EXPSDA2

EXPSCL1

EXPSCL2

SDA1

SCL1

SDA

SCL

SUBSYSTEM 1

400 kHz

SCL1

EXPSDA2

EXPSCL1

EXPSCL2

3.3 V

SDA

SCL

SUBSYSTEM 6

400 kHz

SDA2

SCL2

SDA2

SCL2

SDA

SCL

SUBSYSTEM 2

400 kHz

SDA0

SCL0

SDA

SCL

SDA0

SCL0

3.3 V

or 5 V

5 V

PCA9518A

DEVICE 2

DEVICE 1

BUS

MASTER

SDA3

SDA

SCL

SUBSYSTEM 3

100 kHz

SCL3

400 kHz

3.3 V

EN1

EN2

EN3

EN4

EN1

EN2

EN3

EN4

or 5 V

3.3 V

disabled;

not connected

SDA4

SCL4

SDA4

SCL4

SDA

SCL

SUBSYSTEM 4

100 kHz

V

SS

002aac535

Only two of the ﬁve channels on the PCA9518A Device 2 are being used. EN3 and EN4 are connected to V_SSto disable

channels 3 and 4 and/or SDA3/SCL3 and SDA4/SCL4 are pulled up to V_DD. SDA0 and SCL0 can be used as a normal I²C-bus

port, but if unused then it must be pulled up to V_DDsince there is no enable pin.

The pull-ups shown on Device 2 channels 3 and 4 are not required if their enable pins (ENn) are permanently held LOW.

Fig 5. Typical application: multiple expandable 5-channel I²C-bus hubs

In order to illustrate what would be seen in a typical application, refer to Figure 6. If the

bus master in Figure 5 were to write to the slave through the PCA9518A, we would see

the waveform shown in Figure 6. This looks like a normal I²C-bus transmission except for

the small foot preceding each clock LOW-to-HIGH transition and proceeding each data

LOW-to-HIGH transition for the master. The foot height is the difference between the LOW

level driven by the master and the higher voltage LOW level driven by the PCA9518A

repeater. Its width corresponds to an effective clock stretching coming from the

PCA9518A that delays the rising edge of the clock. That same magnitude of delay is seen

on the rising edge of the data. The foot on the rising edge of the data is extended through

the 9^thclock pulse as the PCA9518A repeats the acknowledge from the slave to the

master. The clock of the slave looks normal except the V_OLis the ~0.5 V level generated

by the PCA9518A. The SDA at the slave has a particularly interesting shape during the 9^th

clock cycle where the slave pulls the line below the value driven by the PCA9518A during

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

7 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

the acknowledge and then returns to the PCA9518A level creating a foot before it

completes the LOW-to-HIGH transition. SDA lines other than the one with the master and

the one with the slave have a uniform LOW level driven by the PCA9518A repeater.

The other four waveforms are the expansion bus signals and are included primarily for

timing reference points. All timing on the expansion bus is with respect to 0.5V_DD

.

EXPSDA1 is the expansion bus that is driven LOW whenever any SDA pin falls below

0.3V_DD. EXPSDA2 is the expansion bus that is driven LOW whenever any pin is ≤0.4 V.

EXPSCL1 is the expansion bus that is driven LOW whenever any SCL pin falls below

0.3V_DD. EXPSCL2 is the expansion bus that is driven LOW whenever any SCL pin is

≤0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the last one being held

below 0.4 V by an external driver starts to rise. The last SDA to rise above 0.4 V is held

down by the PCA9518A to ~0.5 V until after the delay of the circuit which determines that

it was the last to rise, then it is allowed to rise above the ~0.5 V level driven by the

PCA9518A. Considering the bus 0 SDA to be the last one to go above 0.4 V, then the

EXPSDA1 returns to HIGH after the EXPSDA2 is HIGH and either the bus 0 SDA rise time

is 1 µs or, when the bus 0 SDA reaches 0.7V_DD, whichever occurs ﬁrst. After both

EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines are allowed to rise. The

same description applies for the EXPSCL1, EXPSCL2, and SCL pins.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

8 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

th

9

clock cycle

9

clock cycle

V

of master

V

of PCA9518A

OL

SCL of

master

Bus 0

t

stretch

SDA of

master

t

PHL1

EXPSDA1

t

, t

PLH2 PLH1

t

PHL2

PLH2

EXPSDA2

EXPSCL1

EXPSCL2

expansion

bus

SCL of

slave

Bus 1

V

of slave

V

of PCA9518A

OL

SDA of

slave

t

PLH

PHL

Bus n

with n > 1

002aac534

Fig 6. Bus waveforms

It is important to note that any arbitration or clock stretching events on Bus 1 require that

the V_OLof the devices on Bus 1 be 70 mV below the V_OLof the PCA9518A (see V_OL−V_ILc

in the Section 9 “Static characteristics”) to be recognized by the PCA9518A and then

transmitted to Bus 0.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

9 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

8. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

V_DDto V_SS

SCL or SDA

any pin

Min

−0.5

-

Max

+6

Unit

V

[1]

supply voltage

I²C-bus voltage

V_I2C-bus

I_I

+6

V

input current

50

mA

mW

°C

P_tot

total power dissipation

storage temperature

ambient temperature

-

300

+125

+85

T_stg

−55

−40

T_amb

operating

°C

[1] Voltages with respect to pin V_SS

.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

10 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

9. Static characteristics

Table 4.

Static characteristics

V_DD= 3.0 V to 3.6 V^[1]; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Supplies

Conditions

Min

Typ

Max

Unit

V_DD

I_CCH

supply voltage

3.0

-

3.3

7.5

3.6

10

V

HIGH-level supply current

both channels HIGH

mA

V_DD= 3.6 V;

SDAn = SCLn = V_DD

I_CCL

LOW-level supply current

both channels LOW

-

9

11

mA

V_DD= 3.6 V;

one SDA and one SCL = V_SS

other SDA and SCL open

;

I_CCLc

contention LOW-level supply current V_DD= 3.6 V;

SDAn = SCLn = V_SS

Input SCL; input/output SDA

V_IH

V_IL

V_ILc

V_IK

I_LI

HIGH-level input voltage

LOW-level input voltage

SCL, SDA

0.7V_DD

-

5.5

V

[2]

[3]

−0.5

-

+0.25V_DD

+0.4

−1.2

±1

V

contention LOW-level input voltage SCL, SDA

−0.5

-

V

input clamping voltage

input leakage current

LOW-level input current

LOW-level output voltage

I_I= −18 mA

-

V

V_I= 3.6 V

-

µA

V

I_IL

SCL, SDA; V_I= 0.2 V

I_OL= 20 µA or 6 mA

guaranteed by design

-

20

V_OL

0.45

-

0.52

-

0.6

V

_OL−V_ILcdifference between LOW-level

output and LOW-level input voltage

contention

70

mV

C_iinput capacitance

Enable 1 to Enable 4 (EN1 to EN4)

V_I= 3 V or 0 V

-

6

8

pF

V_IH

V_IL

I_IL

HIGH-level input voltage

LOW-level input voltage

LOW-level input current

input leakage current

input capacitance

2.0

−0.5

-

5.5

+0.8

30

V

-

V

V_I= 0.2 V; EN1 to EN4

V_I= 3.0 V or 0 V

10

-

µA

pF

I_LI

−1

-

+1

7

C_i

3

Expansion pins (EXPSCL1, EXPSCL2, EXPSDA1, EXPSDA2)

V_IH

V_IL

I_IL

HIGH-level input voltage

LOW-level input voltage

LOW-level input current

LOW-level output voltage

input capacitance

EXPxxxn

0.6V_DD

-

5.5

V

EXPxxxn

−0.5

-

+0.4V_DD

V

V_I= 0.2 V; EXPxxxn

I_OL= 12 mA

-

5

µA

V

V_OL

C_i

-

0.5

8

V_I= 3.0 V or 0 V

6

pF

[1] For operation between published voltage ranges, refer to worst-case parameter in both ranges.

[2] V_ILspeciﬁcation is for the ﬁrst LOW level seen by the SDAn/SCLn lines.

[3] V_ILcis for the second and subsequent LOW levels seen by the SDAn/SCLn lines.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

11 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

Table 5.

Static characteristics

V_DD= 2.3 V to 2.7 V^[1]; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Supplies

Conditions

Min

Typ

Max

Unit

V_DD

I_CCH

supply voltage

2.3

-

2.5

7.5

2.7

10

V

HIGH-level supply current

both channels HIGH

mA

V_DD= 2.7 V;

SDAn = SCLn = V_DD

I_CCL

LOW-level supply current

both channels LOW

-

9

11

mA

V_DD= 2.7 V;

one SDA and one SCL = V_SS

other SDA and SCL open

;

I_CCLc

contention LOW-level supply current V_DD= 2.7 V;

SDAn = SCLn = V_SS

Input SCL; input/output SDA

V_IH

V_IL

V_ILc

V_IK

I_LI

HIGH-level input voltage

LOW-level input voltage

SCL, SDA

0.7V_DD

-

5.5

V

[2]

[3]

−0.5

-

+0.25V_DD

+0.4

−1.2

±1

V

contention LOW-level input voltage SCL, SDA

−0.5

-

V

input clamping voltage

input leakage current

LOW-level input current

LOW-level output voltage

I_I= −18 mA

-

V

V_I= 2.7 V

-

µA

V

I_IL

SCL, SDA; V_I= 0.2 V

I_OL= 20 µA or 6 mA

guaranteed by design

-

20

V_OL

0.45

-

0.52

-

0.6

V

_OL−V_ILcdifference between LOW-level

output and LOW-level input voltage

contention

70

mV

C_iinput capacitance

Enable 1 to Enable 4 (EN1 to EN4)

V_I= 3 V or 0 V

-

6

8

pF

V_IH

V_IL

I_IL

HIGH-level input voltage

LOW-level input voltage

LOW-level input current

input leakage current

input capacitance

2.0

−0.5

-

5.5

+0.8

30

V

-

V

V_I= 0.2 V; EN1 to EN4

V_I= 2.3 V or 0 V

10

-

µA

pF

I_LI

−1

-

+1

7

C_i

3

Expansion pins (EXPSCL1, EXPSCL2, EXPSDA1, EXPSDA2)

V_IH

V_IL

I_IL

HIGH-level input voltage

LOW-level input voltage

LOW-level input current

LOW-level output voltage

input capacitance

EXPxxxn

0.6V_DD

-

5.5

V

EXPxxxn

−0.5

-

+0.4V_DD

V

V_I= 0.2 V; EXPxxxn

I_OL= 12 mA

-

5

µA

V

V_OL

C_i

-

0.5

8

V_I= 2.3 V or 0 V

6

pF

[1] For operation between published voltage ranges, refer to worst-case parameter in both ranges.

[2] V_ILspeciﬁcation is for the ﬁrst LOW level seen by the SDAn/SCLn lines.

[3] V_ILcis for the second and subsequent LOW levels seen by the SDAn/SCLn lines.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

12 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

10. Dynamic characteristics

Table 6.

Dynamic characteristics

V_DD= 3.0 V to 3.6 V^[1]; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[2][3]

[2][4]

t_PHL

HIGH to LOW propagation delay

SDA to SDAn, or

SCL to SCLn; Figure 7

105

202

389

ns

t_PLH

LOW to HIGH propagation delay

HIGH to LOW propagation delay 1

LOW to HIGH propagation delay 1

LOW to HIGH propagation delay 2

SDA to SDAn, or

SCL to SCLn; Figure 7

110

109

130

160

259

193

153

234

265

327

179

279

ns

t_PHL1

t_PLH1

t_PLH2

EXPSDA1 to SDA, or

EXPSCL1 to SCL; Figure 7

EXPSDA1 to SDA, or

EXPSCL1 to SCL; Figure 7

EXPSDA2 to SDA, or

EXPSCL2 to SCL; Figure 7

t_THL

t_TLH

t_su

HIGH to LOW output transition time

LOW to HIGH output transition time

set-up time

SDA, SCL; Figure 7

58

-

110

187

ns

SDA, SCL; Figure 7

0.85 RC

-

enable to START condition

enable after STOP condition

300

-

t_h

hold time

[1] For operation between published voltage ranges, refer to worst-case parameter in both ranges.

[2] The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are

only sensitive to load capacitance. The rise times are RC time constant controlled and therefor a speciﬁc numerical value can only be

given for ﬁxed RC time constants.

[3] The SDA HIGH to LOW propagation delay includes the fall time from V_DDto 0.5V_DDof the EXPSDA1 or EXPSCL1 pins and the SDA or

SCL fall time from the quiescent HIGH (usually V_DD) to below 0.3V_DD. The SDA and SCL outputs have edge rate control circuits

included which make the fall time almost independent of load capacitance.

[4] The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5V_DDfor the EXPSDA1

or EXPSCL2, the rise time constant for the quiescent LOW to 0.5V_DDfor the EXPSDA1 or EXPSCL1, and the rise time constant from

the quiescent external driven LOW to 0.7V_DDfor the SDA or SCL output. All of these rise times are RC time constants determined by the

external resistance and total capacitance for the various nodes.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

13 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

Table 7.

Dynamic characteristics

V_DD= 2.3 V to 2.7 V^[1]; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[2][3]

[2][4]

t_PHL

HIGH to LOW propagation delay

SDA to SDAn, or

SCL to SCLn; Figure 7

105

202

389

ns

t_PLH

LOW to HIGH propagation delay

HIGH to LOW propagation delay 1

LOW to HIGH propagation delay 1

LOW to HIGH propagation delay 2

SDA to SDAn, or

SCL to SCLn; Figure 7

110

109

130

160

259

193

153

234

265

327

179

279

ns

t_PHL1

t_PLH1

t_PLH2

EXPSDA1 to SDA, or

EXPSCL1 to SCL; Figure 7

EXPSDA1 to SDA, or

EXPSCL1 to SCL; Figure 7

EXPSDA2 to SDA, or

EXPSCL2 to SCL; Figure 7

t_THL

t_TLH

t_su

HIGH to LOW output transition time

LOW to HIGH output transition time

set-up time

SDA, SCL; Figure 7

58

-

110

187

ns

SDA, SCL; Figure 7

0.85 RC

-

enable to START condition

enable after STOP condition

300

-

t_h

hold time

[1] For operation between published voltage ranges, refer to worst-case parameter in both ranges.

[2] The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are

only sensitive to load capacitance. The rise times are RC time constant controlled and therefor a speciﬁc numerical value can only be

given for ﬁxed RC time constants.

[3] The SDA HIGH to LOW propagation delay includes the fall time from V_DDto 0.5V_DDof the EXPSDA1 or EXPSCL1 pins and the SDA or

SCL fall time from the quiescent HIGH (usually V_DD) to below 0.3V_DD. The SDA and SCL outputs have edge rate control circuits

included which make the fall time almost independent of load capacitance.

[4] The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5V_DDfor the EXPSDA1

or EXPSCL2, the rise time constant for the quiescent LOW to 0.5V_DDfor the EXPSDA1 or EXPSCL1, and the rise time constant from

the quiescent external driven LOW to 0.7V_DDfor the SDA or SCL output. All of these rise times are RC time constants determined by the

external resistance and total capacitance for the various nodes.

t

TLH

THL

0.7V

DD

0.7V

DD

0.3V

input SDA or SCL

DD

0.3V

DD

0.4 V

effective

stretch

t

PHL

t

PHL1

EXPSDA1 or EXPSCL1

EXPSDA2 or EXPSCL2

0.5V

PHL2

0.5V

DD

t

PLH2

0.5V

DD

t

PLH

t

PLH1

PLH2

t

PHL1

0.7V

t

TLH

t

THL

DD

0.7V

DD

output SDA or SCL

0.3V

DD

0.52 V

002aac533

Fig 7. AC waveforms

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

14 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

11. Test information

V

DD

V

DD

R

L

V

O

I

PULSE

GENERATOR

DUT

C

L

R

T

002aac532

R_L= load resistor; 1.1 kΩ for I²C-bus, and 500 Ω for EXPxxxn.

C_L= load capacitance includes jig and probe capacitance; 100 pF for I²C-bus, and 100 pF for

EXPxxxn.

R_T= termination resistance should be equal to Z_oof the pulse generators.

Fig 8. Test circuit for open-drain outputs

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

15 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

12. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25

0.01

0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 9. Package outline SOT163-1 (SO20)

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

16 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 10. Package outline SOT360-1 (TSSOP20)

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

17 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

18 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 11) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 8 and 9

Table 8.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

≥ 350

220

< 2.5

235

220

≥ 2.5

220

Table 9.

Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 11.

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

19 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 11. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

14. Abbreviations

Table 10. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged-Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

I/O

Input/Output

I²C-bus

Inter-Integrated Circuit bus

Machine Model

MM

RC

Resistor Capacitor network

System Management Bus

SMBus

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

20 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

15. Revision history

Table 11. Revision history

Document ID

PCA9518A_3

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20081203

Product data sheet

-

PCA9518A_2

• Section 6.1 “Enable”: added new 3^rdparagraph

• Figure 5 “Typical application: multiple expandable 5-channel I²C-bus hubs”: added 2^ndparagraph

below drawing.

PCA9518A_2

PCA9518A_1

20081001

20070606

Product data sheet

-

PCA9518A_1

-

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

21 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

16.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

PCA9518A_3

Product data sheet

Rev. 03 — 3 December 2008

22 of 23

PCA9518A

NXP Semiconductors

Expandable 5-channel I²C-bus hub

18. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

I²C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5

6.1

6.2

6.3

7

Application design-in information . . . . . . . . . . 6

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10

Static characteristics. . . . . . . . . . . . . . . . . . . . 11

Dynamic characteristics . . . . . . . . . . . . . . . . . 13

Test information. . . . . . . . . . . . . . . . . . . . . . . . 15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

8

9

10

11

12

13

Soldering of SMD packages . . . . . . . . . . . . . . 18

Introduction to soldering . . . . . . . . . . . . . . . . . 18

Wave and reﬂow soldering . . . . . . . . . . . . . . . 18

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 19

13.1

13.2

13.3

13.4

14

15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 22

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 December 2008

Document identifier: PCA9518A_3


型号：	PCA9518AD
厂家：	NXP
描述：	Expandable 5-channel I2C-bus hub 可扩展5通道I2C总线集线器驱动程序和接口接口集成电路光电二极管
文件：	总23页 (文件大小：126K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9518AD [NXP]

相关型号：

PCA9518AD,112

PCA9518AD,118

PCA9518AD-T

PCA9518APW

PCA9518APW,512

PCA9518APW,518

PCA9518D

PCA9518D,112

PCA9518D-T

PCA9518DBQR

PCA9518DBQRG4

PCA9518DBR