PCA9502_技术文档

PCA9502

8-bit I/O expander with I²C-bus/SPI interface

Rev. 03 — 13 October 2006

Product data sheet

1. General description

The PCA9502 is an 8-bit I/O expander with I²C-bus/SPI host interface. The device comes

in a very small HVQFN24 package, which makes it ideally suitable for hand-held, battery

operated applications.

The device also supports software reset, which allows the host to reset the device at any

time, independent of the hardware reset signal.

2. Features

2.1 General features

I Selectable I²C-bus or SPI interface

I 3.3 V or 2.5 V operation

I Industrial temperature range: −40 °C to +85 °C

I Eight programmable I/O pins

I Software reset

I Industrial and commercial temperature ranges

I Available in HVQFN24 package

I 16 hardware-selectable slave addresses

2.2 I²C-bus features

I Noise ﬁlter on SCL/SDA inputs

I 400 kbit/s (maximum)

I Compliant with I²C-bus Fast-mode

I Slave mode only

2.3 SPI features

I 15 Mbit/s maximum speed

I Slave mode only

I SPI Mode 0

3. Applications

I Factory automation and process control

I Portable and battery operated devices

I Cellular data devices

PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCA9502BS

HVQFN24 plastic thermal enhanced very thin quad ﬂat package; SOT616-3

no leads; 24 terminals; body 4 × 4 × 0.85 mm

5. Block diagram

V

DD

PCA9502

RESET

SCL

SDA

A0

8

GPIO

REGISTER

GPIO[7:0]

2

I C-BUS

A1

IRQ

1 kΩ (3.3 V)

1.5 kΩ (2.5 V)

V

DD

V

DD

I2C/SPI

002aab837

V

SS

Fig 1. Block diagram of PCA9502 I²C-bus interface

V

DD

PCA9502

RESET

SCLK

CS

8

GPIO

REGISTER

GPIO[7:0]

SO

SPI

SI

IRQ

1 kΩ (3.3 V)

1.5 kΩ (2.5 V)

V

DD

I2C/SPI

002aab838

V

SS

Fig 2. Block diagram of PCA9502 SPI interface

PCA9502_3

Product data sheet

Rev. 03 — 13 October 2006

2 of 25

PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

6. Pinning information

6.1 Pinning

terminal 1

index area

terminal 1

index area

1

2

3

4

5

6

18

17

16

15

14

13

1

2

3

4

5

6

18

17

16

15

14

13

RESET

GPIO4

RESET

GPIO4

V

SS

DD

SS

DD

GPIO3

GPIO2

GPIO1

GPIO0

GPIO3

GPIO2

GPIO1

GPIO0

DD

PCA9502BS

V

SS

DD

A0

CS

SI

A1

002aab839

002aab840

Transparent top view

a. I²C-bus interface

Fig 3. Pin conﬁguration for HVQFN24

b. SPI interface

6.2 Pin description

Table 2.

Symbol

Pin description

Pin Type Description

RESET

V_DD

1

I

device hardware reset (active LOW)^[1]

2, 3, 11,

22, 24

-

power supply

I2C/SPI

CS/A0

4

I

I²C-bus or SPI interface select. I²C-bus interface is selected if this

pin is at logic HIGH. SPI interface is selected if this pin is at logic

LOW.

SPI chip select or I²C-bus device address select A0. If SPI

conﬁguration is selected by I2C/SPI pin, this pin is the SPI chip

select pin (Schmitt trigger, active LOW). If I²C-bus conﬁguration

is selected by I2C/SPI pin, this pin along with A1 pin allows user

to change the device’s base address.

5

SI/A1

SO

6

7

I

SPI data input pin or I²C-bus device address select A1. If SPI

conﬁguration is selected by I2C/SPI pin, this is the SPI data input

pin. If I²C-bus conﬁguration is selected by I2C/SPI pin, this pin

along with A0 pin allows user to change the device’s base

address. To select the device address, please refer to Table 11.

O

SPI data output pin. If SPI conﬁguration is selected by I2C/SPI

pin, this is a 3-stateable output pin. If I²C-bus conﬁguration is

selected by I2C/SPI pin, this pin function is undeﬁned and must

be left as n.c. (not connected).

SCL/SCLK

SDA

8

9

I

I²C-bus or SPI input clock.

I²C-bus data input/output, open-drain if I²C-bus conﬁguration is

selected by I2C/SPI pin. If SPI conﬁguration is selected then this

I/O

pin is an undeﬁned pin and must be connected to V_SS

.

PCA9502_3

Product data sheet

Rev. 03 — 13 October 2006

3 of 25

PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

Table 2.

Pin description …continued

Symbol

Type Description

IRQ

12

O

Interrupt (open-drain, active LOW). Interrupt is enabled when

interrupt sources are enabled in the I/O Interrupt Enable register

(IOIntEna). The interrupt condition is the change of state of the

input pins. An external resistor (1 kΩ for 3.3 V, 1.5 kΩ for 2.5 V)

must be connected between this pin and V_DD

programmable I/O pin

ground

.

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

V_SS

13

14

15

16

18

19

20

21

I/O

-

10, 17,

23

V_SS

center

pad

-

The center pad on the back side of the HVQFN24 package is

metallic and should be connected to ground on the printed-circuit

board.

[1] See Section 7.1 “Hardware reset, Power-On Reset (POR) and software reset”

7. Functional description

The device interfaces to a host through either I²C-bus or SPI interface (selectable through

I2C/SPI pin), and provides the host with eight programmable GPIO pins.

7.1 Hardware reset, Power-On Reset (POR) and software reset

These three reset methods are identical and will reset the internal registers as indicated in

Table 3.

Table 3 summarizes the state of registers after reset.

Table 3.

Registers after reset

Reset state

Register

I/O direction

I/O interrupt enable

I/O control

all bits cleared

Table 4 summarizes the state of hardware pins after reset.

Table 4.

Signal

I/Os

Signals after reset

Reset state

inputs

IRQ

HIGH by external pull-up

PCA9502_3

Product data sheet

Rev. 03 — 13 October 2006

4 of 25

PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

7.2 Interrupts

The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna)

enables interrupts due to I/O pin change of state, and the IRQ signal in response to an

interrupt generation.

8. Register descriptions

The programming combinations for register selection are shown in Table 5.

Table 5.

Register map - read/write properties

Register name

IODir

Read mode

Write mode

I/O pin direction

I/O pin states

I/O pin direction

n/a

IOState

IOIntEna

IOControl

I/O interrupt enable register

I/O pins control

I/O interrupt enable register

I/O pins control

Table 6.

PCA9502 internal registers

Register

address

Register Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

General Register Set

0x0A^[1]

0x0B^[1]

0x0C^[1]

0x0D^[1]

IODir

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

IOState

IOIntEna bit 7

reserved reserved reserved reserved reserved reserved reserved reserved reserved

[2]

0x0E^[1]

IOControl reserved reserved reserved reserved SReset

reserved reserved IOLatch

R/W

[2]

[1] Other addresses 0x00 through 0x09, 0x0F are reserved and should not be accessed (read or write).

[2] These bits are reserved and should be set to 0.

8.1 Programmable I/O pins Direction register (IODir)

This register is used to program the I/O pins direction. Bit 0 to bit 7 control GPIO0 to

GPIO7.

Table 7.

Bit

IODir register (address 0x0A) bit description

Symbol

Description

7:0

IODir

set GPIO pins 7:0 to input or output

0 = input

1 = output

Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending

interrupt will be cleared, that is, the interrupt signal will be negated.

PCA9502_3

Product data sheet

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PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

8.2 Programmable I/O pins State register (IOState)

When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each

register bit will be transferred to the corresponding IO pin programmed as output.

Table 8.

Bit

IOState register (address 0x0B) bit description

Symbol

Description

7:0

IOState

Write this register: set the logic level on the output pins

0 = set output pin to zero

1 = set output pin to one

Read this register: return states of all pins

8.3 I/O Interrupt Enable register (IOIntEna)

This register enables the interrupt due to a change in the I/O conﬁgured as inputs.

Table 9.

Bit

IOIntEna register (address 0x0C) bit description

Symbol

Description

7:0

IOIntEna

input interrupt enable

0 = a change in the input pin will not generate an interrupt

1 = a change in the input will generate an interrupt

8.4 I/O Control register (IOControl)

Table 10. IOControl register (address 0x0E) bit description

Bit

7:4

3

Symbol

-

Description

reserved for future use

software reset

SReset

A write to this bit will reset the device. Once the device is reset this

bit is automatically set to 0.

2:1

0

-

reserved for future use

IOLatch

enable/disable inputs latching

0 = input values are not latched. A change in any input generates an

interrupt. A read of the input register clears the interrupt. If the input

goes back to its initial logic state before the input register is read,

then the interrupt is cleared.

1 = input values are latched. A change in the input generates an

interrupt and the input logic value is loaded in the bit of the

corresponding input state register (IOState). A read of the IOState

register clears the interrupt. If the input pin goes back to its initial

logic state before the interrupt register is read, then the interrupt is

not cleared and the corresponding bit of the IOState register keeps

the logic value that initiates the interrupt.

Example: If GPIO4 input was as logic 0 and the input goes to logic 1

then back to logic 0, the IOState register will capture this change and

an interrupt is generated (if enabled). When the read is performed on

the IOState register, the interrupt is de-asserted, assuming there were

no additional input(s) that changed, and bit 4 of the IOState register

will read ‘1’. The next read of the IOState register should now read ‘0’.

PCA9502_3

Product data sheet

Rev. 03 — 13 October 2006

6 of 25

PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

9. I²C-bus operation

The two lines of the I²C-bus are a serial data line (SDA) and a serial clock line (SCL). Both

lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the

bus is not busy. Each device is recognized by a unique address whether it is a

microcomputer, LCD driver, memory or keyboard interface and can operate as either a

transmitter or receiver, depending on the function of the device. A device generating a

message or data is a transmitter, and a device receiving the message or data is a

receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a

microcontroller or a memory can both transmit and receive data.

9.1 Data transfers

One data bit is transferred during each clock pulse (see Figure 4). The data on the SDA

line must remain stable during the HIGH period of the clock pulse in order to be valid.

Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW

transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START

condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH deﬁnes a STOP

condition (see Figure 5). The bus is considered to be busy after the START condition and

free again at a certain time interval after the STOP condition. The START and STOP

conditions are always generated by the master.

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 4. Bit transfer on the I²C-bus

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 5. START and STOP conditions

The number of data bytes transferred between the START and STOP condition from

transmitter to receiver is not limited. Each byte, which must be eight bits long, is

transferred serially with the most signiﬁcant bit ﬁrst, and is followed by an acknowledge bit.

(see Figure 6). The clock pulse related to the acknowledge bit is generated by the master.

The device that acknowledges has to pull down the SDA line during the acknowledge

clock pulse, while the transmitting device releases this pulse (see Figure 7).

PCA9502_3

Product data sheet

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PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

acknowledgement signal

from receiver

SDA

MSB

SCL

0

1

6

7

8

0

1

2 to 7

8

S

P

ACK

START

condition

STOP

condition

byte complete,

interrupt within receiver

clock line held LOW

while interrupt is serviced

002aab012

Fig 6. Data transfer on the I²C-bus

data output

by transmitter

transmitter stays off of the bus

during the acknowledge clock

data output

by receiver

acknowledgement signal

from receiver

SCL from master

S

0

1

6

7

8

002aab013

START

condition

Fig 7. Acknowledge on the I²C-bus

A slave receiver must generate an acknowledge after the reception of each byte, and a

master must generate one after the reception of each byte clocked out of the slave

transmitter.

There is an exception to the ‘acknowledge after every byte’ rule. It occurs when a master

is a receiver: it must signal an end of data to the transmitter by not signalling an

acknowledge on the last byte that has been clocked out of the slave. The acknowledge

related clock, generated by the master should still take place, but the SDA line will not be

pulled down. In order to indicate that this is an active and intentional lack of

acknowledgement, we shall term this special condition as a ‘negative acknowledge’.

9.2 Addressing and transfer formats

Each device on the bus has its own unique address. Before any data is transmitted on the

bus, the master transmits on the bus the address of the slave to be accessed for this

transaction. A well-behaved slave with a matching address, if it exists on the network,

should of course acknowledge the master's addressing. The addressing is done by the

ﬁrst byte transmitted by the master after the START condition.

An address on the network is seven bits long, appearing as the most signiﬁcant bits of the

address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is

transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete

data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is

shown in Figure 8.

PCA9502_3

Product data sheet

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PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

SDA

SCL

0 to 6

address

0 to 6

data

0 to 6

7

8

7

8

7

8

S

P

START

condition

STOP

condition

R/W

ACK

data

ACK

002aab046

Fig 8. A complete data transfer

When an address is sent, each device in the system compares the ﬁrst seven bits after the

START with its own address. If there is a match, the device will consider itself addressed

by the master, and will send an acknowledge. The device could also determine if in this

transaction it is assigned the role of a slave receiver or slave transmitter, depending on the

R/W bit.

Each node of the I²C-bus network has a unique seven-bit address. The address of a

microcontroller is of course fully programmable, while peripheral devices usually have

ﬁxed and programmable address portions.

When the master is communicating with one device only, data transfers follow the format

of Figure 8, where the R/W bit could indicate either direction. After completing the transfer

and issuing a STOP condition, if a master would like to address some other device on the

network, it could start another transaction by issuing a new START.

Another way for a master to communicate with several different devices would be by using

a ‘repeated START’. After the last byte of the transaction was transferred, including its

acknowledge (or negative acknowledge), the master issues another START, followed by

address byte and data, without effecting a STOP. The master may communicate with a

number of different devices, combining ‘reads’ and ‘writes’. After the last transfer takes

place, the master issues a STOP and releases the bus. Possible data formats are

demonstrated in Figure 9. Note that the repeated START allows for both change of a slave

and a change of direction, without releasing the bus. We shall see later on that the change

of direction feature can come in handy even when dealing with a single device.

In a single master system, the repeated START mechanism may be more efﬁcient than

terminating each transfer with a STOP and starting again. In a multimaster environment,

the determination of which format is more efﬁcient could be more complicated, as when a

master is using repeated STARTs it occupies the bus for a long time and thus preventing

other devices from initiating transfers.

PCA9502_3

Product data sheet

Rev. 03 — 13 October 2006

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PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

data transferred

(n bytes + acknowledge)

master write:

S

SLAVE ADDRESS

W

A

DATA

A

DATA

A

P

START condition

write

acknowledge

acknowledge acknowledge

STOP condition

data transferred

(n bytes + acknowledge)

master read:

S

SLAVE ADDRESS

R

A

DATA

A

DATA

NA

P

START condition

read

acknowledge

not

acknowledge

STOP condition

data transferred

(n bytes + acknowledge)

data transferred

(n bytes + acknowledge)

combined

formats:

S

SLAVE ADDRESS R/W

A

DATA

A

Sr SLAVE ADDRESS R/W

A

DATA

A

P

START condition

read or

write

acknowledge acknowledge

repeated

START condition

read or

write

acknowledge acknowledge

STOP condition

002aab458

direction of transfer

may change at this point

Fig 9. I²C-bus data formats

PCA9502_3

Product data sheet

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PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

9.3 Addressing

Before any data is transmitted or received, the master must send the address of the

receiver via the SDA line. The ﬁrst byte after the START condition carries the address of

the slave device and the read/write bit. Table 11 shows how the PCA9502’s address can

be selected by using A1 and A0 pins. For example, if these 2 pins are connected to V_DD

then the PCA9502’s address is set to 0x90, and the master communicates with it through

this address.

,

Table 11. PCA9502 address map

A1

A0

PCA9502 I²C-bus addresses (hex)^[1]

0x90 (1001 000X)

0x92 (1001 001X)

0x94 (1001 010X)

0x96 (1001 011X)

0x98 (1001 100X)

0x9A (1001 101X)

0x9C (1001 110X)

0x9E (1001 111X)

0xA0 (1010 000X)

0xA2 (1010 001X)

0xA4 (1010 010X)

0xA6 (1010 011X)

0xA8 (1010 100X)

0xAA (1010 101X)

0xAC (1010 110X)

0xAE (1010 111X)

V_DD

V_SS

SCL

SDA

V_DD

V_SS

SCL

SDA

V_DD

V_SS

SCL

SDA

V_DD

V_SS

SCL

SDA

V_DD

V_SS

SCL

SDA

[1] X = logic 0 for write cycle; X = logic 1 for read cycle.

9.4 Use of sub-addresses

When a master communicates with the PCA9502 it must send a sub-address in the byte

following the slave address byte. This sub-address is the internal address of the word the

master wants to access for a single byte transfer, or the beginning of a sequence of

locations for a multi-byte transfer. A sub-address is an 8-bit byte. Unlike the device

address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus

it must be followed by an acknowledge.

A register write cycle is shown in Figure 10. The START is followed by a slave address

byte with the direction bit set to ‘write’, a sub-address byte, a number of data bytes, and a

STOP signal. The sub-address indicates which register the master wants to access. and

the data bytes which follow will be written one after the other to the sub-address location.

PCA9502_3

Product data sheet

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PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

S

SLAVE ADDRESS

W

A

REGISTER ADDRESS

A

nDATA

A

P

002aab047

White block: host to PCA9502

Grey block: PCA9502 to host

Fig 10. Master writes to slave

The register read cycle (see Figure 11) commences in a similar manner, with the master

sending a slave address with the direction bit set to ‘write’ with a following sub-address.

Then, in order to reverse the direction of the transfer, the master issues a repeated START

followed again by the device address, but this time with the direction bit set to ‘read’. The

data bytes starting at the internal sub-address will be clocked out of the device, each

followed by a master-generated acknowledge. The last byte of the read cycle will be

followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated

by a STOP signal.

S

SLAVE ADDRESS

W

A

REGISTER ADDRESS

A

S

SLAVE ADDRESS

R

A

nDATA

A

LAST DATA

NA

P

002aab048

White block: host to PCA9502

Grey block: PCA9502 to host

Fig 11. Master read from Slave

Table 12. Register address byte (I²C-bus)

Bit

7

Name

Function

-

not used

6:3

2:1

0

A[3:0]

internal register select

not used, set to 0

not used

-

PCA9502_3

Product data sheet

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PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

10. SPI operation

SCLK

SI

A3 A2 A1

A0

0

X

D7 D6 D5 D4 D3 D2 D1 D0

R/W

002aab925

R/W = 0; A[3:0] = register address

a. Register write

SCLK

SI

A3 A2 A1

A0

0

X

R/W

D7 D6 D5 D4 D3 D2 D1 D0

SO

002aab926

R/W = 1; A[3:0] = register address

b. Register read

Fig 12. SPI operation

Table 13. Register address byte (SPI)

Bit

Name

Function

7

R/W

1: read from PCA9502

0: write to PCA9502

internal register select

not used, set to 0

not used

6:3

2:1

0

A[3:0]

-

11. Limiting values

Table 14. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I

Parameter

Conditions

Min

−0.3

−10

-

Max

+4.6

+5.5^[1]

+10

Unit

V

supply voltage

input voltage

any input

any output

V

I_I

input current

mA

mW

°C

I_O

output current

+10

P_tot

total power dissipation

power dissipation per output

ambient temperature

storage temperature

300

P/out

T_amb

T_stg

-

50

−40

−65

+85

+150

°C

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present.

4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.

PCA9502_3

Product data sheet

Rev. 03 — 13 October 2006

13 of 25

PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

12. Static characteristics

Table 15. Static characteristics

V_DD= (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_DD= 2.5 V

V_DD= 3.3 V

Unit

Min

Max

Min

Max

Supplies

V_DD

I_DD

supply voltage

supply current

2.3

2.7

750

600

3.0

3.6

750

600

V

operating; no load

static; no load

-

µA

Inputs I2C/SPI

V_IH

HIGH-level input voltage

1.6

5.5^[1]

0.6

1

2.0

5.5^[1]

0.8

1

V

V_IL

LOW-level input voltage

leakage current

-

V

I_L

input; V_I= 0 V or 5.5 V^[1]

µA

pF

C_i

input capacitance

3

Output SO

V_OH

HIGH-level output voltage

LOW-level output voltage

output capacitance

I_OH= −400 µA

I_OH= −4 mA

I_OL= 1.6 mA

I_OL= 4 mA

1.85

-

V

-

2.4

V

V_OL

0.4

-

V

0.4

4

V

C_o

4

pF

Inputs/outputs GPIO0 to GPIO7

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

1.6

5.5^[1]

2.0

5.5^[1]

V

-

0.6

-

0.8

-

V

V_OH

I_OH= −400 µA

I_OH= −4 mA

1.85

-

V

-

2.4

-

V

V_OL

LOW-level output voltage

I_OL= 1.6 mA

0.4

-

V

I_OL= 4 mA

input; V_I= 0 V or 5.5 V^[1]

0.4

1

V

I_L

leakage current

1

µA

pF

C_o

output capacitance

4

Output IRQ

V_OL

LOW-level output voltage

I_OL= 1.6 mA

I_OL= 4 mA

-

0.4

-

0.4

4

V

C_o

output capacitance

4

pF

I²C-bus input/output SDA

V_IH

V_IL

HIGH-level input voltage

1.6

5.5^[1]

0.6

0.4

-

2.0

5.5^[1]

0.8

-

V

LOW-level input voltage

LOW-level output voltage

-

V

V_OL

I_OL= 1.6 mA

V

I_OL= 4 mA

input; V_I= 0 V or 5.5 V^[1]

0.4

10

7

V

I_L

leakage current

10

7

µA

pF

C_o

output capacitance

PCA9502_3

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Table 15. Static characteristics …continued

V_DD= (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_DD= 2.5 V

V_DD= 3.3 V

Unit

Min

Max

Min

Max

I²C-bus inputs SCL, CS/A0, SI/A1

V_IH

V_IL

I_L

HIGH-level input voltage

LOW-level input voltage

leakage current

1.6

5.5^[1]

0.6

10

2.0

5.5^[1]

0.8

10

V

-

V

input; V_I= 0 V or 5.5 V^[1]

µA

pF

C_i

input capacitance

7

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage

tolerance on inputs and outputs when no supply voltage is present.

13. Dynamic characteristics

Table 16. I²C-bus timing speciﬁcations

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

V

_DD= (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); T_amb= −40 °C to +85 °C; refer to V_ILand V_IHwith an input voltage of V_SSto V_DD

.

All output load = 25 pF, except SDA output load = 400 pF.^[1]

Symbol Parameter Conditions

Standard-mode Fast-mode Unit

I²C-bus

Min

Max

100

-

Min

Max

[2]

f_SCL

t_BUF

SCL clock frequency

0

400 kHz

bus free time between a STOP and

START condition

4.7

1.3

-

µs

t_HD;STA

t_SU;STA

hold time (repeated) START condition

4.0

4.7

-

0.6

-

µs

set-up time for a repeated START

condition

t_SU;STOset-up time for STOP condition

t_HD;DATdata hold time

t_VD;ACKdata valid acknowledge time

4.7

-

0.6

-

µs

0

ns

-

0.6

-

0.6 µs

t_VD;DAT

t_SU;DAT

t_LOW

t_HIGH

t_f

data valid time

SCL LOW to data out valid

0.6 ns

data set-up time

250

4.7

4.0

-

150

1.3

0.6

-

ns

µs

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

-

300

1000

50

300 ns

t_r

-

t_SP

pulse width of spikes that must be

suppressed by the input ﬁlter

-

50

ns

t_d1

t_d4

t_d5

I²C-bus GPIO output valid time

I2C input pin interrupt valid time

I2C input pin interrupt clear time

0.5

0.2

-

0.5

0.2

-

µs

[1] A detailed description of the I²C-bus speciﬁcation, with applications, is given in brochure “The I²C-bus and how to use it”. This brochure

may be ordered using the code 9398 393 40011.

[2] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a

minimum of 25 ms.

PCA9502_3

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START

condition

(S)

bit 7

MSB

(A7)

bit 0

LSB

(R/W)

STOP

condition

(P)

bit 6

(A6)

acknowledge

(A)

protocol

t

HIGH

SU;STA

LOW

1

/f

SCL

SDA

t

BUF

f

t

SP

t

r

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

HD;STA

SU;DAT

002aab489

Rise and fall times refer to V_ILand V_IH

.

Fig 13. I²C-bus timing diagram

SLAVE ADDRESS

W

A

SDA

IOSTATE REG.

DATA

t

d1

GPIOn

002aab255

Fig 14. Write to output

ACK from slave

ACK from master

SLAVE ADDRESS

W

A

S

R

A

P

SDA

IRQ

IOSTATE REG.

SLAVE ADDRESS

DATA

t

d4

d5

GPIOn

002aab877

Fig 15. GPIO pin interrupt

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Table 17. SPI-bus timing speciﬁcations

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

_DD= (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); T_amb= −40 °C to +85 °C; and refer to V_ILand V_IHwith an input voltage of V_SSto V_DD

All output load = 25 pF, unless otherwise speciﬁed.

V

.

Symbol

Parameter

Conditions

V_DD= 2.5 V

V_DD= 3.3 V

Unit

Min

-

Max

Min

-

Max

t_{d(CS_NH-SOZ)}

CS HIGH to SO 3-state delay time C_L= 100 pF

100

ns

t_{su(CS_N-SCLK)}CS to SCLK setup time

100

20

-

100

20

-

t_{h(CS_N-SCLK)}

t_d(SCLK-SO)

t_su(SI-SCLK)

t_h(SI-SCLK)

T_SCLK

CS to SCLK hold time

SCLK fall to SO valid delay time

SI to SCLK setup time

SI to SCLK hold time

SCLK period

C_L= 100 pF

25

-

20

-

10

83

30

200

20

10

67

25

200

-

t_SCLKL+ t_SCLKL

-

t_SCLKH

SCLK HIGH time

-

t_SCLKL

SCLK LOW time

-

t_{w(CS_NH)}

t_d9

CS HIGH pulse width

SPI output data valid time

SPI interrupt clear time

-

t_d13

-

CS

t

w(CS_NH)

t

SCLKH

t

h(CS_N-SCLK)

SCLKL

su(CS_N-SCLK)

t

h(CS_N-SCLK)

SCLK

t

h(SI-SCLK)

t

su(SI-SCLK)

SI

t

d(CS_N-SOZ)

d(SCLK-SO)

SO

002aac429

Fig 16. Detailed SPI-bus timing

CS

SCLK

A3 A2 A1

A0

0

X

D7 D6 D5 D4 D3 D2 D1 D0

SI

R/W

t

d9

GPIOn

002aab878

R/W = 0; A[3:0] = IOState (0x0B)

Fig 17. SPI write IOState to GPIO switch

PCA9502_3

Product data sheet

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8-bit I/O expander with I²C-bus/SPI interface

CS

SCLK

A3 A2 A1

A0

0

X

SI

SO

R/W

D7 D6 D5 D4 D3 D2 D1 D0

t

d13

IRQ

002aab879

R/W = 1; A[3:0] = IOState (0x0B)

Fig 18. Read IOState to clear GPIO INT

PCA9502_3

Product data sheet

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14. Package outline

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

SOT616-3

B

A

D

terminal 1

index area

A

1

E

c

detail X

e

1

C

1/2 e

y

C

1

e

v

M

C

A

B

b

7

12

w

L

13

6

e

E

h

2

1/2 e

1

18

terminal 1

index area

24

19

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

mm

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

4.1

3.9

2.75

2.45

4.1

3.9

2.75

2.45

0.5

0.3

0.05

0.1

1

0.2

0.5

2.5

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

04-11-19

05-03-10

SOT616-3

- - -

MO-220

- - -

Fig 19. Package outline SOT616-3 (HVQFN24)

PCA9502_3

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15. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

16. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

PCA9502_3

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• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

16.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 20) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 18 and 19

Table 18. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 19. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 20.

PCA9502_3

Product data sheet

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PCA9502

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8-bit I/O expander with I²C-bus/SPI interface

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 20. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

17. Abbreviations

Table 20. Abbreviations

Acronym

GPIO

I²C-bus

I/O

Description

General Purpose Input/Output

Inter Integrated Circuit bus

Input/Output

LCD

Liquid Crystal Display

Power-On Reset

POR

SPI

Serial Peripheral Interface

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18. Revision history

Table 21. Revision history

Document ID

PCA9502_3

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20061013

Product data sheet

-

PCA9502_2

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 15 “Static characteristics”, sub-section “Supplies”:

–

I

_DD, supply current, operating; no load: changed maximum limit from 6.0 mA to 750 µA for both

2.5 V and 3.3 V supply voltage ranges

_DD, supply current: added “static; no load” Conditions (max 600 µA)

–

I

PCA9502_2

PCA9502_1

20060803

20060707

Product data sheet

-

PCA9502_1

-

PCA9502_3

Product data sheet

Rev. 03 — 13 October 2006

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

19.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

19.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

PCA9502_3

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21. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

19.4

20

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Contact information . . . . . . . . . . . . . . . . . . . . 24

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General features. . . . . . . . . . . . . . . . . . . . . . . . 1

I²C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 1

SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1

2.2

2.3

21

3

4

5

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

Functional description . . . . . . . . . . . . . . . . . . . 4

Hardware reset, Power-On Reset (POR) and

software reset . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.2

8

8.1

Register descriptions . . . . . . . . . . . . . . . . . . . . 5

Programmable I/O pins Direction register

(IODir). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Programmable I/O pins State register

8.2

(IOState) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

I/O Interrupt Enable register (IOIntEna) . . . . . . 6

I/O Control register (IOControl). . . . . . . . . . . . . 6

8.3

8.4

9

I²C-bus operation. . . . . . . . . . . . . . . . . . . . . . . . 7

Data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Addressing and transfer formats. . . . . . . . . . . . 8

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Use of sub-addresses. . . . . . . . . . . . . . . . . . . 11

9.1

9.2

9.3

9.4

10

11

12

13

14

15

SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13

Static characteristics. . . . . . . . . . . . . . . . . . . . 14

Dynamic characteristics . . . . . . . . . . . . . . . . . 15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

Handling information. . . . . . . . . . . . . . . . . . . . 20

16

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Introduction to soldering . . . . . . . . . . . . . . . . . 20

Wave and reﬂow soldering . . . . . . . . . . . . . . . 20

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 21

16.1

16.2

16.3

16.4

17

18

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23

19

Legal information. . . . . . . . . . . . . . . . . . . . . . . 24

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

19.1

19.2

19.3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 October 2006

Document identifier: PCA9502_3


型号：	PCA9502
厂家：	NXP
描述：	8-bit I/O expander with I2C-bus/SPI interface 8位I / O扩展器，带有I2C总线/ SPI接口
文件：	总25页 (文件大小：139K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9502 [NXP]

相关型号：

PCA9502BS

PCA9502BS,128

PCA9503A

PCA9504A

PCA9504A-T

PCA9504ADGG

PCA9504ADGG,112

PCA9504ADGG,118

PCA9504ADGG-T

PCA9504ADGG/G,118

PCA9505

PCA9505DGG