P89C51RD2_技术文档

INTEGRATED CIRCUITS

P89C51RA2xx/RB2xx/RC2xx/RD2xx

80C51 8-bit Flash microcontroller family

8KB/16KB/32KB/64KB ISP/IAP Flash with

512B/512B/512B/1KB RAM

Preliminary data

Supersedes data of 2002 May 20

2002 Jul 18

Philips

Semiconductors

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

P89C51RA2/RB2/RC2/RD2xx

DESCRIPTION

FEATURES

The P89C51RA2/RB2/RC2/RD2xx contains a non-volatile

8KB/16KB/32KB/64KB Flash program memory that is both parallel

programmable and serial In-System and In-Application

Programmable. In-System Programming (ISP) allows the user to

download new code while the microcontroller sits in the application.

In-Application Programming (IAP) means that the microcontroller

fetches new program code and reprograms itself while in the

system. This allows for remote programming over a modem link.

A default serial loader (boot loader) program in ROM allows serial

In-System programming of the Flash memory via the UART without

the need for a loader in the Flash code. For In-Application

Programming, the user program erases and reprograms the Flash

memory by use of standard routines contained in ROM.

• 80C51 Central Processing Unit

• On-chip Flash Program Memory with In-System Programming

(ISP) and In-Application Programming (IAP) capability

• Boot ROM contains low level Flash programming routines for

downloading via the UART

• Can be programmed by the end-user application (IAP)

• Parallel programming with 87C51 compatible hardware interface

to programmer

• Supports 6-clock/12-clock mode via parallel programmer (default

clock mode after ChipErase is 12-clock)

• 6-clock/12-clock mode Flash bit erasable and programmable via

The device supports 6-clock/12-clock mode selection by

programming a Flash bit using parallel programming or

In-System Programming. In addition, an SFR bit (X2) in the clock

control register (CKCON) also selects between 6-clock/12-clock

mode.

ISP

• 6-clock/12-clock mode programmable “on-the-fly” by SFR bit

• Peripherals (PCA, timers, UART) may use either 6-clock or

12-clock mode while the CPU is in 6-clock mode

Additionally, when in 6-clock mode, peripherals may use either 6

clocks per machine cycle or 12 clocks per machine cycle. This

choice is available individually for each peripheral and is selected by

bits in the CKCON register.

• Speed up to 20 MHz with 6-clock cycles per machine cycle

(40 MHz equivalent performance); up to 33 MHz with 12 clocks

per machine cycle

This device is a Single-Chip 8-Bit Microcontroller manufactured in an

advanced CMOS process and is a derivative of the 80C51

microcontroller family. The instruction set is 100% compatible with

the 80C51 instruction set.

• Fully static operation

• RAM expandable externally to 64 kbytes

• Four interrupt priority levels

• Seven interrupt sources

• Four 8-bit I/O ports

The device also has four 8-bit I/O ports, three 16-bit timer/event

counters, a multi-source, four-priority-level, nested interrupt structure,

an enhanced UART and on-chip oscillator and timing circuits.

• Full-duplex enhanced UART

– Framing error detection

The added features of the P89C51RA2/RB2/RC2/RD2xx make it a

powerful microcontroller for applications that require pulse width

modulation, high-speed I/O and up/down counting capabilities such

as motor control.

– Automatic address recognition

• Power control modes

– Clock can be stopped and resumed

– Idle mode

– Power down mode

• Programmable clock-out pin

• Second DPTR register

• Asynchronous port reset

• Low EMI (inhibit ALE)

• Programmable Counter Array (PCA)

– PWM

– Capture/compare

2

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

SELECTION TABLE

Serial

Interfaces

Type

Memory

Timers

Max.

Freq.

at 6-clk

/ 12-clk

(MHz)

Freq.

Range

at 3V at

(MHz)

Freq.

Range

5V

(MHz)

P89C51RD2xx

P89C51RC2xx

P89C51RB2xx

P89C51RA2xx

1K

–

64K

32K

16K

8K

4

√

–

32

7(2)/4

√

12-clk

6-clk

H

20/33

–

0-20/33

512B

NOTE:

1. P89C51Rx2Hxx devices have a 6-clk default clock rate (12-clk optional). Please also see Device Comparison Table.

DEVICE COMPARISON TABLE

Item

1st generation of Rx2 devices

2nd generation of Rx2 devices

(this data sheet)

Difference

No more letter ‘H’

Type description

P89C51Rx2Hxx(x)

P89C51Rx2xx(x)

Programming algo-

rithm

When using a parallel programmer,

be sure to select

P89C51Rx2Hxx(x) devices

When using a parallel programmer, be Different programming algorithm

sure to select P89C51Rx2xx(x) de-

vices (no more letter ‘H’)

due to process change

Clock mode (I)

6-clk default, OTP configuration bit 12-clk default, Flash configuration bit

More flexibility for the end user,

more compatibility to older

P89C51Rx+ parts

to program to 12-clk mode using

parallel programmer (cannot be

programmed back to 6-clk)

to program to 6-clk mode using paral-

lel programmer or ISP (can be repro-

grammed)

Clock mode (II)

N/A

6-clock/12-clock mode programmable

“on the fly” by SFR bit X2 (CKCON.0)

Clock mode can be changed by

software

Peripheral clock

modes

N/A

Peripherals can be run in 12-clk mode

while CPU runs in 6-clk mode

More flexibility, lower power con-

sumption

Flash block structure

Two 8-Kbyte blocks

1–3 16-Kbyte blocks

2–16 4-Kbyte blocks

More flexibility

ORDERING INFORMATION

MEMORY

FLASH RAM

FREQUENCY (MHz)

TEMPERATURE

RANGE (°C)

AND PACKAGE

PART ORDER

NUMBER

VOLTAGE

RANGE

DWG #

1

6-CLOCK

12-CLOCK

MODE

1. P89C51RA2BA/01

2. P89C51RA2BBD/01

3. P89C51RB2BA/01

4. P89C51RB2BBD/01

5. P89C51RC2BN/01

6. P89C51RC2BA/01

7. P89C51RC2FA/01

8. P89C51RC2BBD/01

9. P89C51RC2FBD/01

10. P89C51RD2BN/01

11. P89C51RD2BA/01

12. P89C51RD2BBD/01

13. P89C51RD2FA/01

8 KB

512 B

1024 B

0 to +70, PLCC

0 to +70, LQFP

0 to +70, PLCC

0 to +70, LQFP

0 to +70, PDIP

0 to +70, PLCC

–40 to +85, PLCC

0 to +70, LQFP

–40 to +85, LQFP

0 to +70, PDIP

0 to +70, PLCC

0 to +70, LQFP

–40 to +85, PLCC

4.5–5.5 V

0 to 20 MHz

0 to 33 MHz

SOT187-2

SOT389-1

SOT187-2

SOT389-1

SOT129-1

SOT187-2

SOT389-1

SOT129-1

SOT187-2

SOT389-1

SOT187-2

16 KB

32 KB

64 KB

NOTE:

1. The Part Marking will not include the “/01”.

2002 Jul 18

3

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

BLOCK DIAGRAM 1

ACCELERATED 80C51 CPU

(12-CLK MODE, 6-CLK MODE)

8K / 16K / 32K /

64 KBYTE

CODE FLASH

FULL-DUPLEX

ENHANCED UART

512 / 1024 BYTE

DATA RAM

TIMER 0

TIMER 1

PORT 3

CONFIGURABLE I/Os

TIMER 2

PORT 2

CONFIGURABLE I/Os

PROGRAMMABLE

COUNTER ARRAY

(PCA)

PORT 1

CONFIGURABLE I/Os

WATCHDOG TIMER

PORT 0

CONFIGURABLE I/Os

CRYSTAL OR

RESONATOR

OSCILLATOR

su01606

4

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

BLOCK DIAGRAM – CPU ORIENTED

P0.0–P0.7

P2.0–P2.7

PORT 0

DRIVERS

PORT 2

DRIVERS

V

CC

SS

RAM ADDR

REGISTER

PORT 0

LATCH

PORT 2

LATCH

FLASH

RAM

8

B

STACK

POINTER

ACC

REGISTER

PROGRAM

ADDRESS

REGISTER

TMP1

TMP2

BUFFER

ALU

SFRs

TIMERS

P.C.A.

PC

INCRE-

MENTER

PSW

8

16

PROGRAM

COUNTER

PSEN

ALE

DPTR’S

MULTIPLE

TIMING

AND

CONTROL

EAV

PP

RST

PORT 1

LATCH

PORT 3

LATCH

PD

OSCILLATOR

PORT 1

DRIVERS

PORT 3

DRIVERS

XTAL1

XTAL2

P1.0–P1.7

P3.0–P3.7

SU01065

5

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

LOGIC SYMBOL

Plastic Leaded Chip Carrier

6

1

40

V

SS

CC

XTAL1

7

39

ADDRESS AND

DATA BUS

LCC

XTAL2

RST

17

29

T2

T2EX

18

28

EA/V

PP

Pin Function

PSEN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

NIC*

P1.0/T2

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

XTAL1

V

SS

NIC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P2.7/A15

PSEN

ALE/PROG

NIC*

ALE/PROG

RxD

P1.1/T2EX

P1.2/ECI

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

TxD

INT0

EA/V

PP

INT1

T0

T1

WR

RD

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

ADDRESS BUS

SU01302

V

CC

* NO INTERNAL CONNECTION

PINNING

Plastic Dual In-Line Package

SU00023

Plastic Quad Flat Pack

T2/P1.0

40

39

V

CC

1

2

3

44

34

T2EX/P1.1

P0.0/AD0

ECI/P1.2

38 P0.1/AD1

37 P0.2/AD2

1

33

23

CEX0/P1.3

CEX1/P1.4

4

5

36

P0.3/AD3

35 P0.4/AD4

34

LQFP

CEX2/P1.5

CEX3/P1.6

CEX4/P1.7

RST

6

7

8

9

11

P0.5/AD5

33 P0.6/AD6

32

12

Pin Function

22

P0.7/AD7

Pin Function

DUAL

IN-LINE

PACKAGE

31 EA/V

RxD/P3.0 10

TxD/P3.1 11

INT0/P3.2 12

PP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

P1.5/CEX2

P1.6/CEX3

P1.7/CEX4

RST

P3.0/RxD

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

XTAL2

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

SS

30

NIC*

ALE/PROG

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

29 PSEN

28

13

INT1/P3.3

P2.7/A15

27 P2.6/A14

26

T0/P3.4 14

T1/P3.5 15

WR/P3.6 16

RD/P3.7 17

XTAL2 18

XTAL1 19

V

CC

P2.5/A13

NIC*

P1.0/T2

P1.1/T2EX

P1.2/ECI

P1.3/CEX0

P1.4/CEX1

25 P2.4/A12

24 P2.3/A11

ALE/PROG

NIC*

EA/V

PP

23

22

P2.2/A10

P2.1/A9

P2.0/A8

XTAL1

P0.7/AD7

SU01400

* NO INTERNAL CONNECTION

21

V

20

SS

SU00021

6

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

TYPE

NAME AND FUNCTION

PDIP

20

PLCC

22

LQFP

16

V

SS

I

Ground: 0 V reference.

V

CC

40

44

38

Power Supply: This is the power supply voltage for normal, idle, and power-down

operation.

P0.0–0.7

39–32

1–8

43–36

2–9

37–30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s

written to them float and can be used as high-impedance inputs. Port 0 is also the

multiplexed low-order address and data bus during accesses to external program

and data memory. In this application, it uses strong internal pull-ups when emitting 1s.

P1.0–P1.7

40–44,

1–3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins.

Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, port 1 pins that are externally pulled low will

source current because of the internal pull-ups. (See DC Electrical Characteristics:

I ).

IL

Alternate functions for P89C51RA2/RB2/RC2/RD2xx Port 1 include:

1

2

40

I/O

T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable

Clock-Out)

2

3

4

5

6

7

8

3

4

5

6

7

8

9

41

42

43

44

1

I

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control

ECI (P1.2): External Clock Input to the PCA

I

I/O

CEX0 (P1.3): Capture/Compare External I/O for PCA module 0

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4

2

3

P2.0–P2.7

21–28

24–31

18–25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as

inputs. As inputs, port 2 pins that are externally being pulled low will source current

because of the internal pull-ups. (See DC Electrical Characteristics: I ). Port 2

IL

emits the high-order address byte during fetches from external program memory

and during accesses to external data memory that use 16-bit addresses (MOVX

@DPTR). In this application, it uses strong internal pull-ups when emitting 1s.

During accesses to external data memory that use 8-bit addresses (MOV @Ri),

port 2 emits the contents of the P2 special function register.

P3.0–P3.7

10–17

11,

13–19

5, 7–13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as

inputs. As inputs, port 3 pins that are externally being pulled low will source current

because of the pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves

IL

the special features of the P89C51RA2/RB2/RC2/RD2xx, as listed below:

10

11

12

13

14

15

16

17

11

13

14

15

16

17

18

19

5

7

I

O

I

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

8

INT0 (P3.2): External interrupt

9

I

INT1 (P3.3): External interrupt

10

11

12

13

I

T0 (P3.4): Timer 0 external input

I

T1 (P3.5): Timer 1 external input

O

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

RST

ALE

9

10

4

I

Reset: A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal resistor to V permits a power-on reset using only

SS

an external capacitor to V

.

CC

30

33

27

O

Address Latch Enable: Output pulse for latching the low byte of the address

during an access to external memory. In normal operation, ALE is emitted twice

every machine cycle, and can be used for external timing or clocking. Note that one

ALE pulse is skipped during each access to external data memory. ALE can be

disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a

MOVX instruction.

7

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

PIN NUMBER

MNEMONIC

TYPE

NAME AND FUNCTION

PDIP

PLCC

LQFP

PSEN

29

32

26

O

Program Store Enable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access

to external data memory. PSEN is not activated during fetches from internal

program memory.

EA/V

31

35

29

I

External Access Enable/Programming Supply Voltage: EA must be externally

held low to enable the device to fetch code from external program memory

locations. If EA is held high, the device executes from internal program memory.

The value on the EA pin is latched when RST is released and any subsequent

changes have no effect. This pin also receives the programming supply voltage

PP

(V ) during Flash programming.

PP

XTAL1

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock

generator circuits.

XTAL2

O

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin (other than V ) must not be higher than V + 0.5 V or less than V – 0.5 V.

PP

CC

SS

8

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Table 1. Special Function Registers

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

DESCRIPTION

MSB

E7

–

LSB

E0

ACC*

AUXR#

AUXR1#

B*

Accumulator

E0H

8EH

A2H

F0H

E6

–

E5

E4

–

E3

–

E2

–

E1

00H

EXTRAM

Auxiliary

–

AO

xxxxxx00B

xxxxxxx0B

00H

ENBOOT

Auxiliary 1

B register

–

GF2

F3

0

–

DPS

F0

F7

F6

F5

F4

F2

F1

CCAP0H# Module 0 Capture High

CCAP1H# Module 1 Capture High

CCAP2H# Module 2 Capture High

CCAP3H# Module 3 Capture High

CCAP4H# Module 4 Capture High

CCAP0L# Module 0 Capture Low

CCAP1L# Module 1 Capture Low

CCAP2L# Module 2 Capture Low

CCAP3L# Module 3 Capture Low

CCAP4L# Module 4 Capture Low

FAH

FBH

FCH

FDH

FEH

EAH

EBH

ECH

EDH

EEH

xxxxxxxxB

CCAPM0# Module 0 Mode

CCAPM1# Module 1 Mode

CCAPM2# Module 2 Mode

CCAPM3# Module 3 Mode

CCAPM4# Module 4 Mode

DAH

DBH

DCH

DDH

DEH

–

ECOM CAPP

CAPN

MAT

TOG

PWM

ECCF

x0000000B

DF

CF

DE

CR

DD

–

DC

DB

DA

D9

D8

CCON*#

CH#

PCA Counter Control

PCA Counter High

D8H

F9H

CCF4

CCF3

CCF2

CCF1

CCF0

00x00000B

00H

CKCON#

CL#

Clock control

PCA Counter Low

8FH

E9H

–

WDX2

WDTE

PCAX2

SIX2

–

T2X2

–

T1X2

CPS1

T0X2

CPS0

X2

x0000000B

00H

CMOD#

PCA Counter Mode

D9H

CIDL

–

ECF

00xxx000B

DPTR:

DPH

DPL

Data Pointer (2 bytes)

Data Pointer High

Data Pointer Low

83H

82H

00H

AF

EA

BF

–

AE

EC

AD

ET2

BD

AC

ES

AB

ET1

BB

AA

EX1

BA

A9

ET0

B9

A8

EX0

B8

IE*

Interrupt Enable 0

A8H

00H

BE

BC

IP*

Interrupt Priority

B8H

B7H

PPC

PPCH

PT2

PT2H

PS

PT1

PT1H

PX1

PX1H

PT0

PT0H

PX0

PX0H

x0000000B

IPH#

Interrupt Priority High

–

PSH

87

AD7

97

86

AD6

96

85

AD5

95

84

AD4

94

83

AD3

93

82

AD2

92

81

AD1

91

80

AD0

90

P0*

P1*

P2*

P3*

Port 0

Port 1

Port 2

80H

90H

A0H

FFH

CEX4

A7

CEX3

A6

CEX2

A5

CEX1

A4

CEX0

A3

ECI

A2

T2EX

A1

T2

A0

AD15

B7

AD14

B6

AD13

B5

AD12

B4

AD11

B3

AD10

B2

AD9

B1

AD8

B0

Port 3

B0H

87H

RD

WR

T1

T0

INT1

INT0

TxD

RxD

FFH

1

PCON#

Power Control

SMOD1 SMOD0

–

POF

GF1

GF0

PD

IDL

00xxx000B

*

SFRs are bit addressable.

#

–

SFRs are modified from or added to the 80C51 SFRs.

Reserved bits.

1. Reset value depends on reset source.

9

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Table 1. Special Function Registers (Continued)

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

DIRECT

ADDRESS

RESET

VALUE

SYMBOL

DESCRIPTION

MSB

LSB

D7

CY

D6

AC

D5

F0

D4

D3

D2

D1

F1

D0

P

PSW*

Program Status Word

D0H

RS1

RS0

OV

00000000B

RCAP2H#

RCAP2L#

Timer 2 Capture High

Timer 2 Capture Low

CBH

CAH

00H

SADDR# Slave Address

SADEN# Slave Address Mask

A9H

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

9F

9E

9D

9C

9B

9A

99

TI

98

RI

SM0/FE

SCON*

SP

Serial Control

Stack Pointer

98H

81H

SM1

SM2

REN

TB8

RB8

00H

07H

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer Control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

CF

TF2

–

CE

EXF2

–

CD

RCLK

–

CC

TCLK

–

CB

EXEN2

–

CA

TR2

–

C9

C8

T2CON*

Timer 2 Control

C8H

C9H

C/T2

T2OE

CP/RL2 00H

DCEN xxxxxx00B

T2MOD# Timer 2 Mode Control

TH0

TH1

TH2#

TL0

TL1

TL2#

Timer High 0

Timer High 1

Timer High 2

Timer Low 0

Timer Low 1

Timer Low 2

8CH

8DH

CDH

8AH

8BH

CCH

00H

TMOD

Timer Mode

89H

A6H

GATE

C/T

M1

M0

GATE

C/T

M1

M0

00H

WDTRST Watchdog Timer Reset

*

SFRs are bit addressable.

#

–

SFRs are modified from or added to the 80C51 SFRs.

Reserved bits.

This device is configured at the factory to operate using 12 clock

periods per machine cycle, referred to in this datasheet as “12-clock

mode”. It may be optionally configured on commercially available

Flash programming equipment or via ISP or via software to operate

at 6 clocks per machine cycle, referred to in this datasheet as

“6-clock mode”. (This yields performance equivalent to twice that of

standard 80C51 family devices). Also see next page.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an

on-chip oscillator.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. Minimum and maximum

high and low times specified in the data sheet must be observed.

10

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

The CKCON register also provides individual control of the clock

rates for the peripherals devices. When running in 6-clock mode

each peripheral may be individually clocked from either fosc/6 or

fosc/12. When in 12-clock mode, all peripheral devices will use

fosc/12. The CKCON register is shown below.

CLOCK CONTROL REGISTER (CKCON)

This device provides control of the 6-clock/12-clock mode by means

of both an SFR bit (X2) and a Flash bit (FX2, located in the Security

Block). The Flash clock control bit, FX2, when programmed (6-clock

mode) supercedes the X2 bit (CKCON.0).

CKCON

Address = 8Fh

Reset Value = x0000000B

Not Bit Addressable

7

6

5

4

3

2

1

0

–

WDX2 PCAX2

SIX2

T2X2

T1X2

T0X2

X2

BIT

CKCON.7

SYMBOL FUNCTION

Reserved.

–

CKCON.6 WDX2

CKCON.5 PCAX2

CKCON.4 SIX2

CKCON.3 T2X2

CKCON.2 T1X2

CKCON.1 T0X2

CKCON.0 X2

Watchdog clock; 0 = 6 clocks for each WDT clock, 1 = 12 clocks for each WDT clock

PCA clock; 0 = 6 clocks for each PCA clock, 1 = 12 clocks for each PCA clock

UART clock; 0 = 6 clocks for each UART clock, 1 = 12 clocks for each UART clock

Timer2 clock; 0 = 6 clocks for each Timer2 clock, 1 = 12 clocks for each Timer2 clock

Timer1 clock; 0 = 6 clocks for each Timer1 clock, 1 = 12 clocks for each Timer1 clock

Timer0 clock; 0 = 6 clocks for each Timer0 clock, 1 = 12 clocks for each Timer0 clock

CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle

SU01607

Bits 1 through 6 only apply if 6 clocks per machine cycle is chosen

(i.e.– Bit 0 = 1). If Bit 0 = 0 (12 clocks per machine cycle) then all

peripherals will have 12 clocks per machine cycle as their clock

source.

Also please note that the clock divider applies to the serial port for

modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3

(variable baud rate modes) use either Timer 1 or Timer 2.

Below is the truth table for the peripheral input clock sources.

FX2 clock mode bit

X2

Peripheral clock

mode bit

CPU MODE

Peripheral Clock Rate

(e.g., T0X2)

erased

0

1

x

0

1

0

1

12-clock (default)

6-clock

12-clock (default)

6-clock

erased

6-clock

12-clock

programmed

6-clock

12-clock

RESET

A reset is accomplished by holding the RST pin high for at least two

machine cycles (12 oscillator periods in 6-clock mode, or 24 oscillator

periods in 12-clock mode), while the oscillator is running. To ensure a

good power-on reset, the RST pin must be high long enough to allow

the oscillator time to start up (normally a few milliseconds) plus two

machine cycles. At power-on, the voltage on V and RST must

CC

come up at the same time for a proper start-up. Ports 1, 2, and 3 will

asynchronously be driven to their reset condition when a voltage

above V

(min.) is applied to RST.

IH1

The value on the EA pin is latched when RST is deasserted and has

no further effect.

11

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

LOW POWER MODES

Stop Clock Mode

Design Consideration

The static design enables the clock speed to be reduced down to

0 MHz (stopped). When the oscillator is stopped, the RAM and

Special Function Registers retain their values. This mode allows

step-by-step utilization and permits reduced system power

consumption by lowering the clock frequency down to any value. For

lowest power consumption the Power Down mode is suggested.

When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to

two machine cycles before the internal reset algorithm takes control.

On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited. To eliminate the possibility of

an unexpected write when Idle is terminated by reset, the instruction

following the one that invokes Idle should not be one that writes to a

port pin or to external memory.

Idle Mode

In the idle mode (see Table 2), the CPU puts itself to sleep while all

of the on-chip peripherals stay active. The instruction to invoke the

idle mode is the last instruction executed in the normal operating

mode before the idle mode is activated. The CPU contents, the

on-chip RAM, and all of the special function registers remain intact

during this mode. The idle mode can be terminated either by any

enabled interrupt (at which time the process is picked up at the

interrupt service routine and continued), or by a hardware reset

which starts the processor in the same manner as a power-on reset.

ONCE Mode

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and

debugging of systems without the device having to be removed from

the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN is high;

2. Hold ALE low as RST is deactivated.

While the device is in ONCE Mode, the Port 0 pins go into a float

state, and the other port pins and ALE and PSEN are weakly pulled

high. The oscillator circuit remains active. While the device is in this

mode, an emulator or test CPU can be used to drive the circuit.

Normal operation is restored when a normal reset is applied.

Power-Down Mode

To save even more power, a Power Down mode (see Table 2) can

be invoked by software. In this mode, the oscillator is stopped and

the instruction that invoked Power Down is the last instruction

executed. The on-chip RAM and Special Function Registers retain

Programmable Clock-Out

A 50% duty cycle clock can be programmed to come out on P1.0.

This pin, besides being a regular I/O pin, has two alternate

functions. It can be programmed:

their values down to 2 V and care must be taken to return V to the

CC

minimum specified operating voltages before the Power Down Mode

is terminated.

1. to input the external clock for Timer/Counter 2, or

Either a hardware reset or external interrupt can be used to exit from

Power Down. Reset redefines all the SFRs but does not change the

on-chip RAM. An external interrupt allows both the SFRs and the

on-chip RAM to retain their values.

2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a

16 MHz operating frequency in 12-clock mode (122 Hz to 8 MHz in

6-clock mode).

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in

T2CON) must be cleared and bit T20E in T2MOD must be set. Bit

TR2 (T2CON.2) also must be set to start the timer.

To properly terminate Power Down, the reset or external interrupt

should not be executed before V is restored to its normal

CC

operating level and must be held active long enough for the

oscillator to restart and stabilize (normally less than 10 ms).

The Clock-Out frequency depends on the oscillator frequency and

the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)

as shown in this equation:

With an external interrupt, INT0 and INT1 must be enabled and

configured as level-sensitive. Holding the pin low restarts the oscillator

but bringing the pin back high completes the exit. Once the interrupt

is serviced, the next instruction to be executed after RETI will be the

one following the instruction that put the device into Power Down.

Oscillator Frequency

n (65536 * RCAP2H, RCAP2L)

n =

2 in 6-clock mode

4 in 12-clock mode

POWER-ON FLAG

The Power-On Flag (POF) is set by on-chip circuitry when the V

Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L

taken as a 16-bit unsigned integer.

CC

level on the P89C51RA2/RB2/RC2/RD2xx rises from 0 to 5 V. The

POF bit can be set or cleared by software allowing a user to

determine if the reset is the result of a power-on or a warm start

In the Clock-Out mode Timer 2 roll-overs will not generate an

interrupt. This is similar to when it is used as a baud-rate generator.

It is possible to use Timer 2 as a baud-rate generator and a clock

generator simultaneously. Note, however, that the baud-rate and the

Clock-Out frequency will be the same.

after powerdown. The V level must remain above 3 V for the POF

CC

to remain unaffected by the V level.

CC

Table 2. External Pin Status During Idle and Power-Down Mode

MODE

PROGRAM MEMORY

Internal

ALE

PSEN

PORT 0

Data

PORT 1

Data

PORT 2

Data

PORT 3

Data

Idle

1

0

1

0

External

Float

Data

Address

Data

Power-down

Internal

Data

External

Float

Data

12

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Mode 1

TIMER 0 AND TIMER 1 OPERATION

Mode 1 is the same as Mode 0, except that the Timer register is

being run with all 16 bits.

Timer 0 and Timer 1

The “Timer” or “Counter” function is selected by control bits C/T in

the Special Function Register TMOD. These two Timer/Counters

have four operating modes, which are selected by bit-pairs (M1, M0)

in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters.

Mode 3 is different. The four operating modes are described in the

following text.

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with

automatic reload, as shown in Figure 4. Overflow from TLn not only

sets TFn, but also reloads TLn with the contents of THn, which is

preset by software. The reload leaves THn unchanged.

Mode 2 operation is the same for Timer 0 as for Timer 1.

Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer,

which is an 8-bit Counter with a divide-by-32 prescaler. Figure 2

shows the Mode 0 operation.

Mode 3

Timer 1 in Mode 3 simply holds its count. The effect is the same as

setting TR1 = 0.

In this mode, the Timer register is configured as a 13-bit register. As

the count rolls over from all 1s to all 0s, it sets the Timer interrupt

flag TFn. The counted input is enabled to the Timer when TRn = 1

and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the

Timer to be controlled by external input INTn, to facilitate pulse width

measurements). TRn is a control bit in the Special Function Register

TCON (Figure 3).

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate

counters. The logic for Mode 3 on Timer 0 is shown in Figure 5. TL0

uses the Timer 0 control bits: C/T, GATE, TR0, and TF0 as well as

pin INT0. TH0 is locked into a timer function (counting machine

cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus,

TH0 now controls the “Timer 1” interrupt.

Mode 3 is provided for applications requiring an extra 8-bit timer on

the counter. With Timer 0 in Mode 3, an 80C51 can look like it has

three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be

turned on and off by switching it out of and into its own Mode 3, or

can still be used by the serial port as a baud rate generator, or in

fact, in any application not requiring an interrupt.

The 13-bit register consists of all 8 bits of THn and the lower 5 bits

of TLn. The upper 3 bits of TLn are indeterminate and should be

ignored. Setting the run flag (TRn) does not clear the registers.

Mode 0 operation is the same for Timer 0 as for Timer 1. There are

two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer

0 (TMOD.3).

TMOD

Address = 89H

Reset Value = 00H

Not Bit Addressable

7

6

5

4

3

2

1

0

GATE C/T

M1

M0 GATE

C/T

M1

M0

TIMER 1

TIMER 0

BIT

SYMBOL FUNCTION

TMOD.3/ GATE

TMOD.7

Gating control when set. Timer/Counter “n” is enabled only while “INTn” pin is high and

“TRn” control pin is set. when cleared Timer “n” is enabled whenever “TRn” control bit is set.

TMOD.2/ C/T

TMOD.6

Timer or Counter Selector cleared for Timer operation (input from internal system clock.)

Set for Counter operation (input from “Tn” input pin).

M1 M0

OPERATING

0

1

0

1

0

8048 Timer: “TLn” serves as 5-bit prescaler.

16-bit Timer/Counter: “THn” and “TLn” are cascaded; there is no prescaler.

8-bit auto-reload Timer/Counter: “THn” holds a value which is to be reloaded

into “TLn” each time it overflows.

1

(Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.

TH0 is an 8-bit timer only controlled by Timer 1 control bits.

(Timer 1) Timer/Counter 1 stopped.

SU01580

Figure 1. Timer/Counter 0/1 Mode Control (TMOD) Register

13

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

OSC

÷ d*

C/T = 0

C/T = 1

TLn

(5 Bits)

THn

(8 Bits)

TFn

Interrupt

Control

Tn Pin

TRn

Timer n

Gate bit

INTn Pin

*d = 6 in 6-clock mode; d = 12 in 12-clock mode.

SU01618

Figure 2. Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter

TCON

Address = 88H

Bit Addressable

Reset Value = 00H

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

BIT

SYMBOL FUNCTION

TCON.7

TF1

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.

Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software.

TCON.6

TCON.5

TR1

TF0

Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off.

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.

Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software.

TCON.4

TCON.3

TR0

IE1

Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off.

Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed.

TCON.2

TCON.1

TCON.0

IT1

IE0

IT0

Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered

external interrupts.

Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed.

Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level

triggered external interrupts.

SU01516

Figure 3. Timer/Counter 0/1 Control (TCON) Register

14

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

OSC

÷ d*

C/T = 0

C/T = 1

TLn

(8 Bits)

TFn

Interrupt

Control

Tn Pin

Reload

TRn

Timer n

Gate bit

THn

(8 Bits)

INTn Pin

SU01619

*d = 6 in 6-clock mode; d = 12 in 12-clock mode.

Figure 4. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload

OSC

÷ d*

C/T = 0

TL0

TF0

Interrupt

(8 Bits)

C/T = 1

Control

T0 Pin

TR0

Timer 0

Gate bit

INT0 Pin

TH0

(8 Bits)

TF1

Interrupt

OSC

÷ d*

Control

TR1

*d = 6 in 6-clock mode; d = 12 in 12-clock mode.

SU01620

Figure 5. Timer/Counter 0 Mode 3: Two 8-Bit Counters

15

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Counter Enable) which is located in the T2MOD register (see

Figure 8). When reset is applied the DCEN=0 which means Timer 2

will default to counting up. If DCEN bit is set, Timer 2 can count up

or down depending on the value of the T2EX pin.

TIMER 2 OPERATION

Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an

event timer or an event counter, as selected by C/T2 in the special

function register T2CON (see Figure 6). Timer 2 has three operating

modes: Capture, Auto-reload (up or down counting), and Baud Rate

Generator, which are selected by bits in the T2CON as shown in

Table 3.

Figure 9 shows Timer 2 which will count up automatically since

DCEN=0. In this mode there are two options selected by bit EXEN2

in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH

and sets the TF2 (Overflow Flag) bit upon overflow. This causes the

Timer 2 registers to be reloaded with the 16-bit value in RCAP2L

and RCAP2H. The values in RCAP2L and RCAP2H are preset by

software means.

Capture Mode

In the capture mode there are two options which are selected by bit

EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or

counter (as selected by C/T2 in T2CON) which, upon overflowing

sets bit TF2, the timer 2 overflow bit. This bit can be used to

generate an interrupt (by enabling the Timer 2 interrupt bit in the

IE register). If EXEN2= 1, Timer 2 operates as described above, but

with the added feature that a 1- to -0 transition at external input

T2EX causes the current value in the Timer 2 registers, TL2 and

TH2, to be captured into registers RCAP2L and RCAP2H,

respectively. In addition, the transition at T2EX causes bit EXF2 in

T2CON to be set, and EXF2 like TF2 can generate an interrupt

(which vectors to the same location as Timer 2 overflow interrupt.

The Timer 2 interrupt service routine can interrogate TF2 and EXF2

to determine which event caused the interrupt). The capture mode is

illustrated in Figure 7 (There is no reload value for TL2 and TH2 in

this mode. Even when a capture event occurs from T2EX, the

counter keeps on counting T2EX pin transitions or osc/6 pulses

(osc/12 in 12-clock mode).).

If EXEN2=1, then a 16-bit reload can be triggered either by an

overflow or by a 1-to-0 transition at input T2EX. This transition also

sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be

generated when either TF2 or EXF2 are 1.

In Figure 10 DCEN=1 which enables Timer 2 to count up or down.

This mode allows pin T2EX to control the direction of count. When a

logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will

overflow at 0FFFFH and set the TF2 flag, which can then generate

an interrupt, if the interrupt is enabled. This timer overflow also

causes the 16-bit value in RCAP2L and RCAP2H to be reloaded

into the timer registers TL2 and TH2.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count

down. The timer will underflow when TL2 and TH2 become equal to

the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets

the TF2 flag and causes 0FFFFH to be reloaded into the timer

registers TL2 and TH2.

Auto-Reload Mode (Up or Down Counter)

The external flag EXF2 toggles when Timer 2 underflows or overflows.

This EXF2 bit can be used as a 17th bit of resolution if needed. The

EXF2 flag does not generate an interrupt in this mode of operation.

In the 16-bit auto-reload mode, Timer 2 can be configured (as either

a timer or counter [C/T2 in T2CON]) then programmed to count up

or down. The counting direction is determined by bit DCEN (Down

(MSB)

(LSB)

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Symbol

Position

Name and Significance

TF2

T2CON.7

T2CON.6

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set

when either RCLK or TCLK = 1.

EXF2

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2

interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down

counter mode (DCEN = 1).

RCLK

TCLK

T2CON.5

T2CON.4

T2CON.3

Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock

in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock

in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to

ignore events at T2EX.

TR2

T2CON.2

T2CON.1

Start/stop control for Timer 2. A logic 1 starts the timer.

C/T2

Timer or counter select. (Timer 2)

0 = Internal timer (OSC/6 in 6-clock mode or OSC/12 in 12-clock mode)

1 = External event counter (falling edge triggered).

CP/RL2

T2CON.0

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When

cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when

EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload

on Timer 2 overflow.

SU01251

Figure 6. Timer/Counter 2 (T2CON) Control Register

16

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Table 3. Timer 2 Operating Modes

RCLK + TCLK

CP/RL2

TR2

1

MODE

16-bit Auto-reload

16-bit Capture

0

1

X

0

1

X

1

Baud rate generator

(off)

0

OSC

÷ n*

C/T2 = 0

TL2

(8 BITS)

TH2

(8 BITS)

TF2

C/T2 = 1

T2 Pin

Control

TR2

Capture

Transition

Detector

Timer 2

Interrupt

RCAP2L

RCAP2H

T2EX Pin

EXF2

Control

EXEN2

SU01252

* n = 6 in 6-clock mode, or 12 in 12-clock mode.

Figure 7. Timer 2 in Capture Mode

T2MOD

Address = 0C9H

Not Bit Addressable

—

Reset Value = XXXX XX00B

—

6

—

5

—

4

—

3

—

2

T2OE

1

DCEN

0

Bit

7

Symbol

Function

—

Not implemented, reserved for future use.*

Timer 2 Output Enable bit.

T2OE

DCEN

Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.

*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.

In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

SU00729

Figure 8. Timer 2 Mode (T2MOD) Control Register

17

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

OSC

÷ n*

C/T2 = 0

TL2

(8 BITS)

TH2

(8 BITS)

C/T2 = 1

T2 PIN

CONTROL

TR2

RELOAD

TRANSITION

DETECTOR

RCAP2L

RCAP2H

TF2

TIMER 2

INTERRUPT

T2EX PIN

EXF2

CONTROL

EXEN2

SU01253

* n = 6 in 6-clock mode, or 12 in 12-clock mode.

Figure 9. Timer 2 in Auto-Reload Mode (DCEN = 0)

(DOWN COUNTING RELOAD VALUE)

FFH

TOGGLE

EXF2

÷ n*

OSC

C/T2 = 0

C/T2 = 1

OVERFLOW

TL2

TH2

TF2

INTERRUPT

T2 PIN

CONTROL

TR2

COUNT

DIRECTION

1 = UP

0 = DOWN

RCAP2L

RCAP2H

(UP COUNTING RELOAD VALUE)

T2EX PIN

* n = 6 in 6-clock mode, or 12 in 12-clock mode.

SU01254

Figure 10. Timer 2 Auto Reload Mode (DCEN = 1)

18

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Timer 1

Overflow

n = 1 in 6-clock mode

n = 2 in 12-clock mode

÷ 2

“0”

“1”

OSC

÷ n

C/T2 = 0

C/T2 = 1

SMOD

RCLK

“1”

TL2

(8-bits)

TH2

(8-bits)

T2 Pin

Control

RX Clock

÷ 16

“1”

“0”

TR2

Reload

TCLK

Transition

Detector

RCAP2L

RCAP2H

TX Clock

Timer 2

Interrupt

T2EX Pin

EXF2

Control

EXEN2

Note availability of additional external interrupt.

SU01629

Figure 11. Timer 2 in Baud Rate Generator Mode

The baud rates in modes 1 and 3 are determined by Timer 2’s

overflow rate given below:

Table 4. Timer 2 Generated Commonly Used

Baud Rates

Timer 2 Overflow Rate

Modes 1 and 3 Baud Rates +

Baud Rate

Timer 2

16

Osc Freq

12-clock

mode

6-clock

mode

The timer can be configured for either “timer” or “counter” operation.

In many applications, it is configured for “timer” operation (C/T2=0).

Timer operation is different for Timer 2 when it is being used as a

baud rate generator.

RCAP2H

RCAP2L

375 k

9.6 k

4.8 k

2.4 k

1.2 k

300

110

300

110

750 k

19.2 k

9.6 k

4.8 k

2.4 k

600

220

600

220

12 MHz

6 MHz

FF

FE

FB

F2

FD

F9

FF

D9

B2

64

C8

1E

AF

8F

57

Usually, as a timer it would increment every machine cycle (i.e.,

1

/ the oscillator frequency in 6-clock mode, / the oscillator

6

12

frequency in 12-clock mode). As a baud rate generator, it

OSC

increments at the oscillator frequency in 6-clock mode (

12-clock mode). Thus the baud rate formula is as follows:

/ in

2

Modes 1 and 3 Baud Rates =

Oscillator Frequency

6 MHz

[ n * [65536 * (RCAP2H, RCAP2L)]]

* n =

16 in 6-clock mode

32 in 12-clock mode

Baud Rate Generator Mode

Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port

transmit and receive baud rates to be derived from either Timer 1 or

Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit

baud rate generator. When TCLK= 1, Timer 2 is used as the serial

port transmit baud rate generator. RCLK has the same effect for the

serial port receive baud rate. With these two bits, the serial port can

have different receive and transmit baud rates – one generated by

Timer 1, the other by Timer 2.

Where: (RCAP2H, RCAP2L)= The content of RCAP2H and

RCAP2L taken as a 16-bit unsigned integer.

The Timer 2 as a baud rate generator mode shown in Figure 11, is

valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a

rollover in TH2 does not set TF2, and will not generate an interrupt.

Thus, the Timer 2 interrupt does not have to be disabled when

Timer 2 is in the baud rate generator mode. Also if the EXEN2

(T2 external enable flag) is set, a 1-to-0 transition in T2EX

(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but

will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).

Therefore when Timer 2 is in use as a baud rate generator, T2EX

can be used as an additional external interrupt, if needed.

Figure 11 shows the Timer 2 in baud rate generation mode. The baud

rate generation mode is like the auto-reload mode,in that a rollover in

TH2 causes the Timer 2 registers to be reloaded with the 16-bit value

in registers RCAP2H and RCAP2L, which are preset by software.

19

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

When Timer 2 is in the baud rate generator mode, one should not try

to read or write TH2 and TL2. As a baud rate generator, Timer 2 is

incremented every state time (osc/2) or asynchronously from pin T2;

under these conditions, a read or write of TH2 or TL2 may not be

accurate. The RCAP2 registers may be read, but should not be

written to, because a write might overlap a reload and cause write

and/or reload errors. The timer should be turned off (clear TR2)

before accessing the Timer 2 or RCAP2 registers.

If Timer 2 is being clocked internally, the baud rate is:

f_OSC

Baud Rate +

[ n * [65536 * (RCAP2H, RCAP2L)]]

* n =

16 in 6-clock mode

32 in 12-clock mode

Where f

= Oscillator Frequency

OSC

To obtain the reload value for RCAP2H and RCAP2L, the above

equation can be rewritten as:

Table 4 shows commonly used baud rates and how they can be

obtained from Timer 2.

f_OSC

_{RCAP2H, RCAP2L + 65536 *}ǒ

Ǔ

Summary of Baud Rate Equations

Timer 2 is in baud rate generating mode. If Timer 2 is being clocked

through pin T2 (P1.0) the baud rate is:

n * Baud Rate

Timer/Counter 2 Set-up

Timer 2 Overflow Rate

Except for the baud rate generator mode, the values given for T2CON

do not include the setting of the TR2 bit. Therefore, bit TR2 must be

set, separately, to turn the timer on. see Table 5 for set-up of Timer 2

as a timer. Also see Table 6 for set-up of Timer 2 as a counter.

Baud Rate +

16

Table 5. Timer 2 as a Timer

T2CON

MODE

INTERNAL CONTROL

(Note 1)

EXTERNAL CONTROL

(Note 2)

16-bit Auto-Reload

00H

01H

34H

24H

14H

08H

09H

36H

26H

16H

16-bit Capture

Baud rate generator receive and transmit same baud rate

Receive only

Transmit only

Table 6. Timer 2 as a Counter

TMOD

MODE

INTERNAL CONTROL

(Note 1)

EXTERNAL CONTROL

(Note 2)

16-bit

02H

03H

0AH

0BH

Auto-Reload

NOTES:

1. Capture/reload occurs only on timer/counter overflow.

2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate

generator mode.

20

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

The slaves that weren’t being addressed leave their SM2s set and

go on about their business, ignoring the coming data bytes.

FULL-DUPLEX ENHANCED UART

Standard UART operation

SM2 has no effect in Mode 0, and in Mode 1 can be used to check

the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the

receive interrupt will not be activated unless a valid stop bit is

received.

The serial port is full duplex, meaning it can transmit and receive

simultaneously. It is also receive-buffered, meaning it can

commence reception of a second byte before a previously received

byte has been read from the register. (However, if the first byte still

hasn’t been read by the time reception of the second byte is

complete, one of the bytes will be lost.) The serial port receive and

transmit registers are both accessed at Special Function Register

SBUF. Writing to SBUF loads the transmit register, and reading

SBUF accesses a physically separate receive register.

Serial Port Control Register

The serial port control and status register is the Special Function

Register SCON, shown in Figure 12. This register contains not only

the mode selection bits, but also the 9th data bit for transmit and

receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).

The serial port can operate in 4 modes:

Baud Rates

The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator

Frequency / 12 (12-clock mode) or / 6 (6-clock mode). The baud

rate in Mode 2 depends on the value of bit SMOD in Special

Function Register PCON. If SMOD = 0 (which is the value on reset),

and the port pins in 12-clock mode, the baud rate is 1/64 the

oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator

frequency. In 6-clock mode, the baud rate is 1/32 or 1/16 the

oscillator frequency, respectively.

Mode 0: Serial data enters and exits through RxD. TxD outputs

the shift clock. 8 bits are transmitted/received (LSB first).

The baud rate is fixed at 1/12 the oscillator frequency in

12-clock mode or 1/6 the oscillator frequency in 6-clock

mode.

Mode 1: 10 bits are transmitted (through TxD) or received

(through RxD): a start bit (0), 8 data bits (LSB first), and

a stop bit (1). On receive, the stop bit goes into RB8 in

Special Function Register SCON. The baud rate is

variable.

Mode 2 Baud Rate =

2^SMOD

n

(Oscillator Frequency)

Mode 2: 11 bits are transmitted (through TxD) or received

(through RxD): start bit (0), 8 data bits (LSB first), a

programmable 9th data bit, and a stop bit (1). On

Transmit, the 9th data bit (TB8 in SCON) can be

assigned the value of 0 or 1. Or, for example, the parity

bit (P, in the PSW) could be moved into TB8. On receive,

the 9th data bit goes into RB8 in Special Function

Register SCON, while the stop bit is ignored. The baud

rate is programmable to either 1/32 or 1/64 the oscillator

frequency in 12-clock mode or 1/16 or 1/32 the oscillator

frequency in 6-clock mode.

Where:

n = 64 in 12-clock mode, 32 in 6-clock mode

The baud rates in Modes 1 and 3 are determined by the Timer 1 or

Timer 2 overflow rate.

Using Timer 1 to Generate Baud Rates

When Timer 1 is used as the baud rate generator (T2CON.RCLK

= 0, T2CON.TCLK = 0), the baud rates in Modes 1 and 3 are

determined by the Timer 1 overflow rate and the value of SMOD as

follows:

Mode 3: 11 bits are transmitted (through TxD) or received

(through RxD): a start bit (0), 8 data bits (LSB first), a

programmable 9th data bit, and a stop bit (1). In fact,

Mode 3 is the same as Mode 2 in all respects except

baud rate. The baud rate in Mode 3 is variable.

Mode 1, 3 Baud Rate =

2^SMOD

n

(Timer 1 Overflow Rate)

Where:

In all four modes, transmission is initiated by any instruction that

uses SBUF as a destination register. Reception is initiated in Mode 0

by the condition RI = 0 and REN = 1. Reception is initiated in the

other modes by the incoming start bit if REN = 1.

n = 32 in 12-clock mode, 16 in 6-clock mode

The Timer 1 interrupt should be disabled in this application. The

Timer itself can be configured for either “timer” or “counter”

operation, and in any of its 3 running modes. In the most typical

applications, it is configured for “timer” operation, in the auto-reload

mode (high nibble of TMOD = 0010B). In that case the baud rate is

given by the formula:

Multiprocessor Communications

Modes 2 and 3 have a special provision for multiprocessor

communications. In these modes, 9 data bits are received. The 9th

one goes into RB8. Then comes a stop bit. The port can be

programmed such that when the stop bit is received, the serial port

interrupt will be activated only if RB8 = 1. This feature is enabled by

setting bit SM2 in SCON. A way to use this feature in multiprocessor

systems is as follows:

Mode 1, 3 Baud Rate =

2^SMOD

n

Oscillator Frequency

12 [256–(TH1)]

Where:

When the master processor wants to transmit a block of data to one

of several slaves, it first sends out an address byte which identifies

the target slave. An address byte differs from a data byte in that the

9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no

slave will be interrupted by a data byte. An address byte, however,

will interrupt all slaves, so that each slave can examine the received

byte and see if it is being addressed. The addressed slave will clear

its SM2 bit and prepare to receive the data bytes that will be coming.

n = 32 in 12-clock mode, 16 in 6-clock mode

One can achieve very low baud rates with Timer 1 by leaving the

Timer 1 interrupt enabled, and configuring the Timer to run as a

16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1

interrupt to do a 16-bit software reload. Figure 13 lists various

commonly used baud rates and how they can be obtained from

Timer 1.

21

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

SCON

Address = 98H

Bit Addressable

Reset Value = 00H

7

6

5

4

3

2

1

0

SM0 SM1 SM2 REN TB8

RB8

TI

RI

Where SM0, SM1 specify the serial port mode, as follows:

SM0 SM1 Mode Description Baud Rate

/12 (12-clock mode) or f

0

1

0

1

0

1

0

1

2

3

shift register

8-bit UART

9-bit UART

f

/6 (6-clock mode)

OSC

variable

/64 or f

f

/32 (12-clock mode) or f

/32 or f

/16 (6-clock mode)

OSC

variable

SM2

Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be

activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not

received. In Mode 0, SM2 should be 0.

REN

TB8

RB8

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0,

RB8 is not used.

TI

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other

modes, in any serial transmission. Must be cleared by software.

RI

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other

modes, in any serial reception (except see SM2). Must be cleared by software.

SU01626

Figure 12. Serial Port Control (SCON) Register

Baud Rate

Timer 1

Mode

f

SMOD

OSC

Mode

12-clock mode

6-clock mode

C/T

Reload Value

Mode 0 Max

Mode 2 Max

Mode 1, 3 Max

Mode 1, 3

1.67 MHz

625 k

104.2 k

19.2 k

9.6 k

3.34 MHz

1250 k

208.4 k

38.4 k

19.2 k

9.6 k

20 MHz

X

1

0

X

0

X

2

1

X

20 MHz

FFH

FDH

FAH

F4H

E8H

1DH

72H

FEEBH

11.059 MHz

11.986 MHz

6 MHz

4.8 k

2.4 k

4.8 k

1.2 k

2.4 k

137.5

110

275

220

110

220

12 MHz

Figure 13. Timer 1 Generated Commonly Used Baud Rates

More About Mode 0

S6P2 of every machine cycle in which SEND is active, the contents

of the transmit shift are shifted to the right one position.

Serial data enters and exits through RxD. TxD outputs the shift

clock. 8 bits are transmitted/received: 8 data bits (LSB first). The

baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or

1/6 the oscillator frequency (6-clock mode).

As data bits shift out to the right, zeros come in from the left. When

the MSB of the data byte is at the output position of the shift register,

then the 1 that was initially loaded into the 9th position, is just to the

left of the MSB, and all positions to the left of that contain zeros.

This condition flags the TX Control block to do one last shift and

then deactivate SEND and set T1. Both of these actions occur at

S1P1 of the 10th machine cycle after “write to SBUF.”

Figure 14 shows a simplified functional diagram of the serial port in

Mode 0, and associated timing.

Transmission is initiated by any instruction that uses SBUF as a

destination register. The “write to SBUF” signal at S6P2 also loads a

1 into the 9th position of the transmit shift register and tells the TX

Control block to commence a transmission. The internal timing is

such that one full machine cycle will elapse between “write to SBUF”

and activation of SEND.

Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2

of the next machine cycle, the RX Control unit writes the bits

11111110 to the receive shift register, and in the next clock phase

activates RECEIVE.

RECEIVE enable SHIFT CLOCK to the alternate output function line

of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of

every machine cycle. At S6P2 of every machine cycle in which

RECEIVE is active, the contents of the receive shift register are

SEND enables the output of the shift register to the alternate output

function line of P3.0 and also enable SHIFT CLOCK to the alternate

output function line of P3.1. SHIFT CLOCK is low during S3, S4, and

S5 of every machine cycle, and high during S6, S1, and S2. At

22

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

shifted to the left one position. The value that comes in from the right

is the value that was sampled at the P3.0 pin at S5P2 of the same

machine cycle.

whether the above conditions are met or not, the unit goes back to

looking for a 1-to-0 transition in RxD.

More About Modes 2 and 3

As data bits come in from the right, 1s shift out to the left. When the

0 that was initially loaded into the rightmost position arrives at the

leftmost position in the shift register, it flags the RX Control block to

do one last shift and load SBUF. At S1P1 of the 10th machine cycle

after the write to SCON that cleared RI, RECEIVE is cleared as RI is

set.

Eleven bits are transmitted (through TxD), or received (through

RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data

bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be

assigned the value of 0 or 1. On receive, the 9the data bit goes into

RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64

(12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock

mode) the oscillator frequency in Mode 2. Mode 3 may have a

variable baud rate generated from Timer 1 or Timer 2.

More About Mode 1

Ten bits are transmitted (through TxD), or received (through RxD): a

start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the

stop bit goes into RB8 in SCON. In the 80C51 the baud rate is

determined by the Timer 1 or Timer 2 overflow rate.

Figures 16 and 17 show a functional diagram of the serial port in

Modes 2 and 3. The receive portion is exactly the same as in Mode

1. The transmit portion differs from Mode 1 only in the 9th bit of the

transmit shift register.

Figure 15 shows a simplified functional diagram of the serial port in

Mode 1, and associated timings for transmit receive.

Transmission is initiated by any instruction that uses SBUF as a

destination register. The “write to SBUF” signal also loads TB8 into

the 9th bit position of the transmit shift register and flags the TX

Control unit that a transmission is requested. Transmission

commences at S1P1 of the machine cycle following the next rollover

in the divide-by-16 counter. (Thus, the bit times are synchronized to

the divide-by-16 counter, not to the “write to SBUF” signal.)

Transmission is initiated by any instruction that uses SBUF as a

destination register. The “write to SBUF” signal also loads a 1 into

the 9th bit position of the transmit shift register and flags the TX

Control unit that a transmission is requested. Transmission actually

commences at S1P1 of the machine cycle following the next rollover

in the divide-by-16 counter. (Thus, the bit times are synchronized to

the divide-by-16 counter, not to the “write to SBUF” signal.)

The transmission begins with activation of SEND, which puts the

start bit at TxD. One bit time later, DATA is activated, which enables

the output bit of the transmit shift register to TxD. The first shift pulse

occurs one bit time after that. The first shift clocks a 1 (the stop bit)

into the 9th bit position of the shift register. Thereafter, only zeros

are clocked in. Thus, as data bits shift out to the right, zeros are

clocked in from the left. When TB8 is at the output position of the

shift register, then the stop bit is just to the left of TB8, and all

positions to the left of that contain zeros. This condition flags the TX

Control unit to do one last shift and then deactivate SEND and set

TI. This occurs at the 11th divide-by-16 rollover after “write to SUBF.”

The transmission begins with activation of SEND which puts the

start bit at TxD. One bit time later, DATA is activated, which enables

the output bit of the transmit shift register to TxD. The first shift pulse

occurs one bit time after that.

As data bits shift out to the right, zeros are clocked in from the left.

When the MSB of the data byte is at the output position of the shift

register, then the 1 that was initially loaded into the 9th position is

just to the left of the MSB, and all positions to the left of that contain

zeros. This condition flags the TX Control unit to do one last shift

and then deactivate SEND and set TI. This occurs at the 10th

divide-by-16 rollover after “write to SBUF.”

Reception is initiated by a detected 1-to-0 transition at RxD. For this

purpose RxD is sampled at a rate of 16 times whatever baud rate

has been established. When a transition is detected, the

divide-by-16 counter is immediately reset, and 1FFH is written to the

input shift register.

Reception is initiated by a detected 1-to-0 transition at RxD. For this

purpose RxD is sampled at a rate of 16 times whatever baud rate

has been established. When a transition is detected, the

divide-by-16 counter is immediately reset, and 1FFH is written into

the input shift register. Resetting the divide-by-16 counter aligns its

rollovers with the boundaries of the incoming bit times.

At the 7th, 8th, and 9th counter states of each bit time, the bit

detector samples the value of R-D. The value accepted is the value

that was seen in at least 2 of the 3 samples. If the value accepted

during the first bit time is not 0, the receive circuits are reset and the

unit goes back to looking for another 1-to-0 transition. If the start bit

proves valid, it is shifted into the input shift register, and reception of

the rest of the frame will proceed.

The 16 states of the counter divide each bit time into 16ths. At the

7th, 8th, and 9th counter states of each bit time, the bit detector

samples the value of RxD. The value accepted is the value that was

seen in at least 2 of the 3 samples. This is done for noise rejection.

If the value accepted during the first bit time is not 0, the receive

circuits are reset and the unit goes back to looking for another 1-to-0

transition. This is to provide rejection of false start bits. If the start bit

proves valid, it is shifted into the input shift register, and reception of

the rest of the frame will proceed.

As data bits come in from the right, 1s shift out to the left. When the

start bit arrives at the leftmost position in the shift register (which in

Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do

one last shift, load SBUF and RB8, and set RI.

The signal to load SBUF and RB8, and to set RI, will be generated

if, and only if, the following conditions are met at the time the final

shift pulse is generated.

1. RI = 0, and

2. Either SM2 = 0, or the received 9th data bit = 1.

As data bits come in from the right, 1s shift out to the left. When the

start bit arrives at the leftmost position in the shift register (which in

mode 1 is a 9-bit register), it flags the RX Control block to do one

last shift, load SBUF and RB8, and set RI. The signal to load SBUF

and RB8, and to set RI, will be generated if, and only if, the following

conditions are met at the time the final shift pulse is generated.:

1. R1 = 0, and

If either of these conditions is not met, the received frame is

irretrievably lost, and RI is not set. If both conditions are met, the

received 9th data bit goes into RB8, and the first 8 data bits go into

SBUF. One bit time later, whether the above conditions were met or

not, the unit goes back to looking for a 1-to-0 transition at the RxD

input.

2. Either SM2 = 0, or the received stop bit = 1.

If either of these two conditions is not met, the received frame is

irretrievably lost. If both conditions are met, the stop bit goes into

RB8, the 8 data bits go into SBUF, and RI is activated. At this time,

23

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

80C51 Internal Bus

Write

to

SBUF

RxD

P3.0 Alt

Output

S

D

Q

SBUF

CL

Function

Zero Detector

Start

Shift

TX Control

T1

S6

TX Clock

Send

Serial

Port

Interrupt

TxD

P3.1 Alt

Output

Function

Shift

Clock

R1

RX Clock

Start

Receive

Shift

RX Control

REN

RI

1

0

MSB

LSB

RxD

P3.0 Alt

Input

Input Shift Register

Function

Shift

Load

SBUF

LSB

MSB

SBUF

Read

SBUF

80C51 Internal Bus

S4 .

ALE

.

S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1

Write to SBUF

S6P2

Send

Shift

Transmit

RxD (Data Out)

D0

D1

D2

D3

D4

D5

D6

D7

TxD (Shift Clock)

TI

S3P1

S6P1

Write to SCON (Clear RI)

RI

Receive

Shift

Receive

RxD (Data In)

D0

D1

D2

D3

D4

D5

D6

D7

S5P2

TxD (Shift Clock)

SU00539

Figure 14. Serial Port Mode 0

24

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Timer 1

Overflow

80C51 Internal Bus

TB8

Write

to

÷ 2

SBUF

SMOD = 1

S

SMOD = 0

D

Q

SBUF

TxD

CL

Zero Detector

Start

Shift

Data

TX Control

T1

÷ 16

TX Clock

Send

Serial

Port

Interrupt

÷ 16

Load

SBUF

RX Clock RI

RX Control

Sample

1-to-0

Transition

Detector

Shift

Start

1FFH

Bit Detector

Input Shift Register

(9 Bits)

Shift

RxD

Load

SBUF

Read

SBUF

80C51 Internal Bus

TX

Clock

Write to SBUF

Send

S1P1

Data

Transmit

Shift

Start Bit

TxD

TI

D0

D1

D2

D3

D4

D5

D6

D7

Stop Bit

÷ 16 Reset

RX

Clock

Start

Bit

RxD

D0

D1

D2

D3

D4

D5

D6

D7

Stop Bit

Bit Detector

Receive

Sample Times

Shift

RI

SU00540

Figure 15. Serial Port Mode 1

25

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

80C51 Internal Bus

TB8

Write

to

SBUF

S

D

Q

SBUF

TxD

CL

Phase 2 Clock

(1/2 f

)

OSC

Zero Detector

Mode 2

Stop Bit

Gen.

Shift

Data

Start

TX Control

÷ 16

TX Clock

T1

Send

SMOD = 1

SMOD = 0

Serial

Port

Interrupt

÷ 2

÷ 16

(SMOD is

PCON.7)

Load

SBUF

R1

RX Clock

Sample

RX Control

1-to-0

Transition

Detector

Shift

Start

1FFH

Bit Detector

Input Shift Register

(9 Bits)

Shift

RxD

Load

SBUF

Read

SBUF

80C51 Internal Bus

TX

Clock

Write to SBUF

Send

S1P1

Data

Transmit

Shift

Start Bit

TxD

TI

D0

D1

D2

D3

D4

D5

D6

D7

TB8

Stop Bit

Stop Bit Gen.

÷ 16 Reset

RX

Clock

Start

Bit

RxD

D0

D1

D2

D3

D4

D5

D6

D7

RB8

Stop Bit

Bit Detector

Receive

Sample Times

Shift

RI

SU00541

Figure 16. Serial Port Mode 2

26

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Timer 1

Overflow

80C51 Internal Bus

TB8

Write

to

SBUF

÷ 2

SMOD = 1

S

SMOD = 0

D

Q

SBUF

TxD

CL

Zero Detector

Start

Shift

Data

TX Control

T1

÷ 16

TX Clock

Send

Serial

Port

Interrupt

÷ 16

Load

SBUF

R1

RX Clock

Sample

RX Control

1-to-0

Transition

Detector

Shift

Start

1FFH

Bit Detector

Input Shift Register

(9 Bits)

Shift

RxD

Load

SBUF

Read

SBUF

80C51 Internal Bus

TX

Clock

Write to SBUF

Send

S1P1

Data

Transmit

Shift

Start Bit

TxD

TI

D0

D1

D2

D3

D4

D5

D6

D7

TB8

Stop Bit

Stop Bit Gen.

÷ 16 Reset

RX

Clock

Start

Bit

RxD

D0

D1

D2

D3

D4

D5

D6

D7

RB8

Stop Bit

Bit Detector

Receive

Sample Times

Shift

RI

SU00542

Figure 17. Serial Port Mode 3

27

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Slave 1

SADDR

SADEN

Given

=

1100 0000

1111 1110

1100 000X

Enhanced UART

In addition to the standard operation the UART can perform framing

error detect by looking for missing stop bits, and automatic address

recognition. The UART also fully supports multiprocessor

In the above example SADDR is the same and the SADEN data is

used to differentiate between the two slaves. Slave 0 requires a 0 in

bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is

ignored. A unique address for Slave 0 would be 1100 0010 since

slave 1 requires a 0 in bit 1. A unique address for slave 1 would be

1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be

selected at the same time by an address which has bit 0 = 0 (for

slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed

with 1100 0000.

communication as does the standard 80C51 UART.

When used for framing error detect the UART looks for missing stop

bits in the communication. A missing bit will set the FE bit in the

SCON register. The FE bit shares the SCON.7 bit with SM0 and the

function of SCON.7 is determined by PCON.6 (SMOD0) (see

Figure 18). If SMOD0 is set then SCON.7 functions as FE. SCON.7

functions as SM0 when SMOD0 is cleared. When used as FE

SCON.7 can only be cleared by software. Refer to Figure 19.

In a more complex system the following could be used to select

slaves 1 and 2 while excluding slave 0:

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART

to recognize certain addresses in the serial bit stream by using

hardware to make the comparisons. This feature saves a great deal

of software overhead by eliminating the need for the software to

examine every serial address which passes by the serial port. This

feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART

modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be

automatically set when the received byte contains either the “Given”

address or the “Broadcast” address. The 9-bit mode requires that

the 9th information bit is a 1 to indicate that the received information

is an address and not data. Automatic address recognition is shown

in Figure 20.

Slave 0

Slave 1

Slave 2

SADDR

SADEN

Given

=

1100 0000

1111 1001

1100 0XX0

SADDR

SADEN

Given

=

1110 0000

1111 1010

1110 0X0X

SADDR

SADEN

Given

=

1110 0000

1111 1100

1110 00XX

In the above example the differentiation among the 3 slaves is in the

lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be

uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and

it can be uniquely addressed by 1110 and 0101. Slave 2 requires

that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0

and 1 and exclude Slave 2 use address 1110 0100, since it is

necessary to make bit 2 = 1 to exclude slave 2.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set

if SM2 is enabled and the information received has a valid stop bit

following the 8 address bits and the information is either a Given or

Broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored.

Using the Automatic Address Recognition feature allows a master to

selectively communicate with one or more slaves by invoking the

Given slave address or addresses. All of the slaves may be

contacted by using the Broadcast address. Two special Function

Registers are used to define the slave’s address, SADDR, and the

address mask, SADEN. SADEN is used to define which bits in the

SADDR are to b used and which bits are “don’t care”. The SADEN

mask can be logically ANDed with the SADDR to create the “Given”

address which the master will use for addressing each of the slaves.

Use of the Given address allows multiple slaves to be recognized

while excluding others. The following examples will help to show the

versatility of this scheme:

The Broadcast Address for each slave is created by taking the

logical OR of SADDR and SADEN. Zeros in this result are trended

as don’t-cares. In most cases, interpreting the don’t-cares as ones,

the broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR

address 0B9H) are leaded with 0s. This produces a given address

of all “don’t cares” as well as a Broadcast address of all “don’t

cares”. This effectively disables the Automatic Addressing mode and

allows the microcontroller to use standard 80C51 type UART drivers

which do not make use of this feature.

Slave 0

SADDR

SADEN

Given

=

1100 0000

1111 1101

1100 00X0

28

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

SCON Address = 98H

Reset Value = 0000 0000B

Bit Addressable

SM0/FE

SM1

SM2

REN

TB8

RB8

Tl

Rl

Bit:

7

6

5

4

3

2

1

0

(SMOD0 = 0/1)*

Symbol

FE

Function

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

SM1

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate**

0

1

0

1

0

1

2

shift register

8-bit UART

9-bit UART

f

/6 (6-clock mode) or f

/12 (12-clock mode)

OSC

variable

f

/32 or f

/64 or f

/16 (6-clock mode) or

/32 (12-clock mode)

OSC

1

3

9-bit UART

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.

In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a

Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

TB8

RB8

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6.

**f = oscillator frequency

OSC

SU01255

Figure 18. SCON: Serial Port Control Register

29

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

D0

D1

D2

D3

D4

D5

D6

D7

D8

START

BIT

DATA BYTE

ONLY IN

MODE 2, 3

STOP

BIT

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

SCON

(98H)

SM0 / FE

SMOD1

SM1

SM2

REN

POF

TB8

LVF

RB8

GF0

TI

RI

PCON

(87H)

SMOD0

–

GF1

IDL

0 : SCON.7 = SM0

1 : SCON.7 = FE

SU00044

Figure 19. UART Framing Error Detection

D0

D1

D2

D3

D4

D5

D6

D7

D8

SCON

(98H)

SM0

SM1

SM2

REN

1

TB8

X

RB8

TI

RI

1

0

1

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”

– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

SU00045

Figure 20. UART Multiprocessor Communication, Automatic Address Recognition

30

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

The priority scheme for servicing the interrupts is the same as that

for the 80C51, except there are four interrupt levels rather than two

as on the 80C51. An interrupt will be serviced as long as an interrupt

of equal or higher priority is not already being serviced. If an

interrupt of equal or higher level priority is being serviced, the new

interrupt will wait until it is finished before being serviced. If a lower

priority level interrupt is being serviced, it will be stopped and the

new interrupt serviced. When the new interrupt is finished, the lower

priority level interrupt that was stopped will be completed.

Interrupt Priority Structure

The P89C51RA2/RB2/RC2/RD2xx has a 7 source four-level

interrupt structure (see Table 7).

There are 3 SFRs associated with the four-level interrupt. They are

the IE, IP, and IPH. (See Figures 21, 22, and 23.) The IPH (Interrupt

Priority High) register makes the four-level interrupt structure

possible. The IPH is located at SFR address B7H. The structure of

the IPH register and a description of its bits is shown in Figure 23.

The function of the IPH SFR, when combined with the IP SFR,

determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPH.x

IP.x

0

1

Level 0 (lowest priority)

Level 1

1

0

Level 2

1

Level 3 (highest priority)

Table 7.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

1

2

X0

T0

1

2

3

4

5

IE0

TP0

IE1

N (L) Y (T)

03H

0BH

13H

1BH

33H

Y

X1

N (L) Y (T)

T1

TF1

Y

N

PCA

CF, CCFn

n = 0–4

SP

T2

6

7

RI, TI

N

23H

2BH

TF2, EXF2

NOTES:

1. L = Level activated

2. T = Transition activated

7

6

5

4

3

2

1

0

IE (0A8H)

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables it.

BIT

SYMBOL FUNCTION

IE.7

EA

Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually

enabled or disabled by setting or clearing its enable bit.

PCA interrupt enable bit

Timer 2 interrupt enable bit.

Serial Port interrupt enable bit.

Timer 1 interrupt enable bit.

External interrupt 1 enable bit.

Timer 0 interrupt enable bit.

IE.6

IE.5

IE.4

IE.3

IE.2

IE.1

IE.0

EC

ET2

ES

ET1

EX1

ET0

EX0

External interrupt 0 enable bit.

SU01290

Figure 21. IE Registers

31

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

7

6

5

4

3

2

1

0

IP (0B8H)

–

PPC

PT2

PS

PT1

PX1

PT0

PX0

Priority Bit = 1 assigns high priority

Priority Bit = 0 assigns low priority

BIT

IP.7

IP.6

IP.5

IP.4

IP.3

IP.2

IP.1

IP.0

SYMBOL FUNCTION

–

PPC

PT2

PS

PT1

PX1

PT0

PX0

PCA interrupt priority bit

Timer 2 interrupt priority bit.

Serial Port interrupt priority bit.

Timer 1 interrupt priority bit.

External interrupt 1 priority bit.

Timer 0 interrupt priority bit.

External interrupt 0 priority bit.

SU01291

Figure 22. IP Registers

7

6

5

4

3

2

1

0

IPH (B7H)

–

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Priority Bit = 1 assigns higher priority

Priority Bit = 0 assigns lower priority

BIT

SYMBOL FUNCTION

IPH.7

IPH.6

IPH.5

IPH.4

IPH.3

IPH.2

IPH.1

IPH.0

–

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

PCA interrupt priority bit

Timer 2 interrupt priority bit high.

Serial Port interrupt priority bit high.

Timer 1 interrupt priority bit high.

External interrupt 1 priority bit high.

Timer 0 interrupt priority bit high.

External interrupt 0 priority bit high.

SU01292

Figure 23. IPH Registers

32

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

be quickly toggled simply by executing an INC AUXR1 instruction

without affecting the GF2 bit.

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register when set disables the

ALE output unless the CPU needs to perform an off-chip memory

access.

The ENBOOT bit determines whether the BOOTROM is enabled

or disabled. This bit will automatically be set if the status byte is

non zero during reset or PSEN is pulled low, ALE floats high, and

Reduced EMI Mode

EA > V on the falling edge of reset. Otherwise, this bit will be

IH

cleared during reset.

AUXR (8EH)

7

–

6

–

5

–

4

–

3

–

2

–

1

0

EXTRAM

AO

DPS

BIT0

AUXR.1

AUXR.0

EXTRAM

AO

AUXR1

DPTR1

DPTR0

See more detailed description in Figure 38.

DPH

(83H)

DPL

(82H)

Dual DPTR

EXTERNAL

DATA

MEMORY

The dual DPTR structure (see Figure 24) is a way by which the chip

will specify the address of an external data memory location. There

are two 16-bit DPTR registers that address the external memory,

and a single bit called DPS = AUXR1/bit0 that allows the program

code to switch between them.

SU00745A

Figure 24.

• New Register Name: AUXR1#

• SFR Address: A2H

• Reset Value: xxxxxxx0B

DPTR Instructions

The instructions that refer to DPTR refer to the data pointer that is

currently selected using the AUXR1/bit 0 register. The six

instructions that use the DPTR are as follows:

AUXR1 (A2H)

INC DPTR

Increments the data pointer by 1

7

–

6

–

5

4

–

3

2

0

1

–

0

ENBOOT

GF2

DPS

MOV DPTR, #data16 Loads the DPTR with a 16-bit constant

Where:

MOV A, @ A+DPTR

MOVX A, @ DPTR

Move code byte relative to DPTR to ACC

DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.

Move external RAM (16-bit address) to

ACC

Select Reg

DPS

DPTR0

DPTR1

0

1

MOVX @ DPTR , A

JMP @ A + DPTR

Move ACC to external RAM (16-bit

address)

Jump indirect relative to DPTR

The DPS bit status should be saved by software when switching

between DPTR0 and DPTR1.

The data pointer can be accessed on a byte-by-byte basis by

specifying the low or high byte in an instruction which accesses the

SFRs. See Application Note AN458 for more details.

The GF2 bit is a general purpose user-defined flag. Note that bit 2 is

not writable and is always read as a zero. This allows the DPS bit to

33

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

the PCA counter overflows and an interrupt will be generated if the

ECF bit in the CMOD register is set, The CF bit can only be cleared

by software. Bits 0 through 4 of the CCON register are the flags for

the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set

by hardware when either a match or a capture occurs. These flags

also can only be cleared by software. The PCA interrupt system

shown in Figure 27.

Programmable Counter Array (PCA)

The Programmable Counter Array available on the

P89C51RA2/RB2/RC2/RD2xx is a special 16-bit Timer that has five

16-bit capture/compare modules associated with it. Each of the

modules can be programmed to operate in one of four modes: rising

and/or falling edge capture, software timer, high-speed output, or

pulse width modulator. Each module has a pin associated with it in

port 1. Module 0 is connected to P1.3 (CEX0), module 1 to P1.4

(CEX1), etc. The basic PCA configuration is shown in Figure 25.

Each module in the PCA has a special function register associated

with it. These registers are: CCAPM0 for module 0, CCAPM1 for

module 1, etc. (see Figure 30). The registers contain the bits that

control the mode that each module will operate in. The ECCF bit

(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)

enables the CCF flag in the CCON SFR to generate an interrupt

when a match or compare occurs in the associated module. PWM

(CCAPMn.1) enables the pulse width modulation mode. The TOG

bit (CCAPMn.2) when set causes the CEX output associated with

the module to toggle when there is a match between the PCA

counter and the module’s capture/compare register. The match bit

MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON

register to be set when there is a match between the PCA counter

and the module’s capture/compare register.

The PCA timer is a common time base for all five modules and can

be programmed to run at: 1/6 the oscillator frequency, 1/2 the

oscillator frequency, the Timer 0 overflow, or the input on the ECI pin

(P1.2). The timer count source is determined from the CPS1 and

CPS0 bits in the CMOD SFR as follows (see Figure 28):

CPS1 CPS0 PCA Timer Count Source

0

1/6 oscillator frequency (6-clock mode);

1/12 oscillator frequency (12-clock mode)

1/2 oscillator frequency (6-clock mode);

1/4 oscillator frequency (12-clock mode)

Timer 0 overflow

0

1

0

1

External Input at ECI pin

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)

determine the edge that a capture input will be active on. The CAPN

bit enables the negative edge, and the CAPP bit enables the positive

edge. If both bits are set both edges will be enabled and a capture will

occur for either transition. The last bit in the register ECOM

In the CMOD SFR are three additional bits associated with the PCA.

They are CIDL which allows the PCA to stop during idle mode,

WDTE which enables or disables the watchdog function on

module 4, and ECF which when set causes an interrupt and the

PCA overflow flag CF (in the CCON SFR) to be set when the PCA

timer overflows. These functions are shown in Figure 26.

(CCAPMn.6) when set enables the comparator function. Figure 31

shows the CCAPMn settings for the various PCA functions.

The watchdog timer function is implemented in module 4 (see

Figure 35).

There are two additional registers associated with each of the PCA

modules. They are CCAPnH and CCAPnL and these are the

registers that store the 16-bit count when a capture occurs or a

compare should occur. When a module is used in the PWM mode

these registers are used to control the duty cycle of the output.

The CCON SFR contains the run control bit for the PCA and the

flags for the PCA timer (CF) and each module (refer to Figure 29).

To run the PCA the CR bit (CCON.6) must be set by software. The

PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when

16 BITS

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

MODULE 0

MODULE 1

MODULE 2

MODULE 3

MODULE 4

16 BITS

PCA TIMER/COUNTER

TIME BASE FOR PCA MODULES

MODULE FUNCTIONS:

16-BIT CAPTURE

16-BIT TIMER

P1.7/CEX4

SU00032

16-BIT HIGH SPEED OUTPUT

8-BIT PWM

WATCHDOG TIMER (MODULE 4 ONLY)

Figure 25. Programmable Counter Array (PCA)

34

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

TO PCA

MODULES

OSC/6 (6 CLOCK MODE)

OR

OSC/12 (12 CLOCK MODE)

OSC/2 (6 CLOCK MODE)

OR

OSC/4 (12 CLOCK MODE)

OVERFLOW

INTERRUPT

CH

CL

16–BIT UP COUNTER

TIMER 0 OVERFLOW

EXTERNAL INPUT

(P1.2/ECI)

00

01

10

11

DECODE

IDLE

CMOD

(C1H)

CIDL

CF

WDTE

––

CPS1

CCF2

CPS0

ECF

CCON

(C0H)

CR

CCF4

CCF3

CCF1

CCF0

SU01256

Figure 26. PCA Timer/Counter

CCON

(C0H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

PCA TIMER/COUNTER

MODULE 0

IE.7

EA

IE.6

EC

TO

MODULE 1

MODULE 2

INTERRUPT

PRIORITY

DECODER

MODULE 3

MODULE 4

CCAPMn.0

ECCFn

CMOD.0

ECF

SU01097

Figure 27. PCA Interrupt System

35

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

CMOD Address = D9H

Reset Value = 00XX X000B

CIDL

WDTE

–

CPS1

CPS0

ECF

Bit:

Function

7

6

5

4

3

2

1

0

Symbol

CIDL

Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs

it to be gated off during idle.

WDTE

–

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.

Not implemented, reserved for future use.*

CPS1

CPS0

PCA Count Pulse Select bit 1.

PCA Count Pulse Select bit 0.

CPS1

CPS0

Selected PCA Input**

0

1

0

1

0

1

0

1

2

3

Internal clock, f

/6 in 6-clock mode (f

/2 in 6-clock mode (f

/12 in 12-clock mode)

/4 in 12-clock mode)

OSC

Internal clock, f

OSC

Timer 0 overflow

External clock at ECI/P1.2 pin

(max. rate = f /4 in 6-clock mode, f

/8 in 12-clock mode)

OCS

OSC

ECF

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables

that function of CF.

NOTE:

*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive

value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

**

f

= oscillator frequency

OSC

SU01318

Figure 28. CMOD: PCA Counter Mode Register

CCON Address = D8H

Bit Addressable

CF

Reset Value = 00X0 0000B

CR

–

CCF4

CCF3

CCF2

CCF1

CCF0

Bit:

7

6

5

4

3

2

1

0

Symbol

CF

Function

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is

set. CF may be set by either hardware or software but can only be cleared by software.

CR

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA

counter off.

–

Not implemented, reserved for future use*.

CCF4

CCF3

CCF2

CCF1

CCF0

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

NOTE:

*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive

value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU01319

Figure 29. CCON: PCA Counter Control Register

36

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

CCAPMn Address

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

0DAH

0DBH

0DCH

0DDH

0DEH

Reset Value = X000 0000B

Not Bit Addressable

–

ECOMn CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Bit:

7

6

5

4

3

2

1

0

Symbol

Function

–

Not implemented, reserved for future use*.

ECOMn

CAPPn

CAPNn

MATn

Enable Comparator. ECOMn = 1 enables the comparator function.

Capture Positive, CAPPn = 1 enables positive edge capture.

Capture Negative, CAPNn = 1 enables negative edge capture.

Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit

in CCON to be set, flagging an interrupt.

TOGn

Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn

pin to toggle.

PWMn

ECCFn

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output.

Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features In that case, the reset or inactive

value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU01320

Figure 30. CCAPMn: PCA Modules Compare/Capture Registers

–

X

ECOMn CAPPn CAPNn

MATn

TOGn

PWMn

ECCFn

MODULE FUNCTION

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

1

0

X

0

No operation

16-bit capture by a positive-edge trigger on CEXn

16-bit capture by a negative trigger on CEXn

16-bit capture by a transition on CEXn

16-bit Software Timer

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer

Figure 31. PCA Module Modes (CCAPMn Register)

PCA Capture Mode

counter and the module’s capture registers. To activate this mode

the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must

be set (see Figure 34).

To use one of the PCA modules in the capture mode either one or

both of the CCAPM bits CAPN and CAPP for that module must be

set. The external CEX input for the module (on port 1) is sampled for

a transition. When a valid transition occurs the PCA hardware loads

the value of the PCA counter registers (CH and CL) into the

module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit

for the module in the CCON SFR and the ECCFn bit in the CCAPMn

SFR are set then an interrupt will be generated. Refer to Figure 32.

Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 35

shows the PWM function. The frequency of the output depends on

the source for the PCA timer. All of the modules will have the same

frequency of output because they all share the PCA timer. The duty

cycle of each module is independently variable using the module’s

capture register CCAPLn. When the value of the PCA CL SFR is

less than the value in the module’s CCAPLn SFR the output will be

low, when it is equal to or greater than the output will be high. When

CL overflows from FF to 00, CCAPLn is reloaded with the value in

CCAPHn. the allows updating the PWM without glitches. The PWM

and ECOM bits in the module’s CCAPMn register must be set to

enable the PWM mode.

16-bit Software Timer Mode

The PCA modules can be used as software timers by setting both

the ECOM and MAT bits in the modules CCAPMn register. The PCA

timer will be compared to the module’s capture registers and when a

match occurs an interrupt will occur if the CCFn (CCON SFR) and

the ECCFn (CCAPMn SFR) bits for the module are both set (see

Figure 33).

High Speed Output Mode

In this mode the CEX output (on port 1) associated with the PCA

module will toggle each time a match occurs between the PCA

37

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

PCA INTERRUPT

PCA TIMER/COUNTER

(TO CCFn)

CH

CL

CAPTURE

CEXn

CCAPnH

CCAPnL

CCAPMn, n= 0 to 4

(DAH – DEH)

––

ECOMn

0

CAPPn

CAPNn

MATn

0

TOGn

0

PWMn

0

ECCFn

SU01608

Figure 32. PCA Capture Mode

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

WRITE TO

CCAPnH

RESET

PCA INTERRUPT

CCAPnH

CCAPnL

WRITE TO

CCAPnL

(TO CCFn)

0

1

ENABLE

MATCH

16–BIT COMPARATOR

CH

CL

PCA TIMER/COUNTER

CCAPMn, n= 0 to 4

(DAH – DEH)

––

ECOMn

CAPPn

0

CAPNn

0

MATn

TOGn

0

PWMn

0

ECCFn

SU01609

Figure 33. PCA Compare Mode

38

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

WRITE TO

CCAPnH

RESET

PCA INTERRUPT

CCAPnH

CCAPnL

WRITE TO

CCAPnL

(TO CCFn)

0

1

MATCH

ENABLE

16–BIT COMPARATOR

TOGGLE

CEXn

CH

CL

PCA TIMER/COUNTER

CCAPMn, n: 0..4

(DAH – DEH)

––

ECOMn

CAPPn

0

CAPNn

0

MATn

TOGn

PWMn

0

ECCFn

1

SU01610

Figure 34. PCA High Speed Output Mode

CCAPnH

CCAPnL

0

CL < CCAPnL

ENABLE

8–BIT

CEXn

COMPARATOR

CL >= CCAPnL

1

CL

OVERFLOW

PCA TIMER/COUNTER

CCAPMn, n: 0..4

(DAH – DEH)

––

ECOMn

CAPPn

0

CAPNn

MATn

0

TOGn

0

PWMn

ECCFn

0

SU01611

Figure 35. PCA PWM Mode

39

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

CMOD

(D9H)

CIDL

WDTE

––

MODULE 4

MATCH

––

CPS1

CPS0

ECF

WRITE TO

CCAP4L

RESET

CCAP4H

CCAP4L

WRITE TO

CCAP4H

1

0

ENABLE

16–BIT COMPARATOR

RESET

CH

CL

PCA TIMER/COUNTER

CCAPM4

(DEH)

––

ECOMn

CAPPn

0

CAPNn

0

MATn

1

TOGn

X

PWMn

0

ECCFn

X

SU01612

Figure 36. PCA Watchdog Timer mode (Module 4 only)

PCA Watchdog Timer

The first two options are more reliable because the watchdog

timer is never disabled as in option #3. If the program counter ever

goes astray, a match will eventually occur and cause an internal

reset. The second option is also not recommended if other PCA

modules are being used. Remember, the PCA timer is the time

base for all modules; changing the time base for other modules

would not be a good idea. Thus, in most applications the first

solution is the best option.

An on-board watchdog timer is available with the PCA to improve the

reliability of the system without increasing chip count. Watchdog

timers are useful for systems that are susceptible to noise, power

glitches, or electrostatic discharge. Module 4 is the only PCA module

that can be programmed as a watchdog. However, this module can

still be used for other modes if the watchdog is not needed.

Figure 36 shows a diagram of how the watchdog works. The user

pre-loads a 16-bit value in the compare registers. Just like the other

compare modes, this 16-bit value is compared to the PCA timer

value. If a match is allowed to occur, an internal reset will be

generated. This will not cause the RST pin to be driven high.

Figure 37 shows the code for initializing the watchdog timer.

Module 4 can be configured in either compare mode, and the WDTE

bit in CMOD must also be set. The user’s software then must

periodically change (CCAP4H,CCAP4L) to keep a match from

occurring with the PCA timer (CH,CL). This code is given in the

WATCHDOG routine in Figure 37.

In order to hold off the reset, the user has three options:

1. periodically change the compare value so it will never match the

PCA timer,

This routine should not be part of an interrupt service routine,

because if the program counter goes astray and gets stuck in an

infinite loop, interrupts will still be serviced and the watchdog will

keep getting reset. Thus, the purpose of the watchdog would be

2. periodically change the PCA timer value so it will never match

the compare values, or

3. disable the watchdog by clearing the WDTE bit before a match

occurs and then re-enable it.

defeated. Instead, call this subroutine from the main program within

16

2

count of the PCA timer.

40

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

INIT_WATCHDOG:

MOV CCAPM4, #4CH

MOV CCAP4L, #0FFH

MOV CCAP4H, #0FFH

; Module 4 in compare mode

; Write to low byte first

; Before PCA timer counts up to

; FFFF Hex, these compare values

; must be changed

ORL CMOD, #40H

; Set the WDTE bit to enable the

; watchdog timer without changing

; the other bits in CMOD

;

;********************************************************************

;

; Main program goes here, but CALL WATCHDOG periodically.

;

;********************************************************************

;

WATCHDOG:

CLR EA

; Hold off interrupts

MOV CCAP4L, #00

MOV CCAP4H, CH

SETB EA

; Next compare value is within

; 255 counts of the current PCA

; timer value

RET

Figure 37. PCA Watchdog Timer Initialization Code

41

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

For example:

MOV @R0,acc

Expanded Data RAM Addressing

The P89C51RA2/RB2/RC2/RD2xx has internal data memory that is

mapped into four separate segments: the lower 128 bytes of RAM,

upper 128 bytes of RAM, 128 bytes Special Function Register (SFR),

and 256 bytes expanded RAM (ERAM) (768 bytes for the RD2xx).

where R0 contains 0A0H, accesses the data byte at address 0A0H,

rather than P2 (whose address is 0A0H).

The ERAM can be accessed by indirect addressing, with EXTRAM

bit cleared and MOVX instructions. This part of memory is physically

located on-chip, logically occupies the first 256/768 bytes of external

data memory in the P89C51RA2/RB2/RC2/89C51RD2.

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

With EXTRAM = 0, the ERAM is indirectly addressed, using the

MOVX instruction in combination with any of the registers R0, R1 of

the selected bank or DPTR. An access to ERAM will not affect ports

P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external

addressing. For example, with EXTRAM = 0,

3. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

4. The 256/768-bytes expanded RAM (ERAM, 00H – 1FFH/2FFH)

are indirectly accessed by move external instruction, MOVX, and

with the EXTRAM bit cleared, see Figure 38.

MOVX @R0,acc

where R0 contains 0A0H, accesses the ERAM at address 0A0H

rather than external memory. An access to external data memory

locations higher than the ERAM will be performed with the MOVX

DPTR instructions in the same way as in the standard 80C51, so

with P0 and P2 as data/address bus, and P3.6 and P3.7 as write

and read timing signals. Refer to Figure 39.

The Lower 128 bytes can be accessed by either direct or indirect

addressing. The Upper 128 bytes can be accessed by indirect

addressing only. The Upper 128 bytes occupy the same address

space as the SFR. That means they have the same address, but are

physically separate from SFR space.

With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar

to the standard 80C51. MOVX @ Ri will provide an 8-bit address

multiplexed with data on Port 0 and any output port pins can be

used to output higher order address bits. This is to provide the

external paging capability. MOVX @DPTR will generate a 16-bit

address. Port 2 outputs the high-order eight address bits (the

contents of DPH) while Port 0 multiplexes the low-order eight

address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will

generate either read or write signals on P3.6 (WR) and P3.7 (RD).

When an instruction accesses an internal location above address

7FH, the CPU knows whether the access is to the upper 128 bytes

of data RAM or to SFR space by the addressing mode used in the

instruction. Instructions that use direct addressing access SFR

space. For example:

MOV 0A0H,#data

accesses the SFR at location 0A0H (which is P2). Instructions that

use indirect addressing access the Upper 128 bytes of data RAM.

The stack pointer (SP) may be located anywhere in the 256 bytes

RAM (lower and upper RAM) internal data memory. The stack may

not be located in the ERAM.

AUXR

Address = 8EH

Reset Value = xxxx xx00B

Not Bit Addressable

—

6

—

5

—

4

—

3

—

2

EXTRAM

AO

Bit:

Function

Disable/Enable ALE

7

1

0

Symbol

AO

0

Operating Mode

ALE is emitted at a constant rate of / the oscillator frequency (12-clock mode; / f

3 OSC

1

6

in 6-clock mode).

ALE is active only during off-chip memory access.

1

EXTRAM

Internal/External RAM access using MOVX @Ri/@DPTR

EXTRAM

Operating Mode

0

1

Internal ERAM access using MOVX @Ri/@DPTR

External data memory access.

—

Not implemented, reserved for future use*.

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value

of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU01613

Figure 38. AUXR: Auxiliary Register

42

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

FF

FFFF

UPPER

128 BYTES

INTERNAL RAM

SPECIAL

FUNCTION

REGISTER

EXTERNAL

DATA

MEMORY

80

ERAM

256 or 768 BYTES

LOWER

128 BYTES

INTERNAL RAM

100

00

0000

SU01293

Figure 39. Internal and External Data Memory Address Space with EXTRAM = 0

HARDWARE WATCHDOG TIMER (ONE-TIME

ENABLED WITH RESET-OUT FOR

P89C51RA2/RB2/RC2/RD2xx)

Using the WDT

To enable the WDT, the user must write 01EH and 0E1H in sequence

to the WDTRST, SFR location 0A6H. When the WDT is enabled, the

user needs to service it by writing 01EH and 0E1H to WDTRST to

avoid a WDT overflow. The 14-bit counter overflows when it reaches

16383 (3FFFH) and this will reset the device. When the WDT is

enabled, it will increment every machine cycle while the oscillator is

running. This means the user must reset the WDT at least every

16383 machine cycles. To reset the WDT, the user must write 01EH

and 0E1H to WDTRST. WDTRST is a write only register. The WDT

counter cannot be read or written. When the WDT overflows, it will

generate an output RESET pulse at the reset pin (see note below).

The WDT is intended as a recovery method in situations where the

CPU may be subjected to software upset. The WDT consists of a

14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The

WDT is disabled at reset. To enable the WDT, the user must write

01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.

When the WDT is enabled, it will increment every machine cycle

while the oscillator is running and there is no way to disable the

WDT except through reset (either hardware reset or WDT overflow

reset). When the WDT overflows, it will drive an output reset HIGH

pulse at the RST-pin (see the note below).

The RESET pulse duration is 98 × T

12-clock mode), where T

(6-clock mode; 196 in

. To make the best use of the

OSC

= 1/f

OSC

WDT, it should be serviced in those sections of code that will

periodically be executed within the time required to prevent a WDT

reset.

43

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

FLASH EPROM MEMORY

FLASH PROGRAMMING AND ERASURE

In general, there are three methods of erasing or programming of

the Flash memory that may be used. First, the Flash may be

programmed or erased in the end-user application by calling

low-level routines through entry point in the BootROM. The end-user

application, though, must be executing code from a different block

than the block that is being erased or programmed. Second, the

on-chip ISP boot loader may be invoked. This ISP boot loader will, in

turn, call low-level routines through the common entry point in the

BootROM that can be used by end-user applications. Third, the

Flash may be programmed or erased using parallel method by using

a commercially available EPROM programmer. The parallel

programming method used by these devices is similar to that used

by EPROM 87C51, but it is not identical, and the commercially

available programmer will need to have support for these devices.

GENERAL DESCRIPTION

The P89C51RA2/RB2/RC2/RD2xx Flash memory augments EPROM

functionality with in-circuit electrical erasure and programming. The

Flash can be read and written as bytes. The Chip Erase operation will

erase the entire program memory. The Block Erase function can

erase any Flash block. In-system programming and standard parallel

programming are both available. On-chip erase and write timing

generation contribute to a user friendly programming interface.

The P89C51RA2/RB2/RC2/RD2xx Flash reliably stores memory

contents even after 10,000 erase and program cycles. The cell is

designed to optimize the erase and programming mechanisms. In

addition, the combination of advanced tunnel oxide processing and

low internal electric fields for erase and programming operations

produces reliable cycling. The P89C51RA2/RB2/RC2/RD2xx uses a

+5 V V supply to perform the Program/Erase algorithms.

PP

FLASH MEMORY SPACES

Flash User Code Memory Organization

The P89C51RA2/RB2/RC2/RD2xx contains 8KB/16KB/32KB/64KB

Flash user code program memory organized into 4-kbyte blocks.

ISP and IAP BootROM routines will support the new 4-kbyte block

sizes through additional block number assignments while

maintaining compatibility with previous 8-kbyte and 16-kbyte block

assignments. This memory space is programmable via IAP, ISP, and

parallel modes.

FEATURES – IN-SYSTEM PROGRAMMING (ISP)

AND IN-APPLICATION PROGRAMMING (IAP)

• Flash EPROM internal program memory with Block Erase.

• Internal 1-kbyte fixed BootROM, containing low-level in-system

programming routines and a default serial loader. User program

can call these routines to perform In-Application Programming

(IAP). The BootROM can be turned off to provide access to the

full 64-kbyte Flash memory.

Status Byte/Boot Vector Block

This device includes a 4-kbyte block which contains the Status Byte

and Boot Vector (Status Byte Block) . The Status Byte and Boot

Vector are programmable via IAP, ISP, and parallel modes. Note that

erasing of either the Status Byte and Boot Vector will erase the

entire contents of this block. Thus the Status Byte and Boot Vector

are erased together but are programmable separately.

• Boot Vector allows user provided Flash loader code to reside

anywhere in the Flash memory space. This configuration provides

flexibility to the user.

• Default loader in BootROM allows programming via the serial port

without the need for a user provided loader.

Security & User Configuration Block

• Up to 64-kbyte external program memory if the internal program

This device includes a 4-kbyte block (Security Block) which contains

the Security Bits, the 6-clock/12-clock Flash-based clock mode bit

FX2, and 4095 user programmable bytes. This block is

programmable via IAP, ISP, and parallel modes. Security bits will

prevent, as required, parallel programmers from reading or writing,

however, IAP or ISP inhibitions will be software controlled. This

block may only be erased using full-chip erase functions in ISP, IAP,

or parallel mode. This security feature protects against software

piracy and prevents the contents of the Flash from being read. The

Security bits are located in the Flash. There are three programmable

security bits that will provide different levels of protection for the

on-chip code and data (See Table 11). The 4095 user programmable

bytes are not part of user code memory are intended to be

programmed or read through IAP, ISP, or parallel programmer

functions.

memory is disabled (EA = 0).

• Programming and erase voltage +5 V (+12 V tolerant).

• Read/Programming/Erase using ISP/IAP:

– Byte Programming (8 ms).

– Typical quick erase times:

Block Erase (4 kbyte) in 3 seconds.

Full Chip Erase:

– RD2xx (64K) in 11 seconds

– RC2 (32K) in 7 seconds

– RB2 (16K) in 5 seconds

– RA2 (4K) in 4 seconds

• Parallel programming with 87C51 compatible hardware interface

to programmer.

The 6-clock/12-clock Flash-based clock mode bit FX2 will be latched

at power-on. This allows the bit to be changed via IAP or ISP and

delay taking effect until the next reset. This avoids changing baud

rates during ISP operations.

• In-system programming (ISP).

• In-application programming (IAP).

• Programmable security for the code in the Flash.

• 10,000 minimum erase/program cycles for each byte.

• 10-year minimum data retention.

Boot ROM

When the microcontroller programs its Flash memory, all of the low

level details are handled by code that is contained in a 1-kbyte

44

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

BootROM that is shadowed over a portion of the user code memory

Clock Mode

space. A user program simply calls the common entry point with

appropriate parameters in the BootROM to accomplish the desired

operation. BootROM operations include: erase block, program byte,

verify byte, program security bit, etc. The BootROM overlays the

program memory space at the top of the address space from FC00

to FFFF hex, when it is enabled. The BootROM may be turned off so

that the upper 1 kbyte of user program memory is accessible for

execution.

The clock mode feature sets operating frequency to be 1/12 or 1/6 of

the oscillator frequency. The clock mode configuration bit, FX2, is

located in the Security Block (See Table 8). FX2, when programmed,

will override the SFR clock mode bit (X2) in the CKCON register. If

FX2 is erased, then the SFR bit (X2) may be used to select between

6-clock and 12-clock mode.

Table 8.

CLOCK MODE CONFIG BIT (FX2)

X2 bit in CKCON

DESCRIPTION

12-clock mode (default)

6-clock mode

erased

0

1

x

erased

programmed

6-clock mode

NOTE:

1. Default clock mode after ChipErase is set to SFR selection.

FLASH MEMORY SPACES

Flash User Code Memory Organization

FFFF

BLOCK 15

BOOT ROM

FC00

BLOCK 14

BLOCK 13

BLOCK 12

BLOCK 11

BLOCK 10

BLOCK 9

BLOCK 8

BLOCK 7

BLOCK 6

BLOCK 5

BLOCK 4

BLOCK 3

BLOCK 2

BLOCK 1

BLOCK 0

(1 kB)

89C51RD2xx

C000

PROGRAM

ADDRESS

8000

Each block is

4 kbytes in size

89C51RC2xx

4000

2000

0000

89C51RB2xx

89C51RA2xx

SU01614

Figure 40. Flash Memory Configurations

set to 00H. The factory default setting is 0FCH, corresponds to the

address 0FC00H for the factory masked-ROM ISP boot loader. A

custom boot loader can be written with the Boot Vector set to the

custom boot loader.

Power-On Reset Code Execution

The P89C51RA2/RB2/RC2/RD2xx contains two special Flash

registers: the BOOT VECTOR and the STATUS BYTE. At the falling

edge of reset, the P89C51RA2/RB2/RC2/RD2xx examines the

contents of the Status Byte. If the Status Byte is set to zero,

power-up execution starts at location 0000H, which is the normal

start address of the user’s application code. When the Status Byte is

set to a value other than zero, the contents of the Boot Vector is

used as the high byte of the execution address and the low byte is

NOTE: When erasing the Status Byte or Boot Vector, both

bytes are erased at the same time. It is necessary to reprogram

the Boot Vector after erasing and updating the Status Byte.

45

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

happens, the only way it is possible to change the contents of the

Boot Vector is through the parallel programming method, provided

that the end user application does not contain a customized loader

that provides for erasing and reprogramming of the Boot Vector and

Status Byte.

Hardware Activation of the Boot Loader

The boot loader can also be executed by holding PSEN LOW,

EA greater than V (such as +5 V), and ALE HIGH (or not connected)

IH

at the falling edge of RESET. This is the same effect as having a

non-zero status byte. This allows an application to be built that will

normally execute the end user’s code but can be manually forced

into ISP operation.

After programming the Flash, the status byte should be programmed

to zero in order to allow execution of the user’s application code

beginning at address 0000H.

If the factory default setting for the Boot Vector (0FCH) is changed, it

will no longer point to the ISP masked-ROM boot loader code. If this

V

CC

V

+5 V (+12 V tolerant)

PP

V

+5 V

TxD

RxD

CC

RST

TxD

RxD

XTAL2

P89C51RA2xx

V

SS

P89C51RB2xx

P89C51RC2xx

P89C51RD2xx

XTAL1

V

SS

SU01615

Figure 41. In-System Programming with a Minimum of Pins

the P89C51RA2/RB2/RC2/RD2xx to establish the baud rate. The

ISP firmware provides auto-echo of received characters.

In-System Programming (ISP)

The In-System Programming (ISP) is performed without removing

the microcontroller from the system. The In-System Programming

(ISP) facility consists of a series of internal hardware resources

coupled with internal firmware to facilitate remote programming of

the P89C51RA2/RB2/RC2/RD2xx through the serial port. This

firmware is provided by Philips and embedded within each

P89C51RA2/RB2/RC2/RD2xx device.

Once baud rate initialization has been performed, the ISP firmware

will only accept Intel Hex-type records. Intel Hex records consist of

ASCII characters used to represent hexadecimal values and are

summarized below:

:NNAAAARRDD..DDCC<crlf>

In the Intel Hex record, the “NN” represents the number of data

bytes in the record. The P89C51RA2/RB2/RC2/RD2xx will accept

up to 16 (10H) data bytes. The “AAAA” string represents the

address of the first byte in the record. If there are zero bytes in the

record, this field is often set to 0000. The “RR” string indicates the

record type. A record type of “00” is a data record. A record type of

“01” indicates the end-of-file mark. In this application, additional

record types will be added to indicate either commands or data for

the ISP facility. The maximum number of data bytes in a record is

limited to 16 (decimal). ISP commands are summarized in Table 9.

The Philips In-System Programming (ISP) facility has made in-circuit

programming in an embedded application possible with a minimum

of additional expense in components and circuit board area.

The ISP function uses five pins: TxD, RxD, V , V , and V (see

SS

CC

PP

Figure 41). Only a small connector needs to be available to interface

your application to an external circuit in order to use this feature.

The V supply should be adequately decoupled and V not

PP

allowed to exceed datasheet limits.

Free ISP software is available from the Embedded Systems

Academy: “FlashMagic”

As a record is received by the P89C51RA2/RB2/RC2/RD2xx, the

information in the record is stored internally and a checksum

calculation is performed. The operation indicated by the record type

is not performed until the entire record has been received. Should

an error occur in the checksum, the P89C51RA2/RB2/RC2/RD2xx

will send an “X” out the serial port indicating a checksum error. If the

checksum calculation is found to match the checksum in the record,

then the command will be executed. In most cases, successful

reception of the record will be indicated by transmitting a “.”

character out the serial port (displaying the contents of the internal

program memory is an exception).

1. Direct your browser to the following page:

http://www.esacademy.com/software/flashmagic/

2. Download Flashmagic

3. Execute “flashmagic.exe” to install the software

Using the In-System Programming (ISP)

The ISP feature allows for a wide range of baud rates to be used in

your application, independent of the oscillator frequency. It is also

adaptable to a wide range of oscillator frequencies. This is

accomplished by measuring the bit-time of a single bit in a received

character. This information is then used to program the baud rate in

terms of timer counts based on the oscillator frequency. The ISP

feature requires that an initial character (an uppercase U) be sent to

In the case of a Data Record (record type 00), an additional check is

made. A “.” character will NOT be sent unless the record checksum

matched the calculated checksum and all of the bytes in the record

46

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

were successfully programmed. For a data record, an “X” indicates

that the checksum failed to match, and an “R” character indicates

that one of the bytes did not properly program. It is necessary to

send a type 02 record (specify oscillator frequency) to the

P89C51RA2/RB2/RC2/RD2xx before programming data.

The ISP facility was designed to that specific crystal frequencies

were not required in order to generate baud rates or time the

programming pulses. The user thus needs to provide the

P89C51RA2/RB2/RC2/RD2xx with information required to generate

the proper timing. Record type 02 is provided for this purpose.

47

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Table 9. Intel-Hex Records Used by In-System Programming

RECORD TYPE

COMMAND/DATA FUNCTION

00

Program Data

:nnaaaa00dd....ddcc

Where:

nn

aaaa

= number of bytes (hex) in record

= memory address of first byte in record

dd....dd = data bytes

cc

= checksum

Example:

:10008000AF5F67F0602703E0322CFA92007780C3FD

01

03

End of File (EOF), no operation

:xxxxxx01cc

Where:

xxxxxx

cc

= required field, but value is a “don’t care”

= checksum

Example:

:00000001FF

Miscellaneous Write Functions

:nnxxxx03ffssddcc

Where:

nn

xxxx

03

ff

ss

dd

cc

= number of bytes (hex) in record

= required field, but value is a “don’t care”

= Write Function

= subfunction code

= selection code

= data input (as needed)

= checksum

Subfunction Code = 01 (Erase 8K/16K Code Blocks)

ff = 01

ss = block code as shown below:

block 0, 0k to 8k, 00H

block 1, 8k to 16k, 20H

block 2, 16k to 32k, 40H

block 3, 32k to 48k, 80H

block 4, 48k to 64k, C0H

Example:

(RB2, RC2, RD2)

(RC2, RD2)

(RD2 only)

:0200000301C03A erase block 4

Subfunction Code = 04 (Erase Boot Vector and Status Byte)

ff = 04

ss = don’t care

Example:

:020000030400F7 erase boot vector and status byte

Subfunction Code = 05 (Program Security Bits)

ff = 05

ss = 00 program security bit 1 (inhibit writing to Flash)

01 program security bit 2 (inhibit Flash verify)

02 program security bit 3 (disable external memory)

Example:

:020000030501F5 program security bit 2

Subfunction Code = 06 (Program Status Byte or Boot Vector)

ff = 06

ss = 00 program status byte

01 program boot vector

02 program FX2 bit (dd = 80)

dd = data

Example 1:

:030000030601FCF7 program boot vector with 0FCH

Example 2:

:0300000306028072 program FX2 bit (select 12-clock mode)

48

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

RECORD TYPE

COMMAND/DATA FUNCTION

03 (Cont.)

Subfunction Code = 07 (Full Chip Erase)

Erases all blocks, security bits, and sets status byte and boot vector to default values

ff = 07

ss = don’t care

dd = don’t care

Example:

:0100000307F5 full chip erase

Subfunction Code = 0C (Erase 4K Blocks)

ff = 0C

ss = block code as shown below:

Block 0 , 0k~4k , 00H

Block 1 , 4k~8k , 10H

Block 2 , 8k~12k , 20H

Block 3 , 12k~16k , 30H

Block 4 , 16k~20k , 40H

Block 5 , 20k~24k , 50H

Block 6 , 24k~28k , 60H

Block 7 , 28k~32k , 70H

Block 8 , 32k~36k , 80H

Block 9 , 36k~40k , 90H

Block 10, 40k~44k , A0H

Block 11, 44k~48k , B0H

Block 12, 48k~52k , C0H

Block 13, 52k~56k , D0H

Block 14, 56k~60k , E0H

Block 15, 60k~64k , F0H

(only available on RD2 / RC2 / RB2)

(only available on RD2 / RC2)

(only available on RD2)

Example:

:020000030C20CF (Erase 4k block #2)

04

Display Device Data or Blank Check – Record type 04 causes the contents of the entire Flash array to be sent out

the serial port in a formatted display. This display consists of an address and the contents of 16 bytes starting with that

address. No display of the device contents will occur if security bit 2 has been programmed. Data to the serial port is

initiated by the reception of any character and terminated by the reception of any character.

General Format of Function 04

:05xxxx04sssseeeeffcc

Where:

05

xxxx

04

ssss

eeee

ff

= number of bytes (hex) in record

= required field, but value is a “don’t care”

= “Display Device Data or Blank Check” function code

= starting address

= ending address

= subfunction

00 = display data

01 = blank check

02 = display data in data block (valid addresses: 0001~0FFFH)

= checksum

cc

Example 1:

:0500000440004FFF0069 display 4000–4FFF

Example 2:

:0500000400000FFF02E7 display data in data block

(the data at address 0000 is invalid)

49

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

RECORD TYPE

COMMAND/DATA FUNCTION

05

Miscellaneous Read Functions (Selection)

General Format of Function 05

:02xxxx05ffsscc

Where:

02

xxxx

05

=

number of bytes (hex) in record

required field, but value is a “don’t care”

“Miscellaneous Read” function code

ffss

subfunction and selection code

0000 = read signature byte – manufacturer id (15H)

0001 = read signature byte – device id # 1

0002 = read signature byte – device id # 2

0003 = read FX2 bit

(C2H)

0080 = read ROM Code Revision

0700 = read security bits

0701 = read status byte

0702 = read boot vector

= checksum

cc

Example 1:

:020000050001F8 read signature byte – device id # 1

Example 2:

:020000050003F6 read FX2 bit

(bit7=0 represent 12–clock mode, bit7=1 represent 6–clock mode)

Example 3:

:02000005008079 read ROM Code Revision (0A: Rev. A, 0B:Rev. B)

06

Direct Load of Baud Rate

General Format of Function 06

:02xxxx06hhllcc

Where:

02

xxxx

06

hh

ll

=

number of bytes (hex) in record

required field, but value is a “don’t care”

”Direct Load of Baud Rate” function code

high byte of Timer 2

low byte of Timer 2

checksum

cc

Example:

:02000006F500F3

07

Program Data in Data Block

:nnaaaa07dd....ddcc

Where:

nn

=

number of bytes (hex) in record

memory address of first byte in record (the valid address:0001~0FFFH)

data bytes

checksum

aaaa

dd....dd

cc

Example:

:10008007AF5F67F0602703E0322CFA92007780C3F6

50

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Using the Watchdog Timer (WDT)

In Application Programming Method

The P89C51Rx2 devices support the use of the WDT in IAP. The

user specifies that the WDT is to be fed by setting the most

significant bit of the function parameter passed in R1 prior to calling

PGM_MTP. The WDT function is only supported for Block Erase

when using Quick Block Erase. The Quick Block Erase is specified

by performing a Block Erase with register R0 = 0. Requesting a

WDT feed during IAP should only be performed in applications that

use the WDT since the process of feeding the WDT will start the

WDT if the WDT was not running.

Several In Application Programming (IAP) calls are available for use by

an application program to permit selective erasing and programming of

Flash sectors. All calls are made through a common interface,

PGM_MTP. The programming functions are selected by setting up

the microcontroller’s registers before making a call to PGM_MTP at

FFF0H. The oscillator frequency is an integer number rounded down

to the nearest megahertz. For example, set R0 to 11 for 11.0592 MHz.

Results are returned in the registers. The IAP calls are shown in

Table 10.

Table 10. IAP calls

IAP CALL

PARAMETER

PROGRAM BYTE

Input Parameter:

R0 = osc freq (integer)

R1 = 02h or R1= 82h (WDT feed)

DPTR = address of byte to program

ACC = byte to program

Return Parameter:

ACC = 00 if pass, !=00 if fail

ERASE 4K CODE BLOCK

(New function)

Input Parameter:

R0 = osc freq (integer)

R1 = 0Ch or R1 = 8Ch (WDT feed)

DPH = address of 4k code block

DPH = 00H , 4k block 0, 0k~4k

DPH = 10H , 4k block 1, 4k~8k

DPH = 20H , 4k block 2, 8k~12k

DPH = 30H , 4k block 3, 12k~16k

DPH = 40H , 4k block 4, 16k~20k

DPH = 50H , 4k block 5, 20k~24k

DPH = 60H , 4k block 6, 24k~28k

DPH = 70H , 4k block 7, 28k~32k

DPH = 80H , 4k block 8, 32k~36k

DPH = 90H , 4k block 9, 36k~40k

DPH = A0H , 4k block 10, 40k~44k

DPH = B0H , 4k block 11, 44k~48k

DPH = C0H , 4k block 12, 48k~52k

DPH = D0H , 4k block 13, 52k~56k

DPH = E0H , 4k block 14, 56k~60k

DPH = F0H , 4k block 15, 60k~64k

DPL = 00h

Return Parameter:

ACC = 00 if pass, !=00 if fail

ERASE 8K / 16K CODE

BLOCK

Input Parameter:

R0 = osc freq (integer)

R1 = 01h or R1 = 81h (WDT feed)

DPH = address of code block

DPH = 00H , block 0 , 0k~8k

DPH = 20H , block 1 , 8k~16k

DPH = 40H , block 2 , 16~32k

DPH = 80H , block 3 , 32k~48k

DPH = C0H , block 4 , 48k~64k

DPL = 00h

Return Parameter:

ACC = 00 if pass , !=0 if fail

ERASE STATUS BYTE &

BOOT VECTOR

Input Parameter:

R0 = osc freq (integer)

R1 = 04h or R1 = 84h (WDT feed)

DPH = 00h

DPL = don’t care

Return Parameter:

ACC = 00 if pass , !=0 if fail

51

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

IAP CALL

PARAMETER

PROGRAM SECURITY BITS

Input Parameter:

R0 = osc freq (integer)

R1 = 05h or R1 = 85h (WDT feed)

DPH = 00h

DPL = 00h , security bit #1

DPL = 01h , security bit #2

DPL = 02h , security bit #3

Return Parameter:

ACC = 00 if pass , !=0 if fail

PROGRAM STATUS BYTE

Input Parameter:

R0 = osc freq (integer)

R1 = 06h or R1 = 86h (WDT feed)

DPH = 00h

DPL = 00H - program status byte

ACC = status byte

Return Parameter:

ACC = 00 if pass , !=0 if fail

PROGRAM BOOT VECTOR

Input Parameter:

R0 = osc freq (integer)

R1 = 06h or R1 = 86h (WDT feed)

DPH = 00h

DPL = 01H - program boot vector

ACC = boot vector

Return Parameter:

ACC = 00 if pass , !=0 if fail

PROGRAM 6–CLK/12–CLK

CONFIGURATION BIT

(New function)

Input Parameter:

R0 = osc freq (integer)

R1 = 06h or R1 = 86h (WDT feed)

DPH = 00h

DPL = 02H - program config bit

ACC = 80H (MSB = 6clk/12clk bit)

Return Parameter:

ACC = 00 if pass , !=0 if fail

PROGRAM DATA BLOCK

(New function)

Input Parameter:

R0 = osc freq (integer)

R1 = 0Dh or R1 = 8Dh (WDT feed)

DPTR = address of byte to program

(valid addresses = 0001h~0FFFh)

ACC = data

Return Parameter:

ACC = 00 if pass , !=0 if fail

READ DEVICE DATA

Input Parameter:

R0 = osc freq (integer)

R1 = 03h or R1 = 83h (WDT feed)

DPTR = address of byte to read

Return Parameter:

ACC = value of byte read

READ DATA BLOCK

(New function)

Input Parameter:

R0 = osc freq (integer)

R1 = 0Eh or R1 = 8Eh (WDT feed)

DPTR = address of byte to read

(valid addresses = 0001h~0FFFh)

Return Parameter:

ACC = value of byte read

READ MANUFACTURER ID

Input Parameter:

R0 = osc freq (integer)

R1 = 00h or R1 = 80h (WDT feed)

DPH = 00h

DPL = 00h - read manufacturer ID

Return Parameter:

ACC = value of byte read

52

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

IAP CALL

PARAMETER

READ DEVICE ID #1

READ DEVICE ID #2

READ SECURITY BITS

READ STATUS BYTE

READ BOOT VECTOR

Input Parameter:

R0 = osc freq (integer)

R1 = 00h or R1 = 80h (WDT feed)

DPH = 00h

DPL = 01h - read device ID #1

Return Parameter:

ACC = value of byte read

Input Parameter:

R0 = osc freq (integer)

R1 = 00h or R1 = 80h (WDT feed)

DPH = 00h

DPL = 02h - read device ID #2

Return Parameter:

ACC = value of byte read

Input Parameter:

R0 = osc freq (integer)

R1 = 07h or R1 = 87h (WDT feed)

DPH = 00h

DPL = 00h - read lock byte

Return Parameter:

ACC = value of byte read

Input Parameter:

R0 = osc freq (integer)

R1 = 07h or R1 = 87h (WDT feed)

DPH = 00h

DPL = 01h - read status byte

Return Parameter:

ACC = value of byte read

Input Parameter:

R0 = osc freq (integer)

R1 = 07h or R1 = 87h (WDT feed)

DPH = 00h

DPL = 02h - read boot vector

Return Parameter:

ACC = value of byte read

READ CONFIG

(New function)

Input Parameter:

R0 = osc freq (integer)

R1 = 00h or R1 = 80h (WDT feed)

DPH = 00h

DPL = 03h - read config byte

Return Parameter:

ACC = value of byte read

READ REVISION

(New function)

Input Parameter:

R0 = osc freq (integer)

R1 = 00h or R1 = 80h (WDT feed)

DPH = 00h

DPL = 80h - read revision of ROM Code

Return Parameter:

ACC = value of byte read

53

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Security

The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located

in Flash. The P89C51RA2/RB2/RC2/RD2xx has three programmable security lock bits that will provide different levels of protection for the

on-chip code and data (see Table 11).

Table 11.

1

SECURITY LOCK BITS

PROTECTION DESCRIPTION

LEVEL

LB1

LB2

LB3

1

0

MOVC instructions executed from external program memory are disabled from fetching code

bytes from internal memory.

2

3

4

1

0

1

0

1

Block erase is disabled. Erase or programming of the status byte or boot vector is disabled.

Verify of code memory is disabled.

External execution is disabled.

NOTE:

1. Security bits are independent of each other. Full-chip erase may be performed regardless of the state of the security bits.

2. Any other combination of lock bits is undefined.

3. Setting LBx doesn’t prevent programming of unprogrammed bits.

54

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

1, 2, 3

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Operating temperature under bias

RATING

0 to +70 or –40 to +85

–65 to +150

0 to +13.0

–0.5 to +6.5

15

UNIT

°C

V

Storage temperature range

Voltage on EA/V pin to V

PP

SS

Voltage on any other pin to V

V

SS

Maximum I per I/O pin

mA

W

OL

Power dissipation (based on package heat transfer limitations, not device power consumption)

1.5

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise noted.

SS

55

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

DC ELECTRICAL CHARACTERISTICS

T

amb

= 0 °C to +70 °C or –40 °C to +85 °C; V = 5 V ± 10%; V = 0 V

CC SS

LIMITS

TEST

CONDITIONS

SYMBOL

PARAMETER

UNIT

1

MIN

TYP

MAX

0.2V –0.1

V

Input low voltage

4.5 V < V < 5.5 V

–0.5

V

IL

CC

Input high voltage (ports 0, 1, 2, 3, EA)

Input high voltage, XTAL1, RST

0.2V +0.9

V

CC

V

CC

+0.5

IH

CC

0.7V

IH1

CC

V

OL

= 4.5 V

= 1.6 mA

CC

8

V

Output low voltage, ports 1, 2, 3

0.4

V

OL

2

I

V

CC

= 4.5 V

7, 8

Output low voltage, port 0, ALE, PSEN

0.45

OL1

OH

2

= 3.2 mA

OL

V

CC

= 4.5 V

= –30 µA

3

Output high voltage, ports 1, 2, 3

V

– 0.7

CC

I

OH

Output high voltage (port 0 in external bus mode),

V

CC

= 4.5 V

= –3.2 mA

V

OH1

CC

9

3

ALE , PSEN

I

OH

I

Logical 0 input current, ports 1, 2, 3

Logical 1-to-0 transition current, ports 1, 2, 3

Input leakage current, port 0

V

= 0.4 V

= 2.0 V

–1

–75

–650

±10

µA

IL

IN

6

TL

See Note 4

I

0.45 < V < V – 0.3

LI

IN

CC

Power supply current (see Figure 49):

Active mode (see Note 5)

See Note 5

CC

Idle mode (see Note 5)

Power-down mode or clock stopped (see

Figure 55 for conditions)

T

= 0 °C to 70 °C

= –40 °C to +85 °C

< 30

< 40

60

100

125

µA

mA

amb

T

amb

Programming and erase mode

Internal reset pull-down resistor

f

= 20 MHz

osc

R

C

40

225

15

kΩ

RST

IO

10

Pin capacitance (except EA)

pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the V –0.7 specification when the

OH

CC

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is approximately 2 V.

IN

5. See Figures 52 through 55 for I test conditions and Figure 49 for I vs Freq.

CC

Active mode:

Idle mode:

6. This value applies to T

I

= (10.5 + 0.9 × FREQ.[MHz])mA in 12-clock mode

= (2.5 + 0.33 × FREQ.[MHz])mA in 12-clock mode

= 0 °C to +70 °C.

CC(MAX)

amb

7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

8. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

15 mA (*NOTE: This is 85 °C specification.)

OL

Maximum I per 8-bit port:

26 mA

71 mA

OL

Maximum total I for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

9. ALE is tested to V

, except when ALE is off then V is the voltage specification.

OH

OH1

10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF

(except EA is 25 pF).

56

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE)

1, 2, 3

T

amb

= 0 °C to +70 °C or –40 °C to +85 °C; V = 5 V ± 10%, V = 0 V

CC SS

4

VARIABLE CLOCK

33 MHz CLOCK

SYMBOL FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

MHz

ns

1/t

CLCL

42

Oscillator frequency

ALE pulse width

0

33

t

2t

–40

21

5

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–25

ns

AVLL

LLAX

LLIV

CLCL

–25

5

ns

4t

3t

–65

–60

55

30

ns

CLCL

t

–25

5

ns

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

3t

–45

45

ns

CLCL

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

ns

CLCL

0

ns

t

–25

5

ns

CLCL

5t

–80

70

10

ns

CLCL

10

ns

Data Memory

t

43, 44

44

RD pulse width

6t

–100

82

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

5t

2t

–90

–28

60

CLCL

0

Data float after RD

32

90

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

8t

–150

–165

CLCL

9t

105

140

AVDV

LLWL

3t

–50

–75

3t

CLCL

+50

40

45

0

CLCL

4t

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLCL

t

–30

–25

CLCL

5

Data valid to WR high

RD low to address float

RD or WR high to ALE high

7t

–130

80

CLCL

43, 44

0

t

–25

t

+25

5

55

CLCL

External Clock

t

46

High time

Low time

Rise time

Fall time

17

t

–t

ns

CHCX

CLCX

CLCH

CHCL

CLCL CLCX

t

–t

CLCL CHCX

5

Shift Register

t

45

Serial port clock cycle time

12t

360

167

50

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t –133

CLCL

QVXH

XHQX

XHDX

XHDV

2t

CLCL

–80

0

10t

–133

167

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to

Port 0 drivers.

4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.

57

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE)

1, 2, 3

T

amb

= 0 °C to +70 °C or –40 °C to +85 °C; V = 5 V ± 10%, V = 0 V

CC SS

4

VARIABLE CLOCK

20 MHz CLOCK

SYMBOL FIGURE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

MHz

ns

1/t

CLCL

42

Oscillator frequency

ALE pulse width

0

20

t

–40

10

5

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

0.5t

–20

ns

AVLL

LLAX

LLIV

CLCL

5

ns

CLCL

2t

–65

35

15

ns

CLCL

0.5t

1.5t

–20

–45

5

ns

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

30

ns

CLCL

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

1.5t

–60

ns

CLCL

0

ns

0.5t

2.5t

–20

–80

5

ns

CLCL

45

10

ns

CLCL

10

ns

Data Memory

t

43, 44

44

RD pulse width

3t

–100

50

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

CLCL

RD low to valid data in

Data hold after RD

2.5t

–90

35

CLCL

0

Data float after RD

t

–20

5

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

4t

CLCL

–150

–165

50

4.5t

60

AVDV

LLWL

CLCL

1.5t

–50 1.5t

+50

25

0

125

CLCL

2t

–75

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLCL

0.5t

–25

–20

CLCL

5

CLCL

Data valid to WR high

RD low to address float

RD or WR high to ALE high

3.5t

–130

CLCL

45

43, 44

0

0.5t

–20 0.5t

+20

5

45

CLCL

External Clock

t

46

High time

Low time

Rise time

Fall time

20

t

–t

ns

CHCX

CLCX

CLCH

CHCL

CLCL CLCX

t

–t

CLCL CHCX

5

Shift Register

t

45

Serial port clock cycle time

6t

300

117

20

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

5t

–133

CLCL

QVXH

XHQX

XHDX

XHDV

t

–30

CLCL

0

5t

CLCL

–133

117

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to

Port 0 drivers.

4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

58

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

P – PSEN

Q – Output data

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

designations are:

R – RD signal

t – Time

A – Address

V – Valid

C – Clock

D – Input data

H – Logic level high

I – Instruction (program memory contents)

L – Logic level low, or ALE

W– WR signal

X – No longer a valid logic level

Z – Float

Examples: t

= Time for address valid to ALE low.

= Time for ALE low to PSEN low.

AVLL

LLPL

t

LHLL

ALE

t

LLPL

AVLL

t

PLPH

t

LLIV

t

PLIV

PSEN

t

LLAX

t

PXIZ

t

PLAZ

t

PXIX

A0–A7

INSTR IN

A0–A7

PORT 0

PORT 2

t

AVIV

A0–A15

A8–A15

SU00006

Figure 42. External Program Memory Read Cycle

ALE

PSEN

RD

t

WHLH

t

LLDV

t

LLWL

RLRH

t

RHDZ

t

LLAX

t

RLDV

AVLL

t

RLAZ

t

RHDX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA IN

A0–A7 FROM PCL

INSTR IN

t

AVWL

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00025

Figure 43. External Data Memory Read Cycle

59

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

t

WHQX

t

AVLL

QVWX

t

QVWH

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA OUT

A0–A7 FROM PCL

INSTR IN

t

AVWL

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00026

Figure 44. External Data Memory Write Cycle

INSTRUCTION

ALE

0

1

2

3

4

5

6

7

8

t

XLXL

CLOCK

t

XHQX

t

QVXH

OUTPUT DATA

0

1

2

3

4

5

6

7

WRITE TO SBUF

t

XHDX

t

SET TI

VALID

XHDV

INPUT DATA

CLEAR RI

VALID

SET RI

SU00027

Figure 45. Shift Register Mode Timing

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

t

CHCX

t

CHCL

CLCX

CLCH

t

CLCL

SU00009

Figure 46. External Clock Drive

60

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

V

–0.5

CC

V

+0.1V

LOAD

V

–0.1V

TIMING

REFERENCE

POINTS

OH

0.2V

+0.9

–0.1

CC

V

LOAD

CC

–0.1V

LOAD

+0.1V

OL

0.45V

NOTE:

For timing purposes, a port is no longer floating when a 100mV change from

load voltage occurs, and begins to float when a 100mV change from the loaded

AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.

CC

IH

IL

V

/V level occurs. I /I ≥ ±20mA.

OH OL

SU00717

SU00718

Figure 47. AC Testing Input/Output

Figure 48. Float Waveform

60

50

89C51RA2/RB2/RC2/RD2

MAXIMUM I ACTIVE

40

CC

I

(mA)

CC

30

TYPICAL I ACTIVE

CC

20

10

MAXIMUM IDLE

TYPICAL IDLE

4

8

12

16

20

24

28

32

36

Frequency at XTAL1 (MHz, 12-clock mode)

SU01631

Figure 49. I vs. FREQ

CC

Valid only within frequency specifications of the device under test

61

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

V

–0.5

CC

0.2V

+0.9

–0.1

CC

0.45V

NOTE:

AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

CC

Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.

IH

IL

SU00010

Figure 50. AC Testing Input/Output

V

+0.1V

LOAD

V

–0.1V

TIMING

REFERENCE

POINTS

OH

V

LOAD

–0.1V

LOAD

+0.1V

OL

NOTE:

For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,

and begins to float when a 100mV change from the loaded V /V level occurs. I /I ≥ ±20mA.

OH OL

SU00011

Figure 51. Float Waveform

62

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

V

–0.5

CC

0.5V

I

CC

t

CHCX

t

CHCL

CLCX

CLCH

V

CC

P0

V

CC

t

CLCL

P89C51RA2xx

P89C51RB2xx

P89C51RC2xx

P89C51RD2xx

RST

SU01297

EA

Figure 54. Clock Signal Waveform for I Tests in Active

(NC)

XTAL2

XTAL1

CC

and Idle Modes.

CLOCK SIGNAL

t

= t

= 10 ns

CHCL

CLCL

V

SS

V

CC

SU01478

I

CC

Figure 52. I Test Condition, Active Mode, T

= 25 °C.

CC

amb

V

CC

P0

All other pins are disconnected

RST

EA

V

P89C51RA2xx

P89C51RB2xx

P89C51RC2xx

P89C51RD2xx

V

CC

I

CC

(NC)

XTAL2

XTAL1

V

CC

P0

RST

EA

V

SS

P89C51RA2xx

P89C51RB2xx

P89C51RC2xx

P89C51RD2xx

SU01480

(NC)

XTAL2

XTAL1

Figure 55. I Test Condition, Power Down Mode.

CC

CLOCK SIGNAL

All other pins are disconnected; V = 2 V to 5.5 V

CC

V

SS

SU01479

Figure 53. I Test Condition, Idle Mode, T

= 25 °C.

CC

amb

All other pins are disconnected

63

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

64

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

65

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm

SOT389-1

66

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

REVISION HISTORY

Date

CPCN

Description

2002 July 18

2002 May 20

9397 750 10129

9397 750 09843

Modified ordering information table

Initial release

67

2002 Jul 18

Philips Semiconductors

Preliminary data

80C51 8-bit Flash microcontroller family

P89C51RA2/RB2/RC2/RD2xx

8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 07-02

9397 750 10129

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

68

2002 Jul 18


型号：	P89C51RD2
厂家：	NXP
描述：	80C51 8-bit Flash microcontroller family 80C51的8位闪存微控制器系列闪存微控制器
文件：	总68页 (文件大小：399K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P89C51RD2 [NXP]

相关型号：

P89C51RD2BA

P89C51RD2BA/01

P89C51RD2BA/01,512

P89C51RD2BB

P89C51RD2BBD

P89C51RD2BBD/01

P89C51RD2BN

P89C51RD2BN/01

P89C51RD2BP

P89C51RD2FA

P89C51RD2FA/01

P89C51RD2FB