P87C576EBAA-T [NXP]
IC 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQCC44, Microcontroller;型号: | P87C576EBAA-T |
厂家: | NXP |
描述: | IC 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQCC44, Microcontroller 微控制器 可编程只读存储器 |
文件: | 总46页 (文件大小:450K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D,
4 comparators, failure detect circuitry, watchdog timer
Product specification
1998 Jun 04
Supersedes data of 1998 Jan 06
IC20 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
FEATURES
• OTP available
• That can be programmed in circuit
• Software Reset
• 15 source, 2 level interrupt structure
• Lower EMI noise
• Programmable I/O pins
• 80C51 based architecture
– 8k × 8 ROM (83C576)
– 8k × 8 EPROM (87C576)
– 256 × 8 RAM
– 10-bit, 6 channel A/D
– Three 16-bit counter/timers
– 2 PWM outputs
• Serial on-board programming
• Schmitt trigger inputs on Port 1
– Programmable Counter Array
– Universal Peripheral Interface
– Enhanced UART
DESCRIPTION
– Oscillator fail detect
– Low active reset
The Philips 83C576/87C576 is a high-performance microcontroller
fabricated with Philips high-density CMOS technology. The Philips
CMOS technology combines the high speed and density
characteristics of HMOS with the low power attributes of CMOS.
Philips epitaxial substrate minimizes latch-up sensitivity.
– 4 analog comparators
– Watchdog timer
– Low V detect
CC
The 8XC576 contains an 8k × 8 ROM (83C576) EPROM (87C576),
a 256 × 8 RAM, 32 I/O lines, three 16-bit counter/timers, a
Programmable Counter Array (PCA), a 10-bit, 6 channel A/D,
2 PWM outputs, an 8-bit UPI interface, a fifteen-source, two-priority
level nested interrupt structure, an enhanced UART, four analog
comparators, power-fail detect and oscillator fail detect circuits, and
on-chip oscillator and clock circuits.
– Power-on detect
• Memory addressing capability
– 64k ROM and 64k RAM
• Power control modes:
– Idle mode
– Power-down mode
• CMOS and TTL compatible
• 6 to 16MHz
In addition, the 8XC576 has a low active reset, and a software reset.
There is also a fully configurable watchdog timer, and internal power
on clear circuit. The part includes idle mode and power-down mode
states for reduced power consumption.
• Extended temperature ranges
ORDERING INFORMATION
FREQ
(MHz)
DRAWING
NUMBER
1
ROM
EPROM
TEMPERATURE RANGE °C AND PACKAGE
P83C576EBPN
P83C576EBAA
P83C576EBBB
P83C576EFPN
P83C576EFA A
P83C576EFBB
P83C576EHPN
P83C576EHAA
P87C576EBPN
P87C576EBAA
P87C576EBBB
P87C576EBPN
P87C576EFA A
P87C576EFBB
P87C576EHPN
P87C576EHAA
P87C576EHBB
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
OTP
0 to +70, 40-Pin Plastic Dual In-line Package
0 to +70, 44-Pin Plastic Leaded Chip Carrier
0 to +70, 44-Pin Plastic Quad Flat Pack
16
16
16
16
16
16
16
16
16
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT307-2
–40 to +85, 40-Pin Plastic Dual In-line Package
–40 to +85, 44-Pin Plastic Leaded Chip Carrier
–40 to +85, 44-Pin Plastic Quad Flat Pack
–40 to +125, 40-Pin Plastic Dual In-line Package
–40 to +125, 44-Pin Plastic Leaded Chip Carrier
–40 to +125, 44-Pin Plastic Quad Flat Pack
P83C576EHBB
NOTE:
1. OTP - One Time Programmable EPROM.
2
1998 Jun 04
853-2067 19495
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
BLOCK DIAGRAM
P0.0-P0.7
P2.0-P2.7
UPI
CONTROL
PORT 0
DRIVERS
PORT 2
DRIVERS
LOW
VOLTAGE
DETECT
POWER
ON
DETECT
V
CC
V
SS
A
B
ROM/
EPROM
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 2
LATCH
RAM
PROGRAM
ADDRESS
REGISTER
B
STACK
POINTER
ACC
REGISTER
TMP1
BUFFER
TMP2
PC
INCRE-
MENTER
ALU
WATCHDOG
TIMER
SFRs
TIMERS
PCA
B
A
PSW
PROGRAM
COUNTER
PSEN
ALE
EA
TIMING
AND
CONTROL
DPTR
RST
CLK AND OSC
FAILURE
DETECT
PORT 1
LATCH
PORT 3
LATCH
PD
PWM
10-BIT
ANALOG TO DIGITAL
CONVERTER
OSCILLATOR
COMPARATOR
BLOCK
PORT 1
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
+AV
CC
P3.0-P3.7
P1.0-P1.5
–AV
SS
SU00255B
3
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
LOGIC SYMBOL
V
V
SS
CC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
XTAL1
ADDRESS AND
DATA BUS
XTAL2
RST
ADIN0
ADIN1
ADIN2
ADIN3
ADIN4
ADIN5
PWM1/ECI
CEX4/PWM0
T2/CS#
EA/V
PSEN
PP
ALE/PROG
RxD
TxD
INT0
CMP3+
CMP2+
CMP1+
CMPR–
CMP0+
CMP0–
T2EX/A0
INT1
T0
T1
WR
RD
ADDRESS BUS
CEX3/CMP3
CEX2/CMP2
CEX1/CMP1
CEX0/CMP0
SU00254A
PIN CONFIGURATIONS
44-pin Plastic Quad Flat Pack
Plastic Leaded Chip Carrier
6
1
40
44
34
7
39
29
1
33
23
LCC
PQFP
17
11
18
28
12
22
Pin Function
Pin Function
Pin Function
31 P2.7/A15/PWM1/ECI
32 PSEN
1
2
3
4
5
6
7
8
9
NC*
16 T0/P3.4/CMP1+
17 T1/P3.5/CMPR–
18 WR/P3.6/CMP0+
19 RD/P3.7/CMP0–
20 XTAL2
Pin Function
Pin Function
16
17 NC*
Pin Function
+V
REF
–V
REF
/AV
/AV
CC
1
2
3
4
5
6
7
8
9
ADIN3/P1.3
ADIN4/P1.4
ADIN5/P1.5
RST
V
31 P0.6/AD6/DB6
32 P0.5/AD5/DB5
33 P0.4/AD4/DB4
34 P0.3/AD3/DB3
35 P0.2/AD2/DB2
36 P0.1/AD1/DB1
37 P0.0/AD0/DB0
SS
33 ALE/PROG
34 NC*
SS
ADIN0/P1.0
ADIN1/P1.1
ADIN2/P1.2
ADIN3/P1.3
ADIN4/P1.4
ADIN5/P1.5
18 P2.0/A8/CEX0/CMP0
19 P2.1/A9/CEX1/CMP1
20 P2.2/A10/CEX2/CMP2
21 P2.3/A11/CEX3/CMP3
22 P2.4/A12/T2EX/A0
23 P2.5/A13/T2/CS
24 P2.6/A14/CEX4/PWM0
25 P2.7/A15/PWM1/ECI
26 PSEN
35 EA/V
PP
21 XTAL1
36 P0.7/AD7/DB7
37 P0.6/AD6/DB6
38 P0.5/AD5/DB5
39 P0.4/AD4/DB4
40 P0.3/AD3/DB3
41 P0.2/AD2/DB2
42 P0.1/AD1/DB1
43 P0.0/AD0/DB0
RxD/P3.0
22
V
SS
NC*
23 NC*
TXD/P3.1
24 P2.0/A8/CEX0/CMP0
25 P2.1/A9/CEX1/CMP1
26 P2.2/A10/CEX2/CMP2
27 P2.3/A11/CEX3/CMP3
28 P2.4/A12/T2EX/A0
INT0/P3.2/CMP3+
INT1/P3.3/CMP2+
38
V
CC
10 RST
39 NC*
11 RxD/P3.0
12 NC*
10 T0/P3.4/CMP1+
11 T1/P3.5/CMPR–
12 WR/P3.6/CMP0+
13 RD/P3.7CMP0–
14 XTAL2
40 +V
41 –V
/AV
/AV
REF
CC
REF
SS
13 TxD/P3.1
27 ALE/PROG
42 ADIN0/P1.0
43 ADIN1/P1.1
44 ADIN2/P1.2
14 INT0/P3.2/CMP3+ 29 P2.5/A13/T2/CS
44
V
CC
28 NC*
15 INT1/P3.3/CMP2+ 30 P2.6/A14/CEX4/PWM0
29 EA/V
PP
15 XTAL1
30 P0.7/AD7/DB7
* NO INTERNAL CONNECTION
SU00252A
* NO INTERNAL CONNECTION
SU00253B
4
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
DIP
20
LCC
22
QFP TYPE NAME AND FUNCTION
V
SS
16
38
I
I
Ground: 0V reference.
V
CC
40
44
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0-0.7
39-32 43-36 37-30
I/O
Port 0: Port 0 is a bidirectional I/O port. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory (see Note 5). In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code bytes
during parallel EPROM programming and outputs code bytes during verification. External
pull-ups are required during program verification. During reset, the port register is loaded
with 1’s. Port 0 has 4 output modes selected on a per bit basis by writing to the P0M1 and
P0M2 Special Function Registers as follows:
P0M1.x
P0M2.x
Mode Description
0
0
1
1
0
1
0
1
Open drain (default). See Note 1.
Weak pullup. See Note 2.
High impedance. See Note 3.
Push-pull. See Note 4.
Port 0 is also the data I/O port for the Universal Peripheral Interface (UPI). When the UPI is
enabled, port 0 must be configured as High-Z by the user. Input/Output through P0 is
controlled by pin CS, WR, RD, and A0. Output is push-pull when enabled.
P1.0-P1.5
3-8
5-9
42-44
1-3
I/O
Port 1: Port 1 is a 6-bit bidirectional I/O port with Schmitt trigger inputs. Port 1 receives the control
signals during program memory verification and parallel EPROM programming. During reset, port
1 is configured as a high impedance analog input port. Digital push-pull outputs are enabled by
writing 1’s to the P1M1 register. The programmer must take care to prevent digital outputs from
switching while an A/D conversion is in progress. Port 1 has 3 output modes selected on a per bit
basis by writing to the P1M1 and P1M2 special function registers as follows:
P1M1.X
P1M2.X
Mode Description
0
0
1
0
1
X
A/D only. (High impedance)
Digital input only. High impedance (default).
Push-pull.
Port 1 pins also serve alternate functions as follows:
3
4
5
6
7
8
4
5
6
7
8
9
42
43
44
1
2
3
I/O
I/O
I/O
I/O
I/O
I/O
P1.0/ADIN0
P1.1/ADIN1
P1.2/ADIN2
P1.3/ADIN3
P1.4/ADIN4
P1.5/ADIN5
P2.0-P2.7
21-28 24-31 18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port. Port 2 emits the high-order address byte
during accesses to external program and data memory that use 16-bit addresses (MOVX
@DPTR) (see Note 5). In this application, it uses strong internal pull-ups when emitting 1s.
Port 2 receives the high-order address byte during program verification and parallel EPROM
programming. During reset, the port 2 pullups are turned on synchronously, and the port
register is loaded with 1’s. Port 2 has the following output modes which can be selected on a
per bit basis by writing to P2M1 and P2M0:
P2M1.X
P2M2.X
Mode Description
0
0
1
1
0
1
0
1
Open drain. See Note 1.
Weak pullup (default). See Note 2.
High impedance. See Note 3.
Push-pull. See Note 4.
Port 2 pins serve alternate functions as follows:
21
22
23
24
25
26
27
28
24
25
26
27
28
29
30
31
18
19
20
21
22
23
24
25
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
CEX0
CMP0
CEX1
CMP1
CEX2
CMP2
CEX3
CMP3
T2EX
A0
T2
CS
CEX4
PCA module 0 external I/O
comparator 0 output
PCA module 1 external I/O
comparator 1 output
PCA module 2 external I/O
comparator 2 output
PCA module 3 external I/O
comparator 3 output
timer 2 capture input
UPI address input
timer 2 external I/O — clock-out (programmable)
UPI chip select input
PCA module 4 external I/O
PWM0 Pulse width modulator 0 output
ECI PCA count input
PWM1 Pulse width modulator 1 output
5
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
PIN DESCRIPTIONS (Continued)
PIN NUMBER
MNEMONIC
DIP
1
LCC
QFP TYPE NAME AND FUNCTION
+V
REF
–V
REF
/AV
/AV
2
3
40
41
I
I
A/D positive power supply
A/D 0V reference
CC
SS
2
P3.0-P3.7
10-17
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port. Port 3 pins that have 1s written to them can
be used as inputs but will source current when externally pulled low (see DC Electrical
13-19 7-13
Characteristics: I ). During reset all pins will be synchronously driven high and will remain
IL
high until written to by software. Port 3 has the following output modes which can be
selected on a per bit basis by writing to P3M1 and P3M2:
P3M1.X
P3M2.X
Mode Description
0
0
1
1
0
1
0
1
Open drain. See Note 1.
Weak pullup (default). See Note 2.
High impedance. See Note 3.
Push-pull. See Note 4.
Port 3 pins serve alternate functions as follows:
10
11
12
11
13
14
5
7
8
I
O
I
P3.0
P3.1
P3.2
RxD
TxD
INT0
Serial receive port
Serial transmit port (enabled only when transmitting serial data)
External interrupt 0
CMP3+ Comparator 3 positive input
INT1 External interrupt 1
CMP2+ Comparator 2 positive input
T0 Timer/counter 0 input
CMP1+ Comparator 1 positive input
T1 Timer/counter 1 input
CMPR– Common reference to comparators 1, 2, 3
WR External data memory write strobe
CMP0+ Comparator 0 positive input
RD External data memory read strobe
CMP0– Comparator 0 negative input
13
14
15
16
17
9
15
16
17
18
19
10
9
I
I
P3.3
P3.4
P3.5
P3.6
P3.7
10
11
12
13
4
I
O
O
I
RST
Reset: A low on this pin synchronously resets all port pins to a high state. The pin must be
held low with the oscillator running for 24 oscillator cycles to initialize the internal registers.
An internal diffused resistor to V permits a power on reset using only an external
CC
capacitor to V . RST has a Schmitt trigger input stage to provide additional noise immunity
SS
with a slow rising input voltage.
ALE/PROG
30
33
27
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a constant rate
of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that
one ALE pulse is skipped during each access to external data memory. ALE is switched off
if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse input
(PROG) during parallel EPROM programming. (See also Internal Reset on page 24.)
PSEN
29
31
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
1FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 1FFFH. This pin also receives the
EA/V
PP
12.75V programming supply voltage (V ) during EPROM programming. If this pin is at V
PP
PP
voltage during reset the device enters the in-circuit programming mode.
XTAL1
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2: Output from the inverting oscillator amplifier.
XTAL2
O
NOTES:
1. When Open Drain mode is selected, ports 0 and 2 have weak pulldowns to guarantee positive leakage current (see DC electrical
characteristic I ).
IH
2. When Weak Pullup mode is selected, ports bits that have 1’s written to them can be used as inputs but will source current when externally
pulled low (see DC electrical characteristic I ).
IL
3. When High Impedance mode is selected, all pullups and pulldowns are turned off. The only current sourced or sunk by the pin is the
parasitic leakage current (see DC electrical characteristic I or I , as applicable.
L2
LC
4. When Push-Pull mode is selected, strong pullups are on continuously when emitting 1’s (see DC electrical characteristic V ).
OH
5. When Open-Drain, Weak Pull-up, or Push-pull mode is selected.
6
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
Table 1.
SYMBOL
ACC*
87C576 Special Function Registers
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
RESET
VALUE
LSB
Accumulator
E0H
E7
E6
E5
E4
E3
E2
E1
E0
00H
ADC0H#
ADC1H#
ADC2H#
ADC3H#
ADC4H#
ADC5H#
ADC0L#
ADC1L#
ADC2L#
ADC3L#
ADC4L#
ADC5L#
A/D Channel 0 MSB
A/D Channel 1 MSB
A/D Channel 2 MSB
A/D Channel 3 MSB
A/D Channel 4 MSB
A/D Channel 5 MSB
A/D Channel 0 2-LSBits
A/D Channel 1 2-LSBits
A/D Channel 2 2-LSBits
A/D Channel 3 2-LSBits
A/D Channel 4 2-LSBits
A/D Channel 5 2-LSBits
AAH
ABH
ACH
ADH
AEH
AFH
9AH
9BH
9CH
9DH
9EH
9FH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
AMOD1
ASCA2 ASCA1
ADCON#
ADCS#
A/D Control
B1H
B2H
ADF
ADCE
AD8M
AMOD0
ASCA0 00H
00H
A/D Channel Select
AUXR#
B*
Auxiliary
8EH
F0H
–
–
–
–
SRST
F3
TXI
F2
LO
F1
AO
F0
xxxx0000B
B register
F7
F6
F5
F4
00H
CCAP0H# Module 0 Capture High
CCAP1H# Module 1 Capture High
CCAP2H# Module 2 Capture High
CCAP3H# Module 3 Capture High
CCAP4H# Module 4 Capture High
CCAP0L# Module 0 Capture Low
CCAP1L# Module 1 Capture Low
CCAP2L# Module 2 Capture Low
CCAP3L# Module 3 Capture Low
CCAP4L# Module 4 Capture Low
FAH
FBH
FCH
FDH
FEH
EAH
EBH
ECH
EDH
EEH
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
CCAPM0# Module 0 Mode
CCAPM1# Module 1 Mode
CCAPM2# Module 2 Mode
CCAPM3# Module 3 Mode
CCAPM4# Module 4 Mode
DAH
DBH
DCH
DDH
DEH
–
–
–
–
–
ECOM
ECOM
ECOM
ECOM
ECOM
CAPP
CAPP
CAPP
CAPP
CAPP
CAPN
CAPN
CAPN
CAPN
CAPN
MAT
MAT
MAT
MAT
MAT
TOG
TOG
TOG
TOG
TOG
PWM
PWM
PWM
PWM
PWM
ECCF
ECCF
ECCF
ECCF
ECCF
x0000000B
x0000000B
x0000000B
x0000000B
x0000000B
DF
CF
DE
CR
DD
–
DC
DB
DA
D9
D8
CCON*#
CH#
CL#
PCA Counter Control
PCA Counter High
PCA Counter Low
D8H
F9H
E9H
CCF4
CCF3
CCF2 CCF1
CCF0
00x00000B
00H
00H
CMOD#
PCA Counter Mode
D9H
CIDL
C7
WDTE
C6
–
–
–
CPS1 CPS0
ECF
00xxx000B
C5
C4
C3
C2
C1
C0
CMP*#
CMPE#
Comparator
C0H
92H
EC3DP EC2DP EC1DP EC0DP C3RO
C2RO C1RO
EC2O EC1O
C0RO
EC0O
00H
00H
Comparator Enable
EC3TDC EC2TDC EC1TDC EC0TDC
EC3O
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
00H
00H
AF
EA
AE
EC
EIB
AD
ET2
EAD
AC
ES
AB
AA
A9
A8
IE0*#
IE1*#
Interrupt Enable 0
Interrupt Enable 1
A8H
E8H
ET1
EC3
EX1
EC2
ET0
EC1
EX0
EC0
00H
00H
EOB
EC4
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
7
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
Table 1.
87C576 Special Function Registers (Continued)
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
ADDRESS MSB
LSB
BF
–
BE
PPC
PIB
86
BD
PT2
PAD
85
BC
PS
BB
PT1
PC3
83
BA
PX1
PC2
82
B9
PT0
PC1
81
B8
IP0*
Interrupt Priority 0
Interrupt Priority 1
B8H
F8H
PX0
PC0
80
x0000000B
00H
IP1*#
POB
87
PC4
84
P0*
P1*
P2*
P3*
Port 0
Port 1
Port 2
Port 3
80H
90H
A0H
B0H
AD7
97
AD6
96
AD5
95
AD4
94
AD3
93
AD2
92
AD1
91
AD0
90
FFH
–
–
ADIN5 ADIN4
ADIN3
A3
ADIN2 ADIN1 ADIN0 FFH
A7
ECI
B7
RD
A6
A5
T2
B5
T1
A4
T2EX
B4
A2
CEX2
B2
A1
CEX1
B1
A0
CEX0
B0
CEX4
B6
CEX3
B3
FFH
FFH
WR
T0
INT1
INT0
TxD
RxD
P0M1#
P0M2#
P1M1#
P1M2#
P2M1#
P2M2#
P3M1#
P3M2#
Port 0 Output Mode 1
Port 0 Output Mode 2
Port 1 Output Mode 1
Port 1 Output Mode 2
Port 2 Output Mode 1
Port 2 Output Mode 2
Port 3 Output Mode 1
Port 3 Output Mode 2
84H
85H
94H
95H
A4H
A5H
B4H
B5H
00H
00H
00H
3FH
00H
FFH
00H
FFH
1
1
1
1
WDT0F
SMOD1
D7
SMOD0
D6
PCON
Power Control
87H
OSF
D5
F0
–
POF
LVF
PD
D1
IDL
D0
00xxxx00B
D4
RS1
–
D3
D2
OV
PSW*
Program Status Word
PWM Control
D0H
BCH
CY
AC
RS0
–
P
00H
00H
EN/CLR
PWCON#
–
–
PWMF
PWE1
PWE0
PWMP#
PWM0#
PWM1#
PWM Prescaler
PWM Register 0
PWM Register 1
BDH
BEH
BFH
00H
00H
00H
RACAP2H#
RACAP2L#
Timer 2 Capture High
Timer 2 Capture Low
CBH
CAH
00H
00H
SADDR#
SADEN#
Slave Address
Slave Address Mask
A9H
B9H
00H
00H
SBUF
Serial Data Buffer
99H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SM0/FE
SCON*
SP
Serial Control
Stack Pointer
98H
81H
SM1
SM2
REN
TB8
RB8
00H
07H
8F
TF1
CF
TF2
–
8E
TR1
CE
8D
TF0
CD
8C
TR0
CC
8B
IE1
8A
IT1
CA
TR2
–
89
IE0
C9
88
IT0
C8
TCON*
Timer Control
88H
00H
CB
T2CON*
T2MOD#
Timer 2 Control
C8H
C9H
EXF2
–
RCLK
–
TCLK
–
EXEN2
–
C/T2
CP/RL2 00H
DCEN xxxxxxx0B
2
Timer 2 Mode Control
T2OE
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
1. Reset value depends on reset source.
2. Programmable clock-out
8
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
Table 1.
87C576 Special Function Registers (Continued)
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
ADDRESS MSB
LSB
TH0
TH1
TH2#
TL0
TL1
TL2#
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
Timer Low 1
Timer Low 2
8CH
8DH
CDH
8AH
8BH
CCH
00H
00H
00H
00H
00H
00H
TMOD
UCS#
Timer Mode
89H
86H
GATE
ST7
C/T
M1
M0
GATE
UE
C/T
AF
M1
M0
00H
00H
OBE/OBF
UPI Control/Status
ST6
ST5
ST4
IBF
WDRUN
WDCON
#
Watchdog Timer Control
Watchdog Timer Reload
C4H
PRE2
PRE1
PRE0
LVRE
OFRE
DPD
WDMOD 11111111B
WDL#
C1H
C2H
C3H
00H
xxH
xxH
WFEED1# Watchdog Feed 1
WFEED2# Watchdog Feed 2
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
1. Reset value depends on reset source.
The 8XC576 has a number of failure detect circuits to prevent
abnormal operating conditions. these failure detect circuits generate
resets as shown in Figure 1.
LOW ACTIVE RESET
One of the most notable features on this part is the low active reset.
The low active reset operates exactly the same as high active reset
with the exception that the part is put into the reset mode by
applying a low level to the reset pin. For power-on reset it is also
necessary to invert the power-on reset circuit; connecting the 8.2K
POWER ON CLEAR / POWER ON FLAG
An on-chip Power On Detect Circuit resets the 8XC576 and sets the
resistor from the reset pin to V and the 10µf capacitor from the
reset pin to ground. Figure 1 shows the reset related circuitry.
CC
Power Off Flag (PCON.4) on power up or if V drops to zero
CC
momentarily. The POF can only be cleared by software. The RST
pin is not driven by the power on detect circuit. The POF can be
read by software to determine that a power failure has occurred and
can also be set by software.
When reset the port pins on the 8XC576 are driven high
synchronously.
The 8XC576 also has Low voltage detection circuitry that will, if
enabled, force the part to reset when V (on the part) fails below a
CC
set level. Low Voltage Reset is enabled by a normal reset. Low
Voltage Reset can be disabled by clearing LVRE (bit 4 in the
WDCON SFR) then executing a watchdog feed sequence (A5H to
WFEED1 followed immediately by 5AH to WFEED2). In addition
there is a flag (LVF) that is set if a low voltage condition is detected.
The LVF flag is set even if the Low Voltage detection circuitry is
disabled. Notice that the Low voltage detection circuitry does not
drive the RST# pin so the LVF flag is the only way that the
microcontroller can determine if it has been reset due to a low
voltage condition.
LOW VOLTAGE DETECT
An on-chip Low Voltage Detect circuit sets the Low Voltage Flag
(PCON.3) if V drops below V
(see DC Electrical
CC
LOW
Characteristics) and resets the 8XC576 if the Low Voltage Reset
Enable bit (WDCON.4) is set. If the LVRE is cleared, the reset is
disabled but LVF will still be set if V is low. The RST pin is not
CC
driven by the low voltage detect circuit. The LVF can be read by
software to determine that V was low. The LVF can be set or
CC
cleared by software.
OSCILLATOR FAIL DETECT
The 8XC576 has an on-chip power-on detection circuit that sets the
POF (PCON.4) flag on power up or if the V level momentarily
An on-chip Oscillator Fail Detect circuit sets the Oscillator Fail Flag
(PCON.5) if the oscillator frequency drops below OSCF for one or
more cycles (see AC Electrical Characteristics: OSCF) and resets
the 8XC576 if the Oscillator Fail Reset Enable bit (WDCON.3) is set.
If OFRE is cleared, the reset is disabled but OSF will still be set if
the oscillator fails. The RST pin is not driven by the oscillator fail
detect circuit. The OSF can be read by software to determine that
an oscillator failure has occurred. The OSF can be set or cleared by
software.
CC
drops to 0V. This flag can be used to determine if the part is being
started from a power-on (cold start) or if a reset has occurred due to
another condition (warm start).
The 8XC576 can be reset in software by setting the RST bit of the
AUXR register (AUXR.3). See Figure 1 for reset diagram.
9
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
AUXR
(8EH)
–
–
–
–
SRST
LVF
TXI
LO
PD
AO
IDL
PCON
(87H)
V
CC
SMOD1
SMOD0
OSF
POF
WDTOF
POWER-ON DETECT
8xC576
INTERNAL
RESET
+
–
VLOW
(LOW V
CC
REFERENCE)
OSC FREQ BELOW OSCF
(MIN FREQUENCY)
RST
WDTE
PCA WATCHDOG
SHADOW REGISTER
FOR WDCON
WATCHDOG TIMER
SHADOW REGISTER
WATCHDOG FEED
PRE2
WDCON
PRE1
PRE0
–
LVRE
–
OFRE
–
DPD
WDRUN WDMOD
(C4H)
CMOD
(D9H)
CIDL
WDTE
CPS1
CPS0
ECF
SU00515B
Figure 1. Reset Circuitry
The PCA timer is a common time base for all five modules and can
be programmed to run at: 1/12 the oscillator frequency, 1/4 the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin
(P2.7). The timer count source is determined from the CPS1 and
CPS0 bits in the CMOD SFR as follows (see Figure 3):
TIMERS
The 8XC576 has four on-chip timers.
Timers 0 and 1 are identical in every way to Timers 0 and 1 on the
80C51.
Timer 2 on the 8XC576 is identical to the 80C52 Timer 2 (described
in detail in the 80C52 overview) with the exception that it is an up or
down counter. To configure the Timer to count down the DCEN bit in
the T2MOD special function register must be set and a low level
must be present on the T2EX pin (P1.1).
CPS1 CPS0 PCA Timer Count Source
0
0
1
1
0
1
0
1
1/12 oscillator frequency
1/4 oscillator frequency
Timer 0 overflow
External Input at ECI pin (P2.7)
The Pulse Width Modulator (PWM) system can be used as a timer
by disabling its outputs and monitoring its counter overflow flag, the
PWMF bit in the PWCON register (see the PWM section for details).
In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function on
module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 3.
The Watchdog timer operation and implementation is similar to the
8XC550 (for additional information see the 8XC550 datasheet) with
the exception that the reset values of the WDCON and WDL special
function registers have been changed. The changes in these
registers cause the watchdog timer to be enabled with a timeout of
The watchdog timer function is implemented in module 4 as
implemented in other parts that have a PCA that are available on the
market. However, if a watchdog timer is required in the target
application, it is recommended to use the hardware watchdog timer
that is implemented on the 87C576 separately from the PCA (see
Figure 15).
16384 × T
when the part is reset. The watchdog can be disabled
OSC
by executing a valid feed sequence and then clearing WDRUN (bit 2
in the WDCON SFR). In timer mode, the timer is controlled by
toggling the WDRUN bit. The timeout flag, WDTOF, is set when the
timer overflows and must be cleared in software.
The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and each module (refer to Figure 6). To
run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
PROGRAMMABLE COUNTER ARRAY (PCA)
The Programmable Counter Array is a special Timer that has five
16-bit capture/compare modules associated with it. Each of the
modules can be programmed to operate in one of four modes: rising
and/or falling edge capture, software timer, high-speed output, or
pulse width modulator. Each module has a pin associated with it in
port 2. Module 0 is connected to P2.0(CEX0), module 1 to
P2.1(CEX1), etc. The basic PCA configuration is shown in Figure 2.
10
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
also can only be cleared by software. The PCA interrupt system
shown in Figure 4.
16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both
the ECOM and MAT bits in the modules CCAPMn register. The PCA
timer will be compared to the module’s capture registers and when a
match occurs an interrupt will occur if the CCFn (CCON SFR) and
the ECCFn (CCAPMn SFR) bits for the module are both set (see
Figure 10).
Each module in the PCA has a special function register associated
with it. These registers are: CCAPM0 for module 0, CCAPM1 for
module 1, etc. (see Figure 7). The registers contain the bits that
control the mode that each module will operate in. The ECCF bit
(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt
when a match or compare occurs in the associated module. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG
bit (CCAPMn.2) when set causes the CEX output associated with
the module to toggle when there is a match between the PCA
counter and the module’s capture/compare register. The match bit
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter
and the module’s capture/compare register.
High Speed Output Mode
In this mode the CEX output (on port 2) associated with the PCA
module will toggle each time a match occurs between the PCA
counter and the module’s capture registers. To activate this mode
the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must
be set (see Figure 11).
Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. Figure 12
shows the PWM function. The frequency of the output depends on
the source for the PCA timer. All of the modules will have the same
frequency of output because they all share the PCA timer. The duty
cycle of each module is independently variable using the module’s
capture register CCAPLn. When the value of the PCA CL SFR is
less than the value in the module’s CCAPLn SFR the output will be
low, when it is equal to or greater than the output will be high. When
CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. the allows updating the PWM without glitches. The PWM
and ECOM bits in the module’s CCAPMn register must be set to
enable the PWM mode.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the
positive edge. If both bits are set both edges will be enabled and a
capture will occur for either transition. The last bit in the register
ECOM (CCAPMn.6) when set enables the comparator function.
Figure 8 shows the CCAPMn settings for the various PCA functions.
There are two additional registers associated with each of the PCA
modules. They are CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
PCA Interrupt System
The PCA on most 80C51 family devices provides a single interrupt
source, EC (IE.6). The 8xC576 expands the flexibility of the PCA by
providing additional interrupt sources for each of the five PCA
modules, EC0 (IE1.0) through EC4 (IE1.4), in addition to the original
interrupt source EC (IE.6). Any of these sources can be enabled at
any time. It is possible for both a module source (EC0 through EC4)
to be enabled at the same time that the single source, EC, is
enabled. In this case, a module event will generate an interrupt for
both the module source and the single source, EC.
PCA Capture Mode
To use one of the PCA modules in the capture mode either one or
both of the CCAPM bits CAPN and CAPP for that module must be
set. The external CEX input for the module (on port 2) is sampled for
a transition. When a valid transition occurs the PCA hardware loads
the value of the PCA counter registers (CH and CL) into the
module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit
for the module in the CCON SFR and the ECCFn bit in the CCAPMn
SFR are set then an interrupt will be generated. Refer to Figure 9.
16 BITS
P2.0/CEX0
P2.1/CEX1
P2.2/CEX2
P2.3/CEX3
MODULE 0
MODULE 1
16 BITS
PCA TIMER/COUNTER
MODULE 2
MODULE 3
MODULE 4
TIME BASE FOR PCA MODULES
MODULE FUNCTIONS:
16-BIT CAPTURE
16-BIT TIMER
P2.6/CEX4
SU00578
16-BIT HIGH SPEED OUTPUT
8-BIT PWM
WATCHDOG TIMER (MODULE 4 ONLY)
Figure 2. Programmable Counter Array (PCA)
11
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
TO PCA
MODULES
OSC/12
OSC/4
OVERFLOW
INTERRUPT
CH
CL
16–BIT UP COUNTER
TIMER 0
OVERFLOW
EXTERNAL INPUT
(P2.7/ECI)
00
01
10
11
DECODE
IDLE
CMOD
(D9H)
CIDL
CF
WDTE
––
––
––
––
CPS1
CCF2
CPS0
ECF
CCON
(D8H)
CR
CCF4
CCF3
CCF1
CCF0
SU00516
Figure 3. PCA Timer/Counter
CCON
(D8H)
CF
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
PCA TIMER/COUNTER
MODULE 0
IE0.7
EA
IE1.0
EC0
TO
INTERRUPT
PRIORITY
DECODER
MODULE 1
MODULE 2
IE0.7
EA
IE1.1
EC1
TO
INTERRUPT
PRIORITY
DECODER
MODULE 3
MODULE 4
IE0.7
EA
IE0.6
EC
TO
INTERRUPT
PRIORITY
DECODER
IE0.7
EA
IE1.2
EC2
CCAPMn.0
ECCFn
CMOD.0
ECF
TO
INTERRUPT
PRIORITY
DECODER
IE0.7
EA
IE1.3
EC3
TO
INTERRUPT
PRIORITY
DECODER
IE0.7
EA
IE1.4
EC4
TO
INTERRUPT
PRIORITY
DECODER
SU00579
Figure 4. PCA Interrupt System
12
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
CMOD Address = OD9H
Reset Value = 00XX X000B
CIDL
WDTE
–
–
–
CPS1
CPS0
ECF
Bit:
Function
7
6
5
4
3
2
1
0
Symbol
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode.
CIDL = 1 programs it to be gated off during idle.
WDTE
–
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
Not implemented, reserved for future use.*
CPS1
CPS0
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
CPS1
CPS0
Selected PCA Input**
0
0
1
1
0
1
0
1
0
1
2
3
Internal clock, f
÷ 12
÷ 4
OSC
Internal clock, f
OSC
Timer 0 overflow
External clock at ECI/P2.7 pin (max. rate = f
÷ 8)
OSC
ECF
PCA Enable Counter Overflow interrupt:
ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** –f
= oscillator frequency
OSC
SU00686A
Figure 5. CMOD: PCA Counter Mode Register
CCON Address = OD8H
Reset Value = 00X0 0000B
Bit Addressable
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
Bit:
7
6
5
4
3
2
1
0
Symbol
CF
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
–
Not implemented, reserved for future use*.
CCF4
CCF3
CCF2
CCF1
CCF0
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00036
Figure 6. CCON: PCA Counter Control Register
13
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
CCAPMn Address
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
0DAH
0DBH
0DCH
0DDH
0DEH
Reset Value = X000 0000B
Not Bit Addressable
–
ECOMn CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Bit:
7
6
5
4
3
2
1
0
Symbol
Function
–
Not implemented, reserved for future use*.
ECOMn
CAPPn
CAPNn
MATn
Enable Comparator. ECOMn = 1 enables the comparator function.
Capture Positive, CAPPn = 1 enables positive edge capture.
Capture Negative, CAPNn = 1 enables negative edge capture.
Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit
in CCON to be set, flagging an interrupt.
TOGn
Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn
pin to toggle.
PWMn
ECCFn
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output.
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00037
Figure 7. CCAPMn: PCA Modules Compare/Capture Registers
–
X
X
X
X
X
X
X
X
ECOMn CAPPn CAPNn
MATn
TOGn
PWMn
ECCFn
MODULE FUNCTION
0
X
X
X
1
1
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
X
0
0
0
0
0
0
1
0
0
X
X
X
X
X
0
No operation
16-bit capture by a positive-edge trigger on CEXn
16-bit capture by a negative trigger on CEXn
16-bit capture by a transition on CEXn
16-bit Software Timer
16-bit High Speed Output
8-bit PWM
X
Watchdog Timer
Figure 8. PCA Module Modes (CCAPMn Register)
14
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
CCON
(D8H)
CF
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
PCA INTERRUPT
(TO CCFn)
PCA TIMER/COUNTER
CH
CL
CAPTURE
CEXn
CCAPnH
CCAPnL
CCAPMn, n= 0 to 4
(DAH – DEH)
––
ECOMn
0
CAPPn
CAPNn
MATn
0
TOGn
0
PWMn
ECCFn
0
SU00749
Figure 9. PCA Capture Mode
CCON
(D8H)
CF
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
WRITE TO
CCAPnH
RESET
PCA INTERRUPT
CCAPnH
CCAPnL
WRITE TO
CCAPnL
(TO CCFn)
0
1
ENABLE
MATCH
16–BIT COMPARATOR
CH
CL
PCA TIMER/COUNTER
CCAPMn, n= 0 to 4
(DAH – DEH)
––
ECOMn
CAPPn
0
CAPNn
0
MATn
TOGn
0
PWMn
0
ECCFn
SU00750
Figure 10. PCA Compare Mode
15
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
CCON
(D8H)
CF
CR
––
CCF4
CCF3
CCF2
CCF1
CCF0
WRITE TO
CCAPnH
RESET
PCA INTERRUPT
CCAPnH
CCAPnL
WRITE TO
CCAPnL
(TO CCFn)
0
1
MATCH
ENABLE
16–BIT COMPARATOR
TOGGLE
CEXn
CH
CL
PCA TIMER/COUNTER
CCAPMn, n: 0..4
(DAH – DEH)
––
ECOMn
CAPPn
0
CAPNn
0
MATn
TOGn
PWMn
0
ECCFn
1
SU00751
Figure 11. PCA High Speed Output Mode
CCAPnH
CCAPnL
0
CL < CCAPnL
ENABLE
8–BIT
CEXn
COMPARATOR
CL >= CCAPnL
1
CL
OVERFLOW
PCA TIMER/COUNTER
CCAPMn, n: 0..4
(DAH – DEH)
––
ECOMn
CAPPn
0
CAPNn
MATn
0
TOGn
0
PWMn
ECCFn
0
0
SU00752
Figure 12. PCA PWM Mode
16
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
WATCHDOG TIMER
• Watchdog mode bit set to watchdog mode.
• Watchdog is running.
• Autoload register set to 00 (min. count).
• Watchdog time-out flag is unchanged.
• Prescaler is cleared.
• Prescaler tap set to the highest divide.
• Autoload takes place.
The watchdog timer is not directly loadable by the user. Instead, the
value to be loaded into the main timer is held in an autoload register
or is part of the mask ROM programming. In order to cause the main
timer to be loaded with the appropriate value, a special sequence of
software action must take place. This operation is referred to as
feeding the watchdog timer.
To feed the watchdog, two instructions must be sequentially
executed successfully. No intervening instruction fetches are
allowed, so interrupts should be disabled before feeding the
watchdog. The instructions should move A5H to the WFEED1
register and then 5AH to the WFEED2 register. If WFEED1 is
correctly loaded and WFEED2 is not correctly loaded, then an
immediate underflow will occur.
The watchdog can be fed even though it is in the timer mode.
Note that the operational concept is for the watchdog mode of
operation, when coming out of a hardware reset, the software
should load the autoload registers, set the mode to watchdog, clear
the watchdog timeout flag, and then feed the watchdog (cause an
autoload). The watchdog will now be starting at a known point.
The watchdog timer subsystem has two modes of operation. Its
principal function is a watchdog timer. In this mode it protects the
system from incorrect code execution by causing a system reset
when the watchdog timer underflows as a result of a failure of
software to feed the timer prior to the timer reaching its terminal
count. If the user does not employ the watchdog function, the
watchdog subsystem can be used as a timer. In this mode, reaching
the terminal count sets a flag. In most other respects, the timer
mode possesses the characteristics of the watchdog mode. This is
done to protect the integrity of the watchdog function.
If the watchdog is in the watchdog mode and running and happens
to underflow at the time the external RESET is applied, the
watchdog time-out flag will be set.
When the watchdog is in the watchdog mode and the watchdog
underflows, the following action takes place (see Figure 17):
• Autoload takes place.
• Watchdog time-out flag is set
• Mode bit unchanged.
• Watchdog run bit unchanged.
• Autoload register unchanged.
• Prescaler tap unchanged.
The watchdog timer subsystem consists of a prescaler and a main
counter. The prescaler has 8 selectable taps off the final stages and
the output of a selected tap provides the clock to the main counter.
The main counter is the section that is loaded as a result of the
software feeding the watchdog and it is the section that causes the
system reset (watchdog mode) or time-out flag to be set (timer
mode) if allowed to reach its terminal count.
• All other device action same as external reset.
Note that if the watchdog underflows, the program counter will start
from 00H as in the case of an external reset. The watchdog time-out
flag can be examined to determine if the watchdog has caused the
reset condition. The watchdog time-out flag bit must be cleared by
software.
Programming the Watchdog Timer
Both the EPROM and ROM devices have a set of SFRs for holding
the watchdog autoload values and the control bits. The watchdog
time-out flag is present in the PCON register and operates the same
in all versions. In the EPROM device, the watchdog parameters
(autoload value and control) are always taken from the SFRs. In the
ROM device, the watchdog parameters can be mask programmed
or taken from the SFRs. The selection to take the watchdog
parameters from the SFRs or from the mask programmed values is
controlled by EA (external access). When EA is high (internal ROM
access), the watchdog parameters are taken from the mask
programmed values. If the watchdog is mask programmed to the
timer mode, then the autoload values and the pre-scaler taps are
taken from the SFRs. When EA is low (external access), the
watchdog parameters are taken from the SFRs. The user should be
able to leave code in his program which initializes the watchdog
SFRs even though he has migrated to the mask ROM part. This
allows no code changes from EPROM prototyping to ROM coded
production parts. The run control bit only functions in timer mode
and does not require a feed sequence to modify.
When the watchdog is in the timer mode and the timer software
underflows, the following action takes place:
• Autoload takes place.
• Watchdog time-out flag is set
• Mode bit unchanged.
• Watchdog run bit unchanged.
• Autoload register unchanged.
• Prescaler tap unchanged.
Mask ROM Device (EA = 1)
In the mask ROM device, the watchdog mode bit (WDMOD) is mask
programmed and the bit in the watchdog command register is read
only and reflects the mask programmed selection. If the mask
programmed mode bit selects the timer mode, then the watchdog
run bit (WDRUN) operates as described under EPROM Device. If the
mask programmed bit selects the watchdog mode, then the watchdog
run bit has no effect on the timer operation (see Figure 16).
Watchdog Detailed Operation
EPROM Device (and ROMless Operation: EA = 0)
In the ROMless operation (ROM part, EA = 0) and in the EPROM
device, the watchdog operates in the following manner (see
Figure 15).
Watchdog Function
The watchdog consists of a programmable prescaler and the main
timer. The prescaler derives its clock from the on-chip oscillator. The
prescaler consists of a divide by 2 followed by a 13 stage upcounter
with taps from stage 6 through stage 13. This is shown in Figure 18.
Whether the watchdog is in the watchdog or timer mode, when
external RESET is applied, the following takes place:
17
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
The tap selection is programmable. The watchdog main counter is a
down counter clocked (decremented) each time the programmable
prescaler overflows. The watchdog generates an underflow signal
(and is autoloaded) when the watchdog is at count 0 and the prescaler
clock decrements the watchdog. The watchdog is 8 bits long and the
autoload value can range from 0 to FFH. (The autoload value of 0 is
permissible since the prescaler is cleared upon autoload).
Additional bits in WDCON are used to disable reset generation by
the oscillator fail and low voltage detect circuits. WDCON can be
written by software only by executing a valid watchdog feed
sequence.
WDCON Register Bit Definitions
WDCON.7 PRE2
WDCON.6 PRE1
WDCON.5 PRE0
WDCON.4 LVRE
Prescaler Select 2, reset to 1
Prescaler Select 1, reset to 1
Prescaler Select 0, reset to 1
Low Voltage Reset Enable, reset to 1
(enabled)
This leads to the following user design equations. Definitions :t
OSC
is the oscillator period, N is the selected prescaler tap value, W is
the main counter autoload value, t is the minimum watchdog
MIN
time-out value (when the autoload value is 0), t
is the maximum
MAX
WDCON.3 OFRE
WDCON.2 DPD
Oscillator Fail Reset Enable, reset to 1
(enabled)
Disable Power Down
time-out value (when the autoload value is FFH), t is the design
D
time-out value.
WDCON.1 WDRUN Watchdog Run, reset to 1 (enabled)
WDCON.0 WDMOD Watchdog Mode, reset to 1 (watchdog
mode)
t
t
t
= t
× 2 × 64
OSC
MIN
= t
× 128 × 256
MIN
MAX
PRESCALER
= t
× 2
MIN
× (W + 1)
D
Enhanced UART
(where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7)
The UART operates in all of the usual modes that are described in
the first section of this book for the 80C51. In addition the UART can
perform framing error detect by looking for missing stop bits, and
automatic address recognition. The 8XC576 UART also fully
supports multiprocessor communication as does the standard
80C51 UART.
Note that the design procedure is anticipated to be as follows. A
t
will be chosen either from equipment or operation
MAX
considerations and will most likely be the next convenient value
higher than t . (If the watchdog were inadvertently to start from 00H,
D
an underflow would be guaranteed, barring other anomalies, to
occur within t
).
MAX
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure
20). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 19.
The software must be written so that a feed operation takes place
every t seconds from the last feed operation. Some tradeoffs may
D
need to be made. It is not advisable to include feed operations in
minor loops or in subroutines unless the feed operation is a specific
subroutine.
Watchdog Control Register (WDCON)
Address C4H
The serial port transmitter data can be inverted by setting the TXI
(AUXR.2) bit. For normal operation, the TXI bit should be cleared.
The following bits of this register are read only in the ROM part
when EA is high: WDMOD, DPD, OFRE, LVRE, PRE0, PRE1, and
PRE2. That is, the register will reflect the mask programmed values.
In the ROM part with EA high, these bits are taken from mask coded
bits and are not readable by the program. WDRUN is read only in
the ROM part when EA is high and WDMOD is in the watchdog
mode. When WDMOD is in the timer mode, WDRUN functions
normally.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 21.
The parameters written into WDMOD, DPD, OFRE, LVRE, PRE0,
PRE1, and PRE2 by the program are not applied directly to the
watchdog timer subsystem. The watchdog timer subsystem is
directly controlled by a second register which stores these bits. The
transfer of these bits from the user register to the second control
register takes place when the watchdog is fed. This prevents
random code execution from directly foiling the watchdog function.
This does not affect the operation where these bits are taken from
mask coded values.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
The reset values of the WDCON and WDL registers will be such that
the timer resets to the watchdog mode with a timeout period of 2 ×
Mode 0 is the Shift Register mode and SM2 is ignored.
64 × 128 × t
. The watchdog timer does not generate an interrupt.
OSC
18
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
TXD
P3.1
PIN
TXI
INT. BUS
D
Q
P3.1
LATCH
WRITE TO LATCH
PROGRAMMABLE OUTPUT BUFFER
SU00711
Figure 13. TXI (AUXR.2) Bit Inverts the TxD Pin (P3.1) When Set
CMOD
ECF
CIDL
WDTE
––
––
––
CPS1
CPS0
(D9H)
WRITE TO
CCAP4H
RESET
CCAP4H
CCAP4L
WRITE TO
CCAP4L
0
1
ENABLE
MATCH
16–BIT COMPARATOR
RESET
CH
CL
PCA TIMER/COUNTER
CCAPM4
ECCFn
––
ECOMn
CAPPn
0
CAPNn
0
MATn
1
TOGn
X
PWMn
0
(DEH)
X
SU00042
Figure 14. PCA Watchdog Timer
WDL
(C1H)
WATCHDOG FEED SEQUENCE
MOV WFEED1,#0A5H
MOV WFEED2,#5AH
WDTOF (PCON.2)
8–BIT DOWN
COUNTER
PRESCALER
OSC/2
RESET
SHADOW REGISTER
FOR WDCON
WDCON
(C4H)
PRE2
PRE1
PRE0
LVRE
OFRE
DPD
WDRUN
WDMOD
SU00657C
Figure 15. Watchdog Timer in 87C576 and 80C576 / 83C576 (EA = 0)
19
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
ROM–CODE
CONTENT
WDL
WDCON
ADDRESS
2031H
2030H
WATCHDOG FEED SEQUENCE
MOV WFEED1,#0A5H
MOV WFEED2,#5AH
8–BIT DOWN
COUNTER
RESET
WDTOF (PCON.2)
OSC/2
PRESCALER
1
1
WDCON
(C4H)
PRE2
PRE1
PRE0
LVRE
OFRE
DPD
WDRUN
WDMOD
SU00658C
Figure 16. Watchdog Timer of 83C576 in Watchdog Mode (EA = 1, WDMOD = 1)
ROM–CODE
WDL
(C1H)
CONTENT
WDCON
ADDRESS
2030H
WATCHDOG FEED SEQUENCE
MOV WFEED1,#0A5H
MOV WFEED2,#5AH
8–BIT DOWN
COUNTER
OSC/2
PRESCALER
WDTOF (PCON.2)
0
WDCON
(C4H)
PRE2
PRE1
PRE0
LVRE
OFRE
DPD
WDRUN
WDMOD
SU00659C
Figure 17. Watchdog Timer of 83C576 in Timer Mode (EA = 1, WDMOD = 0)
20
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
OSC/2
÷64
÷2
÷2
÷2
÷2
÷2
÷2048
÷2
÷2
÷64
÷128
÷256
÷512
÷1024
÷4096
÷8192
TO WATCHDOG
DOWN COUNTER
000
001
010
011
PRE2
PRE1
DECODE 100
101
110
111
PRE0
SU00660
Figure 18. Watchdog Prescaler
SCON Address = 98H
Bit Addressable
SM0/FE
Reset Value = 0000 0000B
SM1
SM2
REN
TB8
RB8
Tl
Rl
Bit:
7
6
5
4
3
2
1
0
(SMOD0/1)*
Symbol
FE
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
SM0
SM1
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
f /12
OSC
0
0
1
1
0
1
0
1
0
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
variable
/64 or f
f
/32
OSC
OSC
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
TB8
RB8
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0/1 is located at PCON.6, PCON.7
**f = oscillator frequency
OSC
SU00766
Figure 19. SCON: Serial Port Control Register
21
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
D0
D1
D2
D3
D4
D5
D6
D7
D8
START
BIT
DATA BYTE
ONLY IN
MODE 2, 3
STOP
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SCON
(98H)
SM0 / FE
SMOD1
SM1
SM2
REN
POF
TB8
LVF
RB8
GF0
TI
RI
PCON
(87H)
SMOD0
–
GF1
IDL
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU00044
Figure 20. UART Framing Error Detection
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to be used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Slave 1
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1010
1110 0X0X
Slave 2
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1100
1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary t make bit 2 = 1 to exclude slave 2.
Slave 0
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1101
1100 00X0
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are treated
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Slave 1
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1110
1100 000X
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are loaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. this effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
Analog Comparators
Four analog comparators are provided on chip. Three comparators
have a common negative reference CMPR- and independent
positive inputs CMP1+, CMP2+, CMP3+ on port 3. The fourth
comparator has independent positive and negative inputs CMP0+
and CMP0- on port 2. The CMP register contains an output and
enable bit for each comparator. Figure 22 shows the connection of
the comparators.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1001
1100 0XX0
When the comparator is enabled, the port should be configured by
the user as high impedance.
22
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
D0
D1
D2
D3
D4
D5
D6
D7
D8
SCON
(98H)
SM0
SM1
SM2
REN
1
TB8
X
RB8
TI
RI
1
1
1
0
1
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 21. UART Multiprocessor Communication, Automatic Address Recognition
CMP Register Bit Definitions
CMP.7 enable comparator 3
CMP.6 enable comparator 2
CMP.5 enable comparator 1,
and a bit that can be read by software to determine the state of each
comparator’s output, and CMPE which controls whether the output
from each comparator drives the associated output pin or a capture
input associated with one of the PCA modules.
CMP.4 enable comparator 0
The CMP registers bits 0–3 can be read by software to determine
the state of the output of each comparator. To do this the associated
comparator must be enabled but the output in port 2 can be
disabled. This allows easy polling of the comparator output value
without the need to use up a port pin.
CMP.3 comparator 3 output (read only)
CMP.2 comparator 2 output (read only)
CMP.1 comparator 1 output (read only)
CMP.0 comparator 0 output (read only)
All comparators are disabled automatically in power down mode. In
idle mode unused comparators should be disabled by software to
save power. A comparator can generate an interrupt that will
terminate idle mode when used to drive a PCA capture input.
The CMPE register allows the comparator to drive the associated
PCA module capture input, so that on compare a capture can be
generated in the PCA. Bits 0–3 of this register enable the
comparator output to drive the associated port 2 output circuitry.
Used as a comparator output, the output mode for this port must be
configured for output by the user and the port output SFR bit latch
must be set. If the comparator is not enabled to drive the port 2
circuitry, the associated port 2 pin can be used for other I/O. This
includes when a comparator is enabled to drive the capture input to
a PCA module.
The CMPE register contains bits to enable each comparator to drive
external output pins or internal PCA capture inputs. When the
comparator is configured for external output, the user must also
configure the output port in one of its output modes. The comparator
output is wire-ORed with the corresponding port SFR bit, so the
SFR bit must also be set by software to enable the output.
CMPE Register Bit Definitions
Reduced EMI Mode
CMPE.7 enables comparator 3 to drive CEX3
CMPE.6 enables comparator 2 to drive CEX2
CMPE.5 enables comparator 1 to drive CEX1
CMPE.4 enables comparator 0 to drive CEX0
CMPE.3 enables comparator 3 output on P2.3
CMPE.2 enables comparator 2 output on P2.2
CMPE.1 enables comparator 1 output on P2.1
CMPE.0 enables comparator 0 output on P2.0
There are two bits in the AUXR register that can be set to reduce
the internal clock drive and disable the ALE output. AO (AUXR.0)
when set turns off the ALE output. LO (AUXR.1) when set reduces
the drive of the internal clock circuitry. Both bits are cleared on
Reset. With LO set the 8XC576 will still operate at 12MHz, and will
have reduced EMI in the range above 100MHz.
8XC576 Reduced EMI Mode
AUXR (0X8E)
When 1s are written to CMPE bits 7-4, the comparator outputs will
drive the corresponding capture input. When 1s are written to CMPE
bits 3-0 the comparator output will also drive the corresponding
port 2 pin. If the comparator’s enabled to drive the capture input but
not the port pin, then the port pin can be used for general purpose
I/O. When a comparator output is enabled, the user will need to
configure the port for one of its output modes.
––
––
––
––
RST
TXI
LO
AO
AO: Turns off ALE output.
LO: Reduces drive of internal clock circuitry. 8XC576 spec’d to
12MHz when LO set.
TXI: Inverts TxD when set.
RST: Software reset.
There are two special function registers associated with the
comparators. They are CMP which contains the comparator enables
23
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
CMPE
(92H)
EC3TDC
EC2TDC
EC1TDC
EC0TDC
EC3OD *
EC2OD *
EC1OD *
EC0OD *
P3.6 / CMP0+
P3.7 / CMP0–
+
P2.0 / CMP0
P2.1 / CMP1
P2.2 / CMP2
P2.3 / CMP3
–
TO CEX0 INPUT OF
PCA MODULE 0
ENABLE
+
P3.4 / CMP1+
P3.3 / CMP2+
–
TO CEX1 INPUT OF
PCA MODULE 1
ENABLE
+
–
TO CEX2 INPUT OF
PCA MODULE 2
ENABLE
+
P3.2 / CMP3+
P3.5 / CMPR–
–
TO CEX3 INPUT OF
PCA MODULE 3
ENABLE
* : WILL DISABLE PULLUPS
ON RELEVANT PINS
CMP
(C0H)
EC3DP *
EC2DP *
EC1DP *
EC0DP *
C3RO
C2RO
C1RO
C0RO
SU00517C
Figure 22. Analog Comparators
AMOD1 ADCON.4 – A/D mode select bit 1
AMOD0 ADCON.3 – A/D mode select bit 0
ASCA2 ADCON.2 – A/D channel address bit 2
ASCA1 ADCON.1 – A/D channel address bit 1
ASCA0 ADCON.0 – A/D channel address bit 0
INTERNAL RESET
Internal resets (see Figure 1) generated by the power on, low
voltage, software (SRST), watchdog and oscillator fail detect circuits
are self timed to guarantee proper initialization of the 8XC576. Reset
will be held approximately 24 oscillator periods after normal
conditions are detected by all enabled detect circuits. Internal resets
do not drive RST but will cause missing pulses on ALE.
AMOD1 AMOD0
0
0
Single Conversion Mode – channel selected by bits
ASCA2..0 in ADCON is converted, the result placed
in the associated result registers; ADF is set on
completion.
Analog to Digital Converter
The 8XC576 has a 6 channel10 bit successive approximation A/D
converter with separate result registers for each channel. Operating
modes are provided for single or multiple channel conversions and
multiple conversions of a single channel without software
intervention. The ADC can also be operated in 8 bit mode with faster
conversion times. Registers ADC0H–ADC5H contain the MSBs and
ADC0L–ADC5L bits 6 and 7 contain the 2 LSBs of the conversion
result for each channel. The ADCS register determines which
channels are converted in multiple channel modes. If the ADCS bit
corresponding to a channel is set, that channel is converted, else if
the bit is clear the channel is skipped.
0
1
Mulitple Channel Scan Mode – all channels selected
in the ADCS register are converted starting with the
channel addressed by bits ASCA2..0 in ADON,
conversion results are placed in the corresponding
result registers for each channel. ADF is set when
the last conversion is completed.
1
1
0
1
Single Channel Multiple Conversion – channel
selected by bits ASCA2..0 in ADCON is converted 6
times and all 6 results are saved in ADC0H–ADC5H
and ADC0L–ADC5L, ADF is set when all
conversions are complete.
A/D Channel Select (ADCS) Register (Reset Value = 00H)
ADCS5 ADCS.5 – A/D channel 5 select bit
ADCS4 ADCS.4 – A/D channel 4 select bit
ADCS3 ADCS.3 – A/D channel 3 select bit
ADCS2 ADCS.2 – A/D channel 2 select bit
ADCS1 ADCS.1 – A/D channel 1 select bit
ADCS0 ADCS.0 – A/D channel 0 select bit
Multiple Channel Continuous – same as Multiple
Channel Scan mode but repeats as long as
ADCE=1, ADF is set when all channels have been
converted once. Hardware will prevent the ADC
from wiriting to the result registers while they are
being read.
A/D Control (ADCON) Register (Reset Value = 00H)
ADF
ADCON.7 – A/D conversion complete flag
Flag ADF is set upon completion of a conversion, if the ADC
interrupt enable bit EAD is set, the program will vector to the ADC
interrupt location when ADF is set.
ADCE ADCON.6 – A/D conversion enable
AD8M ADCON.5 – A/D 8-bit mode
24
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
Pulse Width Modulator Control Register Bit Definitions
(PWCON = BCH)
PWMs
The pulse width modulator system of the 8XC576 contains two
PWM output channels. These channels generate pulses of
programmable length and interval. The prescaler and counter are
common to both PWM channels.
PWMF
PWCON.3
Counter overflow flag,
must be cleared by software
Counter enable and counter/prescaler
reset when Low
EN/CLR
PWCON.2
The prescaler is loaded with the complement of the PWMP register
during counter overflow, internal reset, and when EN/CLR# = 0. The
repetition frequency is defined by the 8-bit prescaler which clocks
the counter. The prescaler division factor = PWMP+1. Reading the
PWMP gives the current reload value. The actual count of the
prescaler cannot be read.
PWE1
PWE0
PWCON.1
PWCON.0
PWM1 output to P2.7 pin enable
PWM0 output to P2.6 pin enable
Auxiliary Register Bit Definitions (AUXR =8EH)
RST AUXR.3 Software reset bit
TXI AUXR.2 SIO TxD invert
LO AUXR.1 Low Speed, reduces internal clock drive
AO AUXR.0 ALE Off, when set turns off ALE
The 8-bit counter counts from 0–254 inclusive. The value of the
counter is compared to the contents of the compare registers PWM0
and PWM1. When the counter compares to the compare register,
that register’s output goes LOW. When the counter reaches zero the
output is set HIGH unless PWMn = 00H. The duty cycle of each
channel is defined by the contents of its compare register and is in
the range of 0 to 1, programmed in increments of 1/255.
Interrupt Enable 0 (IE0) Register
EA
EC
ET2 IE0.5
ES IE0.4
ET1 IE0.3
EX1 IE0.2
ET0 IE0.1
EX0 IE0.0
IE0.7
IE0.6
Enable all interrupts
Enable PCA interrupt
Enable Timer 2 interrupt
Enable Serial I/O interrupt
Enable Timer 1 interrupt
Enable External interrupt 1
Enable Timer 0 interrupt
Enable External interrupt 0
The outputs can be set continuously low by loading PWMn with 00H
and continuously high by loading with FFH.
The PWM counter is enabled with bit EN/CLR# of the PWCON
register. Output to the port pin is separately enabled by setting the
PWEn bits in the PWCON register. The counter remains active if
EN/CLR# is set even if both PWEn bits are reset. The PWM function
is reset by a chip reset. In idle mode, the PWM will function as
configured by PWCON. In power-down the state of the PWM will
freeze when the internal clock stops. If the chip is awakened with an
external interrupt, the PWM will continue to function from its state
when power-down was entered. The EN/CLR# bit of PWCON will
clear the counter and load the contents of the PWMP into the
prescaler when set LOW. If PWEn is set at this time the output will
go HIGH unless PWMn is 00H.
Interrupt Enable 1 (IE1) Register
EOB IE1.7
EIB IE1.6
Enable OBE interrupt
Enable IBF interrupt
EAD IE1.5
EC4 IE1.4
EC3 IE1.3
EC2 IE1.2
EC1 IE1.1
EC0 IE1.0
Enable ADC interrupt
Enable PCA module 4 interrupt
Enable PCA module 3 interrupt
Enable PCA module 2 interrupt
Enable PCA module 1 interrupt
Enable PCA module 0 interrupt
Interrupt Priority 0 (IP0) Register
IP0.7
PPC IP0.6
PT2 IP0.5
(reserved)
PCA interrupt priority
Timer 2 interrupt priority
Serial I/O interrupt priority
Timer 1 interrupt priority
External interrupt 1 priority
Timer 0 interrupt priority
External interrupt 0 priority
The repetition frequency is given by:
fOSC
PS
IP0.4
PT1 IP0.3
PX1 IP0.2
PT0 IP0.1
PX0 IP0.0
fPWM
+
(510 (1 ) PWMP))
An oscillator frequency of 12MHz results in a repetition range of
92Hz to 23.5KHz.
Interrupt Priority 1 (IP1) Register
The high/low ratio of PWMn is PWMn/(255–PWMn) for PWMn
values except 255. A PWMn value of 255 results in a high PWMn
output.
POB IP1.7
PIB IP1.6
OBE interrupt priority
IBF interrupt priority
PAD IP1.5
PC4 IP1.4
PC3 IP1.3
PC2 IP1.2
PC1 IP1.1
PC0 IP1.0
ADC interrupt priority
In order for the PWMn output to be used as a standard I/O pin,
PWMn must be reset. The PWM counter can still be used as an
internal timer by setting EN/CLR#.
PCA module 4 interrupt priority
PCA module 3 interrupt priority
PCA module 2 interrupt priority
PCA module 1 interrupt priority
PCA module 0 interrupt priority
25
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
1/2
f
OSC
INTERNAL
BUS
8-BIT
UP
COUNTER
PWMP
REG
8-BIT
PRESCALER
8-BIT
DETECT
OUTPUT
BUFFER
P2.6
PWM0
PWM1
8-BIT
DETECT
OUTPUT
BUFFER
P2.7
SU00256A
Figure 23. Block Diagram of PWMs
PCA Interrupt System
from the host CPU bus, which qualifies RD and WR (these pins
have no effect when CS=1). The A0 pin is an address input from the
host CPU which selects either the port 0 output buffer or the UCS
register to be output during a read operation. During a write
operation, the value of the A0 pin is latched in the AF flag in the
UCS register. The following is a summary of the UPI data control
inputs:
The PCA on most 80C51 family devices provides a single interrupt
source, EC (IE.6). The 8xC576 expands the flexibility of the PCA by
providing additional interrupt sources for each of the five PCA
modules, EC0 (IE1.0) through EC4 (IE1.4), in addition to the original
interrupt source EC (IE.6). Any of these sources can be enabled at
any time. It is possible for both a module source (EC0 through EC4)
to be enabled at the same time that the single source, EC, is
enabled. In this case, a module event will generate an interrupt for
both the module source and the single source, EC.
CS RD WR A0
0
0
1
0
read port 0 output buffer,
clear OBF/set OBE
Priority Source
Flag
IE0
ADF
Vector
03H
3BH
0BH
13H
1BH
23H
43H
4BH
53H
5BH
63H
33H
0
0
0
1
0
1
1
x
1
0
0
x
1
0
1
x
read UPI control/ status register
write data to input buffer set IBF, clear AF
write command to input buffer set IBF, AF
disable input/output
1
2
INT0
ADC
highest priority
3
4
TIMER 0 TF0
INT1 IE1
5
6
TIMER 1 TF1
SERIAL RI,TI
UPI Control Status Register (UCS, Reset value = 00H)
UCS.7
UCS.6
UCS.5
UCS.4
UCS.3
ST7
ST6
ST5
ST4
UE
User defined status bit
User defined status bit
User defined status bit
User defined status bit
7
8
9
10
11
12
13
14
15
PCA0
PCA1
PCA2
PCA3
PCA4
PCA
CC0
CC1
CC2
CC3
CC4
ECF
UPI Enable bit – if UE=1, UPI is enabled
(read only AF, IBF, and OBE/OBF), if UE=0,
UPI is disabled and port 0 functions
normally.
Address Flag – contains status of the A0
(address) pin during the last write. If A0=0,
the input buffer should be interpreted as
data by the 8XC576 software, if A0=1, the
input buffer should be interpreted as a
command.
Input Buffer Full flag – set by hardware on
trailing (rising) edge of WR when CS=0,
cleared by hardware when port 0 SFR is
read (by the 8XC576 software).
Output Buffer Full flag – set by hardware
during writes (by 8XC576 software) to the
port 0 SFR, set/cleared by hardware on the
trailing (rising) edge of RD when CS=0 and
A0=0.
TIMER 2 TF2/EXF2 2BH
UPI
UPI
IBF
OBE
6BH
73H
UCS.2
AF
lowest priority
Power Control (PCON) Register
SMOD1
SMOD0
OSF
POF
LVF
WDTOF
PD
IDL
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
double baud rate bit
SCON.7 access control
oscillator fail flag
power off flag
USC.1
USC.0
IBF
low voltage flag
watchdog timeout flag
power down mode bit
idle mode bit
OBE/OBF
UNIVERSAL PERIPHERAL INTERFACE
UPI mode allows the 8XC576 to function as a slave processor
connected to a host CPU bus via port 0. The interface consists of
port 0 input and output buffer registers and the UPI control/status
register (UCS). UPI mode is enabled by setting the UPI enable bit
(UE) in the UCS. When operating in UPI mode, port 0 pins should
be programmed to High-Z (P0M1=1 and P0M2=0) by user firmware.
Access to port 0 is controlled by inputs WR, RD, CS, and A0. RD
and WR are the external read and write strobes controlled by the
host CPU. CS is the chip select input, normally a decoded address
NOTE: This bit is defined as OBE (1=empty) when read by the
MCU, and, as OBF (—full) when read by the external host.
The IBF and OBF flag bits reflect the status of the input/output
buffers. The host CPU writes to the 8XC576 by driving data on the
external bus connected to port 0 and strobing the WR pin while
CS=0. The WR strobe latches port 0 data in the input buffer and
sets the IBF flag on the trailing (rising) edge. When the 8XC576
reads from port 0 in UPI mode, it reads from the input buffer and
26
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
clears the IBF. When the 8XC576 writes to port 0 in UPI mode, it
writes to the output buffer which sets the OBF and clears the OBE
flag. The host CPU can read the output buffer or the UCS register
enabling the port 0 drivers, the OBF flag is cleared and the OBE flag
is set when the output buffer is read.
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset. Also see UPI section.
When the UPI is enabled, the AF, IBF, and OBE/OBF flags are
read-only, and thus can only be modified by specific hardware
events.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. The control
bits for the reduced power modes are in the special function register
PCON. Power-down mode can be terminated with either a hardware
reset or external interrupt. With an external interrupt INT0 or INT1
must be enabled and configured as level sensitive. Holding the pin
low restarts to oscillator and bringing the pin back high completes
the exit.
The UPI runs in idle mode. It can interrupt the part out of Idle mode
for all UPI write and data read operations. It will not interrupt out of
idle mode for a UCS register read operation.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 4.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Power-down mode can be disabled by the DPD bit in the WDCON
register. Reset and waking up from power-down will also enable the
DPD bit, therefore, the DPD bit must be cleared again before the
power-down mode.
DESIGN CONSIDERATIONS
At power-on, the voltage on V must come up with RST low for a
proper start-up.
CC
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
Table 2 shows the state of I/O ports during low current operating
modes.
Table 2. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
Internal
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
1
1
0
0
1
1
0
0
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
27
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
ROM CODE SUBMISSION
When submitting ROM code for the 83C576, the following must be specified:
1. 8k byte user ROM data
2. 32 byte ROM encryption key
3. ROM security bits
4. The watchdog timer parameters. (See Watchdog Timer Specifications for definition of WDL and WDCON bits.)
ADDRESS
CONTENT
DATA
BIT(S)
7:0
COMMENT
0000H to 1FFFH
2000H to 201FH
User ROM Data
KEY
7:0
ROM Encryption Key
FFH = no encryption
2020H
SEC
0
1
ROM Security Bit 1
0 = enable security
1 = disable security
ROM Security Bit 2
0 = enable security
1 = disable security
2030H
WDCON
7:5
4
PRE2:0
LVRE
3
OFRE
2
DPD
1
WDRUN = 0, not ROM coded
WDMOD
0
2031H
WDL
7:0
Watchdog autoload value
(see specification)
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
If the ROM code file does not include the options, the following information must be included with the ROM code.
For each of the following, check the appropriate box and send to Philips along with the code:
Security Bit #1:
Security Bit #2:
Encryption:
V Enabled
V Enabled
V No
V Disabled
V Disabled
V Yes
If Yes, must send key file.
Watchdog/Timer Modes:
V Watchdog Mode
V Timer Mode
Prescaler Value:
(Value = 64, 128, 256, 512, 1024, 2048, 4096, 8192)
Value
Autoload Value (range 0–255):
Low Voltage Reset (Value 0 or 1):
Oscillator Fail Reset (Value 0 or 1):
Power-Down (Value 0 or 1):
28
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating temperature under bias
RATING
–55 to +125
–65 to +150
0 to +13.0
–0.5 to +6.5
15
UNIT
°C
°C
V
Storage temperature range
Voltage on EA/V pin to V
PP
SS
Voltage on any other pin to V
V
SS
Maximum I per I/O pin
mA
W
OL
Power dissipation (based on package heat transfer limitations, not device power consumption)
NOTES:
1.5
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
29
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; V = 5V ±10%, V = 0V
CC SS
TEST
CONDITIONS
LIMITS
1
SYMBOL
PARAMETER
Input low voltage (except Port 1, EA)
Input low voltage (EA)
MIN
–0.5
–0.5
–0.5
TYP
MAX
0.2V –0.1
UNIT
V
V
V
V
V
V
IL
CC
0.2V –0.45
V
IL1
IL2
IH
CC
Input low voltage (Port 1)
0.3V
V
CC
Input high voltage (except Port 1, XTAL1, RST)
Input high voltage (XTAL1, RST, Port 1)
Hysteresis voltage (Port 1)
I
I
< 2mA
< 2mA
0.2V +0.9
V
CC
V
CC
+0.5
+0.5
V
IH
CC
0.7V
V
IH1
IH
CC
HYS
200
mV
V
V
V
V
V
V
V
V
Output voltage low (Ports 1, 2, 3)
I
I
= 1.6mA
= 3.2mA
= –1.6mA
= –3.2mA
= –10µA
0.45
0.45
OL
OL
)
Output voltage low (Ports 0, ALE, PSEN
V
OL1
OH
OH1
OH2
IO
OL
Output voltage high (Ports 1, 2, 3 in push-pull mode)
Output voltage high (Port 0, ALE, PSEN)
I
I
V
V
V
–1.0
V
OH
OH
CC
CC
CC
–0.7
–1.0
V
Output voltage high in weak pullup mode (Port 0, 2, 3)
Offset voltage comparator inputs
I
V
OH
–35
+35
mV
V
Common mode range comparator inputs
0
V
CC
CR
I
I
I
I
I
Logical 0 input current (Ports 0, 2, 3) (weak pull-up)
Input pulldown current (Port 0, Port2 in open drain mode)
Input leakage current (EA, P0. 2. 3 High-Z)
Input leakage current comparator/ADC inputs
V
= 0.45V
–250
40
µA
µA
µA
µA
IL
IN
0.45 < V < V
2
IH
IN
CC
CC
0.45 < V < V
–10
–1.0
+10
+1.0
L2
LA
CC
IN
0 < V < V
IN
CC
7
Power supply current:
See note 6
5
Active mode @ 16MHz
20
8
5
30
12
75
mA
mA
µA
Idle mode @ 16MHz
Power-down mode
R
Internal reset pull-up resistor
V
= 0V
50
200
4.25
15
kΩ
V
RST
IN
V
LOW
Low V detect voltage
3.75
CC
9
C
Pin capacitance
f = 1MHz
pF
IO
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is between V and V .
IN
IH
IL
5. I MAX at other frequencies can be determined from Figure 33.
CC
6. See Figures 34 through 37 for I test conditions.
CC
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
10mA
26mA
71mA
OL
Maximum I per 8-bit port:
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
9. 20pF MAX for CERDIP package; 15pF MAX for all other packages.
30
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; V = 5V ±10%, V = 0V
CC SS
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Static Characteristics
R
Resolution
Monotonic with no missing codes
10
Bits
LSB
LSB
LSB
LSB
2, 5, 8
IL
Integral non-linearity error
±2
±1
±3
±2
e
2, 3, 4, 7, 8
DL
FS
Differential non-linearity error
e
e
2, 8
Full Scale error
2, 6, 8
OS
Offset error
e
Dynamic Characteristics
t
t
Conversion time (including sampling time)
Sampling tme
48t
µs
µs
ADC
ADS
CY
8t
CY
Analog Input Characteristics
AV
Analog input voltage
AV – 0.2 AV + 0.2
V
pF
IN
SS
DD
C
Analog input capacitance
Channel-to-channel matching
15
IA
7
M
CTC
±1
LSB
dB
7
C
Crosstalk between inputs of port 1
0–100kHz
–60
t
Power Requirements
AV /V
Analog supply and reference voltage
AV = V ± 0.2
4.0
6.0
1.2
V
CC REF+
CC
CC
AI
CC
Analog supply current: operating: (16MHz)
AV = 6.0V
mA
CC
NOTES:
1. The following condition must not be exceeded: V – 0.2V < AV < V + 0.2V.
DD
DD
DD
2. Conditions: AV = 0V; AV = 4.997V; V = 5.0V.
SS
CC
CC
3. The differential non-linearity (DL ) is the difference between the actual step width and the ideal step width. (See Figure 24).
e
4. The ADC is monotonic; there are no missing codes.
5. The integral non-linearity (IL ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
e
appropriate adjustment of gain and offset error. (See Figure 24).
6. The offset error (OS ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
e
a straight line which fits the ideal transfer curve. (See Figure 24).
7. Guaranteed by design.
8. To meet Error Specification, analog input voltage must be less than 1V/ms.
(AVCCń1023) 1000
Slew RateMAX
+
(Vńms)
4 (12ńOsc Freq (MHz))
For 16MHz @ 5.0V slew rate = 1.6V/ms.
31
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
Offset
error
Gain
error
OS
e
G
e
1023
1022
1021
1020
1019
Full Scale
error
FS
e
1018
(2)
7
(1)
Code
Out
6
5
(5)
4
(4)
3
(3)
2
1
1 LSB
(ideal)
0
1
2
3
4
5
6
7
1018
1019
1020
1021
1022
)
1023
1024
AV (LSB
IN
ideal
Offset
error
OS
e
AV
– AV
REF–
REF+
1024
1 LSB =
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DL ).
e
(4) Integral non-linearity (IL ).
e
(5) Center of a step of the actual transfer curve.
SU00710
Figure 24. ADC Conversion Characteristic
32
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
AC ELECTRICAL CHARACTERISTICS
amb
1, 2
T
= 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; V = 5V ±10%, V = 0V
CC SS
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
MIN
MAX
UNIT
25
Oscillator frequency: Speed Version
CLCL
8XC576
E
6
16
5.5
10
MHz
MHz
µs
OSCF
TR
Oscillator fail detect frequency
Comparator response time
ALE pulse width
0.6
t
t
t
t
t
t
t
t
t
t
t
25
25
25
25
25
25
25
25
25
25
25
2t
–40
ns
LHLL
AVLL
LLAX
LLIV
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–40
–30
ns
CLCL
CLCL
ns
4t
3t
–100
ns
CLCL
t
–30
ns
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
3t
–45
ns
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
ns
CLCL
0
ns
t
–25
ns
CLCL
5t
–105
ns
CLCL
10
ns
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
RD pulse width
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
5t
–165
CLCL
0
Data float after RD
2t
–60
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
8t
CLCL
9t
CLCL
–150
–165
AVDV
LLWL
AVWL
QVWX
WHQX
RLAZ
WHLH
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–50
CLCL
CLCL
CLCL
t
–50
RD low to address float
RD or WR high to ALE high
0
t
–40
t
+40
CLCL
CLCL
External Clock
t
t
t
t
29
29
29
29
High time
Low time
Rise time
Fall time
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
Shift Register
t
t
t
t
t
28
28
28
28
28
Serial port clock cycle time
12t
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t –133
CLCL
QVXH
XHQX
XHDX
XHDV
2t
CLCL
–60
0
10t
–133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 83C576/87C576 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port
0 drivers.
33
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
UPI AC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; V = 5V ±10%, V = 0V
CC SS
SYMBOL
PARAMETER
MIN
0
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
CS, A setup to RD
CS, A hold after RD
RD pulse width
AR
RA
RR
AD
RD
DF
35
35
ns
ns
CS, A to data out delay
RD to data out delay
45
35
30
ns
ns
RD to data float delay (guaranteed by design)
CS, A setup to WR
ns
0
ns
AW
WA
WW
DW
WD
CS, A hold after WR
15
45
5
ns
WR pulse width
ns
Data setup to WR
ns
Data hold after WR
25
ns
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal.
The designations are:
P – PSEN
Q – Output data
R – RD signal
t – Time
A – Address
V – Valid
C – Clock
W– WR signal
D – Input data
H – Logic level high
X – No longer a valid logic level
Z – Float
I – Instruction (program memory contents)
L – Logic level low, or ALE
Examples: t
= Time for address valid to ALE low.
=Time for ALE low to PSEN low.
AVLL
t
LLPL
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 25. External Program Memory Read Cycle
34
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
ALE
t
WHLH
PSEN
t
LLDV
t
t
LLWL
RLRH
RD
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 26. External Data Memory Read Cycle
ALE
PSEN
WR
t
WHLH
t
t
WLWH
LLWL
t
LLAX
t
t
WHQX
t
AVLL
QVWX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00069
Figure 27. External Data Memory Write Cycle
35
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 28. Shift Register Mode Timing
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 29. External Clock Drive
V
–0.5
CC
0.2V
0.2V
+0.9
–0.1
CC
CC
0.45V
NOTE:
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
CC
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
IH
IL
SU00010
Figure 30. AC Testing Input/Output
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
V
LOAD
–0.1V
LOAD
+0.1V
OL
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V /V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00011
Figure 31. Float Waveform
36
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
AO, CS
t
t
t
t
t
t
AR
AW
RR
WW
RA
WA
RD
WR
t
t
DF
WD
t
t
DW
RD
t
AD
D0–D7
SU00518
Figure 32. UPI Read/Write Cycles
30
MAX ACTIVE
25
20
TYP ACTIVE
15
I
(mA)
CC
MAX IDLE
TYP IDLE
10
5
0
0
4
5
10
15 16
20
FREQUENCY (MHz)
SU00245
Figure 33.
I
vs. FREQ
CC
Valid only within frequency specifications of the device under test
V
CC
I
CC
V
CC
V
CC
AV
SS
RST
EA
(NC)
XTAL2
XTAL1
AV
CC
CLOCK SIGNAL
V
SS
SU00661
Figure 34.
I
Test Condition, Active Mode
CC
All other pins are disconnected
37
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
V
CC
I
CC
V
CC
V
CC
RST
AV
AV
AV
CC
CC
SS
EA
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
V
SS
SU00662
Figure 35.
I
Test Condition, Idle Mode
CC
All other pins are disconnected
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 36. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
I
CC
V
CC
V
CC
RST
AV
AV
CC
SS
EA
(NC)
XTAL2
XTAL1
V
SS
SU00663A
Figure 37.
I
Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2V to 5.5V
CC
38
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
EPROM CHARACTERISTICS
Quick-Pulse Programming (Parallel)
To put the 87C576 in the parallel EPROM programming mode,
PSEN must be held high during power up, then driven low with reset
active. The 87C576 is programmed by using a modified Quick-Pulse
Programming algorithm.
The setup for microcontroller quick-pulse programming is shown in
Figure 38. Note that the 87C576 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The 87C576 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C576 manufactured by
Philips.
The address of the EPROM location to be programmed is applied to
ports 3 and 2, as shown in Figure 38. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 1 specified in Table 3 are held at the ‘Program
Code Data’ levels indicated in Table 3. The ALE/PROG is pulsed
low 25 times as shown in Figure 39.
Table 3 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 38 and 39. Figure 40 shows the
circuit configuration for normal program memory verification.
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
On-Board Programming (OBP)
To program the security bits, repeat the 25 pulse programming
sequence using the ‘Pgm Security Bit’ levels. After one security bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other security bit can still
be programmed.
The On-Board Programming facility consists of a series of internal
hardware resources coupled with internal firmware to facilitate
remote programming of the 87C576 through the serial port.
The OBP function is invoked by having the EA/V pin at the V
PP
PP
voltage level at the time that the part exits reset. The OBP function
only requires that the TxD, RxD, V , V , and V pins be
connected to an external circuit in order to use this feature.
Note that the EA/V pin must not be allowed to go above the
PP
SS
CC
PP
maximum specified V level for any amount of time. Even a narrow
PP
glitch above that voltage can cause permanent damage to the
The OBP feature provides for the use of a wide range of baud rates
independent of the oscillator frequency used. It is also adaptable to
a wide range of oscillator frequencies. The OBP facility provides for
both auto-echo and no-echo of received characters. The OBP
feature requires that an initial character, an uppercase U, be sent to
the 87C576 to establish the baud rate to be used.
device. The V source should be well regulated and free of glitches
and overshoot.
PP
Program Verification
If security bit 2 has not been programmed, the on-chip program
memory can be read out for program verification. The address of the
program memory locations to be read is applied to ports 3 and 2 as
shown in Figure 40. The other pins are held at the ‘Verify Code Data’
levels indicated in Table 3. The contents of the address location will
be emitted on port 0. External pull-ups are required on port 0 for this
operation.
Once baud rate initialization has been performed, the OBP facility
only accepts Intel Hex records. The record-type field of these hex
records are used to indicate either commands or data for the OBP
facility. The maximum number of data bytes in a record is limited to
16 (decimal). These commands/data are summarized below:
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
Record Command/Data
Type
Function
00
Data record, programs the part with data indicated in
record starting with load address in the record
01
02
EOF record, no operation
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P1.0 and P1.1
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(B6H) = B6H indicates 87C576
Specify timing parameters
– rec length = 3 bytes
– load address = 0000
– 1st byte = timer count for 50µs programming pulse
– 2nd byte = timer count for 10µs delay between pulses
– 3rd byte = 0AH
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 3, and
which satisfies the timing specifications, is suitable.
03
Program security bits
– rec length = 1 byte
– load address = 0000
– 1st byte = sec bit values (xxxx xxB2B1)
04
05
Display contents of USER EPROM array
– rec length = 00
– load address = 0000
Verify security bit status
– rec length = 00
– load address = 0000
Trademark phrase of Intel Corporation.
1998 Jun 04
39
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
Table 3.
EPROM Programming Modes
MODE
RST
PSEN
ALE/PROG
EA/V
P2.7
P2.6
P1.1
P1.0
PP
Read signature
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Program code data
Verify code data
0*
1
V
PP
1
Pgm encryption table
Pgm security bit 1
0*
0*
0*
V
PP
PP
PP
V
V
Pgm security bit 2
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. V = 12.75V ±0.25V.
PP
3. V = 5V±10% during programming and verification.
CC
*
ALE/PROG receives 5 programming pulses while V is held at 12.75V. Each programming pulse is low for 50µs (±10µs) and high for a
PP
minimum of 10µs.
40
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
+5V
+5V
AV
CC
V
CC
P0
A0–A7
PGM DATA
+12.75V
P3
0
1
1
RST
P1.0
EA/V
PP
5 50µs PULSES TO GROUND
ALE/PROG
PSEN
0
1
87C576
P1.1
XTAL2
P2.7
0
P2.6
4–6MHz
XTAL1
A8–A12
P2.0–P2.4
AV
SS
V
SS
SU00257B
Figure 38. Programming Configuration
5 PULSES
1
0
ALE/PROG:
ALE/PROG:
10µs MIN
50µs+10
1
0
SU00664
Figure 39. PROG Waveform
+5V
+5V
AV
CC
V
CC
P0
A0–A7
PGM DATA
P3
0
1
1
RST
P1.0
1
1
0
EA/V
PP
ALE/PROG
PSEN
P1.1
87C576
0
0
ENABLE
XTAL2
P2.7
P2.6
4–6MHz
XTAL1
A8–A12
P2.0–P2.4
AV
SS
V
SS
SU00258B
Figure 40. Program Verification
41
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
T
amb
= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 41)
CC SS
SYMBOL
PARAMETER
MIN
MAX
13.0
50
UNIT
V
V
PP
Programming supply voltage
Programming supply current
Oscillator frequency
12.5
I
PP
mA
MHz
1/t
CLCL
4
12
t
t
t
t
t
t
t
t
t
t
t
t
Address setup to PROG low
Address hold after PROG
Data setup to PROG low
Data hold after PROG
48t
AVGL
CLCL
CLCL
CLCL
CLCL
CLCL
48t
48t
48t
48t
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
AVQV
ELQZ
EHQZ
GHGL
P2.7 (ENABLE) high to V
PP
V
PP
V
PP
setup to PROG low
hold after PROG
10
10
40
µs
µs
µs
PROG width
60
Address to data valid
48t
CLCL
CLCL
CLCL
ENABLE low to data valid
Data float after ENABLE
PROG high to PROG low
48t
48t
0
10
µs
PROGRAMMING*
VERIFICATION*
ADDRESS
P3.0–P3.7
P2.0–P2.4
ADDRESS
t
AVQV
PORT 0
DATA IN
DATA OUT
t
t
GHDX
DVGL
t
t
GHAX
AVGL
ALE/PROG
t
t
GHGL
GLGH
t
GHSL
t
SHGL
LOGIC 1
LOGIC 1
EA/V
PP
LOGIC 0
t
EHSH
t
t
ELQV
EHQZ
P2.7
ENABLE
SU00207
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 38.
FOR VERIFICATION CONDITIONS SEE FIGURE 40.
Figure 41. EPROM Programming and Verification
42
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
43
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
44
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
45
1998 Jun 04
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
83C576/87C576
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 06-98
Document order number:
9397 750 04024
Philips
Semiconductors
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