P87C557E8 [NXP]
8 BIT MICROCONTROLLER; 8位微控制器
| 型号： | P87C557E8 |
| 厂家： | 
NXP |
| 描述： | 8 BIT MICROCONTROLLER |
| 文件： | 总84页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P8xC557E8
8-bit microcontroller
1999 Mar 12
Product specification
File under Integrated Circuits, IC20
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
CONTENTS
15
POWER REDUCTION MODES
15.1
15.2
15.3
15.4
15.5
Idle mode
Power-down mode
Wake-up from Power-down mode
Status of external pins
Power Control Register (PCON)
1
2
FEATURES
GENERAL DESCRIPTION
2.1
2.2
Electromagnetic Compatibility (EMC)
Recommendation on ALE
16
OSCILLATOR CIRCUITS
3
4
5
6
ORDERING INFORMATION
BLOCK DIAGRAM
16.1
16.2
XTAL1; XTAL2 oscillator: standard 80C51
XTAL3; XTAL4 oscillator: 32 kHz PLL oscillator
(with Seconds timer)
FUNCTIONAL DIAGRAM
PINNING INFORMATION
17
RESET CIRCUITRY
Power-on Reset
6.1
6.2
Pinning diagram
Pin description
17.1
18
INSTRUCTION SET
7
8
FUNCTIONAL DESCRIPTION
MEMORY ORGANIZATION
18.1
18.2
18.3
Addressing modes
80C51 family instruction set
Instruction set description
8.1
8.2
8.3
Program Memory
Internal Data Memory
Addressing
19
20
21
22
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
EPROM CHARACTERISTICS
9
I/O FACILITIES
10
PULSE WIDTH MODULATED OUTPUTS
(PWM)
22.1
22.2
Programming and verification
Security
10.1
10.2
10.3
Prescaler Frequency Control Register (PWMP)
Pulse Width Register 0 (PWM0)
Pulse Width Register 1 (PWM1)
23
SPECIAL FUNCTION REGISTERS
OVERVIEW
11
ANALOG-TO-DIGITAL CONVERTER (ADC)
24
25
PACKAGE OUTLINES
SOLDERING
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
ADC features
ADC functional description
ADC timing
ADC configuration and operation
ADC during Idle and Power-down mode
ADC resolution and characteristics
ADC after reset
25.1
25.2
25.3
25.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
26
27
28
DEFINITIONS
ADC Special Function Registers
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
12
TIMERS/COUNTERS
12.1
12.2
12.3
Timer 0 and Timer 1
Timer T2
Watchdog Timer T3
13
SERIAL I/O PORTS
13.1
13.2
Serial I/O Port: SIO0 (UART)
Serial I/O Port: SIO1 (I2C-bus interface)
14
INTERRUPT SYSTEM
14.1
14.2
14.3
14.4
14.5
Interrupt Enable Registers
Interrupt Handling
Interrupt Priority Structure
Interrupt vectors
Interrupt Enable and Priority Registers
1999 Mar 12
2
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
The P8xC557E8 contains a volatile 2048 bytes read/write
Data Memory, five 8-bit I/O ports, one 8-bit input port, two
16-bit timer/event counters (identical to the timers of the
80C51), an additional 16-bit timer coupled to capture and
compare latches, a 15-source, two-priority-level,
nested interrupt structure, an 8-input ADC, a dual
Digital-to-Analog Convertor (DAC), Pulse Width
Modulated interface, two serial interfaces (UART and
I2C-bus), a Watchdog Timer, an on-chip oscillator and
timing circuits.
1
FEATURES
• 80C51 Central Processing Unit (CPU)
• 64 kbytes ROM (only P83C557E8)
• 64 kbytes EPROM (only P87C557E8)
• ROM/EPROM Code protection
• 2048 bytes RAM, expandable externally to 64 kbytes
• Two standard 16-bit timers/counters
• An additional 16-bit timer/counter coupled to four
capture registers and three compare registers
The P8xC557E8 is available in 3 versions:
• A 10-bit Analog-to-Digital Converter (ADC) with eight
• P80C557E8: ROMless version
multiplexed analog inputs and programmable autoscan
• P83C557E8: containing a non-volatile 64 kbytes mask
• Two 8-bit resolution, Pulse Width Modulation outputs
programmable ROM
• Five 8-bit I/O ports plus one 8-bit input port shared with
• P87C557E8: containing 64 kbytes programmable
analog inputs
EPROM/OTP.
• I2C-bus serial I/O port with byte oriented master and
slave functions
The P8xC557E8 is a control-oriented CPU with on-chip
Program and Data Memory; it cannot be extended with
external Program Memory. It can access up to 64 kbytes
of external Data Memory. For systems requiring extra
capability, the P8xC557E8 can be expanded using
standard TTL compatible memories and peripherals.
• Full-duplex UART compatible with the standard 80C51
• On-chip Watchdog Timer
• 15 interrupt sources with 2 priority levels (2 to 6 external
sources possible)
In addition, the P8xC557E8 has two software selectable
reduced power modes: Idle mode and Power-down mode.
The Idle mode freezes the CPU while allowing the RAM,
timers, serial ports, and interrupt system to continue
functioning. The Power-down mode saves the RAM
contents but freezes the oscillator, causing all other chip
functions to be inoperative.The Power-down mode can be
terminated by an external reset, by the seconds interrupt
and by any one of the two external interrupts;
• Phase-Locked Loop (PLL) oscillator with 32 kHz
reference and software-selectable system clock
frequency
• Seconds timer
• Software enable/disable of ALE output pulse
• Electromagnetic compatibility improvements
• Wake-up from Power-down by external or seconds
interrupt
see Section 15.3.
• Frequency range for 80C51-family standard oscillator:
3.5 to 16 MHz
The device also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic as well
as bit-handling capabilities. The instruction set of the
P8xC557E8 is the same as the 80C51 and consists of over
100 instructions: 49 one-byte, 45 two-byte, and
• Extended temperature range: −40 to +85 C
• Supply voltage: 4.5 to 5.5 V.
17 three-byte. With a 16 MHz system clock, 58% of the
instructions are executed in 0.75 µs and 40% in 1.5 µs.
Multiply and divide instructions require 3 µs.
2
GENERAL DESCRIPTION
The 8-bit microcontrollers P80C557E8, P83C557E8 and
P87C557E8 - hereafter referred to as P8xC557E8 - are
manufactured in an advanced CMOS process and are
derivatives of the 80C51 microcontroller family.
1999 Mar 12
3
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
2.1
Electromagnetic Compatibility (EMC)
2.2
Recommendation on ALE
Primary attention is paid to the reduction of
electromagnetic emission of the microcontroller
P8xC557E8. The following features reduce the
electromagnetic emission and additionally improve the
electromagnetic susceptibility:
For applications that require no external memory or
temporarily no external memory: the ALE output signal
(pulses at a frequency of 1⁄6 × fOSC) can be disabled under
software control (bit RFI; SFR: PCON.5); if disabled, no
ALE pulse will occur. ALE pin will be pulled down
internally, switching an external address latch to a quiet
state. The MOVX instruction will still toggle ALE (external
Data Memory is accessed). ALE will retain its normal HIGH
value during Idle mode and a LOW value during
• Four digital part supply voltage pins (VDD1 to VDD4) and
four digital ground pins (VSS1 to VSS4) are placed as
pairs of VDDn and VSSn at two adjacent pins, at each side
of the package.
Power-down mode while in the ‘RFI reduction mode’.
• Separated VDD pins for the internal logic and the port
Additionally during internal access (EA = 1) ALE will toggle
normally when the address exceeds the internal Program
Memory size. During external access (EA = 0) ALE will
always toggle normally, whether the flag ‘RFI’ is set or not.
buffers.
• Internal decoupling capacitance improves the EMC
radiation behaviour and the EMC immunity.
• External capacitors should be connected across
associated VDDn and VSSn pins (i.e. VDD1 and VSS1).
Lead length should be as short as possible. Ceramic
chip capacitors are recommended (100 nF).
3
ORDERING INFORMATION
PACKAGE
FREQUENCY TEMPERATURE
TYPE NUMBER
NAME
RANGE (MHZ)
RANGE (°C)
DESCRIPTION
VERSION
P80C557E8EFB(1)
P83C557E8EFB/nnn(2) QFP80
P87C557E8EFB(3)
plastic quad flat package;
80 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
SOT318-2
3.5 to 16
−40 to +85
Notes
1. ROMless type.
2. ROM coded type; ‘nnn’ denotes the ROM code number.
3. EPROM/OTP type.
1999 Mar 12
4
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
4
BLOCK DIAGRAM
HM0I23
a n d b o o k , f u l l p a g e w
1999 Mar 12
5
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
5
FUNCTIONAL DIAGRAM
SELXTAL1
XTAL4
alternative function
XTAL3
XTAL1
XTAL2
0
1
2
AD0
AD1
AD2
(1)
LOW ORDER
ADDRESS
AND
EA/V
PP
3
AD3
AD4
AD5
AD6
AD7
PORT 0
4
PSEN
(1)
DATA BUS
ALE/PROG
5
6
7
PWM0
PWM1
SCL
0
1
2
CT0I/INT2
CT1I/INT3
CT2I/INT4
CT3I/INT5
T2
SDA
ADEXS
3
PORT 1
4
V
V
ref(p)(A)
ref(n)(A)
STADC
5
6
7
RT2
alternative function
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
0
1
2
3
0
1
2
A8
A9
P8xC557E8
A10
HIGH ORDER
ADDRESS
BUS
3
A11
A12
A13
A14
A15
PORT 5
PORT 2
4
4
5
6
7
5
6
7
RXD/DATA
CMSR0
CMSR1
CMSR2
CMSR3
CMSR4
CMSR5
CMT0
0
1
2
3
4
5
6
7
0
1
2
TXD/CLOCK
INT0
3
INT1
T0
PORT 4
PORT 3
4
5
6
7
T1
WR
RD
CMT1
V
SSA
RSTIN
V
DDA
RSTOUT
(2)
V
SS
EW
V
DD
MHI024
(1) Only the P87C557E8 with an alternative function.
(2) VDDA/VSSA - 2 analog supply pairs;
VDD/VSS - 4 digital supply pairs.
Fig.2 Functional diagram.
6
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
6
PINNING INFORMATION
Pinning diagram
6.1
(1)
V
1
2
3
4
5
6
7
8
9
64 ALE/PROG
63
62 P2.7/A15
61
ref(n)(A)
ref(p)(A)
V
PSEN
V
SSA1
V
P2.6/A14
60 P2.5/A13
59
DDA1
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P2.4/A12
58 P2.3/A11
57 P2.2/A10
56 P2.1/A9
55 P2.0/A8
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2 10
P5.1/ADC1 11
P5.0/ADC0 12
V
V
54
53
52
51
50
SS3
DD3
P8xC557E8
V
13
14
XTAL1
XTAL2
n.c.
SS1
DD1
V
ADEXS 15
PWM0 16
PWM1 17
49 n.c.
48 P3.7/RD
47 P3.6/WR
18
19
EW
P3.5/T1
P3.4/T0
46
45
P4.0/CMSR0
P4.1/CMSR1 20
21
P4.3/CMSR3 22
RSTOUT
44 P3.3/INT1
43 P3.2/INT0
P4.2/CMSR2
P3.1/TXD
23
42
P4.4/CMSR4 24
41 P3.0/RXD
MHI025
(1) Only the P87C557E8 with this alternative function.
Fig.3 Pin configuration QFP80/SOT318 version.
7
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
6.2
Table 1 Pin description for QFP80 (SOT318-2)
To avoid a ‘latch-up’ effect at power-on: VSS − 0.5 V < ‘voltage at any pin at any time’ < VDD + 0.5 V.
SYMBOL PIN DESCRIPTION
Vref(n)(A) Low-end of ADC reference resistor.
Vref(p)(A)
VSSA1
Pin description
1
2
3
4
High-end of ADC reference resistor.
Ground, analog part. For ADC receiver and reference voltage.
Power supply, analog part (+5 V). For ADC receiver and reference voltage.
VDDA1
P5.7/ADC7 to
P5.0/ADC0
5 to 12
Port 5 (P5.7 to P5.0): 8-bit input port lines;
ADC7 to ADC0: 8 input channels to the ADC.
VSS1 to VSS4
VDD1 to VDD4
ADEXS
13, 29,
54, 67
Ground; digital part; circuit ground potential. VSS1, VSS2, VSS4 must be connected,
VSS3 is internally connected to digital ground, but should be connected externally.
14, 28,
53, 66
Power supply, digital part (+5 V). Power supply pins during normal operation and
power reduction modes. All pins must be connected.
15
Start ADC operation. Input starting ADC, triggered by a programmable edge; ADC
operation can also be started by software. This pin must not float.
PWM0
PWM1
EW
16
17
18
Pulse Width Modulation output 0.
Pulse Width Modulation output 1.
Enable Watchdog Timer (WDT): enable for T3 Watchdog Timer and disable
Power-down mode. This pin must not float.
P4.0/CMSR0 to
P4.5/CMSR5
19 to 22, Port 4 (P4.0 to P4.7): 8-bit quasi-bidirectional I/O port lines;
24, 25
CMSR0 to CMSR5: compare and set/reset outputs for Timer T2;
CMT0 to CMT1: compare and toggle outputs for Timer T2.
P4.6/CMT0 to
P4.7/CMT1
26, 27
RSTOUT
23
30
Reset output of the P8xC557E8 for resetting peripheral devices during initialization
and Watchdog Timer overflow.
RSTIN
Reset input to reset the P8xC557E8.
P1.0/CT0I/INT2 to 31 to 34 Port 1 (P1.0 to P1.7): 8-bit quasi-bidirectional I/O port lines;
P1.3/CT3I/INT5
CT0I to CT3I: Capture timer inputs for Timer T2;
INT2 to INT5: external interrupts 2 to 5;
T2: T2 event input (rising edge triggered);
RT2: T2 timer reset input (rising edge triggered).
P1.4/T2 to
P1.5/RT2
35, 36
P1.6 to P1.7
SCL
37 to 38
39
I2C-bus serial clock I/O port. If SCL is not used, it must be connected to VSS
.
SDA
40
I2C-bus serial data I/O port. If SDA is not used, it must be connected to VSS
.
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
n.c.
41
Port 3 (P3.0 to P3.7): 8-bit quasi-bidirectional I/O port lines;
RXD: Serial input port;
TXD: Serial output port;
INT0: External interrupt input 0;
INT1: External interrupt input 1;
T0: Timer 0 external interrupt input;
T1: Timer 1external interrupt input;
WR: External Data Memory Write strobe;
RD: External Data Memory Read strobe.
42
43
44
45
46
47
48
49, 50
Not connected pins.
1999 Mar 12
8
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
SYMBOL
XTAL2
PIN
DESCRIPTION
51
52
Crystal pin 2: output of the inverting amplifier that forms the oscillator.
Left open-circuit when an external oscillator clock is used.
XTAL1
Crystal pin 1: input to the inverting amplifier that forms the oscillator, and input to the
internal clock generator. Receives the external oscillator clock signal when an external
oscillator is used. Must be connected to logic HIGH if the PLL oscillator is selected
(SELXTAL1 = LOW).
P2.0/A08 to
P2.7/A15
55 to 62 Port 2 (P2.0 to P2.7): 8-bit quasi-bidirectional I/O port lines;
A08 to A15: High-order address byte for external memory.
PSEN
63
64
65
Program Store Enable output: read strobe to the external Program Memory via
Ports 0 and 2. Is activated twice each machine cycle during fetches from external
Program Memory. When executing out of external Program Memory two activations of
PSEN are skipped during each access to external Data Memory. PSEN is not
activated (remains HIGH) during no fetches from external Program Memory. PSEN
can sink/source 8 LSTTL inputs. It can drive CMOS inputs without external pull-ups.
ALE/PROG
Address Latch Enable output. Latches the low byte of the address during access of
external memory in normal operation. It is activated every six oscillator periods except
during an external Data Memory access. ALE can sink/source 8 LSTTL inputs. It can
drive CMOS inputs without an external pull-up. To prohibit the toggling of ALE pin (RFI
noise reduction) the bit RFI (SFR: PCON.5) must be set by software; see Section 2.2.
PROG: the programming pulse input; alternative function for the P87C557E8.
EA/VPP
External Access input. If, during reset, EA is held at a TTL level HIGH the CPU
executes out of the internal Program Memory. If, during reset, EA is held at a TTL level
LOW the CPU executes out of external Program Memory via Port 0 and Port 2. EA is
not allowed to float. EA is latched during reset and don’t care after reset.
VPP: the programming supply voltage; alternative function for the P87C557E8.
P0.7/AD7 to
P0.0/AD0
68 to 75 Port 0 (P0.7 to P0.0): 8-bit open-drain bidirectional I/O port lines;
AD7 to AD0: Multiplexed Low-order address and Data bus for external memory.
VDDA2
VSSA2
XTAL3
XTAL4
76
77
78
79
Power supply, analog part (+5 V). For PLL oscillator.
Ground, analog part. For PLL oscillator.
Crystal pin 3: output of the inverting amplifier that forms the 32 kHz oscillator.
Crystal pin 2: input to the inverting amplifier that forms the 32 kHz oscillator. XTAL3 is
pulled LOW if the PLL oscillator is not selected (SELXTAL1 = 1) or if reset is active.
SELXTAL1
80
SELXTAL1 = HIGH, selects the HF oscillator, using the XTAL1/XTAL2 crystal.
If SELXTAL1 = LOW the PLL is selected for clocking of the controller, using the
XTAL3/XTAL4 crystal.
1999 Mar 12
9
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
7
FUNCTIONAL DESCRIPTION
The P8xC557E8 is a stand-alone high-performance
microcontroller designed for use in real time applications
such as instrumentation, industrial control, medium to
high-end consumer applications and specific automotive
control applications.
In addition to the 80C51 standard functions, the device
provides a number of dedicated hardware functions for
these applications.
The P8xC557E8 is a control-oriented CPU with on-chip
program and Data Memory, but it cannot be extended with
external Program Memory. It can access up to 64 kbytes
of external Data Memory. For systems requiring extra
capability, the P8xC557E8 can be expanded using
standard memories and peripherals.
The functional description of the device is described in:
Chapter 8 “Memory organization”
Chapter 9 “I/O facilities”
Chapter 10 “Pulse Width Modulated outputs”
Chapter 11 “Analog-to-Digital Converter (ADC)”
Chapter 12 “Timers/counters”
Chapter 13 “Serial I/O ports”
Chapter 14 “Interrupt system”
Chapter 15 “Reduced power modes”
Chapter 16 “Oscillator circuits”
Chapter 17 “Reset circuitry”.
1999 Mar 12
10
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
8
MEMORY ORGANIZATION
8.2
Internal Data Memory
The Central Processing Unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbytes external
Data Memory, 2048 bytes internal Data Memory
(consisting of 256 bytes standard RAM and 1792 bytes
AUX-RAM) and the 64 kbytes internal or 64 kbytes
external Program Memory (see Fig.4).
The internal Data Memory is divided into three physically
separated parts: 256 bytes of RAM, 1792 bytes of
AUX-RAM, and a 128 bytes Special Function Registers
(SFRs) area. These parts can be addressed each in a
different way as described in Sections 8.2.1 to 8.2.2 and
Table 3.
8.1
Program Memory
Table 3 Internal Data Memory map
The Program Memory of the P8xC557E8 consists of
64 kbytes ROM or 64 kbytes EPROM. If, during reset, the
EA pin was held HIGH, the P8xC557E8 always executes
out of the internal Program Memory. If the EA pin was held
LOW during reset the P8xC557E8 fetches all instructions
from the external Program Memory. The EA input is
latched during reset and is don’t care after reset.
MEMORY
LOCATION
ADDRESS MODE
RAM
0 to 127
128 to 255
128 to 255
0 to 1791
Direct and indirect
Indirect only
SFR
Direct only
AUX-RAM
Indirect only with MOVX
8.2.1
RAM
The internal Program Memory content is protected by
setting a mask programmable security bit (ROM) or by the
software programmable security bits (EPROM)
• RAM 0 to 127 can be addressed directly and indirectly
as in the 80C51. Address pointers are R0 and R1 of the
selected register bank.
respectively, i.e. it cannot be read out at any time by any
test mode or by any instruction in the external Program
Memory space. The MOVC instructions are the only ones
which have access to program code in the internal or
external Program Memory. The EA input is latched during
reset and is don’t care after reset. This implementation
prevents from reading internal program code by switching
from external Program Memory to internal Program
Memory during MOVC instruction or an instruction that
handles immediate data. Table 2 lists the access to the
internal and external Program Memory with MOVC
instructions whether the security feature has been
activated or not.
• RAM 128 to 255 can only be addressed indirectly.
Address pointers are R0 and R1 of the selected register
bank.
Four register banks, each 8 registers wide, occupy
locations 0 through 31 in the lower RAM area. Only one of
these banks may be enabled at a time. The next 16 bytes,
locations 32 through 47, contain 128 directly addressable
bit locations. The stack can be located anywhere in the
internal 256 bytes RAM. The stack depth is only limited by
the available internal RAM space of 256 bytes (see Fig.6).
All registers except the Program Counter and the four
register banks reside in the Special Function Register
address space.
Due to the maximum size of the internal Program Memory,
the MOVC instructions can always operate either in the
internal or in the external Program Memory.
8.2.2
SPECIAL FUNCTION REGISTERS
Table 2 Memory access by the MOVC instruction
The Special Function Registers can only be addressed
directly in the address range from 128 to 255 (see Fig.7).
For code protection of the P87C557E8 see Section 23.2.
PROGRAM MEMORY ACCESS
MOVC
8.2.3
AUX-RAM
INSTRUCTION
INTERNAL
EXTERNAL
• AUX-RAM 0 to 1791 is indirectly addressable via page
register (XRAMP) and MOVX-Ri instructions, unless it is
disabled by setting ARD = 1 (see Fig.5). When
executing from internal Program Memory, an access to
AUX-RAM 0 to 1791 will not affect the ports P0, P2,
P3.6 and P3.7.
MOVC in internal
Program Memory
YES
NO(1)
MOVC in external
Program Memory
NO(1)
YES
Note
• AUX-RAM 0 to 1791 is also indirectly addressable as
external Data Memory locations 0 to 1791 via MOVX-Ri
instructions, unless it is disabled by setting ARD = 1.
1. Not applicable due to 64 kbytes internal Program
Memory.
1999 Mar 12
11
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
An access to external Data Memory locations higher than
1791 will be performed with the MOVX @DPTR
instructions in the same way as in the 80C51 structure, so
with P0 and P2 as data/address bus and P3.6 and P3.7 as
write and read timing signals.
8.2.4
AUX-RAM PAGE REGISTER (XRAMP)
The AUX-RAM Page Register is used to select one of
seven 256-bytes pages of the internal 1792 bytes
AUX-RAM for MOVX-accesses via R0 or R1. Its reset
value is ‘XXXXX000B’.
Note that the external Data Memory cannot be accessed
with R0 and R1 as address pointer if the AUX-RAM is
enabled (ARD = 0, default).
Table 4 AUX-RAM Page Register (address FAH)
7
6
5
4
3
2
1
0
XRAMPx
XRAMPx
XRAMPx
XRAMPx
XRAMPx
XRAMP2
XRAMP1
XRAMP0
Table 5 Description of XRAMP bits
BIT
SYMBOL
FUNCTION
7 to 3
XRAMPx
Reserved for future use. During read XRAMPx = undefined; a write
operation must write logic 0s to these locations.
2 to 0
XRAMP2 to XRAMP0
AUX-RAM page select bits 2 to 0; see Table 6.
Table 6 Memory locations for all possible MOVX-accesses
X = don’t care.
ARD(1) XRAMP2 XRAMP1 XRAMP0
MEMORY LOCATIONS
MOVX @Ri,A and MOVX A,@Ri instructions access
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
AUX-RAM locations 0 to 255 (reset condition)
AUX-RAM locations 256 to 511
AUX-RAM locations 512 to 767
AUX-RAM locations 768 to 1023
AUX-RAM locations 1024 to 1279
AUX-RAM locations 1280 to 1535
AUX-RAM locations 1536 to 1791
No valid memory access; reserved for future use
External RAM locations 0 to 255
MOVX @DPTR,A and MOVX A,@DPTR instructions access
0
X
X
X
AUX-RAM locations 0 to 1791 (reset condition);
External RAM locations 1792 to 65535
1
X
X
X
External RAM locations 0 to 65535
Note
1. ARD: AUX-RAM disable, is a bit in SFR PCON (bit PCON.6); see Section 15.5.
1999 Mar 12
12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
64 kbytes
64 kbytes
64 kbytes
1791
OVERLAPPED SPACE
255
127
0
SPECIAL
FUNCTION
REGISTERS
AUXILIARY
RAM
INTERNAL
(EA = 1)
EXTERNAL
(ARD = 1)
INDIRECT ONLY
(EA = 0)
(ARD = 0)
1792 bytes
DIRECT AND
INDIRECT
0
0
MAIN RAM
PROGRAM MEMORY
INTERNAL DATA
MEMORY
EXTERNAL DATA
MEMORY
MBH077
Fig.4 Memory map and address space.
255
1791
(XRAMP) = 06 H
(XRAMP) = 05 H
(XRAMP) = 04 H
(XRAMP) = 03 H
(XRAMP) = 02 H
(XRAMP) = 01 H
(XRAMP) = 00 H
0
255
1536
1535
0
255
1280
1279
0
255
1024
1023
MOVX @Ri, A
MOVX A, @Ri
MOVX @DPTR, A
MOVX A, @DPTR
0
255
768
767
0
255
512
511
0
255
256
255
0
0
MBH078
Fig.5 Indirect addressing AUX-RAM (1792 bytes); ARD = 0 (bit PCON.6).
13
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
8.3
Addressing
The P8xC557E8 has five methods for addressing:
BYTE
ADDRESS
(HEX)
BYTE
ADDRESS
(DECIMAL)
BIT ADDRESS
(HEX)
• Register
• Direct
255
FFH
(MSB)
(LSB)
• Register-Indirect
• Immediate
• Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
‘destination/source’ field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
2FH 7F 7E 7D 7C 7B 7A 79 78
2EH 77 76 75 74 73 72 71 70
2DH 6F 6E 6D 6C 6B 6A 69 68
2CH 67 66 65 64 63 62 61 60
2BH 5F 5E 5D 5C 5B 5A 59 58
2AH 57 56 55 54 53 52 51 50
29H 4F 4E 4D 4C 4B 4A 49 48
28H 47 46 45 44 43 42 41 40
27H 3F 3E 3D 3C 3B 3A 39 38
26H 37 36 35 34 33 32 31 30
25H 2F 2E 2D 2C 2B 2A 29 28
24H 27 26 25 24 23 22 21 20
23H 1F 1E 1D 1C 1B 1A 19 18
22H 17 16 15 14 13 12 11 10
21H 0F 0E 0D 0C 0B 0A 09 08
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Access to memory addresses is as follows:
• Register in one of the four register banks through
Register, Direct or Register-Indirect addressing.
• Internal RAM (2048 bytes) through Direct or
Register-Indirect addressing.
– Internal RAM: bytes 0 to 127; may be addressed
directly/indirectly.
20H
1FH
07 06 05 04 03 02 01 00
– Internal RAM: bytes 128 to 255; share their address
location with the SFRs and so may only be addressed
indirectly as data RAM.
BANK 3
18H
17H
24
23
– AUX-RAM: bytes 0 to 1791; can only be addressed
indirectly via MOVX.
BANK 2
BANK 1
10H
0FH
16
15
• Special Function Registers through direct addressing at
address locations 128 to 255 (see Fig.7).
08H
07H
8
7
• External Data Memory through Register-Indirect
addressing.
BANK 0
• Program Memory look-up tables through Base-Register
00H
0
plus Index-Register-Indirect addressing.
MBH079
Fig.6 Internal MAIN RAM bit addresses.
1999 Mar 12
14
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
BYTE ADDRESS
BIT ADDRESS
(HEX)
REGISTER
(MNEMONIC)
(HEX)
(MSB)
(LSB)
FFH
PT2
FF
PCM2
FE
PCM1 PCM0
PCT3
FB
PCT2
FA
PCT1
F9
PCT0
F8
IP1
F8H
F0H
F8H
E0H
D8H
D0H
FD
FC
B
F7
ET2
EF
F6
F5
F4
F3
ECT3
EB
F2
ECT2
EA
F1
ECT1
E9
F0
ECT0
E8
ECM2 ECM1 ECM0
IEN1
ACC
S1CON
PSW
EE
ED
EC
E7
CR2
DF
E6
ENS1
DE
E5
STA
DD
E4
STO
DC
E3
SI
E2
AA
E1
CR1
D9
E0
CR0
D8
DB
DA
CY
AC
F0
RS1
D4
RS0
D3
OV
D2
F1
P
D7
D6
D5
D1
D0
T2OV
CF
CMI2
CE
CMI1
CD
CMI0
CC
CTI3
CB
CTI2
CA
CTI1
C9
CTI0
C8
TM2IR
P4
C8H
C0H
B8H
B0H
A8H
A0H
98H
90H
88H
80H
C7
-
C6
PAD
BE
C5
PS1
BD
C4
PS0
BC
C3
PT1
BB
C2
PX1
BA
C1
PT0
B9
C0
PX0
B8
IP0
BF
P3
B7
EA
AF
B6
EAD
AE
B5
ES1
AD
B4
ES0
AC
B3
ET1
AB
B2
EX1
AA
B1
ET0
A9
B0
EX0
A8
IEN0
P2
A7
SM0
9F
A6
SM1
9E
A5
SM2
9D
A4
REN
9C
A3
TB8
9B
A2
RB8
9A
A1
TI
A0
RI
S0CON
P1
99
98
97
TF1
8F
96
TR1
8E
95
TF0
8D
94
TR0
8C
93
IE1
8B
92
IT1
8A
91
IE0
89
90
IT0
88
TCON
P0
87
86
85
84
83
82
81
80
MBH456
Fig.7 Special Function Registers bit addresses.
1999 Mar 12
15
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Port 4 Can be configured to provide signals indicating a
match between timer/counter T2 and its compare
registers.
9
I/O FACILITIES
The P8xC557E8 has six 8-bit ports. Ports 0 to 3 are the
same as in the 80C51, with the exception of the additional
functions of Port 1. The parallel I/O function of Port 4 is
equal to that of Ports 1, 2 and 3. All ports are bidirectional
with the exception of Port 5 which is only a parallel input
port.
Port 5 May be used in conjunction with the ADC interface.
Unused analog inputs can be used as digital inputs.
As Port 5 lines may be used as inputs to the ADC,
these digital inputs have an inherent hysteresis to
prevent the input logic from drawing too much
current from the power lines when driven by analog
signals. Channel-to-channel crosstalk should be
taken into consideration when both digital and
analog signals are simultaneously input to Port 5
(see Chapter 21).
Ports 0, 1, 2, 3, 4 and 5 perform the following alternative
functions:
Port 0 Provides the multiplexed low-order address and
data bus used for expanding the P8xC557E8 with
standard memories and peripherals.
A pin of which the alternative function is not used may be
used as normal bidirectional I/O. The generation or use of
a Port 1, Port 3 or Port 4 pin as an alternative function is
carried out automatically by the P8xC557E8 provided the
associated Special Function Register bit is set HIGH.
Port 1 Is used for a number of special functions:
• 4 capture inputs (or external interrupt request
inputs if capture information is not utilized)
• external counter input
• external counter reset input.
The SDA and SCL lines serve the serial port SI01
(I2C-bus). Because the I2C-bus may be active while the
device is disconnected from VDD, these pins are provided
with open-drain drivers.
Port 2 Provides the high-order address bus when the
P8xC557E8 is expanded with external Data
Memory and / or the P8xC557E8 executes from
external Program Memory.
Figure 8 shows the pull-up arrangements of Ports 1 to 4;
Transistor ‘p1’ is turned on for 2 oscillator periods after Q
makes a HIGH-to-LOW transition. During this time, ‘p1’
also turns on ‘p3’ through the inverter to form an additional
pull-up.
Port 3 Pins can be configured individually to provide:
• External interrupt request inputs
• Counter inputs
• Receiver input and transmitter output of serial
port SIO 0 (UART)
• Control signals to read and write external Data
Memory.
strong pull-up
V
DD
2 oscillator
periods
p2
p3
p1
n
I/O PIN
Q
from port latch
I1
input data
INPUT
BUFFER
MLC926 - 1
read port pin
Fig.8 I/O buffers in the P8xC557E8 (Port 1 to Port 4).
16
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
In this application, the PWM outputs must be integrated
using conventional operational amplifier circuitry. If the
resulting output voltages have to be accurate, external
buffers with their own analog supply should be used to
buffer the PWM outputs before they are integrated.
10 PULSE WIDTH MODULATED OUTPUTS
The P8xC557E8 contains two Pulse Width Modulated
(PWM) output channels (see Fig.9). These channels
generate pulses of programmable length and interval.
The repetition frequency is defined by an 8-bit prescaler
PWMP, which supplies the clock for the counter.
The prescaler and counter are common to both PWM
channels. The 8-bit counter counts modulo 255, i.e., from
0 to 254 inclusive. The value of the 8-bit counter is
compared to the contents of two registers: PWM0 and
PWM1.
The repetition frequency fPWM, at the PWMn outputs is
fCLK
given by: fPWM
=
---------------------------------------------------------------
2 × (PWMP + 1) × 255
This gives a repetition frequency range of 123 Hz to
31.4 kHz (at fclk = 16 MHz). By loading the PWM registers
with either 00H or FFH, the PWM channels will output a
constant HIGH or LOW level, respectively. Since the 8-bit
counter counts modulo 255, it can never actually reach the
value of the PWM registers when they are loaded with
FFH.
Provided the contents of either of these registers is greater
than the counter value, the corresponding PWM0 or
PWM1 output is set LOW. If the contents of these registers
are equal to, or less than the counter value, the output will
be HIGH. The pulse-width-ratio is therefore defined by the
contents of the registers PWM0 and PWM1.
When a compare register (PWM0 or PWM1) is loaded with
a new value, the associated output is updated
immediately. It does not have to wait until the end of the
current counter period. Both PWMn output pins are driven
by push-pull drivers. These pins are not used for any other
purpose.
The pulse-width-ratio is in the range of 0⁄255 to 255
may be programmed in increments of 1⁄255
⁄255 and
.
Buffered PWM outputs may be used to drive DC motors.
The rotation speed of the motor would be proportional to
the contents of PWMn. The PWM outputs may also be
configured as a dual DAC.
PWM0
I
N
T
E
R
N
A
L
OUTPUT
BUFFER
PWM0
8-BIT COMPARATOR
8-BIT COUNTER
f
clk
1/2
PRESCALER
PWMP
B
U
S
OUTPUT
BUFFER
PWM1
8-BIT COMPARATOR
PWM1
MGA154
Fig.9 Functional diagram of Pulse Width Modulated outputs.
17
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
10.1 Prescaler Frequency Control Register (PWMP)
Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read.
Table 7 Prescaler Frequency Control Register (address FEH)
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWMP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.0
Table 8 Description of PWMP bits
BIT
SYMBOL
DESCRIPTION
7 to 0
PWMP.7 to PWMP.0
Prescaler division factor. The Prescaler division factor = (PWMP) + 1.
10.2 Pulse Width Register 0 (PWM0)
Table 9 Pulse width register (address FCH)
7
6
5
4
3
2
1
0
PWM0.7
PWM0.6
PWM0.5
PWM0.4
PWM0.3
PWM0.2
PWM0.1
PWM0.0
Table 10 Description of PWM0 bits
BIT
SYMBOL
DESCRIPTION
7 to 0
PWM0.7 to PWM0.0
Pulse width ratio.
(PWM0)
255 – (PWM0)
LOW/HIGH ratio of PWM0 signals
=
-----------------------------------------
10.3 Pulse Width Register 1 (PWM1)
Table 11 Pulse width register (address FDH)
7
6
5
4
3
2
1
0
PWM1.7
PWM1.6
PWM1.5
PWM1.4
PWM1.3
PWM1.2
PWM1.1
PWM1.0
Table 12 Description of PWM1 bits
BIT
SYMBOL
DESCRIPTION
7 to 0
PWM1.7 to PWM1.0
Pulse width ratio.
(PWM1)
255 – (PWM1)
LOW/HIGH ratio of PWM1 signals
=
-----------------------------------------
1999 Mar 12
18
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Eleven Special Function Registers (SFRs) perform the
user software interface to the ADC; see Table 14 for an
overview of the ADC SFRs. In order to have a minimum of
ADC service overhead in the microcontroller program, the
ADC is able to operate autonomously within its user
configurable autoscan function.
11 ANALOG-TO-DIGITAL CONVERTER (ADC)
11.1 ADC features
• 10-bit resolution
• 8 multiplexed analog inputs
• Programmable autoscan of the analog inputs
Figure 10 shows the functional diagram of the ADC.
• Bit oriented 8-bit scan-select register to select analog
inputs
11.3 ADC timing
• Continuous scan or one time scan configurable from
A programmable prescaler is controlled by the user
selectable bits ADPR1 and ADPR0 in SFR ADCON to
adapt the conversion time for different microcontroller
clock frequencies.
1 to 8 analog inputs
• Start of a conversion by software or with an external
signal
• Eight 10-bit buffer registers, one register for each analog
input channel
Table 13 shows conversion times (tADC) for one
analog-to-digital conversion at some convenient system
clock frequencies (fclk) and ADC programmable prescaler
divisors: m.
• Interrupt request after one channel scan loop
• Programmable prescaler (dividing by 2, 4, 6, 8) to adapt
to different system clock frequencies
Conversion time tADC = (6 × m + 1) machine cycles.
• Conversion time for one analog-to-digital conversion:
15 to 50 µs
A conversion time tADC consists of one sample time period
(which equals two bit conversion times), 10 bit conversion
time periods and one machine cycle to store the result.
After result storage an extra initializing time period follows
to select the next analog input channel (according to the
contents of SFR ADPSS), before the input signal is
sampled.Thus the time period between two adjacent
conversions within an autoscan loop is larger than the pure
time tADC. This autoscan cycle time is (7 × m) machine
cycles.
• Differential non-linearity (DLe): ±1 LSB
• Integral non-linearity (ILe): ±2 LSB
• Offset error (OSe): ±2 LSB
• Gain error (Ge): ±4%
• Absolute voltage error (Ae): 3 LSB
• Channel-to-channel matching (Mctc): ±1 LSB
• Crosstalk between analog inputs (Ct): < 60 dB at
100 kHz
At the start of an autoscan conversion the time between
writing to SFR ADCON and the first analog input signal
sampling depends on the current prescaler value (m) and
the relative time offset between this write operation and the
internal (divided) ADC clock. This gives a variation range
for the analog-to-digital conversion start time of (1⁄2 × m)
machine cycles.
• Monotonic and no missing codes
• Separated analog (VDDA, VSSA) and digital (VDD, VSS
supply voltages
)
• Reference voltage at two special pins: Vref(n)(A) and
Vref(p)(A)
.
For information on the ADC characteristics, refer to
Chapter 21.
Table 13 Conversion time configuration examples
tADC (µs) at fCLK
:
m
11.2
ADC functional description
6 MHz
8 MHz
12 MHz
16 MHz
The P8xC557E8 has a 10-bit successive approximation
ADC with 8 multiplexed analog input channels, comprising
a high input impedance comparator, DAC (built with
1024 series resistors and analog switches), registers and
control logic. Input voltage range is from Vref(n)(A)
(typical 0 V) to Vref(p)(A) (typical +5 V).
2
4
6
8
26.00
19.50
13.00(1)
25.00
37.00
49.00
9.75(1)
18.75
27.75
36.75
50.00
37.50
74.00(1)
98.00(1)
55.50(1)
73.50(1)
Note
Each of the set of 8 buffer registers (10-bit wide) store the
conversion results of the proper analog input channel.
1. Prohibited tADC values; for tADC outside the limits of
15 µs ≤ tADC ≤ 50 µs, the specified ADC
characteristics are not guaranteed.
1999 Mar 12
19
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
COMPARATOR
ADC0
to
ADC7
ANALOG
MULTIPLEXER
SAR
V
V
ref(p)(A)
ref(n)(A)
10
10
DAC
V
DDA1
10
V
SSA1
8 x 10-BIT RESULT
REGISTERS
ADEXS
SCAN LOGIC
2
8
ADPSS
ADCON
2 LATCHES
Read ADRSLn
Read ADRSH
8
8
2
8
INTERNAL BUS
MBH080
Fig.10 Functional diagram of ADC.
Either no edge (external start totally disabled), a rising
edge or/and a falling edge of ADEXS is selectable for
external conversion start by the bits ADSRE and ADSFE
in register ADCON.
11.4 ADC configuration and operation
Every analog-to-digital conversion is an autoscan
conversion. The two user selectable general operation
modes are continuous scan and one-time scan mode.
After completion of an analog-to-digital conversion the
10-bit result is stored in the corresponding 10-bit buffer
register. Then the next analog input is selected according
to the next higher set bit position in ADPSS, converted and
stored, and so on.
The desired analog input port channel(s) for conversion
is(are) selected by programming analog-to-digital input
port scan-select bits in SFR ADPSS. An analog input
channel is included in the autoscan loop if the
corresponding bit in SFR ADPSS is logic 1, a channel is
skipped if the corresponding bit in SFR ADPSS is logic 0.
When the result of the last conversion of this autoscan loop
is stored, the ADC interrupt flag ADINT (SFR ADCON), is
set. It is not cleared by interrupt hardware - it must be
cleared by software.
An autoscan is always started according to the lowest bit
position of SFR ADPSS that contains a logic 1.
An autoscan conversion is started by setting the flag
ADSST in register ADCON either by software or by an
external start signal at input pin ADEXS, if enabled.
1999 Mar 12
20
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
In continuous scan mode (ADCSA = 1; ADCON.2) the
ADC start and status flag ADSST (ADCON.3) retains the
set state and the autoscan loop restarts from the
beginning. In one-time scan mode (ADCSA = 0)
conversions stop after the last selected analog input was
converted, ADINT (ADCON.4) is set and ADSST is
cleared automatically.
11.6
ADC resolution and characteristics
The ADC system has its own analog supply pins VDDA1
and VSSA1. It is referenced by two special reference
voltage input pins sourcing the resistance ladder of the
DAC: Vref(p)(A) and Vref(n)(A). The voltage between Vref(p)(A)
and Vref(n)(A) defines the full-scale range. Due to the 10-bit
resolution the full scale range is divided into 1024 unit
steps.
ADSST cannot be set (neither externally nor by software)
as long as ADINT = 1, i.e. as long as ADINT is set, a new
conversion start - by setting flag ADSST - is inhibited;
actually it is only delayed until ADINT is cleared. If a logic 1
is written to ADSST while ADINT = 1, this new value is
internally latched and preserved, not setting ADSST until
ADINT = 0. In this state, a read of SFR ADCON will display
ADSST = 0, because always the effective ADC status is
read.
The unit step voltage is 1 LSB, which is typically 5 mV
(Vref(p)(A) = 5.12 V, Vref(n)(A) = 0 V = VSSA1).
The DAC's resistance ladder has 1023 equally spaced
taps, separated by a unit resistance ‘R’.
The first tap is located 0.5 × R above Vref(n)(A), the last tap
is located 1.5 × R below Vref(p)(A). This results in a total
ladder resistance of 1024 × R. This structure ensures that
the DAC is monotonic and results in a symmetrical
quantization error. For input voltages between:
• Vref(n)(A) and [Vref(n)(A) + 1⁄2 × LSB] the 10-bit conversion
result code will be 0000000000B (= 000H or 0D)
Note that under software control the analog inputs can also
be converted in arbitrary order, when one-time scan mode
is selected and in SFR ADPSS only one bit is set at a time.
In this case ADINT is set and ADSST is cleared after every
conversion.
• [Vref(p)(A) − 3⁄2 × LSB] and Vref(p)(A) the 10-bit conversion
result code will be 1111111111B (= 3FFH or 1023D).
11.5 ADC during Idle and Power-down mode
The result code corresponding to an analog input voltage
(Vin(A)) can be calculated from the formula:
The analog-to-digital converter is active only when the
microcontroller is in normal operating mode. If the Idle or
Power-down mode is activated, then the ADC is switched
off and put into a power saving idle state - a conversion in
progress is aborted, a previously set ADSST flag is cleared
and the internal clock is halted. The conversion result
registers are not affected.
V
– Vref(n)(A)
in(A)
Result code = 1024 ×
-----------------------------------------------
Vref(p)(A) – V
ref(n)(A)
The analog input voltage should be stable when it is
sampled for conversion. At any times the input voltage
slew rate must be less than 10 V/ms (5 V conversion
range) in order to prevent an undefined result.
This maximum input voltage slew rate can be ensured by
an RC low pass filter with R = 2.2 kΩ and C = 100 nF.
The capacitor between analog input pin and analog
ground pin shall be placed close to the pins in order to
have maximum effect in minimizing input noise coupling.
The interrupt flag ADINT will not be set by activation of Idle
or Power-down mode. A previously set flag ADINT will not
be cleared by the hardware. (Note: ADINT cannot be
cleared by hardware at all, except for a reset - it must be
cleared by the user software.)
After a wake-up from Idle or Power-down mode a set flag
ADINT indicates that at least one autoscan loop was
finished completely before the microcontroller was put into
the respective power reduction mode and it indicates that
the stored result data may be fetched now - if desired.
11.7 ADC after reset
After a reset of the microcontroller the ADCON and
ADPSS registers are initialized to zero. Registers ADRSLn
and ADRSH are not initialized by a reset.
For further information on Idle and Power-down modes,
refer to Chapter 15.
1999 Mar 12
21
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
11.8 ADC Special Function Registers
Table 14 ADC Special Function Registers overview
The SFRs are not bit addressable. For more information on Special Function Registers refer to Section 8.2.
RESET
VALUE
ADDRESS NAME R/W
DESCRIPTION
86H
96H
A6H
B6H
C6H
D6H
E6H
F6H
F7H
ADRSL0
ADRSL1
ADRSL2
ADRSL3
ADRSL4
ADRSL5
ADRSL6
ADRSL7
ADRSH
R
−
ADC Result Registers Low Byte: ADRSL0 to ADRSL7; The read value
after reset is indeterminate. Their data are not affected by chip reset.
R
00H
00H
00H
−
ADC Result Register High Bits: one common result SFR for the upper
2 result bits.
E7H
D7H
C7H
ADPSS R/W
ADCON R/W
ADC Input Port Scan-Select Register. Contains control bits to select the
analog input channel(s) to be scanned for analog-to-digital conversion.
ADC Control Register. Contains control and status bits for the
analog-to-digital converter peripheral block.
P5
R
Digital Input Port Register; shared with analog inputs. P5 is not affected by
chip reset.
11.8.1 ADC RESULT REGISTERS
The binary result code of the analog-to-digital conversions is accessed by the ADC Result Registers:
• ADRSLn (ADRSL0 to ADRSL7); eight input channel related conversion result SFRs for the 8 result lower bytes. Each
of ADRSLn is associated with the indexed analog input channel ADCn (ADC0/P5.0 to ADC7/P5.7).
• ADRSH for the ADC; one general SFR for the 2 result upper bits (bit 9 and 8).
During read (by software) of the ADRSLn register, simultaneously the two highest bits of the 10-bit conversion result are
copied into the two latches, ADRSH.0 and ADRSH.1 (SFR ADRSH) preserving them until the next read of any ADRSLn
register. Thus to ensure that the 10-bit result of the same single analog-to-digital conversion is captured, first read the
ADRSLn register and then the ADRSH register.
Table 15 ADC Result Register Low Byte; ADRSLn; n = 0 to 7 (address see 86H to F6H)
7
6
5
4
3
2
1
0
ADRSn.7
ADRSn.6
ADRSn.5
ADRSn.4
ADRSn.3
ADRSn.2
ADRSn.1
ADRSn.0
Table 16 Description of ADRSLn bits
BIT
SYMBOL
DESCRIPTION
7 to 0
ADRSn.7 to ADRSn.0
ADC result lower byte.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 17 ADC Result Register High Bits; ADRSH (address F7H)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
ADRSn.9
ADRSn.8
Table 18 Description of ADRSH bits
BIT
SYMBOL
DESCRIPTION
7 to 2
1 to 0
−
The upper 6 bits ADRSH.2 to ADRSH.7 are always read as a logic 0.
ADC result upper 2 bits.
ADRSn.9 to ADRSn.8
11.8.2 ADC INPUT PORT SCAN-SELECT REGISTER (ADPSS)
Table 19 ADC Input Port Scan-Select Register (address E7H)
7
6
5
4
3
2
1
0
ADPSS7
ADPSS6
ADPSS5
ADPSS4
ADPSS3
ADPSS2
ADPSS1
ADPSS0
Table 20 Description of ADPSS bits
BIT
SYMBOL
DESCRIPTION
Control bits to select the analog input channel(s) to be scanned for
analog-to-digital conversion. If all bits ADPSS0 to ADPSS7 = 0, then no conversion can
be started. If ADPSS is written while an analog-to-digital conversion is in progress
(ADSST = 1; ADCON.3) then the autoscan loop with the previous selected analog
inputs is completed first. The next autoscan loop is performed with the new selected
analog inputs. For each individual bit position ADPSSn (n = 0 to 7):
7 to 0
ADPSS7
to
ADPSS0
• If ADPSSn = 0, then the corresponding analog input is skipped in the autoscan loop
• If ADPSSn = 1, then the corresponding analog input is included in the autoscan loop.
11.8.3 ADC CONTROL REGISTER (ADCON)
Table 21 ADC Control Register (address D7H)
7
6
5
4
3
2
1
0
ADPR1
ADPR0
ADPOS
ADINT
ADSST
ADCSA
ADSRE
ADSFE
Table 22 Description of ADCON bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
ADPR1
ADPR0
ADPOS
ADINT
These two bits determine the value of the prescaler divisor (m); see Table 23.
ADPOS is reserved for future use. Must be a logic 0 if ADCON is written.
ADC interrupt. This flag is set when all selected analog inputs are converted (both in
continuous scan and in one-time scan mode). An interrupt is invoked if this interrupt flag
is enabled. ADINT must be cleared by software. It cannot be set by software.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
BIT
SYMBOL
DESCRIPTION
3
ADSST
ADC start and status. Setting this bit by software or by hardware (via ADEXS input)
starts the analog-to-digital conversion of the selected analog inputs. ADSST stays a
logic 1 in continuous scan mode. In one-time scan mode, ADSST is cleared by
hardware when the last selected analog input channel has been converted. As long as
ADSST = 1, new start commands to the ADC-block are ignored. An analog-to-digital
conversion in progress is aborted if ADSST is cleared by software.
2
1
0
ADCSA
ADSRE
ADSFE
ADCSA =1 results in a continuous scan of the selected analog inputs after a start of an
analog-to-digital conversion. ADCSA = 0 results in an one-time scan of the selected
analog inputs after a start of an analog-to-digital conversion.
If ADSRE = 1, then a rising edge at input ADEXS will start the analog-to-digital
conversion and generate a capture signal. If ADSRE = 0, then a rising edge at input
ADEXS has no effect.
If ADSFE = 1, then a falling edge at input ADEXS will start the analog-to-digital
conversion and generate a capture signal. If ADSFE = 0, then a falling edge at input
ADEXS has no effect.
Table 23 Prescaler selection
ADPR1
ADPR0
PRESCALER DIVISOR (m)
0
0
1
1
0
1
0
1
2 (default by reset)
4
6
8
11.8.4 DIGITAL INPUT PORT REGISTER (P5)
Digital Input Port Register (P5) is shared with analog inputs. P5 is not affected by chip reset. SFR P5 always represents
the binary value of the logic level at input pins P5.0/ADC0 to P5.7/ADC7. Reading P5 does not affect analog-to-digital
conversions. But it is recommended to use the digital input port function of the hardware Port 5 only as an alternative to
analog input voltage conversions. Simultaneous mixed operation is discouraged to guarantee a reliable and accurate
ADC result. For more information on P5 refer to Chapter 9.
Table 24 Digital Input Port Register (address C7H)
7
6
5
4
3
2
1
0
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
Table 25 Description of P5 bits
BIT
SYMBOL
P5.7 to P5.0
DESCRIPTION
7 to 0
Binary value of the logic level at input pins P5.0/ADC0 to P5.7/ADC.7.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Timer 0 and Timer 1 can be programmed independently to
operate in one of four modes:
12 TIMERS/COUNTERS
The P8xC557E8 contains,
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
prescaler.
• Three 16-bit timer/event counters:
Timer 0, Timer 1 and Timer T2
Mode 1 16-bit time-interval or event counter.
•
One 8-bit timer, T3.
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
12.1 Timer 0 and Timer 1
Timer 0 and Timer 1 may be programmed to carry out the
following functions:
Mode 3 Timer 0: one 8-bit time-interval or event counter
and one 8-bit time-interval counter.
Timer 1: stopped.
• Measure time intervals and pulse durations
• Count events
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes 0, 1 or 2 but cannot set an interrupt
request flag or generate an interrupt. However, the
overflow from Timer 1 can be used to pulse the serial port
baud rate generator. With a 16 MHz crystal, the counting
frequency of these timers/counters is as follows:
• Generate interrupt requests.
Timers 0 and 1 each have a control bit in SFR TMOD that
selects the timer or counter function of the corresponding
timer.
In the timer function, the register is incremented every
machine cycle. Thus, one can think of it as counting
machine cycles. Since a machine cycle consists of
12 oscillator periods, the count rate is 1⁄12 × the oscillator
frequency.
• In the timer function, the timer is incremented at a
frequency of 1.33 MHz (1⁄12 × the system clock
frequency)
• When programmed for external inputs: 0 to 660 kHz
(1⁄24 × the system clock frequency).
In the counter function, the register is incremented in
response to a HIGH-to-LOW transition at the
Both internal and external inputs can be gated to the
counter by a second external source for directly measuring
pulse durations. When configured as a counter, the
register is incremented on every falling edge on the
corresponding input pin T0 or T1. The earliest moment, the
incremented register value can be read is during the
second machine cycle following the machine cycle within
which the incrementing pulse occurred.
corresponding external input pin, T0 or T1. In this function,
the external input is sampled during S5P2 of every
machine cycle. When the samples show a HIGH in one
cycle and a LOW in the next cycle, the counter is
incremented. Thus, it takes two machine cycles
(24 oscillator periods) to recognize a HIGH-to-LOW
transition. There are no restrictions on the duty cycle of the
external input signal. To ensure that a given level is
sampled at least once before it changes, it should be held
for at least one full machine cycle.
The counters are started and stopped under software
control. Each one sets its interrupt request flag when it
overflows from all HIGHs to all LOWs (or automatic reload
value), with the exception of Mode 3 as previously
described.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
12.1.1 TIMER/COUNTER MODE CONTROL REGISTER (TMOD)
Table 26 Timer/Counter Mode Control Register (address 89H)
7
6
5
4
3
2
1
0
GATE
C/T
M1
M0
GATE
C/T
M1
M0
Table 27 Description of TMOD bits for Timer 1 and Timer 0
Timer 0: bit TMOD.0 to TMOD.3; Timer 1: bit TMOD.4 to TMOD.7; n = 0, 1.
BIT
SYMBOL
DESCRIPTION
7 and 3
GATE
Gating control. When set Timer/counter ‘n’ is enabled only while INTn pin is HIGH and
control bit TRn (TR1 or TR0) is set. When cleared Timer ‘n’ is enabled whenever TRn
control bit is set.
6 and 2
C/T
Timer or Counter Selector. Cleared for Timer operation; input from internal system
clock. Set for Counter operation; input from pin Tn (T1 or T0).
5 and 1
4 and 0
M1
M0
Timer 0, Timer 1 mode select; see Table 28.
Table 28 Timer 0, Timer 1 mode select
M1
0
M0
0
OPERATING
Timer TL0/TL1 serves as 5-bit prescaler.
0
1
16-bit Timer/Counter TH0/TH1 and TL0/TL1 are cascaded; there is no prescaler.
1
0
8-bit auto-reload Timer/Counter TH0/TH1 holds a value which is to be reloaded into
TL0/TL1 each time it overflows.
1
1
1
1
Timer 0: TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
Timer 1: Timer/Counter 1 stopped.
12.1.2 TIMER/COUNTER CONTROL REGISTER (TCON)
Table 29 Timer/Counter Control Register (address 88H)
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 30 Description of TCON bits
BIT
SYMBOL
DESCRIPTION
7 and 5
TF1 and TF0 Timer 1 and Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
6 and 4
3 and 1
2 and 0
TR1 and TR0 Timer 1 and Timer 0 run control bit. Set/cleared by software to turn Timer/Counter
on/off.
IE1 and IE0 Interrupt 1 and Interrupt 0 edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
IT1 and IT0 Interrupt 1 and Interrupt 0 type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupts.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Using the Capture Register CTCON (see Table 35), these
inputs may invoke capture and interrupt request on a
positive edge, a negative edge or on both edges. If neither
a positive nor a negative edge is selected for capture input,
no capture or interrupt request can be generated by this
input.
12.2 Timer T2
Timer T2 is a 16-bit timer/counter which has capture and
compare facilities. The operational diagram is shown in
Figure 11.
The 16 bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of
the prescaler is clocked with 1⁄12 of the clock frequency, or
by an external source connected to the T2 input, or it is
switched off. The maximum repetition rate of the external
clock source is 1⁄12 × fclk, twice that of Timer 0 and Timer 1.
The prescaler is incremented on a rising edge. It is cleared
if its division factor or its input source is changed, or if the
timer/counter is reset (see in Table 31). T2 is readable ‘on
the fly’, without any extra read latches; this means that
software precautions have to be taken against
The contents of the Compare Registers CM0, CM1 and
CM2 are continuously compared with the counter value of
Timer T2. When a match occurs, an interrupt may be
invoked. A match of CM0 sets the bits 0 to 5 of Port 4, a
CM1 match resets these bits and a CM2 match toggles bits
6 and 7 of Port 4, provided these functions are enabled by
the STE respectively RTE registers. A match of CM0 and
CM1 at the same time results in resetting bits 0-5 of Port 4.
CM0, CM1 and CM2 are reset by the RSTIN signal.
For more information concerning the TM2CON, CTCON,
TM2IR and the STE/RTE registers see “Data Handbook
IC20; Section 80C51 family hardware description”.
misinterpretation at overflow from least to most significant
byte while T2 is being read. T2 is not loadable and is reset
by the RST signal or at the positive edge of the input signal
RT2, if enabled. In the Idle or Power-down mode the timer/
counter and prescaler are reset and halted.
Port 4 can be read and written by software without
affecting the toggle, set and reset signals. At a byte
overflow of the least significant byte, or at a 16-bit overflow
of the timer/counter, an interrupt sharing the same
interrupt vector is requested. Either one or both of these
overflows can be programmed to request an interrupt.
T2 is connected to four 16-bit Capture Registers:
CT0, CT1, CT2 and CT3. A rising or falling edge on the
inputs CT0I, CT1I, CT2I or CT3I (alternative function of
Port 1) results in loading the contents of T2 into the
respective Capture Registers and an interrupt request.
All interrupt flags must be reset by software.
12.2.1 T2 CONTROL REGISTER (TM2CON)
Table 31 T2 Control Register (address EAH)
7
6
5
4
3
2
1
0
T2IS1
T2IS0
T2ER
T2BO
T2P1
T2P0
T2MS1
T2MS0
Table 32 Description of TM2CON bits
BIT
7
SYMBOL
T2IS1
DESCRIPTION
Timer T2 16-bit overflow interrupt select.
Timer T2 byte overflow interrupt select.
6
T2IS0
5
T2ER
Timer T2 external reset enable. When this bit is set, Timer T2 may be reset by a rising
edge on RT2 (P1.5).
4
3
2
1
0
T2BO
T2P1
Timer T2 byte overflow interrupt flag.
Timer T2 prescaler select (see Table 33).
T2P0
T2MS1
T2MS0
Timer T2 mode select (see Table 34).
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 33 Timer 2 prescaler select
Table 34 Timer 2 mode select
T2MS1 T2MS0 MODE SELECTED
Timer T2 halted (off)
T2P1
T2P0
TIMER T2 CLOCK
clock source
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
1⁄2 × clock source
1⁄4 × clock source
1⁄8 × clock source
⁄12 × fclk T2 clock source
1
Test mode; do not use
T2 clock source = pin T2
12.2.2 CAPTURE CONTROL REGISTER (CTCON)
Table 35 Capture Control Register (address EBH)
7
6
5
4
3
2
1
0
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
Table 36 Description of CTCON bits
BIT
7
SYMBOL
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
DESCRIPTION
interrupt triggered on negative edge of CT3I
interrupt triggered on positive edge of CT3I
interrupt triggered on negative edge of CT2I
interrupt triggered on positive edge of CT2I
interrupt triggered on negative edge of CT1I
interrupt triggered on positive edge of CT1I
interrupt triggered on negative edge of CT0I
interrupt triggered on positive edge of CT0I
6
5
4
3
2
1
0
12.2.3 INTERRUPT FLAG REGISTER (TM2IR)
Table 37 Interrupt flag register (address C8H)
7
6
5
4
3
2
1
0
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
Table 38 Description of TM2IR bits
BIT
7
SYMBOL
T2OV
CMI2
CMI1
CMI0
CTI3
DESCRIPTION
T2: 16-bit overflow interrupt flag
CM2: interrupt flag
CM1: interrupt flag
CM0: interrupt flag
CT3: interrupt flag
6
5
4
3
2
CTI2
CT2: interrupt flag
1
CTI1
CT1: interrupt flag
0
CTI0
CT0: interrupt flag
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
12.2.4 SET ENABLE REGISTER (STE)
Table 39 Set enable register (address EEH)
7
6
5
4
3
2
1
0
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
Table 40 Description of STE bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
If HIGH then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle.
If HIGH then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle.
If HIGH then P4.5 is set on a match between CM0 and T2.
If HIGH then P4.4 is set on a match between CM0 and T2.
If HIGH then P4.3 is set on a match between CM0 and T2.
If HIGH then P4.2 is set on a match between CM0 and T2.
If HIGH then P4.1 is set on a match between CM0 and T2.
If HIGH then P4.0 is set on a match between CM0 and T2.
12.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)
Table 41 Reset/Toggle enable register (address EFH)
7
6
5
4
3
2
1
0
TP47
TP46
RP45
RP44
RP43
RP42
RP41
RP40
Table 42 Description of RTE bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
TP47
TP46
RP45
RP44
RP43
RP42
RP41
RP40
If HIGH then P4.7 toggles on a match between CM2 and T2.
If HIGH then P4.6 toggles on a match between CM2 and T2.
If HIGH then P4.5 toggles on a match between CM1 and T2.
If HIGH then P4.4 toggles on a match between CM1 and T2.
If HIGH then P4.3 toggles on a match between CM1 and T2.
If HIGH then P4.2 toggles on a match between CM1 and T2.
If HIGH then P4.1 toggles on a match between CM1 and T2.
If HIGH then P4.0 toggles on a match between CM1 and T2.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
CT0I
INT
CTI0
CT1I
INT
CT2I
INT
CT3I
INT
CTI1
CTI2
CTI3
CT0
CT1
CT2
CT3
off
8-bit overflow interrupt
16-bit overflow interrupt
f
1/12
clk
T2
PRESCALER
T2 COUNTER
RT2
T2ER
external reset
enable
INT
INT
INT
COMP
COMP
COMP
S
S
S
S
S
S
R
R
R
R
R
R
T
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
CM0 (S)
CM1 (R)
CM2 (T)
I/O port 4
MGD632
TG
TG
T
STE
RTE
S
R
T
= set
= reset
= toggle
T2 SFR address: TML2 = lower 8 bits
TMH2 = higher 8 bits
TG = toggle status
Fig.11 Block diagram of Timer 2.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
The Watchdog Timer can only be reloaded if the condition
flag WLE = PCON.4 has been previously set by software.
12.3 Watchdog Timer (T3)
In addition to Timer T2 and the standard timers, a
Watchdog Timer (T3) consisting of an 11-bit prescaler and
an 8-bit timer is also incorporated (see Fig.12).
At the moment the counter is loaded the condition flag is
automatically cleared.
The time interval between the timer’s reloading and the
occurrence of a reset depends on the reloaded value.
For example, this may range from 1.5 ms to 0.375 s when
using an oscillator frequency of 16 MHz.
T3 is incremented every 1.5 ms, derived from the oscillator
frequency of 16 MHz by the following formula:
fclk
ftimer
=
-------------------------
12 × 2048
In the Idle state the Watchdog Timer and reset circuitry
remain active.
When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at pin RSTOUT. Also
the PLL control register is reset.
The Watchdog Timer is controlled by the watchdog enable
pin (EW). A LOW level enables the watchdog timer and
disables the Power-down mode. A HIGH level disables the
watchdog timer and enables the Power-down mode.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control.
INTERNAL BUS
(1)
to reset circuitry
PRESCALER
11-BIT
1/12 f
clk
TIMER T3 (8-BIT)
CLEAR
LOAD
LOADEN
CLEAR
write
T3
WLE
PD
LOADEN
PCON.4
PCON.1
EW
INTERNAL BUS
MBH081
(1) See Fig.20.
Fig.12 Functional diagram of T3 Watchdog Timer.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Mode 2 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1).
On transmit, the 9th data bit (TB8 in S0CON) can
be assigned the value of 0 or 1. With nominal
software, TB8 can be the parity bit (P in PSW).
During a receive, the 9th data bit is stored in RB8
(S0CON), and the stop bit is ignored. The baud
rate is programmable to either 1⁄32 or 1⁄64 of the
oscillator frequency.
13 SERIAL I/O PORTS
The P8xC557E8 is equipped with 2 independent serial
ports:
• SIO0, which is the full duplex UART port, identical to the
PCB80C51 serial port
• SIO1,which is an I2C-bus serial I/O interface with byte
oriented master and slave functions.
13.1 Serial I/O Port: SIO0 (UART)
Mode 3 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1).
Mode 3 is the same as Mode 2 except for the
baud rate which is variable in Mode 3.
SIO0 is a full duplex serial I/O port - it can transmit and
receive simultaneously. This serial port is also
receive-buffered. It can commence reception of a second
byte before the previously received byte has been read
from the receive register. If, however, the first byte has still
not been read by the time reception of the second byte is
complete, one of the bytes will be lost. The SIO0 receive
and transmit registers are both accessed via the S0BUF
special function register. Writing to S0BUF loads the
transmit register, and reading S0BUF accesses a
physically separate receive register. SIO0 can operate in
four modes:
In all four modes, transmission is initiated by any
instruction that writes to the SFR S0BUF. Reception is
initiated in Mode 0 when RI = 0 and REN = 1. In the other
three modes, reception is initiated by the incoming start bit
provided that REN = 1.
Modes 2 and 3 are provided for multiprocessor
communications. In these modes, 9 data bits are received
with the 9th bit written to RB8 (S0CON). The 9th bit is
followed by the stop bit. The port can be programmed so
that with receiving the stop bit, the serial port interrupt will
be activated if, and only if RB8 = 1.
Mode 0 Serial data is transmitted and received through
RXD. TXD outputs the shift clock. 8 data bits are
transmitted/received (LSB first). The baud rate is
fixed at 1⁄12 × the oscillator frequency. A write into
S0CON should be avoided during a transmission
to avoid spikes on RXD/TXD.
This feature is enabled by setting bit SM2 in S0CON.
It may be used in multiprocessor systems.
Mode 1 10 bits are transmitted via TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
and a stop bit (1). On receive, the stop bit is put
into RB8 of the S0CON SFR. The baud rate is
variable.
For more information about how to use the UART in
combination with the registers S0CON, PCON, IE, SBUF
and the Timer register, refer to “Data Handbook IC20”.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
13.1.1 SERIAL PORT CONTROL REGISTER (S0CON)
Table 43 Serial Port Control Register (address 98H)
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Table 44 Description of S0CON bits
BIT
SYMBOL
DESCRIPTION
These bits are used to select the serial port mode; see Table 45.
7
6
5
SM0
SM1
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In these modes,
if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0.
In Mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received.
In Mode 0, SM2 should be a logic 0.
4
3
2
1
REN
TB8
RB8
TI
Enables serial reception. Set by software to enable reception. Clear by software to
disable reception.
The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as
desired.
In modes 2 and 3, RB8 is the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8
is the stop bit that was received. In Mode 0, RB8 is not used.
Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at
the beginning of the stop bit in the other modes, in any serial transmission. Must be
cleared by software.
0
RI
Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial reception (except
see SM2). Must be cleared by software.
Table 45 Serial port mode select
SM0
SM1
MODE
DESCRIPTION
BAUD RATE
1
0
0
1
1
0
1
0
1
Mode 0
Mode 1
Mode 2
Mode 3
Shift register
8-bit UART
9-bit UART
9-bit UART
⁄12 × fclk
variable
64 or 1⁄32 × fclk
variable
1
⁄
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
13.2 Serial I/O Port: SIO1 (I2C-bus interface)
The SIO1 logic performs a byte oriented data transport;
clock generation, address recognition and bus control
arbitration are all controlled by hardware. Via two pins the
external I2C-bus is interfaced to the SIO1 logic: SCL serial
clock I/O and SDA serial data I/O (SFR S1CON bit ENS1
for enabling the SIO1 logic).
The SIO1 of the P8xC557E8 provides the fast mode,
which allows a fourth-fold increase of the bit rate up to
400 kHz. Nevertheless it is downward compatible, i.e. it
can be used in a 0 to 100 kbit/s I2C-bus system.
Except from the bit rate selection (see Table 48) and the
timing of the SCL and SDA signals (see Chapter 11) the
SIO circuit is the same as described in detail in the
80C51-based “Data Handbook IC20” for the 8xC552
microcontroller.
The SIO1 logic handles byte transfer autonomously.
It keeps track of the serial transfers, and a status register
(S1STA) reflects the status of SIO1 and the I2C-bus.
Via 4 SFRs the CPU interfaces to the I2C-bus logic:
• S1CON; Serial Control Register. Bit-addressable by the
CPU
The I2C-bus is a simple bidirectional 2-wire bus for efficient
inter-IC data exchange. Features of the I2C-bus are:
• S1STA; Status Register whose contents may be used
as a vector to service routines
• Only two bus lines are required: a serial clock line (SCL)
and a serial data line (SDA)
• S1DAT; Data Shift Register. The data byte is stable as
long as SI = 1 (SFR S1CON)
• Each device connected to the bus is software
addressable by a unique address
• S1ADR; Slave Address Register. Its LSB
enables/disables general call address recognition.
• Masters can operate as master transmitter or as master
receiver
• It is a true multi-master bus including collision detection
and arbitration to prevent data corruption if two or more
masters simultaneously initiate data transfer
13.2.1 SERIAL CONTROL REGISTER (S1CON)
The CPU can read from and write to this 8-bit, directly
addressable SFR. Two bits are affected by the SIO1
hardware:
• Serial clock synchronization allows devices with
different bit rates to communicate via the same serial
bus
• the SI bit is set when a serial interrupt is requested, and
• ICs can be added to or removed from an I2C-bus system
without affecting any other circuit on the bus
• the STO bit is cleared when a STOP condition is present
on the I2C-bus. The STO bit is also cleared when
ENS1 = 0.
• Fault diagnostics and debugging are simple;
malfunctions can be immediately traced.
When SIO1 is in a master mode, serial clock frequency is
determined by the clock rate bits CR2, CR1 and CR0.
The various bit rates are shown in Table 48.
For more information on the I2C-bus specification
(including fast-mode) please refer to the Philips publication
“The I2C-bus and how to use it” ordering number
9398 393 40011 and/or the 80C51-based
“Data Handbook IC20”.
The data shown in Table 48 do not apply to SIO1 in a slave
mode. In the slave modes, SIO1 will automatically
synchronize with any clock frequency up to 400 kHz.
However, serial clock frequencies above 100 kHz require
an oscillator frequency fclk of at least 12 MHz.
The on-chip I2C logic provides a serial interface that meets
the I2C-bus specification, supporting 4 modes of operation:
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 46 Serial Control Register (address D8H)
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Table 47 Description of S1CON bits
BIT
SYMBOL
DESCRIPTION
7
6
CR2
Clock rate bit 2, see Table 48.
ENS1
Enable serial I/O. ENS1 = 0: serial I/O disabled and reset. SDA and SCL outputs are high-Z.
ENS1 = 1: serial I/O enabled.
5
4
STA
STO
START flag. When this bit is set in slave mode, the hardware checks the I2C-bus and generates
a START condition if the bus is free or after the bus becomes free. If the device operates in
master mode it will generate a repeated START condition.
STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition
detected on the I2C-bus clears this bit. This bit may also be set in slave mode in order to recover
from an error condition. In this case no STOP condition is generated to the I2C-bus, but the hard
ware releases the SDA and SCL lines and switches to the not selected receiver mode. The
STOP flag is cleared by the hardware.
3
SI
Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the
following events occur:
• A START condition is generated in master mode.
• The own slave address has been received during AA = 1.
• The general call address has been received while GC (bit S1ADR.0) and AA = 1.
• A data byte has been received or transmitted in master mode (even if arbitration is lost).
• A data byte has been received or transmitted as selected slave.
• A STOP or START condition is received as selected slave receiver or transmitter.
While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be
reset by software.
2
AA
Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the
following conditions:
• Own slave address is received.
• General call address is received; GC (bit S1ADR.0) = 1.
• A data byte is received, while the device is programmed to be a master receiver.
• A data byte is received. while the device is a selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when
the own address or general call address is received.
1
0
CR1
CR0
Clock rate bits 1 and 0; see Table 48.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 48 Selection of I2C-bus bit rate
BIT RATE (kbits/s) at fclk
CR2
CR1
CR0
12 MHz
16 MHz
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
3.75
75
66.7
5
100
100
200(1)
−
266.7(1)
10
400(1)
7.5
300(1)
400(1)
−
Note
1. These bit rates are for ‘fast-mode’ I2C-bus applications and cannot be used for standard I2C bit rates up to
100 kbits/s.
7
7
0
0
GC
SLAVE ADDRESS
S1ADR
SHIFT REGISTER
S1DAT
SDA
ARBITRATION SYNC LOGIC
SCL
BUS CLOCK GENERATOR
7
0
CONTROL REGISTER
STATUS REGISTER
S1CON
7
0
MLB199
S1STA
Fig.13 Block diagram of I2C serial I/O interface.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
13.2.2 SERIAL STATUS REGISTER (S1STA)
The contents of this register may be used as a vector to a service routine. This optimizes the response time of the
software and consequently that of the I2C-bus. S1STA is a read-only register. The status codes for all possible modes
of the I2C-bus interface are given in Tables 51 to 55.
Table 49 Serial status register (address D9H)
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
Table 50 Description of S1STA bits
BIT
SYMBOL
DESCRIPTION
7 to 3
2 to 0
SC4 to SC0 5-bit status code.
−
These 3 bits are held LOW (for service routine vector increment 8).
Table 51 MST/TRX mode
S1STA VALUE
DESCRIPTION
08H
10H
18H
20H
28H
30H
38H
A START condition has been transmitted.
A repeated START condition has been transmitted.
SLA and W have been transmitted, ACK has been received.
SLA and W have been transmitted, ACK received.
DATA and S1DAT has been transmitted, ACK received.
DATA and S1DAT has been transmitted, ACK received.
Arbitration lost in SLA, R/W or DATA.
Table 52 MST/REC mode
S1STA VALUE
DESCRIPTION
Arbitration lost while returning ACK.
38H
40H
48H
50H
58H
SLA and R have been transmitted, ACK received.
SLA and R have been transmitted, ACK received.
DATA has been received, ACK returned.
DATA has been received, ACK returned.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 53 SLV/REC mode
S1STA VALUE
DESCRIPTION
Own SLA and W have been received, ACK returned.
60H
68H
70H
78H
80H
88H
90H
98H
A0H
Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned.
General CALL has been received, ACK returned.
Arbitration lost in SLA, R/W as MST. General call has been received.
Previously addressed with own SLA. DATA byte received, ACK returned.
Previously addressed with own SLA. DATA byte received, ACK returned.
Previously addressed with general call. DATA byte has been received, ACK has been returned.
Previously addressed with general call. DATA byte has been received, ACK has been returned.
A STOP condition or repeated START condition has been received while still addressed as SLV/REC
or SLV/TRX.
Table 54 SLV/TRX mode
S1STA VALUE
DESCRIPTION
A8H
B0H
B8H
C0H
C8H
Own SLA and R have been received, ACK returned.
Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned.
DATA byte has been transmitted, ACK returned.
DATA byte has been transmitted, ACK returned.
Last DATA byte has been transmitted (AA = logic 0), ACK received.
Table 55 Miscellaneous
S1STA VALUE
DESCRIPTION
00H
F8H
Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition.
No relevant information available, SI not set.
Table 56 Symbols used in Tables 51 to 55
SYMBOL
DESCRIPTION
SLA
R
7-bit slave address
read bit
W
write bit
ACK
ACK
DATA
MST
SLV
TRX
REC
acknowledgement (acknowledge bit = logic 0)
no acknowledgement (acknowledge bit = logic 1)
8-bit data byte to or from I2C-bus
master
slave
transmitter
receiver
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
13.2.3 DATA SHIFT REGISTER (S1DAT)
This register contains the serial data to be transmitted or data which has been received. Bit 7 is transmitted or received
first; i.e. data is shifted from right to left.
Table 57 Data Shift Register (address DAH)
7
6
5
4
3
2
1
0
S1DAT.7
S1DAT.6
S1DAT.5
S1DAT.4
S1DAT.3
S1DAT.2
S1DAT.1
S1DAT.0
13.2.4 ADDRESS REGISTER (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
a slave receiver/transmitter.
Table 58 Address Register (address DBH)
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
GC
Table 59 Description of S1ADR bits
BIT
7 to 1
0
SYMBOL
SLA6 to SLA0 Own slave address.
DESCRIPTION
GC
This bit is used to determine whether the general call address is recognized. When
GC = 0, the general call address is not recognized; when GC = 1, the general call
address is recognized.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
The Timer 0 and Timer 1 interrupts are generated by TF0
and TF1, which are set by a roll-over in their respective
timer/counter register (except for Timer 0 in Mode 3 of the
serial interface). When a Timer interrupt is generated, the
flag that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
14 INTERRUPT SYSTEM
External events and the real-time-driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. Interrupt response
time in a single-interrupt system is in the range
2.25 µs to 6.75 µs when using a 16 MHz crystal.
The latency time depends on the sequence of instructions
executed directly after an interrupt request.
The eight Timer/Counter T2 Interrupt sources are:
4 capture Interrupts (1), 3 compare interrupts and an
overflow interrupt. The appropriate interrupt request flags
must be cleared by software.
The UART Serial Port Interrupt is generated by the logical
OR of RI and TI (register S0CON). Neither of these flags
is cleared by hardware. The service routine will normally
have to determine whether it was RI or TI that generated
the interrupt, and the bit will have to be cleared by
software.
The P8xC557E8 acknowledges interrupt requests from
15 sources as follows (see Fig.14):
• INT0 and INT1 external interrupts
• Timer 0 and Timer 1 internal timer/counter interrupts
• Timer 2 internal timer/counter byte and/or 16-bit
overflow, 3 compare and 4 capture interrupts (or
4 additional external interrupts).
The I2C Interrupt is generated by bit SI in register S1CON.
This flag has to be cleared by software.
The ADC Interrupt is generated by bit ADINT, which is set
when the conversion of all selected analog inputs to be
scanned is finished. ADINT must be cleared by software.
It cannot be set by software.
Note that if a capture register is unused and its contents
are of no interest, then the corresponding input pin
CTnI/P1.n (n = 0 to 3) may be used as a (configurable)
positive and/or negative edge triggered additional
external interrupt input (INT2, INT3, INT4 and INT5).
The ‘seconds’ timer Interrupt is generated by bit SECINT
in register PLLCON. This flag has to be cleared by
software. Note that the ‘seconds’ timer can only be used
with the 32 kHz PLL oscillator.
• UART serial I/O port receive/transmit interrupt
• I2C-bus interface serial I/O interrupt
• ADC autoscan completion interrupt
All of the bits that generate interrupts can be set or cleared
by software, with the same result as though they had been
set or cleared by hardware (except the ADC interrupt
request flag ADINT, which cannot be set by software).
That is, interrupts can be generated or pending interrupts
can be cancelled in software.
• ‘Seconds’ timer interrupt SEC (ORed with INT1); for
details please refer to Chapter 16.2.4.
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in register TCON. The flags that actually
generate these interrupts are bits IE0 and IE1 in TCON.
When an external interrupt is generated, the
The Interrupts X0, T0, X1, T1, SEC, S0 and S1 are able to
terminate the Idle mode.
corresponding request flag is cleared by the hardware
when the service routine is vectored to, only if the interrupt
was transition-activated. If the interrupt was level-activated
then the interrupt request flag remains set until the external
interrupt pin INTn goes HIGH. Consequently, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate
the request before the interrupt service routine is
completed, or else another interrupt will be generated.
As these external interrupts are active LOW a ‘wire-ORing’
of several interrupt sources to one input pin allows
expansion.
14.1 Interrupt Enable Registers
Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in the interrupt enable
Special Function Registers IEN0 and IEN1. All interrupt
sources can also be globally disabled by clearing bit EA in
IEN0. The interrupt enable registers are described in
Tables 62 and 64.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
14.2 Interrupt Handling
14.3 Interrupt Priority Structure
The interrupt sources are sampled at S5P2 of every
machine cycle. The samples are polled during the
following machine cycle. If one of the flags was in a set
condition at S5P2 of the previous machine cycle, the
polling cycle will detect it and the interrupt system will
generate an LCALL to the appropriate service routine,
provided this hardware generated LCALL is not blocked by
any of the following conditions:
Each interrupt source can be assigned one of two priority
levels: high and low. Interrupt priority levels are defined by
the interrupt priority SFRs IP0 and IP1, which are
described in Tables 66 and 68.
Interrupt priority levels are as follows:
logic 0 = low priority
logic 1 = high priority.
1. An interrupt of higher or equal priority level is already
in progress.
A low priority interrupt may be interrupted by a high priority
interrupt. A high priority interrupt cannot be interrupted by
any other interrupt source. If two requests of different
priority occur simultaneously, the high priority level request
is serviced. If requests of the same priority are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level,
there is a second priority structure determined by the
polling sequence. This second priority structure is shown
in Table 60.
2. The current machine cycle is not the final cycle in the
execution of the instruction in progress. (No interrupt
request will be serviced until the instruction in progress
is completed.).
3. The instruction in progress is RETI or any access to
the interrupt priority or interrupt enable registers.
(No interrupt will be serviced after RETI or after a read
or write to IP0, IP1, IE0, or IE1 until at least one other
instruction has been subsequently executed.).
14.4 Interrupt vectors
The polling cycle is repeated every machine cycle, and the
values polled are the values present at S5P2 of the
previous machine cycle. Note that if an interrupt flag is
active but is not being responded to because of one of the
above conditions, and if the flag is inactive when the
blocking condition is removed, then the blocked interrupt
will not be serviced. Thus, the fact that the interrupt flag
was once active but not serviced is not remembered.
Every polling cycle is new.
The vector indicates the Program Memory location where
the appropriate interrupt service routine starts; Table 60.
Table 60 Interrupt vectors and priority structure
VECTOR
SOURCE
External 0
Serial I/O: SIO1 (I2C-bus)
ADC completion
Timer 0 overflow
T2 capture 0
SYMBOL(1) ADDRESS
(HEX)
X0 (highest)
S1
0003
002B
0053
000B
0033
005B
0013
0033
0063
001B
0043
006B
0023
004B
0073
The processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate
service routine. In some cases it also clears the flag which
generated the interrupt, and in others it does not. It clears
the Timer 0, Timer 1, and external interrupt flags.
An external interrupt flag (IE0 or IE1) is cleared only if it
was transition-activated. All other interrupt flags are not
cleared by hardware and must be cleared by the software.
ADC
T0
CT0
T2 compare 0
CM0
External 1/ seconds interrupt X1/SEC
T2 capture 1
CT1
The LCALL pushes the contents of the program counter on
to the stack (but it does not save the PSW) and reloads the
PC with an address that depends on the source of the
interrupt being vectored to as shown in Table 60.
T2 compare 1
Timer 1 overflow
T2 capture 2
CM1
T1
CT2
Execution proceeds from the vector address until the RETI
instruction is encountered. The RETI instruction clears the
‘priority level active’ flip-flop that was set when this
interrupt was acknowledged. It then pops the top two bytes
from the stack and reloads the program counter. Execution
of the interrupted program continues from where it was
interrupted.
T2 compare 2
Serial I/O SIO0 (UART)
T2 capture 3
CM2
S0
CT3
T2 overflow
T2 (lowest)
Note
1. X0 has the highest priority; T2 the lowest.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
interrupt enable registers
source enable global enable
interrupt
sources
interrupt priority
registers
polling hardware
EXTERNAL
INTERRUPT
REQUEST 0
INT0
a1
a2
b1
b2
c1
c2
d1
d2
e1
e2
f1
a1
b1
c1
d1
e1
f1
2
I C-BUS
SERIAL
PORT
ADC
g1
h1
i1
high
TIMER 0
OVERFLOW
priority
interrupt
request
j1
CT0I
TIMER 2
CAPTURE 0
k1
l1
m1
n1
o1
TIMER 2
COMPARE 0
f2
EXTERNAL
INTERRUPT
REQUEST 1
INT1
CT1I
g1
g2
h1
h2
i1
vector
SOURCE
IDENTIFICATION
TIMER 2
CAPTURE 1
a2
b2
c2
d2
e2
f2
TIMER 2
COMPARE 1
i2
j1
TIMER 1
OVERFLOW
j2
CT2I
k1
k2
l1
TIMER 2
CAPTURE 2
g2
h2
i2
low
priority
interrupt
request
TIMER 2
COMPARE 2
j2
l2
k2
l2
UART
SERIAL
PORT
T
m1
m2
n1
n2
o1
o2
R
m2
n2
o2
CT3I
TIMER 2
CAPTURE 3
vector
TIMER T2
OVERFLOW
SOURCE
IDENTIFICATION
MBC754
Fig.14 Interrupt system.
42
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
14.5 Interrupt Enable and Priority Registers
14.5.1 INTERRUPT ENABLE REGISTER 0 (IEN0)
Logic 0 = interrupt disabled; logic 1 = interrupt enabled.
Table 61 Interrupt Enable Register 0 (address A8H)
7
6
5
4
3
2
1
0
EA
EAD
ES1
ES0
ET1
EX1
ET0
EX0
Table 62 Description of IEN0 bits
BIT
SYMBOL
DESCRIPTION
7
EA
General enable/disable control. If bit EA is:
LOW, then no interrupt is enabled.
HIGH, then any individually enabled interrupt will be accepted.
Enable ADC interrupt.
Enable SIO1 (I2C-bus) interrupt.
6
5
4
3
2
1
0
EAD
ES1
ES0
ET1
EX1
ET0
EX0
Enable SIO0 (UART) interrupt.
Enable Timer 1 interrupt.
Enable External 1 interrupt / Seconds interrupt.
Enable Timer 0 interrupt.
Enable External 0 interrupt.
14.5.2 INTERRUPT ENABLE REGISTER 1 (IEN1)
Logic 0 = interrupt disabled; logic 1 = interrupt enabled.
Table 63 Interrupt Enable Register 1 (address E8H)
7
6
5
4
3
2
1
0
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
Table 64 Description of IEN1 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
ET2
Enable T2 overflow interrupt(s).
ECM2
ECM1
ECM0
ECT3
ECT1
ECT1
ECT0
Enable T2 comparator 2 interrupt.
Enable T2 comparator 1 interrupt.
Enable T2 comparator 0 interrupt.
Enable T2 capture register 3 interrupt.
Enable T2 capture register 2 interrupt.
Enable T2 capture register 1 interrupt.
Enable T2 capture register 0 interrupt.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
14.5.3 INTERRUPT PRIORITY REGISTER 0 (IP0)
Logic 0 = low priority; logic 1 = high priority.
Table 65 Interrupt Priority Register 0 (address B8H)
7
6
5
4
3
2
1
0
−
PAD
PS1
PS0
PT1
PX1
PT0
PX0
Table 66 Description of IP0 bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
Reserved for future use.
PAD
PS1
PS0
PT1
PX1
PT0
PX0
ADC interrupt priority level.
SIO1 (I2C-bus) interrupt priority level.
SIO0 (UART) interrupt priority level.
Timer 1 interrupt priority level.
External interrupt 1/Seconds priority level.
Timer 0 interrupt priority level.
External interrupt 0 priority level.
14.5.4 INTERRUPT PRIORITY REGISTER 1 (IP1)
Logic 0 = low priority; logic 1 = high priority.
Table 67 Interrupt Priority Register 1 (address F8H)
7
6
5
4
3
2
1
0
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
Table 68 Description of IP1 bits
BIT
SYMBOL
DESCRIPTION
T2 overflow interrupt(s) priority level.
7
6
5
4
3
2
1
0
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
T2 comparator 2 priority interrupt level.
T2 comparator 1 priority interrupt level.
T2 comparator 0 priority interrupt level.
T2 capture register 3 priority interrupt level.
T2 capture register 2 priority interrupt level.
T2 capture register 1 priority interrupt level.
T2 capture register 0 priority interrupt level.
1999 Mar 12
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Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
When Idle mode is terminated by an interrupt, the
15 REDUCED POWER MODES
service routine can examine the status of the flag bits.
Two software-selectable modes of reduced power
consumption are implemented: Idle and Power-down
mode. These modes are activated by software via SFR
PCON.
• The second way of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 HF oscillator periods) to
complete the reset operation if the HF oscillator is
selected.
15.1 Idle mode
Idle mode operation permits the interrupt, serial ports and
timer blocks T0, T1 and T3 to function while the CPU is
halted. The functions that are switched off when the
microcontroller enters the Idle mode are:
When the PLL oscillator is selected a hardware reset of
≥ 1 µs (but no longer than 10 ms) is required and the
microcontroller will typically restart within 63 ms after the
reset has finished.
• CPU (halted)
• The third way of terminating the Idle mode is by internal
watchdog reset. The microcontroller restarts after three
machine cycles in all cases.
• Timer 2 (stopped and reset)
• PWM0, PWM1 (reset, output = HIGH)
• ADC (aborted if conversion in progress).
15.2 Power-down mode
The functions that remain active during Idle mode may
generate an interrupt or reset and thus terminate the
Idle mode. These functions are:
In Power-down mode the system clock is halted. If the PLL
oscillator is selected (SELXTAL1 = 0) and the RUN32 bit
is set, the 32 kHz oscillator keeps running, otherwise it is
stopped. If the HF oscillator (SELXTAL1 = 1) is selected,
it is stopped after setting the bit PD in the PCON register.
• Timer 0, Timer 1, Timer 3 (Watchdog Timer)
• UART
• I2C
The instruction that sets PCON.1 is the last executed prior
to going into the Power-down mode. Once in
Power-down mode, the HF oscillator is stopped.
The 32 kHz oscillator may remain active. The contents of
the on-chip RAM and the Special Function Registers are
preserved.
• External interrupt
• Seconds timer.
The instruction that sets PCON.0 is the last instruction
executed in the normal operating mode before Idle mode
is activated.
Note that the Power-down mode can not be entered when
the Watchdog Timer has been enabled.
Once in the Idle mode, the CPU status is preserved in its
entirety: the Stack Pointer, Program Counter, Program
Status Word, Accumulator, RAM and all other registers
maintain their data during Idle mode. The status of
external pins during Idle mode is shown in Table 69.
The Power-down mode can be terminated by an external
reset in the same way as in the 80C51 (RAM is saved, but
SFRs are cleared due to reset) or in addition by any one of
the external interrupts (INT0, INT1) or Seconds interrupt.
There are three ways to terminate the Idle mode:
The status of the external pins during Power-down mode
is shown in Table 69. If the Power-down mode is activated
while in external Program Memory, the port data that is
held in the Special Function Register P2 is restored to
Port 2. If the data is a logic 1, the port pin is held HIGH
during the Power-down mode by the strong pull-up
transistor P1 (see Fig.8).
• Activation of any enabled interrupt X0, T0, X1, SEC, T1,
S0 or S1 will cause PCON.0 to be cleared by hardware
terminating Idle mode but only, if there is no interrupt in
service with the same or higher priority. The interrupt is
serviced, and following return from interrupt instruction
RETI, the next instruction to be executed will be the one
which follows the instruction that wrote a logic 1 to
PCON.0.
The Power-down mode should not be entered within an
interrupt routine because Wake-up with an external or
‘Seconds’ interrupt is not possible in that case.
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during Idle mode.
For example, the instruction that writes to PCON.0 can
also set or clear one or both flag bits.
1999 Mar 12
45
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
To terminate the Power-down mode with an external
15.3 Wake-up from Power-down mode
interrupt, INT0 or INT1 must be switched to be
level-sensitive and must be enabled. The external interrupt
input signal INT0 or INT1 must be kept LOW till the
oscillator has restarted and stabilized (see Fig.15).
A Seconds interrupt will terminate the Power-down mode
if it is enabled and INT1 is level sensitive. In order to
prevent any interrupt priority problems during Wake-up,
the priority of the desired Wake-up interrupt should be
higher than the priorities of all other enabled interrupt
sources.
The Power-down mode of the P8xC557E8 can also be
terminated by any one of the three enabled interrupts,
INT0, INT1 or Seconds interrupt.
If there is an interrupt already in service, which has same
or higher priority than the Wake-up interrupt,
Power-down mode will switch over to Idle mode and stay
there until an interrupt of higher priority terminates
Idle mode.
A termination with these interrupts does not affect the
internal Data Memory and does not affect the Special
Function Registers. This gives the possibility to exit
Power-down without changing the port output levels.
The instruction following the one that put the device into
the Power-down mode will be the first one which will be
executed after the interrupt routine has been serviced.
15.4 Status of external pins
Table 69 Status of external pins during Idle and Power-down modes
PWM0/
PWM1
MODE
Idle
MEMORY ALE PSEN
PORT0 PORT1 PORT2 PORT3 PORT4 SCL/ SDA
internal
external
1
1
0
0
1
1
0
0
1
1
1
1
port data port data port data port data port data operative(1)
high-Z
port data port data port data port data port data
high-Z port data port data port data port data
port data address port data port data operative(1)
Power-down internal
external
high-Z
high-Z
Note
1. In Idle mode SCL and SDA can be active as outputs only if SIO1 is enabled; if SIO1 is disabled (S1CON.6/ENS1 = 0)
these pins are in a high-impedance state.
internal timing stopped
Power-down mode
C1
C1
C1
C2
LCALL
Idle mode
oscillator start-up time
interrupts are polled
interrupt routine
XTAL1, 2 oscillator stopped
>
560 ms
32 kHz oscillator stopped
32 kHz oscillator running
>
10 ms
INT0
INT1
MBH083
set external interrupt latch
Fig.15 Wake-up by interrupt.
46
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
XTAL3
XTAL3
SELXTAL1
32 kHz
PLL
OCSILLATOR
interrupts,
serial
f
clk
CLOCK
'second'
timer
ports
T0, T1, T3
GENERATOR
CPU
T2
ADC
PWM
OCSILLATOR
PD
IDL
3.5 to 16 kHz
XTAL2
XTAL1
MBH082
Fig.16 Idle and Power-down hardware for clock generation.
15.5 Power Control Register (PCON)
PCON is not bit addressable and the value after reset is 00H.
Table 70 Power Control Register (address 87H)
7
6
5
4
3
2
1
0
SMOD
ARD
RFI
WLE
GF1
GF0
PD
IDL
Table 71 Description of PCON bits
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double Baud rate. When set to logic 1 the baud rate is doubled when the serial port
SIO0 is being used in Modes 1, 2 and 3.
6
5
ARD
RFI
AUX-RAM disable. When set to logic 1 the internal 1792 bytes AUX-RAM is disabled,
so that all MOVX-Instructions access the external Data Memory - as it is with the
standard 80C51.
RFI-Reduction Mode. When set to HIGH the toggling of ALE pin is prohibited. This bit
is cleared on reset and can be set and cleared by software. When set, ALE pin will be
pulled down internally, switching an external address latch to a quiet state. See also
Sections 2.1 and 6.2.
4
WLE
Watchdog Load Enable. This flag must be set by software prior to loading T3
(Watchdog Timer). It is cleared when T3 is loaded.
3
2
1
GF1
GF0
PD
General purpose flag bits.
Power-down mode select. Setting this bit activates Power-down mode. It can only be
set if input EW is HIGH.
0
IDL
Idle mode select. Setting this bit activates the Idle mode.
1999 Mar 12
47
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
16 OSCILLATOR CIRCUITS
16.2.2 PLL CURRENT CONTROLLED OSCILLATOR
A Current Controlled Oscillator (CCO) generates a clock
frequency fCCO of approximately 32, 38, 44 or 50 MHz.
This CCO is controlled by the PLL, with the 32 kHz
oscillator as the reference clock.
16.1 XTAL1; XTAL2 oscillator: standard 80C51
The XTAL1; XTAL2 oscillator: standard 80C51 is selected
when input SELXTAL1 = 1. The oscillator circuit is a
single-stage inverting amplifier in a Pierce oscillator
configuration. The circuitry between pins XTAL1 and
XTAL2 is basically an inverter biased to the transfer point.
Either a crystal or ceramic resonator can be used as the
feedback element to complete the oscillator circuitry. Both
are operated in parallel resonance.
The system clock frequency fclk is derived from fCCO and
can be varied under software control by changing the
contents of the PLL Control Register (PLLCON) bits
FSEL.4 to FSEL.0. The CCO frequency fCCO can be
changed via the PLLCON bits FSEL.1 and FSEL.0 and the
maximum locking time is 10 ms (this parameter is
characterized). During the stabilization phase, no time
critical routines should be executed.
XTAL1 is the high gain amplifier input, and XTAL2 is the
output; see Fig.17. To drive the P8xC557E8 externally,
XTAL1 is driven from an external source and XTAL2 is left
open-circuit; see Fig.18.
Changing fclk has to be done in two steps:
• From high to low frequencies; first change
FSEL.4 to FSEL.2, then FSEL.1 to FSEL.0
When the ‘XTAL1; XTAL2 oscillator’ is selected the
‘XTAL3; XTAL4 oscillator’ is halted; pins XTAL3 and
XTAL4 must not be connected.
• From low to high frequencies; first change
FSEL.1 to FSEL.0 only, and after a stabilization phase
of 10 ms, change FSEL.4 to FSEL.2.
16.2 XTAL3; XTAL4 oscillator: 32 kHz PLL oscillator
(with Seconds timer)
If only FSEL.4 to FSEL.2 is changed, and FSEL.1 to
FSEL.0 not, then it takes approximately 1 µs until the new
frequency is available. The frequency selection is shown in
Table 73.
The XTAL3; XTAL4 oscillator: 32 kHz oscillator and the
Phase Locked Loop (PLL) are selected when
SELXTAL1 = 0 (XTAL1; XTAL2 oscillator is halted). In this
case pin XTAL2 is kept floating.
16.2.3 PLL CONTROL REGISTER (PLLCON)
16.2.1 32 KHZ OSCILLATOR
PLLCON is a Special Function Register, which can be
read and written by software. It contains the control bits:
The 32 kHz oscillator consists of an inverter, which forms
a Pierce oscillator with the on-chip components C1, C2, Rf
and an external crystal of 32768 Hz. The inverter is
• to select the system clock frequencies (fclk)
• the seconds interrupt flag (SECINT)
switched to 3-state and pin XTAL3 is pulled to VSS
:
• to enable the seconds interrupt flag (ENSECI)
• During Power-down mode, when RUN32
• the RUN32 bit, which defines if during Power-down
(PLLCON.7) = 0
mode the 32 kHz oscillator is halted or not.
• During reset, RSTIN = 1
PLLCON is initialized to 0DH upon reset (RSTIN = 1) or
Watchdog Timer overflow. PLLCON = 0DH corresponds
to a system clock frequency fclk = 11.01 MHz.
• When the XTAL1; XTAL2 oscillator is selected
(SELXTAL1 = 1).
1999 Mar 12
48
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 72 PLL Control Register (address F9H)
7
6
5
4
3
2
1
0
RUN32
ENSECI
SECINT
FSEL.4
FSEL.3
FSEL.2
FSEL.1
FSEL.0
Table 73 Description of PLLCON bits
BIT
SYMBOL
DESCRIPTION
7
RUN32
If RUN32 = 0, then the 32 kHz oscillator is halted during Power-down
mode. If RUN32 = 1, then the 32 kHz oscillator remains active during
Power-down mode.
6
5
ENSECI
SECINT
Enable the seconds interrupt; enabling INT1 is also required.
Seconds interrupt requested by an overflow of the seconds timer (which
occurs every second) or via writing a logic 1 to this bit. SECINT can only
be cleared by writing a logic 0 to this bit.
4 to 0
FSEL.4 to FSEL.0
System clock frequency selection bits; see Table 74.
Table 74 System clock frequency (fclk) selection
Other combinations than mentioned in this table, are reserved and may not be selected. This allows to generate the
standard baudrates 19200, 9600, 4800, 2400 and 1200 Baud, when using the UART and Timer 1.
FSEL.4
FSEL.3
FSEL.2
FSEL.1
FSEL.0
fCLK (MHz)
1
0
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
3.93
7.86
15.73
4.72
9.44
5.51
11.01
6.29
12.58
handbook, halfpage
handbook, halfpage
SELXTAL1
XTAL1
HIGH
SELXTAL1
XTAL1
HIGH
external
clock
signal
C1
quartz crystal
or ceramic
resonator
C2
n.c.
XTAL2
XTAL2
C1 = C2 = 20 pF
V
V
SS
SS
MBH085
MBH084
Fig.17 Using the on-chip oscillator.
Fig.18 Using an external clock.
1999 Mar 12
49
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
It controls the stretching of the reset pulse to the
16.2.4
SECONDS TIMER
microcontroller and controls releasing the system clock to
the microcontroller. A RSTIN signal of 1 µs at minimum will
reset the microcontroller.
This counter provides an overflow signal every second,
when the 32 kHz oscillator is running. The overflow output
sets the interrupt flag SECINT. This interrupt can be
disabled/enabled by ENSECI. If SECINT is enabled, it is
logically ORed with INT1 (External interrupt 1).
The ‘seconds’ interrupt and INT1 therefore share the same
priority and vector. The software has to check both flags
SECINT (PLLCON.5) and IE1 (TCON.3) to distinguish
between the two interrupt sources. SECINT can only be
cleared via writing a logic 0 to this bit.
• In the even of reset or wake-up with halted 32 kHz
oscillator: from RSTIN falling edge or wake-up interrupt
it takes 560 ms at maximum for the start-up of the
32 kHz oscillator itself and the stabilization of the PLLs.
• In the event of wake-up with running 32 kHz oscillator:
from wake-up interrupt it takes about 10 ms for the
stabilization of the PLLs.
The external interrupts INT0, INT1 or the seconds interrupt
can wake-up the PLL oscillator and the microcontroller as
described in Chapter 15.3. For a wake-up via INT1 or
seconds interrupt, IE1 must be enabled and
level-sensitive.
After this start-up time, the microcontroller is supplied with
the system clock and - in case of a reset - the internally
stretched reset signal overlaps about 45 µs, to guarantee
a proper initialization of the microcontroller.
For further information refer to Chapter 15.
A further function of the seconds timer is to control the
start-up timing of the microcontroller after reset or after
wake-up from Power-down.
32.768 kHz
C1
C2
R
f
PD
XTAL4
XTAL3
32 kHz
OCSILLATOR
PHASE
COMPARATOR FILTER
LOOP
CCO
PROGRAMMABLE
DIVIDER
system
clock
PD
reset to
RUN32
controller
SECONDS TIMER
PLLCON
'seconds'
interrupt
request
RSTIN
INTERNAL BUS
MBH086
Fig.19 Block diagram PLL.
1999 Mar 12
50
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
A reset leaves the internal registers as shown in
17 RESET CIRCUITRY
Chapter 18. The internal RAM is not affected by reset.
At power-on, the RAM content is indeterminate.
The reset input pin RSTIN is connected to a Schmitt
Trigger for noise reduction (see Fig.20). If the HF oscillator
is selected, a reset is accomplished by holding the RSTIN
pin HIGH for at least 2 machine cycles (24 system clock
periods). If the PLL oscillator is selected the RSTIN pulse
must have a width of at least 1 µs, independent of the
32 kHz-oscillator running or not (see PLL description).
The CPU responds by executing an internal reset.
The RSTOUT pin represents the signal resetting the CPU
and can be used to reset peripheral devices.
17.1 Power-on-reset
An automatic reset can be obtained by switching on VDD
if the RSTIN pin is connected to VDD via a capacitor, as
shown in Figure 21. Is the HF oscillator selected the VDD
rise time must not exceed 10 ms and the capacitor should
be at least 2.2 µF. The decrease of the RSTIN pin voltage
,
depends on the capacitor and the internal resistor RRST
.
That voltage must remain above the lower threshold for at
minimum the HF oscillator start-up time plus 2 machine
cycles. If the PLL oscillator is selected, a 0.1 µF capacitor
is sufficient to obtain an automatic reset.
The RSTOUT level also could be high due to a Watchdog
timer overflow.The length of the output pulse from T3 is
three machine cycles. A pulse of such short duration is
necessary in order to recover from a processor or system
fault as fast as possible. During reset, ALE and PSEN
output a HIGH level. In order to perform a correct reset,
this level must not be affected by external elements.
PLL
OSCILLATOR
Schmitt
trigger
internal
reset
RSTIN
MUX
RSTOUT
on-chip
resistor
R
RST
overflow
timer T3
SELXTAL1
MBH087
Fig.20 On-chip reset configuration.
V
DD
handbook, halfpage
V
DD
(1)
C
P8xC557E8
RSTIN
R
RST
MHI026
Fig.21 Power-on-reset.
51
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
18 SPECIAL FUNCTION REGISTERS OVERVIEW
The P8xC557E8 has 67 SFRs available to the user.
ADDRESS
(HEX)
RESET VALUE
(B)
NAME
FUNCTION
FF
FE
FD
FC
FA
F9
T3(1)
XXXX0000
00000000
00000000
00000000
XXXXX000
00001101
00000000
000000XX
XXXXXXXX
00000000
00000000
11000000
00000000
00000000
00000000
00000000
00000000
00000000
XXXXXXXX
00000000
XXXXXXXX
XXXXXXXX
00001100
00000000
XX000000
XXXXXXXX
00000000
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
00000000
00000000
00000000
11111111
Watchdog Timer
PWMP(1)
PWM1(1)
PWM0(1)
XRAMP(1)
PLLCON(1)
IP1(1)
ADRSH(1)
ADRSL7
B(2)
Prescaler Frequency Control Register
Pulse Width Register 1
Pulse Width Register 0
AUX-RAM Page Register
PLL Control Register
F8
Interrupt Priority Register 1
ADC Result Register High Byte
ADC Result Register Low Byte
B Register
F7
F6
F0
EF
EE
ED
EC
EB
EA
E8
E7
E6
E0
DB
DA
D9
D8
D7
D6
D0
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
C0
RTE(2)
STE(2)
Reset/Toggle Enable Register
Set Enable Register
TMH2(2)
TML2(2)
CTCON(2)
TM2CON(2)
IEN1(2)
ADPSS
ADRSL6
ACC(2)
T2 Register High Byte
T2 Register Low Byte
Capture Control Register
T2 Control Register
Interrupt Enable Register 1
ADC Input Port Scan-Select Register
ADC Result Register Low Byte
Accumulator
S1ADR
S1DAT
S1STA
S1CON
ADCON
ADRSL5
PSW(2)
CTH3
Address Register
Data Shift Register
Serial Status Register
The Serial Control Register
ADC Control Register
ADC Result Register Low Byte
Program Status Word
T2 Capture Register 3 High Byte
T2 Capture Register 2 High Byte
T2 Capture Register 1 High Byte
T2 Capture Register 0 High Byte
T2 Compare Register 2 High Byte
T2 Compare Register 1 High Byte
T2 Compare Register 0 High Byte
Interrupt Flag Register
CTH2
CTH1
CTH0
CMH2
CMH1
CMH0
TM2IR(2)
P5(1)
Digital Input Port Register
ADC Result Register Low Byte
Digital Input Port Register
ADRSL4
P4(1)(2)
XXXXXXXX
11111111
1999 Mar 12
52
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
ADDRESS
NAME
RESET VALUE
(B)
FUNCTION
Interrupt Priority Register 0
(HEX)
B8
B6
B0
AF
AE
AD
AC
AB
AA
A9
A8
A6
A0
99
98
96
90
8D
8C
8B
8A
89
88
87
86
83
82
81
80
IP0(2)
XXX00000
XXXXXXXX
11111111
ADRSL3
P3(1)(2)
CTL3(2)
CTL2(2)
CTL1(2)
CTL0(2)
CML2(2)
CML1(2)
CML0(2)
IEN0(2)
ADRSL2
P2
ADC Result Register Low Byte
Digital Input Port Register
T2 Capture Register 3 Low Byte
T2 Capture Register 2 Low Byte
T2 Capture Register 1 Low Byte
T2 Capture Register 0 Low Byte
T2 Compare Register 2 Low Byte
T2 Compare Register 1 Low Byte
T2 Compare Register 0 Low Byte
Interrupt Enable Register 0
ADC Result Register Low Byte
Digital Input Port Register
Serial Data Buffer Register 0
Serial Port Control Register 0
ADC Result Register Low Byte
Digital Input Port Register
Timer 1 High byte
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
00000000
00000000
00000000
XXXXXXXX
11111111
S0BUF(1)
S0CON(1)
ADRSL1
P1
XXXXXXXX
00000000
XXXXXXXX
11111111
TH1
00000000
00000000
0000000
TH0
Timer 0 High byte
TL1
Timer 1 Low byte
TL0
00000000
XX00XX00
0000X000
XXXX0000
XXXXXXXX
00000000
00000000
00000111
11111111
Timer 0 Low byte
TMOD
TCON(2)
PCON
ADRSL0
DPH
Timer 0 and 1 Mode Control Register
Timer 0 and 1 Control/External Interrupt Control Register
Power Control Register
ADC Result Register Low Byte
Data Pointer High byte
DPL
Data Pointer Low byte
SP
Stack Pointer
P0
Digital Input Port Register
Notes
1. P8xC557E8 specific SFRs.
2. Bit addressable register.
1999 Mar 12
53
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
19 INSTRUCTION SET
19.2 80C51 family instruction set
The P8xC557E8 uses the powerful instruction set of the
PCB80C51. It consists of 49 single byte, 45 two byte and
17 three byte instructions. Using a 16 MHz crystal, 64 of
the instructions are executed in 0.75 µs, 45 in 1,5 µs and
the multiply, divide instructions in 3 µs.
Table 75 Instructions that affect flag settings; note 1
FLAG(2)
INSTRUCTION
C
OV
AC
ADD
X
X
X
0
X
X
X
X
X
X
X
X
X
A summary of the instruction set is given in
Tables 76, 77, 78, 79 and 80.
ADDC
SUBB
The P8xC557E8 has additional Special Function
Registers to control the on-chip peripherals.
MUL
DIV
0
DA
X
X
X
1
19.1 Addressing modes
RRC
Most instructions have a ‘destination, source’ field that
specifies the data type, addressing modes and operands
involved. For all these instructions, except for MOVs, the
destination operand is also the source operand
(e.g. ADD A,R7).
RLC
SETB C
CLR C
CPL C
ANL C, bit
ANL C,/bit
ORL C, bit
ORL C,/bit
MOV C, bit
CJNE
0
X
X
X
X
X
X
X
There are five kinds of addressing modes:
• Register Addressing
– R0 to R7 (4 banks)
– A,B,C (bit), AB (2 bytes), DPTR (double byte)
• Direct Addressing
– lower 128 bytes of internal main RAM (including the
four R0 to R7 register banks)
Note
– Special Function Registers
1. Note that operations on SFR byte address 208 or bit
addresses 209 to 215 (i.e. the PSW or bits in the
PSW) will also affect flag settings.
– 128 bits in a subset of the internal main RAM
– 128 bits in a subset of the Special Function Registers
• Register-Indirect Addressing
2. X = don’t care.
– internal main RAM (@R0, @R1, @SP [PUSH/POP])
– internal auxiliary RAM (@R0, @R1, @DPTR)
– external Data Memory (@R0, @R1, @DPTR)
• Immediate Addressing
– Program Memory (in-code 8 bit or 16 bit constant)
• Base-Register-plus-Index-Register-Indirect Addressing
– Program Memory look-up table
(@DPTR+A, @PC+A).
The first three addressing modes are usable for
destination operands.
1999 Mar 12
54
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
19.3 Instruction set description
For the description of the Data Addressing Modes and Hexadecimal opcode cross-reference see Table 80.
Table 76 Instruction set description: Arithmetic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Arithmetic operations
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
A,Rr
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
2*
A,direct
A,@Ri
A,#data
A,Rr
Add direct byte to A
25
Add indirect RAM to A
26, 27
24
Add immediate data to A
Add register to A with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment A
3*
A,direct
A,@Ri
A,#data
A,Rr
35
36, 37
34
9*
A,direct
A,@Ri
A,#data
A
95
96, 97
94
04
INC
Rr
Increment register
0*
INC
direct
@Ri
Increment direct byte
05
INC
Increment indirect RAM
Decrement A
06, 07
14
DEC
DEC
DEC
DEC
INC
A
Rr
Decrement register
1*
direct
@Ri
Decrement direct byte
15
Decrement indirect RAM
Increment data pointer
16, 17
A3
DPTR
AB
MUL
DIV
Multiply A and B
A4
AB
Divide A by B
84
DA
A
Decimal adjust A
D4
1999 Mar 12
55
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 77 Instruction set description: Logic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Logic operations
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A,Rr
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
5*
A,direct
A,@Ri
A,#data
direct,A
AND direct byte to A
AND indirect RAM to A
AND immediate data to A
AND A to direct byte
55
56, 57
54
52
direct,#data AND immediate data to direct byte
53
A,Rr
OR register to A
4*
A,direct
A,@Ri
A,#data
direct,A
OR direct byte to A
OR indirect RAM to A
OR immediate data to A
OR A to direct byte
45
46, 47
44
42
direct,#data OR immediate data to direct byte
43
A,Rr
Exclusive-OR register to A
6*
A,direct
A,@Ri
A,#data
direct,A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR A to direct byte
65
66, 67
64
62
direct,#data Exclusive-OR immediate data to direct byte
63
A
A
A
A
A
A
A
Clear A
E4
F4
Complement A
Rotate A left
23
RLC
RR
Rotate A left through the carry flag
Rotate A right
33
03
RRC
SWAP
Rotate A right through the carry flag
Swap nibbles within A
13
C4
1999 Mar 12
56
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 78 Instruction set description: Data transfer
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Data transfer
A,Rr
A,direct (note 1) Move direct byte to A
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
Move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E*
E5
A,@Ri
Move indirect RAM to A
E6, E7
74
A,#data
Move immediate data to A
Move A to register
Rr,A
F*
Rr,direct
Rr,#data
direct,A
Move direct byte to register
Move immediate data to register
Move A to direct byte
A*
7*
F5
direct,Rr
direct,direct
direct,@Ri
direct,#data
@Ri,A
Move register to direct byte
Move direct byte to direct
8*
85
Move indirect RAM to direct byte
Move immediate data to direct byte
Move A to indirect RAM
86, 87
75
F6, F7
A6, A7
76, 77
90
@Ri,direct
@Ri,#data
Move direct byte to indirect RAM
Move immediate data to indirect RAM
DPTR,#data 16 Load data pointer with a 16-bit constant
A,@A+DPTR
A,@A+PC
A,@Ri
Move code byte relative to DPTR to A
Move code byte relative to PC to A
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
Move A to external RAM (8-bit address)
Move A to external RAM (16-bit address)
Push direct byte onto stack
93
83
E2, E3
E0
A,@DPTR
@Ri,A
F2, F3
F0
@DPTR,A
direct
C0
direct
Pop direct byte from stack
D0
XCH
A,Rr
Exchange register with A
C*
XCH
A,direct
A,@Ri
Exchange direct byte with A
C5
XCH
Exchange indirect RAM with A
C6, C7
D6, D7
XCHD
A,@Ri
Exchange LOW-order digit indirect RAM with A
Note
1. MOV A,ACC is not permitted.
1999 Mar 12
57
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 79 Instruction set description: Boolean variable manipulation, Program and machine control
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Boolean variable manipulation
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
Clear carry flag
Clear direct bit
Set carry flag
Set direct bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3
bit
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
C
bit
C
Complement carry flag
bit
Complement direct bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
AND direct bit to carry flag
AND complement of direct bit to carry flag
OR direct bit to carry flag
OR complement of direct bit to carry flag
Move direct bit to carry flag
Move carry flag to direct bit
Program and machine control
ACALL
LCALL
RET
addr11
addr16
Absolute subroutine call
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
•1
Long subroutine call
12
22
32
♦ 1
02
80
73
60
70
40
50
20
30
10
B5
B4
B*
Return from subroutine
RETI
AJMP
LJMP
SJMP
JMP
Return from interrupt
addr11
addr16
rel
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if A is zero
@A+DPTR
rel
JZ
JNZ
rel
Jump if A is not zero
JC
rel
Jump if carry flag is set
JNC
rel
Jump if carry flag is not set
Jump if direct bit is set
JB
bit,rel
JNB
bit,rel
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Compare direct to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to register and jump if not equal
JBC
bit,rel
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
A,direct,rel
A,#data,rel
Rr,#data,rel
@Ri,#data,rel Compare immediate to indirect and jump if not equal
B6, B7
D*
D5
00
Rr,rel
Decrement register and jump if not zero
Decrement direct and jump if not zero
No operation
direct,rel
1999 Mar 12
58
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 80 Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
Working register R0-R7.
128 internal RAM locations and any special function register (SFR).
direct
@Ri
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
8-bit constant included in instruction.
#data
#data 16
bit
16-bit constant included as bytes 2 and 3 of instruction.
Direct addressed bit in internal RAM or SFR.
addr16
16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 kbytes Program Memory address space.
addr11
rel
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction.
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is −128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
*
•
8, 9, A, B, C, D, E, F.
1, 3, 5, 7, 9, B, D, F.
0, 2, 4, 6, 8, A, C, E.
♦
1999 Mar 12
59
Table 81 Instruction map
First hexadecimal character of opcode
← Second hexadecimal character of opcode →
↓
0
1
2
3
4
5
6
0
0
7
1
1
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
1
1
1
1
1
1
1
1
1
1
1
A
2
2
B C D E
INC Rr
F
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
INC @Ri
DEC @Ri
AJMP
addr11
LJMP
addr16
RR
A
INC
A
INC
direct
0
NOP
3
4
5
6
6
6
6
6
6
6
6
6
6
6
DEC Rr
JBC
bit,rel
ACALL
addr11
LCALL
addr16
RRC
A
DEC
A
DEC
direct
1
2
3
4
5
ADD A,@Ri
ADD A,Rr
JB
bit,rel
AJMP
addr11
RL
A
ADD
A,#data
ADD
A,direct
RET
0
1
2
3
4
5
ADDC A,@Ri
ADDC A,Rr
JNB
bit,rel
ACALL
addr11
RLC
A
ADDC
A,#data
ADDC
A,direct
3
RETI
0
1
2
2
2
2
3
4
5
5
5
5
ORL A,@Ri
ANL A,@Ri
XRL A,@Ri
ORL A,Rr
JC
rel
AJMP
addr11
ORL
direct,A
ORL
direct,#data
ORL
A,#data
ORL
A,direct
4
0
0
0
1
1
1
3
4
ANL A,Rr
JNC
rel
ACALL
addr11
ANL
direct,A
ANL
direct,#data
ANL
A,#data
ANL
A,direct
5
3
4
XRL A,Rr
JZ
rel
AJMP
addr11
XRL
direct,A
XRL
direct,#data
XRL
A,#data
XRL
A,direct
6
3
4
MOV @Ri,#data
MOV Rr,#data
JNZ
rel
ACALL
addr11
ORL
C,bit
JMP
@A+DPTR
MOV
A,#data
MOV
direct,#data
7
0
1
2
3
4
5
MOV direct,@Ri
MOV direct,Rr
SJMP
rel
AJMP
addr11
ANL
C,bit
MOVC
A,@A+PC
DIV
AB
MOV
direct,direct
8
0
1
2
3
4
5
SUBB A,@Ri
SUB A,Rr
MOV
DTPR,#data16
ACALL
addr11
MOV
bit,C
MOVC
A,@A+DPTR
SUBB
A,#data
SUBB
A,direct
9
0
1
2
3
4
5
MOV @Ri,direct
MOV Rr,direct
ORL
C,/bit
AJMP
addr11
MOV
bit,C
INC
DPTR
MUL
AB
A
0
1
2
3
4
5
CJNE @Ri,#data,rel
CJNE Rr,#data,rel
ANL
C,/bit
ACALL
addr11
CPL
bit
CPL
C
CJNE
A,#data,rel
CJNE
A,direct,rel
B
0
1
1
1
1
1
1
2
3
4
5
6
6
6
6
6
XCH A,@Ri
XCH A,Rr
PUSH
direct
AJMP
addr11
CLR
bit
CLR
C
SWAP
A
XCH
A,direct
C
D
E
0
0
1
2
3
4
5
XCHD A,@Ri
DJNZ Rr,rel
POP
direct
ACALL
addr11
SETB
bit
SETB
C
DA
A
DJNZ
direct,rel
1
2
3
4
5
MOVX A,@Ri
MOV A,@Ri
MOV A,Rr
MOVX
A,@DTPR
AJMP
addr11
CLR
A
MOV
A,direct (1)
0
0
1
0
1
2
3
4
5
MOVX @Ri,A
MOV @Ri,A
MOV Rr,A
MOVX
@DTPR,A
ACALL
addr11
CPL
A
MOV
direct,A
F
1
0
1
2
3
4
5
Note
1. MOV A, ACC is not a valid instruction.
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
20 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); note 1
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
UNIT
voltage on VDD to VSS and SCL, SDA to VSS
input voltage on:
+6.5
V
VI
any other pin to VSS
−0.5
−0.5
−
VDD + 0.5
+13
V
EA/VPP to VSS
V
II, IO
Ptot
input/output current on any I/O pin
total power dissipation (note 2)
storage temperature range
operating ambient temperature range:
P8xC557E8EFB
±10
mA
W
°C
−
1.0
Tstg
Tamb
−65
+150
−40
+85
°C
Notes
1. The following applies to the Absolute Maximum Ratings:
a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any conditions other than those described
in the Chapters 21 and 22 of this specification is not implied.
b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging
effect of excessive static charge. However, its suggested that conventional precautions be taken to avoid
applying greater than the rated maxima.
c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect
to VSS unless otherwise noted.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on
device power consumption.
1999 Mar 12
61
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
21 DC CHARACTERISTICS
VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified;
Tamb = −40 to +85 °C for the P8xC557E8EFB; VDDA = 5 V ±10%; VSSA = 0 V.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply (digital part)
VDD
supply voltage
4.5
−
5.5
40
V
IDD
operating supply current
VDD = 5.5 V; notes 1 and 2
VDD = 5.5 V; notes 1 and 3
2 V < VDD < VDDmax; note 4
VDD = 5.5 V; note 17
mA
mA
µA
µA
IDD(ID)
IDD(PD)
supply current Idle mode
−
12
supply current Power-down mode
−
100
100
supply current Power-down mode;
32 kHz/PLL operation
−
Inputs
VIL
LOW level input voltage
(except EA, SCL, SDA)
−0.5
0.2VDD − 0.15 V
0.2VDD − 0.35 V
VIL1
VIL2
LOW level input voltage EA
−0.5
−0.5
LOW level input voltage
SCL and SDA; note 5
0.3VDD
V
VIH
VIH1
VIH2
IIL
HIGH level input voltage (except
XTAL1, RSTIN, SCL, SDA, ADEXS)
0.2VDD + 1.0 VDD + 0.5
0.7VDD + 0.1 VDD + 0.5
V
HIGH level input voltage
XTAL1, RSTIN, ADEXS
V
HIGH level input voltage
SCL and SDA; note 5
0.7VDD
6.0
V
LOW level input current
Ports 1, 2, 3 and 4
VIN = 0.45 V
note 6
−
−
−
−
−
−75
−750
±10
±10
±1
µA
µA
µA
µA
µA
ITL
input current HIGH-to-LOW
transition Ports 1, 2, 3 and 4
ILI1
ILI2
input leakage current
Port 0, EA, ADEXS, EW, SELXTAL1
0.45 V < VI < VDD
input leakage current SCL and SDA 0 V < VI < 6 V
0 V < VDD < 5.5 V
ILI3
input leakage current Port 5
0.45 V < VI < VDD
Outputs
VOL
LOW level output voltage
Ports 1, 2, 3 and 4
IOL = 1.6 mA; note 7
IOL = 3.2 mA; note 7
−
−
0.45
0.45
V
V
VOL1
LOW level output voltage
Port 0, ALE, PSEN, PWM0, PWM1,
RSTOUT
VOH
HIGH level output voltage
Ports 1, 2, 3 and 4
IOH = −60 µA
IOH = −25 µA
IOH = −10 µA
IOH = −800 µA
IOH = −300 µA
IOH = −80 µA
2.4
−
−
−
−
−
−
V
V
V
V
V
V
0.75VDD
0.9VDD
2.4
VOH1
HIGH level output voltage
Port 0 in external bus mode,
ALE, PSEN, PWM0, PWM1,
RSTOUT; note 8
0.75VDD
0.9VDD
1999 Mar 12
62
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
(20)
VHYS
hysteresis of Schmitt Trigger inputs
SCL and SDA (Fast Mode)
0.05VDD
−
V
RRST
CI/O
RST pull-down resistor
I/O pin capacitance
50
150
10
kΩ
test frequency = 1 MHz;
−
pF
T
amb = 25 °C
Supply (analog part)
VDDA supply voltage
IDDA
VDDA = VDD ± 0.2 V
4.5
5.5
1.2
V
supply current operating
Port 5 = 0 V to VDDA
notes 1 and 2
;
;
−
mA
supply current operating
32 kHz / PLL operation
Port 5 = 0 V to VDDA
notes 17 and 18
−
7.2
mA
IDDA(ID)
supply current Idle mode
notes 1 and 3
−
−
70
µA
supply current Idle mode
32 kHz / PLL operation
notes 17 and 18
6.0
mA
IDDA(PD)
supply current Power-down mode
2 V < VDD <VDD(max); note 4
VDD = 5.5 V; note 17
−
−
50
µA
µA
supply current Power-down mode
32 kHz/PLL operation
200
Analog inputs
Vin(A)
analog input voltage
V
V
−
SSA − 0.2
VDDA + 0.2
V
Vref(n)(A)
Vref(p)(A)
RREF
reference voltage
SSA − 0.2
−
V
VDDA + 0.2
50
V
resistance between
Vref(p)(A) and Vref(n)(A)
10
kΩ
CIA
DLe
ILe
analog input capacitance
differential non-linearity
integral non-linearity
offset error
−
−
−
−
−
−
−
−
15
pF
notes 9, 10 and 11
notes 9 and 12
notes 9 and 13
notes 9 and 14
notes 9 and 15
±1
LSB
LSB
LSB
%
±2
OSe
Ge
±2
gain error
±0.4
±3
Ae
absolute voltage error
channel-to-channel matching
crosstalk between P5 inputs
LSB
LSB
dB
Mctc
Ct
±1
0 to 100 kHz; note 16
−60
1999 Mar 12
63
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Notes to the DC characteristics
1. See Figs 22, 25 and 24 for IDD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with
tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD − 0.5 V; XTAL2, XTAL3 not connected;
Port 0 = EW = SCL = SDA = SELXTAL1 = VDD; EA = RSTIN = ADEXS = XTAL4 = VSS
.
3. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns;
VIL = VSS + 0.5 V; VIH = VDD − 0.5 V; XTAL2, XTAL3 not connected;
EA = RSTIN = Port 0 = EW = SCL = SDA = SELXTAL1 = VDD; ADEXS = XTAL4 = VSS
.
4. The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
Port 0 = EW = SCL = SDA = SELXTAL1 = VDD; EA = RSTIN = ADEXS = XTAL1 = XTAL4 = VSS
.
5. The input threshold voltage of SCL and SDA (SIO1) meets the I2C specification, so an input voltage below 0.3 VDD
will be recognized as a logic 0 while an input voltage above 0.7 VDD will be recognized as a logic 1.
6. Pins of Ports 1, 2, 3 and 4 source a transition current when they are being externally driven from HIGH to LOW.
The transition current reaches its maximum value when VIN is approximately 2 V.
7. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports 1, 3
and 4. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make
HIGH-to-LOW transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on
the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an
address latch with a Schmitt Trigger STROBE input.
8. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD
specification when the address bits are stabilizing.
9. Vref(n)(A) = 0 V; VDDA = 5.0 V, Vref(p)(A) = 5.12 V. VDD = 5.0 V, VSS = 0 V, ADC is monotonic with no missing codes.
Measurement by continuous conversion of Vin(A) = −20 mV to 5.12 V in steps of 0.5 mV, deriving parameters from
collected conversion results of ADC. ADC prescaler programmed according to the actual oscillator frequency,
resulting in a conversion time within the specified range for tADC (15 to 50 µs).
10. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width.
11. The ADC is monotonic; there are no missing codes.
12. The integral non-linearity (ILe) is the peak difference between the centre of the steps of the actual and the ideal
transfer curve after appropriate adjustment of gain and offset error.
13. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after
removing gain error), and a straight line which fits the ideal transfer curve. The offset error is constant at every point
of the actual transfer curve.
14. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after
removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point
on the transfer curve.
15. The absolute voltage error (Ae) is the maximum difference between the centre of the steps of the actual transfer curve
of the non-calibrated ADC and the ideal transfer curve.
16. This should be considered when both analog and digital signals are simultaneously input to Port 5.
17. The supply current with 32 kHz oscillator running and PLL operation (SELXTAL1 = 0) is measured with all output
pins disconnected; XTAL4 driven with tr = tf = 5 ns; VIL = VSS + 0.5 V; VIH = VDD − 0.5 V; XTAL2 not connected;
Port 0 = EW = SCL = SDA = VDD; EA = RSTIN = ADEXS = SELXTAL 1 = XTAL1 = VSS
.
18. Not 100% tested; sum of IDDA(ID) (PLL) and IDDA (HF-Oscillator).
19. The parameter meets the I2C-bus specification for standard-mode and fast-mode devices.
20. Not 100% tested.
1999 Mar 12
64
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
MBH089
50
handbook, halfpage
I
DD
(mA)
40
30
20
(1)
(2)
10
0
0
4
8
12
16
f (MHz)
For P8xC557E8 at VDD = 5.5 V:
(1) Maximum operating supply current (IDD).
(2) Maximum supply current Idle mode (IDD(ID)).
Fig.22 Supply current (IDD) as a function of frequency at XTAL1 (fclk).
1999 Mar 12
65
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
offset error OS
gain error G
1023
e
e
1022
1021
1020
1019
1018
(2)
code
out
7
6
5
4
3
2
1
0
(1)
(5)
(4)
(3)
7
1 LSB (ideal)
1
2
3
4
5
6
1018 1019 1020 1021 1022 1023 1024
(LSB
V
)
ideal
in(A)
offset error
OS
e
MGD634
Vref(p)(A) + Vref(n)(A)
-----------------------------------------------
1024
1LSBideal
=
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DLe).
(4) Integral non-linearity (ILe).
(5) Centre of a step of the actual transfer curve.
Fig.23 ADC conversion characteristic.
66
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
22 AC CHARACTERISTICS
VDD = 5 V ±10%; VSS = 0 V; Tamb = −40 °C to +85°C; CL = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other
outputs unless otherwise specified; tclk(min) = 1/fclk(max) (fclk(max) = maximum operating frequency); tclk(min) = 63 ns.
VARIABLE CLOCK
fclk = 12 MHz fclk = 16 MHz
fclk = 3.5 to 16 MHz
SYMBOL
PARAMETER
UNIT
MIN. MAX. MIN. MAX.
MIN.
MAX.
External Program Memory; see Fig.27
tLHLL
tAVLL
tLLAX
tLLIV
ALE pulse width
127
43
53
−
−
85
23
33
−
−
2tclk − 40
−
−
−
ns
address valid to ALE LOW
address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
−
−
t
t
clk − 40
clk − 30
ns
ns
−
−
234
−
150
−
−
4tclk − 100 ns
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
53
205
−
33
143
−
t
clk − 30
−
−
ns
ns
−
−
3tclk − 45
PSEN LOW to valid instruction in
input instruction hold after PSEN
input instruction float after PSEN
address to valid instruction in
PSEN LOW to address float
145
−
83
−
−
0
−
−
−
3tclk − 105 ns
0
0
−
ns
ns
−
59
312
10
−
38
208
10
tclk − 25
−
−
5tclk − 105 ns
−
−
10
ns
External Data Memory; see Fig.28
tRLRH
tWLWH
tAVLL
RD pulse width
400
400
43
48
−
−
275
275
23
28
−
−
6tclk − 100
6tclk − 100
−
−
−
−
ns
ns
ns
ns
WR pulse width
−
−
address valid to ALE LOW
address hold after ALE LOW
RD LOW to valid data in
data hold after RD
−
−
t
t
clk − 40
clk − 35
tLLAX
−
−
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
252
−
148
−
−
5tclk −165 ns
0
0
0
−
ns
ns
data float after RD
−
97
517
585
300
−
−
55
350
398
238
−
−
2tclk − 70
ALE LOW to valid data in
address to valid data in
ALE LOW to RD or WR LOW
address valid to RD or WR LOW
RD or WR HIGH to ALE HIGH
data valid to WR transition
data valid time WR HIGH
data hold after WR
−
−
−
8tclk − 150 ns
9tclk − 165 ns
−
−
−
200
203
43
33
433
33
−
138
120
23
13
288
13
−
3tclk − 50
4tclk − 130
3tclk + 50
ns
ns
ns
ns
ns
ns
ns
−
123
−
103
−
t
t
clk − 40
clk − 50
tclk + 40
−
−
−
0
−
−
7tclk − 150
clk − 50
−
−
t
RD LOW to address float
0
0
−
UART Timing - Shift Register Mode; see Fig.30
tXLXL
serial port clock cycle time
1.0
−
0.75
492
8
−
12tclk
−
−
−
−
µs
ns
ns
ns
tQVXH
tXHQX
tXHDX
tXHDV
output data setup to clock rising edge 700
SCL clock frequency 50
input data hold after clock rising edge 0
clock rising edge to input data valid
−
−
10tclk − 133
−
−
2tclk−117
−
0
−
0
−
700
−
492
−
10tclk−133 ns
1999 Mar 12
67
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 82 I2C-bus interface timing
All values referred to VIH(min) and VIL(max) levels; see Fig.31.
I2C-BUS
STANDARD MODE FAST MODE
MIN. MAX. MIN. MAX.
100 400
SYMBOL
PARAMETER
UNIT
fSCL
tBUF
SCL clock frequency
0
0
kHz
bus free time between STOP and START
condition
4.7
−
1.3
−
µs
tHD;STA
hold time (repeated) START condition; after this 4.0
period, the first clock pulse is generated
−
0.6
−
µs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START condition
data hold time:
4.7
4.0
4.7
−
−
−
1.3
0.6
0.6
−
−
−
µs
µs
µs
tHIGH
tSU;STA
tHD;DAT
for CBUS compatible masters
(see Chapter 21; notes 1 and 3)
5.0
−
−
−
µs
for I2C-bus devices (notes 1 and 2)
0
0
0.9
µs
ns
ns
tSU;DAT
data set-up time
250
−
−
100(3)
−
tRD; tRC
rise time of SDA and SCL signals
fall time of SDA and SCL signals
set-up time for STOP condition
capacitive load for each bus line
1000
300
−
(4)
20 + 0.1Cb
300
t
FD; tFC
tSU;STO
Cb
−
4.0
−
0.6
−
−
µs
pF
ns
400
−
400
50
tSP
pulse width of spikes which must be suppressed
by the input filter
−
0
Notes
1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) in order to bridge the undefined region of the falling edge of SCL.
2. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU, DAT > 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
R(max) + tSU,DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line
is released.
4. Cb = total capacitance of one bus line in pF.
1999 Mar 12
68
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 83 External clock drive XTAL1
VARIABLE CLOCK
(fclk = 3.5 to 16 MHz)
SYMBOL
PARAMETER
UNIT
MIN. MAX.
286
tclk
oscillator clock period
HIGH time
63
20
20
−
ns
ns
ns
ns
ns
µs
tHIGH
tLOW
tr
t
clk − tLOW
clk − tHIGH
LOW time
t
rise time
20
20
3.4
tf
fall time
−
tCYC
cycle time (12 × tclk)
0.75
t
t
t
HIGH
r
f
V
V
V
V
IH1
IH1
IH1
0.8 V
IH1
0.8 V
0.8 V
CLK
0.8 V
t
LOW
t
MGA175
Fig.24 External clock drive XTAL1.
2.4 V
2.0 V
0.8 V
test points
0.45 V
(a)
float
2.4 V
2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
0.45 V
0.45 V
(b)
MGA174
AC testing inputs are driven at 2.4 V for a HIGH and 0.45 V for a LOW.
Timing measurements are taken at 2.0 V for a HIGH and 0.8 V for a LOW, see Fig.25 (a).
The float state is defined as the point at which a Port 0 pin sinks 3.2 mA or sources 400 µA at the voltage test levels, see Fig.25 (b).
Fig.25 AC testing input, output waveform (a) and float waveform (b).
1999 Mar 12
69
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
one machine cycle
one machine cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2
P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2
XTAL1
INPUT
ALE
dotted lines
are valid when
RD or WR are
active
PSEN
only active
during a read
from external
RD
data memory
only active
during a write
WR
to external
data memory
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
external
program
memory
fetch
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
address
A0 - A7
data output or data input
read or
write of
external data
memory
address A8 - A15
address A8 - A15 or Port 2 out
address A8 - A15
PORT 2
PORT
OUTPUT
old data
new data
PORT
INPUT
sampling time of I/O port pins during input (including INT0 and INT1)
SERIAL
PORT
CLOCK
MGA180
The Port 5 input buffers have a maximum propagation delay of 300 ns.
As a result Port 5 sample time begins 300 ns before state S5 and ends when S5 has finished.
Fig.26 Instruction cycle timing.
1999 Mar 12
70
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
t
CY
t
t
LHLL
LLIV
ALE
PSEN
t
LLPL
t
PLPH
t
LLAX
t
t
t
PXIZ
AVLL
PLIV
PORT 0
PORT 2
A0 to A7
inst. input
A0 to A7
inst. input
t
t
PXIX
PLAZ
t
AVIV
address A8 to A15
address A8 to A15
MGA176
Fig.27 Read from external Program Memory.
t
CY
ALE
t
t
t
LHLL
LLDV
WHLH
PSEN
RD
t
t
RLRH
LLWL
t
t
t
RHDZ
AVLL
LLAX
t
t
t
RHDX
AVWL
RLDV
PORT 0
PORT 2
A0 to A7
data input
t
RLAZ
t
AVDV
address A8 to A15 (DPH) or Port 2
MGA177
Fig.28 Read from external Data Memory.
71
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
t
CY
t
t
LHLL
WHLH
ALE
PSEN
WR
t
t
WLWH
LLWL
t
AVWL
LLAX
t
t
t
t
WHQX
AVLL
QVWH
t
QVWX
PORT 0
PORT 2
A0 to A7
data output
address A8 to A15 (DPH) or Port 2
MGA178
Fig.29 Write to external Data Memory.
h
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
t
XHDX
SET TI
t
XHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
MGA179
Fig.30 UART waveforms in Shift Register Mode.
72
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
LM7A3
1999 Mar 12
73
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
23 EPROM CHARACTERISTICS
Table 84 Programming and Verification
The P87C557E8 has an on-chip 64 kbytes EPROM for
fast and flexible controller software development. It is
available as an OTP-version in a plastic QFP package,
P87C557E8EFB, which is not erasable.
ADDRESS
CONTENT
MEANING
Philips
P87C557E8
30H
31H
15H
C3H
23.2 Security
23.1 Programming and verification
For code protection the P87C557E8 has an Encryption
table and three Lock bits (LB1, LB2 and LB3). After
programming the Encryption table from addresses
00H to 3FH, a verification sequence will present the data
at Port 0 as a logical EXNOR of the program byte with one
of the Encryption bytes. The Encryption table is not
readable.
The P87C557E8 is programmed by using a modified
Quick-Pulse Programming algorithm (Trademark
algorithm of Intel Corporation).
In Table 85, the logic levels for reading the Signature bytes
and for programming the Program Memory, the Encryption
Table and the Lock bits are listed.
The circuit configuration and waveforms for programming
are shown in the Figs 32 and 33. Figure 34 shows the
circuit configuration for code data verification.
The P87C557E8 has 3 programmable Lock bits which
must be programmed according to Table 85 to provide
different levels of protection of the on-chip code and data.
Erasing the EPROM also erases the encryption array and
the program lock bits, returning the part to full functionality.
The lock bits cannot be directly verified. Verification of the
lock bits is done by observing that their features are
enabled.
Note that programming and verification is done with an
oscillator frequency of 4 to 6 MHz. The two Signature
bytes identifying the device as an P87C557E8
manufactured by Philips are located as shown in Table 84.
Table 85 Protection Level 69Programming
P = programmed; U = unprogrammed.
PROTECTION
LB1 LB2 LB3
LEVEL
PROTECTION DESCRIPTION
1
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.).
2
P
U
U
MOVC instructions executed from external Program Memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further programming of the EPROM is disabled.
3
4
P
P
P
P
U
P
Same as Protection Level 2 and also verify is disabled.
Same as Protection Level 3 and external memory execution by forcing EA = LOW
is disabled.
1999 Mar 12
74
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 86 EPROM programming modes
ALE/
PROG
MODE
RSTIN
PSEN
EA/VPP
P2.7
P2.6
P3.7
P3.6
P3.3
Read Signature
Program code data
Verify code data
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
LOW (1) VPP
HIGH
LOW
HIGH
LOW
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
(2)
HIGH
LOW(1)
LOW(1)
LOW(1)
LOW(1)
HIGH
(2)
(2)
(2)
(2)
Program Encryption table HIGH
VPP
VPP
VPP
VPP
Program Lock bit 1
Program Lock bit 2
Program Lock bit 3
HIGH
HIGH
HIGH
Notes
1. Each programming pulse is:
a) LOW for 50 ± 5 µs.
b) HIGH for at least 5 µs.
2. ALE/PROG receives 5 programming pulses while VPP is held at 12.75 ± 0.25 V.
+5 V
V
DD
P0
A0 to A7
P1
PGM data
+12.75 V
RST
P3.6
P3.7
P3.3
HIGH
HIGH
HIGH
HIGH
EA/V
PP
5 50 µs - PULSES TO GROUND
ALE/PROG
PSEN
P2.7
LOW
HIGH
LOW
P8xC557E8
XTAL2
P2.6
4 to 6 MHz
P2.0 to P2.5
A8 to A13
P3.4
P3.5
A14
A15
XTAL1
V
SS
MBH090
Fig.32 Programming configuration.
1999 Mar 12
75
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
5 pulses
ALE/PROG
≥ 5 µs
50 ± 5 µs
MGL170
Fig.33 PROG waveform.
+5 V
V
DD
A0 to A7
P1
P0
PGM data
HIGH
RST
HIGH
HIGH
HIGH
LOW
EA/V
PP
P3.6
P3.7
P3.3
XTAL2
ALE/PROG
HIGH
LOW
LOW
LOW
PSEN
P2.7
P8xC557E8
P2.6
4 to 6 MHz
P2.0 to P2.5
P3.4
A8 to A13
A14
XTAL1
V
P3.5
A15
SS
MBH091
Fig.34 Program verification P87C557E8.
76
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
Table 87 EPROM programming and verification characteristics
V
DD = 5 V ± 10%; VSS = 0 V; Tamb = 21 °C to 27 °C.
SYMBOL PARAMETER
programming supply voltage
MIN.
12.5
MAX.
UNIT
VPP
13.0
V
IPP
programming supply current
oscillator frequency
−
50
mA
fclk
4
6
MHz
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHGL
address set-up to PROG LOW
address hold after PROG HIGH
data set-up to PROG LOW
data hold after PROG HIGH
P2.7 (ENABLE) HIGH to Vpp
Vpp set-up to PROG LOW
Vpp hold after PROG HIGH
PROG pulse width
48 tclk
48 tclk
48 tclk
48 tclk
48 tclk
10
−
−
−
−
−
−
µs
µs
µs
10
−
45
55
address to data valid
−
48tclk
48tclk
48tclk
−
P2.7 (ENABLE) LOW to data valid
data float after P2.7 (ENABLE) HIGH
PROG HIGH to PROG LOW
−
0
5
µs
(1)
(2)
PROGRAMMING
VERIFICATION
ADDRESS
P1.0 - P1.7
P2.0 - P2.5
P3.4 - P3.5
ADDRESS
t
AVQV
PORT 0
DATA IN
DATA OUT
t
t
GHDX
DVGL
t
t
AVGL
GHAX
ALE/PROG
t
t
GLGH
GHGL
t
t
GHSL
SHGL
EA/V
PP
HIGH
LOW
t
t
t
EHSH
ELQV
EHQZ
P2.7
(ENABLE)
MGD633
(1) For programming see Fig.32.
(2) For verification conditions see Fig.34.
Fig.35 EPROM Programming and Verification.
77
1999 Mar 12
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
24 PACKAGE OUTLINE
QFP80: plastic quad flat package;
80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT318-1
y
X
A
64
65
41
40
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
w M
p
θ
pin 1 index
L
p
b
L
25
80
detail X
1
24
w M
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.36 2.87
0.10 2.57
0.45 0.25 20.1 14.1
0.30 0.13 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.0
0.6
1.2
0.8
mm
3.3
0.25
0.8
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT318-1
1999 Mar 12
78
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
25 SOLDERING
25.3 Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
25.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
25.2 Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
Reflow soldering techniques are suitable for all QFP
packages.
QFP100 (SOT382-1) or QFP160 (SOT322-1).
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
25.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1999 Mar 12
79
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
26 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
27 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
28 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Mar 12
80
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
NOTES
1999 Mar 12
81
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
NOTES
1999 Mar 12
82
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
NOTES
1999 Mar 12
83
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/1200/01/pp84
Date of release: 1999 Mar 12
Document order number: 9397 750 02689
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