P5021P5021NSE7VNC [NXP]
P5021 QorIQ Integrated Processor Data Sheet;型号: | P5021P5021NSE7VNC |
厂家: | NXP |
描述: | P5021 QorIQ Integrated Processor Data Sheet |
文件: | 总155页 (文件大小:3229K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: P5021
Rev. 1, 05/2014
P5021
P5021 QorIQ
Integrated Processor
Data Sheet
FC-PBGA–1295
37.5 mm × 37.5 mm
The P5021 QorIQ integrated communication processor
combines two Power Architecture® processor cores with
high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and aerospace
applications.
• Two serial ATA (SATA) 2.0 controllers
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interface (eSPI)
• Two high-speed USB 2.0 controllers with integrated PHYs
• RAID 5 and 6 storage accelerator with support for
end-to-end data protection information
• Data Path Acceleration Architecture (DPAA) incorporating
acceleration for the following functions:
– Frame Manager (FMan) for packet parsing,
classification, and distribution
This chip can be used for combined control, data path, and
application layer processing in routers, switches, base station
controllers, and general-purpose embedded computing. Its
high level of integration offers significant performance
benefits compared to multiple discrete devices while also
greatly simplifying board design.
– Queue Manager (QMan) for scheduling, packet
sequencing and congestion management
– Hardware Buffer Manager (BMan) for buffer allocation
and deallocation
The chip includes the following function and features:
– Encryption/Decryption
• 1295 FC-PBGA package
• Two e5500 Power Architecture cores
– Each core has a backside 512 KB L2 cache with ECC
– Three levels of instructions: user, supervisor, and
hypervisor
This figure shows the major functional units within the chip.
– Independent boot and reset
– Secure boot capability
• CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet endpoints
• Frontside 2 MB CoreNet platform cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os,
datapath accelerators, and high and low speed peripheral
interfaces
• Two 10-Gigabit Ethernet (XAUI) controllers
• Ten 1-Gigabit Ethernet controllers
– SGMII, 2.5Gb/s SGMII and RGMII interfaces
• Two 64-bit DDR3/3L SDRAM memory controllers with
ECC
• Multicore programmable interrupt controller (PIC)
2
• Four I C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller (eLBC)
• Three PCI Express 2.0 controllers/ports
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
© 2013-2014 Freescale Semiconductor, Inc. All rights reserved.
Table of Contents
1
2
Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .3
2.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.19 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.20 High-speed serial interfaces (HSSI) . . . . . . . . . . . . . 101
Hardware design considerations. . . . . . . . . . . . . . . . . . . . . 129
3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.2 Supply power default setting . . . . . . . . . . . . . . . . . . . 136
3.3 Power supply design . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.4 Decoupling recommendations. . . . . . . . . . . . . . . . . . 139
3.5 SerDes block power supply decoupling recommendations
140
1.1 1295 FC-PBGA ball layout diagrams . . . . . . . . . . . . . . .3
1.2 Pinout list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .52
2.2 Power-up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3 Power-down requirements . . . . . . . . . . . . . . . . . . . . . .60
2.4 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.5 Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.6 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.7 RESET initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.8 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.9 DDR3 and DDR3L SDRAM controller. . . . . . . . . . . . . .66
2.10 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.11 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.12 Ethernet: data path three-speed Ethernet (dTSEC),
management interface, IEEE Std 1588. . . . . . . . . . . . .77
2.13 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
2.14 Enhanced local bus interface (eLBC) . . . . . . . . . . . . . .87
2.15 Enhanced secure digital host controller (eSDHC) . . . .92
2.16 Multicore programmable interrupt controller (MPIC)
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
2.17 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
3
3.6 Connection recommendations. . . . . . . . . . . . . . . . . . 140
3.7 Recommended thermal model . . . . . . . . . . . . . . . . . 150
3.8 Thermal management information. . . . . . . . . . . . . . . 150
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.1 Package parameters for the FC-PBGA . . . . . . . . . . . 151
4.2 Mechanical dimensions of the FC-PBGA . . . . . . . . . 152
Security fuse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.1 Part numbering nomenclature . . . . . . . . . . . . . . . . . . 153
6.2 Orderable part numbers addressed by this document154
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4
5
6
7
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
2
Freescale Semiconductor
Pin assignments and reset states
1024 KB
frontside
L3 cache
64-bit
1600 MT/s DDR-3
QorIQ P5021
memory controller
Power Architecture®
e5500 Core
512 KB
backside
L2 cache
64-bit
1600 MT/s DDR-3
memory controller
1024 KB
frontside
L3 cache
32 KB
32 KB
I-cache
D-cache
eOpenPIC
PreBoot
Loader
CoreNet™
Coherency Fabric
Peripheral access
management unit (PAMU)
Security
Monitor
PAMU
PAMU
PAMU
PAMU
PAMU
Internal
BootROM
Power mgmt
SD/MMC
SPI
Real-time debug
Frame Manager
Frame Manager
eLBC
DMA
DMA
Parse, classify,
distribute
Parse, classify,
distribute
Security
Queue
Test
Port/
SAP
5.0
Mgr
Watchpoint
cross
trigger
Buffer
Buffer
2x DUART
1GE
1GE
10GE 1GE
1GE
2
4x I Cs
1GE
1GE
1GE
10GE
Perf
monitor
CoreNet
trace
Buffer
Mgr
RAID5/6
2x USB 2.0
+ 2x PHY
1GE
1GE
1GE
Clocks/Reset
GPIO
SATA
SerDes
18-Lane 5-GHz SerDes
RGMII
CCSR
Figure 1. P5021 block diagram
1
Pin assignments and reset states
1.1
1295 FC-PBGA ball layout diagrams
These figures show the FC-PBGA ball map diagrams.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
3
Pin assignments and reset states
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D2_
MDQS
0
D2_
MDQ
01
D2_
MDQ
04
D1_
MDQ
03
D1_
MDQ
06
D1_
MDM
0
D1_
MDQ
00
SD_
REF_
CLK1
D2_
MDQ
21
D2_
MDQ
20
D2_
MDQ
10
D2_
MDQS
1
D2_
MDQS
1
D2_
MDQ
08
D2_
MDQ
03
D2_
MDQ
07
D2_
MDQS
0
RSRV
_A21
SV
DD
AVDD_ SV
SRDS1
NC_
A27
SGND SD_RX
01
SD_RX SGND
03
SGND
GND
AVDD_ AVDD_
GND
RSRV
_A25
GND
LWE
1
DD
LALE
A
B
A
DDR
CC1
SD_
REF_
CLK1
D2_
MDQ
16
D2_
MDQ
17
D2_
MDQ
11
D2_
MDM
1
D2_
MDQ
13
D2_
MDQ
02
D2_
MDQ
06
D2_
MDM
0
D2_
MDQ
05
D1_
MDQ
07
D1_
MDQS
0
D1_
MDQ
05
TEMP_
CATH-
ODE
BV
SV
SV
SV
DD
GV
DD
GV
DD
GV
DD
SD_IMP_
CAL_RX
AGND_
SRDS1
GND
GND
NC_
B26
SGND
SGND
GND
GND
GND
LCS
5
LGPL
0
SD_RX
01
SD_RX
03
DD
DD
DD
MVREF
B
D2_
MDQS
2
D2_
MDM
2
D2_
MDQ
14
D2_
MDQ
12
D1_
MDQ
16
D1_
MDQ
21
D1_
MDQ
20
D2_
MDQ
00
D1_
MDQ
02
D1_
MDQS
0
D1_
MDQ
04
D2_
MDQS
2
SV
DD
SV
DD
SV
DD
GV
DD
GV
DD
GV
DD
NC_
C19
NC_
C20
LCLK
1
LCLK
0
LGPL
4
NC_
C26
NC_
C27
SD_RX SGND SD_RX
SGND
GND
GND
GND
TEMP_
ANODE
RSRV
_C32
SD_RX
04
LBCTL
C
C
00
02
D2_
MDQ
22
D2_
MDQ
23
D2_
MDQ
18
D2_
MDQ
15
D2_
MDQ
09
D1_
MDQS
2
D1_
MDQS
2
D1_
MDM
2
D1_
MDQ
17
D1_
MDM
1
D1_
MDQ
08
D1_
MDQ
01
GV
DD
SV
DD
GV
DD
GV
DD
SD_RX
04
NC_
D18
LAD
09
LGPL
2
LAD
27
NC_
D27
SGND
XGND SD_TX SGND
04
GND
GND
LCS
00
LCS
1
LCS
3
LCS
4
LWE
0
SD_RX
00
SD_RX
02
RSRV
_D32
D
D
D2_
MDQ
19
D2_
MDQ
29
D2_
MDQ
28
D1_
MDQ
22
D1_
MDQ
23
D1_
MDQ
18
D1_
MDQ
19
D1_
MDQ
10
D1_
MDQ
14
D1_
MDQ
13
BV
DD
BV
DD
XV
XV
SV
DD
GV
DD
GV
DD
GV
DD
NC_
E16
LA
28
GND
LA
21
LAD
08
LGPL
1
LGPL
5
NC_
E27
XGND
XGND
SGND
GND
GND
GND
LCS
2
SD_TX
01
SD_TX
03
SD_TX
04
DD
DD
E
E
D2_
MDQ
24
D2_
MDQ
25
D1_
MDQ
24
D1_
MDQ
29
D1_
MDQ
28
D1_
MDQ
25
D1_
MDQ
15
D1_
MDQ
12
D1_
MDQS
1
BV
DD
BV
XV
DD
XV
DD
SV
DD
GV
DD
GV
DD
SD_TX
03
SD_RX
05
LA
29
LAD
12
LA
22
LA
19
GND
LCS
6
LAD
04
GND
XGND
RSRV
_F1
RSRV
_F2
GND
GND
GND
LA
31
SD_TX
01
SD_TX
05
SD_RX
05
DD
F
F
D2_
MDM
3
D2_
MDQS
3
D2_
MDQS
3
D1_
MDQS
3
D1_
MDQS
3
D1_
MDM
3
D1_
MDQ
11
D1_
MDQS
1
D1_
MDQ
09
XV
SV
DD
GV
DD
GV
DD
GV
DD
LAD
06
SD_TX
00
SD_TX
02
SD_TX
05
LAD
31
LA
28
LA
25
GND
LAD
11
LAD
07
LA
17
LCS
7
NC_
G27
XGND
XGND
XGND
XGND
SGND
XGND
SGND
RSRV
_G2
GND
GND
GND
RSRV
_G1
DD
G
G
D2_
MDQ
31
D2_
MDQ
30
D2_
MDQ
26
D2_
MDQ
27
D1_
MDQ
30
D1_
MDQ
31
D1_
MDQ
26
BV
DD
XV
XV
DD
GV
DD
GV
DD
GV
DD
BV
DD
SD_TX
00
SD_TX
02
SD_RX
06
GND
NC_
H12
NC_
H13
NC_
H15
LDP
02
LA
29
LA
23
LA
20
LA
18
LAD
05
LAD
03
LGPL
3
NC_
H27
XGND
GND
LDP
3
SD_RX
06
DD
H
H
D2_
D2_
D2_
D1_
D1_
D1_
D1_
MDQ
27
XV
DD
XV
DD
XV
SV
DD
GV
DD
NC_
J11
GV
DD
NC_
J13
NC_
J14
LA
30
LAD
15
LAD
13
LA
30
LA
26
GND
LAD
10
GND
LDP
0
LA
16
LAD
02
GND
XGND
SD_TX SD_TX SGND
GND
GND
LWE
2
DD
MECC MECC
MECC MECC
MECC MECC
J
J
06
06
0
5
4
1
5
4
SEE DETAIL A
SEE DETAIL B
D2_
MDM
8
D2_
MECC
1
D1_
MDQS
8
D1_
MDM
8
D1_
MECC
0
D2_
MDQS
8
D1_
MDQS
8
SENSE-
GND_PL
2
BV
DD
BV
DD
XV
SV
DD
GV
DD
GV
DD
SENSE- SENSE-
VDD_CA GND_CA
NC_
K11
NC_
K12
NC_
K13
NC_
K14
LWE
3
LAD
14
GND
LA
27
LA
24
LDP
1
GND
LAD
00
XGND
XGND
XGND
SD_TX
07
SGND
SD_RX
07
GND
SD_RX
07
SD_TX
07
DD
K
K
D2_
MDQS
8
D2_
D2_
D1_
MECC
6
D1_
D1_
SENSE-
VDD_PL
XV
XV
SV
DD
GV
DD
GV
DD
SD_RX SD_RX
D1_MA
15
LAD
01
XGND
SGND
GND
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL
DD
DD
RSRV
_L28
MECC MECC
6
MECC MECC
7
L
L
08
08
7
2
2
D2_
MBA
2
D2_
D2_
D1_
MBA
2
D1_
MECC
3
RSRV
_M28
XV
DD
SV
DD
GV
DD
SD_TX
08
SD_RX
09
XGND
XGND
SGND
GND
GND
GND VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL
GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL
GND VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL
SD_RX
09
D2_MA
15
D1_MA
14
SD_TX
08
MCKE MECC
3
M
M
02
D2_
MAPAR_
ERR
D2_
MECC
3
D1_
MAPAR_
ERR
D1_
MCKE
3
RSRV
_N28
XV
SV
DD
GV
DD
GV
DD
SD_TX
09
D2_MA
12
D2_MA
14
D1_MA
12
XGND
XGND
XGND
SGND
GND
SD_TX
09
DD
N
N
D2_
MCKE
2
D1_
MCKE
2
D1_
MCKE
0
XV
DD
XV
DD
GV
DD
GV
DD
SD_TX
10
SD_RX
10
SD_TX
10
XGND
GND
SD_RX
10
RSRV
_P28
D2_MA
09
D2_MA
11
D1_MA D1_MA
09 11
P
P
D2_
MCKE
0
D1_
MCKE
1
XV
DD
XV
SV
DD
SV
DD
GV
DD
D2_MA
07
AVDD_
SRDS4
XGND
XGND
SGND
SGND
D2_MA D2_MA
06 08
GND
D1_MA D1_MA
GND
DD
R
R
08
07
D2_
MCKE
1
D1_
MDIC
0
XV
DD
XV
GV
DD
GV
DD
AGND_
SRDS2
AGND_
SRDS4
SD_TX
11
SD_RX SGND
11
GND
SD_TX
11
SD_RX
11
D2_MA D2_MA D2_MA
03
D1_MA D1_MA
05 06
DD
T
T
04
05
XV
DD
SV
DD
GV
DD
GV
DD
AVDD_
SRDS2
SD_
REF_
CLK4
XGND
XGND
XGND
XGND
SGND
RSRV
D2_MA
01
GND
D2_MA
02
GND
D1_MA D1_MA
01
D1_MA D1_MA
RSRV
_U32
U
U
02
03
04
_U35
SD_
REF_
CLK2
D2_
MCK
2
D2_
MCK
2
D2_
MCK
1
D2_
MCK
1
D1_
MCK
1
D1_
MCK
1
D1_
MCK
2
D1_
MCK
2
SD_
SV
XV
DD
XV
GV
DD
SD_
REF_
CLK4
SGND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND
DD
DD
V
REF_
CLK2
V
D2_
MCK
3
D2_
MCK
3
D2_
MCK
0
D2_
MCK
0
D1_
MCK
0
D1_
MCK
0
D1_
MCK
3
D1_
MCK
3
NC_
W27
XV
DD
SV
GV
DD
XGND SD_TX
12
SGND
SD_RX SD_RX
12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_PL
SD_TX
12
VDD_PL
GND
VDD_PL
GND
GND
GND
GND
GND
DD
W
Y
W
Y
12
D2_
MDIC
1
D1_
MBA
1
D2_
MAPAR_
OUT
D1_
MAPAR_
OUT
XV
SD_TX
SV
DD
GV
DD
GV
DD
XGND SD_TX
13
XGND SD_RX SD_RX SGND
13
13
GND
GND
GND
GND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND
D2_MA
00
D1_MA
00
VDD_PL
GND
VDD_PL
GND
GND
GND
GND
GND
DD
13
D2_
MBA
1
D2_
MBA
0
D2_
MDIC
0
D1_
MDIC
1
D1_
MBA
0
XV
SD1_IMP_
GND VDD_PL GND VDD_PL GND VDD_PL
DD
SV
DD
GV
DD
D1_
MRAS
D2_MA
10
D1_MA
10
XGND SD_TX SD_TX
SGND SD_RX SD_RX
GND
GND
VDD_PL
VDD_PL
GND
GND
GND
GND
GND
GND
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
CAL_TX
14
14
14
14
D2_
MCS
2
D1_
MDQ
36
D1_
MDQ
37
D1_
MCS
2
XV
DD
XV
DD
SV
DD
D2_
MRAS
D2_
MWE
GV
DD
D1_
MWE
GV
DD
SD_TX
15
SD_TX SD_TX
18
XGND
SGND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND
SD_TX
15
GND VDD_PL GND
GND
GND
GND
GND
GND
GND
18
D2_
MCS
0
D1_
MDQ
33
D1_
MDQ
32
SD_
REF_
CLK3
SD_
REF_
CLK3
D1_
MCS
0
XV
DD
GV
DD
D2_
MCAS
GV
DD
D1_
MCAS
SD_RX
15
D2_MA
13
V
S1V
DD
XGND
XGND SD_RX
15
GND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL
VDD_PL
VDD_PL
GND
GND
GND
DD_
LL
D2_
D2_
D1_
MDQS
4
D1_
MDM
4
D1_
MODT
2
D1_
MODT
0
D1_
MDQS
4
XV
SV
DD
GV
DD
SD_RX XGND XGND
18
SGND
GND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND
RSRV
_AD33 _AD34
RSRV
GND VDD_PL
VDD_PL
GND
VDD_PL
GND
VDD_PL
VDD_
LP
DD
MODT MODT
2
0
D2_
MCS
1
D2_
MCS
3
D2_
MODT
3
D1_
MDQ
38
D1_
MDQ
39
D1_
MCS
1
XV
DD
SV
GV
DD
GV
DD
SD_TX
16
AVDD_ AGND_
SRDS3 SRDS3
D1_MA
13
SD_RX
18
SGND
DD
GND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND
GND
SD_TX
16
VDD_PL
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
LP_TMP
_DETECT
D2_
MODT
1
D2_
MDQ
37
D2_
MDQ
36
D1_
MDQ
34
D1_
MDQ
35
D1_
MODT
3
D1_
MCS
3
SENSE- SENSE-
VDD_PL GND_PL
XV
DD
SV
GV
DD
GV
DD
SD1_IMP SD_RX SD_RX SGND
XGND SD_RX SD_RX
SGND
DD
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_PL
VDD_PL
GND
VDD_PL
GND
SD_IMP_
CAL_TX
CAL_RX
19
19
16
16
1
1
D2_
MDM
4
D2_
MDQ
33
D2_
MDQ
32
D1_
MDQ
40
D1_
MDQ
45
D1_
MDQ
44
D1_
MODT
1
DMA2_
DACK
0
IO_
VSEL
4
PD
17
CV
DD
OV
DD
SV
DD
GV
DD
IIC4_
SCL
NC_
AG15
IRQ
06
PD
13
SD_TX SD_TX X1V
S1VDD
RSRV
_AG29
XGND SD_TX
17
SGND
SD_RX SD_RX
GND
GND
RSRV
RSRV
_AG11 _AG12
IRQ
08
GPIO
07
SD_TX
17
DD
19
USB1_ USB2_
19
17
17
SEDE1_ DETAIL C
D2_
MDQ
38
D2_
MDQS
4
D1_
MDQS
5
D1_
GV
D2_
MDQS
4
D1_
MDQS
5
EC2_
RX_ER
GV
DD
IIC1_
SCL
USB1_
AGND
SPI_
MISO
XV
DD
SV
DD
IRQ
10
IRQ
01
IRQ
04
GND
USB2_
SD_PLL4
XGND
GND
GND
RSRV
RSRV
_AH11 _AH12
GND
UART2_
CTS
SGND
SGND
DD
MSRCID
2
MSRCID GPIO
MDM
5
MDQ
41
VDD_
1P0
VDD_
1P0
AGND
_TPD
0
04
SEE DETAIL D
TSEC_
1588_ALARM
_OUT1
TSEC_
1588_PULSE
_OUT2
D2_
MDQ
35
D2_
MDQ
34
D2_
MDQ
39
D1_
MDQ
46
D1_
MDQ
47
D1_
MDQ
42
D1_
MDQ
43
DMA2_
DREQ
0
USB1_ USB2_
USB2_
VDD_
3P3
EC_XTRNL
_TX_STMP
2
OV
DD
CV
DD
LV
GV
DD
GV
DD
OV
GND
OV
DD
OV
USB1_
AGND
GND
EMI1_
MDC
IRQ
05
IRQ
03
IRQ
00
EVT
0
GND
EMI2_
MDIO
GPIO UART2_
SPI_CS
1
DD
DD
DD MSRCID
1
VDD_
3P3
VDD_
3P3
05
SOUT
IO_
VSEL
2
TSEC_
TSEC_
588_ALARM1588_TRIG
D2_
MDQ
45
D2_
MDQ
44
D1_
MDQ
53
D1_
MDQ
52
USB1_
VBUS_
CLMP
USB2_
VBUS_
CLMP
EC1_
GTX_
CLK125
EC_XTRNL EC_XTRNL
_RX_STMP_RX_STMP
2
LV
GV
DD
GV
DD
IIC3_
SCL
IRQ_
OUT
CLK_
OUT
USB1_
UID
SPI_
CLK
IRQ
09
IRQ
02
EVT
3
EVT
1
GND
USB2_
UID
GND
GND
GND
GND
GPIO
06
GPIO
01
EMI2_
MDC
RSRV
_AK1
RSRV
_AK2
UART2_
RTS
DD
_OUT2
_IN2
1
IO_
VSEL
0
USB2_
VDD_1P8
_DECAP
TSEC_
1588_PULSE
_OUT01
D2_
MDM
5
D2_
MDQ
41
D2_
MDQ
40
D1_
MDQ
49
D1_
MDQ
48
D1_
MDM
6
USB1_
VDD_
3P3
USB1_
VDD_1P8
_DECAP
EC2_
GTX_
CLK125
TSEC_
1588_CLK
_IN
TSEC_
1588_TRIG
_IN1
DMA1_
DACK
0
OV
DD
LV
DD
GV
DD
GV
DD
IIC2_
SDA
IIC4_
SDA
OV
DD
USB1_
AGND
EMI1_
MDIO
IRQ
11
USB1_
AGND
GND
GND
GND
GND
GPIO
00
RSRV
_AL1
RSRV
_AL2
SCAN_
MODE
UART1_ SHDC_
SOUT
CLK
IO_
VSEL
3
D2_
MDQ
52
D2_
MDQS
5
D2_
MDQS
5
D2_
MDQ
46
D2_
MDQ
47
D1_
MDQS
6
D1_
MDQS
6
USB2_
IBIAS_
REXT
EC1_
RXD
03
USB1_
IBIAS_
REXT
EC_XTRNL
_TX_STMP
1
TSEC_
1588_CLK_
OUT
SDHC_
DAT
2
LV
GV
DD
GV
DD
IIC3_
SDA
IIC2_
SCL
USB1_
AGND
GND
EC1_
RX_DV
EC1_
RX_CLK
VID_
VDD_CA
_CB3
IRQ
07
EVT
4
GND
USB_
CLKIN
USB2_
AGND
GND
GND
GND
CKSTP_ GPIO
UART1_
RTS
SPI_CS
3
DD
02
OUT
D2_
MDQ
48
D2_
MDQ
53
D2_
MDQ
42
D2_
MDQ
43
D1_
MDQ
54
D1_
MDQ
55
D1_
MDQ
50
D1_
MDQ
51
EC1_
RXD
2
EC1_
RXD
1
EC1_
RXD
0
DMA1_
DDONE
0
TMP_
DETECT
OV
USB2_ USB2_ USB2_
LV
GV
DD
GV
DD
IIC1_
VDD_CA SDA
OV
DD
VID_
EVT
2
USB2_
AGND
GND
GND
GND
GND
GPIO
03
SPI_CS
0
PD
06
DD UART2_
SIN
PD
12
DD
TDI
RTC
AGND
AGND
AGND
_CB2
IO_
D2_
MDQS
6
D2_
MDM
6
D2_
MDQ
49
D2_
MDQ
56
D2_
MDM
7
D2_
MDQ
58
D1_
MDQ
60
D1_
MDQ
63
EC1_
TXD
3
EC1_
GTX_
CLK
DMA2_
DDONE
0
DMA1_
DREQ
0
PD
14
CV
DD
LV
GV
DD
GV
DD
OV
DD
USB2_
UDM
TEST_
SEL2
VID_
VDD_CA
_CB1
GND
GND
USB2_
AGND
GND
GND
GND
USB2_
AGND
UART1_
CTS
USB2_
UDP
PD
02
DD
PD
07
PD
05
TDO
PORESET VSEL
1
D2_
MDQS
6
D2_
MDQ
54
D2_
MDQ
60
D2_
MDQS
7
D2_
MDQ
62
D1_
MDQ
61
D1_
MDQ
57
D1_
MDQ
62
D1_
MDQ
59
EC1_
TXD
1
OV
DD
LV
GV
DD
GV
DD
GV
DD
USB1_ USB1_ USB2_
GND
EC1_
TX_EN
GND
GND
GND
GND
UART1_
SIN
USB1_
AGND
PD
03
PD
09
SPI_CS
2
PD
10
DD
MDVAL
HRESET
TRST
TMS ASLEEP TCK
AGND AGND
AGND
D2_
MDQ
50
D2_
MDQ
51
D2_
MDQ
55
D2_
MDQ
61
D2_
MDQ
57
D2_
MDQS
7
D2_
MDQ
63
D2_
MDQ
59
D1_
MDQ
56
D1_
MDM
7
D1_
MDQS
7
D1_
MDQS
7
D1_
MDQ
58
EC1_
TXD
2
EC1_
TXD
0
PD
15
OV
DD
SPI_
MOSI
VID_
VDD_CA
_CB0
AVDD_
FM
GND
22
USB2_
AGND
GND
36
AVDD_
POVDD
AVDD_ TEST_
USB1_ USB1_
PD
04
PD
01
PD
08
RESET_
REQ
USB1_
AGND
PD
11
SYSCLK
23
UDM
26
UDP
27
CC2
PLAT
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
24
25
28
29
30
31
32
33
34
35
Signal Groups
AVDD_
SRDS1
SENSE-
VDD
OV
SV
XV
DD
DD
I/O Supply Voltage
I/O Supply Voltage
SerDes 1 PLL Supply Voltage
SerDes 2 PLL Supply Voltage
Platform PLL Supply Voltage
Core PLL Supply Voltage
Platform Voltage Sense
Core Group A Voltage Sense
Core Group B Voltage Sense
Reserved
SerDes Core Power Supply
AVDD_
SRDS2
SENSE-
VDD_CB
LV
DD
DD
SerDes Transcvr Pad Supply
Platform Supply Voltage
VDD_
PL
AVDD_
PLAT
GV
CV
BV
RSRV
DD
DD
DD
DDR DRAM I/O Supply
SPI Voltage Supply
VDD_
CA
AVDD_
CC
POVDD
Core Group A Supply Voltage
Fuse Programming Override Supply
SENSE-
VDD_PL
Local Bus I/O Supply
Figure 2. 1295 BGA ball map diagram (top view)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
4
Freescale Semiconductor
Pin assignments and reset states
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
D2_
MDQS
0
D2_
MDQ
21
D2_
MDQ
20
D2_
MDQ
10
D2_
MDQS
1
D2_
MDQS
1
D2_
MDQ
08
D2_
MDQ
03
D2_
MDQ
07
D2_
MDQS
0
D2_
MDQ
01
D2_
MDQ
04
D1_
MDQ
03
D1_
MDQ
06
D1_
MDM
0
D1_
MDQ
00
GND
A
B
C
D
E
F
D2_
MDQ
16
D2_
MDQ
17
D2_
MDQ
11
D2_
MDM
1
D2_
MDQ
13
D2_
MDQ
02
D2_
MDQ
06
D2_
MDM
0
D2_
MDQ
05
D1_
MDQ
07
D1_
MDQS
0
D1_
MDQ
05
GV
DD
GV
DD
GV
DD
GND
GND
GND
D2_
MDQS
2
D2_
MDM
2
D2_
MDQ
14
D2_
MDQ
12
D1_
MDQ
16
D1_
MDQ
21
D1_
MDQ
20
D2_
MDQ
00
D1_
MDQ
02
D1_
MDQS
0
D1_
MDQ
04
D2_
MDQS
2
GV
DD
GV
DD
GV
DD
GND
GND
GND
D2_
MDQ
22
D2_
MDQ
23
D2_
MDQ
18
D2_
MDQ
15
D2_
MDQ
09
D1_
MDQS
2
D1_
MDQS
2
D1_
MDM
2
D1_
MDQ
17
D1_
MDM
1
D1_
MDQ
08
D1_
MDQ
01
GV
DD
GV
DD
GV
DD
NC_
D18
GND
GND
D2_
MDQ
19
D2_
MDQ
29
D2_
MDQ
28
D1_
MDQ
22
D1_
MDQ
23
D1_
MDQ
18
D1_
MDQ
19
D1_
MDQ
10
D1_
MDQ
14
D1_
MDQ
13
GV
DD
GV
DD
GV
DD
LAD
28
NC_
E16
GND
GND
GND
D2_
MDQ
24
D2_
MDQ
25
D1_
MDQ
24
D1_
MDQ
29
D1_
MDQ
28
D1_
MDQ
25
D1_
MDQ
15
D1_
MDQ
12
D1_
MDQS
1
GV
DD
GV
DD
LAD
29
RSRV
_F1
RSRV
_F2
GND
GND
GND
LAD
31
D2_
MDM
3
D2_
MDQS
3
D2_
MDQS
3
D1_
MDQS
3
D1_
MDQS
3
D1_
MDM
3
D1_
MDQ
11
D1_
MDQS
1
D1_
MDQ
09
RSRV
_G1
RSRV
_G2
GV
DD
GV
DD
GV
DD
GND
LA
31
GND
GND
G
H
J
D2_
MDQ
31
D2_
MDQ
30
D2_
MDQ
26
D2_
MDQ
27
D1_
MDQ
30
D1_
MDQ
31
D1_
MDQ
26
GV
DD
GV
DD
GV
DD
BV
DD
LDP
2
NC_
H12
NC_
H13
NC_
H15
GND
GND
LDP
3
D2_
MECC
0
D2_
MECC
5
D2_
MECC
4
D1_
MECC
1
D1_
MECC
5
D1_
MECC
4
D1_
MDQ
27
GV
DD
GV
DD
LWE
2
NC_
J11
NC_
J13
LAD
30
NC_
J14
LAD
15
LAD
13
GND
GND
D2_
MDM
8
D2_
MECC
1
D1_
MDQS
8
D1_
MDM
8
D1_
MECC
0
D2_
MDQS
8
D1_
MDQS
8
GV
DD
GV
DD
SENSE- SENSE-
VDD_CA GND_CA
NC_
K11
NC_
K12
NC_
K13
NC_
K14
LAD
14
GND
LWE
3
K
L
D2_
MDQS
8
D2_
MECC
6
D2_
MECC
7
D1_
MECC
6
D1_
MECC
7
D1_
MECC
2
GV
DD
GV
DD
D1_MA
15
GND
VDD_PL
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA
GND VDD_PL GND VDD_CA GND VDD_CA GND
VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA
GND VDD_PL GND VDD_CA GND VDD_CA GND
VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA
GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL
D2_
MBA
2
D2_
MCKE
3
D2_
MECC
2
D1_
MBA
2
D1_
MECC
3
GV
DD
GND
GND
D2_MA
15
D1_MA
14
M
N
P
R
T
D2_
MAPAR_
ERR
D2_
MECC
3
D1_
MAPAR_
ERR
D1_
MCKE
3
GV
DD
GV
DD
D2_MA
12
D2_MA
14
D1_MA
12
GND
VDD_PL
GND
D2_
MCKE
2
D1_
MCKE
2
D1_
MCKE
0
GV
DD
GV
DD
GND
D2_MA
09
D2_MA
11
D1_MA D1_MA
09 11
D2_
MCKE
0
D1_
MCKE
1
GV
D2_MA
07
D2_MA D2_MA
06 08
GND
D1_MA D1_MA
GND
VDD_PL
GND
DD
08
07
D2_
MCKE
1
D1_
MDIC
0
GV
DD
GV
DD
GND
D2_MA D2_MA D2_MA
D1_MA D1_MA
05 06
03
04
05
GV
GV
D2_MA
01
GND
D2_MA
02
GND
D1_MA D1_MA
01
VDD_PL
GND
D1_MA D1_MA
03
DD
DD
U
V
02
04
D2_
MCK
2
D2_
MCK
2
D2_
MCK
1
D2_
MCK
1
D1_
MCK
1
D1_
MCK
1
D1_
MCK
2
D1_
MCK
2
GV
GND
DD
DETAIL A
Figure 3. 1295 BGA ball map diagram (detail view A)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
5
Pin assignments and reset states
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SD_
REF_
CLK1
SV
AVDD_
SRDS1
SV
DD
RSRV
_A21
NC_
A27
SGND SD_RX
01
SD_RX SGND
03
SGND
GND
RSRV
_A25
GND
AVDD_ AVDD_
LWE
1
DD
LALE
A
B
C
D
E
F
DDR
CC1
SD_
REF_
CLK1
TEMP_
CATH-
ODE
BV
SV
SV
SV
DD
SD_IMP_
CAL_RX
AGND_
SRDS1
GND
GND
NC_
B26
SGND
SGND
SD_RX
DD
SD_RX
DD
LCS
5
LGPL
0
DD
MVREF
01
03
SV
SV
DD
SV
DD
RSRV
_C32
NC_
C19
NC_
C20
NC_
C26
NC_
C27
SD_RX SGND SD_RX
SGND
LCLK
1
LCLK
0
LGPL
4
TEMP_
ANODE
SD_RX
04
DD
LBCTL
00
02
SV
RSRV
_D32
LAD
27
NC_
D27
SGND
XGND SD_TX SGND
04
SD_RX
04
LAD
09
LGPL
2
LCS
0
LCS
1
LCS
3
LCS
4
LWE
0
SD_RX
00
SD_RX
02
DD
BV
DD
BV
DD
XV
DD
XV
SV
DD
GND
LGPL
5
NC_
E27
XGND
XGND
SGND
LA
21
LAD
08
LGPL
1
LCS
2
SD_TX
01
SD_TX
03
SD_TX
04
DD
BV
DD
BV
DD
XV
DD
XV
DD
SV
DD
SD_TX
03
SD_RX
05
LAD
12
LAD
04
GND
XGND
LA
22
LA
19
GND
LCS
06
SD_RX
05
SD_TX
01
SD_TX
05
XV
DD
SV
DD
LAD
06
SD_TX
00
SD_TX
02
SD_TX
05
LAD
07
LA
17
LCS
7
NC_
G27
XGND
XGND
SGND
XGND
SGND
LA
28
LA
25
GND
LAD
11
G
H
J
BV
DD
XV
DD
XV
DD
LA
18
LAD
05
LAD
03
LGPL
3
NC_
H27
SD_TX
00
XGND SD_TX
02
XGND
SD_RX
06
LA
29
LA
23
LA
20
SD_RX
06
XV
DD
XV
XV
XV
XV
DD
SV
DD
LDP
00
LA
16
LAD
02
GND
XGND
XGND
XGND
XGND
SD_TX
06
SGND
LA
30
LA
26
GND
LAD
10
GND
SD_TX
06
DD
DD
DD
SENSE-
GND_PL
02
BV
DD
BV
DD
SV
DD
LAD
00
XGND
SD_TX
07
SGND
SD_RX
07
LDP
1
GND
GND
LA
27
LA
24
SD_RX
07
SD_TX
07
K
L
SENSE-
VDD_PL
02
XV
DD
SV
DD
LAD
01
XGND SD_RX SD_RX
SGND
VDD_PL GND
VDD_PL GND VDD_PL GND VDD_PL
RSRV
_L28
08
08
XV
DD
SV
SD_TX
08
SD_RX
09
XGND
XGND
SGND
GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL
GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL
GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND
SD_RX
09
SD_TX
08
DD
RSRV
_M28
M
N
P
R
T
XV
DD
SV
DD
RSRV
_N28
XGND
XGND
XGND SD_TX
09
SGND
SD_TX
09
XV
DD
XV
SD_TX
SD_TX
10
SD_RX
10
XGND
SD_RX
10
RSRV
_P28
DD
10
XV
DD
XV
DD
SV
DD
SV
DD
AVDD_
SRDS4
XGND
XGND
SGND
SGND
XV
DD
XV
DD
AGND_
SRDS2
SD_TX
11
SD_RX
11
SGND
AGND_
SRDS4
SD_TX
11
SD_RX
11
XV
DD
SV
DD
AVDD_
SRDS2
SD_
REF_
CLK4
XGND
XGND
XGND
XGND
SGND
VDD_PL GND
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL
RSRV
_U32
RSRV
_U35
U
V
SD_
REF_
CLK2
SD_
REF_
CLK2
XV
DD
XV
DD
SV
DD
SD_
REF_
CLK4
SGND
GND VDD_PL GND
VDD_PL GND VDD_PL GND VDD_PL GND
DETAIL B
Figure 4. 1295 BGA ball map diagram (detail view B)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
6
Freescale Semiconductor
Pin assignments and reset states
DETAIL C
D1_
MCK
0
D2_
MCK
3
D2_
MCK
3
D2_
MCK
0
D2_
MCK
0
D1_
MCK
0
D1_
MCK
3
D1_
MCK
3
GV
DD
GND
GND
GND
GND
GND
VDD_PL
GND
VDD_PL
GND
GND
GND
GND
GND
W
Y
D2_
MDIC
1
D1_
D2_
MAPAR_
OUT
D1_
MAPAR_
OUT
GV
DD
GV
DD
GND
GND
D2_MA
00
D1_MA
MBA
VDD_PL
GND
VDD_PL
GND
GND
GND
GND
GND
00
1
D2_
MBA
1
D2_
MBA
0
D2_
MDIC
0
D1_
MDIC
1
D1_
MBA
0
GV
DD
D1_
MRAS
D2_MA
10
D1_MA
10
GND
VDD_PL
GND
VDD_PL
GND
GND
GND
GND
GND
AA
AB
AC
AD
AE
AF
AG
AH
AJ
D1_
MDQ
36
D1_
MDQ
37
D2_
MCS
2
D1_
MCS
2
D2_
MRAS
D2_
MWE
GV
DD
D1_
MWE
GV
DD
GND
VDD_PL
GND
GND
GND
GND
GND
GND
GND
D2_
MCS
0
D1_
MDQ
33
D1_
MDQ
32
D1_
D1_
GV
DD
D2_
MCAS
GV
DD
D2_MA
13
GND
VDD_PL
GND
VDD_PL
GND
GND
GND
GND
GND
MCS
MCAS
0
D2_
MODT
2
D2_
MODT
0
D1_
MDQS
4
D1_
MDM
4
D1_
MODT
2
D1_
GND
D1_
MDQS
4
GV
DD
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
MODT
0
D2_
MODT
3
D1_
MDQ
38
D1_
MDQ
39
D2_
MCS
1
D2_
MCS
3
D1_
MCS
1
GV
DD
GV
DD
D1_MA
13
GND
VDD_PL
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
D2_
MODT
1
D2_
MDQ
37
D2_
MDQ
36
D1_
MDQ
34
D1_
MDQ
35
D1_
MODT
3
D1_
MCS
3
SENSE- SENSE-
VDD_PL GND_PL
GV
DD
GV
DD
GND
VDD_PL
VDD_PL
GND
VDD_PL
GND
1
1
D2_
MDM
4
D2_
MDQ
33
D2_
MDQ
32
D1_
MDQ
40
D1_
MDQ
45
D1_
MDQ
44
D1_
MODT
1
GV
DD
NC_
AG15
IIC4_
SCL
IRQ
08
IRQ
06
GND
GND
RSRV
RSRV
_AG11 _AG12
D2_
MDQ
38
D2_
MDQS
4
D1_
MDQS
5
D1_
MDM
5
D1_
MDQ
41
D2_
MDQS
4
D1_
MDQS
5
GV
DD
GV
DD
IIC1_
SCL
IRQ
10
IRQ
01
IRQ
04
GND
RSRV RSRV
GND
MSRCID
2
_AH11 _AH12
OV
D2_
MDQ
35
D2_
MDQ
34
D2_
MDQ
39
D1_
MDQ
46
D1_
MDQ
47
D1_
MDQ
42
D1_
MDQ
43
GV
DD
GV
DD
OV
DD
OV
DD
IRQ
05
IRQ
03
IRQ
00
EVT
0
GND
GND
DD
IO_
VSEL
2
D2_
MDQ
45
D2_
MDQ
44
D1_
MDQ
53
D1_
MDQ
52
GV
DD
GV
DD
IIC3_
SCL
IRQ_
OUT
IRQ
09
IRQ
02
EVT
3
EVT
1
RSRV
_AK1
GND
GND
GND
RSRV
_AK2
AK
AL
AM
AN
AP
AR
AT
IO_
VSEL
0
D2_
MDM
5
D2_
MDQ
41
D2_
MDQ
40
D1_
MDQ
49
D1_
MDQ
48
D1_
MDM
6
GV
DD
GV
DD
OV
DD
IIC2_
SDA
IIC4_
SDA
IRQ
11
RSRV
_AL2
GND
GND
RSRV
_AL1
SCAN_
MODE
IO_
VSEL
3
D2_
MDQ
52
D2_
MDQS
5
D2_
MDQ
46
D2_
MDQ
47
D1_
MDQS
6
D2_
MDQS
5
D1_
MDQS
6
GV
DD
GV
DD
IIC3_
SDA
IIC2_
SCL
VID_
VDD_CA
_CB3
IRQ
07
EVT
4
GND
GND
GND
D2_
MDQ
48
D2_
MDQ
53
D2_
MDQ
42
D2_
MDQ
43
D1_
MDQ
54
D1_
MDQ
55
D1_
MDQ
50
D1_
MDQ
51
GV
DD
GV
DD
OV
DD
IIC1_
SDA
VID_
VDD_CA
_CB2
EVT
2
GND
GND
GND
TDI
IO_
D2_
MDQS
6
D2_
MDM
6
D2_
MDQ
49
D2_
MDQ
56
D2_
MDM
7
D2_
MDQ
58
D1_
MDQ
60
D1_
MDQ
63
GV
DD
GV
DD
OV
DD
TEST_
SEL2
VID_
VDD_CA
_CB1
GND
GND
TDO
PORESET VSEL
1
D2_
MDQS
6
D2_
MDQ
54
D2_
MDQ
60
D2_
MDQS
7
D2_
MDQ
62
D1_
MDQ
61
D1_
MDQ
57
D1_
MDQ
62
D1_
MDQ
59
GV
DD
GV
DD
GV
DD
GND
GND
GND
GND
MDVAL
HRESET
D2_
MDQ
50
D2_
MDQ
51
D2_
MDQ
55
D2_
MDQ
61
D2_
MDQ
57
D2_
MDQS
7
D2_
MDQ
63
D2_
MDQ
59
D1_
MDQ
56
D1_
MDM
7
D1_
MDQS
7
D1_
MDQS
7
D1_
MDQ
58
OV
DD
VID_
VDD_CA
_CB0
AVDD_
POVDD
RESET_
REQ
CC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 5. 1295 BGA ball map diagram (detail view C)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
7
Pin assignments and reset states
DETAIL D
XV
SV
DD
XGND SD_TX
12
SGND
SD_RX
12
SD_RX
12
GND
GND
GND
GND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND
VDD_PL
NC_
W27
SD_TX
12
DD
W
XV
SV
DD
SD_TX
13
SD_RX
13
XGND
XGND
SGND
SD_RX
13
GND
GND
GND
GND VDD_PL GND VDD_PL GND VDD_PL GND
SD_TX
13
DD
Y
XV
DD
SV
DD
SD_TX
14
SD_RX
14
SD1_IMP
_CAL_TX
XGND
SGND
SD_TX
14
SD_RX
14
GND
GND VDD_PL GND VDD_PL GND VDD_PL
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
XV
DD
XV
DD
SV
DD
SD_TX SD_TX
18 18
XGND
SD_TX
15
SGND
GND VDD_PL GND VDD_PL GND VDD_PL GND
SD_TX
15
SD_
REF_
CLK3
SD_
REF_
CLK3
XV
DD
SD_RX
15
S1V
XGND
XGND
SD_RX
15
GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL
V
DD
DD_
LL
XV
DD
SV
DD
VDD_ SD_RX XGND
XGND
SGND
GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND
RSRV
_AD33
RSRV
_AD34
LP
18
LP_
TEMP_
DETECT
XV
SV
DD
AVDD_ AGND_
SRDS3 SRDS3
SD_TX
16
SD_RX
18
SGND
VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND
GND
SD_TX
16
DD
XV
DD
SV
SD_RX
16
SD1_IMP SD_RX SD_RX SGND
_CAL_RX 19 19
XGND
SGND
DD
SD_RX
16
GND VDD_PL GND VDD_PL GND VDD_PL GND
SD_IMP_
CAL_TX
DMA2_
DACK
0
IO_
VSEL
4
SDHC_
DAT
3
OV
CV
SV
DD
SD_TX
17
SD_RX
SD_RX
17
17
SD_TX SD_TX X1V
S1V
RSRV
_AG29
XGND
SGND
SGND
GPIO
07
SDHC_
CMD
SD_TX
17
DD
DD
DD
DD
19
19
USB1_
VDD_
1P0
USB2_
VDD_
1P0
XV
DD
SV
SGND
SPI_
MISO
GND
USB2_
SD_PLL4 XGND
_TPD
GND
GPIO
04
UART2_
CTS
USB1_
AGND
EC_RX_
ER
DD
MSRCID
0
AGND
TSEC_
1588_ALARM
_OUT1
TSEC_
1588_PULSE
_OUT2
USB1_
VDD_
3P3
USB2_ USB2_
_VDD_
3P3
DMA2_
DREQ
0
EC_XTRNL
EMI2_
OV
DD
CV
DD
LV
EMI1_
MDC
GND
USB1_
AGND
GPIO
05
UART2_
SOUT
SPI_CS
1
DD
MSRCID
1
VDD_
3P3
_TX_STMP
MDIO
2
EC1_
TSEC_
TSEC_
USB1_
VBUS_
CLMP
USB2_
VBUS_
CLMP
EC_XTRNL EC_XTRNL
_RX_STMP _RX_STMP
LV
EMI2_
MDC
CLK_
OUT
GND
GND
SPI_
CLK
USB2_
UID
GPIO
06
GPIO
01
UART2_
RTS
DD
USB2_
UID
GTX_ 1588_ALARM 1588_TRIG
CLK125
_OUT2
_IN2
2
1
USB1_
VDD_1P8_
DECAP
TSEC_
1588_PULSE
_OUT1
USB2_
_DD_1P8_
DECAP
EC2_
GTX_
CLK125
USB1_
VDD_
3P3
TSEC_
1588_TRIG
_IN1
TSEC_
1588_CLK
_IN
DMA1_
DACK
0
OV
DD
LV
DD
USB2_
AGND
EMI1_
MDIO
USB1
_AGND
GND
GND
GPIO
00
SDHC_
CLK
UART1_
SOUT
USB1_
IBIAS_
REXT
USB2_
IBIAS_
REXT
EC1_
RXD
3
TSEC_
EC_XTRNL
SDHC_
DAT
02
LV
EC1_
RX_DV
EC1_
RX_CLK
CLKIN
GND
GND
USB_
USB1_
AGND
CKSTP_ GPIO
OUT
USB2_
AGND
SPI_CS
3
UART1_
RTS
DD
1588_CLK_ _TX_STMP
02
OUT
1
EC2_
RXD
2
EC1_
RXD
2
EC1_
RXD
1
EC1_
RXD
0
EC2_
GTX_
CLK
DMA1_
DDONE
00
USB2_ USB2_
AGND
OV
LV
TMP_
GPIO
DETECT
GND
USB2_
AGND
USB2_
AGND
SPI_CS
0
DD UART2_
SIN
DD
RTC
AGND
03
EC2_
TXD
2
EC2_
RXD
1
EC2_
RXD
3
EC1_
TXD
3
EC1_
GTX_
CLK
DMA2_ DMA1_
SDHC_
DAT
0
USB2_
UDP
CV
DD
LV
USB2_
UDM
GND
GND
USB2_
AGND
GND
USB2_
AGND
UART1_
DD
DDONE
0
DREQ
0
CTS
TCK
GND
EC2_
TXD
1
EC1_
TXD
1
USB1_
AGND
OV
DD
USB1_
AGND
LV
USB1_
AGND
EC2_
TX_EN
EC2_
RX_DV
EC1_
TX_EN
USB1_
AGND
GND
UART1_
SIN
SPI_CS
2
DD
TRST
TMS
ASLEEP
EC2_
TXD
0
EC2_
TXD
3
EC2_
RXD
0
EC1_
TXD
2
EC1_
TXD
0
SDHC_
DAT
1
USB1_
AGND
USB1_
AGND
SPI_
MOSI
EC2_
RX_CLK
USB1_
UDM
USB1_
UDP
GND
AVDD_ AVDD_
FM
TEST_
SEL
SYSCLK
PLAT
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Figure 6. 1295 BGA ball map diagram (detail view D)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
8
Freescale Semiconductor
Pin assignments and reset states
1.2
Pinout list
This table provides the pinout listing for the 1295 FC-PBGA package by bus.
Table 1. Pins listed by bus
Package
pin number type supply
Pin Power
Signal
Signal description
Notes
DDR SDRAM Memory interface 1
D1_MDQ00
D1_MDQ01
D1_MDQ02
D1_MDQ03
D1_MDQ04
D1_MDQ05
D1_MDQ06
D1_MDQ07
D1_MDQ08
D1_MDQ09
D1_MDQ10
D1_MDQ11
D1_MDQ12
D1_MDQ13
D1_MDQ14
D1_MDQ15
D1_MDQ16
D1_MDQ17
D1_MDQ18
D1_MDQ19
D1_MDQ20
D1_MDQ21
D1_MDQ22
D1_MDQ23
D1_MDQ24
D1_MDQ25
D1_MDQ26
D1_MDQ27
D1_MDQ28
D1_MDQ29
D1_MDQ30
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
A17
D17
C14
A14
C17
B17
A15
B15
D15
G15
E12
G12
F16
E15
E13
F13
C8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D12
E9
E10
C11
C10
E6
E7
F7
F11
H10
J10
F10
F8
H7
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
9
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
D1_MDQ31
D1_MDQ32
D1_MDQ33
D1_MDQ34
D1_MDQ35
D1_MDQ36
D1_MDQ37
D1_MDQ38
D1_MDQ39
D1_MDQ40
D1_MDQ41
D1_MDQ42
D1_MDQ43
D1_MDQ44
D1_MDQ45
D1_MDQ46
D1_MDQ47
D1_MDQ48
D1_MDQ49
D1_MDQ50
D1_MDQ51
D1_MDQ52
D1_MDQ53
D1_MDQ54
D1_MDQ55
D1_MDQ56
D1_MDQ57
D1_MDQ58
D1_MDQ59
D1_MDQ60
D1_MDQ61
D1_MDQ62
D1_MDQ63
D1_MECC0
Data
H9
AC7
AC6
AF6
AF7
AB5
AB6
AE5
AE6
AG5
AH9
AJ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
AJ10
AG8
AG7
AJ6
Data
Data
Data
Data
AJ7
Data
AL9
Data
AL8
Data
AN10
AN11
AK8
AK7
AN7
AN8
AT9
Data
Data
Data
Data
Data
Data
Data
AR10
AT13
AR13
AP9
AR9
AR12
AP12
K9
Data
Data
Data
Data
Data
Data
Error Correcting Code
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
10
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
D1_MECC1
D1_MECC2
D1_MECC3
D1_MECC4
D1_MECC5
D1_MECC6
D1_MECC7
D1_MAPAR_ERR
D1_MAPAR_OUT
D1_MDM0
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Address Parity Error
Address Parity Out
Data Mask
J5
L10
M10
J8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
J7
L7
L9
N8
Y7
O
A16
D14
D11
G11
AD7
AH8
AL11
AT10
K8
O
D1_MDM1
Data Mask
O
D1_MDM2
Data Mask
O
D1_MDM3
Data Mask
O
D1_MDM4
Data Mask
O
D1_MDM5
Data Mask
O
D1_MDM6
Data Mask
O
D1_MDM7
Data Mask
O
D1_MDM8
Data Mask
O
D1_MDQS0
D1_MDQS1
D1_MDQS2
D1_MDQS3
D1_MDQS4
D1_MDQS5
D1_MDQS6
D1_MDQS7
D1_MDQS8
D1_MDQS0
D1_MDQS1
D1_MDQS2
D1_MDQS3
D1_MDQS4
D1_MDQS5
D1_MDQS6
Data Strobe
C16
G14
D9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data Strobe
Data Strobe
Data Strobe
G9
Data Strobe
AD5
AH6
AM10
AT12
K6
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
B16
F14
D8
Data Strobe
Data Strobe
Data Strobe
G8
Data Strobe
AD4
AH5
AM9
Data Strobe
Data Strobe
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
11
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
D1_MDQS7
D1_MDQS8
D1_MBA0
D1_MBA1
D1_MBA2
D1_MA00
D1_MA01
D1_MA02
D1_MA03
D1_MA04
D1_MA05
D1_MA06
D1_MA07
D1_MA08
D1_MA09
D1_MA10
D1_MA11
D1_MA12
D1_MA13
D1_MA14
D1_MA15
D1_MWE
D1_MRAS
D1_MCAS
D1_MCS0
D1_MCS1
D1_MCS2
D1_MCS3
D1_MCKE0
D1_MCKE1
D1_MCKE2
D1_MCKE3
D1_MCK0
D1_MCK1
Data Strobe
Data Strobe
Bank Select
Bank Select
Bank Select
Address
AT11
K5
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AA8
Y10
M8
Y9
Address
U6
Address
U7
Address
U9
Address
U10
T8
Address
Address
T9
Address
R8
Address
R7
Address
P6
Address
AA7
P7
Address
Address
N6
Address
AE8
M7
Address
Address
L6
Write Enable
Row Address Strobe
Column Address Strobe
Chip Select
Chip Select
Chip Select
Chip Select
Clock Enable
Clock Enable
Clock Enable
Clock Enable
Clock
AB8
AA10
AC10
AC9
AE9
AB9
AF9
P10
R10
P9
N9
W6
V6
Clock
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
12
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
D1_MCK2
D1_MCK3
D1_MCK0
D1_MCK1
D1_MCK2
D1_MCK3
D1_MODT0
D1_MODT1
D1_MODT2
D1_MODT3
D1_MDIC0
D1_MDIC1
Clock
V8
W9
O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
16
16
Clock
Clock Complements
Clock Complements
Clock Complements
Clock Complements
On Die Termination
On Die Termination
On Die Termination
On Die Termination
Driver Impedance Calibration
Driver Impedance Calibration
W5
O
V5
O
V9
O
W8
O
AD10
AG10
AD8
AF10
T6
O
O
O
O
I/O
I/O
AA5
DDR SDRAM Memory interface 2
D2_MDQ00
D2_MDQ01
D2_MDQ02
D2_MDQ03
D2_MDQ04
D2_MDQ05
D2_MDQ06
D2_MDQ07
D2_MDQ08
D2_MDQ09
D2_MDQ10
D2_MDQ11
D2_MDQ12
D2_MDQ13
D2_MDQ14
D2_MDQ15
D2_MDQ16
D2_MDQ17
D2_MDQ18
D2_MDQ19
D2_MDQ20
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
C13
A12
B9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A8
A13
B13
B10
A9
A7
D6
A4
B4
C7
B7
C5
D5
B1
B3
D3
E1
A3
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
13
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
D2_MDQ21
D2_MDQ22
D2_MDQ23
D2_MDQ24
D2_MDQ25
D2_MDQ26
D2_MDQ27
D2_MDQ28
D2_MDQ29
D2_MDQ30
D2_MDQ31
D2_MDQ32
D2_MDQ33
D2_MDQ34
D2_MDQ35
D2_MDQ36
D2_MDQ37
D2_MDQ38
D2_MDQ39
D2_MDQ40
D2_MDQ41
D2_MDQ42
D2_MDQ43
D2_MDQ44
D2_MDQ45
D2_MDQ46
D2_MDQ47
D2_MDQ48
D2_MDQ49
D2_MDQ50
D2_MDQ51
D2_MDQ52
D2_MDQ53
D2_MDQ54
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
A2
D1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D2
F4
F5
H4
H6
E4
E3
H3
H1
AG4
AG2
AJ3
AJ1
AF4
AF3
AH1
AJ4
AL6
AL5
AN4
AN5
AK5
AK4
AM6
AM7
AN1
AP3
AT1
AT2
AM1
AN2
AR3
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
14
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
D2_MDQ55
D2_MDQ56
D2_MDQ57
D2_MDQ58
D2_MDQ59
D2_MDQ60
D2_MDQ61
D2_MDQ62
D2_MDQ63
D2_MECC0
D2_MECC1
D2_MECC2
D2_MECC3
D2_MECC4
D2_MECC5
D2_MECC6
D2_MECC7
D2_MAPAR_ERR
D2_MAPAR_OUT
D2_MDM0
Data
AT3
AP5
AT5
AP8
AT8
AR4
AT4
AR7
AT7
J1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data
Data
Data
Data
Data
Data
Data
Data
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Error Correcting Code
Address Parity Error
Address Parity Out
Data Mask
K3
M5
N5
J4
J2
L3
L4
N2
Y1
O
B12
B6
O
D2_MDM1
Data Mask
O
D2_MDM2
Data Mask
C4
O
D2_MDM3
Data Mask
G3
O
D2_MDM4
Data Mask
AG1
AL3
AP2
AP6
K2
O
D2_MDM5
Data Mask
O
D2_MDM6
Data Mask
O
D2_MDM7
Data Mask
O
D2_MDM8
Data Mask
O
D2_MDQS0
D2_MDQS1
D2_MDQS2
D2_MDQS3
D2_MDQS4
D2_MDQS5
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
A10
A5
I/O
I/O
I/O
I/O
I/O
I/O
C2
G6
AH2
AM4
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
15
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
D2_MDQS6
D2_MDQS7
D2_MDQS8
D2_MDQS0
D2_MDQS1
D2_MDQS2
D2_MDQS3
D2_MDQS4
D2_MDQS5
D2_MDQS6
D2_MDQS7
D2_MDQS8
D2_MBA0
D2_MBA1
D2_MBA2
D2_MA00
D2_MA01
D2_MA02
D2_MA03
D2_MA04
D2_MA05
D2_MA06
D2_MA07
D2_MA08
D2_MA09
D2_MA10
D2_MA11
D2_MA12
D2_MA13
D2_MA14
D2_MA15
D2_MWE
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Data Strobe
Bank Select
Bank Select
Bank Select
Address
AR1
AR6
L1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A11
A6
C1
G5
AH3
AM3
AP1
AT6
K1
AA3
AA1
M1
Y4
O
O
O
Address
U1
O
Address
U4
O
Address
T1
O
Address
T2
O
Address
T3
O
Address
R1
O
Address
R4
O
Address
R2
O
Address
P1
O
Address
AA2
P3
O
Address
O
Address
N1
O
Address
AC4
N3
O
Address
O
Address
M2
AB2
AB1
AC3
O
Write Enable
Row Address Strobe
Column Address Strobe
O
D2_MRAS
D2_MCAS
O
O
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
16
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
D2_MCS0
D2_MCS1
D2_MCS2
D2_MCS3
D2_MCKE0
D2_MCKE1
D2_MCKE2
D2_MCKE3
D2_MCK0
D2_MCK1
D2_MCK2
D2_MCK3
D2_MCK0
D2_MCK1
D2_MCK2
D2_MCK3
D2_MODT0
D2_MODT1
D2_MODT2
D2_MODT3
D2_MDIC0
D2_MDIC1
Chip Select
AC1
AE1
AB3
AE2
R5
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
16
Chip Select
Chip Select
Chip Select
Clock Enable
Clock Enable
T5
Clock Enable
P4
Clock Enable
M4
Clock
W3
V3
Clock
Clock
V1
Clock
W2
W4
V4
Clock Complements
Clock Complements
Clock Complements
Clock Complements
On Die Termination
On Die Termination
On Die Termination
On Die Termination
Driver Impedance Calibration
Driver Impedance Calibration
V2
W1
AD2
AF1
AD1
AE3
AA4
Y6
Local bus controller interface
LAD00
LAD01
LAD02
LAD03
LAD04
LAD05
LAD06
LAD07
LAD08
LAD09
LAD10
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
K26
L26
J26
H25
F25
H24
G24
G23
E23
D23
J22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
3
3
3
3
3
3
3
3
3
3
3
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
17
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
LAD11
LAD12
LAD13
LAD14
LAD15
LAD16
LAD17
LAD18
LAD19
LAD20
LAD21
LAD22
LAD23
LAD24
LAD25
LAD26
LAD27
LAD28
LAD29
LAD30
LAD31
LDP0
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Muxed Data/Address
Data Parity
G22
F19
J18
K18
J17
J25
G25
H23
F22
H22
E21
F21
H21
K21
G20
J20
D26
E18
F18
J15
F17
J24
K23
H17
H16
K20
G19
H19
J19
G18
D19
D20
E20
D21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
3
3
3
3
3
3
3
3,35
3,35
3,35
3,35
3,35
3
3
3,35
32
—
—
—
—
—
—
—
—
—
—
35
35
35
35
5
LDP1
Data Parity
LDP2
Data Parity
LDP3
Data Parity
LA27
Address
LA28
Address
O
LA29
Address
O
LA30
Address
O
LA31
Address
O
LCS0
Chip Selects
O
LCS1
Chip Selects
O
5
LCS2
Chip Selects
O
5
LCS3
Chip Selects
O
5
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
18
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
LCS4
Chip Selects
Chip Selects
Chip Selects
Chip Selects
Write Enable
Write Enable
Write Enable
Write Enable
Buffer Control
Address Latch Enable
D22
B23
F24
G26
D24
A24
J16
O
O
O
O
O
O
O
O
O
I/O
O
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
5
5
LCS5
LCS6
5
LCS7
5
LWE0
—
—
—
—
—
—
3, 4
LWE1
LWE2
LWE3
K15
C22
A23
B25
LBCTL
LALE
LGPL0/LFCLE
UPM General Purpose Line 0/
LFCLE—FCM
LGPL1/LFALE
LGPL2/LOE/LFRE
LGPL3/LFWP
UPM General Purpose Line 1/
LFALE—FCM
E25
D25
H26
C25
E26
O
O
BVDD
BVDD
BVDD
BVDD
BVDD
3, 4
3, 4
3, 4
39
UPM General Purpose Line 2/
LOE_B—Output Enable
UPM General Purpose LIne 3/
LFWP_B—FCM
O
LGPL4/LGTA/LUPWAIT/LPBSE
LGPL5
UPM General Purpose Line 4/
LGTA_B—FCM
I/O
O
UPM General Purpose Line 5 /
Amux
3, 4
LCLK0
LCLK1
Local Bus Clock
Local Bus Clock
C24
C23
O
O
BVDD
BVDD
—
—
DMA
DMA1_DREQ0/GPIO18
DMA1 Channel 0 Request
DMA1 Channel 0 Acknowledge
DMA1 Channel 0 Done
AP21
AL19
AN21
AJ20
AG19
AP20
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
26
26
27
26
26
26
DMA1_DACK0/GPIO19
O
O
I
DMA1_DDONE0
DMA2_DREQ0/GPIO20/ALT_MDVAL
DMA2_DACK0/EVT7/ALT_MDSRCID0
DMA2_DDONE0/EVT8/ALT_MDSRCID1
DMA2 Channel 0 Request
DMA2 Channel 0 Acknowledge
DMA2 Channel 0 Done
O
O
USB Port 1
USB_V
_
_
_
USB1_UDP
USB1 PHY Data Plus
AT27
AT26
AK25
I/O
I/O
I
—
—
38
DD
3P3
USB_V
USB1_UDM
USB1 PHY Data Minus
DD
3P3
USB_V
USB1_VBUS_CLMP
USB1 PHY VBUS Divided Signal
DD
3P3
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
19
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Package
pin number type supply
Pin Power
Signal
Signal description
Notes
USB1_V
_1P8
USB1_UID
USB1 PHY ID Detect
AK24
I
—
DD
_DECAP
OVDD
OVDD
OVDD
USB1_DRVVBUS/GPIO04
USB1_PWRFAULT/GPIO05
USB_CLKIN
USB1 5V Supply Enable
USB1 Power Fault
AH21
AJ21
AM24
O
I
26,38
26,38
—
USB PHY Clock Input
I
USB Port 2
USB_V
_
USB2_UDP
USB2 PHY Data Plus
AP27
AP26
AK26
AK27
I/O
—
—
38
—
DD
3P3
USB_V
_
USB2_UDM
USB2 PHY Data Minus
I/O
DD
3P3
USB_V
_
USB2_VBUS_CLMP
USB2_UID
USB2 PHY VBUS Divided Signal
USB2 PHY ID Detect
I
I
DD
3P3
USB2_V
_1P8
DD
_DECAP
OVDD
OVDD
USB2_DRVVBUS/GPIO06
USB2_PWRFAULT/GPIO07
USB2 5V Supply Enable
USB2 Power Fault
AK21
AG20
O
O
26,38
26,38
Programmable Interrupt controller
IRQ00
External Interrupts
External Interrupts
External Interrupts
External Interrupts
External Interrupts
External Interrupts
External Interrupts
External Interrupts
External Interrupts
External Interrupts
External Interrupts
External Interrupts
Interrupt Output
AJ16
AH16
AK12
AJ15
AH17
AJ13
AG17
AM13
AG13
AK11
AH14
AL12
AK14
I
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
26
26
26
26
26
26
26
26
26
IRQ01
IRQ02
I
IRQ03/GPIO21
IRQ04/GPIO22
IRQ05/GPIO23
IRQ06/GPIO24
IRQ07/GPIO25
IRQ08/GPIO26
IRQ09/GPIO27
IRQ10/GPIO28
IRQ11/GPIO29
IRQ_OUT/EVT9
I
I
I
I
I
I
I
I
I
O
OVDD 1, 2, 26
Trust
TMP_DETECT
Tamper Detect
AN19
AE28
I
I
OVDD
27
—
LP_TMP_DETECT
Low Power Tamper Detect
VDD_LP
eSDHC
SDHC_CMD
Command/Response
AG23
I/O
CVDD
—
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
20
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
SDHC_DAT0
SDHC_DAT1
SDHC_DAT2
SDHC_DAT3
Data
AP24
AT24
AM23
AG22
AN29
AJ28
AR29
AM29
AL23
AK13
AM14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
—
—
Data
Data
—
Data
—
SDHC_DAT4/SPI_CS0
SDHC_DAT5/SPI_CS1
SDHC_DAT6/SPI_CS2
SDHC_DAT7/SPI_CS3
SDHC_CLK
Data
26, 31
26, 31
26, 31
26, 31
—
Data
Data
Data
Host to Card Clock
Card Detection
Card Write Protection
SDHC_CD/IIC3_SCL/GPIO16
SDHC_WP/IIC3_SDA/GPIO17
I
OVDD 26,27,31
OVDD 26,27,31
I
eSPI
SPI_MOSI
Master Out Slave In
Master In Slave Out
eSPI clock
AT29
AH28
AK29
AN29
AJ28
AR29
AM29
I/O
I
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
—
—
—
26
26
26
26
SPI_MISO
SPI_CLK
O
O
O
O
O
SPI_CS0/SDHC_DAT4
SPI_CS1/SDHC_DAT5
SPI_CS2/SDHC_DAT6
SPI_CS3/SDHC_DAT7
eSPI chip select
eSPI chip select
eSPI chip select
eSPI chip select
IEEE 1588
TSEC_1588_CLK_IN
Clock In
AL35
AL36
AK36
AJ36
AK35
AM30
AL30
AJ34
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
—
—
—
—
26
—
—
26
TSEC_1588_TRIG_IN1
Trigger In 1
Trigger In 2
Alarm Out 1
I
TSEC_1588_TRIG_IN2/EC1_RX_ER
TSEC_1588_ALARM_OUT1
I
O
O
O
O
O
TSEC_1588_ALARM_OUT2/EC1_COL/GPIO30 Alarm Out 2
TSEC_1588_CLK_OUT
Clock Out
TSEC_1588_PULSE_OUT1
Pulse Out1
TSEC_1588_PULSE_OUT2/EC1_CRS/GPIO31 Pulse Out2
Ethernet Management interface 1
EMI1_MDC
EMI1_MDIO
Management Data Clock
Management Data In/Out
AJ33
AL32
O
LVDD
LVDD
—
—
I/O
Ethernet Management interface 2
EMI2_MDC
Management Data Clock
AK30
O
1.2 V 2, 18, 22
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
21
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
EMI2_MDIO
Management Data In/Out
AJ30
I/O
1.2 V 2, 18, 22
Ethernet Reference Clock
EC1_GTX_CLK125/
EC1_TX_CLK
Reference Clock (RGMII)
Transmit Clock (MII)
AK34
AL33
I
I
LVDD
LVDD
27
27
EC2_GTX_CLK125/
EC2_TX_CLK
Reference Clock (RGMII)
Transmit Clock (MII)
Ethernet External Timestamping
EC_XTRNL_TX_STMP1
External Timestamp Transmit 1
External Timestamp Receive 1
External Timestamp Transmit 2
External Timestamp Receive 2
AM31
AK32
AJ31
AK31
I
I
I
I
LVDD
LVDD
LVDD
LVDD
—
—
—
—
EC_XTRNL_RX_STMP1
EC_XTRNL_TX_STMP2/EC2_COL
EC_XTRNL_RX_STMP2/EC2_CRS
Three-Speed Ethernet controller 1
EC1_TXD3
EC1_TXD2
EC1_TXD1
EC1_TXD0
EC1_TX_EN
Transmit Data
Transmit Data
Transmit Data
Transmit Data
Transmit Enable
AP36
AT34
AR34
AT35
AR36
AP35
O
O
O
O
O
O
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
35
35
35
35
15
26
EC1_GTX_CLK/
EC1_TX_ER
Transmit Clock Out (RGMII)
Transmit Error (MII)
EC1_RXD3
Receive Data
AM33
AN34
AN35
AN36
AM34
AM36
AK36
AK35
AJ34
I
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
27
27
27
27
27
27
—
26
26
EC1_RXD2
Receive Data
EC1_RXD1
Receive Data
I
EC1_RXD0
Receive Data
I
EC1_RX_DV
Receive Data Valid
Receive Clock
Receive Error (MII)
I
EC1_RX_CLK
I
EC1_RX_ER/TSEC_1588_TRIG_IN2
I
EC1_COL/GPIO30/TSEC_1588_ALARM_OUT2 Collision Detect (MII)
EC1_CRS/GPIO31/TSEC_1588_PULSE_OUT2 Carrier Sense (MII)
O
O
Three-Speed Ethernet controller 2
EC2_TXD3
EC2_TXD2
EC2_TXD1
EC2_TXD0
EC2_TX_EN
Transmit Data
Transmit Data
Transmit Data
Transmit Data
Transmit Enable
AT31
AP30
AR30
AT30
AR31
O
O
O
O
O
LVDD
LVDD
LVDD
LVDD
LVDD
35
35
35
35
15
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
22
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
EC2_GTX_CLK/
EC2_TX_ER
Transmit Clock Out (RGMII)
Transmit Error (MII)
AN31
O
LVDD
26
EC2_RXD3
EC2_RXD2
EC2_RXD1
EC2_RXD0
EC2_RX_DV
EC2_RX_CLK
EC2_RX_ER
Receive Data
AP33
AN32
AP32
AT32
AR33
AT33
AH29
AJ31
AK31
I
I
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
27
27
Receive Data
Receive Data
I
26, 27
26, 27
27
Receive Data
I
Receive Data Valid
Receive Clock
I
I
27
Receive Error (MII)
Collision Detect (MII)
Carrier Sense (MII)
I
—
EC2_COL/EC_XTRNL_TX_STMP2
EC2_CRS/EC_XTRNL_RX_STMP2
O
O
26
26
UART
UART1_SOUT/GPIO8
Transmit Data
Transmit Data
Receive Data
Receive Data
Ready to Send
Ready to Send
Clear to Send
Clear to Send
AL22
AJ22
AR23
AN23
AM22
AK23
AP22
AH23
O
O
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
26
26
26
26
26
26
26
26
UART2_SOUT/GPIO9
UART1_SIN/GPIO10
UART2_SIN/GPIO11
I
UART1_RTS/UART3_SOUT/GPIO12
UART2_RTS/UART4_SOUT/GPIO13
UART1_CTS/UART3_SIN/GPIO14
UART2_CTS/UART4_SIN/GPIO15
O
O
I
I
I2C interface
IIC1_SCL
Serial Clock
Serial Data
Serial Clock
Serial Data
Serial Clock
Serial Data
Serial Clock
Serial Data
AH15
AN14
AM15
AL14
AK13
AM14
AG14
AL15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
2, 14
2, 14
2, 14
2, 14
IIC1_SDA
IIC2_SCL
IIC2_SDA
IIC3_SCL/SDHC_CD/GPIO16
IIC3_SDA/SDHC_WP/GPIO17
IIC4_SCL/EVT5
IIC4_SDA/EVT6
OVDD 2, 14, 27
OVDD 2, 14, 27
OVDD
OVDD
2, 14
2, 14
SerDes (x20) PCIe, Aurora, 10GE, 1GE, SATA
SD_TX19
SD_TX18
SD_TX17
SD_TX16
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
AG25
AB28
AG31
AE31
O
O
O
O
XVDD
XVDD
XVDD
XVDD
—
—
—
—
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
23
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
SD_TX15
SD_TX14
SD_TX13
SD_TX12
SD_TX11
SD_TX10
SD_TX09
SD_TX08
SD_TX07
SD_TX06
SD_TX05
SD_TX04
SD_TX03
SD_TX02
SD_TX01
SD_TX00
SD_TX19
SD_TX18
SD_TX17
SD_TX16
SD_TX15
SD_TX14
SD_TX13
SD_TX12
SD_TX11
SD_TX10
SD_TX09
SD_TX08
SD_TX07
SD_TX06
SD_TX05
SD_TX04
SD_TX03
SD_TX02
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (positive)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
Transmit Data (negative)
AB33
AA31
Y29
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W31
T30
P31
N33
M31
K31
J33
G33
D34
F31
H30
F29
H28
AG26
AB29
AG32
AE32
AB34
AA32
Y30
W32
T31
P32
N34
M32
K32
J34
F33
E34
E31
G30
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
24
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
SD_TX01
SD_TX00
SD_RX19
SD_RX18
SD_RX17
SD_RX16
SD_RX15
SD_RX14
SD_RX13
SD_RX12
SD_RX11
SD_RX10
SD_RX09
SD_RX08
SD_RX07
SD_RX06
SD_RX05
SD_RX04
SD_RX03
SD_RX02
SD_RX01
SD_RX00
SD_RX19
SD_RX18
SD_RX17
SD_RX16
SD_RX15
SD_RX14
SD_RX13
SD_RX12
SD_RX11
SD_RX10
SD_RX09
SD_RX08
Transmit Data (negative)
Transmit Data (negative)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (positive)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
E29
G28
AF27
AD29
AG36
AF34
AC36
AA36
Y34
O
O
I
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
W36
T34
I
I
P36
I
M36
L34
I
I
K36
I
H36
I
F36
I
D36
I
A31
I
C30
I
A29
I
C28
I
AF28
AE29
AG35
AF33
AC35
AA35
Y33
I
I
I
I
I
I
I
W35
T33
I
I
P35
I
M35
L33
I
I
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
25
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
SD_RX07
SD_RX06
SD_RX05
SD_RX04
SD_RX03
SD_RX02
SD_RX01
SD_RX00
SD_REF_CLK1
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
Receive Data (negative)
K35
H35
F35
C36
B31
D30
B29
D28
A35
I
I
I
I
I
I
I
I
I
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
—
—
—
—
—
—
—
—
—
SerDes Bank 1 PLL Reference
Clock
SD_REF_CLK1
SD_REF_CLK2
SD_REF_CLK2
SD_REF_CLK3
SD_REF_CLK3
SD_REF_CLK4
SD_REF_CLK4
SerDes Bank 1 PLL Reference
Clock Complement
B35
V34
I
I
I
I
I
I
I
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
—
—
—
—
—
—
—
SerDes Bank 2 PLL Reference
Clock
SerDes Bank 2 PLL Reference
Clock Complement
V33
SerDes Bank 3 PLL Reference
Clock
AC32
AC31
U28
SerDes Bank 3 PLL Reference
Clock Complement
SerDes Bank 4 PLL Reference
Clock
SerDes Bank 4 PLL Reference
Clock Complement
V28
General-Purpose Input/Output
GPIO00
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
AL21
AK22
AM20
AN20
AH21
AJ21
AK21
AG20
AL22
AJ22
AR23
AN23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
—
—
—
GPIO01
GPIO02
GPIO03
GPIO04/USB1_DRVVBUS
GPIO05/USB1_PWRFAULT
GPIO06/USB2_DRVVBUS
GPIO07/USB2_PWRFAULT
GPIO08/UART1_SOUT
GPIO09/UART2_SOUT
GPIO10/UART1_SIN
GPIO11/UART2_SIN
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
26
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GPIO12/UART1_RTS/UART3_SOUT
GPIO13/UART2_RTS/UART4_SOUT
GPIO14/UART1_CTS/UART3_SIN
GPIO15/UART2_CTS/UART4_SIN
GPIO16/IIC3_SCL/SDHC_CD
GPIO17/IIC3_SDA/SDHC_WP
GPIO18/DMA1_DREQ0
GPIO19/DMA1_DACK0
GPIO20/DMA2_DREQ0/ALT_MDVAL
GPIO21/IRQ3
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
General Purpose Input / Output
AM22
AK23
AP22
AH23
AK13
AM14
AP21
AL19
AJ20
AJ15
AH17
AJ13
AG17
AM13
AG13
AK11
AH14
AL12
AK35
AJ34
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
LVDD
—
—
—
—
27
27
—
—
—
—
—
—
—
—
—
—
—
—
25
25
GPIO22/IRQ4
GPIO23/IRQ5
GPIO24/IRQ6
GPIO25/IRQ7
GPIO26/IRQ8
GPIO27/IRQ9
GPIO28/IRQ10
GPIO29/IRQ11
GPIO30/TSEC_1588_ALARM_OUT2/EC1_COL General Purpose Input / Output
GPIO31/TSEC_1588_PULSE_OUT2/EC1_CRS General Purpose Input / Output
LVDD
System Control
PORESET
HRESET
Power On Reset
Hard Reset
AP17
AR17
AT16
AM19
I
OVDD
OVDD
OVDD
OVDD
—
1, 2
35
I/O
O
RESET_REQ
CKSTP_OUT
Reset Request
Checkstop Out
O
1, 2
Debug
EVT0
Event 0
Event 1
Event 2
Event 3
Event 4
Event 5
Event 6
Event 7
AJ17
AK17
AN16
AK16
AM16
AG14
AL15
AG19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
20
—
—
—
—
—
—
—
EVT1
EVT2
EVT3
EVT4
EVT5/IIC4_SCL
EVT6/IIC4_SDA
EVT7/DMA2_DACK0/ALT_MSRCID0
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
27
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
EVT8/DMA2_DDONE0/ALT_MSRCID1
EVT9/IRQ_OUT
Event 8
AP20
AK14
AR15
AH20
AJ19
AH18
AJ20
AG19
AP20
AK20
I/O
I/O
O
OVDD
OVDD
OVDD
—
—
—
Event 9
MDVAL
Debug Data Valid
Debug Source ID 0
Debug Source ID 1
Debug Source ID 2
Alternate Debug Data Valid
Alternate Debug Source ID 0
Alternate Debug Source ID 1
Clock Out
MSRCID0
O
OVDD 4,20,35
MSRCID1
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
26
26
26
6
MSRCID2
O
ALT_MDVAL/DMA2_DREQ0/GPIO20
ALT_MSRCID0/DMA2_DACK0/EVT7
ALT_MSRCID1/DMA2_DDONE0/EVT8
CLK_OUT
O
O
O
O
Clock
RTC
Real Time Clock
System Clock
AN24
AT23
I
I
OVDD
OVDD
—
—
SYSCLK
JTAG
TCK
TDI
Test Clock
AR22
AN17
AP15
AR20
AR19
I
I
OVDD
OVDD
OVDD
OVDD
OVDD
—
7
Test Data In
Test Data Out
Test Mode Select
Test Reset
TDO
TMS
TRST
O
I
6
7
I
7
DFT
SCAN_MODE
TEST_SEL
Scan Mode
AL17
AT21
AP11
I
I
I
OVDD
OVDD
OVDD
12
28
44
Test Mode Select
Test Mode Select 2
TEST_SEL2
Power Management
Asleep
ASLEEP
AR21
O
OVDD
35
Input/Output Voltage Select
IO_VSEL0
IO_VSEL1
IO_VSEL2
IO_VSEL3
IO_VSEL4
I/O Voltage Select
I/O Voltage Select
I/O Voltage Select
I/O Voltage Select
I/O Voltage Select
AL18
AP18
AK18
AM18
AH19
I
I
I
I
I
OVDD
OVDD
OVDD
OVDD
OVDD
30
30
30
30
30
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
28
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
Core Voltage ID Signals
Core voltage ID 0
AT14
AP14
AN13
AM12
O
O
O
O
OVDD
OVDD
OVDD
OVDD
42
42
42
42
VID_VDD_CA_CB0
VID_VDD_CA_CB1
VID_VDD_CA_CB2
VID_VDD_CA_CB3
Core voltage ID 1
Core voltage ID 2
Core voltage ID 3
Power and Ground Signals
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
C3
B5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F3
E5
D7
C9
B11
J3
H5
G7
G17
F9
E11
D13
C15
K19
B20
B22
E19
L22
J23
A22
L20
A26
A18
E17
F23
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
29
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
J27
F27
G21
K25
B18
L18
J21
M27
G13
F15
H11
J9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
K7
L5
M3
R3
P5
N7
M9
V25
R9
T7
U5
U3
Y3
Y5
W7
V10
AA9
AB7
AC5
AD3
AD9
AE7
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
30
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
AF5
AG3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AG9
AH7
AJ5
AK3
AN3
AM5
AL7
AK9
AJ11
AH13
AR5
AP7
AN9
AM11
AL13
AK15
AG18
AR11
AP13
AN15
AM17
AK19
AF13
AR18
AB27
AP19
AH22
AM21
AL29
AR16
AT22
AP23
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
31
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
AR32
AK28
AE27
L16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AP34
AJ32
AN30
AH34
AT36
AL34
AM32
AE26
AC26
AA26
W26
U26
R26
N26
M11
P11
T11
V11
Y11
AB11
AD11
AE12
AC12
AA12
W12
U12
R12
N12
M13
P13
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
32
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
T13
V13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y13
AB13
AD13
AE14
AC14
AA14
W14
U14
R14
N14
L14
M15
P15
T15
V15
Y15
AB15
AD15
AF15
W16
AC16
AA16
AE16
U16
R16
N16
M17
P17
T17
N18
R18
U18
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
33
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Y17
AB17
AD17
AF17
W18
AC18
AA18
AE18
AF19
AD19
AB19
Y19
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V19
T19
P19
M19
N20
R20
U20
AE20
AA20
AC20
W20
AF21
AD21
AB21
Y21
V21
T21
P21
M21
AE22
AC22
AA22
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
34
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
W22
U22
R22
N22
AF23
AD23
AB23
Y23
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V23
T23
P23
M23
L24
N24
R24
U24
W24
AA24
AC24
AE24
AF25
AD25
AB25
Y25
P27
V17
T25
P25
M25
T27
V27
Y27
AD27
L12
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
35
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GND
Ground
AG16
W15
W19
AA19
Y20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
AB14
AA21
Y16
GND
Ground
GND
Ground
GND
Ground
AA15
AC15
AA17
AC17
W17
Y18
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
GND
Ground
AB18
AB16
AC19
AB20
AA30
AB32
AC30
AC34
AD30
AD31
AF32
AG30
D33
GND
Ground
GND
Ground
GND
Ground
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
E28
E30
F32
G29
G31
H29
H32
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
36
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
XGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Transceiver GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
H34
J29
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
J31
K28
K29
L29
L32
M30
N29
N30
N32
P29
P34
R30
R32
U29
U31
V29
V31
W30
Y32
AH31
Y28
A28
A32
A36
AA34
AB36
AD35
AE34
AF36
AG33
B30
B34
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
37
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
SGND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes Core Logic GND
SerDes PLL1 GND
C29
C33
D31
D35
E35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
SGND
SGND
SGND
SGND
SGND
G34
G36
J35
SGND
SGND
SGND
K33
SGND
L36
SGND
M34
N35
R33
R36
T35
SGND
SGND
SGND
SGND
SGND
U34
V36
SGND
SGND
W33
Y35
SGND
SGND
AH35
AH33
AF29
B33
SGND
SGND
AGND_SRDS1
AGND_SRDS2
AGND_SRDS3
AGND_SRDS4
SENSEGND_PL1
SENSEGND_PL2
SENSEGND_CA
USB1_AGND
USB1_AGND
USB1_AGND
USB1_AGND
USB1_AGND
SerDes PLL2 GND
T36
SerDes PLL3 GND
AE36
T28
SerDes PLL4 GND
Platform GND Sense 1
Platform GND Sense 2
Core Group A GND Sense
USB1 PHY Transceiver GND
USB1 PHY Transceiver GND
USB1 PHY Transceiver GND
USB1 PHY Transceiver GND
USB1 PHY Transceiver GND
AF12
K27
8
K17
8
AH24
AJ24
AL25
AM25
AR25
—
—
—
—
—
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
38
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
USB1_AGND
USB1_AGND
USB1_AGND
USB1_AGND
USB1_AGND
USB2_AGND
USB2_AGND
USB2_AGND
USB2_AGND
USB2_AGND
USB2_AGND
USB2_AGND
USB2_AGND
USB2_AGND
OVDD
USB1 PHY Transceiver GND
USB1 PHY Transceiver GND
USB1 PHY Transceiver GND
USB1 PHY Transceiver GND
USB1 PHY Transceiver GND
USB2 PHY Transceiver GND
USB2 PHY Transceiver GND
USB2 PHY Transceiver GND
USB2 PHY Transceiver GND
USB2 PHY Transceiver GND
USB2 PHY Transceiver GND
USB2 PHY Transceiver GND
USB2 PHY Transceiver GND
USB2 PHY Transceiver GND
General I/O Supply
AR26
AR27
AR28
AT25
AT28
AH27
AL28
AM28
AN25
AN26
AN27
AN28
AP25
AP28
AN22
AJ14
AJ18
AL16
AJ12
AN18
AG21
AL20
AT15
AJ23
AP16
AR24
AG24
AJ29
AP29
B2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
CVDD
CVDD
CVDD
GVDD
GVDD
GVDD
GVDD
GVDD
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
OVDD
General I/O Supply
CVDD
eSPI & eSDHC Supply
eSPI & eSDHC Supply
eSPI & eSDHC Supply
DDR Supply
CVDD
CVDD
GVDD
GVDD
DDR Supply
B8
GVDD
DDR Supply
B14
GVDD
DDR Supply
C18
GVDD
DDR Supply
C12
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
39
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
C6
D4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D10
D16
E14
E8
E2
F6
F12
AR8
G4
G10
G16
H14
H8
H2
J6
K10
K4
L2
L8
M6
N4
N10
P8
P2
R6
T10
T4
J12
U2
U8
V7
AK10
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
40
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
BVDD
BVDD
BVDD
BVDD
BVDD
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
DDR Supply
Local Bus Supply
Local Bus Supply
Local Bus Supply
Local Bus Supply
Local Bus Supply
W10
AA6
AR2
Y2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
BVDD
BVDD
BVDD
BVDD
BVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y8
AC2
AD6
AE10
AE4
AF2
AF8
AB4
AB10
AC8
AG6
AH10
AH4
AJ2
AJ8
AR14
AK6
AL4
AL10
AM2
AM8
AP10
AN12
AN6
AP4
B24
K22
F20
F26
E24
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
41
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
BVDD
BVDD
BVDD
BVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
Local Bus Supply
E22
K24
H20
H18
A30
A34
AA33
AB35
AD36
AE33
AF35
AG34
B28
B32
B36
C31
C34
C35
D29
E36
F34
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BVDD
BVDD
BVDD
BVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Local Bus Supply
Local Bus Supply
Local Bus Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Core Logic Supply
G35
J36
K34
L35
M33
N36
R34
R35
U33
V35
W34
Y36
AH36
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
42
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
S1VDD
S1VDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
SerDes Core Logic Supply
SerDes Core Logic Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes Transceiver Supply
AC29
AG28
AA29
AB30
AB31
AC33
AD32
AE30
AF31
E32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SVDD
SVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
XVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E33
F28
F30
G32
H31
H33
J28
J30
J32
K30
L30
L31
M29
N31
P30
P33
R29
R31
T29
T32
U30
V30
V32
W29
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
43
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
XVDD
XVDD
X1VDD
VDD_LL
LVDD
SerDes Transceiver Supply
Y31
AH32
AG27
AC28
AK33
AP31
AL31
AN33
AJ35
AR35
AM35
AT17
—
—
—
—
—
—
—
—
—
—
—
—
XVDD
XVDD
XVDD
VDD_PL
LVDD
—
—
—
43
—
—
—
—
—
—
—
33
SerDes Transceiver Supply
SerDes Transceiver Supply
SerDes B4 Logic supply
Ethernet Controller 1 and 2 Supply
Ethernet Controller 1 and 2 Supply
Ethernet Controller 1 and 2 Supply
Ethernet Controller 1 and 2 Supply
Ethernet Controller 1 and 2 Supply
Ethernet Controller 1 and 2 Supply
Ethernet Controller 1 and 2 Supply
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
POVDD
Fuse Programming Override
Supply
POVDD
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
M26
P26
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T26
V26
Y26
AB26
AD26
N11
R11
W11
AA11
AE11
M12
P12
T12
V12
Y12
AB12
AD12
AE13
AE15
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
44
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
V16
AE17
L11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AE19
U11
AC11
V20
AE21
V22
U13
R27
U23
W23
AA27
AC27
AE23
M24
P24
T24
V24
Y24
AB24
AD24
N25
R25
U25
W25
AA25
AC25
N27
U27
W28
AE25
AF24
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
45
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Platform Supply
AF22
AF20
AF16
W13
AF18
V14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V18
L13
L15
L17
L19
L21
L23
L25
AF14
N23
R23
AA23
AC23
U21
W21
U15
AC21
AD22
M22
N13
AC13
P22
T22
Y22
AB22
AA13
R13
M14
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
46
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_LP
Platform Supply
U17
U19
T14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_PL
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_CA
VDD_LP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Platform Supply
Platform Supply
Platform Supply
AD14
AD16
AD18
AD20
Y14
T20
Platform Supply
Platform Supply
Platform Supply
Platform Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
Core/L2 Group A Supply
P20
R21
R19
P14
N19
M20
N21
M16
N15
P16
T16
R17
T18
R15
N17
M18
P18
AD28
Low Power Security Monitor
Supply
AVDD_CC1
AVDD_CC2
AVDD_PLAT
AVDD_DDR
AVDD_FM
Core Cluster PLL1 Supply
Core Cluster PLL2 Supply
Platform PLL Supply
DDR PLL Supply
A20
AT18
AT20
A19
—
—
—
—
—
—
—
—
—
—
—
—
13
13
13
13
13
13
FMan PLL Supply
AT19
A33
AVDD_SRDS1
SerDes PLL1 Supply
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
47
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
AVDD_SRDS2
AVDD_SRDS3
AVDD_SRDS4
SENSEVDD_PL1
SENSEVDD_PL2
SENSEVDD_CA
USB1_VDD_3P3
SerDes PLL2 Supply
SerDes PLL3 Supply
SerDes PLL4 Supply
Platform Vdd Sense
Platform Vdd Sense
Core Group A Vdd Sense
U36
AE35
R28
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
13
13
8
AF11
L27
8
K16
8
USB1 PHY Transceiver 3.3V
Supply
AL24
—
USB1_VDD_3P3
USB2_VDD_3P3
USB2_VDD_3P3
USB1 PHY Transceiver 3.3V
Supply
AJ25
AJ26
AJ27
—
—
—
—
—
—
—
—
—
USB2 PHY Transceiver 3.3V
Supply
USB2 PHY Transceiver 3.3V
Supply
USB1_VDD_1P0
USB2_VDD_1P0
USB1 PHY PLL 1.0V Supply
USB2 PHY PLL 1.0V Supply
AH25
AH26
—
—
—
—
—
—
Analog Signals
MVREF
SSTL_1.5/1.35 Reference Voltage
B19
I
I
GVDD/2
—
SD_IMP_CAL_TX
SerDes transmitter Impedance
Calibration
AF30
200Ω
(±1%) to
XVDD
23
SD1_IMP_CAL_TX
SD_IMP_CAL_RX
SD1_IMP_CAL_RX
SerDes transmitter Impedance
Calibration
AA28
B27
I
I
I
200Ω
(±1%) to
XVDD
23
24
24
SerDes receiver Impedance
Calibration
200Ω
(±1%) to
SVDD
SerDes receiver Impedance
Calibration
AF26
200Ω
(±1%) to
SVDD
TEMP_ANODE
Temperature Diode Anode
Temperature Diode Cathode
C21
B21
—
—
—
—
—
internal
diode
9
TEMP_CATHODE
USB1_IBIAS_REXT
USB2_IBIAS_REXT
USB1_VDD_1P8_DECAP
internal
diode
9
USB PHY1 Reference Bias Current
Generation
AM26
AM27
AL26
—
—
—
36
36
37
USB PHY2 Reference Bias Current
Generation
USB1 PHY 1.8V Output to External
Decap
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
48
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
USB2_VDD_1P8_DECAP
Notes
USB2 PHY 1.8V Output to External
Decap
AL27
—
—
37
No Connection Pins
NC_A27
NC_B26
NC_C19
NC_C20
NC_C26
NC_C27
NC_D18
NC_D27
NC_E16
NC_E27
NC_G27
NC_H12
NC_H13
NC_H15
NC_H27
NC_J11
NC_J13
NC_J14
NC_K11
NC_K12
NC_K13
NC_K14
NC_W27
NC_AG15
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
A27
B26
C19
C20
C26
C27
D18
D27
E16
E27
G27
H12
H13
H15
H27
J11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
J13
J14
K11
K12
K13
K14
W27
AG15
Reserved Pins
Reserve_A21
Reserve_A25
Reserve_C32
Reserve_D32
Reserve_F1
Reserve_F2
—
—
—
—
—
—
A21
A25
C32
D32
F1
—
—
—
—
—
—
—
—
—
—
—
—
41
11
11
11
11
11
F2
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
49
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
Reserve_G1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
G1
G2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
11
11
21
21
21
21
11
11
11
11
21
21
11
11
21
21
11
11
11
11
11
Reserve_G2
Reserve_L28
Reserve_M28
Reserve_N28
Reserve_P28
Reserve_U32
Reserve_U35
Reserve_AD33
Reserve_AD34
Reserve_AG11
Reserve_AG12
Reserve_AG26
Reserve_AG29
Reserve_AH11
Reserve_AH12
Reserve_AH30
Reserve_AK1
Reserve_AK2
Reserve_AL1
Reserve_AL2
L28
GND
GND
GND
GND
—
M28
N28
P28
U32
U35
—
AD33
AD34
AG11
AG12
AG26
AG29
AH11
AH12
AH30
AK1
—
—
GND
GND
—
—
GND
GND
—
—
AK2
—
AL1
—
AL2
—
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
50
Freescale Semiconductor
Pin assignments and reset states
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
Notes:
1. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD
2. This pin is an open drain signal.
.
3. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ resistor. However, if the signal is
intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then
a pull up or active driver is needed.
4. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.
5. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to BVDD, to ensure no random chip select assertion due
to possible noise, and so forth.
6. This output is actively driven during reset rather than being three-stated during reset.
7. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
8. These pins are connected to the correspondent power and ground nets internally and may be connected as a differential pair
to be used by the voltage regulators with remote sense function.
9. These pins may be connected to a thermal diode monitoring device such as the ADT7461A only with a clear understanding
that proper thermal diode operation is not implied and the thermal diode feature may not be available in the production device.
11. Do not connect.
12. These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OVDD for normal device operation.
13. Independent supplies derived from board VDD_PL (Core clusters, Platform, DDR) or SVDD (SerDes).
14. Recommend a pull-up resistor of 1-kΩ be placed on this pin to OVDD if I2C interface is used.
15. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively
driven.
16. For DDR3 and DDR3L, Dn_MDIC[0] is grounded through an 40.2-Ω (half-strength mode) precision 1% resistor and
Dn_MDIC[1] is connected to GVDD through an 40.2-Ω (half-strength mode) precision 1% resistor. These pins are used for
automatic calibration of the DDR3 and DDR3L IOs.
18. These pins should be pulled up to 1.2V through a 180Ω ± 1% resistor for EM2_MDC and a 330Ω ± 1% resistor for
EM2_MDIO.
20. Pin has a weak internal pull-up.
21. These pins should be pulled to ground (GND).
22. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage
levels. LVDD must be powered to use this interface.
23. This pin requires a 200-Ω pull-up to XVDD
24. This pin requires a 200-Ω pull-up to SVDD
25. This GPIO pin is on LVDD power plane, not OVDD
.
.
.
26. Functionally, this pin is an I/O, but may act as an output only or an input only depending on the pin mux configuration defined
by the RCW.
27. See Section 3.6, “Connection recommendations,” for additional details on this signal.
28. This signal must be pulled low to GND.
30. Warning, incorrect voltage select settings can lead to irreversible device damage. See Section 3.2, “Supply power default
setting.”
31. SDHC_DAT[4:7] require CVDD = 3.3 V when muxed extended SDHC data signals are enabled via the RCW[SPI] field.
32. The cfg_xvdd_sel(LAD[26]) reset configuration pin must select the correct voltage that is being supplied on the XVDD pin.
Incorrect voltage select settings can lead to irreversible device damage.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
51
Electrical characteristics
Table 1. Pins listed by bus (continued)
Signal description
Package
pin number type supply
Pin Power
Signal
Notes
33. See Section 2.2, “Power-up sequencing and Section 5, “Security fuse processor,” for additional details on this signal.
35. Pin must NOT be pulled down by a resistor or the component it is connected to during power-on reset.
36. This pin should be connected to GND through a 10kΩ ± 0.1% resistor with a low temperature coefficient of ≤ 25ppm/°C for
bias generation.
37. A 1uF to 1.5uF capacitor connected to GND is required on this signal. A list of recommended capacitors are shown in
Section 3.6.4.2, “USBn_VDD_1P8_DECAP capacitor options.”
38. A divider network is required on this signal. See Section 3.6.4.1, “USB divider network.”
39. For systems which boot from local bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pullup on LGPL4 is
required.
40. Functionally, this pin is an input, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan.
41. If migration from a P4 device, this pin is allowed to be powered by AVDD_CC2. If not migrating, do not connect.
42. The VDD_VID_CA_CB pins are inputs at POR. If a voltage regulator is connected directly to the VID_VDD_CA_CB pins,
customers need to put weak pull-ups or pull-downs on their board so that their voltage regulator drives a guaranteed-to-work
voltage with the cores configured to run at a safe frequency for that voltage. This is needed so that a working voltage can be
applied until the operating voltage is determined (for example, so that PLLs can begin to lock, and so on, during this time frame
or while the voltage is ramping). The safe boot voltage for the chip is 1.1 V. Note that the P5021 does not require VID to meet
it's performance and power envelope. All power rails should be fixed at the operating values specified in Table 3.
“Recommended operating conditions.”
43. VDD_LL should be connected directly to VDD_PL.
44. Normally tied to GND. See the applicable migration application note if moving from P3041 (AN4395) or P5020/P5010
(AN4400).
2
Electrical characteristics
This section provides the AC and DC electrical specifications for the chip. The chip is currently targeted to these specifications,
some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC electrical characteristics
This section describes the ratings, conditions, and other electrical characteristics.
2.1.1
Absolute maximum ratings
This table provides the absolute maximum ratings.
1
Table 2. Absolute maximum operating conditions
Parameter
Symbol
Maximum value
Unit Notes
Core group A (core 0,1) supply voltage
Platform supply voltage
VDD_CA
VDD_PL
–0.3 to 1.32
–0.3 to 1.1
V
V
9,11
9,10,
11
PLL supply voltage (core, platform, DDR)
AVDD
–0.3 to 1.1
–0.3 to 1.1
V
V
—
—
PLL supply voltage (SerDes, filtered from SVDD
)
AVDD_SRDS
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
52
Freescale Semiconductor
Electrical characteristics
Table 2. Absolute maximum operating conditions (continued)
1
Parameter
Fuse programming override supply
Symbol
Maximum value
Unit Notes
POVDD
OVDD
–0.3 to 1.65
–0.3 to 3.63
V
V
1
DUART, I2C, DMA, MPIC, GPIO, system control and power
management, clocking, debug, I/O voltage select, and JTAG I/O
voltage
—
eSPI, eSHDC
CVDD
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
V
—
DDR3 and DDR3L DRAM I/O voltage
Enhanced local bus I/O voltage
GVDD
BVDD
–0.3 to 1.65
V
V
—
—
–0.3 to 3.63
–0.3 to 2.75
–0.3 to 1.98
Core power supply for SerDes transceivers
Pad power supply for SerDes transceivers
SVDD
XVDD
–0.3 to 1.1
V
V
—
—
–0.3 to 1.98
–0.3 to 1.65
Ethernet I/O, Ethernet management interface 1 (EMI1), 1588, GPIO
LVDD
–0.3 to 3.63
–0.3 to 2.75
V
3
Ethernet management interface 2 (EMI2)
USB PHY Transceiver supply voltage
USB PHY PLL supply voltage
—
–0.3 to 1.32
–0.3 to 3.63
–0.3 to 1.1
–0.3 to 1.1
V
V
V
V
8
USB_VDD_3P3
USB_VDD_1P0
VDD_LP
—
—
—
Low-power security monitor supply
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
53
Electrical characteristics
Table 2. Absolute maximum operating conditions (continued)
1
Parameter
Symbol
Maximum value
Unit Notes
Input voltage7
DDR3 and DDR3L DRAM signals
DDR3 and DDR3L DRAM reference
Ethernet signals (except EMI2)
eSPI, eSHDC
MVIN
MVREF
LVIN
–0.3 to (GVDD + 0.3)
–0.3 to (GVDD/2+ 0.3)
–0.3 to (LVDD + 0.3)
–0.3 to (CVDD + 0.3)
–0.3 to (BVDD + 0.3)
–0.3 to (OVDD + 0.3)
V
V
V
V
V
V
2, 7
2, 7
3, 7
4, 7
5, 7
6, 7
CVIN
BVIN
Enhanced local bus signals
DUART, I2C, DMA, MPIC, GPIO, system
control and power management, clocking,
debug, I/O voltage select, and JTAG I/O
voltage
OVIN
SerDes signals
XVIN
–0.4 to (XVDD + 0.3)
V
V
7
7
USB PHY transceiver signals
USB_VIN_3P3
–0.3 to
(USB_VDD_3P3 + 0.3)
Ethernet management interface 2 (EMI2)
signals
—
–0.3 to (1.2 + 0.3)
–55 to 150
V
7
Storage junction temperature range
Tstg
°C
—
Notes:
1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only; functional operation
at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to
the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
4. Caution: CVIN must not exceed CVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. Caution: BVIN must not exceed BVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
6. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
7. (C,X,B,G,L,O)VIN may overshoot (for VIH) or undershoot (for VIL) to the voltages and maximum duration shown in Figure 7.
8. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage levels.
LVDD must be powered to use this interface.
9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
10. Implementation may choose either VDD_PL pin for feedback loop. If the platform and core groups are supplied by a single
regulator, it is recommended that VDD_CA be used.
11. VDD_PL voltage must not exceed VDD_CA
.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
54
Freescale Semiconductor
Electrical characteristics
2.1.2
Recommended operating conditions
This table provides the recommended operating conditions for this device. Note that proper device operation outside these
conditions is not guaranteed.
Table 3. Recommended operating conditions
Recommended
Parameter
Symbol
Unit Notes
value
Core group A (core 0,1) supply voltage
VDD_CA
1.1 50mV (core
frequency ≤
V
1,6
2000 MHz)
1.2V 30mV (core
frequency >
2000 MHz)
Platform supply voltage
VDD_PL
AVDD
1.0 50mV
1.0 50mV
1.0 50mV
1.5 75mV
3.3 165mV
V
V
V
V
V
1,6
—
—
2
PLL supply voltage (core, platform, DDR, FMan)
PLL supply voltage (SerDes)
AVDD_SRDS
POVDD
OVDD
Fuse programming override supply
DUART, I2C, DMA, MPIC, GPIO, system control and power
management, clocking, debug, I/O voltage select, and JTAG I/O
voltage
—
eSPI, eSDHC
CVDD
GVDD
BVDD
3.3 165mV
2.5 125mV
1.8 90mV
V
V
V
—
—
—
DDR DRAM I/O voltage
DDR3
1.5 75mV
DDR3L
1.35 67mV
Enhanced local bus I/O voltage
3.3 165mV
2.5 125mV
1.8 90mV
Main power supply for internal circuitry of SerDes and pad power
supply for SerDes receiver
SVDD
XVDD
LVDD
1.0 + 50mV
1.0 – 30mV
V
V
V
—
—
3
Pad power supply for SerDes transmitter
1.8 90mV
1.5 75mV
Ethernet I/O, Ethernet Management interface 1 (EMI1), 1588, GPIO
3.3 165mV
2.5 125mV
USB PHY transceiver supply voltage
USB PHY PLL supply voltage
USB_VDD_3P3
USB_VDD_1P0
VDD_LP
3.3 165mV
1.0 50mV
1.0 50mV
V
V
V
—
—
—
Low-power security monitor supply
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
55
Electrical characteristics
Table 3. Recommended operating conditions (continued)
Recommended
value
Parameter
DDR3 and DDR3L DRAM
Symbol
Unit Notes
Input voltage
MVIN
GND to GVDD
V
V
7
7
signals
DDR3 and DDR3L DRAM
reference
MVREF
GVDD/2 1%
Ethernet signals (except EMI2)
eSPI, eSHDC
LVIN
CVIN
BVIN
OVIN
GND to LVDD
GND to CVDD
GND to BVDD
GND to OVDD
V
V
V
V
7
7
7
7
Enhanced local bus signals
DUART, I2C, DMA, MPIC, GPIO,
system control and power
management, clocking, debug,
I/O voltage select, and JTAG I/O
voltage
SerDes signals
SVIN
GND to SVDD
V
V
7
7
USB PHY Transceiver signals
USB_VIN_3P3
GND to
USB_VDD_3P3
Ethernet Management interface
2 (EMI2) signals
—
GND to 1.2V
V
4, 7
—
Operating Temperature range
Normal Operation
TA,
TJ
TA = 0 (min) to
TJ = 105 (max)
(90 (max) core
frequency > 2000
MHz)
°C
Extended Temperature
TA,
TJ
TA = -40 (min) to
TJ = 105 (max)
°C
°C
—
2
Secure Boot Fuse Programming
TA,
TJ
TA = 0 (min) to
TJ = 70 (max)
Notes:
1. VDD_PL voltage must not exceed VDD_CA
.
2. POVDD must be supplied 1.5 V and the chip must operate in the specified fuse programming temperature range only
during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the
power sequencing constraints shown in Section 2.2, “Power-up sequencing.”
3. Selecting RGMII limits LVDD to 2.5V.
4. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage
levels. LVDD must be powered to use this interface.6. Supply voltage specified at the voltage sense pin. Voltage input
pins must be regulated to provide specified voltage at the sense pin.
7. All input signals must increase/decrease monotonically throughout the entire rise/fall duration.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
56
Freescale Semiconductor
Electrical characteristics
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
Nominal C/X/B/G/L/OVDD + 20%
C/X/B/G/L/OVDD + 5%
C/X/B/G/L/OVDD
VIH
GND
GND – 0.3V
VIL
GND – 0.7 V
Not to Exceed 10%
of tCLOCK
Note:
tCLOCK refers to the clock period associated with the respective interface:
For I2C, tCLOCK refers to SYSCLK.
For DDR GVDD, tCLOCK refers to Dn_MCK.
For eSPI CVDD, tCLOCK refers to SPI_CLK.
For eLBC BVDD, tCLOCK refers to LCLK.
For SerDes XVDD, tCLOCK refers to SD_REF_CLK.
For dTSEC LVDD, tCLOCK refers to EC_GTX_CLK125.
For JTAG OVDD, tCLOCK refers to TCK.
Figure 7. Overshoot/Undershoot voltage for BV /GV /LV /OV
DD
DD
DD
DD
The core and platform voltages must always be provided at nominal 1.0 V or 1.2 V. See Table 3 for the actual recommended
core voltage conditions. Voltage to the processor interface I/Os is provided through separate sets of supply pins and must be
provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage.
CV , BV , OV , and LV -based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type
DD
DD
DD
DD
specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied MV
signal
REF
(nominally set to GV /2) as is appropriate for the SSTL_1.5 electrical signaling standard. The DDR DQS receivers cannot be
DD
operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
57
Electrical characteristics
2.1.3
Output driver characteristics
This table provides information about the characteristics of the output driver strengths. The values are preliminary estimates.
Table 4. Output drive capability
(Nominal) supply
Driver type
Output impedance (Ω)
Notes
voltage
Local bus interface utilities signals
45
45
45
BVDD = 3.3 V
BVDD = 2.5 V
BVDD = 1.8 V
—
DDR3 signal
20 (full-strength mode)
40 (half-strength mode)
GVDD = 1.5 V
1
1
DDR3L signal
20 (full-strength mode)
40 (half-strength mode)
GVDD = 1.35 V
eTSEC/10/100 signals
45
45
LVDD = 3.3 V
LVDD = 2.5 V
—
DUART, system control, JTAG
I2C
45
45
OVDD = 3.3 V
OVDD = 3.3 V
—
—
—
eSPI and SD/MMC
45
45
45
CVDD = 3.3 V
CVDD = 2.5 V
CVDD = 1.8 V
Note:
1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at GVDD (min).
2.2
Power-up sequencing
The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. These
requirements are as follows for power up:
1. Bring up OV , LV , BV , CV , and USB_V _3P3. Drive POV = GND.
DD
DD
DD
DD
DD
DD
— PORESET input must be driven asserted and held during this step
— IO_VSEL inputs must be driven during this step and held stable during normal operation.
— USB_V _3P3 rise time (10% to 90%) has a minimum of 350 μs.
DD
2. Bring up V
, V
, SV , AV (cores, platform, DDR, SerDes) and USB_V _1P0. V
and
DD_PL
DD_CA
DD
DD
DD
DD_PL
USB_V _1P0 must be ramped up simultaneously.
DD
3. Bring up GV and XV
.
DD
DD
4. Negate PORESET input as long as the required assertion/hold time has been met per Table 15.
5. For secure boot fuse programming: After negation of PORESET, drive POV = 1.5 V after a required minimum
DD
delay per Table 5. After fuse programming is completed, it is required to return POV = GND before the system is
DD
power cycled (PORESET assertion) or powered down (V
ramp down) per the required timing specified in
DD_PL
Table 5. See Section 5, “Security fuse processor,” for additional details.
WARNING
Only two secure boot fuse programming events are permitted per lifetime of a device.
No activity other than that required for secure boot fuse programming is permitted while
POV driven to any voltage above GND, including the reading of the fuse block. The
DD
reading of the fuse block may only occur while POV = GND.
DD
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
58
Freescale Semiconductor
Electrical characteristics
WARNING
Only 100,000 POR cycles are permitted per lifetime of a device.
WARNING
While VDD is ramping, current may be supplied from VDD through the P5021 to GVDD.
Nevertheless, GVDD from an external supply should follow the sequencing described
above.
All supplies must be at their stable values within 75 ms.
Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered
sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step
reach 10% of theirs.
This figure provides the POV timing diagram.
DD
1
Fuse programming
10% POV
10% POV
DD
DD
POVDD
VDD_PL
90% V
DD_PL
tPOVDD_VDD
90% OV
t
90% OV
DD
DD
POVDD_PROG
PORESET
tPOVDD_RST
tPOVDD_DELAY
NOTE: POVDD must be stable at 1.5 V prior to initiating fuse programming.
Figure 8. POV timing diagram
DD
This table provides information on the power-down and power-up sequence parameters for POV
.
DD
5
Table 5. POV timing
DD
Driver type
Min
Max
Unit
Notes
tPOVDD_DELAY
tPOVDD_PROG
tPOVDD_VDD
tPOVDD_RST
Notes:
100
0
—
—
—
—
SYSCLKs
1
2
3
4
μs
μs
μs
0
0
1. Delay required from the negation of PORESET to driving POVDD ramp up. Delay measured from PORESET negation at 90%
OVDD to 10% POVDD ramp up.
2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD
is stable at 1.5 V. No activity other than that required for secure boot fuse programming is permitted while POVDD driven to
any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD
GND. After fuse programming is completed, it is required to return POVDD = GND.
=
3. Delay required from POVDD ramp down complete to VDD_PL ramp down start. POVDD must be grounded to minimum 10%
POVDD before VDD_PL is at 90% VDD
4. Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to minimum 10% POVDD
before PORESET assertion reaches 90% OVDD
5. Only two secure boot fuse programming events are permitted per lifetime of a device.
.
.
To guarantee MCKE low during power up, the above sequencing for GV is required. If there is no concern about any of the
DD
DDR signals being in an indeterminate state during power up, the sequencing for GV is not required.
DD
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
59
Electrical characteristics
WARNING
Incorrect voltage select settings can lead to irreversible device damage. See Section 3.2,
“Supply power default setting.”
NOTE
From a system standpoint, if any of the I/O power supplies ramp prior to the V
, or
DD_CA
V
supplies, the I/Os associated with that I/O supply may drive a logic one or zero
DD_PL
during power-up, and extra current may be drawn by the device.
2.3
Power-down requirements
The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be
started.
If performing secure boot fuse programming per Section 2.2, “Power-up sequencing,” it is required that POV = GND before
DD
the system is power cycled (PORESET assertion) or powered down (V
Table 5.
ramp down) per the required timing specified in
DD_PL
V
and USB_V _1P0 must be ramped down simultaneously. USB_V _1P8_DECAP should starts ramping down only
DD DD
DD_PL
after USB_V _3P3 is below 1.65 V.
DD
2.4
Power characteristics
This table shows the power dissipations of the V
, SV
and V
supply for various operating platform clock
DD_PL
DD_CA
DD,
frequencies versus the core and DDR clock frequencies for the chip.
Table 6. Power dissipation
Core
Junction and plat- VDD_PL VDD_CA SVDD
DDR
data FM freq
rate
(MHz)
Core
freq
(MHz) (MHz)
Plat
freq
VDD_PL,
SVDD
(V)
Power
Mode
VDD_CA
(V)
temp
form
power1
(W)
power power power Note
(MHz)
(°C)
(W)
(W)
(W)
Typical
65
90
23
33
34
21
30
31
—
—
17
—
—
16
—
—
15
—
—
13
—
—
15
—
—
13
—
—
Thermal 2200
Maximum
800
700
1600
1333
600
1.0
1.0
1.2
1.1
2.2
—
Typical
65
Thermal 2000
Maximum
600
—
105
2.2
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
60
Freescale Semiconductor
Electrical characteristics
Table 6. Power dissipation (continued)
Core
DDR
Core
freq
(MHz) (MHz)
Plat
freq
VDD_PL,
SVDD
(V)
Junction and plat- VDD_PL VDD_CA SVDD
Power
Mode
data FM freq
VDD_CA
(V)
temp
form
power1
(W)
power power power Note
rate
(MHz)
(MHz)
(°C)
(W)
(W)
(W)
Typical
65
20
29
30
—
—
15
—
—
13
—
—
13
—
—
Thermal 1800
Maximum
600
1200
450
1.0
1.1
105
2.2
Notes:
1. Combined power of VDD_PL, VDD_CA, SVDD with both DDR controllers and all SerDes banks active. Does not include I/O
power.
2. Typical power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform with
90% activity factor.
3. Typical power based on nominal processed device.
4. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and executing DMA on the platform
at 100% activity factor.
5. Thermal power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform at
90% activity factor.
6. Maximum power provided for power supply design sizing.
7. Thermal and maximum power are based on worst case processed device.
This table shows the estimated power dissipation on the AV and AV
supplies for the chip’s PLLs, at allowable
DD
DD_SRDS
voltage levels.
Table 7. AV power dissipation
DD
AVDD
s
Typical
Maximum
Unit
Notes
AVDD_DDR
AVDD_CC1
5
5
15
15
15
15
15
36
36
36
36
10
5
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
1
AVDD_CC2
5
AVDD_PLAT
AVDD_FM
5
5
AVDD_SRDS1
AVDD_SRDS2
AVDD_SRDS3
AVDD_SRDS4
USB_VDD_1P0
VDD_LP
—
—
—
—
—
—
2
3
Note:
1. VDD_CA = 1.2 V, TA = 80°C, TJ = 105°C
2. VDD_PL, SVDD = 1.0 V, TA = 80°C, TJ = 105°C
3. USB_VDD_1P0, VDD_LP = 1.0 V, TA = 80°C, TJ = 105°C
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
61
Electrical characteristics
This table shows the estimated power dissipation on the POV supply for the chip, at allowable voltage levels.
DD
Table 8. POV power dissipation
DD
Supply
Maximum
Unit
Notes
POVDD
450
mW
1
Note:
1. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature
range per Table 3.
This table shows the estimated power dissipation on the V
supply for the chip, at allowable voltage levels.
DD_LP
Table 9. V
Power Dissipation
DD_LP
Supply
Maximum
Unit
Note
V
DD_LP (P5021 on, 105C)
1.5
195
132
mW
uW
uW
1
2
2
VDD_LP (P5021 off, 70C)
DD_LP (P5021 off, 40C)
V
Note:
1. VDD_LP = 1.0 V, TJ = 105°C.
2. When P5021 is off, VDD_LP may be supplied by battery power to the Zeroizable Master Key and other Trust Architecture
state. Board should implement a PMIC which switches VDD_LP to battery when P5021 is powered down. See P5040
Reference Manual Trust Architecture chapter for more information.
2.5
Thermal
This table shows the thermal characteristics for the chip.
6
Table 10. Package thermal characteristics
Rating
Board
Symbol
Value
Unit
Notes
Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to ambient (at 200 ft./min.)
Junction to ambient (at 200 ft./min.)
Single-layer board (1s)
Four-layer board (2s2p)
Single-layer board (1s)
Four-layer board (2s2p)
RΘJA
RΘJA
14
10
9
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2
1, 2
1, 2
RΘJMA
RΘJMA
7
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
62
Freescale Semiconductor
Electrical characteristics
6
Table 10. Package thermal characteristics (continued)
Rating
Board
Symbol
Value
Unit
Notes
Junction to board
Junction to case top
Junction to lid top
Notes:
—
—
—
RΘJB
RΘJCtop
RΘJClid
3
°C/W
°C/W
°C/W
3
4
5
0.44
0.17
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer.
4. Junction-to-Lid-Top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the cold
plate, the lid top temperature is used here for the reference case temperature. The reported value does not include the thermal
resistance of the interface layer between the package and cold plate.
5. Junction-to-lid-top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the cold
plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the thermal
resistance of the interface layer between the package and cold plate.
6. Reference Section 3.8, “Thermal management information,” for additional details.
2.6
Input clocks
This section discusses the system clock timing specifications for DC and AC power, spread spectrum sources, real time clock
timing, and dTSEC gigabit Ethernet reference clocks AC timing.
2.6.1
System clock (SYSCLK) timing specifications
This table provides the system clock (SYSCLK) DC specifications.
Table 11. SYSCLK DC electrical characteristics (OV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Input high voltage
Symbol
Min
Typical
Max
Unit
Notes
VIH
VIL
IIN
2.0
—
—
—
—
—
0.8
40
V
V
1
1
2
Input low voltage
Input current (OVIN= 0 V or OVIN
OVDD)
=
—
μA
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
63
Electrical characteristics
This table provides the system clock (SYSCLK) AC timing specifications.
Table 12. SYSCLK AC timing specifications
For recommended operating conditions, see Table 3.
Parameter/Condition
SYSCLK frequency
Symbol
Min
Typ
Max
Unit
Notes
fSYSCLK
100
6
—
—
—
—
—
—
—
166
10
MHz
ns
1, 2
1, 2
2
SYSCLK cycle time
tSYSCLK
SYSCLK duty cycle
tKHK / tSYSCLK
40
1
60
%
SYSCLK slew rate
—
—
4
V/ns
ps
3
SYSCLK peak period jitter
SYSCLK jitter phase noise
AC Input Swing Limits at 3.3 V OVDD
Notes:
—
—
1.9
150
500
—
—
4
—
KHz
V
ΔVAC
—
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency, do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from 0.3 ΔVAC at center of peak to peak voltage at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
2.6.2
Spread-spectrum sources recommendations
Spread-spectrum clock sources is an increasingly popular way to control electromagnetic interference emissions (EMI) by
spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter
specification given in Table 13 considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output
jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns;
the chip is compatible with spread spectrum sources if the recommendations listed in Table 13 are observed.
Table 13. Spread-spectrum clock source recommendations
For recommended operating conditions, see Table 3.
Parameter
Frequency modulation
Min
Max
Unit
Notes
—
—
60
kHz
%
—
Frequency spread
1.0
1, 2
Notes:
1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Table 12.
2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.
CAUTION
The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which
the processor is operated at its maximum rated core/platform/DDR frequency should avoid
violating the stated limits by using down-spreading only.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
64
Freescale Semiconductor
Electrical characteristics
2.6.3
Real time clock timing
The real time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an
input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum pulse
width of the RTC signal should be greater than 16× the period of the platform clock with a 50% duty cycle. There is no minimum
RTC frequency; RTC may be grounded if not needed.
2.6.4
dTSEC gigabit Ethernet reference clock timing
This table provides the dTSEC gigabit Ethernet reference clocks AC timing specifications.
Table 14. EC_GTX_CLK125 AC timing specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise and fall time
tG125
tG125
tG125R/tG125F
—
—
—
125
8
—
—
MHz
ns
—
—
1
—
ns
LVDD = 2.5 V
LVDD = 3.3 V
0.75
1.0
EC_GTX_CLK125 duty cycle
1000Base-T for RGMII
tG125H G125
/t
—
—
%
2
2
47
—
53
EC_GTX_CLK125 jitter
Note:
1. Rise and fall times for EC_GTX_CLK125 are measured from 20% to 80% (rise time) and 80% to 20% (fall time) of LVDD
—
150
ps
.
2. EC_GTX_CLK125 is used to generate the GTX clock for the dTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty
cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the dTSEC
GTX_CLK. See Section 2.12.2.3, “RGMII AC timing specifications,” for duty cycle for 10Base-T and 100Base-T reference
clock.
2.6.5
Other input clocks
A description of the overall clocking of this device is available in the applicable chip reference manual in the form of a clock
subsystem block diagram. For information on the input clock requirements of functional blocks sourced external of the device,
such as SerDes, Ethernet Management, eSDHC, Local bus, see the specific interface section.
2.7
RESET initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements. This table provides the
RESET initialization AC timing specifications.
Table 15. RESET initialization timing specifications
Parameter
Required assertion time of PORESET
Min
Max
Unit1
Notes
1
32
4
—
—
—
ms
3
1, 2
1
Required input assertion time of HRESET
SYSCLKs
SYSCLKs
Input setup time for POR configurations with respect to negation of
PORESET
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
65
Electrical characteristics
Table 15. RESET initialization timing specifications (continued)
Parameter
Min
Max
Unit1
Notes
Input hold time for all POR configurations with respect to negation of
PORESET
2
—
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR
configurations with respect to negation of PORESET
—
5
SYSCLKs
1
Notes:
1. SYSCLK is the primary clock input for the chip.
2. The device asserts HRESET as an output when PORESET is asserted to initiate the power-on reset process. The device
releases HRESET sometime after PORESET is negated. The exact sequencing of HRESET negation is documented in
Section 4.4.1 “Power-On Reset Sequence,” of the applicable chip reference manual.
3. PORESET must be driven asserted before the core and platform power supplies are powered up , see Section 2.2, “Power-up
sequencing.”
This table provides the PLL lock times.
Table 16. PLL lock times
Parameter
Min
Max
Unit
Notes
PLL lock times
—
100
μs
—
2.8
Power-on ramp rate
This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum
Power-On Ramp Rate is required to avoid falsely triggering the ESD circuitry. This table provides the power supply ramp rate
specifications.
Table 17. Power supply ramp rate
Parameter
Min
Max
Unit
Notes
Required ramp rate for all voltage supplies (including OVDD/CVDD
/
—
36000
V/s
1, 2
GVDD/BVDD/SVDD/XVDD/LVDD all VDD supplies, MVREF and all AVDD supplies.)
Notes:
1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change
from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Over full recommended operating temperature range (see Table 3).
2.9
DDR3 and DDR3L SDRAM controller
This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note
that the required GV (typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and GV (typ) voltage is 1.35 V when
DD
DD
interfacing to DDR3L SDRAM.
NOTE
When operating at DDR data rates of 1600 MT/s only one dual-ranked module per memory
controller is supported.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
66
Freescale Semiconductor
Electrical characteristics
2.9.1
DDR3 and DDR3L SDRAM interface DC electrical characteristics
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3
SDRAM.
1
Table 18. DDR3 SDRAM interface DC electrical characteristics (GV = 1.5 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
I/O reference voltage
Input high voltage
Input low voltage
I/O leakage current
Notes:
MVREF
VIH
0.49 × GVDD
MVREF + 0.100
GND
0.51 × GVDD
GVDD
V
V
2, 3, 4
5
5
6
VIL
MVREF – 0.100
50
V
IOZ
–50
μA
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed the MVREF DC level by more than 1% of the DC value (that is, 15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREF with a min value of MVREF – 0.04 and a max value of MVREF + 0.04. VTT should track variations in the DC
level of MVREF
.
4. The voltage regulator for MVREF must meet the specifications stated in Table 21.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD
.
This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L
SDRAM.
1
Table 19. DDR3L SDRAM interface DC electrical characteristics (GV = 1.35 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
I/O reference voltage
Input high voltage
Input low voltage
MVREF
VIH
0.49 × GVDD
MVREF + 0.090
GND
0.51 × GVDD
GVDD
V
V
V
2, 3, 4
5
5
VIL
MVREF – 0.090
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
67
Electrical characteristics
1
Table 19. DDR3L SDRAM interface DC electrical characteristics (GV = 1.35 V) (continued)
DD
For recommended operating conditions, see Table 3.
Parameter
I/O leakage current
Symbol
Min
Max
Unit
Note
IOZ
IOH
IOL
–50
—
50
–23.3
—
μA
mA
mA
6
Output high current (VOUT = 0.641 V)
Output low current (VOUT = 0.641 V)
Notes:
7, 8
7, 8
23.3
1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage
supply may or may not be from the same source.
2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed the MVREF DC level by more than 1% of the DC value (that is, 13.5 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREF with a min value of MVREF – 0.04 and a max value of MVREF + 0.04. VTT should track variations in the DC
level of MVREF
.
4. The voltage regulator for MVREF must meet the specifications stated in Table 21.
5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD
.
7. Refer to the IBIS model for the complete output IV curve characteristics.
8. IOH and IOL are measured at GVDD = 1.283 V
This table provides the DDR controller interface capacitance for DDR3 and DDR3L.
Table 20. DDR3 and DDR3L SDRAM Capacitance
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
Delta input/output capacitance: DQ, DQS, DQS
Notes:
CIO
6
8
pF
pF
1, 2
1, 2
CDIO
—
0.5
1. This parameter is sampled. GVDD = 1.5 V 0.075 V (for DDR3), f = 1 MHz, TA = 25 °C, VOUT = GVDD/2,
VOUT (peak-to-peak) = 0.150 V.
2. This parameter is sampled. GVDD = 1.35 V – 0.067 V ÷ + 0.100 V (for DDR3L), f = 1 MHz, TA = 25 °C, VOUT = GVDD/2,
OUT (peak-to-peak) = 0.167 V.
V
This table provides the current draw characteristics for MVREF.
Table 21. Current Draw Characteristics for MVREF
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Current draw for DDR3 SDRAM for MVREF
Current draw for DDR3L SDRAM for MVREF
MVREF
MVREF
—
—
1250
1250
μA
μA
—
—
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
68
Freescale Semiconductor
Electrical characteristics
2.9.2
DDR3 and DDR3L SDRAM interface AC timing specifications
This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports
DDR3 and DDR3L memories. Note that the required GV (typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the
DD
required GV (typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
DD
2.9.2.1
DDR3 and DDR3L SDRAM interface input AC timing specifications
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
Table 22. DDR3 SDRAM interface input AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage > 1200 MT/s data rate
≤ 1200 MT/s data rate
VILAC
—
MVREF – 0.150
MVREF – 0.175
—
V
—
AC input high voltage > 1200 MT/s data rate
≤ 1200 MT/s data rate
VIHAC
MVREF + 0.150
MVREF + 0.175
V
—
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM.
Table 23. DDR3L SDRAM interface input AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
> 1067 MT/s data rate
Symbol
Min
Max
Unit
Notes
AC input low voltage
VILAC
—
MVREF – 0.135
MVREF – 0.160
—
V
—
≤ 1067 MT/sdata rate
> 1067 MT/s data rate
≤ 1067 MT/s data rate
AC input high voltage
VIHAC
MVREF + 0.135
MVREF + 0.160
V
—
This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.
Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for MDQS—MDQ/MECC
1600 MT/s data rate
tCISKEW
ps
1
–112
–125
112
125
1333 MT/s data rate
1200 MT/s data rate
–147.5
–170
147.5
170
1066 MT/s data rate
800 MT/s data rate
–200
200
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
69
Electrical characteristics
Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Tolerated Skew for MDQS—MDQ/MECC
1600 MT/s data rate
1333 MT/s data rate
1200 MT/s data rate
1066 MT/s data rate
800 MT/s data rate
tDISKEW
ps
2
–200
–250
–275
–300
–425
200
250
275
300
425
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = (T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW
.
This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.
MCK[n]
MCK[n]
tMCK
MDQS[n]
tDISKEW
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
70
Freescale Semiconductor
Electrical characteristics
2.9.2.2
DDR3 and DDDR3L SDRAM interface output AC timing specifications
This table contains the output AC timing targets for the DDR3 SDRAM interface.
Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
MCK[n] cycle time
Symbol1
Min
Max
Unit
Notes
tMCK
1.25
2.5
ns
ns
2
3
ADDR/CMD output setup with respect to MCK
1600 MT/s data rate
tDDKHAS
0.495
0.606
0.675
0.744
0.917
—
—
—
—
—
1333 MT/s data rate
1200 MT/s data rate
1066 MT/s data rate
800 MT/s data rate
ADDR/CMD output hold with respect to MCK
1600 MT/s data rate
tDDKHAX
tDDKHCS
tDDKHCX
tDDKHMH
ns
ns
ns
ns
3
3
3
4
0.495
0.606
0.675
0.744
0.917
—
—
—
—
—
1333 MT/s data rate
1200 MT/s data rate
1066 MT/s data rate
800 MT/s data rate
MCS[n] output setup with respect to MCK
1600 MT/s data rate
0.495
0.606
0.675
0.744
0.917
—
—
—
—
—
1333 MT/s data rate
1200 MT/s data rate
1066 MT/s data rate
800 MT/s data rate
MCS[n] output hold with respect to MCK
1600 MT/sdata rate
0.495
0.606
0.675
0.744
0.917
—
—
—
—
—
1333 MT/s data rate
1200 MT/s data rate
1066 MT/sdata rate
800 MT/s data rate
MCK to MDQS Skew
> 1066 MT/s data rate
800 MT/s data rate
–0.245
–0.375
0.245
0.375
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
71
Electrical characteristics
Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max
Unit
Notes
MDQ/MECC/MDM output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
ps
5
1600 MT/s data rate
1333 MT/s data rate
1200 MT/s data rate
1066 MT/s data rate
800 MT/s data rate
200
250
275
300
375
—
—
—
—
—
MDQ/MECC/MDM output hold with respect to
MDQS
tDDKHDX,
tDDKLDX
ps
5
1600 MT/s data rate
1333 MT/s data rate
1200 MT/s data rate
1066 MT/s data rate
800 MT/s data rate
MDQS preamble
MDQS post-amble
Notes:
200
250
—
—
275
—
300
—
—
375
tDDKHMP
tDDKHME
0.9 × tMCK
0.4 × tMCK
—
ns
ns
—
—
0.6 × tMCK
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK and MDQS/MDQS referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay
as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters
have been set to the same adjustment value. See the applicable chip reference manual for a description and explanation of
the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
NOTE
For the ADDR/CMD setup and hold specifications in Table 25, it is assumed that the clock
control register is set to adjust the memory clocks by ½ applied cycle.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
72
Freescale Semiconductor
Electrical characteristics
This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement
(t ).
DDKHMH
MCK[n]
MCK[n]
tMCK
tDDKHMH(max)
MDQS[n]
MDQS[n]
tDDKHMH(min)
Figure 10. t
timing diagram
DDKHMH
This figure shows the DDR3 and DDR3L SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS, tDDKHCS
tDDKHAX, tDDKHCX
ADDR/CMD
Write A0
tDDKHMP
NOOP
tDDKHMH
MDQS[n]
MDQ[x]
tDDKHME
tDDKHDS
tDDKLDS
D0
D1
tDDKLDX
tDDKHDX
Figure 11. DDR3 and DDR3L output timing diagram
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
73
Electrical characteristics
This figure provides the AC test load for the DDR3 and DDR3L controller bus.
GVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 12. DDR3 and DDR3L controller bus AC test load
2.10 eSPI
This section describes the DC and AC electrical specifications for the eSPI interface.
2.10.1 eSPI DC electrical characteristics
This table provides the DC electrical characteristics for the eSPI interface operating at CV = 3.3 V.
DD
1,2
Table 26. eSPI DC electrical characteristics (CV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
2.0
—
—
0.8
40
—
V
V
1
1
Input current (VIN = 0 V or VIN = CVDD
)
IIN
—
μA
V
2
Output high voltage
VOH
2.4
—
(CVDD = min, IOH = –2 mA)
Output low voltage
VOL
—
0.4
V
—
(CVDD = min, IOL = 2 mA)
Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
This table provides the DC electrical characteristics for the eSPI interface operating at CV = 2.5 V.
DD
Table 27. eSPI DC electrical characteristics (CV = 2.5 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
1.7
—
—
0.7
40
—
V
V
1
1
Input current (VIN = 0 V or VIN = CVDD
)
IIN
—
μA
V
2
Output high voltage
VOH
2.0
—
(CVDD = min, IOH = –1 mA)
Output low voltage
VOL
—
0.4
V
—
(CVDD = min, IOL = 1 mA)
Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
74
Freescale Semiconductor
Electrical characteristics
This table provides the DC electrical characteristics for the eSPI interface operating at CV = 1.8 V.
DD
Table 28. eSPI DC electrical characteristics (CV = 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
1.25
—
—
0.6
40
—
V
V
1
1
Input current (VIN = 0 V or VIN = CVDD
)
IIN
—
μA
V
2
Output high voltage
VOH
1.35
—
(CVDD = min, IOH = –0.5 mA)
Output low voltage
VOL
—
0.4
V
—
(CVDD = min, IOL = 0.5 mA)
Notes:
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
2.10.2 eSPI AC timing specifications
This table provides the eSPI input and output AC timing specifications.
Table 29. eSPI AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max
Unit Note
SPI_MOSI output—Master data (internal clock) hold time
tNIKHOX
2.36 +
(tPLATFORM_CLK * SP
MODE[HO_ADJ])
—
—
ns 2, 3
SPI_MOSI output—Master data (internal clock) delay
tNIKHOV
—
5.24 +
ns 2, 3
(tPLATFORM_CLK
*
SPMODE[HO_ADJ])
SPI_CS outputs—Master data (internal clock) hold time
SPI_CS outputs—Master data (internal clock) delay
eSPI inputs—Master data (internal clock) input setup time
eSPI inputs—Master data (internal clock) input hold time
Notes:
tNIKHOX2
tNIKHOV2
tNIIVKH
0
—
5
—
6.0
—
ns
ns
ns
ns
2
2
—
—
tNIIXKH
0
—
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid
(V).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
3. See the applicable chip reference manual for details on the SPMODE register.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
75
Electrical characteristics
This figure provides the AC test load for the eSPI.
CVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 13. eSPI AC test load
This figure represents the AC timing from Table 29 in master mode (internal clock). Note that although timing specifications
generally refer to the rising edge of the clock, this figure also applies when the falling edge is the active edge. Also, note that
the clock edge is selectable on eSPI.
SPICLK (output)
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO1
tNIKHOX
tNIKHOV
Output Signals:
SPIMOSI1
tNIKHOV2
tNIKHOX2
Output Signals:
SPI_CS[0:3]1
Figure 14. eSPI AC timing in master mode (Internal Clock) diagram
2.11 DUART
This section describes the DC and AC electrical specifications for the DUART interface.
2.11.1 DUART DC electrical characteristics
This table provides the DC electrical characteristics for the DUART interface.
Table 30. DUART DC electrical characteristics (OV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
2
—
V
V
1
1
—
0.8
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
76
Freescale Semiconductor
Electrical characteristics
Table 30. DUART DC electrical characteristics (OV = 3.3 V) (continued)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input current (OVIN = 0 V or OVIN = OVDD
)
IIN
—
2.4
—
40
—
μA
V
2
Output high voltage (OVDD = min, IOH = –2 mA)
Output low voltage (OVDD = min, IOL = 2 mA)
Notes:
VOH
VOL
—
—
0.4
V
1. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
2.11.2 DUART AC electrical specifications
This table provides the AC timing parameters for the DUART interface.
Table 31. DUART AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Value
Unit
Notes
Minimum baud rate
Maximum baud rate
Oversample rate
Notes:
fPLAT/(2*1,048,576)
fPLAT/(2*16)
16
baud
baud
—
1
1,2
3
1. fPLAT refers to the internal platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each 16th sample.
2.12 Ethernet: data path three-speed Ethernet (dTSEC),
management interface, IEEE Std 1588
This section provides the AC and DC electrical characteristics for the data path three-speed Ethernet controller, the Ethernet
management interface, and the IEEE Std 1588 interface.
2.12.1 SGMII timing specifications
See Section 2.20.8, “SGMII interface.”
2.12.2 MII and RGMII timing specifications
This section discusses the electrical characteristics for the MII and RGMII interfaces.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
77
Electrical characteristics
2.12.2.1 MII and RGMII DC electrical characteristics
This table shows the MII DC electrical characteristics when operating at LV = 3.3 V supply.
DD
Table 32. MII DC electrical characteristics (LV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
IIH
2.0
—
—
0.90
V
V
1
—
2
Input high current (VIN = LVDD
)
—
40
μA
μA
V
Input low current (VIN = GND)
IIL
–600
2.4
—
2
Output high voltage (LVDD = min, IOH = –4.0 mA)
Output low voltage (LVDD = min, IOL = 4.0 mA)
Notes:
VOH
VOL
LVDD + 0.3
0.50
—
—
GND
V
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3.
This table shows the MII and RGMII DC electrical characteristics when operating at LV = 2.5 V supply.
DD
Table 33. MII and RGMII DC electrical characteristics (LV = 2.5 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
VIL
1.7
—
—
0.7
40
—
V
V
1
1
Input low voltage
Input current (LVIN = 0 V or LVIN = LVDD
)
IIH
—
μA
V
2
Output high voltage (LVDD = min, IOH = –1.0 mA)
Output low voltage (LVDD = min, IOL = 1.0 mA)
Notes:
VOH
VOL
2.0
—
—
—
0.4
V
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3.
2.12.2.2 MII AC timing specifications
This section describes the MII transmit and receive AC timing specifications.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
78
Freescale Semiconductor
Electrical characteristics
This table provides the MII transmit AC timing specifications.
Table 34. MII transmit AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
tMTX
399.96
39.996
35
400
40
—
400.04
40.004
65
ns
ns
%
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
MTXH/tMTX
tMTKHDX
tMTXR
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise (20%–80%)
TX_CLK data clock fall (80%–20%)
0
—
25
ns
ns
ns
1.0
—
4.0
tMTXF
1.0
—
4.0
This figure shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXF
tMTXH
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 15. MII transmit AC timing diagram
This table provides the MII receive AC timing specifications.
Table 35. MII Receive AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
RX_CLK clock period 10 Mbps
Symbol
Min
Typ
Max
Unit
tMRX
tMRX
399.96
39.996
35
400
40
—
400.04
40.004
65
ns
ns
%
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
MRXH/tMRX
tMRDVKH
tMRDXKH
tMRXR
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%-80%)
10.0
10.0
1.0
—
—
ns
ns
ns
ns
—
—
—
4.0
RX_CLK clock fall time (80%-20%)
tMRXF
1.0
—
4.0
Note: The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
79
Electrical characteristics
This figure provides the AC test load for eTSEC.
LVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 16. eTSEC AC test load
This figure shows the MII receive AC timing diagram.
tMRX
tMRXR
RX_CLK
tMRXF
Valid Data
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRDVKH
tMRDXKL
Figure 17. MII Receive AC timing diagram
2.12.2.3 RGMII AC timing specifications
This table presents the RGMII AC timing specifications.
Table 36. RGMII AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Typ
Max
Unit
Notes
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock period duration
tSKRGT_TX
tSKRGT_RX
tRGT
–500
1.0
7.2
40
0
500
2.6
8.8
60
ps
ns
ns
%
5
2
—
8.0
50
50
—
3
Duty cycle for 10BASE-T and 100BASE-TX
Duty cycle for Gigabit
tRGTH RGT
tRGTH/tRGT
tRGTR
/t
3, 4
—
—
45
55
%
Rise time (20%–80%)
—
0.75
ns
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
80
Freescale Semiconductor
Electrical characteristics
Table 36. RGMII AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Typ
Max
Unit
Notes
Fall time (20%–80%)
Notes:
tRGTF
—
—
0.75
ns
—
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.
Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. The tSKRGT_RX specification implies that PC board design requires clocks to be routed such that an additional trace delay of
greater than 1.5 ns is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay
inside their chip. If so, additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speeds transitioned
between.
5. The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm.
This figure shows the RGMII AC timing and multiplexing diagrams.
ꢀ
ꢏꢀꢁ
ꢀ
ꢏꢀꢁꢚ
ꢀꢁꢂꢃꢄꢅꢆ
ꢐꢑꢒꢓꢑꢒ
ꢀ
ꢀ
ꢙꢆꢏꢀꢁꢃꢁꢂ
ꢙꢆꢏꢀꢁꢃꢁꢂ
ꢁꢂꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢌ
ꢐꢑꢒꢓꢑꢒ
ꢁꢂꢇꢈꢍꢊꢎꢌ
ꢁꢂꢖꢗ
ꢁꢂꢇꢈꢉꢊꢋꢌ
ꢁꢂꢖꢏꢏ
ꢁꢂꢃꢄꢁꢅ
ꢐꢑꢒꢓꢑꢒ
ꢏꢂꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢌ
ꢔꢕꢓꢑꢒ
ꢏꢂꢇꢈꢍꢊꢎꢌ
ꢏꢂꢇꢘ
ꢏꢂꢇꢈꢉꢊꢋꢌ
ꢏꢂꢖꢏꢏ
ꢏꢂꢃꢄꢁꢅ
ꢔꢕꢓꢑꢒ
ꢒ
ꢒ
ꢙꢆꢏꢀꢁꢃꢏꢂ
ꢙꢆꢏꢀꢁꢃꢏꢂ
ꢏꢂꢃꢄꢅꢆ
ꢔꢕꢓꢑꢒ
ꢒ
ꢏꢀꢁꢚ
ꢒ
ꢏꢀꢁ
Figure 18. RGMII AC timing and multiplexing diagrams
2.12.3 Ethernet management interface
This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces. EMI1 is the PHY management interface
controlled by the MDIO controller associated with Frame Manager 1 1GMAC-1. EMI2 is the XAUI PHY management interface
controlled by the MDIO controller associated with Frame Manager 1 10GMAC-0.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
81
Electrical characteristics
2.12.3.1 Ethernet management interface 1 DC electrical characteristics
The Ethernet management interface 1 is defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for the
Ethernet management interface is provided in this table.
Table 37. Ethernet management Interface 1 DC electrical characteristics (LV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
VIL
IIH
2.0
—
—
0.9
40
—
V
V
2
2
Input low voltage
Input high current (LVDD = Max, VIN = 2.1 V)
Input low current (LVDD = Max, VIN = 0.5 V)
Output high voltage (LVDD = Min, IOH = –1.0 mA)
Output low voltage (LVDD = Min, IOL = 1.0 mA)
Note:
—
μA
μA
V
1
IIL
–600
2.4
—
1
VOH
VOL
—
—
—
0.4
V
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 2 and Table 3.
2. The min VIL and max VIH values are based on the respective LVIN values found in Table 3.
The Ethernet management interface 1 is defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for the
Ethernet management interface 1 is provided in Table 37.
Table 38. Ethernet management interface 1 DC electrical characteristics (LV = 2.5 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
VIL
1.7
—
—
0.7
40
—
V
V
1
1
Input low voltage
Input current (LVIN = 0 V or LVIN = LVDD
)
IIH
—
μA
V
2
Output high voltage (LVDD = Min, IOH = –1.0 mA)
Output low voltage (LVDD = Min, IOL = 1.0 mA)
Note:
VOH
VOL
2.4
—
—
—
0.4
V
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
2.12.3.2 Ethernet management interface 2 DC electrical characteristics
Ethernet management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels.
LV must be powered to use this interface. The DC electrical characteristics for EMI2_MDIO and EMI2_MDC are provided
DD
in this section.
Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
VIH
VIL
0.84
—
—
V
V
—
—
0.36
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
82
Freescale Semiconductor
Electrical characteristics
Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V) (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Note
Output low voltage (IOL = 100 μA)
Output low current (VOL = 0.2 V)
Input capacitance
VOL
IOL
—
4
0.2
—
V
—
—
—
mA
pF
CIN
—
10
2.12.3.3 Ethernet management interface 1 AC timing specifications
This table provides the Ethernet management interface 1 AC timing specifications.
Table 40. Ethernet management interface 1 AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
MDC frequency
Symbol1
Min
Typ
Max
Unit
Note
fMDC
—
—
—
—
—
—
2.5
MHz
ns
2
—
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
Note:
tMDCH
160
—
tMDKHDX
tMDDVKH
tMDDXKH
(16 × tplb_clk) – 6
(16 × tplb_clk) + 6
ns
3, 4
—
8
0
—
—
ns
ns
—
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or
data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D)
reaching the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of
the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the frame manager clock frequency. The delay is equal to 16 frame manager clock periods
6 ns. For example, with a frame manager clock of 333 MHz, the min/max delay is 48 ns 6 ns. Similarly, if the frame
manager clock is 400 MHz, the min/max delay is 40 ns 6 ns.
4. tplb_clk is the frame manager clock period.
2.12.3.4 Ethernet management interface 2 AC electrical characteristics
This table provides the Ethernet management interface 2 AC timing specifications.
Table 41. Ethernet management interface 2 AC timing specifications
For recommended operating conditions, see Table 3.
Parameter/Condition
MDC frequency
Symbol1
Min
Typ
Max
Unit
Note
fMDC
—
—
—
—
—
2.5
MHz
ns
2
—
3
MDC clock pulse width high
MDC to MDIO delay
tMDCH
160
—
(0.5 ×(1/fMDC)) + 6
—
tMDKHDX
tMDDVKH
(0.5 ×(1/fMDC)) – 6
8
ns
MDIO to MDC setup time
ns
—
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
83
Electrical characteristics
Table 41. Ethernet management interface 2 AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter/Condition
Symbol1
tMDDXKH
Min
Typ
Max
Unit
Note
MDIO to MDC hold time
0
—
—
ns
—
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or
data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach
the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the frame manager clock frequency (MIIMCFG [MgmtClk] field determines the clock
frequency of the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the management data clock frequency, fMDC. The delay is equal to 0.5 management data
clock period 6 ns. For example, with a management data clock of 2.5 MHz, the min/max delay is 200 ns 6 ns.
This figure shows the Ethernet management interface timing diagram.
tMDC
tMDCR
MDC
tMDCF
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 19. Ethernet management interface timing diagram
2.12.4 eTSEC IEEE Std 1588 timing specifications
This section discusses the electrical characteristics for the eTSEC IEEE Std 1588 interfaces.
2.12.4.1 eTSEC IEEE Std 1588 DC electrical characteristics
This table shows eTSEC IEEE Std 1588 DC electrical characteristics when operating at LV = 3.3 V supply.
DD
Table 42. eTSEC IEEE 1588 DC electrical characteristics (LV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
VIL
IIH
2.0
—
—
0.9
40
V
V
2
2
1
Input low voltage
Input high current (LVDD = Max, VIN = 2.1 V)
—
μA
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
84
Freescale Semiconductor
Electrical characteristics
Table 42. eTSEC IEEE 1588 DC electrical characteristics (LV = 3.3 V) (continued)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input low current (LVDD = Max, VIN = 0.5 V)
Output high voltage (LVDD = Min, IOH = –1.0 mA)
Output low voltage (LVDD = Min, IOL = 1.0 mA)
Note:
IIL
–600
2.4
—
—
μA
V
1
VOH
VOL
—
—
—
0.4
V
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 2 and Table 3.
2. The min VIL and max VIH values are based on the respective LVIN values found in Table 3.
2.12.4.2 eTSEC IEEE Std 1588 AC specifications
This table provides the IEEE 1588 AC timing specifications.
Table 43. eTSEC IEEE 1588 AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
TSEC_1588_CLK clock period
TSEC_1588_CLK duty cycle
tT1588CLK
3.3
40
—
TRX_CLK × 7
ns
%
1, 2
3
tT1588CLKH
tT1588CLK
/
50
60
TSEC_1588_CLK peak-to-peak jitter
Rise time eTSEC_1588_CLK (20%–80%)
Fall time eTSEC_1588_CLK (80%–20%)
TSEC_1588_CLK_OUT clock period
TSEC_1588_CLK_OUT duty cycle
tT1588CLKINJ
tT1588CLKINR
tT1588CLKINF
tT1588CLKOUT
—
—
—
—
—
50
250
2.0
2.0
—
ps
ns
ns
ns
%
—
—
—
—
—
1.0
1.0
2 × tT1588CLK
30
tT1588CLKOTH
/
70
tT1588CLKOUT
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_IN pulse width
Notes:
tT1588OV
0.5
—
—
3.0
—
ns
ns
—
2
tT1588TRIGH
2 × tT1588CLK_MAX
1.TRX_CLK is the maximum clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the QorIQ Integrated
Processor Reference Manual for a description of TMR_CTRL registers.
2. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK be 2800, 280, and 56 ns, respectively.
3. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the QorIQ Integrated
Processor Reference Manual for a description of TMR_CTRL registers.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
85
Electrical characteristics
This figure shows the data and command output AC timing diagram.
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_CLK_OUT
tT1588OV
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_OUT
Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting. Otherwise, it
is counted starting at the falling edge.
Figure 20. eTSEC IEEE 1588 output AC timing
This figure shows the data and command input AC timing diagram.
tT1588CLK
tT1588CLKH
TSEC_1588_CLK
TSEC_1588_TRIG_IN
tT1588TRIGH
Figure 21. eTSEC IEEE 1588 input AC timing
2.13 USB
This section provides the AC and DC electrical specifications for the USB interface.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
86
Freescale Semiconductor
Electrical characteristics
2.13.1 USB DC electrical characteristics
This table provides the DC electrical characteristics for the USB interface at USB_V _3P3 = 3.3 V.
DD
Table 44. USB DC electrical characteristics (USB_VDD_3P3 = 3.3 V)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage1
Input low voltage
VIH
VIL
IIN
2.0
—
—
0.8
40
V
V
1
1
2
Input current (USB_VIN_3P3 = 0 V or USB_VIN_3P3 =
USB_VDD_3P3)
—
μA
Output high voltage (USB_VDD_3P3 = min, IOH = –2 mA)
Output low voltage (USB_VDD_3P3 = min, IOL = 2 mA)
Notes:
VOH
VOL
2.8
—
—
V
V
—
—
0.3
1. The min VILand max VIH values are based on the respective min and max USB_VIN_3P3 values found in Table 3.
2. The symbol USB_VIN_3P3, in this case, represents the USB_VIN_3P3 symbol referenced in Section 2.1.2, “Recommended
operating conditions.”
2.13.2 USB AC electrical specifications
This table provides the USB clock input (USBn_CLKIN) AC timing specifications.
Table 45. USBn_CLKIN AC timing specifications
For recommended operating conditions, see Table 3.
Parameter/Condition
Frequency range
Conditions
Symbol
Min
Typ
Max
Unit
—
—
fUSB_CLK_IN
tCLK_TOL
tCLK_DUTY
tCLK_PJ
—
–0.005
40
24
0
—
0.005
60
MHz
%
Clock frequency tolerance
Reference clock duty cycle
Measured at 1.6 V
50
—
%
Total input jitter/time interval
error
Peak-to-peak value measured with a
second-order high-pass filter of 500 kHz
bandwidth
—
5
ps
This figure provides the USB AC test load.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 22. USB AC test load
2.14 Enhanced local bus interface (eLBC)
This section describes the DC and AC electrical specifications for the enhanced local bus interface.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
87
Electrical characteristics
2.14.1 Enhanced local bus DC electrical characteristics
This table provides the DC electrical characteristics for the enhanced local bus interface operating at BV = 3.3 V.
DD
Table 46. Enhanced local bus DC electrical characteristics (BV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
VIL
2.0
—
—
0.8
40
—
V
V
1
1
Input low voltage
Input current (VIN = 0 V or VIN = BVDD
)
IIN
—
μA
V
2
Output high voltage
VOH
2.4
—
(BVDD = min, IOH = –2 mA)
Output low voltage
VOL
—
0.4
V
—
(BVDD = min, IOL = 2 mA)
Notes:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
This table provides the DC electrical characteristics for the enhanced local bus interface operating at BV = 2.5 V.
DD
Table 47. Enhanced local bus DC electrical characteristics (BV = 2.5 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
IIN
1.7
—
—
0.7
40
—
V
V
1
1
Input low voltage
Input current (VIN = 0 V or VIN = BVDD
)
—
μA
V
2
Output high voltage
VOH
2.0
—
(BVDD = min, IOH = –1 mA)
Output low voltage
VOL
—
0.4
V
—
(BVDD = min, IOL = 1 mA)
Notes:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
This table provides the DC electrical characteristics for the enhanced local bus interface operating at BV = 1.8 V.
DD
Table 48. Enhanced local bus DC electrical characteristics (BV = 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Input high voltage
Input low voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
1.25
—
—
V
V
1
1
0.6
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
88
Freescale Semiconductor
Electrical characteristics
Table 48. Enhanced local bus DC electrical characteristics (BV = 1.8 V) (continued)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input current (VIN = 0 V or VIN = BVDD
)
IIN
—
40
—
μA
2
Output high voltage
VOH
1.35
V
—
(BVDD = min, IOH = –0.5 mA)
Output low voltage
VOL
—
0.4
V
—
(BVDD = min, IOL = 0.5 mA)
Notes:
1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.
2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
2.14.2 Enhanced local bus AC timing specifications
This section describes the AC timing specifications for the enhanced local bus interface.
2.14.2.1 Test condition
This figure provides the AC test load for the enhanced local bus.
Output
BVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 23. Enhanced local bus AC test load
2.14.2.2 Local bus AC timing specification
All output signal timings are relative to the falling edge of any LCLKs. The external circuit must use the rising edge of the
LCLKs to latch the data.
All input timings except LGTA/LUPWAIT/LFRB are relative to the rising edge of LCLKs. LGTA/LUPWAIT/LFRB are relative
to the falling edge of LCLKs.
This table describes the timing specifications of the local bus interface.
Table 49. Enhanced local bus timing specifications
For recommended operating conditions, see Table 3.
Parameter
Local bus cycle time
Symbol1
Min
Max
Unit
Notes
tLBK
10
45
—
6
—
55
ns
%
—
—
2
Local bus duty cycle
t
LBKH/tLBK
tLBKSKEW
tLBIVKH
LCLK[n] skew to LCLK[m]
150
—
ps
ns
Input setup
—
(except LGTA/LUPWAIT/LFRB)
Input hold
tLBIXKH
1
—
ns
—
(except LGTA/LUPWAIT/LFRB)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
89
Electrical characteristics
Table 49. Enhanced local bus timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol1
tLBIVKL
Min
Max
Unit
Notes
Input setup
(for LGTA/LUPWAIT/LFRB)
6
—
ns
—
Input hold
(for LGTA/LUPWAIT/LFRB)
tLBIXKL
1
—
—
1.5
—
2
ns
ns
ns
ns
ns
—
—
5
Output delay
(Except LALE)
tLBKLOV
tLBKLOX
tLBKLOZ
tLBONOT
Output hold
(Except LALE)
-3.5
—
Local bus clock to output high impedance
for LAD/LDP
3
LALE output negation to LAD/LDP output
transition (LATCH hold time)
2 platform clock
cycles—1ns
—
4
(LBCR[AHD]=1)
4 platform clock
cycles—1ns
—
(LBCR[AHD]=0)
Notes:
1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question.
2. Skew measured between different LCLKs at BVDD/2.
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined
by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not
the external LCLK. LCLK cycle = eLBC controller clock cycle X LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults to
0 and eLBC runs at maximum hold time.
5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
90
Freescale Semiconductor
Electrical characteristics
This figure shows the AC timing diagram of the local bus interface.
LCLK[m]
tLBIXKH
tLBIVKH
Input Signals
(Except LGTA/LUPWAIT/LFRB)
tLBIVKL
Input Signal
(LGTA/LUPWAIT/LFRB)
tLBIXKL
tLBKLOV
tLBKLOX
Output Signals
(Except LALE)
LAD
(address phase)
tLBONOT
LALE
tLBKLOZ
LAD/LDP
(data phase)
Figure 24. Enhanced local bus signals
Figure 25 applies to all three controllers that eLBC supports: GPCM, UPM, and FCM.
For input signals, the local bus AC timing data is used directly for all three controllers.
For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay
value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed
to delay by t (0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is t + t .
acs
acs
LBKLOV
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
91
Electrical characteristics
This figure shows how the local bus AC timing diagram applies to GPCM. The same principle applies to UPM and FCM.
LCLK
taddr
taddr
address
LAD[0:31]
read data
address
write data
tLBONOT
tLBONOT
LALE
tarcs + tLBKLOV
tawcs + tLBKLOV
LCS_B
tLBKLOX
taoe + tLBKLOV
LGPL2/LOE_B
LWE_B
twen
tawe + tLBKLOV
trc
toen
twc
LBCTL
read
write
1
2
taddr is programmable and determined by LCRR[EADC] and ORx[EAD].
tarcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. See the applicable chip reference manual.
Figure 25. GPCM Output timing diagram
2.15 Enhanced secure digital host controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface.
2.15.1 eSDHC DC electrical characteristics
This table provides the DC electrical characteristics for the eSDHC interface.
Table 50. eSDHC interface DC electrical characteristics
For recommended operating conditions, see Table 3.
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
Notes
VIH
VIL
—
—
—
0.625 × CVDD
—
—
V
V
1
1
Input low voltage
0.25 × CVDD
Input/output leakage current
Output high voltage
IIN/IOZ
VOH
–50
50
—
μA
V
—
—
IOH = –100 μA at
0.75 × CVDD
CVDD min
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
92
Freescale Semiconductor
Electrical characteristics
Table 50. eSDHC interface DC electrical characteristics (continued)
For recommended operating conditions, see Table 3.
Characteristic
Output low voltage
Symbol
Condition
Min
Max
Unit
Notes
VOL
IOL = 100μA at
—
0.125 × CVDD
V
—
CVDD min
Output high voltage
Output low voltage
Notes:
VOH
VOL
IOH = –100 μA at
CVDD – 0.2
—
—
V
V
2
2
CVDD min
IOL = 2 mA at
CVDD min
0.3
1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.
2. Open drain mode for MMC cards only.
2.15.2 eSDHC AC timing specifications
This table provides the eSDHC AC timing specifications as defined in Figure 26 and Figure 27.
Table 51. eSDHC AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max
Unit
Notes
SD_CLK clock frequency:
fSHSCK
MHz
2, 4
SD Full speed/high speed mode
MMC Full speed/high speed mode
0
25/50
20/52
SD_CLK clock low time—Full-speed/High-speed mode
SD_CLK clock high time—Full-speed/High-speed mode
SD_CLK clock rise and fall times
tSHSCKL
tSHSCKH
tSHSCKR/
10/7
10/7
—
—
—
3
ns
ns
ns
4
4
4
tSHSCKF
Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
Notes:
tSHSIVKH
tSHSIXKH
tSHSKHOV
5
—
—
3
ns
ns
ns
3, 4, 5
4, 5
2.5
–3
4, 5
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC
high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing
the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. In full-speed mode, the clock frequency value can be 0–25 MHz for an SD card and 0–20 MHz for an MMC card. In high-speed
mode, the clock frequency value can be 0–50 MHz for an SD card and 0–52 MHz for an MMC card.
3. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should not
exceed 1 ns. For any high speed or default speed mode SD card, the oneway routing delay between Host and Card on
SD_CLK, SD_CMD and SD_DATx should not exceed 1.5 ns.
4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF
5. The parameter values apply to both full speed and high speed modes.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
93
Electrical characteristics
This figure provides the eSDHC clock input timing diagram.
eSDHC
External Clock
VM
VM
VM
operational mode
tSHSCKL
tSHSCKH
tSHSCK
tSHSCKF
tSHSCKR
VM = Midpoint Voltage (OVDD/2)
Figure 26. eSDHC clock input timing diagram
This figure provides the data and command input/output timing diagram.
VM
VM
VM
VM
SD_CK
External Clock
tSHSIXKH
tSHSIVKH
SD_DAT/CMD
Inputs
SD_DAT/CMD
Outputs
tSHSKHOV
VM = Midpoint Voltage (OVDD/2)
Figure 27. eSDHC data and command input/output timing diagram referenced to clock
2.16 Multicore programmable interrupt controller (MPIC)
specifications
This section describes the DC and AC electrical specifications for the multicore programmable interrupt controller.
2.16.1 MPIC DC specifications
This table provides the DC electrical characteristics for the MPIC interface.
Table 52. MPIC DC electrical characteristics (OV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
2.0
—
—
0.8
40
—
V
V
1
1
Input current (OVIN = 0 V or OVIN = OVDD
)
IIN
—
μA
V
2
Output high voltage (OVDD = min, IOH = –2 mA)
VOH
2.4
—
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
94
Freescale Semiconductor
Electrical characteristics
Table 52. MPIC DC electrical characteristics (OV = 3.3 V) (continued)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Output low voltage (OVDD = min, IOL = 2 mA)
VOL
—
0.4
V
—
Notes:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3
2.16.2 MPIC AC timing specifications
This table provides the MPIC input and output AC timing specifications.
Table 53. MPIC Input AC timing specifications
For recommended operating conditions, see Table 3.
Characteristic
Symbol
Min
Max
Unit
Notes
MPIC inputs—minimum pulse width
tPIWID
3
—
SYSCLKs
1
Notes:
1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs should be synchronized before use by any
external synchronous logic. MPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode
2.17 JTAG controller
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface.
2.17.1 JTAG DC electrical characteristics
This table provides the JTAG DC electrical characteristics.
Table 54. JTAG DC electrical characteristics (OV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
2.0
—
—
0.8
40
—
V
V
1
1
Input current (OVIN = 0 V or OVIN = OVDD
)
IIN
—
μA
V
2
Output high voltage (OVDD = min, IOH = –2 mA)
Output low voltage (OVDD = min, IOL = 2 mA)
Notes:
VOH
VOL
2.4
—
—
—
0.4
V
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol found in Table 3.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
95
Electrical characteristics
2.17.2 JTAG AC timing specifications
This table provides the JTAG AC timing specifications as defined in Figure 28 through Figure 31.
Table 55. JTAG AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
fJTG
tJTG
0
33.3
—
—
2
MHz
ns
—
—
—
—
2
30
15
0
tJTKHKL
JTGR/tJTGF
tTRST
ns
t
ns
25
—
—
ns
Input setup times
tJTDVKH
ns
—
Boundary-scan USB only
Boundary-scan except USB
TMS
14
4
4
TDI
5
Input hold times
tJTDXKH
tJTKLDV
10
—
—
ns
—
Output valid times
Boundary-scan data
TDO
15
10
—
ns
ns
ns
3
—
3
Output hold times
tJTKLDX
0
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to
the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must
be added for trace lengths, vias, and connectors in the system.
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Output
OVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 28. AC test load for the JTAG interface
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
96
Freescale Semiconductor
Electrical characteristics
This figure provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
tJTKHKL
VM
VM
tJTGR
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 29. JTAG clock input timing diagram
This figure provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 30. TRST timing diagram
This figure provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 31. Boundary-scan timing diagram
2
2.18 I C
2
This section describes the DC and AC electrical characteristics for the I C interface.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
97
Electrical characteristics
2.18.1 I2C DC electrical characteristics
2
This table provides the DC electrical characteristics for the I C interfaces.
2
Table 56. I C DC electrical characteristics (OV = 3.3 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
VIL
2.0
—
0
—
0.8
0.4
50
V
V
1
1
2
3
Input low voltage
Output low voltage (OVDD = min, IOL = 2 mA)
VOL
V
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL
0
ns
Input current each I/O pin (input voltage is between
0.1 × OVDD and 0.9 × OVDD(max)
II
–40
0
40
10
μA
4
Capacitance for each I/O pin
CI
pF
—
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. Output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the applicable chip reference manual for information about the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
2.18.2 I2C AC electrical specifications
2
This table provides the AC timing parameters for the I C interfaces.
2
Table 57. I C AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max
Unit
Notes
SCL clock frequency
fI2C
tI2CL
0
400
—
kHz
μs
2
Low period of the SCL clock
1.3
0.6
0.6
0.6
—
—
—
—
High period of the SCL clock
tI2CH
—
μs
Setup time for a repeated START condition
tI2SVKH
tI2SXKL
—
μs
Hold time (repeated) START condition (after this period,
the first clock pulse is generated)
—
μs
Data setup time
tI2DVKH
tI2DXKL
100
—
ns
—
3
Data input hold time:
CBUS compatible masters
I2C bus devices
μs
—
0
—
—
Data output delay time
tI2OVKL
—
0.9
—
μs
μs
μs
4
Setup time for STOP condition
t
0.6
1.3
—
—
I2PVKH
Bus free time between a STOP and START condition
tI2KHDX
—
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
98
Freescale Semiconductor
Electrical characteristics
2
Table 57. I C AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol1
Min
Max
Unit
Notes
Noise margin at the LOW level for each connected
device (including hysteresis)
VNL
0.1 × OVDD
—
V
—
Noise margin at the HIGH level for each connected
device (including hysteresis)
VNH
Cb
0.2 × OVDD
—
V
—
—
Capacitive load for each bus line
—
400
pF
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Freescale application note AN2919, “Determining the
I2C Frequency Divider Ratio for SCL.”
3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal)
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When
the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are
balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time
is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter,
application note AN2919 referred to in note 2 above is recommended.
4. The maximum tI2OVKL must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
2
This figure provides the AC test load for the I C.
Output
OVDD/2
Z0 = 50 Ω
RL = 50 Ω
2
Figure 32. I C AC test load
2
This figure shows the AC timing diagram for the I C bus.
SDA
tI2DVKH
tI2KHKL
tI2KHDX
tI2SXKL
tI2CL
SCL
tI2CH
tI2DXKL, I2OVKL
tI2SVKH
tI2SXKL
tI2PVKH
t
S
Sr
Figure 33. I C bus AC timing diagram
P
S
2
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
99
Electrical characteristics
2.19 GPIO
This section describes the DC and AC electrical characteristics for the GPIO interface.
2.19.1 GPIO DC electrical characteristics
This table provides the DC electrical characteristics for GPIO pins operating at 3.3 V.
Table 58. GPIO DC electrical characteristics (LV or OV = 3.3 V)
DD
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
VIH
VIL
2.0
—
—
0.8
40
—
V
V
1
1
Input current (OVIN = 0 V or OVIN = OVDD
)
IIN
—
μA
V
2
Output high voltage (OVDD = min, IOH = –2 mA)
Output low voltage (OVDD = min, IOL = 2 mA)
Notes:
VOH
VOL
2.4
—
—
—
0.4
V
1. The min VILand max VIH values are based on the min and max L/OVIN respective values found in Table 3.
2. The symbol VIN, in this case, represents the L/OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
This table provides the DC electrical characteristics for GPIO pins operating at LV = 2.5 V.
DD
Table 59. GPIO DC electrical characteristics (LV = 2.5 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Input high voltage
Symbol
Min
Max
Unit
Notes
VIH
VIL
1.7
—
—
0.7
40
—
V
V
1
1
Input low voltage
Input current (VIN = 0 V or VIN = LVDD
)
IIN
—
μA
V
2
Output high voltage
VOH
2.0
—
(LVDD = min, IOH = –2 mA)
Output low voltage
VOL
—
0.4
V
—
(LVDD = min, IOH = 2 mA)
Notes:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
100
Freescale Semiconductor
Electrical characteristics
2.19.2 GPIO AC timing specifications
This table provides the GPIO input and output AC timing specifications.
Table 60. GPIO Input AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Unit
Notes
GPIO inputs—minimum pulse width
Trust inputs—minimum pulse width
Note:
tPIWID
tTIWID
20
3
ns
1
2
SYSCLK
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
2. Trust inputs are asynchronous to any visible clock. Trust inputs are required to be valid for at least tTIWID to ensure proper
operation. For low power trust input pin LP_TMP_DETECT, the voltage is VDD_LP and see Table 3.for the voltage
requirement.
This figure provides the AC test load for the GPIO.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 34. GPIO AC test load
2.20 High-speed serial interfaces (HSSI)
The chip features a serializer/deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The
SerDes interface can be used for PCI Express, XAUI, Aurora and SGMII data transfers.
This section describes the common portion of SerDes DC electrical specifications: the DC requirement for SerDes reference
clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.
2.20.1 Signal terms definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description
and specification of differential signals.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
101
Electrical characteristics
This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This
figure shows the waveform for either a transmitter output (SD_TXn and SD_TXn) or a receiver input (SD_RXn and SD_RXn).
Each signal swings between A volts and B volts where A > B.
SD_TXn
SD_RXn
or
A Volts
B Volts
Vcm = (A + B)/2
SD_TXn
SD_RXn
or
Differential Swing, VID or VOD = A – B
Differential Peak Voltage, VDIFFp = |A – B|
Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)
Figure 35. Differential voltage definitions for transmitter or receiver
Using this waveform, the definitions are as shown in the following list. To simplify the illustration, the definitions assume that
the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment:
Single-Ended Swing
The transmitter output signals and the receiver input signals SD_TXn, SD_TXn, SD_RXn and
SD_RXn each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s
single-ended swing.
Differential Output Voltage, V (or Differential Output Swing):
OD
The differential output voltage (or swing) of the transmitter, V , is defined as the difference of
OD
the two complementary output voltages: V
positive or negative.
– V
The V value can be either
SD_TXn
SD_TXn. OD
Differential Input Voltage, V (or Differential Input Swing):
ID
The differential input voltage (or swing) of the receiver, V , is defined as the difference of the two
ID
complementary input voltages: V
negative.
– V
The V value can be either positive or
SD_RXn
SD_RXn. ID
Differential Peak Voltage, V
DIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as the differential peak voltage, V
= |A – B| volts.
DIFFp
Differential Peak-to-Peak, V
DIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
V
= 2 × V
= 2 × |(A – B)| volts, which is twice the differential swing in amplitude, or
DIFFp-p
DIFFp
twice of the differential peak. For example, the output differential peak-peak voltage can also be
calculated as V = 2 × |V |.
TX-DIFFp-p
OD
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SD_TXn, for
example) from the non-inverting signal (SD_TXn, for example) within a differential pair. There is
only one signal trace curve in a differential waveform. The voltage represented in the differential
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
102
Freescale Semiconductor
Electrical characteristics
waveform is not referenced to ground. See Figure 40, “Differential measurement points for rise
and fall time,” as an example for differential waveform.
Common Mode Voltage, V
cm
The common mode voltage is equal to half of the sum of the voltages between each conductor of
a balanced interchange circuit and ground. In this example, for SerDes output,
V
= (V
+ V
) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
cm_out
SD_TXn
SD_TXn
complementary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. It may be different between the
receiver input and driver output circuits within the same component. It is also referred to as the DC
offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (V ) has
OD
the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV.
In other words, V is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (V
) is 500 mV.
OD
DIFFp
The peak-to-peak differential voltage (V
) is 1000 mV p-p.
DIFFp-p
2.20.2 SerDes reference clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK1 and SD_REF_CLK1 for SerDes bank1, SD_REF_CLK2
and SD_REF_CLK2 for SerDes bank2, SD_REF_CLK3 and SD_REF_CLK3 for SerDes bank3, and SD_REF_CLK4 and
SD_REF_CLK4 for SerDes bank4.
SerDes banks 1–4 may be used for various combinations of the following IP blocks based on the RCW Configuration field
SRDS_PRTCL:
•
•
•
•
SerDes bank 1: PEX1/2/3, SGMII (1.25 Gbps only) or Aurora.
SerDes bank 2: SGMII (1.25 or 3.125 GBaud) or XAUI.
SerDes bank 3: SATA, or XAUI.
SerDes bank 4: SATA
The following sections describe the SerDes reference clock requirements and provide application information.
2.20.2.1 SerDes reference clock receiver characteristics
This figure shows a receiver reference diagram of the SerDes reference clocks.
50 Ω
SD_REF_CLKn
Input
Amp
SD_REF_CLKn
50 Ω
Figure 36. Receiver of SerDes reference clocks
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
103
Electrical characteristics
The characteristics of the clock signals are as follows:
•
The SerDes transceivers core power supply voltage requirements (SV ) are as specified in Section 2.1.2,
DD
“Recommended operating conditions.”
•
The SerDes reference clock receiver reference circuit structure is as follows:
— The SD_REF_CLKn and SD_REF_CLKn are internally AC-coupled differential inputs as shown in Figure 36.
Each differential clock input (SD_REF_CLKn or SD_REF_CLKn) has on-chip 50-Ω termination to SGND
followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the differential mode and
single-ended mode descriptions below for detailed requirements.
•
The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷ 50 = 8 mA)
while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle
can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SD_REF_CLKn and SD_REF_CLKn inputs cannot drive 50 Ω to SGND DC or the drive
strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip.
•
The input amplitude requirement is described in detail in the following sections.
2.20.2.2 DC-level requirement for SerDes reference clocks
The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
•
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, as described in Section 2.20.2.1, “SerDes reference clock receiver
characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) as between 100 mV and 400 mV. Figure 37 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLKn
Vmax < 800 mV
100 mV < Vcm < 400 mV
Vmin > 0 V
SD_REF_CLKn
Figure 37. Differential reference clock input DC requirements (external DC-coupled)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
104
Freescale Semiconductor
Electrical characteristics
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock
receiver operate in different common mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing
below and above the common mode voltage (SGND). Figure 38 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLKn
Vmax < Vcm + 400 mV
Vcm
Vmin > Vcm – 400 mV
Figure 38. Differential reference clock input DC requirements (external AC-coupled)
SD_REF_CLKn
•
Single-Ended Mode
— The reference clock can also be single-ended. The SD_REF_CLKn input amplitude (single-ended swing) must be
between 400 mV and 800 mV peak-peak (from V
tied to ground.
to V
) with SD_REF_CLKn either left unconnected or
MIN
MAX
— The SD_REF_CLKn input average voltage must be between 200 and 400 mV. Figure 39 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SD_REF_CLKn) through the same source impedance as the clock input (SD_REF_CLKn) in use.
400 mV < SD_REF_CLKn Input Amplitude < 800 mV
SD_REF_CLKn
0 V
SD_REF_CLKn
Figure 39. Single-ended reference clock input DC requirements
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
105
Electrical characteristics
2.20.2.3 AC requirements for SerDes reference clocks
This table lists AC requirements for the PCI Express, SGMII, Serial RapidIO and Aurora SerDes reference clocks to be
guaranteed by the customer’s application design.
Table 61. SD_REF_CLKn and SD_REF_CLKn input clock requirements (SV = 1.0 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
SD_REF_CLK/SD_REF_CLK frequency range
tCLK_REF
tCLK_TOL
—
100/125
—
—
MHz
ppm
1
SD_REF_CLK/SD_REF_CLK clock frequency
tolerance
–350
350
—
SD_REF_CLK/SD_REF_CLK reference clock duty
cycle
tCLK_DUTY
tCLK_DJ
40
—
—
50
—
—
60
42
86
%
ps
ps
4
—
2
SD_REF_CLK/SD_REF_CLK max deterministic
peak-peak jitter at 10-6 BER
SD_REF_CLK/SD_REF_CLK total reference clock
jitter at 10-6 BER (peak-to-peak jitter at refClk input)
tCLK_TJ
SD_REF_CLK/SD_REF_CLK rising/falling edge rate tCLKRR/ CLKFR
t
1
200
—
—
—
—
—
4
—
V/ns
mV
mV
%
3
4
Differential input high voltage
Differential input low voltage
VIH
VIL
–200
20
4
Rising edge rate (SD_REF_CLKn) to falling edge rate
(SD_REF_CLKn) matching
Rise-Fall
Matching
—
5, 6
Notes:
1. Caution: Only 100 and 125 have been tested. In-between values not work correctly with the rest of the system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 40.
4. Measurement taken from differential waveform
5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate
of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 41.
Rise Edge Rate
Fall Edge Rate
VIH = +200 mV
0.0 V
VIL = –200 mV
SD_REF_CLKn –
SD_REF_CLKn
Figure 40. Differential measurement points for rise and fall time
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
106
Freescale Semiconductor
Electrical characteristics
TFALL
TRISE
SDn_REF_CLK
VCROSS MEDIAN
SDn_REF_CLK
SDn_REF_CLK
VCROSS MEDIAN + 100 mV
VCROSS MEDIAN
VCROSS MEDIAN – 100 mV
SDn_REF_CLK
Figure 41. Single-ended measurement points for rise and fall time matching
2.20.2.4 Spread-spectrum clock
SD_REF_CLK1/SD_REF_CLK1 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate
is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended
modulation should be used.
SD_REF_CLK2/SD_REF_CLK2 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate
is allowed), assuming both ends have same reference clock and the industry protocol specifications supports it. For better
results, a source without significant unintended modulation should be used.
SD_REF_CLK3/SD_REF_CLK3 are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
SD_REF_CLK4/SD_REF_CLK4 are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
2.20.3 SerDes transmitter and receiver reference circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
SD_RXn
SD_TXn
50 Ω
50 Ω
50 Ω
50 Ω
Receiver
Transmitter
SD_TXn
SD_RXn
Figure 42. SerDes transmitter and receiver reference circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below based on the application
usage:
•
•
•
•
•
Section 2.20.4, “PCI Express”
Section 2.20.5, “XAUI”
Section 2.20.6, “Aurora”
Section 2.20.7, “Serial ATA (SATA)
Section 2.20.8, “SGMII interface”
Note that external AC-coupling capacitor is required for the above serial transmission protocols per the protocol’s standard
requirements.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
107
Electrical characteristics
2.20.4 PCI Express
This section describes the clocking dependencies, DC and AC electrical specifications for the PCI Express bus.
2.20.4.1 Clocking dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
2.20.4.2 PCI Express clocking requirements for SD_REF_CLKn and
SD_REF_CLKn
SerDes banks 1–2 (SD_REF_CLK[1:2] and SD_REF_CLK[1:2]) may be used for various SerDes PCI Express configurations
based on the RCW Configuration field SRDS_PRTCL. PCI Express is not supported on SerDes bank 3.
For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”
2.20.4.3 PCI Express DC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.20.4.3.1
PCI Express DC physical layer transmitter specifications
This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters
are specified at the component pins.
Table 62. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications
(XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min Typical Max Units
Notes
Differential peak-to-peak
output voltage
VTX-DIFFp-p
800
3.0
—
1200
4.0
mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1.
De-emphasized differential VTX-DE-RATIO
output voltage (ratio)
3.5
dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note 1.
DC differential transmitter ZTX-DIFF-DC
impedance
80
40
100
50
120
60
Ω
Transmitter DC differential mode low Impedance
Transmitter DC impedance ZTX-DC
Ω
Required transmitter D+ as well as D– DC
Impedance during all states
Note:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
108
Freescale Semiconductor
Electrical characteristics
This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all transmitters. The parameters
are specified at the component pins.
Table 63. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications
(XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
VTX-DIFFp-p
Min Typical Max Units
Notes
Differential peak-to-peak
output voltage
800
400
—
500
3.5
1200
1200
4.0
mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1.
mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1.
Low Power differential
peak-to-peak output voltage
VTX-DIFFp-p_low
De-emphasized differential VTX-DE-RATIO-3.5dB 3.0
output voltage (ratio)
dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note 1.
De-emphasized differential VTX-DE-RATIO-6.0dB 5.5
output voltage (ratio)
6.0
6.5
dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition. See
Note 1.
DC differential transmitter ZTX-DIFF-DC
impedance
80
40
100
50
120
60
Ω
Transmitter DC differential mode low
impedance
Transmitter DC Impedance ZTX-DC
Ω
Required transmitter D+ as well as D– DC
impedance during all states
Note:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2.20.4.4 PCI Express DC physical layer receiver specifications
This section discusses the PCI Express DC physical layer receiver specifications 2.5 GT/s, and 5 GT/s.
This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are
specified at the component pins.
Table 64. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min Typ Max Units
Notes
Differential input peak-to-peak voltage
VRX-DIFFp-p
120
—
1200 mV VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-|
See Note 1.
DC differential input impedance
DC input impedance
ZRX-DIFF-DC
80
100 120
Ω
Ω
Receiver DC differential mode
impedance.
See Note 2
ZRX-DC
40
50
60
Required receiver D+ as well as D–
DC Impedance (50 20%
tolerance).
See Notes 1 and 2.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
109
Electrical characteristics
Table 64. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (XV = 1.5 V or 1.8 V)
DD
(continued)
Parameter
Symbol
Min Typ Max Units
Notes
Powered down DC input impedance
ZRX-HIGH-IMP-DC
50 k
—
—
Ω
Required receiver D+ as well as D–
DC Impedance when the receiver
terminations do not have power.
See Note 3.
Electrical idle detect threshold
VRX-IDLE-DET-DIFFp-p 65
—
175 mV VRX-IDLE-DET-DIFFp-p
=
|
2 × |VRX-D+ – VRX-D–
Measured at the package pins of the
receiver
Notes:
1. Measured at the package pins with a test load of 50 Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the receiver ground.
This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are
specified at the component pins.
Table 65. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min Typ Max Units
Notes
Differential input peak-to-peak voltage
VRX-DIFFp-p
120
—
1200
V
Ω
Ω
VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–|
See Note 1.
DC differential input impedance
DC input impedance
ZRX-DIFF-DC
80
100 120
Receiver DC Differential mode
impedance. See Note 2
ZRX-DC
40
50
—
60
—
Required receiver D+ as well as D–
DC Impedance (50 20%
tolerance). See Notes 1 and 2.
Powered down DC input impedance
Electrical idle detect threshold
Notes:
ZRX-HIGH-IMP-DC
50
kΩ Required receiver D+ as well as D–
DC Impedance when the receiver
terminations do not have power.
See Note 3.
VRX-IDLE-DET-DIFFp-p 65
—
175 mV VRX-IDLE-DET-DIFFp-p
=
2 × |VRX-D+ – VRX-D–
|
Measured at the package pins of the
receiver
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the receiver ground.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
110
Freescale Semiconductor
Electrical characteristics
2.20.4.5 PCI Express AC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this device.
2.20.4.5.1
PCI Express AC physical layer transmitter specifications
This section discusses the PCI Express AC physical layer transmitter specifications 2.5 GT/s, and 5 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 66. PCI Express 2.0 (2.5 GT/s) differential transmitter Output AC specifications
For recommended operating conditions, see Table 3.
Parameter
Unit interval
Symbol
Min
Typ
Max Units
Notes
UI
399.88 400 400.12
ps Each UI is 400 ps 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Minimum transmitter eye
width
TTX-EYE
0.75
—
—
—
—
UI
UI
The maximum transmitter jitter can be derived
as TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.
Does not include spread spectrum or RefCLK
jitter. Includes device random jitter at 10-12
See Notes 2 and 3.
.
Maximum time between the TTX-EYE-MEDIAN-
jitter median and maximum
deviation from the median
0.125
Jitter is defined as the measurement variation
of the crossing points (VTX-DIFFp-p = 0 V) in
relation to a recovered transmitter UI. A
recovered transmitter UI is calculated over
3500 consecutive unit intervals of sample
data. Jitter is measured using all edges of the
250 consecutive UI in the center of the 3500 UI
used for calculating the transmitter UI.
See Notes 2 and 3.
to-
MAX-JITTER
AC coupling capacitor
CTX
75
—
200
nF All transmitters must be AC coupled. The AC
coupling is required either within the media or
within the transmitting component itself.
See Note 4.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250
consecutive transmitter UIs.
3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of
the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It should be noted that the median is not
the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is
approximately equal as opposed to the averaged time value.
4. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
111
Electrical characteristics
This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 67. PCI Express 2.0 (5 GT/s) differential transmitter Output AC specifications
For recommended operating conditions, see Table 3.
Parameter
Unit Interval
Symbol
Min
Typ
Max Units
Notes
UI
199.94 200.00 200.06
ps Each UI is 400 ps 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Minimum transmitter eye width
TTX-EYE
0.75
—
—
UI
The maximum transmitter jitter can be
derived as:
TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.
See Notes 2 and 3.
Transmitter RMS deterministic
jitter > 1.5 MHz
TTX-HF-DJ-DD
TTX-LF-RMS
CTX
—
—
75
—
3.0
—
0.15
—
ps
—
Transmitter RMS deterministic
jitter < 1.5 MHz
ps Reference input clock RMS jitter (< 1.5 MHz)
at pin < 1 ps
AC coupling capacitor
200
nF All transmitters must be AC coupled. The AC
coupling is required either within the media
or within the transmitting component itself.
See Note 4.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250
consecutive transmitter UIs.
3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of
the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It should be noted that the median is not
the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is
approximately equal as opposed to the averaged time value.
4. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
2.20.4.5.2
PCI Express AC physical layer receiver specifications
This section discusses the PCI Express AC physical layer receiver specifications 2.5 GT/s, and 5 GT/s.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
112
Freescale Semiconductor
Electrical characteristics
This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are
specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 68. PCI Express 2.0 (2.5 GT/s) differential receiver Input AC specifications
For recommended operating conditions, see Table 3.
Parameter
Unit Interval
Symbol
Min
Typ
Max Units
Notes
UI
399.88 400.00 400.12
ps Each UI is 400 ps 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Minimum receiver eye width
TRX-EYE
0.4
—
—
—
—
UI
UI
The maximum interconnect media and
transmitter jitter that can be tolerated by the
receiver can be derived as
TRX-MAX-JITTER = 1 – TRX-EYE= 0.6 UI.
See Notes 2 and 3.
Maximum time between the
jitter median and maximum
deviation from the median.
TRX-EYE-MEDIAN-
0.3
Jitter is defined as the measurement
variation of the crossing points
to-MAX-JITTER
(VRX-DIFFp-p = 0 V) in relation to a recovered
transmitter UI. A recovered transmitter UI is
calculated over 3500 consecutive unit
intervals of sample data. Jitter is measured
using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating
the transmitter UI.
See Notes 2, 3 and 4.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used
as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same
reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive transmitter UIs. It should be noted that the median is not the same as the mean. The jitter
median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the
averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter
UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
4. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit
algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
113
Electrical characteristics
This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers (RXs). The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.
Table 69. PCI Express 2.0 (5 GT/s) differential receiver Input AC specifications
For recommended operating conditions, see Table 3.
Parameter
Unit Interval
Symbol
Min
Typ
Max Units
Notes
UI
199.94 200.00 200.06 ps Each UI is 400 ps 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Max receiver inherent timing
error
TRX-TJ-CC
—
—
0.4
UI The maximum inherent total timing error for
common RefClk receiver architecture
Maximum time between the
jitter median and maximum
deviation from the median
TRX-TJ-DC
—
—
0.34
UI Max receiver inherent total timing error
Max receiver inherent
deterministic timing error
TRX-DJ-DD-CC
—
—
—
—
0.30
0.24
UI The maximum inherent deterministic timing
error for common RefClk receiver
architecture
Max receiver inherent
deterministic timing error
TRX-DJ-DD-DC
UI The maximum inherent deterministic timing
error for common RefClk receiver
architecture
Note:
1. No test load is necessarily associated with this value.
2.20.4.6 Test and measurement load
The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in Figure 43.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary. If the vendor does not explicitly
state where the measurement point is located, the measurement point is assumed to be the
D+ and D– package pins.
D+ package pin
C = CTX
Transmitter
silicon
+ package
C = CTX
D– package pin
R = 50 Ω
R = 50 Ω
Figure 43. Test/Measurement load
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
114
Freescale Semiconductor
Electrical characteristics
2.20.5 XAUI
This section describes the DC and AC electrical specifications for the XAUI bus.
2.20.5.1 XAUI DC electrical characteristics
This section discusses the XAUI DC electrical characteristics for the clocking signals, transmitter, and receiver.
2.20.5.1.1
DC requirements for XAUI SD_REF_CLKn and SD_REF_CLKn
Only SerDes banks 2–3 (SD_REF_CLK[2:3] and SD_REF_CLK[2:3]) may be used for various SerDes XAUI configurations
based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1.
For more information on these specifications, see Section 2.20.2.2, “DC-level requirement for SerDes reference clocks.”
2.20.5.1.2
XAUI transmitter DC electrical characteristics
This table defines the XAUI transmitter DC electrical characteristics.
Table 70. XAUI transmitter DC electrical characteristics (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Unit
Notes
Max
2.30
1600
Output voltage
VO
–0.40
800
—
—
V
1
Differential output voltage
VDIFFPP
mV p-p
—
Note:
1. Absolute output voltage limit
2.20.5.1.3
XAUI receiver DC electrical characteristics
This table defines the XAUI receiver DC electrical characteristics.
Table 71. XAUI receiver DC timing specifications (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Differential input voltage
VIN
200
900
1600
mV p-p
1
Note:
1. Measured at the receiver.
2.20.5.2 XAUI AC timing specifications
This section discusses the XAUI AC timing specifications for the clocking signals, transmitter, and receiver.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
115
Electrical characteristics
2.20.5.2.1
AC requirements for XAUI SD_REF_CLKn and SD_REF_CLKn
This table specifies AC requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [2:3]. Only SerDes banks 2–3 may
be used for various SerDes XAUI configurations based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported
on SerDes bank 1.
Table 72. XAUI AC SD_REF_CLKn and SD_REF_CLKn input clock requirements (SV = 1.0 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
SD_REF_CLK/SD_REF_CLK frequency range
tCLK_REF
—
125/
—
MHz
—
156.25
SD_REF_CLK/SD_REF_CLK clock frequency
tolerance
tCLK_TOL
tCLK_DUTY
tCLK_CJ
–100
40
—
50
—
—
100
60
ppm
%
—
2
SD_REF_CLK/SD_REF_CLK reference clock duty
cycle
SD_REF_CLK/SD_REF_CLK cycle to cycle jitter
(period jitter at refClk input)
—
100
50
ps
—
—
SD_REF_CLK/SD_REF_CLK total reference clock
jitter (peak-to-peak phase jitter at refClk input)
tCLK_PJ
-50
ps
SD_REF_CLK/SD_REF_CLK rising/falling edge rate tCLKRR/ CLKFR
t
1
200
—
—
—
—
—
4
—
V/ns
mV
mV
%
1
2
Differential input high voltage
Differential input low voltage
VIH
VIL
–200
20
2
Rising edge rate (SD_REF_CLKn) to falling edge rate
(SD_REF_CLKn) matching
Rise-Fall
Matching
—
3, 4
Notes:
1. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn – SD_REF_CLKn). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 40.
2. Measurement taken from differential waveform
3. Measurement taken from single-ended waveform
4. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate
of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 41.
2.20.5.2.2
XAUI transmitter AC timing specifications
This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not included.
Table 73. XAUI transmitter AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Deterministic jitter
Symbol
Min
Typical
Max
Unit
Notes
JD
JT
UI
—
—
—
—
0.17
0.35
UI p-p
UI p-p
ps
—
—
—
Total jitter
Unit Interval: 3.125 GBaud
320 – 100 ppm
320
320 + 100 ppm
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
116
Freescale Semiconductor
Electrical characteristics
2.20.5.2.3
XAUI receiver AC timing specifications
This table defines the receiver AC specifications for XAUI. RefClk jitter is not included.
Table 74. XAUI receiver AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Deterministic jitter tolerance
JD
0.37
0.55
—
—
—
—
UI p-p
UI p-p
1
1
Combined deterministic and random
jitter tolerance
JDR
Total jitter tolerance
Bit error rate
JT
BER
UI
0.65
—
—
—
—
UI p-p
—
1, 2
—
10–12
Unit Interval: 3.125 GBaud
320 – 100 ppm
320
320 + 100 ppm
ps
—
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
This figure shows the single-frequency sinusoidal jitter limits.
8.5 UI p-p
Sinusoidal
jitter
amplitude
0.10 UI p-p
22.1 kHz
Frequency
1.875 MHz
20 MHz
Figure 44. Single-Frequency Sinusoidal Jitter Limits
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
117
Electrical characteristics
2.20.6 Aurora
This section describes the Aurora clocking requirements and AC and DC electrical characteristics.
2.20.6.1 Aurora DC electrical characteristics
This section describes the DC electrical characteristics for Aurora.
2.20.6.1.1
Aurora DC clocking requirements for SD_REF_CLKn and SD_REF_CLKn
Only SerDes bank 1 (SD_REF_CLK1 and SD_REF_CLK1) may be used for SerDes Aurora configurations based on the RCW
Configuration field SRDS_PRTCL. Aurora is not supported on SerDes banks 2-3.
For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”
2.20.6.1.2
Aurora transmitter DC electrical characteristics
This table defines the Aurora transmitter DC electrical characteristics.
Table 75. Aurora transmitter DC electrical characteristics (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Differential output voltage
Symbol
Min
Typical
Unit
Max
VDIFFPP
800
—
1600
mV p-p
2.20.6.1.3
Aurora receiver DC electrical characteristics
This table defines the Aurora receiver DC electrical characteristics for Aurora.
Table 76. Aurora receiver DC electrical characteristics (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Differential input voltage
VIN
120
900
1200
mV p-p
1
Note:
1. Measured at receiver
2.20.6.2 Aurora AC timing specifications
This section describes the AC timing specifications for Aurora.
2.20.6.2.1
Aurora AC clocking requirements for SD_REF_CLKn and SD_REF_CLKn
Only SerDes bank 1 (SD_REF_CLK1 and SD_REF_CLK1) may be used for SerDes Aurora configurations based on the RCW
Configuration field SRDS_PRTCL. Aurora is not supported on SerDes banks 2–3.
Please note that the XAUI clock requirements for SD_REF_CLKn and SD_REF_CLKn are intended to be used within the
clocking guidelines specified by either Section 2.20.2.3, “AC requirements for SerDes reference clocks” or Section 2.20.7.2.1,
“AC requirements for SATA REF_CLK.”
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
118
Freescale Semiconductor
Electrical characteristics
2.20.6.2.2
Aurora transmitter AC timing specifications
This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not included.
Table 77. Aurora transmitter AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Deterministic jitter
Symbol
Min
Typical
Max
Unit
JD
JT
UI
UI
UI
—
—
—
0.17
UI p-p
UI p-p
ps
Total jitter
—
0.35
Unit Interval: 2.5 GBaud
Unit Interval: 3.125 GBaud
Unit Interval: 5.0 GBaud
400 – 100 ppm
320 – 100 ppm
200 – 100 ppm
400
320
200
400 + 100 ppm
320 + 100 ppm
200 + 100 ppm
ps
ps
2.20.6.2.3
Aurora receiver AC timing specifications
This table defines the Aurora receiver AC timing specifications. RefClk jitter is not included.
Table 78. Aurora receiver AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Deterministic jitter tolerance
JD
0.37
0.55
—
—
—
—
UI p-p
UI p-p
1
1
Combined deterministic and random
jitter tolerance
JDR
Total jitter tolerance
Bit error rate
JT
BER
UI
0.65
—
—
—
UI p-p
—
1,2
—
—
—
—
—
10–12
Unit Interval: 2.5 GBaud
Unit Interval: 3.125 GBaud
Unit Interval: 5.0 GBaud
400 – 100 ppm
320 – 100 ppm
200 – 100 ppm
400
320
200
400 + 100 ppm
320 + 100 ppm
200 + 100 ppm
ps
ps
ps
UI
UI
Note:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
2.20.7 Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) interface.
2.20.7.1 SATA DC electrical characteristics
This section describes the DC electrical characteristics for SATA.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
119
Electrical characteristics
2.20.7.1.1
SATA DC transmitter Output Characteristics
This table provides the DC differential transmitter output DC characteristics for the transmission.
Table 79. Gen1i/1.5G transmitter DC specifications (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Units
Notes
Transmitter differential output
voltage
VSATA_TXDIFF
400
—
600
mV p-p
1
Transmitter differential pair
impedance
ZSATA_TXDIFFIM
85
100
115
Ω
2
Notes:
1. Terminated by 50 Ω load
2. DC impedance
This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s
transmission.
Table 80. Gen 2i/3G transmitter DC specifications (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Units
Notes
Transmitter diff output voltage
VSATA_TXDIFF
400
85
—
700
115
mV p-p
1
Transmitter differential pair
impedance
ZSATA_TXDIFFIM
100
Ω
—
Note:
1. Terminated by 50 Ω load
2.20.7.1.2
SATA DC receiver Input Characteristics
This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface.
Table 81. Gen1i/1.5 G receiver Input DC specifications (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
Differential receiver input impedance
OOB signal detection threshold
Notes:
VSATA_RXDIFF
ZSATA_RXSEIM
VSATA_OOB
240
85
—
600
115
240
mV p-p
Ω
1
2
2
100
120
50
mV p-p
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
120
Freescale Semiconductor
Electrical characteristics
This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface.
Table 82. Gen2i/3 G receiver Input DC specifications (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
Differential receiver input impedance
OOB signal detection threshold
Notes:
VSATA_RXDIFF
ZSATA_RXSEIM
VSATA_OOB
275
85
—
750
115
240
mV p-p
Ω
1
2
2
100
120
75
mV p-p
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
2.20.7.2 SATA AC timing specifications
This section discusses the SATA AC timing specifications.
2.20.7.2.1
AC requirements for SATA REF_CLK
The AC requirements for the SATA reference clock are listed in this table to be guaranteed by the customer’s application design.
Table 83. SATA reference clock input requirements
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
SD_REF_CLK/SD_REF_CLK frequency range
tCLK_REF
—
100/125
—
MHz
1
SD_REF_CLK/SD_REF_CLK clock frequency tolerance
tCLK_TOL
–350
—
+350
ppm
—
SD_REF_CLK/SD_REF_CLK reference clock duty cycle
tCLK_DUTY
40
—
50
—
60
%
5
2
SD_REF_CLK/SD_REF_CLK cycle-to-cycle clock jitter (period jitter) tCLK_CJ
100
ps
SD_REF_CLK/SD_REF_CLK total reference clock jitter, phase jitter tCLK_PJ
(peak-peak)
–50
—
+50
ps
2, 3, 4
Notes:
1. Caution: Only 100, and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.
2. At RefClk input
3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12
4. Total peak-to-peak deterministic jitter should be less than or equal to 50 ps.
5. Measurement taken from differential waveform
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
121
Electrical characteristics
This figure shows the reference clock timing waveform.
TH
Ref_CLK
TL
Figure 45. Reference clock timing waveform
2.20.7.3 AC transmitter Output Characteristics
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.
Table 84. Gen1i/1.5 G transmitter AC specifications
For recommended operating conditions, see Table 3.
Parameter
Channel speed
Symbol
Min
Typ
Max
Units
Notes
tCH_SPEED
TUI
—
1.5
—
670.2333
0.355
0.47
Gbps
ps
—
—
1
Unit Interval
666.4333
666.6667
Total jitter data-data 5 UI
Total jitter, data-data 250 UI
Deterministic jitter, data-data 5 UI
Deterministic jitter, data-data 250 UI
Note:
USATA_TXTJ5UI
USATA_TXTJ250UI
USATA_TXDJ5UI
USATA_TXDJ250UI
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
1
0.175
0.22
1
1
1. Measured at transmitter output pins peak to peak phase variation, random data pattern
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.
Table 85. Gen 2i/3 G transmitter AC specifications
For recommended operating conditions, see Table 3.
Parameter
Channel speed
Symbol
Min
Typ
Max
Units
Notes
tCH_SPEED
TUI
—
333.2167
—
3.0
333.3333
—
—
335.1167
0.3
Gbps
ps
—
—
1
Unit Interval
Total jitter fC3dB = fBAUD ÷ 10
Total jitter fC3dB = fBAUD ÷ 500
Total jitter fC3dB = fBAUD ÷ 1667
USATA_TXTJfB/10
USATA_TXTJfB/500
USATA_TXTJfB/1667
UI p-p
UI p-p
UI p-p
—
—
0.37
1
—
—
0.55
1
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
122
Freescale Semiconductor
Electrical characteristics
Table 85. Gen 2i/3 G transmitter AC specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Deterministic jitter,
Symbol
Min
Typ
Max
Units
Notes
USATA_TXDJfB/10
—
—
0.17
UI p-p
1
fC3dB = fBAUD ÷ 10
Deterministic jitter,
USATA_TXDJfB/500
USATA_TXDJfB/1667
—
—
—
—
0.19
0.35
UI p-p
UI p-p
1
1
fC3dB = fBAUD ÷ 500
Deterministic jitter,
fC3dB = fBAUD ÷ 1667
Note:
1. Measured at transmitter output pins peak-to-peak phase variation, random data pattern
2.20.7.4 AC differential receiver Input characteristics
This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing
specifications do not include RefClk jitter.
Table 86. Gen 1i/1.5G receiver AC specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Units
Notes
Unit Interval
TUI
666.4333
666.6667
670.2333
0.43
ps
—
1
Total jitter data-data 5 UI
USATA_TXTJ5UI
USATA_TXTJ250UI
USATA_TXDJ5UI
USATA_TXDJ250UI
—
—
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
UI p-p
Total jitter, data-data 250 UI
0.60
1
Deterministic jitter, data-data 5 UI
Deterministic jitter, data-data 250 UI
0.25
1
0.35
1
Note:
1. Measured at receiver
This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission.
The AC timing specifications do not include RefClk jitter.
Table 87. Gen 2i/3G receiver AC specifications
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Units
Notes
Unit Interval
TUI
333.2167
333.3333
335.1167
0.46
ps
—
1
Total jitter fC3dB = fBAUD ÷ 10
Total jitter fC3dB = fBAUD ÷ 500
Total jitter fC3dB = fBAUD ÷ 1667
USATA_TXTJfB/10
USATA_TXTJfB/500
USATA_TXTJfB/1667
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
0.60
1
0.65
1
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
123
Electrical characteristics
Table 87. Gen 2i/3G receiver AC specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
USATA_TXDJfB/10
USATA_TXDJfB/500
Min
Typical
Max
Units
Notes
Deterministic jitter, fC3dB = fBAUD ÷ 10
Deterministic jitter, fC3dB = fBAUD ÷ 500
—
—
—
—
—
—
0.35
0.42
0.35
UI p-p
UI p-p
UI p-p
1
1
1
Deterministic jitter, fC3dB = fBAUD ÷ 1667 USATA_TXDJfB/1667
Note:
1. Measured at receiver
2.20.8 SGMII interface
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 46, where
is the external (on board) AC-coupled capacitor. Each output pin of the SerDes transmitter differential pair features 50-Ω
C
TX
output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XGND. The reference
circuit of the SerDes transmitter and receiver is shown in Figure 42.
2.20.8.0.1
SGMII clocking requirements for SD_REF_CLKn and SD_REF_CLKn
When operating in SGMII mode, the EC_GTX_CLK125 clock is not required for this port. Instead, a SerDes reference clock
is required on SD_REF_CLK[1:3] and SD_REF_CLK[1:3] pins. SerDes banks 1-3 may be used for SerDes SGMII
configurations based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”
2.20.8.1 SGMII DC electrical characteristics
This section discusses the electrical characteristics for the SGMII interface.
2.20.8.1.1
SGMII transmit DC timing specifications
This table describe the SGMII SerDes transmitter and receiver AC-coupled DC electrical characteristics for 1.25 GBaud.
Transmitter DC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) as shown in Figure 47.
Table 88. SGMII DC transmitter electrical characteristics (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Output high voltage
Symbol
VOH
Min
Typ
Max
Unit
Notes
—
—
1.5 x
mV
1
|VOD -max
|
Output low voltage
VOL
|VOD -min
|
/2
—
—
mV
1
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
124
Freescale Semiconductor
Electrical characteristics
Table 88. SGMII DC transmitter electrical characteristics (XV = 1.5 V or 1.8 V) (continued)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
|VOD
Min
Typ
Max
Unit
Notes
Output differential voltage2, 3, 4
(XVDD-Typ at 1.5 V and 1.8 V)
|
320
500.0
725.0
665.6
604.7
545.2
482.9
423.4
362.5
60
mV B(1-3)TECR(lane)0[AMP_RED]
=0b000000
293.8
266.9
240.6
213.1
186.9
160.0
40
459.0
417.0
376.0
333.0
292.0
250.0
50
B(1-3)TECR(lane)0[AMP_RED]
=0b000010
B(1-3)TECR(lane)0[AMP_RED]
=0b000101
B(1-3)TECR(lane)0[AMP_RED]
=0b001000
B(1-3)TECR(lane)0[AMP_RED]
=0b001100
B(1-3)TECR(lane)0[AMP_RED]
=0b001111
B(1-3)TECR(lane)0[AMP_RED]
=0b010011
Output impedance (single-ended)
RO
Ω
—
Notes:
1. This does not align to DC-coupled SGMII.
2. |VOD| = |VSD_TXn– VSD_TXn|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2*|VOD .
|
3. Example amplitude reduction setting for SGMII on SerDes bank 1 lane E: B1TECRE0[AMP_RED] = 0b000010 for an output
differential voltage of 459 mV typical.
4. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.5 V or 1.8 V, no common mode
offset variation. SerDes transmitter is terminated with 100-Ω differential load between SD_TXn and SD_TXn.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
125
Electrical characteristics
This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.
SD_TXn
SD_RXn
50 Ω
50 Ω
CTX
50 Ω
50 Ω
Receiver
Transmitter
CTX
SD_TXn
SD_RXn
SD_RXn
SGMII
SerDes interface
CTX
SD_TXn
SD_TXn
50 Ω
50 Ω
50 Ω
Receiver
Transmitter
50 Ω
CTX
SD_RXn
Figure 46. 4-wire, AC-coupled, SGMII serial link connection example
This figure shows the SGMII transmitter DC measurement circuit.
SGMII
SerDes interface
SD_TXn
SD_TXn
50 Ω
50
50
Ω
Transmitter
VOD
50 Ω
Ω
Figure 47. SGMII transmitter DC measurement circuit
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
126
Freescale Semiconductor
Electrical characteristics
This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125 GBaud.
Table 89. SGMII 2.5x transmitter DC electrical characteristics (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Unit
Notes
Max
2.30
1600
Output voltage
VO
–0.40
800
—
—
V
1
Differential output voltage
VDIFFPP
mV p-p
—
Note:
1. Absolute output voltage limit
2.20.8.1.2
SGMII DC receiver electrical characteristics
This table lists the SGMII DC receiver electrical characteristics for 1.25 GBaud. Source synchronous clocking is not supported.
Clock is recovered from the data.
Table 90. SGMII DC receiver electrical characteristics (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Unit Notes
DC Input voltage range
Input differential voltage
—
N/A
—
—
1
REIDL_CTL = 001xx
REIDL_CTL = 100xx
REIDL_CTL = 001xx
REIDL_CTL = 100xx
VRX_DIFFp-p
100
175
30
1200
mV
2, 4
—
Loss of signal threshold
VLOS
—
100
175
120
mV
3, 4
—
65
—
Receiver differential input impedance
ZRX_DIFF
80
—
Ω
Notes:
1. Input must be externally AC coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See
Section 2.20.4.4, “PCI Express DC physical layer receiver specifications,” and Section 2.20.4.5.2, “PCI Express AC physical
layer receiver specifications,” for further explanation.
4. The REIDL_CTL shown in the table refers to the chip’s SerDes control register B(1-3)GCR(lane)1[REIDL_CTL] bit field.
This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.
Table 91. SGMII 2.5x receiver DC timing specifications (XV = 1.5 V or 1.8 V)
DD
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Differential input voltage
VIN
200
900
1600
mV p-p
1
Note:
1. Measured at the receiver.
2.20.8.2 SGMII AC timing specifications
This section discusses the AC timing specifications for the SGMII interface.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
127
Electrical characteristics
2.20.8.2.1
SGMII transmit AC timing specifications
This table provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing
specifications do not include RefClk jitter.
Table 92. SGMII transmit AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Deterministic jitter
Symbol
Min
Typ
Max
Unit
Notes
JD
JT
—
—
—
—
0.17
0.35
UI p-p
UI p-p
ps
—
1
Total jitter
Unit Interval: 1.25 GBaud
Unit Interval: 3.125 GBaud
AC coupling capacitor
Notes:
UI
800 – 100 ppm
320 – 100 ppm
10
800
320
—
800 + 100 ppm
320 + 100 ppm
200
—
—
2
UI
ps
CTX
nF
1. See Figure 44 for single frequency sinusoidal jitter measurements.
2. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.
2.20.8.2.2
SGMII AC measurement details
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) or at the receiver
inputs (SD_RXn and SD_RXn) respectively, as depicted in this figure.
D+ package pin
C = CTX
Transmitter
silicon
+ package
C = CTX
D– package pin
R = 50 Ω
R = 50 Ω
Figure 48. SGMII AC test/measurement load
2.20.8.2.3
SGMII receiver AC timing specification
This table provides the SGMII receiver AC timing specifications. The AC timing specifications do not include RefClk jitter.
Source synchronous clocking is not supported. Clock is recovered from the data.
Table 93. SGMII receive AC timing specifications
For recommended operating conditions, see Table 3.
Parameter
Deterministic jitter tolerance
Symbol
Min
Typ
Max
Unit
Notes
JD
JDR
JT
0.37
0.55
0.65
—
—
—
—
—
—
UI p-p
UI p-p
UI p-p
1, 2
1, 2
Combined deterministic and random jitter tolerance
Total jitter tolerance
1,2, 3
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
128
Freescale Semiconductor
Hardware design considerations
Table 93. SGMII receive AC timing specifications (continued)
For recommended operating conditions, see Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Bit error ratio
BER
UI
—
—
10-12
—
ps
ps
—
1
Unit Interval: 1.25 GBaud
Unit Interval: 3.125 GBaud
800 – 100 ppm
320 – 100 ppm
800
320
800 + 100 ppm
320 + 100 ppm
UI
1
Notes:
1. Measured at receiver
2. See the RapidIOTM 1×/4× LP Serial Physical Layer Specification for interpretation of jitter specifications.
3. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 44.
3
Hardware design considerations
3.1
System clocking
This section describes the PLL configuration of the chip.
This device includes nine PLLs, as follows:
•
There are two selectable core cluster PLLs which generate a core clock from the externally supplied SYSCLK input.
Core complex 0–1 can select from either CC1 PLL or CC2 PLL. The frequency ratio between the core cluster PLLs
and SYSCLK is selected using the configuration bits as described in Section 3.1.3, “e5500-64 core complex/ FMan to
SYSCLK PLL ratio.” The frequency for each core complex 0–1 is selected using the configuration bits as described
in Table 97.
•
•
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 3.1.2, “Platform to SYSCLK PLL ratio.”
The DDR block PLL generates the DDR clock from the externally supplied SYSCLK input (asynchronous mode) or
from the platform clock (synchronous mode). The frequency ratio is selected using the Memory Controller Complex
PLL multiplier/ratio configuration bits as described in Section 3.1.5, “DDR controller PLL ratios.”
•
•
The FMan PLL generates the FMan clock from the platform PLL when operating synchronously, or from CC3 PLL
when operating asynchronously. Described in Section 3.1.8, “Frame Manager (FMan) clock select.”
Each of the four SerDes blocks has a PLL which generate a core clock from their respective externally supplied
SD_REF_CLKn/SD_REF_CLKn inputs. The frequency ratio is selected using the SerDes PLL ratio configuration bits
as described in Section 3.1.6, “Frequency options.”
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
129
Hardware design considerations
3.1.1
Clock ranges
This table provides the clocking specifications for the processor core, platform, memory, and local bus.
Table 94. Processor clocking specifications
Maximum Processor Core Frequency
Characteristic
1800 MHz
2000 MHz
2200 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Core PLL frequency
1000
667
600
400
—
1800
1800
600
600
75
1000
667
600
400
—
2000
2000
700
1000
667
600
400
—
2200
2200
800
MHz
MHz
MHz
MHz
MHz
MHz
1,4
Core frequency
4
Platform clock frequency
Memory bus clock frequency
Local bus clock frequency
FMan frequency
1
667
800
1,2,5,6
87.5
600
100
3
7
300
450
300
300
600
Notes:
1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting
SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The memory bus clock speed is half the DDR3/DDR3L data rate. DDR3/DDR3L memory bus clock frequency is limited to min
= 400 MHz.
3. The local bus clock speed on LCLK[0:1] is determined by the platform clock divided by the local bus ratio programmed in
LCRR[CLKDIV]. See the applicable chip reference manual for more information.
4.The core can run at core complex PLL/1 or PLL/2. With a core complex PLL frequency of 1333 MHz, this results in the minimum
allowable core frequency of 667MHz for PLL/2.
5. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
the same as the platform frequency. If the desired DDR data rate is higher than the platform frequency, asynchronous mode
must be used.
6. In asynchronous mode, the memory bus clock speed is dictated by its own PLL.
7. The minimum frequencies for the FMan to support the specified interfaces are: 300 MHz for a 1G interface, 450 MHz for a
10 G interface, 500 MHz for a 10 G interface with PCD and 600 MHz for a 10 G and two 1 G interfaces. The FMAN PLL
frequency range is the same as the Core PLL frequency range.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
130
Freescale Semiconductor
Hardware design considerations
3.1.2
Platform to SYSCLK PLL ratio
The allowed platform clock to SYSCLK ratios are shown in this table.
Note that in synchronous DDR mode, the DDR data rate is the determining factor for selecting the platform bus frequency
because the platform frequency must equal the DDR data rate.
In asynchronous DDR mode, the memory bus clock frequency is decoupled from the platform bus frequency.
Table 95. Platform to SYSCLK PLL ratios
Binary value of
Platform:SYSCLK ratio
SYS_PLL_RAT
0_0101
0_0110
0_0111
0_1000
All Others
5:1
6:1
7:1
8:1
Reserved
3.1.3
e5500-64 core complex/ FMan to SYSCLK PLL ratio
The clock ratio between SYSCLK and each of the two core complex PLLs and FMan PLL is determined at power up by the
binary value of the RCW field CCn_PLL_RAT. (Note: n=1 or 2 are the core complex PLLs, n=3 is the FMan PLL). This table
describes the supported ratios. Note that a core complex/ FMan PLL setting targeting 1 GHz and above must set RCW field
CCn_PLL_CFG = 0b10, for setting targeting below 1 GHz CCn_PLL_CFG=0b00.
This table lists the supported core complex/ FMan to SYSCLK ratios.
Table 96. Core complex/ FMan PLL to SYSCLK ratios
Binary value of
Core cluster:SYSCLK ratio
CCn_PLL_RAT
0_1000
0_1001
0_1010
0_1011
0_1100
0_1110
0_1111
1_0000
1_0001
1_0010
1_0100
1_0110
All Others
8:1
9:1
10:1
11:1
12:1
14:1
15:1
16:1
17:1
18:1
20:1
22:1
Reserved
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
131
Hardware design considerations
3.1.4
Core complex PLL select
The clock frequency of each of the core 0–1 complex is determined by the binary value of the RCW field Cn_PLL_SEL. This
table describes the supported ratios for each core complex 0-1, where each individual core complex can select a frequency from
the table.
Table 97. Core complex [0,1] PLL select
Binary value of Cn_PLL_SEL
Core cluster ratio
0000
0001
CC1 PLL /1
CC1 PLL /2
CC2 PLL /1
CC2 PLL/2
Reserved
0100
0101
All Others
Note: If CC2 PLL is used by core0 or core1, then CC2 PLL must be operated
at a lower frequency than the CC1 PLL, and its maximum allowed
frequency is 80% of the maximum rated frequency of the core at nominal
voltage.
3.1.5
DDR controller PLL ratios
The dual DDR memory controller complexes can be synchronous with or asynchronous to the platform, depending on
configuration. Both DDR controllers operate at the same frequency configuration.
Table 98 describes the clock ratio between the DDR memory controller PLLs and the externally supplied SYSCLK input
(asynchronous mode) or from the platform clock (synchronous mode).
In asynchronous DDR mode, the DDR data rate to SYSCLK ratios supported are listed in Table 98. This ratio is determined by
the binary value of the RCW Configuration field MEM_PLL_RAT[10:14]. The corresponding setting for
MEM_PLL_CFG[0:1] is listed in Table 99.
NOTE
The RCW Configuration field DDR_SYNC (bit 184) must be set to b’0 for asynchronous
mode, and b’1 for synchronous mode.
The RCW Configuration field DDR_RATE (bit 232) must be set to b’0 for asynchronous
mode, and b’1 for synchronous mode.
The RCW Configuration field DDR_RSV0 (bit 234) must be set to b’0 for all ratios.
Table 98. Asynchronous DDR clock ratio
Binary value of MEM_PLL_RAT[10:14]
DDR:SYSCLK ratio
0_0101
0_0110
0_1000
0_1001
0_1010
5:1
6:1
8:1
9:1
10:1
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
132
Freescale Semiconductor
Hardware design considerations
Table 98. Asynchronous DDR clock ratio (continued)
Binary value of MEM_PLL_RAT[10:14]
DDR:SYSCLK ratio
0_1100
0_1101
1_0000
1_0010
1_0011
1_0100
1_1000
All Others
12:1
13:1
16:1
18:1
19:1
20:1
24:1
Reserved
Note:
1. RCW[MEM_PLL_CFG] is set dependant on the DDR clock ratio used. See Table 99 for
valid setttings of DDR clock ratio and MEM_PLL_CFG.
Table 99. Supported DDR ratios and RCW MEM_PLL_CFG settings
SYSCLK (MHz)
MEM:SYSCLK
100
125
133.3
150
Ratio
DDR Rate (MT/s)/MEM_PLL_CFG
Platform Clock/01
1 (Sync Mode)
6
8
Reserved
800/11
900/113
1200/01
1350/01
1500/01
Reserved
800/101
900/102
1000/01
1200/11
1300/11
1600/11
1000/011
1125/012
1250/01
1500/11
1067/01
1200/01
1333/01
1600/11
Reserved
Reserved
9
10
12
13
16
Notes:
1. For MEM SYSYCLK RATIO = 8, MEM_PLL_CFG changes from 10 to 01 when SYSCLK is
greater than or equal to 120.9MHz
2. For MEM SYSYCLK RATIO = 9, MEM_PLL_CFG changes from 10 to 01 when SYSCLK is
greater than or equal to 107.4MHz
3. Maximum SYSCLK is 161.2MHz when MEM:SYSCLK ratio = 6
In synchronous mode, the DDR data rate to platform clock ratios supported are listed in this table. This ratio is determined by
the binary value of the RCW Configuration field MEM_PLL_RAT[10:14].
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
133
Hardware design considerations
Table 100. Synchronous DDR clock ratio
Binary Value of
MEM_PLL_RAT[10:14]
Set MEM_PLL_CFG=01
DDR:Platform CLK ratio
for platform CLK freq1
0_0001
1:1
>600 MHz
—
All Others
Reserved
Note:
1. Set RCW field MEM_PLL_CFG=0b01
3.1.6
Frequency options
This section discusses interface frequency options.
3.1.6.1
SYSCLK and platform frequency options
This table shows the expected frequency options for SYSCLK and platform frequencies.
Table 101. SYSCLK and platform frequency options
SYSCLK (MHz)
Platform:
SYSCLK
ratio
100
125
133.3
150
Platform frequency (MHz)1
5:1
6:1
7:1
8:1
625
750
666
800
750
600
700
800
1
Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy
removed)
3.1.6.2
Minimum platform frequency requirements for high-speed interfaces
The platform clock frequency must be considered for proper operation of high-speed interfaces as described below.
For proper PCI Express operation, the platform clock frequency must be greater than or equal to the values shown in these
figures.
527 MHz × (PCI Express link width)
--------------------------------------------------------------------------------
16
Figure 49. Gen 1 PEX minimum platform frequency
527 MHz × (PCI Express link width)
--------------------------------------------------------------------------------
8
Figure 50. Gen 2 PEX minimum platform frequency
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
134
Freescale Semiconductor
Hardware design considerations
Note that “PCI Express link width” in the above equation refers to the negotiated link width as the result of PCI Express link
training, which may or may not be the same as the link width POR selection.
3.1.7
SerDes PLL ratio
The clock ratio between each of the four SerDes PLLs and their respective externally supplied
SD_REF_CLKn/SD_REF_CLKn inputs is determined by the binary value of the RCW Configuration field SRDS_RATIO_Bn
as shown in this table. Furthermore, each SerDes lane grouping can be run at a SerDes PLL frequency divider determined by
the binary value of the RCW field SRDS_DIV_Bn as shown in Table 103 and Table 104.
This table lists the supported SerDes PLL Bank n to SD_REF_CLKn ratios.
Table 102. SerDes PLL bank n to SD_REF_CLKn ratios
SRDS_PLL_n:SD_REF_CLKn ratio
Binary value of
SRDS_RATIO_Bn
n = 1 (bank 1) n = 2 (bank 2) n = 3 (bank 3) n = 4(bank 4)
001
010
Reserved
25:1
20:1
25:1
20:1
25:1
Reserved
Reserved
Reserved
Reserved
24:1
011
40:1
40:1
40:1
100
50:1
50:1
50:1
101
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
24:1
110
30:1
30:1
All Others
Reserved
Reserved
This table shows the PLL divider support for each pair of lanes on SerDes Bank 1.
Table 103. SerDes bank 1 PLL dividers
Binary value of SRDS_DIV_B1[0:4] SerDes bank 1 PLL divider
0b0
0b1
Divide by 1 off Bank 1 PLL
Divide by 2 off Bank 1 PLL
Note:
1. 1 bit (of 5 total SRDS_DIV_B1 bits) controls each pair of lanes,
where the first bit controls configuration of lanes A/B (or 0/1) and
the last bit controls configuration of lanes I/J (or 8/9).
This table shows the PLL dividers supported for each 4 lane group for SerDes Banks 2, 3, and 4.
Table 104. SerDes banks 2, 3, and 4 PLL dividers
Binary value of SRDS_DIV_Bn SerDes Bank n PLL divider
0b0
0b1
Divide by 1 off Bank n PLL
Divide by 2 off Bank n PLL
Notes:
1. One bit controls all 4 lanes of each bank.
2. n = 2 or 3 (SerDes bank 2 or bank 3)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
135
Hardware design considerations
3.1.8
Frame Manager (FMan) clock select
The Frame Managers (FM) can each be synchronous with or asynchronous to the platform, depending on configuration.
This table describes the clocking options that may be applied to each FM. The clock selection is determined by the binary value
of the RCW Clocking Configuration fields FM1_CLK_SEL and FM2_CLK_SEL.
Table 105. Frame Manager (FMan) clock select
Binary value of FMn_CLK_SEL
FM frequency
0b0
0b1
Platform Clock Frequency /2
FMan PLL Frequency /2 1,2
Notes:
1. For asynchronous mode, max frequency see Table 94.
2. For PLL settings, see Table 96.
3.2
Supply power default setting
This chip is capable of supporting multiple power supply levels on its I/O supplies. The I/O voltage select inputs, shown in the
following table, properly configure the receivers and drivers of the I/Os associated with the BVDD, CVDD, and LVDD power
planes, respectively.
WARNING
Incorrect voltage select settings can lead to irreversible device damage.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
136
Freescale Semiconductor
Hardware design considerations
Table 106. I/O voltage selection
VDD voltage selection
Value
Signals
(binary)
BVDD
CVDD
LVDD
IO_VSEL[0:4]
Default (0_0000)
0_0000
0_0001
0_0011
0_0100
0_0110
0_0111
0_1001
0_1010
0_1100
0_1101
0_1111
1_0000
1_0010
1_0011
1_0101
1_0110
1_1000
1_1001
1_1011
1_1100
1_1101
1_1110
1_1111
All Others
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
2.5 V
2.5 V
1.8 V
1.8 V
3.3 V
3.3 V
2.5 V
2.5 V
1.8 V
1.8 V
3.3 V
3.3 V
2.5 V
2.5 V
1.8 V
1.8 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Reserved
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3
Power supply design
3.3.1
PLL power supply filtering
Each of the PLLs described in Section 3.1, “System clocking,” is provided with power through independent power supply pins
(AV , AV , AV , AV , and AV ). AV , AV AV , and AV
DD_PLAT
DD_CCn
DD_DDR
DD_FM
DD_SRDSn
DD_PLAT
DD_CCn,
DD_FM
DD_DDR
voltages must be derived directly from the V
source through a low frequency filter scheme. AV
voltages must
DD_PL
DD_SRDSn
be derived directly from the SV source through a low frequency filter scheme.
DD
The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in
Figure 51, one for each of the AV pins. By providing independent filters to each PLL the opportunity to cause noise injection
DD
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
137
Hardware design considerations
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize noise coupled from
DD
nearby circuits. It should be possible to route directly from the capacitors to the AV pin, which is on the periphery of the
DD
footprint, without the inductance of vias.
Figure 51 shows the PLL power supply filter circuit.
Where:
R = 5 Ω ± 5%
C1 = 10μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH
C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH
NOTE
A higher capacitance value for C2 may be used to improve the filter as long as the other C2
parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH).
Voltage for AV is defined at the PLL supply filter and not the pin of AV
.
DD
DD
R
VDD_PL
AVDD_PLAT, AVDD_CCn, AVDD_DDR
AVDD_FM
C1
C2
Low ESL Surface Mount Capacitors
GND
Figure 51. PLL power supply filter circuit
The AV
signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,
DD_SRDSn
the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 52. For maximum
effectiveness, the filter circuit is placed as closely as possible to the AV balls to ensure it filters out as much noise as
DD_SRDSn
possible. The ground connection should be near the AV
balls. The 0.003-µF capacitor is closest to the balls, followed
DD_SRDSn
by two 2.2-µF capacitors, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from AV
DD_SRDSn
to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept
short, wide, and direct.
1.0 Ω
SVDD
AVDD_SRDSn
2.2 µF1
2.2 µF1
0.003 µF
GND
Figure 52. SerDes PLL power supply filter circuit
Note the following:
•
•
•
•
AV
should be a filtered version of SV
.
DD
DD_SRDSn
Signals on the SerDes interface are fed from the XV power plane.
DD
Voltage for AV
is defined at the PLL supply filter and not the pin of AV
.
DD_SRDSn
DD_SRDSn
An 0805 sized capacitor is recommended for system initial bring-up.
3.3.2
XVDD power supply filtering
XV may be supplied by a linear regulator or sourced by a filtered 1.5 V or 1.8 V voltage source. Systems may design in both
DD
options to allow flexibility to address system noise dependencies.
An example solution for XV filtering, where 1.5 V or 1.8 V is sourced from voltage source (for example, GV at 1.5 V
DD
DD
when using DDR3, or CV at 1.8 V), is illustrated in Figure 53. The component values in this example filter is system
DD
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
138
Freescale Semiconductor
Hardware design considerations
dependent and are still under characterization, component values may need adjustment based on the system or environment
noise.
Where:
C1 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
C2 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
F1 = 120 Ω at 100-MHz 2A 25% 0603 Ferrite
F2 = 120 Ω at 100-MHz 2A 25% 0603 Ferrite
Bulk and decoupling capacitors are added, as needed, per power supply design.
Bulk and
Decoupling
Capacitors
F1
F2
XVDD
1.5 V or 1.8V source
C1
C2
GND
Figure 53. XV power supply filter circuit
DD
3.3.3
USB_VDD_1P0 power supply filtering
USB_V _1P0 should be sourced by a filtered V
using a star connection. An example solution for USB_V _1P0
DD
DD_PL
DD
filtering, where USB_V _1P0 is sourced from V
, is illustrated in Figure 54. The component values in this example filter
DD
DD_PL
is system dependent and are still under characterization, component values may need adjustment based on the system or
environment noise.
Where:
C1 = 2.2 μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)
F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
Bulk and decoupling capacitors are added, as needed, per power supply design.
Bulk and
Decoupling
Capacitors
F1
VDD_PL
USB_VDD_1P0
C1
C1
GND
Figure 54. USB_V _1P0 power supply filter circuit
DD
3.4
Decoupling recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the chip’s system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each V , BV , OV , CV , GV , and
DD
DD
DD
DD
DD
LV pin of the chip. These decoupling capacitors should receive their power from separate V , BV , OV , CV ,
DD
DD
DD
DD
DD
GV , LV , and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed
DD
DD
directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 μF. Only ceramic SMT (surface mount technology) capacitors should be
used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V , BV
,
DD
DD
OV , CV , GV , and LV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
DD
DD
DD
DD
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
139
Hardware design considerations
have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected
to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
3.5
SerDes block power supply decoupling recommendations
The SerDes block requires a clean, tightly regulated source of power (SV and XV ) to ensure low jitter on transmit and
DD
DD
reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be
done with multiple vias to further reduce inductance.
•
First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
chip as close to the supply and ground connections as possible.
•
•
Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes
supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip
capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
3.6
Connection recommendations
To ensure reliable operation, it is recommended the user consider the following:
•
Connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to V
BV
,
DD
DD,
CV , OV , GV , and LV as required. All unused active high inputs should be connected to GND. All NC (no
DD
DD
DD
DD
connect) signals must remain unconnected. Power and ground connections must be made to all external V , BV
,
DD
DD
CV , OV , GV , LV and GND pins of the chip.
DD
DD
DD
DD,
•
The Ethernet controllers 1 and/or 2 input pins may be disabled by setting their respective RCW Configuration field
EC1 (bits 360–361), and EC2 (bits 363–364), to 0b11 = No parallel mode Ethernet. When disabled, these inputs do
not need to be externally pulled to an appropriate signal level.
•
•
•
ECn_GTX_CLK125 is a 125-MHz input clock on the dTSEC ports. If the dTSEC ports are not used for RGMII, the
ECn_GTX_CLK125 input can be tied off to GND.
If RCW field DMA1=0b1 (RCW bit 384), the DMA1 external interface is not enabled and this pin should be left as a
no connect.
If RCW field I2C = 0b100 or 0b101 (RCW bits 355–357), the SDHC_WP and SDHC_CD input signals are enabled
for external use. If SDHC_WP and SDHC_CD are selected and not used, they must be externally pulled low such that
SDHC_WP = 0 (write enabled) and SDHC_CD = 0 (card detected). If RCW field I2C != 0b100 or 0b101, thereby
selecting either I2C3 or GPIO functionality, SDHC_WP and SDHC_CD are internally driven such that SDHC_WP =
write enabled and SDHC_CD = card detected and the selected I2C3 or GPIO external pin functionality may be used.
•
•
.For P5021 (SVR = 0x8205_00XX) or P5021E (SVR = 0x820D_00XX), TEST_SEL must be connected to GND.
The TMP_DETECT pin is an active low input to the Security Monitor (see Chapter “Secure Boot and Trust
Architecture” in the applicable chip reference manual). When using Trust Architecture functionality, external logic
must ramp TMP_DETECT with OV . If not using Trust Architecture functionality, TMP_DETECT must be tied to
DD
OV to prevent the input from going low.
DD
3.6.1
Legacy JTAG configuration signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 56.
Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating conditions as most
have asynchronous behavior and spurious assertion gives unpredictable results.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
140
Freescale Semiconductor
Hardware design considerations
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std 1149.1
specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST to be
asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal device operation.
While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST
during the power-on reset flow. Simply tying TRST to PORESET is not practical because the JTAG interface is also used for
accessing the common on-chip processor (COP), which implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging
software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG
port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert
PORESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage
monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into
these signals with logic.
The arrangement shown in Figure 56 allows the COP port to independently assert PORESET or TRST, while ensuring that the
target can drive PORESET as well.
The COP interface has a standard header, shown in Figure 55, for connection to the target system, and is based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a
connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and
other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; so emulator vendors have issued many different pin numbering
schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom.
Still others number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal
placement recommended in Figure 55 is common to all known emulators.
3.6.1.1
Termination of unused signals
If the JTAG interface and COP header is not used, Freescale recommends the following connections:
•
TRST should be tied to PORESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal
(PORESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale
recommends that the COP header be designed into the system as shown in Figure 56. If this is not possible, the
isolation resistor allows future access to TRST in case a JTAG interface may need to be wired onto the system in future
debug situations.
•
No pull-up/pull-down is required for TDI, TMS, or TDO.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
141
Hardware design considerations
2
4
1
3
COP_TDO
COP_TDI
NC
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
5
7
6
8
COP_TCK
COP_TMS
COP_SRESET
9
10
12
NC
NC
11
KEY
13
15
COP_HRESET
No pin
GND
COP_CHKSTP_OUT
16
Figure 55. Legacy COP connector physical pinout
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
142
Freescale Semiconductor
Hardware design considerations
OVDD
10 kΩ
10 kΩ
HRESET6
HRESET
From Target
Board Sources
(if any)
PORESET
PORESET1
COP_HRESET
13
11
10 kΩ
10 kΩ
10 kΩ
10 kΩ
COP_SRESET
B
A
5
TRST1
COP_TRST
4
2
4
1
3
COP_VDD_SENSE2
NC
10 Ω
6
5
5
6
COP_CHKSTP_OUT
7
8
15
CKSTP_OUT
9
10
12
14 3
10 kΩ
10 kΩ
11
KEY
13
15
COP_CHKSTP_IN
COP_TMS
No pin
System logic
8
9
1
3
16
TMS
TDO
TDI
COP_TDO
COP_TDI
COP_TCK
COP Connector
Physical Pinout
7
2
TCK
NC
NC
10
4
12
16
Chip
Notes:
1. The COP port and target board should be able to independently assert PORESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved
signal integrity.
5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
to position B.
6. Asserting HRESET causes a hard reset on the device.
Figure 56. Legacy JTAG interface connection
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
143
Hardware design considerations
3.6.2
Aurora configuration signals
Correct operation of the Aurora interface requires configuration of a group of system control pins as demonstrated in Figure 57
and Figure 58. Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating
conditions as most have asynchronous behavior and spurious assertion gives unpredictable results.
Freescale recommends that the Aurora 22 pin duplex connector be designed into the system as shown in Figure 59 or the 70 pin
duplex connector be designed into the system as shown in Figure 60.
If the Aurora interface is not used, Freescale recommends the legacy COP header be designed into the system as described in
Section 3.6.1.1, “Termination of unused signals.”
2
4
1
3
TX0+
TX0-
VIO (VSense)
TCK
TMS
GND
TX1+
TX1-
GND
5
7
6
8
TDI
9
10
12
TDO
TRST
11
14
16
18
20
22
Vendor I/O 0
Vendor I/O 1
13
15
17
19
21
RX0+
RX0-
GND
Vendor I/O 2
Vendor I/O 3
RESET
RX1+
RX1-
Figure 57. Aurora 22 pin connector duplex pinout
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
144
Freescale Semiconductor
Hardware design considerations
2
4
6
1
3
5
TX0+
TX0-
GND
TX1+
TX1-
GND
VIO (VSense)
TCK
TMS
TDI
7
9
8
10
12
14
TDO
TRST
11
13
Vendor I/O 0
Vendor I/O 1
RX0+
RX0-
15
17
19
21
23
25
27
16
18
20
GND
RX1+
RX1-
GND
TX2+
TX2-
GND
TX3+
TX3-
Vendor I/O 2
Vendor I/O 3
RESET
22
24
26
28
GND
CLK+
CLK-
GND
29
31
33
35
37
39
41
43
30
32
34
36
38
40
42
44
46
48
50
Vendor I/O 4
Vendor I/O 5
GND
GND
N/C
RX2+
RX2-
N/C
GND
N/C
GND
RX3+
45
47
49
RX3-
GND
TX4+
TX4-
GND
TX5+
N/C
GND
N/C
N/C
51
53
55
57
59
61
63
65
67
69
52
54
56
58
GND
N/C
N/C
TX5-
GND
GND
60
62
64
66
68
70
TX6+
N/C
N/C
GND
TX6-
GND
N/C
N/C
TX7+
TX7-
Figure 58. Aurora 70 pin connector duplex pinout
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
145
Hardware design considerations
OVDD
HRESET4
PORESET1
10 kΩ
10 kΩ
From Target
HRESET
PORESET
Board Sources
(if any)
RESET
22
10 kΩ
10 kΩ
10 kΩ
10 kΩ
B
A
3
1
3
5
7
9
2
4
TRST1
TRST
12
2
6
VIO VSense2
COP_TMS
1 kΩ
8
10
6
10
8
TMS
TDO
TDI
11
13
15
17
19
21
12
14
16
18
20
22
COP_TDO
COP_TDI
COP_TCK
4
TCK
Vendor I/O 3 N/C
20
18
Vendor I/O 2 (Aurora Event Out)
Vendor I/O 1 (Aurora Event In)
Vendor I/O 0 (Aurora HALT)
EVT[4]
EVT[1]
EVT[0]
16
14
Duplex 22 Connector
Physical Pinout
TX0_P
TX0_N
TX1_P
TX1_N
RX0_P
RX0_N
RX1_P
RX1_N
SD_TX09_P
SD_TX09_N
SD_TX08_P
SD_TX08_N
SD_RX09_P
SD_RX09_N
SD_RX08_P
SD_RX08_N
1
3
7
9
13
15
19
21
5
11
17
Chip
Notes:
1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
to position B.
4. Asserting HRESET causes a hard reset on the device. HRESET is not used by the Aurora 22 pin connector.
Figure 59. Aurora 22 pin connector duplex interface connection
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
146
Freescale Semiconductor
Hardware design considerations
OVDD
10 kΩ
10 kΩ
HRESET
HRESET4
From Target
Board Sources
(if any)
PORESET
PORESET1
1
3
2
4
6
8
RESET
5
22
7
10 kΩ
10 kΩ
10 kΩ
10 kΩ
25,26,27,28,
31,33,37,38,
39,40,43,44,
45,46,49,50,
51,52,55,56,
57,58,61,62,
63,64,67,68,
69,70
9
10
12
14
11
13
B
A
N/C
3
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
16
18
20
TRST1
TRST
22
24
26
28
12
VIO VSense2
COP_TMS
1 kΩ
2
6
TMS
TDO
30
32
34
36
38
40
42
44
46
48
50
COP_TDO
COP_TDI
COP_TCK
10
8
4
TDI
TCK
Vendor I/O 5 (Aurora HRESET)
34
32
20
18
Vendor I/O 4 N/C
10 k
Ω
EVT[4]
Vendor I/O 3 N/C
Vendor I/O 2 (Aurora Event Out)
Vendor I/O 1 (Aurora Event In)
Vendor I/O 0 (Aurora HALT)
TX0_P
EVT[4]
EVT[1]
16
51
53
55
57
59
61
63
65
67
69
52
54
56
58
60
62
64
66
68
70
EVT[0]
14
1
SD_TX09_P
SD_TX09_N
SD_TX08_P
SD_TX08_N
SD_RX09_P
SD_RX09_N
SD_RX08_P
SD_RX08_N
TX0_N
3
7
TX1_P
TX1_N
RX0_P
RX0_N
RX1_P
RX1_N
9
13
15
19
21
Duplex 70
Connector
Physical Pinout
5,11,17,23,24,
29,30,35,36,41,
42,47,48,53,54,
59,60,65,66
Chip
Notes:
1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
to position B.
4. Asserting HRESET causes a hard reset on the device.
Figure 60. Aurora 70 pin connector duplex interface connection
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
147
Hardware design considerations
3.6.3
Guidelines for high-speed interface termination
This section provides the guidelines for high-speed interface termination when the SerDes interface is entirely unused or when
it is partly unused.
3.6.3.1
SerDes interface entirely unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section.
The following pins must be left unconnected:
•
•
•
•
•
•
SD_TX[19:0]
SD_TX[19:0]
SD_IMP_CAL_RX
SD_IMP_CAL_TX
SD1_IMP_CAL_RX
SD1_IMP_CAL_TX
The following pins must be connected to SGND:
•
•
•
•
SD_RX[19:0]
SD_RX[19:0]
SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4
SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4
The RCW configuration fields SRDS_LPD_B1, SRDS_LPD_B2, SRDS_LPD_B3, and SRDS_LPD_B4, all bits must be set to
power down all the lanes in each bank.
The RCW configuration field SRDS_EN may be cleared to power down the SerDes block for power saving. Setting
RCW[SRDS_EN_S1] = 0 powers down the PLLs of banks 1 to 3; RCW[SRDS_EN_S2]=0 powers down the PLL of bank 4.
Additionally, software may configure SRDSBnRSTCTL[SDRD] = 1 for the unused banks to power down the SerDes bank
PLLs to save power.
Note that both SV and XV must remain powered.
DD
DD
3.6.3.2
SerDes interface partly unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as
described in this section.
The following pins must be left unconnected:
•
•
SD_TX[n]
SD_TX[n]
The following unused pins must be connected to SGND:
•
•
•
•
•
•
SD_RX[n]
SD_RX[n]
SD_REF_CLK1, SD_REF_CLK1 (If entire SerDes bank 1 unused)
SD_REF_CLK2, SD_REF_CLK2 (If entire SerDes bank 2 unused)
SD_REF_CLK3, SD_REF_CLK3 (If entire SerDes bank 3 unused)
SD_REF_CLK4, SD_REF_CLK4 (If entire SerDes bank 4 unused)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
148
Freescale Semiconductor
Hardware design considerations
In the RCW configuration field for each bank SRDS_LPD_Bn with unused lanes, the respective bit for each unused lane must
be set to power down the lane.
3.6.4
USB controller connections
This section details the hardware connections required for the USB controllers.
3.6.4.1
USB divider network
This figure shows the required divider network for the VBUS interface for the chip. Additional requirements for the external
components are as follows:
•
Both resistors require 0.1% accuracy and a current capability of up to 1 mA. They must both have the same temperature
coefficient and accuracy.
•
•
The zener diode must have a value of 5 V−5.25 V.
The 0.6 V diode requires an I = 10 mA, I < 500 nA and V
= 0.8 V.
F
R
F(Max)
USBn_DRVVBUS
USBn_PWRFAULT
VBUS Charge
Pump
VBUS
(USB Connector)
0.6 VF
51.2 kΩ
18.1 kΩ
5 VZ
USBn_VBUS_CLMP
Chip
Figure 61. Divider network at VBUS
USB1_DRVVBUS and USB1_PWRFAULT are muxed on GPIO[4:5] pins, respectively. USB2_DRVVBUS and
USB2_PWRFAULT are muxed on GPIO[6:7] pins, respectively. Setting the RCW[GPIO] bit selects USB functionality on the
GPIO pins.
3.6.4.2
USBn_V _1P8_DECAP capacitor options
DD
The USBn_V _1P8_DECAP pins require a capacitor connected to GND. This table list the recommended capacitors for the
DD
USBn_V _1P8_DECAP signal.
DD
Table 107. Recommended capacitor parts for USBn_V _1P8_DECAP
DD
Manufacturer
Part Number
Value
ESR
Package
Kemet
T494B105(1)025A(2)
T494B155(1)025A(2)
NMC0603X7R106KTRPF
CERB2CX5R0G105M
TR3B105(1)035(2)1500
1 μF, 25 V
1.5 μF, 25 V
1 μF, 10 V
1 μF, 4 V
2 Ω
B(3528)
—
1.5 Ω
NIC
TDK Corporation
Vishay
Low ESR
200 m-Ω
1.5 Ω
0603
0603
1 μF, 35 V
B(3528)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
149
Hardware design considerations
3.7
Recommended thermal model
Information about Flotherm models of the package or thermal data not available in this document can be obtained from your
local Freescale sales office.
3.8
Thermal management information
This section provides thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for
air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow,
and thermal interface material.
The recommended attachment method to the heat sink is illustrated in this figure. The heat sink should be attached to the
printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45
Newton).
FC-PBGA package (small lid)
Heat sink
Heat sink
clip
Adhesive or
thermal interface material
Die lid
Die
Printed-circuit board
Figure 62. Exploded cross-sectional view—FC-PBGA (with lid) package
The system board designer can choose between several types of heat sinks to place on the device. There are several
commercially-available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat
sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method,
assembly, and cost.
3.8.1
Internal package conduction resistance
For the package, the intrinsic internal conduction thermal resistance paths are as follows:
•
•
•
The die junction-to-case thermal resistance
The die junction-to-lid-top thermal resistance
The die junction-to-board thermal resistance
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
150
Freescale Semiconductor
Package information
This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External resistance
Radiation
Convection
Junction to case top
Heat sink
Junction to lid top
Thermal interface material
Die/Package
Die junction
Internal resistance
Package/solder balls
Printed-circuit board
Radiation
Convection
External resistance
(Note the internal versus external package resistance)
Figure 63. Package with heat sink mounted to a printed-circuit board
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the
silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case
thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.
3.8.2
Thermal interface materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The
performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is
generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by
means of a spring clip attachment to the printed-circuit board (see Figure 62).
The system board designer can choose among several types of commercially-available thermal interface materials.
4
Package information
The following section describes the detailed content and mechanical description of the package.
4.1
Package parameters for the FC-PBGA
The package parameters are as provided in the following list. The package type is 37.5 mm × 37.5 mm, 1295 flip-chip,
plastic-ball, grid array (FC-PBGA).
Package outline
Interconnects
37.5 mm × 37.5 mm
1295
Ball Pitch
1.0 mm
Ball Diameter (typical)
Solder Balls
0.60 mm
96.5% Sn, 3% Ag, 0.5% Cu
2.88 mm to 3.53 mm (Maximum)
Module height (typical)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
151
Package information
4.2
Mechanical dimensions of the FC-PBGA
This figure shows the mechanical dimensions and bottom surface nomenclature of the chip.
Figure 64. Mechanical dimensions of the FC-PBGA with full lid
NOTES:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. All dimensions are symmetric across the package center lines unless dimensioned otherwise.
4. Maximum solder ball diameter measured parallel to datum A.
5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
6. Parallelism measurement shall exclude any effect of mark on top surface of package.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
152
Freescale Semiconductor
Security fuse processor
5
Security fuse processor
This chip implements the QorIQ platform’s Trust Architecture, supporting capabilities such as secure boot. Use of the Trust
Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust
Architecture and SFP can be found in the applicable chip reference manual.
To program SFP fuses, the user is required to supply 1.5 V to the POV pin per Section 2.2, “Power-up sequencing.” POV
DD
DD
should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles.
All other times, connect POV to GND. The sequencing requirements for raising and lowering POV are shown in Figure 8.
DD
DD
To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature
range per Table 3.
Users not implementing the QorIQ platform’s Trust Architecture features are not required to program fuses and should connect
POV to GND.
DD
6
Ordering information
Please contact your local Freescale sales office or regional marketing team for ordering information.
6.1
Part numbering nomenclature
This table provides the Freescale QorIQ platform part numbering nomenclature.
Table 108. Part Numbering Nomenclature
p
n
nn
n
x
t
e
n
c
d
r
Number
of Cores
Qual
Status
Temperature
Range
Package
Type
CPU
Speed
DDR
Speed
Die
Revision
Generation Platform
Derivative
Encryption
P = 45 nm
5
• 01 =
1 core
• 02 =
2 cores
• 04 =
4 cores
0–9
P =
Prototype
N =
• S = Std
temp
(0 °C to
105 °C
• X = Ext
temp
• E =
SEC
1 =
FC-PBGA
• T =
1800 MHz
• M =
1200 MHz
• N =
1333 MHz
• Q =
1600 MHz
A = Rev
1.0
B = Rev
2.0
C = Rev
2.1
present lead-free • V =
• N =
SEC
not
Qualified
7 =
2000 MHz
FC-PBGA • 2 =
C4/C5
2200 MHz
(–40 °Cto
105 °C)
present lead-free
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
153
Revision history
6.2
Orderable part numbers addressed by this document
This table provides the Freescale orderable part numbers addressed by this document for the chip. Contact your Freescale Sales
Representative for more information on orderable parts as not all combinations of orderable part numbers are available.
Table 109. Orderable part numbers addressed by this document
Part
number
p
n
nn
n
x
t
e
n
cd
r
P5021
P
5
02 = 2 cores
1
P =
Prototype
N =
• S = Std
temp (0 °C
to 105 °C
• E = SEC
present FC-PBGA
• N = SEC lead-free
1 =
• TM =
1800 MHz/
1200 MHz
B = Rev
2.0
C = Rev
2.1
Qualified • X = Ext
not
7 =
• VN =
temp
(–40 °C to
105 °C)
present FC-PBGA
C4/C5
2000 MHz/
1333 MHz
lead-free • 2Q =
2200 MHz/
1600 MHz
7
Revision history
This table provides a revision history for this document.
Table 110. Revision history
Rev.
Number
Date
Description
1
0
05/2014 • Includes two SATA controllers
• Updated block diagram
• In Table 1 “Pins listed by bus,” updated footnote 42.
• In Table 9 “VDD_LP power dissipation,” updated footnote 2.
12/2013 • Initial public release.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
154
Freescale Semiconductor
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based on the
information in this document.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for each
customer application by customer’s technical experts. Freescale does not convey any
license under its patent rights nor the rights of others. Freescale sells products pursuant
to standard terms and conditions of sale, which can be found at the following address:
freescale.com/SalesTermsandConditions.
Freescale, the Freescale logo, and QorIQ are trademarks of Freescale Semiconductor,
Inc., Reg. U.S. Pat. & Tm. Off. CoreNet is a trademark of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. The
Power Architecture and Power.org word marks and the Power and Power.org logos and
related marks are trademarks and service marks licensed by Power.org.
© 2013-2014 Freescale Semiconductor, Inc.
Document Number: P5021
Rev. 1
05/2014
相关型号:
©2020 ICPDF网 联系我们和版权申明