NTSX2102GU8 [NXP]

Dual supply translating transceiver; open drain; auto direction sensing;
NTSX2102GU8
型号: NTSX2102GU8
厂家: NXP    NXP
描述:

Dual supply translating transceiver; open drain; auto direction sensing

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中文:  中文翻译
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NTSX2102  
Dual supply translating transceiver; open drain; auto  
direction sensing  
Rev. 2 — 11 February 2013  
Product data sheet  
1. General description  
The NTSX2102 is a 2-bit, dual supply translating transceiver with auto direction sensing,  
that enables bidirectional voltage level translation. It features two 2-bit input-output ports  
(An and Bn), one output enable input (OE) and two supply pins (VCC(A) and VCC(B)). Both  
supplies can be supplied at any voltage between 1.65 V and 5.5 V. This flexibility makes  
the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V, 3.3 V  
and 5.0 V). Pins An and OE are referenced to VCC(A) and pins Bn are referenced to VCC(B)  
A LOW level at pin OE causes the outputs to assume a high-impedance OFF-state. This  
device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing the damaging backflow current through the device when it  
is powered down.  
.
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 1.65 V to 5.5 V and VCC(B): 1.65 V to 5.5 V  
Maximum data rates:  
50 Mbps  
IOFF circuitry provides partial Power-down mode operation  
Inputs accept voltages up to 5.5 V  
ESD protection:  
HBM JS-001 Class 2 exceeds 2000 V  
CDM JESD22-C101E exceeds 2000 V  
Latch-up performance exceeds 100 mA per JESD 78B Class II  
Multiple package options  
Specified from 40 C to +85 C  
3. Applications  
I2C/SMBus  
UART  
GPIO  
NTSX2102  
NXP Semiconductors  
Dual supply translating transceiver; open drain; auto direction sensing  
4. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
NTSX2102GM  
NTSX2102GU8  
NTSX2102GD  
40 C to +85 C  
40 C to +85 C  
40 C to +85 C  
XQFN8  
XQFN8  
XSON8  
plastic extremely thin quad flat package; no leads;  
8 terminals; body 1.6 1.6 0.5 mm  
SOT902-2  
XQFN8: plastic, extremely thin quad flat package; no SOT1309-1  
leads; 8 terminals; body 1.4 1.2 0.5 mm  
plastic extremely thin small outline package;  
SOT996-2  
no leads; 8 terminals; body 3 2 0.5 mm  
5. Marking  
Table 2.  
Marking  
Type number  
NTSX2102GM  
NTSX2102GU8  
NTSX2102GD  
Marking code  
sX2  
sX  
sX2  
6. Functional diagram  
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ꢌꢍ  
ꢃꢈ  
ꢎꢏꢐꢑꢒꢓꢎꢔ  
ꢎꢏꢐꢑꢒꢓꢎꢔ  
ꢎꢏꢐꢑꢒꢓꢎꢔ  
ꢎꢏꢐꢑꢒꢓꢎꢔ  
ꢇꢈ  
ꢇꢅ  
ꢃꢅ  
ꢁꢁꢂꢃꢄ  
ꢁꢁꢂꢇꢄ  
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢄ  
Fig 1. Logic symbol  
NTSX2102  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 11 February 2013  
2 of 20  
NTSX2102  
NXP Semiconductors  
Dual supply translating transceiver; open drain; auto direction sensing  
7. Pinning information  
7.1 Pinning  
ꢀꢁꢂꢃꢄꢅꢆꢄ  
ꢔꢓꢎ"ꢘꢐꢏ#ꢕꢁ  
ꢘꢐ$ꢓ%ꢕꢏꢎꢓꢏ  
ꢀꢁꢂꢃꢄꢅꢆꢄ  
ꢃꢃꢄꢀꢅ  
ꢀꢁ  
!
ꢉꢁ  
ꢉꢆ  
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ꢘꢐ$ꢓ%ꢕꢏꢎꢓꢏ  
ꢀꢁ  
 
!
ꢃꢃꢄꢉꢅ  
ꢀꢆ  
ꢉꢁ  
ꢉꢆ  
ꢇꢈ  
ꢀꢆ  
ꢊꢋꢌ  
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢅ  
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢆ  
ꢍꢎꢏꢐꢑꢒꢏꢎꢓꢐꢔꢕꢔꢖꢒꢕꢗꢘꢓꢙ  
ꢍꢎꢏꢐꢑꢒꢏꢎꢓꢐꢔꢕꢔꢖꢒꢕꢗꢘꢓꢙ  
Fig 2. Pin configuration SOT902-2 (XQFN8)  
Fig 3. Pin configuration SOT1309-1 (XQFN8)  
ꢀꢁꢂꢃꢄꢅꢆꢄ  
ꢃꢃꢄꢉꢅ  
 
!
ꢃꢃꢄꢀꢅ  
ꢀꢁ  
ꢉꢁ  
ꢉꢆ  
ꢀꢆ  
ꢇꢈ  
ꢊꢋꢌ  
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢃ  
ꢍꢎꢏꢐꢑꢒꢏꢎꢓꢐꢔꢕꢔꢖꢒꢕꢗꢘꢓꢙ  
Fig 4. Pin configuration SOT996-2 (XSON8)  
7.2 Pin description  
Table 3.  
Symbol  
B2, B1  
GND  
Pin description  
Pin  
6, 7  
4
Description  
data input or output (referenced to VCC(B)  
)
)
ground (0 V)  
VCC(A)  
A2, A1  
OE  
1
supply voltage A  
3, 2  
5
data input or output (referenced to VCC(A)  
output enable input (active HIGH; referenced to VCC(A)  
)
VCC(B)  
8
supply voltage B  
NTSX2102  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 11 February 2013  
3 of 20  
NTSX2102  
NXP Semiconductors  
Dual supply translating transceiver; open drain; auto direction sensing  
8. Functional description  
Table 4.  
Function table[1]  
Supply voltage  
VCC(A)  
Input  
OE  
L
Input/output  
VCC(B)  
An  
Bn  
1.65 V to 5.5 V  
1.65 V to 5.5 V  
GND[2]  
1.65 V to 5.5 V  
1.65 V to 5.5 V  
GND[2]  
Z
Z
H
input or output  
Z
output or input  
Z
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.  
[2] When either VCC(A) or VCC(B) is at GND level, the device goes into power-down mode.  
9. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC(A)  
VCC(B)  
VI  
Parameter  
Conditions  
Min  
Max  
+6.5  
+6.5  
+6.5  
+6.5  
Unit  
V
supply voltage A  
supply voltage B  
input voltage  
0.5  
0.5  
0.5  
0.5  
V
[1][2]  
[1][2]  
[1][2]  
A port and OE input  
B port  
V
V
VO  
output voltage  
Active mode  
A or B port  
0.5  
VCCO + 0.5  
V
[1]  
Power-down or 3-state mode  
A or B port  
0.5  
50  
50  
-
+6.5  
-
V
IIK  
input clamping current  
output clamping current  
output current  
VI < 0 V  
mA  
mA  
mA  
mA  
mA  
C  
IOK  
IO  
VO < 0 V  
-
[2]  
VO = 0 V to VCCO  
ICC(A) or ICC(B)  
50  
100  
-
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
ground current  
100  
65  
-
storage temperature  
total power dissipation  
+150  
250  
Tamb = 40 C to +85 C  
mW  
[1] The minimum input and minimum output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] CCO is the supply voltage associated with the output.  
V
10. Recommended operating conditions  
Table 6.  
Symbol  
VCC(A)  
Recommended operating conditions[1]  
Parameter  
Conditions  
Min  
1.65  
1.65  
Max  
5.5  
Unit  
V
supply voltage A  
supply voltage B  
VCC(B)  
5.5  
V
NTSX2102  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 11 February 2013  
4 of 20  
NTSX2102  
NXP Semiconductors  
Dual supply translating transceiver; open drain; auto direction sensing  
Table 6.  
Symbol  
Tamb  
Recommended operating conditions[1] …continued  
Parameter  
Conditions  
Min  
Max  
Unit  
ambient temperature  
40  
+85  
C  
t/V  
input transition rise and fall rate A, B or OE port  
VCC(A) = 1.65 V to 5.5 V;  
VCC(B) = 1.65 V to 5.5 V  
-
10  
ns/V  
[1] Hold the A and B sides of an unused I/O pair in the same state, both at VCCI or both at GND.  
11. Static characteristics  
Table 7.  
Typical static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
CI  
input  
OE input; VCC(A) = VCC(B) = 0 V  
-
2.2  
-
pF  
capacitance  
CI/O  
input/output  
capacitance  
A or B port; VCC(A) = 5.0 V; VCC(B) = 5.0 V  
-
10  
-
pF  
[1] VCCO is the supply voltage associated with the output.  
Table 8.  
Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 C to +85 C  
Unit  
Min  
Max  
VIH  
HIGH-level input  
A or B port  
voltage  
[1]  
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V  
OE input  
VCCI 0.4  
-
V
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V  
A or B port  
0.65VCC(A)  
-
V
V
V
VIL  
LOW-level input  
voltage  
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V  
OE input  
-
-
0.4  
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V  
0.35VCC(A)  
[2]  
[2]  
VOL  
LOW-level output A or B port; IO = 6 mA  
voltage  
VI 0.15 V; VCC(A) = 1.65 V to 5.5 V;  
-
-
-
-
-
0.4  
1  
2  
2  
2  
V
VCC(B) = 1.65 V to 5.5 V  
II  
input leakage  
current  
OE input; VI = 0 V to VCC(A); VCC(A) = 1.65 V to 5.5 V;  
A  
A  
A  
A  
V
CC(B) = 1.65 V to 5.5 V  
IOZ  
IOFF  
OFF-state output A or B port; VO = 0 V or VCCO; VCC(A) = 0 V to 5.5 V;  
current VCC(B) = 0 V to 5.5 V  
power-off leakage A port; VI or VO = 0 V to 5.5 V;  
current  
VCC(A) = 0 V; VCC(B) = 0 V to 5.5 V  
B port; VI or VO = 0 V to 5.5 V;  
VCC(B) = 0 V; VCC(A) = 0 V to 5.5 V  
NTSX2102  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 11 February 2013  
5 of 20  
NTSX2102  
NXP Semiconductors  
Dual supply translating transceiver; open drain; auto direction sensing  
Table 8.  
Static characteristics …continued  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
40 C to +85 C  
Unit  
Min  
Max  
[1]  
ICC  
supply current  
VI = 0 V or VCCI; IO = 0 A  
ICC(A)  
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V;  
OE = LOW or HIGH  
-
5
A  
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 0 V  
VCC(A) = 0 V; VCC(B) = 1.65 V to 5.5 V  
ICC(B)  
-
-
2
A  
A  
2  
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V;  
OE = LOW  
-
5
A  
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 0 V  
VCC(A) = 0 V; VCC(B) = 1.65 V to 5.5 V  
-
-
2  
A  
A  
2
[1] VCCI is the supply voltage associated with the input.  
[2] CCO is the supply voltage associated with the output.  
V
12. Dynamic characteristics  
Table 9.  
Typical dynamic characteristics for temperature 25 C  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for waveforms see Figure 5 and Figure 6.  
[1]  
Symbol Parameter  
Conditions  
VCCO  
Unit  
1.8 V  
2.5 V  
3.3 V  
5.0 V  
tTLH  
tTHL  
CPD  
LOW to HIGH  
output transition  
time  
A or B port  
7
5
4
3
ns  
HIGH to LOW  
output transition  
time  
A or B port  
4
-
6
-
8
-
11  
ns  
[2]  
power dissipation OE = VCC(A); VCC(A) = VCC(B)  
capacitance  
;
13.5  
pF  
[3]  
fI = 400 kHz; VI = VCCI  
[1] VCCO is the supply voltage associated with the output.  
[2] CPD is used to determine the dynamic power dissipation (PD in W).  
D = CPD VCC2 fi N + (CL VCC2 fo) where:  
P
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
(CL VCC2 fo) = sum of the outputs.  
[3] VCCI is the supply voltage associated with the input.  
NTSX2102  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 11 February 2013  
6 of 20  
NTSX2102  
NXP Semiconductors  
Dual supply translating transceiver; open drain; auto direction sensing  
Table 10. Dynamic characteristics for temperature range 40 C to +85 C[1]  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.  
Symbol Parameter  
Conditions  
VCC(B)  
Unit  
1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V  
Typ  
Max  
Typ Max Typ Max Typ  
Max  
VCC(A) = 1.8 V 0.15 V  
tPHL  
tPLH  
tPHL  
tPLH  
tPZL  
HIGH to LOW  
propagation delay  
A to B  
A to B  
B to A  
B to A  
3
5
3
5
7
12  
7
3
5
3
1
6
8
6
3
3
4
3
1
5
8
5
2
5
4
5
1
7
7
7
2
ns  
ns  
ns  
ns  
LOW to HIGH  
propagation delay  
HIGH to LOW  
propagation delay  
LOW to HIGH  
propagation delay  
12  
OFF-state to LOW OE to A  
propagation delay  
9
9
16  
16  
9
6
18  
12  
10  
6
14  
12  
10  
6
15 ns  
14 ns  
120 ns  
120 ns  
OE to B  
tPLZ  
LOW to OFF-state OE to A  
propagation delay  
100  
100  
-
120  
120  
1
100  
100  
-
120  
120  
1
100  
100  
-
120  
120  
1
100  
100  
-
OE to B  
[2]  
tsk(o)  
fdata  
output skew time between channels  
data rate  
1
ns  
-
18  
-
18  
-
18  
-
18 Mbps  
VCC(A) = 2.5 V 0.2 V  
tPHL  
tPLH  
tPHL  
tPLH  
tPZL  
HIGH to LOW  
propagation delay  
A to B  
A to B  
B to A  
B to A  
3
1
3
5
6
3
6
8
2
2
2
2
5
4
5
4
2
5
7
5
3
2
2.5  
2
5
5
5
3
ns  
ns  
ns  
ns  
LOW to HIGH  
propagation delay  
2.5  
2
HIGH to LOW  
propagation delay  
LOW to HIGH  
propagation delay  
1.5  
1
OFF-state to LOW OE to A  
propagation delay  
6
9
12  
18  
5
5
10  
10  
8
4.5  
100  
100  
-
10  
9
5
4
8
8
ns  
ns  
OE to B  
tPLZ  
LOW to OFF-state OE to A  
propagation delay  
100  
100  
-
120  
120  
1
100  
100  
-
120  
120  
1
120  
120  
1
100  
100  
-
120 ns  
120 ns  
OE to B  
[2]  
tsk(o)  
fdata  
output skew time between channels  
data rate  
1
ns  
-
18  
-
32  
-
32  
-
32 Mbps  
VCC(A) = 3.3 V 0.3 V  
tPHL  
tPLH  
tPHL  
tPLH  
tPZL  
HIGH to LOW  
propagation delay  
A to B  
A to B  
B to A  
B to A  
3
1
3
4
5
2
5
8
2
5
3
5
7
2
4
3
4
3
2
2
2
1
4
4
4
3
ns  
ns  
ns  
ns  
LOW to HIGH  
propagation delay  
1.5  
2
1.5  
2
HIGH to LOW  
propagation delay  
LOW to HIGH  
propagation delay  
2.5  
1.5  
OFF-state to LOW OE to A  
propagation delay  
6
12  
14  
4.5  
5
9
6
6
9
9
4
4
7
8
ns  
ns  
OE to B  
10  
10  
NTSX2102  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 11 February 2013  
7 of 20  
NTSX2102  
NXP Semiconductors  
Dual supply translating transceiver; open drain; auto direction sensing  
Table 10. Dynamic characteristics for temperature range 40 C to +85 C[1]  
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.  
Symbol Parameter  
Conditions  
VCC(B)  
Unit  
1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V  
Typ  
100  
100  
-
Max  
120  
120  
1
Typ Max Typ Max Typ  
Max  
tPLZ  
LOW to OFF-state OE to A  
100  
120  
120  
1
100  
120  
120  
1
100  
120 ns  
120 ns  
propagation delay  
OE to B  
100  
100  
100  
[2]  
tsk(o)  
fdata  
output skew time between channels  
data rate  
-
-
-
-
-
-
1
ns  
-
18  
32  
40  
40 Mbps  
VCC(A) = 5.0 V 0.5 V  
tPHL  
tPLH  
tPHL  
tPLH  
tPZL  
HIGH to LOW  
propagation delay  
A to B  
A to B  
B to A  
B to A  
5
1
5
4
7
2
7
7
2
1
5
3
5
5
2
1
2
2
4
3
4
4
2
1
2
1
4
3
4
3
ns  
ns  
ns  
ns  
LOW to HIGH  
propagation delay  
HIGH to LOW  
propagation delay  
2
LOW to HIGH  
propagation delay  
2.5  
OFF-state to LOW OE to A  
propagation delay  
6
10  
100  
100  
-
14  
15  
4
5
8
8
4
4
8
7
3
4
5
5
ns  
ns  
OE to B  
tPLZ  
LOW to OFF-state OE to A  
propagation delay  
120  
120  
1
100  
100  
-
120  
120  
1
100  
100  
-
120  
120  
1
100  
100  
-
120 ns  
120 ns  
OE to B  
[2]  
tsk(o)  
fdata  
output skew time between channels  
data rate  
1
ns  
-
18  
-
32  
-
40  
-
52 Mbps  
[1] All typical values are measured at nominal VCC and Tamb = 25 °C.  
[2] Skew between any two outputs of the same package switching in the same direction.  
13. Waveforms  
+
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-./  
ꢇ.  
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ꢉꢐ&ꢕꢀꢐ  
ꢖ'ꢔꢒ'ꢔ  
,
ꢃꢃꢇ  
ꢇ/  
ꢍ./  
ꢍ/.  
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢇ  
Measurement points are given in Table 11.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 5. The data input (An, Bn) to data output (Bn, An) propagation delay times  
NTSX2102  
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+
ꢇꢈꢕꢘꢐꢒ'ꢔ  
,
ꢊꢋꢌ  
-0/ꢕ  
-/0  
ꢃꢃꢇ  
ꢖ'ꢔꢒ'ꢔ  
5
/ꢇ23ꢔꢖ3ꢇ44  
ꢇ443ꢔꢖ3/ꢇ2  
6
ꢇ/  
ꢖ'ꢔꢒ'ꢔꢑ  
ꢓꢐꢏ1#ꢓ$  
ꢖ'ꢔꢒ'ꢔꢑ  
$ꢘꢑꢏ1#ꢓ$  
ꢖ'ꢔꢒ'ꢔꢑ  
ꢓꢐꢏ1#ꢓ$  
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢈ  
Measurement points are given in Table 11.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 6. Enable and disable times  
Table 11. Measurement points[1][2]  
Supply voltage  
VCCO  
Input  
VM  
Output  
VM  
VX  
0.5VCCO  
VY  
1.65 V to 5.5 V  
0.5VCCI  
0.5VCCO  
0.1VCCO  
[1] VCCI is the supply voltage associated with the input.  
[2] CCO is the supply voltage associated with the output.  
V
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2
+
7(ꢕ)  
ꢐꢓ8ꢏꢔꢘꢗꢓ  
ꢒ'#ꢑꢓ  
,
,
ꢁ(ꢕ)  
(ꢕꢂ  
*
*
+
7(ꢕ)  
ꢒꢖꢑꢘꢔꢘꢗꢓ  
ꢒ'#ꢑꢓ  
,
,
ꢁ(ꢕ)  
(ꢕꢂ  
2
/
ꢃꢃ  
ꢃꢃꢇ  
:
/
+
ꢌ9ꢍ  
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢉ  
Test data is given in Table 12.  
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; ZO = 50 ; dV/dt 1.0 V/ns.  
RL = Load resistance.  
CL = Load capacitance including jig and probe capacitance.  
VCC0 = Supply voltage associated with the output.  
Fig 7. Test circuit for measuring switching times  
Table 12. Test data  
Supply voltage  
VCC(A)  
Input  
VI[1]  
Load  
CL  
VCC(B)  
tr/tf  
RL  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
1.65 V to 1.95 V  
2.3 V to 2.7 V  
3.0 V to 3.6 V  
4.5 V to 5.5 V  
VCCI  
VCCI  
VCCI  
VCCI  
2.0 ns  
2.0 ns  
2.5 ns  
2.5 ns  
50 pF  
50 pF  
50 pF  
50 pF  
2.2 k  
2.2 k  
2.2 k  
2.2 k  
[1] VCCI is the supply voltage associated with the input.  
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14. Application information  
14.1 Applications  
The NTSX2102 can be used in point-to-point applications to interface between devices or  
systems operating at different supply voltages. The device is targeted at I2C or 1-wire  
buses which use open-drain drivers.  
ꢁ; ꢕꢂ  
ꢚ;ꢚꢕꢂ  
ꢁ; ꢕꢂ  
ꢚ;ꢚꢕꢂ  
(;ꢁꢕꢟ4  
ꢆ;ꢆꢕ=ꢞ  
ꢆ;ꢆꢕ=ꢞ  
ꢆ;ꢆꢕ=ꢞ  
ꢆ;ꢆꢕ=ꢞ  
(;ꢁꢕꢟ4  
ꢁꢕꢟ4  
ꢃꢃꢄꢀꢅ  
ꢃꢃꢄꢉꢅ  
<6<ꢍꢈ,  
<6<ꢍꢈ,  
ꢃꢇꢋꢍ:ꢇ//ꢈ:  
ꢃꢇꢋꢍ:ꢇ//ꢈ:  
ꢇꢈ  
ꢀꢁꢂꢃꢄꢅꢆꢄ  
ꢀꢁ  
ꢀꢆ  
ꢉꢁ  
ꢉꢆ  
ꢌꢀꢍꢀ  
ꢌꢀꢍꢀ  
ꢀꢀꢀꢁꢂꢂꢃꢄꢃꢊ  
Fig 8. Typical voltage level-translation circuit  
14.2 Architecture  
The architecture of the NTSX2102 is shown in Figure 9. The device does not require an  
extra input signal to control the direction of data flow from A to B or B to A. The NTSX2102  
is a "switch" type voltage translator, it employs two key circuits to enable voltage  
translation:  
1. Two pass-gate transistors (N-channel) that tie the ports together.  
2. An output edge-rate accelerator that detects and accelerates rising and falling edges  
on the I/O pins (see Figure 10).  
ꢃꢃꢄꢀꢅ  
ꢃꢃꢄꢉꢅ  
ꢍꢚ  
ꢇꢋꢈ  
<.ꢇꢍ  
ꢇꢋꢈ  
<.ꢇꢍ  
ꢍꢁ  
ꢇꢋꢈ  
<.ꢇꢍ  
ꢇꢋꢈ  
<.ꢇꢍ  
ꢍꢆ  
ꢍꢜ  
ꢃꢃꢄꢀꢅ  
ꢍꢝ  
ꢃꢃꢄꢉꢅ  
ꢍꢛ  
ꢀꢀꢀꢁꢂꢂꢃꢄꢇꢂ  
Fig 9. Architecture of NTSX2102 I/O cell (one channel)  
NTSX2102  
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During an input transition, a one-shot accelerates the output transition by switching on the  
PMOS transistors (T1, T3) for a LOW-to-HIGH transition. Alternatively, it switches on the  
NMOS transistors (T2, T4) for a HIGH-to-LOW transition. Once activated, the one-shot is  
de-activated after approximately 25 ns (see Figure 11). During the acceleration time, the  
driver output resistance is between approximately 10 and 35 . To avoid signal  
contention, the application must not exceed the maximum data rate or wait for the  
one-shot circuit to turn-off, before applying a signal in the opposite direction.  
ꢀꢀꢀꢁꢂꢂꢃꢄꢇꢋ  
+ꢄꢀꢐꢅ  
ꢄꢂꢅ  
(
(
ꢇꢄꢉꢐꢅ  
ꢄꢂꢅ  
(
ꢆ(  
ꢜ(  
ꢛ(  
 (  
ꢁ((  
ꢍꢕꢄꢐꢑꢅ  
VCC(A) = 3.3 V; VCC(B) = 3.3 V.  
Fig 10. Input and output waveforms showing edge-rate acceleration  
ꢀꢀꢀꢁꢂꢂꢃꢄꢇꢄ  
 (  
ꢇꢐꢓ3ꢑ@ꢖꢔ  
ꢔꢘ"ꢓ  
ꢄꢐꢑꢅ  
ꢛ(  
ꢜ(  
ꢆ(  
(
ꢕꢄꢂꢅ  
ꢃꢃꢇ  
Fig 11. One-shot pulse time versus VCCO  
NTSX2102  
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14.3 Input driver requirements  
As the NTSX2102 is a switch type translator, properties of the input driver directly affect  
the output signal. The external open-drain driver applied to an I/O, determines the static  
current sinking capability of the system. The maximum data rate, output transition times  
(tTHL, tTLH) and propagation delays (tPHL, tPLH) are dependent upon the output impedance  
and edge-rate of the external driver.  
14.4 Output load considerations  
The maximum lumped capacitive load that can be driven is dependent upon the one-shot  
pulse duration and has been tuned to 600 pF. In cases with higher capacitive loading,  
there is a risk that the output does not reach the positive rail within the one-shot pulse  
duration. To avoid excessive capacitive loading and to ensure correct triggering of the  
one-shot, use short trace lengths and low capacitance connectors on NTSX2102 PCB  
layouts. The length of the PCB trace should be such that the round-trip delay of any  
reflection is within the one-shot pulse duration. Such a length ensures low impedance  
termination and avoids output signal oscillations and one-shot retriggering.  
14.5 Output enable (OE)  
An output enable input (OE) is used to disable the device. Setting OE = LOW causes all  
I/Os to assume the high-impedance OFF-state.  
14.6 Power-up  
When either of the supplies VCC(n) is at 0 V, outputs are in the high-impedance OFF-state.  
One of the advantages of NTSX translators is that either VCC(A) or VCC(B) may be powered  
up first. To reduce dissipation during power-up, ensure that output enable (OE) is defined.  
Connect it via a pull down resistor to GND or, if the application allows, hardwired to VCC(A)  
.
If the OE pin is hardwired to VCC(A), either supply can be powered up or down first. If a pull  
down is used, the following sequences are recommended.  
For power-up:  
1. Apply power to either supply pin  
2. Apply power to other supply pin  
3. Enable the device by driving OE HIGH  
For power down:  
1. Disable the device by driving OE LOW  
2. Remove power from either supply pin  
3. Remove power from other supply pin  
14.7 Pull-up resistors on I/O lines  
Each A port I/O requires a pull-up resistor to VCC(A), and each B port I/O requires a pull-up  
resistor to VCC(B). Choose the magnitude of the pull-up resistors to ensure that the output  
voltage levels meet the application requirement.  
NTSX2102  
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15. Package outline  
XQFN8: plastic, extremely thin quad flat package; no leads;  
8 terminals; body 1.6 x 1.6 x 0.5 mm  
SOT902-2  
X
D
B
A
E
terminal 1  
index area  
A
A
1
detail X  
e
C
v
w
C
C
A
B
b
y
y
C
1
4
3
2
5
e
1
6
7
1
terminal 1  
index area  
8
L
metal area  
not for soldering  
L
1
0
1
2 mm  
scale  
Dimensions  
(1)  
Unit  
A
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max 0.5 0.05 0.25 1.65 1.65  
0.35 0.15  
0.20 1.60 1.60 0.55 0.5 0.30 0.10 0.1 0.05 0.05 0.05  
0.00 0.15 1.55 1.55 0.25 0.05  
mm nom  
min  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
sot902-2_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
- - -  
JEDEC  
JEITA  
- - -  
10-11-02  
11-03-31  
SOT902-2  
MO-255  
Fig 12. Package outline SOT902-2 (XQFN8)  
NTSX2102  
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XQFN8: plastic, extremely thin quad flat package; no leads;  
8 terminals; body 1.4 x 1.2 x 0.5 mm  
SOT1309-1  
B
A
E
D
A
A
1
A
3
terminal 1  
index area  
detail X  
e
1
v
w
C
C
A
B
C
b
terminal 1  
index area  
y
1
y
e
C
2
4
L
1
b
5
8
6
X
L
1
0
3 mm  
scale  
Dimensions  
Unit  
A
A
1
A
3
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max 0.50 0.025  
mm nom  
min  
0.25 1.45 1.25  
0.35 0.45  
0.127 0.20 1.40 1.20 0.4 0.8 0.30 0.40 0.10 0.05 0.05 0.05  
0.15 1.35 1.15 0.25 0.35  
0.00  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included  
sot1309-1_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
JEDEC  
JEITA  
11-08-18  
11-08-23  
SOT1309-1  
MO-255  
Fig 13. Package outline SOT1309-1 (XQFN8)  
NTSX2102  
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XSON8: plastic extremely thin small outline package; no leads;  
8 terminals; body 3 x 2 x 0.5 mm  
SOT996-2  
D
B
A
E
A
A
1
detail X  
terminal 1  
index area  
e
1
C
v
w
C
C
A
B
b
e
L
1
y
1
y
C
1
4
L
2
L
8
5
X
0
1
2 mm  
scale  
Dimensions (mm are the original dimensions)  
(1)  
Unit  
A
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max  
mm nom 0.5  
min  
0.05 0.35 2.1 3.1  
0.00 0.15 1.9 2.9  
0.5 0.15 0.6  
0.3 0.05 0.4  
0.5 1.5  
0.1 0.05 0.05 0.1  
sot996-2_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
JEDEC  
JEITA  
07-12-21  
12-11-20  
SOT996-2  
Fig 14. Package outline SOT996-2 (XSON8)  
NTSX2102  
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16. Abbreviations  
Table 13. Abbreviations  
Acronym  
CDM  
Description  
Charged Device Model  
CMOS  
DUT  
Complementary Metal Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
GPIO  
General Purpose Input Output  
Human Body Model  
HBM  
I2C  
Inter-Integrated Circuit  
PCB  
Printed Circuit Board  
PMOS  
SMBus  
UART  
UTLP  
Positive Metal Oxide Semiconductor  
System Management Bus  
Universal Asynchronous Receiver Transmitter  
Ultra Thin Leadless Package  
17. Revision history  
Table 14. Revision history  
Document ID  
NTSX2102 v.2  
Modifications:  
NTSX2102 v.1.1  
Modifications:  
NTSX2102 v.1  
Release date  
20130211  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
NTSX2102 v.1.1  
For type number NTSX2102GD XSON8U has changed to XSON8.  
20121121 Product data sheet  
Section 1 “General description” text updated.  
20121119 Product data sheet  
-
NTSX2102 v.1  
-
-
NTSX2102  
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18. Legal information  
18.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use — NXP Semiconductors products are not designed,  
18.2 Definitions  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer’s own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
18.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
NTSX2102  
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Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
non-automotive qualified products in automotive equipment or applications.  
18.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
19. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
NTSX2102  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 11 February 2013  
19 of 20  
NTSX2102  
NXP Semiconductors  
Dual supply translating transceiver; open drain; auto direction sensing  
20. Contents  
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
7
7.1  
7.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
8
Functional description . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 4  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
9
10  
11  
12  
13  
14  
Application information. . . . . . . . . . . . . . . . . . 11  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Input driver requirements . . . . . . . . . . . . . . . . 13  
Output load considerations. . . . . . . . . . . . . . . 13  
Output enable (OE) . . . . . . . . . . . . . . . . . . . . 13  
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Pull-up resistors on I/O lines. . . . . . . . . . . . . . 13  
14.1  
14.2  
14.3  
14.4  
14.5  
14.6  
14.7  
15  
16  
17  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17  
18  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
18.1  
18.2  
18.3  
18.4  
19  
20  
Contact information. . . . . . . . . . . . . . . . . . . . . 19  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2013.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 11 February 2013  
Document identifier: NTSX2102  

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