MS140131KT/D_技术文档

Order Number: MS140131KT/D

Rev. 5.0, 5/2001

Semiconductor Products Sector

6KRUWꢀ+DXOꢀ/RRSꢀ'XDOꢀ3&0ꢀ

&RGHFꢁ)LOWHUꢂ6/,&ꢀ&KLSVHWꢀZLWKꢀ

*&,ꢀ,QWHUIDFH

&217(176

Section 1

Overview

1.1

1.2

Introduction: MC1420232 CODSP and MC1430132 SHLIC. . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Section 2

Applications

2.1

2.2

Recommended External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Section 3

Pin Descriptions

3.1

3.2

3.3

3.4

Device Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

MC1420232 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

MC1430132 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Unused Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.1 CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.2 SHLIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Note on Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5.1 CODSP Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5.2 SHLIC Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.5

Section 4

Functional Characteristics of the SH-POTS System

4.1

4.2

On-Hook Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Ringing Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1 Balanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.2 Semi-Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.1 Battery Voltage and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3

MS140131KT

iii

Contents

4.4

AC Transmission Characteristics (MS140131KT System). . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.4.1 Transmit and Receive Filter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.4.2 Transmit and Receive Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.4.3 Source Impedance (Z ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

CO

4.4.4 Balance Impedance (Echo Canceller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Metering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.5.1 Metering Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.5.2 Metering Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

CODSP Clock Recovery PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

4.7.1 User-Defined I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

4.7.2 Test Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

4.5

4.6

4.7

Section 5

Electrical Characteristics

5.1

5.2

5.3

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Thermal Shutdown SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.3.1 Transient Energy Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . 5-2

5.4.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.4

5.4.2

V

Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

DD3

5.4.3 DCO DC Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.4.4 VAG Analog Ground Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.4.5 DC Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.4.6 DCC Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.4.7 Characteristics for the Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.4.8 Test Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.4.9 Battery Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

AC Characteristics (SHLIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.5.1 Receive Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.5.2 Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.5.3 Overpower and Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Off-Hook Characteristics (MS140131KT System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.5

5.6

Section 6

Detailed Programming Description

6.1

6.2

6.3

6.4

6.5

GCI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Timeslot Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

SH-POTS GCI Interface: Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

C/I Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

iv

MS140131KT

Contents

6.6

ID Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Write Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Memory Map of the CODSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Data RAM — MemID = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

LBO Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Alarm Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

Meaning and Default Values of the Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

Coprocessor Coefficient RAM — MemID = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

Meaning and Default Values of the Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

Shared Memory — MemID = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

Meaning and Default Values of the Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.7

6.8

6.9

6.10

6.11

6.12

6.13

6.14

6.15

6.16

6.17

Section 7

Mechanical Specifications

7.1

7.2

7.3

MC1420232 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

MC1430132 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Recommended Pad Layout for 44-Lead TQFP MC1420232 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

MS140131KT

v

),*85(6

1-1. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

2-1. Typical SH-POTS Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2-2. Application Schematic for Two Analog Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2-3. Recommended Overvoltage Protection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

3-1. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3-2. MC1420232 CODSP Recommended Power-Supply Decoupling Arrangements . . . . . . . . . . . . 3-7

4-1. SH-POTS Line Voltages — Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4-2. Nominal Hookswitch Detection Thresholds (Default Values) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4-3. Application Suggestion for Semi-Unbalanced Ringing Injection . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4-4. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4-5. Transmit and Receive Frequency Response (Default). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4-6. Relative Group Delay, Transmit and Receive Paths (Digital-to-Digital) Referred to 1 kHz . . . 4-7

4-7. Three-Element Z

CO

Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4-8. Metering Pulse Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

5-1. Block Diagram Showing Gains in Various Signal Paths in SHLIC . . . . . . . . . . . . . . . . . . . . . . 5-10

5-2. Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

6-1. GCI Data Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6-2. GCI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

7-1. Recommended Pad Layout for 44-Lead TQFP MC1420232 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

MS140131KT

vii

7$%/(6

2-1. Recommended External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

3-1. Pin Descriptions for MC1420232 CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3-2. Pin Descriptions for MC1430132 SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3-3. MC1420232 CODSP Unused Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3-4. MC1430132 SHLIC Unused Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

4-1. On-Hook Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4-2. Ringing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4-3. DC Feed Characteristics [R

4-4. Examples of Z

CO

= 60 Ω Total (50 Ω +10 Ω Protection) x 2] . . . . . . . . . . . 4-5

Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

feed

4-5. Metering Characteristics (Determined by MC1420232 CODSP) . . . . . . . . . . . . . . . . . . . . 4-10

4-6. Tone Signal Levels (Common Values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4-7. Tone Generator Division Values for Common Frequencies from ETS-300-001

and DTMF Tones. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4-8. Required Frequency Setting Values (N) for a Melody Generator

(Western Equal-Tempered Scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

5-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5-2. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5-3. Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5-4. SHLIC Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5-5. Power-On Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5-6.

V

Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

DD3

5-7. Voltage Characteristics A Wire (AW), B Wire (BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5-8. Impedance Characteristics A Wire (AW), B Wire (BW). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5-9. Rx, Tx Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5-10. DCO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5-11. VAG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5-12. DC Loop Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5-13. DCC Input Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5-14. Digital I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5-15. Sense Bridge Inputs Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5-16. Test Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5-17. Ringing Battery Switch Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5-18. Typical Gains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5-19. Short Circuit Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5-20. Off-Hook Characteristics (MS140131KT System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

6-1. GCI Mode and Timeslot Address Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6-2. GCI Interface: Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6-3. C/I Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6-4. Memory Map for CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6-5. Data RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

MS140131KT

viii

Tables

6-6. LBO Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6-7. Data RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6-8. Coprocessor Coefficient RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6-9. Coprocessor Coefficient RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . 6-12

6-10. Shared Memory: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6-11. Shared Memory: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

MS140131KT

ix

6(&7,21ꢀꢃ

29(59,(:

ꢃꢄꢃ ,1752'8&7,21ꢅꢀ0&ꢃꢆꢇꢈꢇꢉꢇꢀ&2'63ꢀ$1'ꢀ

0&ꢃꢆꢉꢈꢃꢉꢇꢀ6+/,&

The MS140131KT chipset provides all the functions necessary to connect analog telephone sets or other

analog terminals (telefax, answering machines, modems, etc.) into digital communication systems. It

provides an economical solution for the traditional “BORS(C)HT” [Battery, Overvoltage, Ringing,

Supervision, (Codec), Hybrid, Test] functions found in central-office exchanges, but is optimized for

short-range communication [e.g., up to 500 m with 5 RENs (Ringer Equivalence Number) attached].

Virtually all system-dependent parameters can be set under software control, giving an unprecedented

flexibility to the system integrator, as well as optimizing the system cost. The digital interface to the

1

SH-POTS (Short Haul, Plain Old Telephone System) chipset uses the industry-standard GCI interface .

The system architecture has been designed to offer the most cost-effective solution for short haul systems,

yet offers the full flexibility required to meet worldwide analog telephony standards. The MS140131KT

chipset is also suitable for Q.552 applications.

The MS140131KT chipset comprises three devices (see Figure 1-1): a pair of high-voltage devices, the

Short Haul Line Interface Circuit (SHLIC) which provides the signal and power interface to the analog

lines (one per line), and a low-voltage CMOS, DSP-based dual codec/control device (CODSP) which

provides all signal processing and control functions for up to two lines.

ꢃꢄꢇ .(<ꢀ)($785(6

•

Digitally Programmable Transmission and Signalling Characteristics Meet Worldwide

Specification Requirements

•

Integrated Ringing: Sine or Trapezoid with Auto Cadence

Metering Injection (12 or 16 kHz)

Support On-Hook Transmission: ADSI, CLIP

Battery Reversal

Codec and AC Parameters (Z

CO

and Hybrid) are Fully Programmable (A-Law or µ-Law)

Tone Generators for Signalling and Testing

Loop Current Control and Monitoring are Programmable

1.The General Circuit Interface (GCI) is an interface specification developed jointly by Alcatel, Italtel, GPT, and Siemens, March 1989,

Issue 1.0.

MS140131KT

1-1

: Key Features

•

Minimal External Components

Codec and SLIC Functions for Two Lines

Low-Cost POTS Interface for Short Range

Standard GCI Interface with Timeslot Assigner

Test Support (Test Load Switch, Loopback, Tone Generators)

Supports up to –72 V on V

Ring and –35 V on V

Speech

BAT

CODSP (Dual Codec) is 3.3 V with 5 V Tolerant Input for Low Power Consumption

APPLICATION

DEPENDENT

PROTECTION

V

(+3.3 V)

DD

(OPTIONAL)

SH POTS

V

(+5 V)

DD

POTS

PORT

V

(0 V)

SS

MC1430132

SHLIC

V

(–68 V)

(–32 V)

BATR

V

CODSP

BATS

MC1420232

POTS

PORT

GCI

MC1430132

SHLIC

SERIAL BUS

Figure 1-1. Block Diagram

1-2

MS140131KT

6(&7,21ꢀꢇ

$33/,&$7,216

Figure 2-1 shows a typical SH-POTS application using Motorola semiconductor chip solutions. The short

haul dual PCM chipset provides all necessary functions to connect analog telephone sets or fax terminals to

digital communications systems.

•

Advanced ISDN NT (NTplus), Smart NT1 Personal Router

Analog/Digital PABX

Cable Telephone Systems (Set-Top Box)

Remote Telephone Access Systems

— Fiber to the Curb

— Radio in the Loop

•

Internet Telephones

"U" OR "S/T"

INTERFACE

68030

CPU

CORE

TRANSCEIVER

SCP

ETHERNET

10BASE-T

DC

SCP

METALLIC

TERMINATOR

MC145572

IDL2

OR GCI

“U”

ETHERNET

TRANSCEIVER

ETHERNET

MAC

SCC1

SCC2

SCC3

MC145574

“S/T”

TIMER

BUS INTERFACE

FLASH

GPIO

DRAM

ANALOG

POTS/FAX

POTS

CIRCUITRY

MS140131KT

Figure 2-1. Typical SH-POTS Application

MS140131KT

2-1

Applications:

V

DD3D

USER

OUTPUTS

(OPTIONAL)

V

SA

AW

SPIDI

DD3D

a

CV3D

SPIDO

SPICS

SPICK

RB1

C

B1

TST[0]

BR[0]

TST

BR

SSB

Z

test

RNG[0]

PU[0]

D

RNG

PU

SB

BW

out

b

D

in

FSC

GCI PORT

RB2

C

B2

SHLIC

R

PROT

Rx[0]

Tx[0]

Rx

Tx

DCL

BAT

0, 1

GCIM

AD0

AD1

V

BATS

DCC[0]

DCO[0]

DCC

DCO

BATS

GCI MODE

AND TIMESLOT

ADDRESS

0, 1

D

C

S

C

P

D

P

C

DCI

AD2

DCI

V

BATR

JTDI

V

DD5A

1

—

V

DD5A

C

D

JTDO

JTCK

JTMS

JTRS

VAG

V

JTAG TEST

ACCESS

SSB

1

0

C

V

SSA

DCLF2

DCLF1

VAG

R

F1

C

F1

PLLCK

0

R

F2

C

F2

0

TEST

DEVICE

TEST

Z

VAG

out

V

DD3

DD3A

SA

0

SCLK

CV3A

a

AW

RB1

C

B1

V

DD3D

TST[1]

BR[1]

TST

BR

SSB

R

PWRS

D1

Z

test

RNG[1]

PU[1]

RNG

PU

SB

BW

b

PWRS

RB2

C

B2

C

SHLIC

PWRS

R

PROT

Rx

Tx

Rx[1]

Tx[1]

BAT

V

DCC[1]

DCC

DCO

BATS

C

S

C

P

D

P

DCO[1]

C

DCI

BATR

V

DCI

BATR

CODSP

V

DD5A

C

D

V

SSB

V

SSA

V

SSD

CPLL

V

SSA

DCLF2 DCLF1

C

PLL

R

F1

C

F1

R

F2

C

F2

Figure 2-2. Application Schematic for Two Analog Lines

2-2

MS140131KT

Applications: Recommended External Components

ꢇꢄꢃ 5(&200(1'('ꢀ(;7(51$/ꢀ

&20321(176

Table 2-1. Recommended External Components

Component

Function

x

50 Ω

Comment

R

, R

B1 B2

Feed resistor

1/4 W ±1% (see Note 1)

R

Protection resistance

Test resistor

2 x 10 Ω

510 Ω

PROT

Z

1/4 W, optional

test

, R

R

DC bias filter

10 kΩ

F1 F2

, C

C

No-load stabilization

DC feed separation

DC bias filter

1 nF

100 V (see Note 2)

5%

B1 B2

C

330 nF

470 nF

100 nF

10 µF + 100 nF

100 nF

4.7 nF

DCI

, C

C

100 V, 10%

F1 F2

C

Analog ground decoupling

Analog 3.3 V regulator decoupling

Digital 3.3 V decoupling

Battery supply decoupling

PLL loop filter

VAG

CV3A

CV3D

C

S

100 V

C

PLL

C

Power-on reset delay

Power loss reset

100 nF

100 kΩ

—

PWRS

R

PWS

D

Any small signal diode

1

D

Battery input protection

—

BAT46 required depending

on the power supplies

P

C

5 V power supply decoupling

100 nF

D

NOTES: 1. A ±1% results in a maximum longitudinal balance of 40 dB. For higher values, more precise

matching is required (e.g., ±0.1% for 46 dB).

2. Capacitors are generally not required. They are foreseen to stabilize the line driver outputs when

active but driving no load (test condition only).

ꢇꢄꢇ 29(592/7$*(ꢀ3527(&7,21

There are several recommended overvoltage protection options. The application will determine the most

appropriate one to chose (e.g., in-house only systems with minimal protection requirements, or systems

with loops outside a protected environment requiring more extended protection).

The first external protection network to protect the line circuit against foreign voltages consist of resistors

R

and R

and an overvoltage protection component (see Figure 2-3). Series resistors R and

PR1

PR2

can be PTC, poly-switch, or fusible components.

PR1

For further protection, the simplest and cheapest solution is a diode bridge between SA, SB and V

BATR, respectively. The diodes must be able to allow current peaks more than 20 A.

,

SSB

In case the battery BATR can not accept these high current peaks, add a voltage clamping component to

, or a transient suppressor between each line and V . The clamp voltage or protection voltage

V

SS

minimum must always be larger than the maximum used ringing battery BATR.

MS140131KT

2-3

Applications: Overvoltage Protection

The protection components must be dimensioned in such a way that the transient energy on the chip pins

AW, BW does not exceed 1 mJoule (or, the energy on-chip because of one lightning pulse).

SA

R

PR1

RB1

RB2

RB1

AW

BATR

MC1430132

SHLIC

MC1430132

SHLIC

V

SSB

R

PR2

RB2

PR2

BW

SB

BW

SB

SA

R

PR1

RB1

RB2

PR1

RB1

RB2

AW

TRANSIENT

SUPPRESSOR

MC1430132

SHLIC

MC1430132

SHLIC

V

SSB

R

PR2

R

PR2

BW

SB

BW

SB

Figure 2-3. Recommended Overvoltage Protection Options

2-4

MS140131KT

6(&7,21ꢀꢉ

3,1ꢀ'(6&5,37,216

ꢉꢄꢃ '(9,&(ꢀ3,12876

MC1430132

MC1420232

28-LEAD SOIC

44-LEAD TQFP

PIN 1

V

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AW

SSB

INDICATOR

BW

BAT

BATS

BATR

PU

2

SA

3

SB

4

SSB

DCO

DCI

NC

44 43 42 41 40 39 38 37 36 35 34

5

6

JTDO

JTCK

JTMS

JTDI

33

Rx[0]

1

NC

7

Tx[0]

2

3

32

31

30

29

NC

8

NC

DCC[0]

DCO[0]

DCC[1]

DCO[1]

RNG

BR

9

DCC

Tx

10

11

12

13

14

4

5

TST

VAG

Rx

JTRS

DCLF1

DCLF2

V

6

7

DD3D

28

27

V

DD5A

D

V

out

SSA

V

DD3

SSA

D

in

VAG

8

9

26

25

DCL

FSC

V

DD3A

Tx[1]

Rx[1]

10

11

24

23

V

SSD

12 13 14 15 16 17 18 19 20 21 22

Figure 3-1. Pin Assignments

MS140131KT

3-1

Pin Descriptions: MC1420232 Pin Descriptions

ꢉꢄꢇ 0&ꢃꢆꢇꢈꢇꢉꢇꢀ3,1ꢀ'(6&5,37,216

Table 3-1. Pin Descriptions for MC1420232 CODSP

Type

Pin Name Pin No.

Pin Description

(See Note)

JTDO

JTCK

JTMS

JTDI

1

JTAG test port data out

JTAG test port clock

DO

DIu

P

2

3

JTAG test port mode select

JTAG test port data in

4

JTRS

5

JTAG test port reset

V

6

Digital section supply voltage

GCI port upstream data

GCI port downstream data

GCI port data clock

DD3D

D

out

7

DO5

DI5

P

D

in

8

DCL

FSC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

GCI port frame clock

V

SSD

Digital ground (0 V)

AD2

GCI port timeslot select, MSB

GCI port timeslot select

GCI port timeslot select, LSB

GCI port operating mode (0 = 1 timeslot, 1 = 8 timeslots)

SHLIC 1 test select

DI

AD1

AD0

DI

GCIM

TST[1]

BR[1]

RNG[1]

PU[1]

SCLK

PLLCK

CPLL

Rx[1]

DIs

DO

DB

DI

SHLIC 1 bat reverse control

SHLIC 1 ring control

SHLIC 1 power-up control

System clock (test only)

PLL clock (test only)

DIs

AO

AI

PLL loop filter capacitor

SHLIC 1 Rx analog signal

SHLIC 1 Tx analog signal

Analog supply voltage

Tx[1]

V

DD3A

P

VAG

Analog ground reference voltage output

Analog ground (0 V)

AO

P

V

SSA

DCO[1]

DCC[1]

DCO[0]

DCC[0]

Tx[0]

SHLIC 1 DC loop output

SHLIC 1 DC loop control

SHLIC 0 DC loop output

SHLIC 0 DC loop control

SHLIC 0 Tx analog signal

AI

AO

AI

AO

AI

3-2

MS140131KT

Pin Descriptions: MC1420232 Pin Descriptions

Table 3-1. Pin Descriptions for MC1420232 CODSP (continued)

Type

Pin Name Pin No.

Rx[0]

Pin Description

SHLIC 0 Rx analog signal

(See Note)

33

34

35

36

37

38

39

40

41

42

43

44

AO

Z

Digital I/O drive control (test only)

Test mode select (test only)

SHLIC 0 test select

DB

out

TEST

TST[0]

BR[0]

DId

DO

SHLIC 0 bat reverse control

SHLIC 0 ring control

DO

RNG[0]

PU[0]

DO

SHLIC 0 power-up control

SPI port data in (user I/O)

SPI port chip-select (user I/O)

SPI port clock (user I/O)

SPI port data out (user I/O)

Reset input

DB

SPIDI

DB

SPICS

SPICK

SPIDO

PWRS

DB

DIs

NOTE: The first letter differentiates between:

D: Digital

A: Analog

P: Power

The second letter differentiates between:

I: Input

O: Output

B: Bidirectional

The third letter differentiates between:

d: Pin with internal pull-down

u: Pin with internal pull-up

s: Pin with Schmitt-trigger input

5: 5 V compatible input

NC: No connect

MS140131KT

3-3

Pin Descriptions: MC1430132 Pin Descriptions

ꢉꢄꢉ 0&ꢃꢆꢉꢈꢃꢉꢇꢀ3,1ꢀ'(6&5,37,216

Table 3-2. Pin Descriptions for MC1430132 SHLIC

Pin Name Pin No.

Pin Description

Type

P

V

1

Battery ground (0 V)

B wire output

SSB

BW

BAT

BATS

BATR

PU

2

AB

P

3

Battery voltage (output, do not connect)

Battery voltage input, SPEECH mode

Battery voltage input, RING mode

Power-up control

4

P

5

P

6

DI

NC

DI

P

NC

7

Do not connect; thermal conduction pin

Ring mode control

NC

8

RNG

BR

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Battery reverse control

TST

VAG

Test mode control

Analog ground reference input

Analog supply voltage

V

P

DD5A

V

Analog ground, 0 V

P

SSA

V

3 V regulator output

P

DD3

DCLF2

DCLF1

Rx

DC bias filter capacitor 2

DC bias filter capacitor 1

Analog receive signal

AO

AI

Tx

Analog transmit signal

DCC

NC

DC loop control input

DI

NC

AI

Do not connect; thermal conduction pin

DC loop control separation filter input

DC loop control output

NC

DCI

DCO

SSB

SB

AO

AI

Loop test resistor switch

B wire sense input

AI

SA

A wire sense input

AI

AW

A wire output

AB

NOTES: 1. A ±1% results in a maximum longitudinal balance of 40 dB. For higher values, more precise

matching is required (e.g., ±0.1% for 46 dB).

2. Capacitors are generally not required. They are foreseen to stabilize the line driver outputs when

active but driving no load (test condition only).

3-4

MS140131KT

Pin Descriptions: Unused Pins

ꢉꢄꢆ 8186('ꢀ3,16

ꢉꢄꢆꢄꢃ &2'63

Table 3-3 lists the pins on the CODSP that are not connected. Pins that are not used in the application

should be connected as described here. Failure to do so could result in excessive sensitivity to RFI or other

erratic behavior. A 0 or 1 indicates that the pin should be connected to ground or to the device’s digital

supply. A “—” indicates that the pin is an output and must be left unconnected.

Table 3-3. MC1420232 CODSP

Unused Pin Connections

Pin Name

SPDO

GCIM

AD0

Pin No.

43

15

14

13

12

4

Connect To

—

0, 1 (GCI mode select)

0, 1 (GCI timeslot select)

AD1

AD2

JTDI

1 (V

)

DD3D

JTDO

JTCK

JTMS

JTRS

SCLK

PLLCK

1

—

2

1 (V

)

DD3D

3

DD3D

5

0 (V

)

SS

20

21

34

35

V

SS

Z

out

TEST

ꢉꢄꢆꢄꢇ 6+/,&

Table 3-4 lists the pins on the SHLIC that are not connected. The NC pins (7, 8, 21, and 22) are connected

to the device substrate, which is at a voltage equal to the V

electrically connected to this pin.

supply pin, and may optionally be

BATR

The BAT pin is the internal supply to the line drivers, and adopts the voltage of V

BATR

or V

, plus

BATS

the voltage drop across the internal switch, depending on the operating mode. In low-voltage only systems

(very short connections), the BAT pins, V and V , may all be connected together and a single

BATR

BATS

supply (e.g., –27 V) may be used for both ringing and speech modes. (In this mode, the voltage drop of the

internal switches is avoided.)

MS140131KT

3-5

Pin Descriptions: Note on Decoupling

Table 3-4. MC1430132 SHLIC

Unused Pin Connections

Pin Name

BAT

NC

Pin No.

Connect To

3

7

No connect or see text above

NC

8

NC

21

22

NC

ꢉꢄꢊ 127(ꢀ21ꢀ'(&283/,1*

As in any system, the PCB layout and supply decoupling can influence the system performance,

particularly with respect to noise.

ꢉꢄꢊꢄꢃ &2'63ꢀ'HFRXSOLQJ

•

It is recommended to connect V

configuration from the supply (either from the SHLIC or from an external supply), and each pin be

independently decoupled using 10 µF in parallel with 100 nF.

and V

(digital and analog supply pins) in a star

DD3A

DD3D

In two-line systems, using the SHLIC regulator to supply only the CODSP (i.e., no other use is

made of the regulator), one SHLIC may be used to provide V

power and the other V

,

DD3D

thus giving improved decoupling between analog and digital supplies. See Figure 3-2.

DD3A

The VAG line (analog signal reference) must always be properly decoupled using 100 nF, placed

as close as possible to the CODSP device.

ꢉꢄꢊꢄꢇ 6+/,&ꢀ'HFRXSOLQJ

•

The SHLIC should use separate 100 nF decoupling capacitors between V

DD5A

and V

, and

SSB

. When the on-board regulator of the SHLIC is not used, no capacitor is

V

and V

DD5A

SSA

DD3

required at the V

pin.

3-6

MS140131KT

Pin Descriptions: Note on Decoupling

MC1430132

SHLIC

V

DD3A

DD3

MC1420132

V

100 nF

CERAMIC

10 µF T

SSB

A

CODSP

V

SSA

V

SSA

100 nF

CERAMIC

GROUND

STAR-POINT

VAG

V

SSD

SSA

V

SSB

100 nF

CERAMIC

MC1430132

SHLIC

10 µF T

A

V

DD3D

DD3

(a) Arrangement A

+3.3 V STAR POINT

MC1430132

SHLIC

V

DD3A

MC1420132

CODSP

V

100 nF

CERAMIC

SSB

10 µF T

A

V

SSA

V

SSA

100 nF

CERAMIC

GROUND

STAR-POINT

VAG

V

SSD

SSA

V

100 nF

CERAMIC

SSB

10 µF T

A

MC1430132

SHLIC

V

DD3D

(b) Arrangement B

Figure 3-2. MC1420232 CODSP Recommended Power-Supply

Decoupling Arrangements

MS140131KT

3-7

6(&7,21ꢀꢆ

)81&7,21$/ꢀ&+$5$&7(5,67,&6ꢀ2)ꢀ7+(ꢀ

6+ꢁ3276ꢀ6<67(0

For reference, Figure 4-1 shows the typical voltages on tip and ring during various stages of operation. For

detailed electrical parameters, refer to Section 5.

(SATURATION, <0.5 V)

(BIAS, 3 V)

0 V

V

BATS

(e.g., –24 V)

(BIAS, 3 V + DROP

OF BAT SWITCH)

(AVG. DC = V

BATR

/2)

(BIAS, 3 V + DROP OF BAT SWITCH)

V

BATR

(e.g., –64 V)

ON-HOOK

ON-HOOK ADSI

RING BURST

OFF-HOOK

Figure 4-1. SH-POTS Line Voltages — Example

ꢆꢄꢃ 21ꢁ+22.ꢀ&21',7,216

When a line is not in use (on-hook), the designer may select either the speech battery or the ringing battery

as the supply to the line drivers. In the on-hook mode, most of the internal circuits are put into a low-power

operating mode to minimize supply currents. The A and B wire outputs are effectively connected to the

supply voltage, thus applying this voltage (minus a small saturation voltage) to the line. The output is

current-limited in this mode, thus protecting against short circuits and limiting any inrush current when a

set goes off-hook. If the SHLIC detects a current in excess of a (programmable) limit, the off-hook

MS140131KT

4-1

Functional Characteristics of the SH-POTS System: On-Hook Conditions

condition will be detected (an on-chip debouncer with selectable delay avoids accidental hookswitch

detection), and the circuit will be put into active speech mode. The nominal off-hook detection currents

and hysteresis are shown in Figure 4-2. When a line is in the on-hook condition, the system designer may

select, under program control via the GCI bus, an “on-hook active mode,” whereby, on-hook signalling

(ADSI, CLIP, etc.) can be performed in either direction (though battery reversal is not available in this

mode).

The hookswitch detector has a programmable debounce timer. Times of 8, 16, 24, or 64 ms can be selected.

(The timer is common for both channels.)

OFF-HOOK

ON-HOOK

LINE CURRENT

(mA)

6.3

10.0

Figure 4-2. Nominal Hookswitch

Detection Thresholds (Default Values)

Table 4-1. On-Hook Characteristics

Parameter

Condition

Min

Max

Unit Note

V

Open-line feed voltage

V

1

2

3

feedO

BATS-1

BATR-1

I

Line current guaranteeing on-hook state

Line current guaranteeing off-hook state

Hookswitch detect hysteresis

4.67

7.93

mA

V

on

off

I

7.86

2

12.14

—

I

OHYST

I

Peak over-current limit, on-hook mode

—

2

145

4

OC

V

Bias voltage during ADSI mode on A (H) and B (L) wires,

ref. BAT pin

biasH

biasL

NOTES: 1. I

= 0 mA, independent of battery reversal mode. This voltage is selected by the user. The output

line

impedance when in the on-hook condition is set by the sense resistors R

. The hook-switch detector

feed

has a programmable debounce timer. Times of 8, 16, 24, or 64 ms can be selected (common for both

channels).

2. These are the default values after reset. The on-hook and off-hook thresholds can be individually

programmed in the range 0 to 63 mA nominal.

3. This is the intrinsic current limit of the output driver. This current can only be seen during on-hook to

off-hook transients, or during ringing into a short-circuit load during the ring-trip delay period. The actual

value measured will depend on the load resistance used.

4-2

MS140131KT

Functional Characteristics of the SH-POTS System: Ringing Injection

ꢆꢄꢇ 5,1*,1*ꢀ,1-(&7,21

ꢆꢄꢇꢄꢃ %DODQFHGꢀ5LQJLQJ

The SH-POTS chipset is capable of directly injecting a ringing signal of up to 50 Vrms (sine wave) without

the need for additional external components. The technique of “balanced ringing” is used, which allows

this large voltage swing to remain within the technology limits of the SHLIC device. (Balanced ringing

requires a specific algorithm for ring-trip detection, which is also implemented by the chipset.) The

SH-POTS chipset allows the user to program a dc offset during ringing as well as a reduced amplitude

ringing signal, should the application require this. Ringing waveform, frequency, amplitude, and cadence,

as well as ring-trip thresholds, are controlled by the CODSP device, and are all programmable. Ringing

cadence can be automatic, with independently programmable ring and pause times, or ringing can be

controlled directly via the GCI bus. In the automatic cadence mode, ringing bursts on both channels can be

optionally interleaved, if simultaneously active, to avoid peaks in current from the ringing battery supply.

Table 4-2. Ringing Characteristics

Parameter

Condition

Min

Max

Unit Note

F

Ringing frequency

16.66, 20, 25 Hz

50 Hz

Hz

R

–1

–2

1

2

SF

V

Single-frequency noise, 10 Hz to 4 kHz

Ringing voltage (max), V = –72 V

—

50

—

0

–63

—

dBm

NR

Vrms

%

1

R

BATR

D

Ringing distortion, sine mode 30 Hz to 132 kHz

Ring-trip delay, load = 500 Ω + 4 µF

Ring-trip debounce time

5

R

t

150

30

ms

RTD

t

ms

2

4

3

RTDEB

t

Ring-cadence times (active and silent)

Ring-trip current, high threshold

Ring-trip current, low threshold

Ring-trip hysteresis

1

255

12.0

9.5

—

n/n

mA

C

I

6.0

3.5

2

RTH

I

RTL

H

RT

NOTES: 1. Ringing voltage is user-programmable from 0 to 70 Vp(diff) between the A and B wires (NB, the ringing

battery voltage must be large enough to encompass this voltage) in 256 steps. The default is the

maximum value. Condition: Load = 0 mA.

2. User-selectable 0 or 30 ms. Default is 30 ms.

3. These are the default values after reset. The max and min ring-trip thresholds can be individually

programmed in the range 0 to 63 mA nominal. The ring-trip detect mask time is used to bridge the

zero-crossings of the ringing signal, and is programmable between 0 and 32 ms in 125 µs steps.

4. Units are periods of the selected ringing frequency. The default values are 1 s on, 3 s off, with a ringing

frequency of 50 Hz.

ꢆꢄꢇꢄꢇ 6HPLꢁ8QEDODQFHGꢀ5LQJLQJ

In order to support “semi-unbalanced ringing” (dc bias equal to V

BATR

superimposed on the differential

ringing signal), two of these outputs will be active high during the active ringing period on each channel

(SPICK for channel 0 and SPICS for channel 1). This can be used to drive a relay via an external NPN

transistor, as shown in Figure 4-3.

MS140131KT

4-3

Functional Characteristics of the SH-POTS System: DC Feed Characteristics

PROTECTION

R

feed

AW

BW

LINE

NC

R

feed

RLY

47 µF

+5 V

V

BATR

RLY

SPICK

(LINE 0)

OR

SPICS

(LINE 1)

Figure 4-3. Application Suggestion for Semi-Unbalanced Ringing Injection

ꢆꢄꢉ '&ꢀ)(('ꢀ&+$5$&7(5,67,&6

As shown in Figure 4-4, the SH-POTS chipset implements a constant-current feed. The limit current and

the residual resistance (slope of the characteristic) are both programmable by the user. The dc

characteristic falls into three regions. When the combination of line and subset result in a current less than

the programmed limit current, the system behaves like a battery with a fixed feed resistance of 120 Ω, and

a voltage equivalent to the speech supply voltage (V

) minus the bias voltage on both lines (6 V

BATS

nominal in total). Should line conditions permit a current that exceeds the programmed limit current, the

system enters the constant-current feed mode described above. In order to protect the output stage in the

transition region at higher line currents (in excess of 50 mA), a third region is defined, where the system

synthesizes a fixed feed resistance of 200 Ω. The slope of the voltage/current characteristic in the

constant-current mode can be user-programmed to select the effective feed-resistance.

127(

The SHLIC device includes over-temperature protection, that

activates at 165°C in case of overheating of the device.

4-4

MS140131KT

Functional Characteristics of the SH-POTS System: DC Feed Characteristics

I

line

(mA)

80

R

feed

= 200 Ω

(PROGRAMMABLE)

R

feed

R

= 120 Ω

feed

60

40

20

V

(V)

line

V

FN BATS

Figure 4-4. DC Feed Characteristics

Table 4-3. DC Feed Characteristics

[R

= 60 Ω Total (50 Ω +10 Ω Protection) x 2]

feed

Parameter

Condition

Min

2.5

–15

20

Max

3.5

15

Unit

V

Bias voltage, A wire (I

Bias voltage, B wire (I

= 0)

biasH

line

V

biasL

TOL

Current limit tolerance

%

ICL

RfeedCL

T

Tolerance on programmed R

when in current-limit

15

%

feed

I

Current-limit, useful programmed range

70

mA

CL

ꢆꢄꢉꢄꢃ %DWWHU\ꢀ9ROWDJHꢀDQGꢀ5HYHUVDO

The open-line voltage (i.e., the voltage seen on the line when on-hook) is user-selectable for each channel

via an internal register. It can be either the ringing battery supply (most common use) or the speech battery

supply. The speech battery supply is automatically selected when an off-hook condition is detected,

independently of these control bits. The selected supply voltage is maintained when the on-hook signalling

function (ADSI) is enabled.

The polarity of the line feed can be dynamically controlled by the user. In the “normal” condition, the

A wire is the most positive. Thus, reversal makes the B wire the most positive. Battery reversal is fast

(audible), is controlled by programming an internal register, and is independent for both channels. The

selected polarity is used in all states (on-hook, off-hook, ringing, etc.) except for on-hook signalling, which

is in normal battery mode.

MS140131KT

4-5

Functional Characteristics of the SH-POTS System: AC Transmission Characteristics

(MS140131KT System)

ꢆꢄꢆ $&ꢀ75$160,66,21ꢀ&+$5$&7(5,67,&6ꢀ

ꢋ06ꢃꢆꢈꢃꢉꢃ.7ꢀ6<67(0ꢌ

ꢆꢄꢆꢄꢃ 7UDQVPLWꢀDQGꢀ5HFHLYHꢀ)LOWHUꢀ&KDUDFWHULVWLFV

The SH-POTS chipset implements transmit and receive filters according to ITU-T (G.712). These filters

can be reprogrammed by the user for specific requirements. Please contact a Motorola sales office for more

information. The implemented default filter characteristics are shown in Figures 4-5 and 4-6.

(dB)

–0.3

RECEIVE

π (4000–ƒ)

dB

12.5 1 – SIN

[

]

0.0

1200

TRANSMIT

RECEIVE / TRANSMIT

0.35

0.55

0.75

12.5

25.0

1.0

1.5

FREQUENCY

16,000

3,600

3,400

600

2,400 3,000

4,000

4,600

200 300 400

(Hz)

Figure 4-5. Transmit and Receive Frequency Response (Default)

4-6

MS140131KT

Functional Characteristics of the SH-POTS System: AC Transmission Characteristics

(MS140131KT System)

DELAY

(µs)

1800

1500

1200

900

600

300

FREQUENCY

0

(Hz)

500 600

1000

2000

2600

2800

Figure 4-6. Relative Group Delay, Transmit and Receive Paths

(Digital-to-Digital) Referred to 1 kHz

ꢆꢄꢆꢄꢇ 7UDQVPLWꢀDQGꢀ5HFHLYHꢀ*DLQ

Transmit (from analog subset towards the switching system) and receive gains are user-programmable,

independently for both lines. The default values are 0 dBr in the transmit direction, and –7 dBr in the

receive direction.

ꢆꢄꢆꢄꢉ 6RXUFHꢀ,PSHGDQFHꢀꢋ=

ꢌ

&2

The central-office impedance, Z , is synthesized using digital signal processing techniques. This renders

CO

it very stable, and moreover, programmable by the user by means of coefficients which are loaded via the

GCI. Real or complex Z

Rp, Cp; see Figure 4-7). The Z

impedances can be programmed to address the local requirements of specifications worldwide, and cover

the following range.

impedances can be synthesized using the common three-element model (Rs,

setting is common for both lines. Both real and complex Z

CO

Using the default coefficient values, the return loss when measured against 600 Ω (using 0 dBm input

signal level) is better than 20 dB in the 300 to 3400 Hz band, and better than 10 dB at 10 kHz.

Real impedances: 600 Ω to 900 Ω.

Complex impedances: Rs from 160 Ω to 500 Ω

Rp from 300 Ω to 1000 Ω

Rp//Cp pole from 725 Hz to 5 kHz.

MS140131KT

4-7

Functional Characteristics of the SH-POTS System: Metering

C

P

R

S

R

P

Figure 4-7. Three-Element Z

CO

Model

ꢆꢄꢆꢄꢆ %DODQFHꢀ,PSHGDQFHꢀꢋ(FKRꢀ&DQFHOOHUꢌ

The balance impedance (model of the line plus set impedance used to separate the receive and transmit

signals in the “hybrid”) is independently programmable (though is the same for both channels). Default

values offer echo return loss of better than 20 dB, though optimization to specific line and set

characteristics may yield further improvement.

Table 4-4. Examples of Z

Coefficients

CO

Z

Sh

Z

-

Z

-

CO

Rs

Rp

0

Cp

Alfa3

Z

A2 RZ

Gamma Alfa3

Ftx

237

52

Ap

0

Nan ACG

CO

Belgium

Germany

Europe

600

220

270

850

900

0

115 nF

150 nF

0

3

0

9

0

5

4

0

512

–179

0

103

125

123

126

820

750

0

40

19

0

9

7

0

346

388

0

15

0

122

282

290

Z

850

900

CO

0

h0

4

h1

–22

48

h2

105

1

h3

95

a0

0

c5

0

b0

0

Dzd0 Dzd1

Belgium

Germany

Europe

1

0

1

0

1

–31

3

156

88

0

–23

–22

118

105

0

Z

850

900

4

95

0

CO

4

95

0

ꢆꢄꢊ 0(7(5,1*

ꢆꢄꢊꢄꢃ 0HWHULQJꢀ,QMHFWLRQ

Metering pulses of selectable frequency (12 kHz or 16 kHz) and programmable amplitude can be injected

into either analog channel independently. The width of the injected pulse is determined by the user (on/off

mode), or by an internal timer (burst mode) which can be set by the user from 2 ms to 510 ms in steps of

2 ms. The metering signal is always a multiple of half metering periods. See Figure 4-8.

Metering is initiated on a channel by an active low state on the corresponding MPI bit in the GCI C/I byte.

4-8

MS140131KT

Functional Characteristics of the SH-POTS System: Metering

ON/OFF MODE

MPI

METERING

BURST MODE

MPI

t

Mburst

METERING

Figure 4-8. Metering Pulse Timing Diagrams

The metering level on the line is set by: V

LM

= (V

Z )/(Z + Z

GEN M

) where:

COM

M

V

= metering pulse level on the line

LM

V

= set level of the metering generator

GEN

Z

= impedance of the metering load

M

= CO impedance at the metering frequency.

COM

The metering level V

GEN

is selectable from 0 to a maximum level of 230 mVrms (500 m line with Z

900 Ω) in 15 linear steps. The internal tolerance on the metering signal level is ±10%.

=

CO

MS140131KT

4-9

Functional Characteristics of the SH-POTS System: Tone Generation

ꢆꢄꢊꢄꢇ 0HWHULQJꢀ&KDUDFWHULVWLFV

Table 4-5. Metering Characteristics (Determined by MC1420232 CODSP)

(Conditions: Refer to Section 5.2)

Parameter

Condition

Metering frequency, 12 kHz

Min

Max

Unit

Hz

Note

F

11,940

25,920

12,060

16,080

1

ML

F

Metering frequency, 16 kHz

Hz

MH

SFN1

Single-frequency noise, subharmonics

for 12 kHz, 30 Hz to 12 kHz

for 16 kHz, 30 Hz to 12 kHz

dBm0

—

–69

SFN2

Single-frequency noise, mixed products

12 kHz, 12 kHz to 20 kHz

12 kHz, 20 kHz to 132 kHz

16 kHz

dBm0

—

–51

–69

N

In-band noise due to metering signal

Transient noise due to metering pulse

—

–60

–35

0.5

dBmp

dBm0

%

2

MC

N

MT

THD

Metering total harmonic distortion, 30 Hz to 132 kHz, out

of CODSP

M

D

Metering signal distortion at load

—

5

%

3

4

M

V

Metering pulse amplitude, maximum level with

207

253

mVrms

LM

Z

= 900 Ω, R = 130 Ω

CO

line

SYM

Metering symmetry, A and B wires

24

—

dB

5

M

SFN

Single frequency noise, mixed products, 10 Hz to 4 kHz,

Tx path

–63

dBm

TX

NOTES: 1. Tolerance = ±0.5%.

2. Measured in accordance to ITU-T Specification 071 (Blue Book).

3. On 200 Ω.

4. Tolerance = ±10%.

5. Tolerance = max 6%.

ꢆꢄꢍ 721(ꢀ*(1(5$7,21

The SH-POTS system allows the injection of user programmable tones, independently per channel, for

signalling or user test purposes. Per channel, a tone comprising two programmable (sine wave) frequencies

and programmable amplitudes can be generated (in this way, the most common call-progress and

information tones, melody notes, or DTMF tones can be synthesized). The tone signal is added to the

speech signal (the user must be aware of possible clipping which may occur if high signal levels are

programmed), or the speech signal can also be muted during a tone burst. The tone burst duration is under

user control only (the control bits for mute and tone insertion occupy the same register, which simplifies

the generation of tone bursts).

The amplitude of each frequency within the tone can be independently set from 0 to the maximum level in

256 linear amplitude steps (8-bit value), with n = 63 corresponding to 0 dBm on the line. From this, the

line signal level, V , for a given gain factor n is given by:

TL

V

= 20 log(n/63) in dBm

TL

4-10

MS140131KT

Functional Characteristics of the SH-POTS System: Tone Generation

or

n = int(63 x 10^(Vtl/20) + 0.5)

Table 4-6 lists values for n, for a range of tone signal levels.

The tone frequency is given by:

Fout = 250 x N / 256 Hz,

where N is a 16-bit value (thus, N = 1024 yields a tone of 1 kHz) or

N = int(Fout x 256/250 + 0.5)

The tone generated has continuous phase if the programmed frequency is changed during the course of a

tone (this is not so if the generator is stopped and restarted). Tables 4-7 and 4-8 list the values of N required

to generate commonly occurring frequencies, and the resulting error.

Table 4-6. Tone Signal Levels (Common Values) (See Note)

dBm

3

n

Actual

3.00

Error (dB)

0.00

89

75

63

53

45

32

25

20

11

6

1.5

0

1.51

0.01

0.00

–1.5

–3

–1.50

–2.92

–5.88

–8.03

–9.97

–15.16

–20.42

–29.97

–35.99

0.00

0.08

–6

0.12

–8

–0.03

0.03

–10

–15

–20

–30

–36

–0.16

–0.42

0.03

2

1

0.01

NOTE: It is possible to generate tones of very high amplitude. The user must

ensure that the amplitude parameter is programmed before the tone is

enabled.

MS140131KT

4-11

Functional Characteristics of the SH-POTS System: Tone Generation

Table 4-7. Tone Generator Division Values for Common Frequencies

from ETS-300-001 and DTMF Tones

Common Signalling Frequencies

Frequency (Hz)

300.00

320.00

325.00

340.00

350.00

375.00

380.00

382.50

400.00

410.00

420.00

440.00

450.00

455.00

475.00

490.00

500.00

525.00

550.00

N

Actual Frequency

299.805

320.313

325.195

339.844

349.609

375.000

379.883

382.813

400.391

410.156

419.922

440.430

450.195

455.078

474.609

490.234

500.000

525.391

549.805

Error (%)

–0.07

0.10

307

328

333

348

358

384

389

392

410

420

430

451

461

466

486

502

512

538

563

0.06

–0.05

–0.11

0.00

–0.03

0.08

0.10

0.04

–0.02

0.10

0.04

0.02

–0.08

0.05

0.00

0.07

–0.04

DTMF Tones

Frequency (Hz)

697.00

N

Actual Frequency

697.266

Error (%)

0.04

714

770.00

788

769.531

–0.06

–0.05

0.04

852.00

872

851.563

941.00

964

941.406

1209.00

1336.00

1477.00

1633.00

1238

1368

1512

1672

1208.984

1335.938

1476.563

1632.813

0.00

–0.03

–0.01

4-12

MS140131KT

Functional Characteristics of the SH-POTS System: Tone Generation

Table 4-8. Required Frequency Setting Values (N) for a Melody Generator

(Western Equal-Tempered Scale)

Frequency

(Hz)

Error

(%)

Octave

Note

C

N

Actual

261.719

277.344

293.945

311.523

330.078

349.609

370.117

391.602

415.039

440.430

465.820

494.141

523.438

554.688

586.914

622.070

659.180

698.242

740.234

784.180

831.055

879.883

932.617

987.305

1046.875

1108.398

1174.805

1244.141

1318.359

1396.484

1479.492

1568.359

1661.133

1759.766

1864.258

1975.586

2092.773

2217.773

2349.609

2489.258

2

3

4

5

261.626

277.183

293.665

311.127

329.628

349.228

369.994

391.995

415.305

440.000

466.164

493.883

523.251

554.365

587.330

622.254

659.255

698.456

739.989

783.991

830.609

880.000

932.328

987.767

1046.502

1108.731

1174.659

1244.508

1318.510

1396.913

1479.978

1567.982

1661.219

1760.000

1864.655

1975.533

2093.005

2217.461

2349.318

2489.016

268

0.04

0.06

(Middle-C)

C#

D

284

301

0.10

Eb

E

319

0.13

338

0.14

F

358

0.11

F#

G

379

0.03

401

–0.10

–0.06

0.10

Ab

A

425

451

Bb

B

477

–0.07

0.05

506

C

536

0.04

C#

D

568

0.06

601

–0.07

–0.03

–0.01

–0.03

0.03

Eb

E

637

675

F

715

F#

G

758

803

0.02

Ab

A

851

0.05

901

–0.01

0.03

Bb

B

955

1011

1072

1135

1203

1274

1350

1430

1515

1606

1701

1802

1909

2023

2143

2271

2406

2549

–0.05

0.04

C

C#

D

–0.03

0.01

Eb

E

–0.03

–0.01

–0.03

0.02

F

F#

G

Ab

A

–0.01

–0.02

0.00

Bb

B

C

–0.01

0.01

C#

D

0.01

Eb

0.01

MS140131KT

4-13

Functional Characteristics of the SH-POTS System: CODSP Clock Recovery PLL

Table 4-8. Required Frequency Setting Values (N) for a Melody Generator

(Western Equal-Tempered Scale) (continued)

Frequency

(Hz)

Error

(%)

Octave

Note

E

N

Actual

5

2637.020

2793.826

2959.955

3135.963

3322.438

3520.000

3729.310

3951.066

2700

2861

3031

3211

3402

3604

3819

4046

2636.719

2793.945

2959.961

3135.742

3322.266

3519.531

3729.492

3951.172

–0.01

0.00

F

F#

G

0.00

–0.01

0.00

Ab

A

Bb

B

0.00

ꢆꢄꢎ &2'63ꢀ&/2&.ꢀ5(&29(5<ꢀ3//

The CODSP device derives its internal clocks from the GCI DCL input by means of a PLL. The PLL

automatically detects the clock mode in use, and sets the multiplication factor accordingly. The PLL loop

filter requires an external capacitor as shown in the application schematic.

ꢆꢄꢎꢄꢃ 8VHUꢁ'HILQHGꢀ,ꢂ2ꢀ3LQV

The SPIDI, SPICS, and SPICK pins are part of an SPI port which is used by the manufacturer during

product evaluation and testing. They are available to the user, via the GCI, as output bits (e.g., for driving

small indicator LEDs). The SPIDO pin is used as part of the power-up and testing routines, and the

behavior during power-up can not be guaranteed. It is, therefore, advised not to make use of this pin for

any other purpose. The outputs can source or sink a maximum of 4 mA each.

ꢆꢄꢎꢄꢇ 7HVWꢀ)XQFWLRQV

Please contact a Motorola sales office.

4-14

MS140131KT

6(&7,21ꢀꢊ

(/(&75,&$/ꢀ&+$5$&7(5,67,&6

ꢊꢄꢃ $%62/87(ꢀ0$;,080ꢀ5$7,1*6

Operation of the device at or near these conditions is not guaranteed. Sustained exposure to these limits

will adversely affect device reliability.

Table 5-1. Absolute Maximum Ratings

Parameter

Symbol

BATR

BATS

Min

–75

–35

–40

Max

0.5

Unit

V

Battery voltage BATR (ref. to V

) of SHLIC

SSB

Battery voltage BATS (ref. to V

) of SHLIC

0.5

V

SSB

Difference between the batteries BATR and BATS,

BATR-BATS of SHLIC

DBAT

0.5

V

(ref. to V

) of SHLIC

V

–0.5

–40

—

7

V

DD5A

SSA

DD5A

(ref. to V

) of SHLIC

SSA

V

0.5

85

1.3

4

SSB

Ambient temperature under bias of SHLIC

Maximum absolute power dissipation, T = 85°C

T

°C

W

V

A

V

,V

to CODSP

V

– 0.3

DD3A DD3D

DD3

SS

Voltage on any device pin (see Note) of CODSP

Function temperature under bias of CODSP

Storage temperature

V

– 0.3

V

+ 0.3

V

in

SS

DD3

–55

150

300

°C

T

stg

–65

—

Lead temperature (soldering 10 s)

NOTE: Except special 5 V tolerant I/Os of CODSP.

ꢊꢄꢇ 23(5$7,1*ꢀ&21',7,216

Operating ranges define the limits for functional operation and parametric characteristics of the device as

described in this document, and for the reliability specifications. Correct functioning outside of these limits

is not implied. Total cumulative exposure outside the normal power supply voltage range or ambient

temperature under bias, must be less than 0.1% of the normal useful life as defined in the Reliability

section.

MS140131KT

5-1

Electrical Characteristics: Thermal Shutdown SHLIC

Table 5-2. Operating Conditions

(All Voltages Referenced to V

= V

or V = V

, as Appropriate)

SSA

SSB

SS SSA

Limits

Typ

Symbol

BATR

Parameter

Ringing battery voltage

Min

–72

–35

–40

Max

–18

0

Unit

V

–65

BATS

Speech battery voltage

–32

V

D

BAT

Difference between the batteries BATR and BATS,

BATR-BATS

–35

V

Supply voltage SHLIC (ref. to V

Operating temperature range

)

SSA

4.75

–40

5

5.5

85

V

DD5A

T

—

°C

(Note)

range

V

of CODSP (3.3 V ±8%)

3.036

3.3

3.564

V

DD3D

DD3A

DD

NOTE: See Section 5.4; maximum power dissipation is dependent on maximum ambient temperature.

ꢊꢄꢉ 7+(50$/ꢀ6+87'2:1ꢀ6+/,&

Thermal limiting circuitry on chip of the SHLIC will shut down the circuit at a junction temperature of

about 165°C. The device should never be run at this temperature. Operation above 145°C junction

temperature might degrade device reliability.

Thermal resistance = 55°C/w typ.

ꢊꢄꢉꢄꢃ 7UDQVLHQWꢀ(QHUJ\ꢀ&DSDELOLW\

During testing, each device termination withstands being shorted to the supply voltages or ground as

specified below. The shorting must be limited to 1 s.

Shorted to V

to Rx

, V

SSA DD5A

or V

: VAG, PU, RNG, BR, TST, T , DCC, DCO, DCI, Tx

SSB A

Shorted to V

, V or BATS: AW, BW, SA to SB

SSA SSB

ꢊꢄꢆ '&ꢀ&+$5$&7(5,67,&6ꢀꢋ0&ꢃꢆꢉꢈꢃꢉꢇꢀ

6+/,&ꢏꢀ81/(66ꢀ27+(5:,6(ꢀ127('ꢌ

Unless otherwise stated, these characteristics apply for the operating conditions specified in Section 5.2.

All parameters are explicitly or implicitly tested during production at the operating conditions unless they

are marked with an asterisk (*), where they are guaranteed by design. Parameters marked with a double

asterisk (**) are meant as user information only. Tests are performed using an equivalent of the application

schematic.

5-2

MS140131KT

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

Table 5-3. Power Supply Currents

Limits

Symbol

Parameter

Test Condition

Power RNG = 0

Min

—

Typ

0.35

3.5

0.35

2.5

3.5

1.5

—

Max

0.5

5.0

0.5

3.5

5

Unit

mA

mW

I

BATR current (IL = 0)

BATR

Up RNG = 1

Power RNG = 0

Down RNG = 1

Power RNG = 0

Up RNG = 1

I

BATS current (IL = 0)

BATS

5

Power RNG = 0

Down RNG = 1

Power-up

2.5

0.5

5.5

4

I

V

current (I = 0)

V3

3

VDD

DD

Power-down

2.5

—

P

Power dissipation of CODSP

(@ 3.45 V V and

Power-down

30

CC

DD3A

Power-up 1 line active*

Power-up 2 lines active

—

140

180

V

)

DD3D

—

NOTES: 1. IL is the line current; i.e., these parameters are measured without line current.

2. I is the load current in pin V3.

V3

3. The maximum values in the table are valid for the full battery voltage ranges:

–18 V to –72 V for ringing battery BATR.

–18 V to –35 V for battery BATS. (BATR must always be the most negative one.)

4. In case of sleep mode activation. See Tables 6-5 and 6-7 for programming values.

Table 5-4. SHLIC Dissipation

Parameter

Maximum operating power dissipation, T = 70°C

Symbol

Value

1.2

Unit

Pmax_op

W

A

The specifications for power dissipation imply that in ring mode, the active ring phase must at least be four

times shorter than the non-active ring phase. The maximum duration of the active ring phase must be

below 2 s.

ꢊꢄꢆꢄꢃ 3RZHUꢁ2Qꢀ5HVHW

Table 5-5 shows the power reset threshold for V

DD5A

of the SHLIC. As long as V

reset threshold, SHLIC is held in power-down, and the output pins AW and BW are high impedance.

is below the

DD5A

The CODSP uses a separate input pin, PWRS, for system reset at power-up.

MS140131KT

5-3

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

Table 5-5. Power-On Reset Characteristics

Limits

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

V

Threshold voltage for power

3.0

3.5

4.0

V

DDPWR

reset on V

of SHLIC

DD

t

Active low pulse width on

PWRS of CODSP

10

—

ms

V

PWRS

V

Threshold voltage for reset

on PWRS of CODSP

1.6

1.7

PWRS

ꢊꢄꢆꢄꢇ 9

ꢀ5HJXODWRU

''ꢉ

This series regulator of the SHLIC can be used to provide the supply voltage for the CODSP or other 3.3 V

devices.

Table 5-6. V

DD3

Regulator Characteristics

Limits

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

V

output voltage

Load current I

0 and 50 mA

between

V3V

3.05

3.3

3.55

V

DD3

I

Load current range

0

—

50

—

mA

dB

load

PSRR

Signal rejection V

to V

DD3

Frequency range 0 to

10 kHz

20

DD

L

Load regulation

Load current range from

5 to 50 mA

–1

—

70

—

100

—

1

Ω

REG

C

(**) Maximum load capacitance

Load current range from

0 to 50 mA

—

nF

mA

load

I

(*)

CC

Current limitation shorted

output

V

shorted to V

200

DD3

SSA

5-4

MS140131KT

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

Table 5-7. Voltage Characteristics A Wire (AW), B Wire (BW)

Test Condition

Limits

Typ

Symbol

Parameter

PU

BR

RNG

Min

Max

Unit

V

Normal DC-bias on AW

1

0

1

0

1

–3.5

–3.1

–2.7

V

AWN

(ref. V

)

SSB

V

Normal DC-bias on BW

(ref. BAT)

1

0

1

0

1

x

0

2.5

–3.5

–4

3

3.5

–2.7

–2

V

BWN

V

AWR

Reverse polarity DC-bias on

AW (ref. BAT)

V

Reverse polarity DC-bias on

–3.1

–3

BWR

BW (ref. V

)

SSB

DC bias on AW in Act_H

mode (TST = 1, ref. V

V

AW_H

BW_H

HWPD

)

SSB

V

DC bias on BW in Act_H

mode (TST = 1, ref. BAT)

2

3

4

V

Voltage level high wire

(IL < 5 mA)

–0.8

—

–0.5

0.5

BAT/2

—

V

Voltage level low wire

(IL < 5 mA), ref. BAT

0.8

LWPD

V

DC-level both wires in ringing

mode (TST = 0)

BAT/2

–2%

BAT/2

2%

AWring

BWring

NOTE: These bias values are only valid if both DCC and Rx are biased at VAG voltage level.

Table 5-8. Impedance Characteristics A Wire (AW), B Wire (BW)

Limits

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Z

Output impedance at AW

(BW) (power-up)

0 mA < IL < 70 mA

0 < f < 16 kHz

—

1.5

Ω

A(B)WO

(*)

Z

Tracking of the output

impedance on AW and BW

0 mA < IL < 70 mA

0 < f < 16 kHz

—

5

—

0.3

130

70

Ω

A-BWO

(*)

Z

Output impedance on high

wire (power-down)

PU = 0

HWOD

Z

Output impedance on low wire PU = 0

(power-down)

5

LWOD

Z

Matching output impedance

low versus high wire

(power-down)

PU = 0

–70

OMD

I

Output current in and out

AW (BW) with OT (over-

temperature) detected

A(B)W_V

and A(B)W_BATS

–700

—

700

µA

A(B)OC

SSB

I

A(B)HIMP

MS140131KT

5-5

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

Table 5-9. Rx, Tx Characteristics

Limits

Symbol

(*)

Parameter

Test Condition

f = 1 kHz

SA shorted to AW and SB to

Min

—

Typ

—

0

Max

10

Unit

Ω

Z

Output impedance at Tx

Tx

V

OTx

Offset voltage on Tx (PU=1)

(ref. VAG)

–20

20

mV

BW, DCI to V

VAG

, DCO to

DD3

I

Tx output current capability

–1

—

0.05

1

mA

V

OUTTx

(*)

V

Rx input voltage range (ref.

VAG)

Rx

Z

Rx input impedance

f = 1 kHz

20

—

kΩ

Rx

ꢊꢄꢆꢄꢉ '&2ꢀ'&ꢀ/HYHOVꢏꢀ,PSHGDQFHV

These limits are generally transparent to the user, but are given here for information.

Table 5-10. DCO Characteristics

Limits

Symbol

(*)

Parameter

Test Condition

Min

—

Typ

—

0

Max

10

Unit

Ω

Z

Output impedance at DCO

DCO

V

Offset voltage on DCO

(ref. VAG)

SA shorted to AW and SB

to BW

–20

20

mV

ODCO

I

DCO output current capability

–1

—

0.05

—

mA

OUTDCO

(*)

Z

Input impedance at DCI

f = 1kHz

210

kΩ

DCI

ꢊꢄꢆꢄꢆ 9$*ꢀ$QDORJꢀ*URXQGꢀ,QSXW

The analog ground is typically half the voltage of the V

analog interfacing between SHLIC and the CODSP. VAG is provided by the CODSP.

output voltage. It is the reference for all

DD3

Table 5-11. VAG Characteristics

Limits

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

V

(**) Voltage level at VAG pin

CODSP

1.53

1.65

1.77

V

VAG

I

VAG input current SHLIC

VAG = 1.65 V

—

0.5

mA

VAG

5-6

MS140131KT

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

ꢊꢄꢆꢄꢊ '&ꢀ/RRSꢀ)LOWHU

These limits are generally transparent to the user, but are given here for information.

Table 5-12. DC Loop Filter Characteristics

Limits

Symbol

Parameter

Test Condition

RNG = 0, PU = 1

Min

Typ

Max

Unit

V

DCLF1 output voltage

–3.5

–3.1

–2.7

V

DCLF1

(ref. V

)

SSB

V

DCLF2 output voltage

(ref. BAT)

RNG = 0, PU = 1

2.5

0.6

3.0

1

3.5

1.4

V

DCLF2

Z

Output impedance at DCLF,

MΩ

DCLF1S

DCLF2S

V

– V

< 0.5 V

DCLF

Output impedance at DCLF,

– V < 0.5 V

DCLF1

1

V

DCLF2

DCLF

ꢊꢄꢆꢄꢍ '&&ꢀ,QSXWꢀ3LQ

These limits are generally transparent to the user, but are given here for information.

Table 5-13. DCC Input Characteristics

Limits

Symbol

Parameter

Test Condition

RNG = 0, PU = 1

Min

Typ

Max

Unit

V

DCC input voltage range

(ref. VAG)

–1

—

1

V

DCC

I

DCC input current,

RNG = 0, PU = 1

—

4

10

µA

INDCC

V

DCC

= VAG + 1 V

NOTE: Forcing DCC positive (ref. VAG) will result in a smaller voltage between the A and B wire. If too large of a

signal is applied at DCC, both wires are clamped at the same voltage (only a small residual voltage remains

on the line).

MS140131KT

5-7

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

ꢊꢄꢆꢄꢎ &KDUDFWHULVWLFVꢀIRUꢀWKHꢀ'LJLWDOꢀ,ꢂ2ꢀ3LQV

These include CODSP, plus TST, PU, BR, RNG of SHLIC.

Table 5-14. Digital I/O Characteristics

Limits

Symbol

Parameter

Low-level input voltage

High-level input voltage

Test Condition

Min

—

Typ

—

Max

0.8

—

Unit

V

IL

IH

IL

V

2.0

–1

—

V

I

Low-level input current

(except PU, see RPD below)

V

= 5.25 V

—

1

µA

DD

I

High-level input current

(except PU, see RPD below)

–1

—

1

µA

IH

DD

C

(*) Input capacitance

—

7

pF

INP

R

Pull-down resistance at

pin PU

18

30

40

kΩ

PD

V

OL

Output level PU pin, driven

low

Over-temperature OT

activated, I = 0.2 mA,

tested at high temperature

only

—

0.5

V

PU

V

Low-level input voltage,

CODSP

—

2.3

—

0.5

—

V

IL

V

High-level input voltage,

CODSP

IH

V

Low-level output voltage,

CODSP

0.4

—

V

OL

V

OH

High-level output voltage,

CODSP

2.3

—

V

C

Input pin capacitance,

CODSP

1

pF

in

C

Load capacitance, CODSP

—

100

out

Table 5-15. Sense Bridge Inputs Characteristics

Limits

Typ

Symbol

Parameter

Test Condition

Min

Max

Unit

R

Bridge resistance from

AW to SB

V

, VAG = 0 V, 25°C

205

257

309

kΩ

AW-SB

SA-BW

DD

R

Bridge resistance from

BW to SA

, VAG = 0 V, 25°C

205

257

309

kΩ

DD

5-8

MS140131KT

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

ꢊꢄꢆꢄꢐ 7HVWꢀ6ZLWFK

The internal test switch is between pins SB and SSB. Connecting an external load between SSB and SA

allows test of the transmission characteristics in (simulated) off- and on-hook conditions. The typical

on-resistance of the test switch is around 75 Ω, and has to be taken into account when defining the external

load. The test switch is on when RNG = 0, PU = 1, TST = 1, BR = 0.

Table 5-16. Test Switch Characteristics

Limits

Symbol

Parameter

Test Condition

– VSB| < 72 V

Min

—

4

Typ

—

Max

Unit

µA

V

I

Switch leakage current

Voltage drop over test switch

|V

SSB

5

9

3

SWoff

V

I

= 80 mA

—

SWon

SW

I

= 20 mA

– VSB > 0 V)

1

—

V

(V

SSB

NOTE: The test switch is normally off when V

is below the reset level. If the battery voltages are sufficient, the

DD

switch remains on, if it was on before V

went below the reset level.

DD

ꢊꢄꢆꢄꢑ %DWWHU\ꢀ6ZLWFK

This switch is activated during ringing or when the higher on-hook voltage is selected (RNG = 1). When

active, BATR is connected to the internal battery supply line V . In other cases (RNG = 0), the switch is

BAT

open; V

is now connected to BATS via an internal diode.

BAT

Table 5-17. Ringing Battery Switch Characteristics

Limits

Symbol

Parameter

Test Condition

BATR = –72 V,

Min

Typ

Max

Unit

I

Leakage current battery

switch

—

5

µA

BSWoff

(*)

BATS = –32 V

(RNG = 0)

I

Reverse current BATS diode

(RNG = 1)

BATR = –72 V,

BATS = –32 V

—

5

µA

REVBATS

(*)

V

Forward drop BATS diode

Load current < 80 mA

—

0

0.85

—

1.2

80

V

DRBATS

I

Current capability battery

switch

mA

BSon

V

Voltage drop over battery

switch (RNG = 1)

Load current < 80 mA

—

1

2

V

BSWon

MS140131KT

5-9

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

ꢊꢄꢊ $&ꢀ&+$5$&7(5,67,&6ꢀꢋ6+/,&ꢌ

Unless otherwise stated, the characteristic limits apply over the operating conditions specified in

Section 5.2 and each combination of the drive bits.

All parameters are specified in the presence of a longitudinal current of max 5 mA and a dc current of

between 0 mA and the current limit. The behavior of the chip in the presence of longitudinal voltages is not

tested in production.

The different gains in the signal paths are shown in Figure 5-1. The values of the gains are given in

Table 5-18.

AW

bias

AW

R

RB

PROT

+

Rx

G2

G3

GR

–

V

VL

ZL

AB

DCC

G4

+

I/O TO ADSP

(REF. VAG)

BW

R

PROT

BW

bias

G1

G5

Tx

SENSE

BRIDGE

DCO

Figure 5-1. Block Diagram Showing Gains in

Various Signal Paths in SHLIC

Table 5-18. Typical Gains

Gain

G1

Factor

1.66

0.079

2

G1′

G2

G3

–2

G4

15

G5

–1/8

1

GR

GR′

35/2

5-10

MS140131KT

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

The gains in Table 5-18 are not tested. They are mentioned for information only. The pin-to-pin gains in

Table 5-20 (G , G , etc.) are tested and guaranteed. In case of ringing, the receive gain is changed

RX TX

from GR to GR′, the transmit gain factor G1 is changed to G1′.

The default test condition of the input bits is: PU = 1, RNG = 0, BR = 0/1. DCC is shorted to VAG.

NOTE

0 dBm: 1 mW in 600 ohms.

ꢊꢄꢊꢄꢃ 5HFHLYHꢀ3DWK

The following equation is valid for an open loop configuration. This does not incorporate the Z

synthesis, which is defined by the feedback from Tx to Rx. This function is performed in the CODSP.

CO

VAB

VRX

=

= GR(G3 – G2)

GRX

ꢊꢄꢊꢄꢇ 7UDQVPLWꢀ3DWK

The following equation is valid under open loop conditions.

Vx 2RB

VL ZL

=

G1

GRX

ꢊꢄꢊꢄꢉ 2YHUSRZHUꢀDQGꢀ6KRUWꢀ&LUFXLWꢀ3URWHFWLRQ

In power-down, the DC-loop current limitation is not active. The line current is limited directly through the

line drivers.

The AW and BW outputs are fully protected against short circuits to a voltage between V

BATR (see Figure 5-2).

/V and

SSA SSB

The current flowing from (or into) AW and/or BW is limited to a value I /I

as long as the junction

for different conditions

LW HW

temperature T < 165°C (electronic current limitation). The values for I /I

J

LW HW

are given in the table below. If T rises above 165°C (±15%) the output drivers’ outputs are made high

J

impedance. Current can only flow in or out of the internal protection diodes, in case V

and/or V

SA

SB

exceeds the range between V and BATR. The currents should, however, be limited externally (internal

SS

clamping diodes protection) (see Section 2.2).

MS140131KT

5-11

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

RS1 = RS2 ≥ 0.3 Ω

V

SSB

RS1

AW

BATR

V

AW

V

SSB

RS2

BW

–

+

V

BW

V

BATR

V

SB

SA

V

SSB

Figure 5-2. Short Circuit Protection

Table 5-19. Short Circuit Protection Characteristics

Limits

Symbol

Parameter

Test Condition

PU = 1

Min

Typ

Max

Unit

I

Short circuit peak current,

power-up, sink current

–145

–120

–95

mA

LW

Short circuit peak current,

power-down, sink current

PU = 0

PU = 1

PU = 0

–65

95

–45

120

45

–20

145

65

mA

I

Short circuit peak current,

power-up, source current

HW

Short circuit peak current,

power-down, source current

20

5-12

MS140131KT

Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)

ꢊꢄꢍ 2))ꢁ+22.ꢀ&+$5$&7(5,67,&6ꢀ

ꢋ06ꢃꢆꢈꢃꢉꢃ.7ꢀ6<67(0ꢌ

Table 5-20. Off-Hook Characteristics (MS140131KT System)

(Conditions: Refer to Section 5.2)

Parameter

Condition

Min

Max

Unit Note

G

Relative gain, transmit direction

Gain programming step

Step accuracy

–6

—

1

dB

1

TX

0.25

0.1

0.5

Gain tolerance (ref. programmed value)

–0.5

G

RX

Relative gain, receive direction

Gain programming step

Step accuracy

–12

—

1

dB

1

0.25

0.05

0.5

Gain tolerance (ref. programmed value)

–0.5

d

Long-term gain stability

–0.5

0.5

dB

2

3

GLT

G

Gain tracking, Tx path

3 to –40 dBm0

–40 to –50 dBm0

–50 to –55 dBm0

TTX

–0.3

–0.6

–1.6

0.3

0.6

1.6

G

TRX

Gain tracking, Rx path

3 to –40 dBm0

–40 to –50 dBm0

–50 to –55 dBm0

dB

3

–0.3

–0.6

–1.6

0.3

0.6

1.6

IMD

Intermodulation distortion, Tx path

Intermodulation distortion, Rx path

—

–45

–50

dBm0

dB

4

5

TX

RX

S

DTX

Signal to total distortion ratio, Tx (gain = 0 dB)

0 to –10 dBm0

–20 dBm0

–30 dBm0

–40 dBm0

–45 dBm0

35

—

34.7

32.9

24.9

19.9

S

Signal to total distortion ratio, Rx (gain = –7 dB)

dB

5

DRX

0 to –10 dBm0

–20 dBm0

–30 dBm0

–40 dBm0

–45 dBm0

35

—

33.8

28.8

19.5

14.5

SFN

RX

Single frequency noise

300 to 3400 Hz, all out-of-band frequencies

700 to 1100 Hz in-band 300 to 3400 Hz

dB

—

–40

–49

Longitudinal balance

Resistor matching

1%

40

46

dB

0.1%

NOTES: 1. User programmable.

2. Covers variations within the permitted ranges of supply voltage and temperature during any one year.

3. Referred to the gain at 1020 Hz applied to the input at a level –10 dBm0.

4. Intermodulation distortion measured for all intermodulation products of any non-harmonically related

frequencies in the range 300 to 3400 Hz for levels between –4 and –21 dBm0.

5. Intermodulation distortion measured for all intermodulation products of a frequency in the range 300 to

3400 Hz at –9 dBm0 and 50 Hz at –23 dBm0.

MS140131KT

5-13

6(&7,21ꢀꢍ

'(7$,/('ꢀ352*5$00,1*ꢀ'(6&5,37,21

ꢍꢄꢃ *&,ꢀ,17(5)$&(

The SH-POTS system uses the GCI standard interface to exchange B channel data (PCM-coded voice) and

control information with the controlling system. GCI data is exchanged in both directions (downstream,

towards the analog line; and upstream, from the analog line) in 4-byte frames at a rate of 8000 frames per

second (the standard PCM sampling rate). See Figure 6-1.

Voice information or data is transmitted via “bearer” channels B1 and B2. Real-time signalling information

for the two channels are communicated via the six C/I bits (the two least significant bits of the C/I byte are

used to manage communication via the monitor channel). Programming and status information is

communicated by means of commands over the monitor channel.

SH-POTS GCI INTERFACE: MODES

1 TIMESLOT

C/I

B1

3

MONITOR

B2

D

/

out

7

6

5

4

2

1

0

7

6

5

4

3

2

A

E

in

FSC

DCL

8 kHz GCI FRAME CLOCK

SINGLE TIMESLOT MODE : FSC = 8 kHz

DCL = 512 kHz ; DATA RATE = 256 kbps

D

/

out

TIMESLOT 1

TIMESLOT 2

TIMESLOT 8

D

in

FSC

DCL

8 kHz GCI FRAME CLOCK

MULTIPLEXED TIMESLOT MODE : FSC = 8 kHz

DCL = 4096 kHz ; DATA RATE = 2048 kbps

SH-POTS GCI INTERFACE: TIMING

Figure 6-1. GCI Data Exchange

MS140131KT

6-1

Detailed Programming Description: Timeslot Address

ꢍꢄꢇ 7,0(6/27ꢀ$''5(66

Frames can be formatted singly (four bytes per frame), or in a multiplexed mode whereby up to eight

GCI-compatible devices can be connected to the same bus. In the multiplexed mode, the frames of four

bytes are transmitted in one of eight timeslots — the mode and the timeslot address of a particular GCI

terminal is set by means of strapping a code on three device pins GCIM and AD0 to AD2 on the CODSP

(see Table 6-1). The CODSP uses the GCI standard format for analog terminals (see Figure 6-2).

Table 6-1. GCI Mode and Timeslot Address Programming

DCL

Timeslot

Mode

Frequency

(kHz)

Timeslot

Address

GCIM

AD2

0

AD1

0

AD0

0

1

3

4

8

512

0

1

2

0

1

2

3

0

1

2

3

4

5

6

7

0

1

1536

2048

4096

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6-2

MS140131KT

Detailed Programming Description: Timeslot Address

ꢍꢄꢉ 6+ꢁ3276ꢀ*&,ꢀ,17(5)$&(ꢅꢀ7,0,1*

t

F

t

WH

t

WL

R

DCL

FSC

t

HF

SF

t

WFL

WFH

t

DDF

D

out

t

DDC

D

in

t

HD

SD

Figure 6-2. GCI Timing Diagram

Table 6-2. GCI Interface: Timing Characteristics

Signal

Inputs

Parameter

Description

Input level low

Min

—

Max

0.8

—

Unit

V

IL

V

Input level high

Output level low

Output level high

Clock period

Clock rise/fall

Pulse width

2.0

—

V

IH

D

V

0.4

—

V

out

OL

OH

V

2.4

1952

—

V

out

DCL(2)

DCL(3)

FSC

t

1955

60

ns

DCL

t , t

R F

t

, t

800

243.9

90

—

WH WH

t

Clock period

Pulse width

244.3

—

DCL

,t

t

WL WH

t

Frame setup

Frame rise/fall

Frame width H

Frame width L

Frame hold

70

DCL-60

60

SF

t , t

FSC

—

R F

FSC

t

130

—

WFH

FSC

t

—

WFL

DCL

60

FSC

t

—

HF

DDC

D

t

Data delay/clock

Data delay/frame

Data setup

—

100

150

—

out(1)

t

out(1)

DDF

D

t

+ 20

in

SD

HD

wH

60

t

Data hold

—

in

(1)

(2)

(3)

Condition C = 150 pF

L

—

256 kbps transmission

2048 kbps transmission

—

MS140131KT

6-3

Detailed Programming Description: C/I Bits

ꢍꢄꢆ &ꢂ,ꢀ%,76

The C/I bits are used to transfer signalling information for both channels simultaneously. The C/I bits must

be stable for at least two consecutive GCI frames before they will be recognized.

The bit allocations for both downstream and upstream directions are shown in Table 6-3. Note that the

signals are active low, meaning that the idle condition is a logic 1.

Table 6-3. C/I Bit Allocation

Direction

Downstream

C/I 7

RNG0

LS0

C/I 6

MPI0

AL0

C/I 5

ADSI0

RPH0

C/I 4

RNG1

LS1

C/I 3

MPI1

AL1

C/I 2

ADSI1

RPH1

Upstream

RNG Activate ringing.

MPI

Activate metering pulse.

ADSI Activate on-hook signalling.

LS

AL

Off-hook condition detected (loop stable).

Alarm (indicates any of the possible alarm conditions: initrequest, overpower detected).

RPH Ring phase. Indicates that ADSI data can not be sent.

ꢍꢄꢊ 021,725ꢀ&+$11(/

The CODSP acts as a slave device on the GCI — commands received in the downstream direction are

responded to in the upstream direction.

The E and A bits in the C/I byte are used to synchronize and acknowledge the correct transfer of a monitor

channel byte.

Valid commands are:

ID Request

1 0 0 0 0 0 0 0

1 0 0 0 1 B B B

1 0 0 1 1 B B B

Write Request

Read Request

(BBB is the memory block identifier or “MemID” — see below.) Other commands should not be used.

ꢍꢄꢍ ,'ꢀ5(48(67

The ID request command returns two bytes:

Byte 1

Byte 2

1 0 0 0 0 0 0 0

Command Confirmation

Revision Code

1 0 R R R R R R

This command returns a unique code for each device revision.

6-4

MS140131KT

Detailed Programming Description: Read Command

ꢍꢄꢎ 5($'ꢀ&200$1'

A read request command comprises 3 bytes:

Read Request

Address High

Address Low

1 0 0 1 1 B B B

n n n n n n n n

The response is a 5-byte stream:

Command Conf.

Address High

Address Low

Data High

Data Low

1 0 0 1 1 B B B

n n n n n n n n

d d d d d d d d

ꢍꢄꢐ :5,7(ꢀ&200$1'

The write command comprises 5 bytes:

Command Conf.

Address High

Address Low

Data High

Data Low

1 0 0 0 1 B B B

n n n n n n n n

d d d d d d d d

d d d d d d d

No bytes are returned.

ꢍꢄꢑ 0(025<ꢀ0$3ꢀ2)ꢀ7+(ꢀ&2'63

Global memory map and MemID definitions:

•

All addresses can be read and written, though writing to locations or individual bits which are not

described here may result in unpredictable behavior.

The default parameter and coefficient values that are used at startup and after reset are listed in the

following tables.

The memory block to be accessed is given as part of the READ or WRITE command (see above)

as the “B” bits in the command byte.

The control registers of the SH-POTS system, accessed via the GCI, are organized in a number of

memory blocks. Within each block, a number of addresses are used directly to control the

operation of specific functions of the SH-POTS system.

MS140131KT

6-5

Detailed Programming Description: Data RAM — MemID = 2

Table 6-4. Memory Map for CODSP

MemID

Memory

Start Address

Memory Contents

2

Data RAM

0x 02 0000

C-code read/write data

C-code stack region

C-code IRQ stack region

4

5

Coprocessor Coef RAM

Shared RAM

0x 04 0000

0x 05 0000

Filter coefficients

Data packet buffers

Label vectors, FIFO control

ꢍꢄꢃꢈ '$7$ꢀ5$0ꢀ³ꢀ0(0,'ꢀ ꢀꢇ

Table 6-5. Data RAM: Memory Map

Address

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

00 (0x0000)

01 (0x0001)

02 (0x0002)

03 (0x0003)

04 (0x0004)

05 (0x0005)

06 (0x0006)

07 (0x0007)

08 (0x0008)

09 (0x0009)

10 (0x000A)

11 (0x000B)

12 (0x000C)

13 (0x000D)

14 (0x000E)

15 (0x000F)

16 (0x0010)

17 (0x0011)

18 (0x0012)

19 (0x0013)

20 (0x0014)

21 (0x0015)

22 (0x0016)

23 (0x0017)

24 (0x0018)

25 (0x0019)

Bbs0

Bbs1

Bsa0 Bs0 Br0 Tst0 Sh0

Bsa1 Bs1 Br1 Tst1 Sh1

Tx Gain 0

Tx Gain 1

Rx Gain 0

Rx Gain 1

Dzd1 Dzd0

Td1 Td0

CurLim_Rlarge

CurLim_Threshold

RW

RIL RM

Ringing_Amplitude

Ringing_On_Period

LBO

RF

Ringing_DC_Offset

Ringing_Off_Period

RTDAC_ThresholdLow

RTDAC_Debouncetime

RTDAC_ThresholdHigh

RTDAC_GapTime

AlarmReg

IDC0

IDC1

IAC0

IAC1

TG1 TG0 MS1 MS0

TestTone_Ampl1_L0

TestTone_Ampl1_L1

TestTone_Ampl2_L0

TestTone_Ampl2_L1

TestTone_Freq1_L0

6-6

MS140131KT

Detailed Programming Description: LBO Register

Table 6-5. Data RAM: Memory Map (continued)

Address

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

26 (0x001A)

27 (0x001B)

28 (0x001C)

29 (0x001D)

30 (0x001E)

31 (0x001F)

32 (0x0020)

TestTone_Freq1_L1

TestTone_Freq2_L0

TestTone_Freq2_L1

ACG

Rzd0

Sleep2

Pd1 Pd0

Rzd1

Sleep1

DialP_SatTxLevel

DialP_DebTime

NOTE: Bit positions and memory locations not documented must not be changed.

ꢍꢄꢃꢃ /%2ꢀ5(*,67(5

This register controls various loopback modes, as well as the routing of the GCI B channels to or from the

physical line analog channels. The bits are codes as shown in Table 6-6.

Table 6-6. LBO Register Description

Mode

Normal

D2

D1

D0

GCI Side

Analog Side

0

Tx(0) -> B1Up

Tx(1) -> B2Up

B1Down -> Rx(0)

B2Down -> Rx(1)

Simplex loop B2

Simplex loop B1

0

1

0

1

0

1

0

1

0

Tx(0) -> B1Up

B2Down -> B2Up

B1Down -> Rx(0)

Tx(1) -> Rx(1)

B1Down -> B1Up

Tx(1) -> B2Up

Tx(0) -> Rx(0)

B2Down -> Rx(1)

Simplex loop B1

and B2

B1Down -> B1Up

B2Down -> B2Up

Tx(0) -> Rx(0)

Tx(1) -> Rx(1)

Duplex loopback

B2Down -> B1Up

B1Down -> B2Up

Tx(0) -> Rx(1)

Tx(1) -> Rx(0)

Reserved

Swap mode

1

0

1

0

1

Tx(0) -> B2Up

Tx(1) -> B1Up

B1Down -> Rx(1)

B2Down -> Rx(0)

BnDown: GCI B channel 1 or 2, downstream direction.

BnUp:

Tx(m):

Rx(m):

GCI B channel 1 or 2, upstream direction.

Analog “transmit” signal (upstream direction), line 1 or 2.

Analog “receive” signal (downstream direction), line 1 or 2.

MS140131KT

6-7

Detailed Programming Description: Alarm Bits

ꢍꢄꢃꢇ $/$50ꢀ%,76

•

After initialization (e.g., due to a hardware reset), the CODSP itself will make the upstream

CI/Alarm bit active, and set the AlarmReg with an InitRequest value (i.e., “1xx”). The CI/Alarm

bit will remain active until the InitRequest is cleared by the GCI supervisor (indicating that the

supervisor has done the necessary reinitialization of system parameters).

•

In order to check the contents of the AlarmReg, execute the following GCI command:

ReadRequest ( MemId=2, Add=0x0010 );

This results in a four-nibble value; e.g., “0xabgd,” read by the supervisor.

•

In order to clear the InitRequest alarm, in principle, one must only clear one bit. Therefore, the

supervisor should execute the following commands:

NewValue = ”0xabgd” AND ”0xFFFB”;

WriteRequest ( MemId=2, Add=0x0010, NewValue );

•

Note that the other bits in the alarm register are updated by the DSP at a 8 kHz rate, and that they

are only used by the GCI supervisor; therefore, the other bits might also be overwritten for one

cycle, clearing all bits (inclusive the InitRequest bit) in one command:

WriteRequest ( MemId=2, Add=0x0010, 0x0000 );

ꢍꢄꢃꢉ 0($1,1*ꢀ$1'ꢀ'()$8/7ꢀ9$/8(6ꢀ2)ꢀ7+(ꢀ

3$5$0(7(56

Table 6-7. Data RAM: Description and Default Values

Name (Note 1)

Sh0, Sh1

Address Position

Description

Mapping

Default

00, 01

0

1

2

3

SHLIC test mode control 0: normal mode

0

bit

1: test mode

(normal)

Tst0, Tst1

Br0, Br1

Bs0, Bs1

SHLIC test switch

control bit

0: open switch

1: closed switch

0

(open)

SHLIC battery reversal 0: non-reversed

control bit 1: reversed

0

(non rev.)

SHLIC battery selection 0: BATS selection L

control bit for NonAct_X 1: BATR selection H

variant

0

(NonAct_L)

Bsa0, Bsa1

Bbs0, Bbs1

00, 01

4

SHLIC battery selection 0: BATS selection L

control bit for ActAdsi_X 1: BATR selection H

variant

0

(ActAdsi_L)

6:5

SHLIC battery selection 0 = “00”:BATS L

0

control bit for

1 = “01”:BATR H

(ActRng_Sph_L)

ActRng_Sph_X variant 2 = “10”:BATS + bias

LA

3 = “11”:BATR + bias

HA

6-8

MS140131KT

Detailed Programming Description: Meaning and Default Values of the Parameters

Table 6-7. Data RAM: Description and Default Values (continued)

Name (Note 1)

Address Position

Description

Mapping

Default

Tx_Gain_0

Tx_Gain_1

03

04

15:0

Gain factor in Tx

direction for Line0 and

Line1

320

(0 dB)

Tx-Gain_*

20 log

320

Rx_Gain_0

Rx_Gain_1

05

06

15:0

Gain factor in Rx

direction for Line0 and

Line1

384

( –7dB)

Rx-Gain_*

384

– 7 + 20 log

Dzd1, Dzd0

07

08

09

1:0

7:0

Disable digital Z

path 0: enable

1: disable

1

CO

(disabled)

Td1, Td0

Disable Tx path at pdm 0: enable

level

0

1: disable

(enabled)

CurLim_Threshold

Current limitation

val = 0 ... 127

51

threshold parameter

unit = 0.63 mA

(eq = 0 ... 80 mA)

(32 mA)

CurLim_RLarge

RF

09

10

15:8

1:0

Current limitation

RLarge resistance

parameter (internal

resistance)

val = 0 ... 210

unit = 47

(eq = 0 ... 10 kΩ)

64

(3 kΩ)

Ringing frequency

0 = “00”: 16 Hz

1 = “01”: 20 Hz

2 = “10”: 25 Hz

3 = “11”: 50 Hz

3

(50 Hz)

RM

10

11

2

3

Ringing mode

0: on/off mode

1: burst mode

0

(on/off)

RIL

Enable interleaved

ringing

0: non-interleaved

1: interleaved

1

(interleaved)

RW

5

Ringing waveform

0: sine wave

1: trapezoidal wave

0

(sine)

Ringing_Amplitude

Ringing_DC_Offset

7:0

15:8

Amplitude of ringing

signal

val = 0 ... 255

unit = 194 mV rms

255

(max ampl)

DC offset of ringing

signal

val = 0 ... 255

unit = 250 mV

0

(no offset)

(Between A and B wire)

Ringing_On_Period

Ringing_Off_Period

12

7:0

Length of active ringing val = 0 ... 255

32

(1 s)

phase to be used in

burst mode

unit = 32 ms

15:8

Length of silent ringing val = 0 ... 255

96

phase to be used in

burst mode

unit = 32 ms

(3 s)

LBO

13

14

15

3:0

7:0

GCI loopback register

(encoding see below)

val = 0 ... 15

0

(no loop)

RTDAC_ThresholdHigh

RTDAC_ThresholdLow

RTDAC_GapTime

RTDAC_Debouncetime

Threshold level high

during ringing

val = 0 ... 255

unit = 1.6 mA

27

(43.2 mA)

15:8

7:0

Threshold level low

during ringing

val = 0 ... 255

unit = 1.6 mA

7

(11.2 mA)

Gaptime during RTDAC val = 0 ... 255

peak detection

10

(1.25 ms)

unit = 125 µs

15:8

Deb. time during

RTDAC

val = 0 ... 255

unit = 125 µs

240 (30 ms)

MS140131KT

6-9

Detailed Programming Description: Meaning and Default Values of the Parameters

Table 6-7. Data RAM: Description and Default Values (continued)

Name (Note 1)

AlarmReg

Address Position

Description

Mapping

val = 0 ... 7

Default

16

17

18

19

20

2:0

Alarm status register

(encoding)

4 (InitReq’st)

IDC1

7:0

DC line current of Line1, val = 0 ... 127

sampled at 2 kHz unit = 0.63 mA

0

IDC0

15:8

15:0

3, 2

1, 0

7:0

DC line current of Line0, val = 0 ... 127

sampled at 2 kHz unit = 0.63 mA

IAC0

AC line current of Line0, unit = 215/1.6 V @ Tx

sampled at 8 kHz

IAC1

AC line current of Line1, unit = 215/1.6 V @ Tx

sampled at 8 kHz

TG1, TG0

MS1, MS0

Tone generator control 0 : do not add tone

bit for Line1 and Line0 1 : add tone

0

(no tone)

Mute speech control bit 0 : pass speech

for Line1 and Line0

0

1 : mute speech

(no mute)

TestTone_Ampl1_L0

TestTone_Ampl1_L1

21

22

Amplitude of first sine for val = 0 ... 255

Line0 and Line1

63

(0 dBm)

TestTone_Ampl2_L0

TestTone_Ampl2_L1

23

24

7:0

Amplitude of second

sine for Line0 and Line1

val = 0 ... 255

63

(0 dBm)

TestTone_Freq1_L0

TestTone_Freq1_L1

25

26

15:0

7:0

Frequency of first sine

for Line0 and Line1

unit = 250 Hz/256

1024/256

(1 kHz)

TestTone_Freq2_L0

TestTone_Freq2_L1

27

28

Frequency of second

sine for Line0 and Line1

512/256

(500 Hz)

ACG

29

30

31

Rx amplitude correction val = 0 ... 255/128

for Z synthesis

103/128

(600 Ω)

CO

Pd1, Pd0

11:10

13:12

2:0

Power denial mode

Line1

1 = enable

0 = disable

0

(disable)

Sleep2 (Note 2)

Sleep1 (Note 2)

Rzd1, Rzd0

DialP_SatTxLevel

Low power activation

00 = inactive

11 = active

00

active

Sleep factor to be used val = 0 ... 7

when one line inactive

0

eq = 0 ... 70% sleepy (0% sleep)

4:3

Disable analog Z

path

0: enable

1: disable

0

CO

(enabled)

15:0

Tx saturation level to be unit = 48.83 µV @ Tx 8192

used for dial pulse

detection

(400 mV)

DialP_DebTime

32

15:0

Debounce time to be

used for dial pulse

detection

unit = 125 µs

40

(5 ms)

NOTES: 1. Parameter names with 0 or 1 at the end refer to the analog Line0 or Line1.

2. In low power applications: recommended program value is sleep 1 = 5 combined with sleep 2 = 3 will save

power consumption when only one line off-hook.

6-10

MS140131KT

Detailed Programming Description: Coprocessor Coefficient RAM — MemID = 4

ꢍꢄꢃꢆ &2352&(6625ꢀ&2()),&,(17ꢀ5$0ꢀ³ꢀꢀ

0(0,'ꢀ ꢀꢆ

Access is similar to that of the data RAM parameters. Note, however, that the GCI commands work with

2-byte values whereas the memory contains only 3-nibble values. Because all values are <12, 0>, the most

significant nibble of the 2-byte GCI value will be a sign-extension of the 12-bit value. In the case of a

ReadRequest; the most significant nibble of a WriteRequest will be neglected.

Table 6-8. Coprocessor Coefficient RAM: Memory Map

Address

11

10

9

8

7

6

5

4

3

2

1

0

00 (0x0000)

01 (0x0001)

02 (0x0002)

03 (0x0003)

04 (0x0004)

05 (0x0005)

06 (0x0006)

07 (0x0007)

08 (0x0008)

09 (0x0009)

10 (0x000A)

11 (0x000B)

12 (0x000C)

13 (0x000D)

14 (0x000E)

15 (0x000F)

16 (0x0010)

17 (0x0011)

18 (0x0012)

19 (0x0013)

20 (0x0014)

21 (0x0015)

22 (0x0016)

23 (0x0017)

24 (0x0018)

25 (0x0019)

26 (0x001A)

27 (0x001B)

28 (0x001C)

29 (0x001D)

30 (0x001E)

31 (0x001F)

32 (0x0020)

Rx32KFilter coefficient : r0

r1

r4

s1

s2

r2

r3

r5

s3

s4

m0

m1

u0

u1

Hyb16KFilter coefficient : h0

h1

h2

h3

a0

c5

b0

Tx32KFilter coefficient : t0

t1

t8

q1

q2

t2

t3

t9

q3

q4

t4

t5

MS140131KT

6-11

Detailed Programming Description: Meaning and Default Values of the Parameters

Table 6-8. Coprocessor Coefficient RAM: Memory Map (continued)

Address

11

10

9

8

7

6

5

4

3

2

1

0

33 (0x0021)

34 (0x0022)

35 (0x0023)

36 (0x0024)

37 (0x0025)

38 (0x0026)

39 (0x0027)

40 (0x0028)

41 (0x0029)

42 (0x002A)

43 (0x002B)

44 (0x002C)

45 (0x002D)

46 (0x002E)

t10

q5

t6

t7

t11

q6

q7

c2

c3

ZcoTxFilter coefficient : Ftx

Ap

NAn

Constants : HLF

ONE_EIGHT

ꢍꢄꢃꢊ 0($1,1*ꢀ$1'ꢀ'()$8/7ꢀ9$/8(6ꢀ2)ꢀ7+(ꢀ

3$5$0(7(56

Table 6-9. Coprocessor Coefficient RAM: Description and

Default Values

Name

r0

Address

00

Position

11:0

Description

Rx filter coefficient

Mapping

Default

96

unit = intval / 512

r1

01

Rx filter coefficient

–78*

96

r4

02

Rx filter coefficient

s1

s2

r2

03

Rx filter coefficient

642

–263*

256

–303*

256

746

–450*

512

0

04

Rx filter coefficient

05

Rx filter coefficient

r3

06

Rx filter coefficient

r5

07

Rx filter coefficient

s3

s4

m0

m1

u0

u1

h0

h1

h2

h3

08

Rx filter coefficient

09

Rx filter coefficient

10

Rx filter coefficient

11

Rx filter coefficient

12

Rx filter coefficient

13

Rx filter coefficient

0

14

Echo cancelling coefficient

4

15

–22*

105

95

16

17

6-12

MS140131KT

Detailed Programming Description: Meaning and Default Values of the Parameters

Table 6-9. Coprocessor Coefficient RAM: Description and

Default Values (continued)

Name

Address

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

Position

11:0

Description

Echo cancelling coefficient

Tx filter coefficient

Mapping

Default

0

a0

unit = intval / 512

c5

0

b0

0

t0

48

t1

–37*

48

t8

q1

728

–439*

390

–492*

390

573

–227*

64

q2

t2

t3

t9

q3

q4

t4

t5

128

64

t10

q5

442

384

768

384

962

–458*

512

–512*

237

0

t6

t7

t11

q6

q7

c2

c3

Ftx

Z

Tx filter coefficient

CO

Ap

NAn

0

HLF

Constant definition

256

64

ONE_EIGHT

*For negative values, 2’s complement is used.

MS140131KT

6-13

Detailed Programming Description: Shared Memory — MemID = 5

ꢍꢄꢃꢍ 6+$5('ꢀ0(025<ꢀ³ꢀ0(0,'ꢀ ꢀꢊ

Table 6-10. Shared Memory: Memory Map

Address

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

85

VLM

HT

Deb

MF MM

(0x0055)

86

SpiDo SpiDi SpiSk SpiCs SpiSe RBD

SR* SR*

(0x0056)

87

(0x0057)

HSD_ThresholdHigh

RTD_ThresholdHigh

HSD_ThresholdLow

RTD_ThresholdLow

88

(0x0058)

89

(0x0059)

MeteringDutyCycle

ZcoA2

RZco

90

(0x005A)

ZcoShAlfa3

Rxd*

Alo*

Sleep*

ZcoAlfa3

91

ZcoGamma

(0x005B)

94

TL

(0x005E)

NOTE: Bit positions and memory locations not described here must not be changed.

ꢍꢄꢃꢎ 0($1,1*ꢀ$1'ꢀ'()$8/7ꢀ9$/8(6ꢀ2)ꢀ7+(ꢀ

3$5$0(7(56

Table 6-11. Shared Memory: Description and Default Values

Name

Address Position

Description

Mapping

val = 0 ... 15

Default

VLM

HT

85

14:11

Metering amplitude

3

(unit value = depending on

Z

)

CO

85

10:9

HSD debounce time

0 = “00”: 8 ms

1 = “01” : 24 ms

2 = “10” : 16 ms

3 = “11”: 64 ms

2

(16 ms)

DEB

MF

85

8

4

3

RTD debounce time

Metering frequency

Metering mode

0 : 0 ms

1 : 30 ms

1

(30 ms)

0 : 12 kHz

1 : 16 kHz

1

(16 kHz)

MM

0 : burst mode

1 : on/off mode

1

(on/off)

SPIDO

SPIDI

86

15

14

13

12

SPI D

out

port

0

SPI D port

in

SPISK

SPICS

SPI SK port

SPI CS port

6-14

MS140131KT

Detailed Programming Description: Meaning and Default Values of the Parameters

Table 6-11. Shared Memory: Description and Default Values (continued)

Name

Address Position

Description

SPI port selection

Mapping

Default

SPISE

RBD

86

11

10

0

Disable automatic ring

activation of SPICK and

SPICK

1 = disabled

0 = enabled

0

(enabled)

SR (Note 1)

86

5:4

1:0

Software resets of SID1, SID0, 1 = reset block

0

CP, GCI

0 = no reset

Soft Resets (Note 2)

5:0

13:7

6:0

Reset ability of HW blocks

(SID0, SID1, MRT, LS, CP,

GCI)

0: no reset

1: reset block

0

(no reset)

HSD_ThresholdHigh

HSD_ThresholdLow

RTD_ThresholdHigh

RTD_ThresholdLow

MeteringDutyCycle

87

88

89

HSD high threshold

HSD low threshold

RTD high threshold

RTD low threshold

val = 0 ... 127

unit = 0.63 mA

= 0 ... 80 mA

16

(10 mA)

val = 0 ... 127

unit = 0.63 mA

= 0 ... 80 mA

10

(6.3 mA)

13:7

6:0

val = 0 ... 127

unit = 0.63 mA

= 0 ... 80 mA

16

(10 mA)

val = 0 ... 127

unit = 0.63 mA

= 0 ... 80 mA

10

(6.3 mA)

15:8

Length of the metering burst to val = 0 ... 255

150

be used in “burst” metering

mode

unit = 2 ms

= 0 ... 510 ms

(300 ms)

ZcoShAlfa3

ZcoA2

90

91

94

15:1

13:7

6

Central office impedance

parameter

(Note 1)

0

(600 Ω)

Central office impedance

parameter

0

(600 Ω)

RxD (Note 1)

ALO (Note 2)

Sleep (Note 2)

RZco

RxDisable at input of analog

part

0: enabled Rx path

1: disable Rx path

0

(enabled)

4

Analog loopback at pdm

0: disabled loop

1: enable loop

0

(disabled)

2:0

11:8

7:4

3:0

1:0

Sleep factor actually used by val = 0 ... 7

the processor

0

= 0 ... 70% sleepy

(0% sleep)

Central office impedance

parameter

(Note 1)

3

(600 Ω)

ZcoGamma

ZcoAlfa3

TL

Central office impedance

parameter

0

(600 Ω)

Central office impedance

parameter

0

(600 Ω)

Transcode law selection

0 = “00”: A Law

1 = “01”: µ Law

2 = “10”: Linear

0

(A-Law)

NOTES: 1. Examples of other Z

parameters are listed in Table 4-4. Otherwise, contact a Motorola sales office.

2. Do not change these values.

CO

MS140131KT

6-15

6(&7,21ꢀꢎ

0(&+$1,&$/ꢀ63(&,),&$7,216

ꢎꢄꢃ 0&ꢃꢆꢇꢈꢇꢉꢇꢀ3$&.$*(ꢀ',0(16,216

FU SUFFIX

TQFP PACKAGE

CASE 824D-02

PLATING

BASE METAL

–X–

X=L, M, N

4X 11 TIPS

0.2 (0.008)

T

L–M N

4X

0.2 (0.008)

H

L–M N

F

44

34

33

J

U

C

L

1

AB

40X

G

D

M

S

0.20 (0.008)

T

L–M

N

3X VIEW Y

–L–

–M–

SECTION AB–AB

ROTATED 90 CLOCKWISE

VIEW Y

B

V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

B1

V1

11

23

22

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –L–, –M– AND –N– TO BE DETERMINED

AT DATUM PLANE –H–.

12

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –T–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

–N–

A1

S1

A

S

DETERMINED AT DATUM PLANE –H–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED 0.53

(0.021). MINIMUM SPACE BETWEEN

PROTRUSION AND ADJACENT LEAD OR

PROTRUSION 0.07 (0.003).

4X ( 2)

VIEW AA

C

–H–

0.1 (0.004)

T

MILLIMETERS

MIN MAX

10.00 BSC

5.00 BSC

10.00 BSC

5.00 BSC

INCHES

MIN MAX

0.394 BSC

0.197 BSC

0.394 BSC

0.197 BSC

DIM

A

A1

B

B2

C

C1

C2

D

–T–

SEATING

PLANE

4X ( 3)

C2

–––

0.05

1.35

0.30

0.45

0.30

1.60

–––

0.002

0.053

0.012

0.018

0.012

0.063

0.15

1.45

0.45

0.75

0.40

0.006

0.057

0.018

0.030

0.016

S

0.05 (0.002)

E

F

G

(W)

0.80 BSC

0.031 BSC

J

K

R1

S

S1

U

0.09

0.50 REF

0.09

12.00 BSC

6.00 BSC

0.09 0.16

0.20

0.004

0.020 REF

0.004

0.472 BSC

0.236 BSC

0.004 0.006

0.008

1

2X R R1

0.20

0.008

0.25 (0.010)

GAGE PLANE

V

12.00 BSC

6.00 BSC

0.20 REF

1.00 REF

0.472 BSC

0.236 BSC

0.008 REF

0.039 REF

V1

W

Z

(K)

E

(Z)

C1

0

7

–––

0

7

–––

1

2

3

12 REF

VIEW AA

MS140131KT

7-1

Mechanical Specifications: MC1420232 Package Dimensions

ꢎꢄꢇ 0&ꢃꢆꢉꢈꢃꢉꢇꢀ3$&.$*(ꢀ',0(16,216

DW SUFFIX

SOIC PACKAGE

CASE 751F-05

NOTES:

D

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND

TOLERANCES PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

A

28

15

4. MAXIMUM MOLD PROTRUSION 0.015 PER

SIDE.

5. DIMENSION B DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.13

TOTAL IN EXCESS OF B DIMENSION AT

MAXIMUM MATERIAL CONDITION.

1

14

MILLIMETERS

B

PIN 1 IDENT

DIM MIN

2.35

A1 0.13

MAX

2.65

0.29

0.49

0.32

A

B

C

D

E

e

H

L

q

0.35

0.23

17.80 18.05

7.40 7.60

1.27 BSC

10.05 10.55

L

0.10

e

0.41

0

0.90

8

C

×

SEATING

PLANE

B

C

q

M

S

0.025

C A

B

7-2

MS140131KT

Mechanical Specifications: MC1420232 Package Dimensions

ꢎꢄꢉ 5(&200(1'('ꢀ3$'ꢀ/$<287ꢀ)25ꢀ

ꢆꢆꢁ/($'ꢀ74)3ꢀ0&ꢃꢆꢇꢈꢇꢉꢇ

A

B

Solder Pad Size: W = 0.55 mm x L = 2.0 mm

Solder Pad Pitch: 0.8 mm (center to center)

Toe to Toe Dimension: A = 14.2 mm x B = 14.2 mm

Figure 7-1. Recommended Pad Layout for 44-Lead TQFP MC1420232

MS140131KT

7-3

Digital DNA is a trademark of Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application

by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola

products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could

create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly

or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges

that Motorola was negligent regarding the design or manufacture of the part. Motorola and

Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

are registered trademarks of

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217.

1-303-675-2140 or 1-800-441-2447

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573

Japan. 81-3-3440-3569

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate,

Tao Po, N.T., Hong Kong. 852-26668334

TECHNICAL INFORMATION CENTER: 1-800-521-6274

HOME PAGE: http://motorola.com/semiconductors/

MS140131KT/D


型号：	MS140131KT/D
厂家：	NXP
描述：	SPECIALTY TELECOM CIRCUIT, PQFP44, TQFP-44 电信电信集成电路
文件：	总66页 (文件大小：561K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MS140131KT/D [NXP]

相关型号：

MS140131KTR2

MS140132KT

MS1402

MS1402

MS1403

MS1403

MS1404

MS14046

MS14046-07RU

MS14046-09RU

MS14046-1

MS14046-10