MPC8541VTAJE [NXP]
32-BIT, 533MHz, RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783;
| 型号： | MPC8541VTAJE |
| 厂家： | 
NXP |
| 描述： | 32-BIT, 533MHz, RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783 时钟 外围集成电路 |
| 文件： | 总88页 (文件大小：1109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC8541EEC
Rev. 4.2, 1/2008
Freescale Semiconductor
Technical Data
MPC8541E PowerQUICC™ III
Integrated Communications Processor
Hardware Specification
Contents
The MPC8541E integrates a PowerPC™ processor core
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
built on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8541E is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the MPC8555E
PowerQUICC™ III Integrated Communications Processor
Reference Manual.
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. Ethernet: Three-Speed, MII Management . . . . . . . . . . 21
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
14. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 54
15. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
16. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
17. System Design Information . . . . . . . . . . . . . . . . . . . . . 76
18. Document Revision History . . . . . . . . . . . . . . . . . . . . 83
19. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 84
To locate any published errata or updates for this document
refer to http://www.freescale.com or contact your Freescale
sales office.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Overview
1 Overview
The following section provides a high-level overview of the MPC8541E features. Figure 1 shows the
major functional units within the MPC8541E.
.
DDR
SDRAM
DDR SDRAM Controller
Security
Engine
256 Kbyte
L2 Cache/
SRAM
2
I C Controller
e500 Core
e500
Coherency
Module
DUART
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
Core Complex
Bus
GPIO
32b
Local Bus Controller
Programmable
Interrupt Controller
IRQs
Serial
CPM
DMA
64/32b PCI Controller
0/32b PCI Controller
DMA Controller
OCeaN
FCC
ROM
FCC
I-Memory
MIIs/RMIIs
I/Os
DPRAM
RISC
10/100/1000 MAC
10/100/1000 MAC
Engine
SPI
MII, GMII, TBI,
RTBI, RGMIIs
I2C
Parallel I/O
Baud Rate
Generators
Timers
CPM
Interrupt
Controller
Figure 1. MPC8541E Block Diagram
1.1
Key Features
The following lists an overview of the MPC8541E feature set.
Embedded e500 Book E-compatible core
•
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
2
Freescale Semiconductor
Overview
•
Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels,
a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:
— Public Key Execution Unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511-bits
— Data Encryption Standard Execution Unit (DEU)
– DES, 3DES
– Two key (K1, K2) or Three Key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced Encryption Standard Unit (AESU)
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and Counter modes
— ARC Four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message Digest Execution Unit (MDEU)
– SHA with 160-bit or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random Number Generator (RNG)
— 4 Crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
High-performance RISC CPM
•
•
— Two full-duplex fast communications controllers (FCCs) that support the following protocol:
– IEEE Std 802.3™/Fast Ethernet (10/100)
— Serial peripheral interface (SPI) support for master or slave
2
— I C bus controller
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
256 Kbytes of on-chip memory
— Can act as a 256-Kbyte level-2 cache
— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays
— Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
— Full ECC support on 64-bit boundary in both cache and SRAM modes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
3
Overview
— SRAM operation supports relocation and is byte-accessible
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines
– Individual line locks set and cleared through Book E instructions or by externally mastered
transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
Address translation and mapping unit (ATMU)
•
•
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI
– Four inbound windows
– Four outbound windows plus default translation for PCI
DDR memory controller
— Programmable timing supporting first generation DDR SDRAM
— 64-bit data interface, up to MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Sleep mode support for self refresh DDR SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
•
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
4
Freescale Semiconductor
Overview
— Four global high resolution timers/counters that can generate interrupts
— Supports additional internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
2
•
•
Two I C controllers (one is contained within the CPM, the other is a stand-alone controller which
is not part of the CPM)
— Two-wire interface
— Multiple master support
2
— Master or slave I C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
2
— Optionally loads configuration data from serial ROM at reset via the stand-alone I C interface
— Can be used to initialize configuration registers and/or memory
2
— Supports extended I C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
•
•
— Two 4-wire interfaces (RXD, TXD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Two Three-speed (10/100/1000)Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers
— Support for Ethernet physical interfaces:
•
– 10/100/1000 Mbps IEEE 802.3 GMII
– 10/100 Mbps IEEE 802.3 MII
– 10 Mbps IEEE 802.3 MII
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
5
Overview
– 1000 Mbps IEEE 802.3z TBI
– 10/100/1000 Mbps RGMII/RTBI
— Full- and half-duplex support
— Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— 2-Kbyte internal transmit and receive FIFOs
— MII management interface for control and status
— Programmable CRC generation and checking
OCeaN switch fabric
•
•
— Three-port crossbar packet switch
— Reorders packets from a source based on priorities
— Reorders packets to bypass blocked packets
— Implements starvation avoidance algorithms
— Supports packets with payloads of up to 256 bytes
Integrated DMA controller
— Four-channel controller
— All channels accessible by both local and remote masters
— Extended DMA functions (advanced chaining and striding capability)
— Support for scatter and gather transfers
— Misaligned transfer capability
— Interrupt on completed segment, link, list, and error
— Supports transfers to or from any local memory or I/O port
— Selectable hardware-enforced coherency (snoop/no-snoop)
— Ability to start and flow control each DMA channel from external 3-pin interface
— Ability to launch DMA from single write transaction
PCI Controllers
•
— PCI 2.2 compatible
— One 64-bit or two 32-bit PCI ports supported at 16 to 66 MHz
— Host and agent mode support, 64-bit PCI port can be host or agent, if two 32-bit ports, only one
can be an agent
— 64-bit dual address cycle (DAC) support
— Supports PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses
— Supports posting of processor-to-PCI and PCI-to-memory writes
— PCI 3.3-V compatible
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
6
Freescale Semiconductor
Electrical Characteristics
— Selectable hardware-enforced coherency
— Selectable clock source (SYSCLK or independent PCI_CLK)
Power management
•
•
— Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O
— Supports power save modes: doze, nap, and sleep
— Employs dynamic power management
— Selectable clock source (sysclk or independent PCI_CLK)
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter specific events
— Supports 64 reference events that can be counted on any of the 8 counters
— Supports duration and quantity threshold counting
— Burstiness feature that permits counting of burst events with a programmable time between
bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
•
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE Std 1149.1™-compatible, JTAG boundary scan
783 FC-PBGA package
•
•
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8541E. The MPC8541E is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
7
Electrical Characteristics
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
1
Table 1. Absolute Maximum Ratings
Symbol
Characteristic
Max Value
Unit
Notes
Core supply voltage
PLL supply voltage
DDR DRAM I/O voltage
V
–0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
DD
AV
–0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
DD
GV
–0.3 to 3.63
V
V
DD
Three-speed Ethernet I/O, MII management voltage
LV
–0.3 to 3.63
–0.3 to 2.75
DD
CPM, PCI, local bus, DUART, system control and power
management, I C, and JTAG I/O voltage
OV
–0.3 to 3.63
V
3
DD
2
Input voltage
DDR DRAM signals
MV
–0.3 to (GV + 0.3)
V
V
V
V
2, 5
2, 5
4, 5
5
IN
DD
DDR DRAM reference
Three-speed Ethernet signals
MV
–0.3 to (GV + 0.3)
DD
REF
LV
–0.3 to (LV + 0.3)
DD
IN
CPM, Local bus, DUART,
OV
–0.3 to (OV + 0.3)1
DD
IN
SYSCLK, system control and
2
power management, I C, and
JTAG signals
PCI
OV
–0.3 to (OV + 0.3)
V
6
IN
DD
Storage temperature range
T
–55 to 150
°C
STG
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
3. Caution: OV must not exceed OV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
4. Caution: LV must not exceed LV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
5. (M,L,O)V and MV may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
IN
REF
6. OV on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
IN
shown in Figure 3.
2.1.2
Power Sequencing
The MPC8541Erequires its power rails to be applied in a specific sequence in order to ensure proper device
operation. These requirements are as follows for power up:
1. V , AV
DD
DDn
2. GV , LV , OV (I/O supplies)
DD
DD
DD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
8
Electrical Characteristics
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value
before the voltage rails on the current step reach ten percent of theirs.
NOTE
If the items on line 2 must precede items on line 1, please ensure that the
delay does not exceed 500 ms and the power sequence is not done greater
than once per day in production environment.
NOTE
From a system standpoint, if the I/O power supplies ramp prior to the V
DD
core supply, the I/Os on the MPC8541E may drive a logic one or zero during
power-up.
2.1.3
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8541E. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended Value
Unit
Core supply voltage
PLL supply voltage
DDR DRAM I/O voltage
V
1.2 V 60 mV
1.3 V 50 mV (for 1 GHz only)
V
DD
AV
1.2 V 60 mV
1.3 V 50 mV (for 1 GHz only)
V
DD
GV
2.5 V 125 mV
V
V
DD
Three-speed Ethernet I/O voltage
LV
3.3 V 165 mV
2.5 V 125 mV
DD
PCI, local bus, DUART, system control and power management,
I C, and JTAG I/O voltage
OV
3.3 V 165 mV
V
DD
2
Input voltage
DDR DRAM signals
MV
GND to GV
GND to GV
V
V
V
V
IN
DD
DD
DD
DDR DRAM reference
Three-speed Ethernet signals
MV
REF
LV
GND to LV
IN
PCI, local bus, DUART,
OV
GND to OV
IN
DD
SYSCLK, system control and
2
power management, I C, and
JTAG signals
Die-junction Temperature
T
0 to 105
°C
j
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
9
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8541E.
G/L/OV + 20%
DD
G/L/OV + 5%
DD
G/L/OV
V
DD
IH
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
1
of t
SYS
Note:
1. Note that t
refers to the clock period associated with the SYSCLK signal.
SYS
Figure 2. Overshoot/Undershoot Voltage for GV /OV /LV
DD
DD
DD
The MPC8541E core voltage must always be provided at nominal 1.2 V (see Table 2 for actual
recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with
respect to the associated I/O supply voltage. OV and LV based receivers are simple CMOS I/O
DD
DD
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced the externally supplied MV signal (nominally set to
REF
GV /2) as is appropriate for the SSTL2 electrical signaling standard.
DD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
10
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8541E for the 3.3-V
signals, respectively.
11 ns
(Min)
+7.1 V
Overvoltage
Waveform
7.1 V p-to-p
(Min)
0 V
4 ns
(Max)
4 ns
(Max)
62.5 ns
+3.6 V
Undervoltage
Waveform
7.1 V p-to-p
(Min)
–3.5 V
Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
2.1.4
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Programmable Output
Supply
Voltage
Driver Type
Notes
Impedance (Ω)
Local bus interface utilities signals
25
OV = 3.3 V
1
DD
42 (default)
PCI signals
25
2
42 (default)
DDR signal
20
42
42
GV = 2.5 V
DD
TSEC/10/100 signals
DUART, system control, I2C, JTAG
Notes:
LV = 2.5/3.3 V
DD
OV = 3.3 V
DD
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
11
Power Characteristics
3 Power Characteristics
The estimated typical power dissipation for this family of PowerQUICC III devices is shown in Table 4.
(1) (2)
Table 4. Power Dissipation
(3)(4)
(5)
CCB Frequency (MHz)
Core Frequency (MHz)
V
Typical Power
(W)
Maximum Power (W)
DD
200
400
500
600
533
667
800
667
833
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.3
4.4
4.7
5.0
4.9
5.4
5.8
5.5
6.0
9.0
6.1
6.5
6.8
6.7
7.2
8.6
7.4
8.8
12.2
267
333
(6)
1000
Notes:
1. The values do not include I/O supply power (OV , LV , GV ) or AV
DD.
DD
DD
DD
2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance. Any customer design must take these considerations into account to ensure the maximum 105 degrees junction
temperature is not exceeded on this device.
3. Typical power is based on a nominal voltage of V = 1.2V, a nominal process, a junction temperature of T = 105° C, and a
DD
j
Dhrystone 2.1 benchmark application.
4. Thermal solutions likely need to design to a value higher than Typical Power based on the end application, T target, and I/O
A
power
5. Maximum power is based on a nominal voltage of V = 1.2V, worst case process, a junction temperature of T = 105° C, and
DD
j
an artificial smoke test.
6. The nominal recommended V = 1.3V for this speed grade.
DD
Notes:
1.
2.
3.
4.
5.
6.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
12
Power Characteristics
Comments
Table 5. Typical I/O Power Dissipation
GV
OV
LV
LV
DD
DD
DD
DD
Interface
DDR I/O
Parameters
Unit
(2.5 V) (3.3 V) (3.3 V) (2.5 V)
CCB = 200 MHz
CCB = 266 MHz
CCB = 300 MHz
CCB = 333 MHz
64b, 66 MHz
64b, 33 MHz
32b, 66 MHz
32b, 33 MHz
32b, 167 MHz
32b, 133 MHz
32b, 83 MHz
32b, 66 MHz
32b, 33 MHz
MII
0.46
0.59
0.66
0.73
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.04
—
—
—
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
—
—
—
—
—
—
—
—
PCI I/O
—
0.14
0.08
0.07
0.04
0.30
0.24
0.16
0.13
0.07
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Multiply by 2 if using two 32b ports
—
Local Bus I/O
—
—
—
—
—
—
—
—
—
—
TSEC I/O
0.01
0.07
—
Multiply by number of interfaces
used.
GMII or TBI
RGMII or RTBI
MII
—
—
CPM - FCC
0.015
0.013
0.009
—
—
—
—
RMII
—
HDLC 16 Mbps
—
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
13
Clock Timing
4 Clock Timing
4.1
System Clock Timing
Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8541E.
Table 6. SYSCLK AC Timing Specifications
Parameter/Condition
SYSCLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
t
—
6.0
0.6
40
—
—
—
166
—
MHz
ns
1
—
2
SYSCLK
SYSCLK
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
t
, t
1.0
—
1.2
ns
KH KL
t
/t
60
%
3
KHK SYSCLK
—
—
+/- 150
ps
4, 5
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. For spread spectrum clocking, guidelines are 1% of the input frequency with a maximum of 60 kHz of modulation regardless
of the input frequency.
4.2
TSEC Gigabit Reference Clock Timing
Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the
MPC8541E.
Table 7. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise time
EC_GTX_CLK125 fall time
EC_GTX_CLK125 duty cycle
f
—
—
—
—
125
8
—
—
MHz
ns
—
—
1
G125
t
G125
t
—
—
—
1.0
1.0
ns
G125R
t
ns
1
G125F
t
/t
%
1, 2
G125H G125
GMII, TBI
RGMII, RTBI
45
47
55
53
Notes:
1. Timing is guaranteed by design and characterization.
2. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle
can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
14
Freescale Semiconductor
RESET Initialization
4.3
Real Time Clock Timing
Table 8 provides the real time clock (RTC) AC timing specifications.
Table 8. RTC AC Timing Specifications
Parameter/Condition
RTC clock high time
Symbol
Min
Typical
Max
Unit
Notes
t
2 x
—
—
ns
—
RTCH
t
t
CCB_CLK
RTC clock low time
t
2 x
—
—
ns
—
RTCL
CCB_CLK
5 RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8541E. Table 9 provides the RESET initialization AC timing specifications.
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Required assertion time of HRESET
Min
Max
Unit
Notes
100
512
100
—
—
—
μs
SYSCLKs
μs
—
1
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET
negation
—
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
4
2
—
—
5
SYSCLKs
SYSCLKs
SYSCLKs
1
1
1
Input hold time for POR configs (including PLL config) with
respect to negation of HRESET
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
—
Notes:
1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8541E. See the MPC8555E
PowerQUICC™ III Integrated Communications Processor Reference Manual for more details.
Table 10 provides the PLL and DLL lock times.
Table 10. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
DLL lock times
Notes:
—
100
μs
—
7680
122,880
CCB Clocks
1, 2
1. DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the
minimum and an 8:1 ratio results in the maximum.
2. The CCB clock is determined by the SYSCLK × platform PLL ratio.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
15
DDR SDRAM
6 DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8541E.
6.1
DDR SDRAM DC Electrical Characteristics
Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8541E.
Table 11. DDR SDRAM DC Electrical Characteristics
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
2.375
2.625
V
V
1
2
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
+ 0.18
MV
+ 0.04
REF
V
3
REF
REF
V
MV
GV + 0.3
V
—
—
4
IH
DD
Input low voltage
V
I
–0.3
MV
– 0.18
REF
V
IL
Output leakage current
–10
–15.2
15.2
—
10
μA
mA
mA
μA
OZ
OH
Output high current (V
= 1.95 V)
I
—
—
5
—
—
—
OUT
Output low current (V
= 0.35 V)
I
OL
OUT
MV
input leakage current
I
VREF
REF
Notes:
1. GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2. MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver. Peak-to-peak
REF
DD DD
may not exceed 2% of the DC value.
noise on MV
REF
3. V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
TT
equal to MV
. This rail should track variations in the DC level of MV
.
REF
REF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
Table 12 provides the DDR capacitance.
Table 12. DDR SDRAM Capacitance
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, MSYNC_IN
Delta input/output capacitance: DQ, DQS
Note:
C
6
8
pF
pF
1
1
IO
C
—
0.5
DIO
1. This parameter is sampled. GV = 2.5 V 0.125 V, f = 1 MHz, T = 25°C, V
= GV /2, V
(peak to peak) = 0.2 V.
DD
A
OUT
DD
OUT
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
16
DDR SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 13 provides the input AC timing specifications for the DDR SDRAM interface.
Table 13. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter
AC input low voltage
Symbol
Min
Max
– 0.31
REF
Unit
Notes
V
—
MV
V
V
—
—
1
IL
AC input high voltage
V
MV
+ 0.31
GV + 0.3
IH
REF
DD
MDQS—MDQ/MECC input skew per
byte
t
—
ps
DISKEW
For DDR = 333 MHz
For DDR < 266 MHz
750
1125
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 <= n <=
7) or ECC (MECC[{0...7}] if n = 8).
6.2.2
DDR SDRAM Output AC Timing Specifications
Table 14 and Table 15 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface.
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of 2.5 V 5%.
1
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
t
6
10
ns
2
MCK
Skew between any MCK to ADDR/CMD
t
ps
ns
ns
ns
3
4
4
4
AOSKEW
333 MHz
266 MHz
200 MHz
–1000
–1100
–1200
200
300
400
ADDR/CMD output setup with respect to MCK
t
t
t
—
—
—
DDKHAS
DDKHAX
DDKHCS
333 MHz
266 MHz
200 MHz
2.8
3.45
4.6
ADDR/CMD output hold with respect to MCK
333 MHz
266 MHz
200 MHz
2.0
2.65
3.8
MCS(n) output setup with respect to MCK
333 MHz
266 MHz
200 MHz
2.8
3.45
4.6
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
17
DDR SDRAM
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
At recommended operating conditions with GVDD of 2.5 V 5%.
1
Parameter
Symbol
Min
Max
Unit
Notes
MCS(n) output hold with respect to MCK
t
—
ns
4
DDKHCX
333 MHz
266 MHz
200 MHz
2.0
2.65
3.8
MCK to MDQS
t
ns
ps
5
6
DDKHMH
333 MHz
266 MHz
200 MHz
–0.9
–1.1
–1.2
0.3
0.5
0.6
MDQ/MECC/MDM output setup with respect to
MDQS
t
t
t
—
DDKHDS,
t
DDKLDS
333 MHz
266 MHz
200 MHz
900
900
1200
MDQ/MECC/MDM output hold with respect to
MDQS
—
ps
6
DDKHDX,
t
DDKLDX
333 MHz
266 MHz
200 MHz
900
900
1200
MDQS preamble start
MDQS epilogue end
Notes:
–0.5 × t
– 0.9
–0.5 × t
+0.3
ns
ns
7
7
DDKHMP
MCK
MCK
t
–0.9
0.3
DDKLME
1. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. Output hold time can be read as DDR timing
(first two letters of functional block)(reference)(state)(signal)(state)
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H) state until
t
DDKHAS
MCK
outputs (A) are setup (S) or output valid time. Also, t
symbolizes DDR timing (DD) for the time t
memory clock
DDKLDX
MCK
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control
Register. For the skew measurements referenced for t
address/command valid with the rising edge of MCK.
it is assumed that the clock adjustment is set to align the
AOSKEW
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle. The MCSx pins are separated from the ADDR/CMD (address and command) bus in the HW spec. This
was separated because the MCSx pins typically have different loadings than the rest of the address and command bus,
even though they have the same timings.
5. Note that t
follows the symbol conventions described in note 1. For example, t
describes the DDR timing
DDKHMH
DDKHMH
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). In the source synchronous mode,
MDQS can launch later than MCK by 0.3 ns at the maximum. However, MCK may launch later than MDQS by as much as
0.9 ns. t
can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source
DDKHMH
synchronous mode, this typically is set to the same delay as the clock adjust in the CLK_CNTL register. The timing
parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the
MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8541E.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8541E. Note that t
conventions described in note 1.
follows the symbol
DDKHMP
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
18
DDR SDRAM
Figure 4 shows the DDR SDRAM output timing for address skew with respect to any MCK.
MCK[n]
MCK[n]
t
MCK
t
AOSKEWmax)
ADDR/CMD
ADDR/CMD
CMD
NOOP
t
AOSKEW(min)
CMD
NOOP
Figure 4. Timing Diagram for t
Measurement
AOSKEW
Figure 5 shows the DDR SDRAM output timing diagram for the source synchronous mode.
MCK[n]
MCK[n]
t
MCK
t
,t
DDKHAS DDKHCS
t
,t
DDKHAX DDKHCX
ADDR/CMD
Write A0
NOOP
t
DDKHMP
t
DDKHMH
MDQS[n]
MDQ[x]
t
DDKLME
t
DDKHDS
t
DDKLDS
D0
D1
t
DDKLDX
t
DDKHDX
Figure 5. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
19
DUART
Figure 6 provides the AC test load for the DDR bus.
Output
GV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 6. DDR AC Test Load
Table 15. DDR SDRAM Measurement Conditions
Symbol
DDR
Unit
Notes
V
MV
0.31 V
V
V
1
2
TH
REF
V
0.5 × GV
DD
OUT
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
7 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8541E.
7.1
DUART DC Electrical Characteristics
Table 16 provides the DC electrical characteristics for the DUART interface of the MPC8541E.
Table 16. DUART DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
Low-level input voltage
Input current
V
V
≥ V (min) or
2
OV + 0.3
V
V
IH
OUT
OH
DD
V
V
≤ V (max)
–0.3
—
0.8
5
IL
OUT
OL
1
I
V
= 0 V or V = V
DD
μA
V
IN
IN
IN
High-level output voltage
V
OV = min,
OV – 0.2
—
OH
DD
DD
I
= –100 μA
OH
Low-level output voltage
V
OV = min, I = 100 μA
—
0.2
V
OL
DD
OL
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
20
Ethernet: Three-Speed, MII Management
7.2
DUART AC Electrical Specifications
Table 17 provides the AC timing parameters for the DUART interface of the MPC8541E.
Table 17. DUART AC Timing Specifications
Parameter
Value
/ 1048576
Unit
Notes
Minimum baud rate
Maximum baud rate
Oversample rate
Notes:
f
baud
baud
—
3
CCB_CLK
f
/ 16
1, 3
2, 3
CCB_CLK
16
1. Actual attainable baud rate is limited by the latency of interrupt processing.
th
2. The middle of a start bit is detected as the 8 sampled 0 after the 1-to-0 transition of the start
th
bit. Subsequent bit values are sampled each 16 sample.
3. Guaranteed by design.
8 Ethernet: Three-Speed, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII
management.
8.1
Three-Speed Ethernet Controller (TSEC)
(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), the
MII (media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent
interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and
MDC (management data clock). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII
and TBI interfaces can be operated at 3.3 V or 2.5 V. Whether the GMII, MII, or TBI interface is operated
at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI interfaces
follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device
Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in
Section 8.3, “Ethernet Management Interface Electrical Characteristics.”
8.1.1
TSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes
specified in Table 18 and Table 19. The potential applied to the input of a GMII, MII, TBI, RGMII, or
RTBI receiver may exceed the potential of the receiver’s power supply (for example, a GMII driver
powered from a 3.6-V supply driving V into a GMII receiver powered from a 2.5-V supply). Tolerance
OH
for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The RGMII
and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
21
Ethernet: Three-Speed, MII Management
Table 18. GMII, MII, and TBI DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage 3.3 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Note:
LV
—
3.13
2.40
GND
1.70
–0.3
—
3.47
V
V
DD
V
I
= –4.0 mA
LV = Min
LV + 0.3
OH
OH
DD
DD
V
I
= 4.0 mA
LV = Min
0.50
V
OL
OL
DD
V
—
—
—
—
LV + 0.3
V
IH
DD
V
I
0.90
40
V
IL
1
1
V
= LV
DD
μA
μA
IH
IN
I
V
= GND
–600
—
IL
IN
1. The symbol V , in this case, represents the LV symbol referenced in Table 1 and Table 2.
IN
IN
Table 19. GMII, MII, RGMII RTBI, and TBI DC Electrical Characteristics
Parameters
Symbol
LV
Min
Max
Unit
Supply voltage 2.5 V
Output high voltage (LV = Min, I = –1.0 mA)
2.37
2.00
2.63
V
V
DD
V
LV + 0.3
DD
OH
OH
DD
Output low voltage (LV = Min, I = 1.0 mA)
V
OL
GND – 0.3
1.70
0.40
V
DD
OL
Input high voltage (LV = Min)
V
LV + 0.3
V
DD
IH
DD
Input low voltage (LV = Min)
V
–0.3
0.70
10
V
DD
IL
1
Input high current (V
Input low current (V
= LV
)
I
—
μA
μA
IN
DD
IH
1
= GND)
I
–15
—
IN
IL
Note:
1. Note that the symbol V , in this case, represents the LV symbol referenced in Table 1and Table 2.
IN
IN
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
22
Ethernet: Three-Speed, MII Management
8.2
GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.2
GMII Transmit AC Timing Specifications
Table 20 provides the GMII transmit AC timing specifications.
Table 20. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GTX_CLK clock period
t
—
40
2.5
0.5
—
8.0
—
—
—
—
—
60
—
ns
%
GTX
GTX_CLK duty cycle
t
/t
GTXH GTX
GMII data TXD[7:0], TX_ER, TX_EN setup time
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK data clock rise and fall times
Notes:
t
ns
ns
ns
GTKHDV
t
5.0
1.0
GTKHDX
3
2,4
t
t
GTXR , GTXR
1. The symbols used for timing specifications herein follow the pattern t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes GMII
(first two letters of functional block)(reference)(state)(signal)(state)
GTKHDV
transmit timing (GT) with respect to the t
clock reference (K) going to the high state (H) relative to the time date input
GTX
signals (D) reaching the valid state (V) to state or setup time. Also, t
symbolizes GMII transmit timing (GT) with respect
GTKHDX
to the t
clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
GTX
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t represents the GMII(G) transmit (TX) clock. For rise and fall times,
GTX
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by characterization.
4. Guaranteed by design.
Figure 7 shows the GMII transmit AC timing diagram.
t
t
GTX
GTXR
GTX_CLK
t
t
GTXF
GTXH
TXD[7:0]
TX_EN
TX_ER
t
GTKHDX
t
GTKHDV
Figure 7. GMII Transmit AC Timing Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
23
Ethernet: Three-Speed, MII Management
8.2.2.1
GMII Receive AC Timing Specifications
Table 21 provides the GMII receive AC timing specifications.
Table 21. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period
t
—
40
2.0
0.5
—
8.0
—
—
—
—
—
60
—
ns
%
GRX
RX_CLK duty cycle
t
/t
GRXH GRX
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise and fall time
Note:
t
t
ns
ns
ns
GRDVKH
GRDXKH
—
2,3
t
, t
1.0
GRXR GRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
GRDVKH
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to
the t clock reference (K) going to the high state (H) or setup time. Also, t
with respect to the time data input signals (D) went invalid (X) relative to the t
symbolizes GMII receive timing (GR)
clock reference (K) going to the low (L)
RX
GRDXKL
GRX
state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing
the clock of a particular functional. For example, the subscript of t represents the GMII (G) receive (RX) clock. For rise
GRX
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Figure 8 provides the AC test load for TSEC.
Output
LV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 8. TSEC AC Test Load
Figure 9 shows the GMII receive AC timing diagram.
t
t
GRXR
GRX
RX_CLK
t
t
GRXF
GRXH
RXD[7:0]
RX_DV
RX_ER
t
GRDXKH
t
GRDVKH
Figure 9. GMII Receive AC Timing Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
24
Ethernet: Three-Speed, MII Management
8.2.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.3.1
MII Transmit AC Timing Specifications
Table 22 provides the MII transmit AC timing specifications.
Table 22. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
2
TX_CLK clock period 10 Mbps
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
—
—
35
1
400
40
—
5
—
—
ns
ns
%
MTX
t
MTX
t
t
65
15
4.0
MTXH/ MTX
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise and fall time
Notes:
t
ns
ns
MTKHDX
2,3
t
, t
1.0
—
MTXR MTXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
symbolizes MII transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid
MTX
(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock
of a particular functional. For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall
MTX
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Figure 10 shows the MII transmit AC timing diagram.
t
t
MTXR
MTX
TX_CLK
t
t
MTXF
MTXH
TXD[3:0]
TX_EN
TX_ER
t
MTKHDX
Figure 10. MII Transmit AC Timing Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
25
Ethernet: Three-Speed, MII Management
8.2.3.2
MII Receive AC Timing Specifications
Table 23 provides the MII receive AC timing specifications.
Table 23. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
2
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
—
—
400
40
—
—
—
ns
ns
%
MRX
t
MRX
t
/t
35
65
—
MRXH MRX
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise and fall time
Notes:
t
10.0
10.0
1.0
—
ns
ns
ns
MRDVKH
t
—
—
MRDXKH
2,3
t
, t
—
4.0
MRXR MRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference
MRX
(K) going to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data
MRDXKL
input signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in
MRX
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
MRX
used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 11 shows the MII receive AC timing diagram.
t
t
MRXR
MRX
RX_CLK
t
t
MRXF
MRXH
RXD[3:0]
RX_DV
RX_ER
Valid Data
t
MRDVKH
t
MRDXKH
Figure 11. MII Receive AC Timing Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
26
Ethernet: Three-Speed, MII Management
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
TBI Transmit AC Timing Specifications
Table 24 provides the MII transmit AC timing specifications.
Table 24. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GTX_CLK clock period
GTX_CLK duty cycle
t
—
40
8.0
—
—
60
—
ns
%
TTX
t
/t
TTXH TTX
GMII data TCG[9:0], TX_ER, TX_EN setup time
GTX_CLK going high
t
2.0
—
ns
TTKHDV
GMII data TCG[9:0], TX_ER, TX_EN hold time from
GTX_CLK going high
t
1.0
—
—
—
—
ns
ns
TTKHDX
2,3
GTX_CLK clock rise and fall time
t
, t
1.0
TTXR TTXF
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state
for inputs and t
for outputs. For example, t
)(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
TTKHDV
symbolizes the TBI transmit timing (TT) with respect to the time from t
(K) going high (H) until the referenced data
TTX
signals (D) reach the valid state (V) or setup time. Also, t
symbolizes the TBI transmit timing (TT) with respect to the
TTKHDX
time from t
(K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in
TTX
general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter
TTX
convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Figure 12 shows the TBI transmit AC timing diagram.
t
t
TTXR
TTX
GTX_CLK
t
TTXH
t
TTXF
t
TTXF
TCG[9:0]
t
t
TTXR
TTKHDV
t
TTKHDX
Figure 12. TBI Transmit AC Timing Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
27
Ethernet: Three-Speed, MII Management
8.2.4.2
TBI Receive AC Timing Specifications
Table 25 provides the TBI receive AC timing specifications.
Table 25. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period
t
16.0
—
ns
ns
%
TRX
RX_CLK skew
t
7.5
40
8.5
60
—
SKTRX
RX_CLK duty cycle
t
/t
—
TRXH TRX
RCG[9:0] setup time to rising RX_CLK
RCG[9:0] hold time to rising RX_CLK
RX_CLK clock rise time and fall time
Note:
t
2.5
1.5
0.7
—
ns
ns
ns
TRDVKH
TRDXKH
t
—
—
2,3
t
, t
—
2.4
TRXR TRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
TRDVKH
symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the
clock reference (K) going to the high (H) state or setup time. Also, t symbolizes TBI receive timing (TR) with
t
TRX
TRDXKH
respect to the time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state.
TRX
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t represents the TBI (T) receive (RX) clock. For rise and fall times,
TRX
the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is
skew (SK) followed by the clock that is being skewed (TRX).
2. Guaranteed by design.
Figure 13 shows the TBI receive AC timing diagram.
t
t
TRXR
TRX
RX_CLK1
RXD[9:0]
t
t
TRXF
TRXH
Valid Data
Valid Data
t
TRDVKH
t
t
SKTRX
TRDXKH
RX_CLK0
t
t
TRDXKH
TRXH
t
TRDVKH
Figure 13. TBI Receive AC Timing Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
28
Ethernet: Three-Speed, MII Management
8.2.5
RGMII and RTBI AC Timing Specifications
Table 26 presents the RGMII and RTBI AC timing specifications.
Table 26. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
5
Data to clock output skew (at transmitter)
t
–500
1.0
7.2
45
0
500
2.8
8.8
55
ps
ns
ns
%
SKRGT
2
Data to clock input skew (at receiver)
t
—
SKRGT
3
6
Clock cycle duration
t
8.0
50
50
—
RGT
4
6
6
Duty cycle for 1000Base-T
t
t
/t
RGTH RGT
3
Duty cycle for 10BASE-T and 100BASE-TX
/t
40
60
%
RGTH RGT
6,7
6,7
Rise and fall times
t
t
—
0.75
ns
RGTR , RGTF
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note also that the
RGT
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. The RGMII specification requires that PC board designer add 1.5 ns or greater in trace delay to the RX_CLK in order to
meet this specification. However, as stated above, this device functions with only 1.0 ns of delay.
3. For 10 and 100 Mbps, t
scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
RGT
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three t
transitioned between.
of the lowest speed
RGT
5. Guaranteed by characterization.
6. Guaranteed by design.
7. Signal timings are measured at 0.5 and 2.0 V voltage levels.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
29
Ethernet: Three-Speed, MII Management
Figure 14 shows the RBMII and RTBI AC timing and multiplexing diagrams.
t
RGT
t
RGTH
GTX_CLK
(At Transmitter)
t
SKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
t
SKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
t
SKRGT
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
t
SKRGT
RX_CLK
(At PHY)
Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller (TSEC)
(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics.”
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics
for MDIO and MDC are provided in Table 27.
Table 27. MII Management DC Electrical Characteristics
Parameter
Symbol
OV
Conditions
Min
Max
Unit
Supply voltage (3.3 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
—
3.13
2.10
GND
1.70
—
3.47
V
V
V
V
V
DD
V
I
= –1.0 mA
= 1.0 mA
LV = Min
LV + 0.3
OH
OH
DD
DD
V
I
LV = Min
0.50
—
OL
OL
DD
V
—
—
IH
V
0.90
IL
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
30
Ethernet: Three-Speed, MII Management
Table 27. MII Management DC Electrical Characteristics (continued)
Parameter
Input high current
Symbol
Conditions
Min
Max
Unit
1
I
LV = Max
V
= 2.1 V
V = 0.5 V
IN
—
40
—
μA
μA
IH
DD
IN
Input low current
I
LV = Max
–600
IL
DD
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
8.3.2
MII Management AC Electrical Specifications
Table 28 provides the MII management AC timing specifications.
Table 28. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V 5%.
1
Parameter/Condition
MDC frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
0.893
96
—
—
—
10.4
1120
—
MHz
ns
2
MDC
MDC period
MDC
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
t
32
ns
MDCH
t
2*[1/(f
/8)]
/8)]
ns
3
3
MDKHDV
MDKHDX
ccb_clk
t
10
5
—
—
—
—
—
2*[1/(f
ns
ccb_clk
t
—
ns
MDDVKH
MDDXKH
t
0
—
10
10
ns
t
—
—
ns
MDCR
MDC fall time
t
ns
MDHF
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MDKHDX
symbolizes management data timing (MD) for the time t
from clock reference (K) high (H) until data outputs (D) are
MDC
invalid (X) or data hold time. Also, t
symbolizes management data timing (MD) with respect to the time data input
MDDVKH
signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup time. For
MDC
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the delay is 70 ns and for
a system clock of 333 MHz, the delay is 58 ns).
3. This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
CCB clock of 333 MHz, the delay is 48 ns).
4. Guaranteed by design.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
31
Local Bus
Figure 15 shows the MII management AC timing diagram.
t
t
MDCR
MDC
MDC
t
t
MDCF
MDCH
MDIO
(Input)
t
MDDVKH
t
MDDXKH
MDIO
(Output)
t
MDKHDX
Figure 15. MII Management Interface Timing Diagram
9 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8541E.
9.1
Local Bus DC Electrical Characteristics
Table 29 provides the DC electrical characteristics for the local bus interface.
Table 29. Local Bus DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
Low-level input voltage
Input current
V
V
≥ V (min) or
2
OV + 0.3
V
V
IH
OUT
OH
DD
V
V
≤ V (max)
–0.3
—
0.8
5
IL
OUT
OL
1
I
V
= 0 V or V = V
DD
μA
V
IN
IN
IN
High-level output voltage
V
OV = min,
OV –0.2
—
OH
DD
DD
I
= –2mA
OH
Low-level output voltage
V
OV = min, I = 2mA
—
0.2
V
OL
DD
OL
Note:
1. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
32
Local Bus
9.2
Local Bus AC Electrical Specifications
Table 30 describes the general timing parameters of the local bus interface of the MPC8541E with the DLL
enabled.
Table 30. Local Bus General Timing Parameters—DLL Enabled
7
1
Parameter
Local bus cycle time
Configuration
Symbol
Min
Max
Unit
Notes
t
6.0
—
—
150
—
ns
ps
ns
2
LBK
LCLK[n] skew to LCLK[m] or LSYNC_OUT
t
7, 9
LBKSKEW
Input setup to local bus clock (except
LUPWAIT)
t
1.8
3, 4, 8
LBIVKH1
LUPWAIT input setup to local bus clock
t
t
1.7
0.5
—
—
ns
ns
3, 4
LBIVKH2
Input hold from local bus clock (except
LUPWAIT)
3, 4, 8
LBIXKH1
LUPWAIT input hold from local bus clock
t
1.0
1.5
—
—
ns
ns
3, 4
6
LBIXKH2
LALE output transition to LAD/LDP output
transition (LATCH hold time)
t
LBOTOT
Local bus clock to output valid (except
LAD/LDP and LALE)
LWE[0:1] = 00
t
—
—
—
2.3
3.8
2.5
4.0
2.6
4.1
—
ns
ns
ns
ns
ns
ns
3, 8
3, 8
3, 8
3, 8
3, 8
5, 9
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOX1
LBKHOX2
LBKHOZ1
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
t
t
t
t
t
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Output hold from local bus clock (except
LAD/LDP and LALE)
0.7
1.6
0.7
1.6
—
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Output hold from local bus clock for
LAD/LDP
—
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
2.8
4.2
LWE[0:1] = 11 (default)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
33
Local Bus
Table 30. Local Bus General Timing Parameters—DLL Enabled (continued)
7
1
Parameter
Configuration
Symbol
Min
Max
Unit
Notes
Local bus clock to output high impedance for
LAD/LDP
LWE[0:1] = 00
t
—
2.8
4.2
ns
5, 9
LBKHOZ2
LWE[0:1] = 11 (default)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes
clock reference (K) to go
LBK
LBK
high (H), in this case for clock one(1). Also, t
symbolizes local bus timing (LB) for the t
LBKHOX
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OV /2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OV of the signal in
DD
DD
question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of t
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of
LBOTOT
local bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OV /2.
DD
8. Guaranteed by characterization.
9. Guaranteed by design.
Table 31 describes the general timing parameters of the local bus interface of the MPC8541E with the DLL
bypassed.
Table 31. Local Bus General Timing Parameters—DLL Bypassed
7
1
Parameter
Local bus cycle time
Configuration
Symbol
Min
Max
Unit
Notes
—
—
—
—
t
6.0
1.8
—
—
3.4
150
—
ns
ns
ps
ns
2
LBK
Internal launch/capture clock to LCLK delay
LCLK[n] skew to LCLK[m] or LSYNC_OUT
t
8
LBKHKT
t
7, 9
3, 4
LBKSKEW
Input setup to local bus clock (except
LUPWAIT)
t
5.2
LBIVKH1
LUPWAIT input setup to local bus clock
—
—
t
t
5.1
—
—
ns
ns
3, 4
3, 4
LBIVKH2
Input hold from local bus clock (except
LUPWAIT)
–1.3
LBIXKH1
LUPWAIT input hold from local bus clock
—
—
t
–0.8
1.5
—
—
ns
ns
3, 4
6
LBIXKH2
LALE output transition to LAD/LDP output
transition (LATCH hold time)
t
LBOTOT
Local bus clock to output valid (except
LAD/LDP and LALE)
LWE[0:1] = 00
t
—
—
0.5
2.0
0.7
2.2
ns
ns
3
3
LBKLOV1
LBKLOV2
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Local bus clock to data valid for LAD/LDP
t
LWE[0:1] = 11 (default)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
34
Local Bus
Table 31. Local Bus General Timing Parameters—DLL Bypassed (continued)
7
1
Parameter
Configuration
Symbol
Min
Max
Unit
Notes
Local bus clock to address valid for LAD
LWE[0:1] = 00
t
t
t
t
t
—
0.8
2.3
—
ns
3
LBKLOV3
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Output hold from local bus clock (except
LAD/LDP and LALE)
–2.7
–1.8
–2.7
–1.8
—
ns
ns
ns
ns
3
3
5
5
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Output hold from local bus clock for LAD/LDP
—
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
1.0
2.4
1.0
2.4
LWE[0:1] = 11 (default)
LWE[0:1] = 00
Local bus clock to output high impedance for
LAD/LDP
—
LWE[0:1] = 11 (default)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local bus
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this case for
LBK
clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with respect to the
LBKHOX
LBK
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OV /2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OV of the signal
DD
DD
in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of t
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
LBOTOT
bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OV /2.
DD
8. Guaranteed by characterization.
9. Guaranteed by design.
Figure 16 provides the AC test load for the local bus.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 16. Local Bus C Test Load
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
35
Local Bus
Figure 17 to Figure 22 show the local bus signals.
LSYNC_IN
t
t
LBIXKH1
LBIXKH1
t
t
t
t
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
LBIVKH1
Input Signal:
LGTA
t
LBKHOZ1
LBKHOX1
t
LBKHOV1
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
LBKHOZ2
LBKHOX2
t
LBKHOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ2
t
LBKHOX2
LBKHOV3
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
LALE
Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
36
Freescale Semiconductor
Local Bus
Internal launch/capture clock
LCLK[n]
t
LBKHKT
t
LBIVKH1
t
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIVKH2
Input Signal:
LGTA
t
LBIXKH2
t
LBKLOV1
t
t
LBKLOZ1
t
LBKLOX1
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
LBKLOZ2
LBKLOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
t
LBKLOX2
LBKLOV3
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
LALE
Figure 18. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
37
Local Bus
LSYNC_IN
T1
T3
t
LBKHOZ1
t
LBKHOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
t
LBIXKH2
t
t
LBIVKH2
UPM Mode Input Signal:
LUPWAIT
LBIXKH1
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ1
t
LBKHOV1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
38
Local Bus
t
Internal launch/capture clock
LBKHKT
T1
T3
LCLK
t
t
LBKLOX1
LBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBKLOZ1
t
LBIVKH2
t
t
LBIXKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
39
Local Bus
LSYNC_IN
T1
T2
T3
T4
t
LBKHOZ1
t
LBKHOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBIXKH2
t
LBIVKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH1
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ1
t
LBKHOV1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Enabled)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
40
Local Bus
t
Internal launch/capture clock
LBKHKT
T1
T2
T3
T4
LCLK
t
t
LBKLOX1
LBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBKLOZ1
t
LBIVKH2
t
t
LBIXKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Bypass Mode)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
41
CPM
10 CPM
This section describes the DC and AC electrical specifications for the CPM of the MPC8541E.
10.1 CPM DC Electrical Characteristics
Table 32 provides the DC electrical characteristics for the CPM.
Table 32. CPM DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
Notes
V
2.0
GND
2.4
—
3.465
0.8
—
V
V
V
V
V
V
1
1, 2
1
IH
Input low voltage
V
IL
Output high voltage
Output low voltage
Output high voltage
Output low voltage
V
I
I
= –8.0 mA
OH
OH
V
I
= 8.0 mA
OL
0.5
—
1
OL
OH
OL
V
V
= –2.0 mA
= 3.2 mA
2.4
—
1
OH
I
0.4
1
OL
10.2 CPM AC Timing Specifications
Table 33 and Table 34 provide the CPM input and output AC timing specifications, respectively.
NOTE: Rise/Fall Time on CPM Input Pins
It is recommended that the rise/fall time on CPM input pins should not
exceed 5 ns. This should be enforced especially on clock signals. Rise time
refers to signal transitions from 10% to 90% of VCC; fall time refers to
transitions from 90% to 10% of VCC.
1
Table 33. CPM Input AC Timing Specifications
2
3
Characteristic
Symbol
Min
Unit
FCC inputs—internal clock (NMSI) input setup time
FCC inputs—internal clock (NMSI) hold time
FCC inputs—external clock (NMSI) input setup time
FCC inputs—external clock (NMSI) hold time
SPI inputs—internal clock (NMSI) input setup time
SPI inputs—internal clock (NMSI) input hold time
SPI inputs—external clock (NMSI) input setup time
SPI inputs—external clock (NMSI) input hold time
PIO inputs—input setup time
t
t
6
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIIVKH
FIIXKH
t
2.5
2
FEIVKH
t
b
FEIXKH
t
t
6
NIIVKH
NIIXKH
0
t
4
NEIVKH
NEIXKH
t
2
t
8
PIIVKH
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
42
CPM
1
Table 33. CPM Input AC Timing Specifications (continued)
2
3
Characteristic
Symbol
Min
Unit
PIO inputs—input hold time
COL width high (FCC)
Notes:
t
1
ns
PIIXKH
t
1.5
CLK
FCCH
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings
are measured at the pin.
2. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
FIIVKH
symbolizes the FCC inputs internal timing (FI) with respect to the time the input signals (I) reaching the valid state (V)
relative to the reference clock t (K) going to the high (H) state or setup time.
FCC
3. PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock. PIO/TIMER inputs
are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be treated as asynchronous.
1
Table 34. CPM Output AC Timing Specifications
2
Characteristic
Symbol
Min
Max
Unit
FCC outputs—internal clock (NMSI) delay
FCC outputs—external clock (NMSI) delay
SPI outputs—internal clock (NMSI) delay
SPI outputs—external clock (NMSI) delay
PIO outputs delay
t
1
2
5.5
8
ns
ns
ns
ns
ns
FIKHOX
t
FEKHOX
t
0.5
2
10
8
NIKHOX
t
NEKHOX
t
1
11
PIKHOX
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. For example, t
symbolizes the FCC
(first two letters of functional block)(reference)(state)(signal)(state)
FIKHOX
inputs internal timing (FI) for the time t
invalid (X).
memory clock reference (K) goes from the high state (H) until outputs (O) are
FCC
Figure 23 provides the AC test load for the CPM.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 23. CPM AC Test Load
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
43
CPM
Figure 24 through Figure 29 represent the AC timing from Table 33 and Table 34. Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
Figure 24 shows the FCC internal clock.
BRG_OUT
t
FIIXKH
t
FIIVKH
FCC Input Signals
t
FIKHOX
FCC Output Signals
(When GFMR TCI = 0)
t
FIKHOX
FCC Output Signals
(When GFMR TCI = 1)
Figure 24. FCC Internal AC Timing Clock Diagram
Figure 25 shows the FCC external clock.
Serial CLKIN
t
FEIXKH
t
FEIVKH
FCC Input Signals
t
FEKHOX
FCC Output Signals
(When GFMR TCI = 0)
t
FEKHOX
FCC Output Signals
(When GFMR TCI = 1)
Figure 25. FCC External AC Timing Clock Diagram
Figure 26 shows Ethernet collision timing on FCCs.
COL
(Input)
t
FCCH
Figure 26. Ethernet Collision AC Timing Diagram (FCC)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
44
Freescale Semiconductor
CPM
Figure 27 shows the SPI external clock.
Serial CLKIN
t
NEIXKH
t
NEIVKH
Input Signals:
SPI
(See Note)
t
NEKHOX
Output Signals:
SPI
(See Note)
Note:
The clock edge is selectable on SPI.
Figure 27. SPI AC Timing External Clock Diagram
Figure 28 shows the SPI internal clock.
BRG_OUT
t
NIIXKH
t
NIIVKH
Input Signals:
SPI
(See Note)
t
NIKHOX
Output Signals:
SPI
(See Note)
Note:
The clock edge is selectable on SPI.
Figure 28. SPI AC Timing Internal Clock Diagram
NOTE
1
SPI AC timings are internal mode when it is master because SPICLK is an
output, and external mode when it is slave.
2 SPI AC timings refer always to SPICLK.
Sys clk
t
PIIXKH
t
PIIVKH
PIO inputs
t
PIKHOX
PIO outputs
Figure 29. PIO Signal Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
45
CPM
10.3 CPM I2C AC Specification
Table 35. I2C Timing
All Frequencies
Characteristic
Expression
Unit
Min
Max
(1)
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
f
0
F
Hz
Hz
s
SCL
MAX
f
BRGCLK/16512
BRGCLK/48
SCL
t
t
t
t
1/(2.2 * f
1/(2.2 * f
1/(2.2 * f
)
)
)
—
—
SDHDL
SCLCH
SCHCL
SCHDL
SCL
SCL
SCL
s
High period of SCL
—
(2)
s
2
Start condition setup time
2/(divider * f
3/(divider * f
2/(divider * f
3/(divider * f
—
)
)
)
)
s
SCL
SCL
SCL
SCL
2
Start condition hold time
t
—
—
—
s
SDLCL
SCLDX
SDVCH
2
Data hold time
t
s
2
Data setup time
t
s
SDA/SCL rise time
SDA/SCL fall time
Stop condition setup time
Notes:
t
1/(10 * f
1/(33 * f
—
)
s
SRISE
SFALL
SCL
t
—
)
s
SCL
t
2/(divider * f
)
s
SCHDH
SCL
1.
F
= BRGCLK/(min_divider*prescale. Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter disabled
MAX
and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then FMAX=BRGCLK/576
2. divider = f
/prescaler.
SCL
In master mode: divider=BRGCLK/(f
*prescaler)=2*(I2BRG[DIV]+3)
SCL
In slave mode: divider=BRGCLK/(f
*prescaler)
SCL
SDA
t
t
SCHCL
t
SCLCH
SDHDL
t
t
SDVCH
t
SCLDX
SCHDL
SCL
t
t
t
t
SCHDH
SDLCL
SRISE
SFALL
Figure 30. CPM I2C Bus Timing Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
46
CPM
The following two tables are examples of I2C AC parameters at I2C clock value of 100k and 400k
respectively.
Table 36. CPM I2C Timing (f
=100 kHz)
SCL
Frequency = 100 kHz
Characteristic
SCL clock frequency (slave)
Expression
Unit
Min
Max
f
f
—
—
4.7
4.7
4
100
100
—
kHz
kHz
μs
μs
μs
μs
μs
μs
μs
μs
ns
SCL
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
SCL
t
t
t
t
SDHDL
SCLCH
SCHCL
SCHDL
—
High period of SCL
—
Start condition setup time
Start condition hold time
Data hold time
2
—
t
3
—
SDLCL
t
t
2
—
SCLDX
Data setup time
3
—
SDVCH
SDA/SCL rise time
t
—
—
2
1
SRISE
SDA/SCL fall time (master)
Stop condition setup time
t
303
—
SFALL
t
μs
SCHDH
Table 37. CPM I2C Timing (f
Expression
=400 kHz)
SCL
Frequency = 400 kHz
Min Max
Characteristic
Unit
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
f
f
—
—
400
400
—
kHz
kHz
μs
μs
μs
ns
SCL
SCL
t
t
t
t
1.2
1.2
1
SDHDL
SCLCH
SCHCL
SCHDL
—
High period of SCL
—
Start condition setup time
Start condition hold time
Data hold time
420
630
420
630
—
—
t
—
ns
SDLCL
SCLDX
SDVCH
t
—
ns
Data setup time
t
—
ns
SDA/SCL rise time
t
250
75
—
ns
SRISE
SFALL
SDA/SCL fall time
t
—
ns
Stop condition setup time
t
420
ns
SCHDH
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
47
JTAG
11 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8541E.
Table 38 provides the JTAG AC timing specifications as defined in Figure 32 through Figure 35.
1
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 2).
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
f
0
33.3
—
MHz
ns
—
—
—
—
3
JTG
t
30
15
0
JTG
t
—
ns
JTKHKL
t
& t
2
ns
JTGR
JTGF
t
25
—
ns
TRST
Input setup times:
ns
Boundary-scan data
t
t
4
0
—
—
4
4
JTDVKH
TMS, TDI
JTIVKH
Input hold times:
Valid times:
ns
ns
ns
ns
Boundary-scan data
TMS, TDI
t
20
25
—
—
JTDXKH
t
JTIXKH
Boundary-scan data
TDO
t
t
4
4
20
25
5
JTKLDV
JTKLOV
Output hold times:
Boundary-scan data
TDO
t
t
—
—
—
—
5
JTKLDX
JTKLOX
JTAG external clock to output high impedance:
Boundary-scan data
TDO
t
t
3
3
19
9
5, 6
JTKLDZ
JTKLOZ
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
to the midpoint of the signal in
TCLK
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Figure 31). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
JTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
clock reference (K) going to the high (H) state or setup time. Also, t symbolizes JTAG timing (JT) with respect to
t
JTG
JTDXKH
the time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that,
JTG
in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
.
TCLK
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design.
.
TCLK
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
48
JTAG
Figure 31 provides the AC test load for TDO and the boundary-scan outputs of the MPC8541E.
Z = 50 Ω
OV /2
Output
0
DD
R = 50 Ω
L
Figure 31. AC Test Load for the JTAG Interface
Figure 32 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
t
VM
VM
t
JTGR
JTKHKL
t
t
JTGF
JTG
VM = Midpoint Voltage (OV /2)
DD
Figure 32. JTAG Clock Input Timing Diagram
Figure 33 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (OV /2)
DD
Figure 33. TRST Timing Diagram
Figure 34 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
Input
Data Valid
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
Output Data Valid
t
JTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 34. Boundary-Scan Timing Diagram
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
49
I2C
Figure 35 provides the test access port timing diagram.
JTAG
External Clock
VM
VM
t
JTIVKH
t
JTIXKH
Input
TDI, TMS
TDO
Data Valid
t
JTKLOV
t
JTKLOX
Output Data Valid
t
JTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 35. Test Access Port Timing Diagram
12 I2C
2
This section describes the DC and AC electrical characteristics for the I C interface of the MPC8541E.
2
12.1 I C DC Electrical Characteristics
2
Table 39 provides the DC electrical characteristics for the I C interface of the MPC8541E.
2
Table 39. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
Input low voltage level
Low level output voltage
V
0.7 × OV
–0.3
0
OV + 0.3
V
V
—
—
1
IH
DD
DD
V
0.3 × OV
IL
DD
V
0.2 × OV
V
OL
DD
Output fall time from V (min) to V (max) with a bus
capacitance from 10 to 400 pF
t
20 + 0.1 × C
B
250
ns
2
IH
IL
I2KLKV
Pulse width of spikes which must be suppressed by the
input filter
t
0
50
ns
μA
pF
3
4
I2KHKL
Input current each I/O pin (input voltage is between 0.1 ×
OV and 0.9 × OV (max)
I
–10
—
10
I
DD
DD
Capacitance for each I/O pin
C
10
—
I
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C = capacitance of one bus line in pF.
B
3. Refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for information on the
digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OV is switched off.
DD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
50
Freescale Semiconductor
I2C
2
12.2 I C AC Electrical Specifications
2
Table 40 provides the AC timing parameters for the I C interface of the MPC8541E.
2
Table 40. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 39).
1
Parameter
Symbol
Min
Max
Unit
SCL clock frequency
f
0
400
—
kHz
μs
I2C
6
Low period of the SCL clock
High period of the SCL clock
t
1.3
0.6
0.6
0.6
I2CL
6
t
—
μs
I2CH
6
Setup time for a repeated START condition
t
—
μs
I2SVKH
6
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
t
—
μs
I2SXKL
6
Data setup time
t
100
—
—
—
ns
I2DVKH
Data hold time:
t
μs
I2DXKL
CBUS compatible masters
2
2
3
I C bus devices
0
0.9
4
4
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
t
20 + 0.1 C
20 + 0.1 C
0.6
300
300
—
ns
ns
μs
μs
V
I2CR
b
b
t
I2CF
t
I2PVKH
Bus free time between a STOP and START condition
t
1.3
—
I2KHDX
Noise margin at the LOW level for each connected device (including
hysteresis)
V
0.1 × OV
—
NL
DD
DD
Noise margin at the HIGH level for each connected device (including
hysteresis)
V
0.2 × OV
—
V
NH
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
2
for inputs and t
for outputs. For example, t
symbolizes I C timing
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the
I2C
2
high (H) state or setup time. Also, t
symbolizes I C timing (I2) for the time that the data with respect to the start
I2SXKL
condition (S) went invalid (X) relative to the t
symbolizes I C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative
clock reference (K) going to the low (L) state or hold time. Also, t
I2C
I2PVKH
2
to the t clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used
I2C
with the appropriate letter: R (rise) or F (fall).
2. MPC8541E provides a hold time of at least 300 ns for the SDA signal (referred to the V
undefined region of the falling edge of SCL.
of the SCL signal) to bridge the
IHmin
3. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2DVKH
I2CL
4. C = capacitance of one bus line in pF.
B
5. Guaranteed by design.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
51
PCI
2
Figure 16 provides the AC test load for the I C.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
2
Figure 36. I C AC Test Load
2
Figure 37 shows the AC timing diagram for the I C bus.
SDA
t
t
t
t
I2CF
I2CF
I2DVKH
I2KHKL
t
t
t
I2CR
I2CL
I2SXKL
SCL
t
t
t
t
I2PVKH
I2SXKL
I2CH
I2SVKH
t
I2DXKL
S
Sr
P
S
2
Figure 37. I C Bus AC Timing Diagram
13 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8541E.
13.1 PCI DC Electrical Characteristics
Table 41 provides the DC electrical characteristics for the PCI interface of the MPC8541E.
1
Table 41. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
Low-level input voltage
Input current
V
V
≥ V (min) or
2
OV + 0.3
V
V
IH
OUT
OH
DD
V
V
≤ V (max)
–0.3
—
0.8
5
IL
OUT
OL
2
I
V
= 0 V or V = V
DD
μA
V
IN
IN
IN
High-level output voltage
V
OV = min,
OV – 0.2
—
OH
DD
DD
I
= –100 μA
OH
Low-level output voltage
V
OV = min,
—
0.2
V
OL
DD
I
= 100 μA
OL
Notes:
1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications.
2. Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
52
PCI
13.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the MPC8541E. Note that the
SYSCLK signal is used as the PCI input clock. Table 42 provides the PCI AC timing specifications at 66
MHz.
NOTE
PCI Clock can be PCI1_CLK or SYSCLK based on POR config input.
NOTE
The input setup time does not meet the PCI specification.
Table 42. PCI AC Timing Specifications at 66 MHz
1
Parameter
Symbol
Min
Max
Unit
Notes
Clock to output valid
t
—
2.0
6.0
—
14
—
—
—
50
—
ns
ns
2, 3
2, 9
PCKHOV
Output hold from Clock
t
PCKHOX
Clock to output high impedance
Input setup to Clock
t
—
ns
2, 3, 10
2, 4, 9
2, 4, 9
5, 6, 10
6, 10
PCKHOZ
t
3.3
ns
PCIVKH
Input hold from Clock
t
0
ns
PCIXKH
9
REQ64 to HRESET setup time
t
10 × t
clocks
ns
PCRVRH
PCRHRX
SYS
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Notes:
t
0
t
10
clocks
7, 10
PCRHFV
1. Note that the symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
PCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK
clock, t , reference (K) going to the high (H) state or setup time. Also, t symbolizes PCI timing (PC) with respect to
SYS
PCRHFV
the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The timing parameter t
indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
SYS
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 15, “Clocking.”
6. The setup and hold time is with respect to the rising edge of HRESET.
7. The timing parameter t
Specifications.
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
PCRHFV
8. The reset assertion timing requirement for HRESET is 100 μs.
9. Guaranteed by characterization.
10.Guaranteed by design.
Figure 16 provides the AC test load for PCI.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 38. PCI AC Test Load
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
53
Package and Pin Listings
Figure 39 shows the PCI input AC timing conditions.
CLK
t
PCIVKH
t
PCIXKH
Input
Figure 39. PCI Input AC Timing Measurement Conditions
Figure 40 shows the PCI output AC timing conditions.
CLK
t
PCKHOV
Output Delay
t
PCKHOZ
High-Impedance
Output
Figure 40. PCI Output AC Timing Measurement Condition
14 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions.
14.1 Package Parameters for the MPC8541E FC-PBGA
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783
flip chip plastic ball grid array (FC-PBGA).
Die size
8.7 mm × 9.3 mm × 0.75 mm
Package outline
Interconnects
Pitch
29 mm × 29 mm
783
1 mm
Minimum module height 3.07 mm
Maximum module height 3.75 mm
Solder Balls
62 Sn/36 Pb/2 Ag
0.5 mm
Ball diameter (typical)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
54
Package and Pin Listings
14.2 Mechanical Dimensions of the FC-PBGA
Figure 41 the mechanical dimensions and bottom surface nomenclature of the MPC8541E 783 FC-PBGA
package.
Figure 41. Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA
Notes:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
5. Capacitors may not be present on all devices.
6. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top.
7. The socket lid must always be oriented to A1.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
55
Package and Pin Listings
14.3 Pinout Listings
Table 43 provides the pin-out listing for the MPC8541E, 783 FC-PBGA package.
Table 43. MPC8541E Pinout Listing
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
PCI1 and PCI2 (one 64-bit or two 32-bit)
PCI1_AD[63:32],
PCI2_AD[31:0]
AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14,
V15, W15, Y15, AA15, AB15, AC15, AD15, AG15,
AH15, V16, W16, AB16, AC16, AD16, AE16, AF16,
V17, W17, Y17, AA17, AB17, AE17, AF17, AF18
I/O
OV
OV
17
DD
DD
PCI1_AD[31:0]
AH6, AD7, AE7, AH7, AB8, AC8, AF8, AG8, AD9,
AE9, AF9, AG9, AH9, W10, Y10, AA10, AE11, AF11,
AG11, AH11, V12, W12, Y12, AB12, AD12, AE12,
AG12, AH12, V13, Y13, AB13, AC13
I/O
17
PCI_C_BE64[7:4]
PCI2_C_BE[3:0]
AG13, AH13, V14, W14
I/O
I/O
OV
OV
17
17
DD
DD
PCI_C_BE64[3:0]
PCI1_C_BE[3:0]
AH8, AB10, AD11, AC12
PCI1_PAR
AA11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
—
—
2
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
PCI1_PAR64/PCI2_PAR
PCI1_FRAME
PCI1_TRDY
Y14
AC10
AG10
2
PCI1_IRDY
AD10
2
PCI1_STOP
V11
2
PCI1_DEVSEL
PCI1_IDSEL
AH10
2
AA9
—
5, 10
2
PCI1_REQ64/PCI2_FRAME
PCI1_ACK64/PCI2_DEVSEL
PCI1_PERR
AE13
I/O
I/O
I/O
I/O
I/O
I
AD13
W11
2
PCI1_SERR
Y11
2, 4
—
—
—
5, 9
—
—
—
PCI1_REQ[0]
AF5
AF3, AE4, AG4, AE5
AE6
PCI1_REQ[1:4]
PCI1_GNT[0]
I/O
O
PCI1_GNT[1:4]
PCI1_CLK
AG5, AH5, AF6, AG6
AH25
I
PCI2_CLK
AH27
I
PCI2_GNT[0]
AC18
I/O
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
56
Package and Pin Listings
Table 43. MPC8541E Pinout Listing (continued)
Power
Notes
Signal
PCI2_GNT[1:4]
Package Pin Number
Pin Type
Supply
AD18, AE18, AE19, AD19
O
I
OV
OV
OV
OV
OV
OV
OV
OV
OV
5, 9
—
2
DD
DD
DD
DD
DD
DD
DD
DD
DD
PCI2_IDSEL
PCI2_IRDY
AC22
AD20
I/O
I/O
I/O
I
PCI2_PERR
PCI2_REQ[0]
PCI2_REQ[1:4]
PCI2_SERR
PCI2_STOP
PCI2_TRDY
AC20
2
AD21
—
—
2,4
2
AE21, AD22, AE22, AC23
AE20
AC21
AC19
I/O
I/O
I/O
2
DDR SDRAM Memory Interface
MDQ[0:63]
M26, L27, L22, K24, M24, M23, K27, K26, K22, J28,
F26, E27, J26, J23, H26, G26, C26, E25, C24, E23,
D26, C25, A24, D23, B23, F22, J21, G21, G22, D22,
H21, E21, N18, J18, D18, L17, M18, L18, C18, A18,
K17, K16, C16, B16, G17, L16, A16, L15, G15, E15,
C14, K13, C15, D15, E14, D14, D13, E13, D12, A11,
F13, H13, A13, B12
I/O
GV
—
DD
MECC[0:7]
MDM[0:8]
MDQS[0:8]
MBA[0:1]
MA[0:14]
N20, M20, L19, E19, C21, A21, G19, A19
L24, H28, F24, L21, E18, E16, G14, B13, M19
L26, J25, D25, A22, H18, F16, F14, C13, C20
B18, B19
I/O
O
GV
GV
GV
GV
GV
—
—
—
—
—
DD
DD
DD
DD
DD
I/O
O
N19, B21, F21, K21, M21, C23, A23, B24, H23, G24,
K19, B25, D27, J14, J13
O
MWE
D17
O
O
O
O
O
O
O
I
GV
GV
GV
GV
GV
GV
GV
GV
GV
—
—
—
—
11
—
—
22
22
DD
DD
DD
DD
DD
DD
DD
DD
DD
MRAS
F17
MCAS
J16
H16, G16, J15, H15
E26, E28
MCS[0:3]
MCKE[0:1]
MCK[0:5]
MCK[0:5]
MSYNC_IN
MSYNC_OUT
J20, H25, A15, D20, F28, K14
F20, G27, B15, E20, F27, L14
M28
N28
O
Local Bus Controller Interface
LA[27]
U18
O
OV
5, 9
DD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
57
Package and Pin Listings
Table 43. MPC8541E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
LA[28:31]
LAD[0:31]
T18, T19, T20, T21
O
OV
OV
5, 7, 9
—
DD
DD
AD26, AD27, AD28, AC26, AC27, AC28, AA22,
AA23, AA26, Y21, Y22, Y26, W20, W22, W26, V19,
T22, R24, R23, R22, R21, R18, P26, P25, P20, P19,
P18, N22, N23, N24, N25, N26
I/O
LALE
V21
O
O
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
5, 8, 9
9
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
LBCTL
V20
LCKE
U23
O
—
LCLK[0:2]
U27, U28, V18
O
—
LCS[0:4]
Y27, Y28, W27, W28, R27
O
—
LCS5/DMA_DREQ2
LCS6/DMA_DACK2
LCS7/DMA_DDONE2
LDP[0:3]
R28
I/O
O
1
P27
1
P28
O
1
AA27, AA28, T26, P21
I/O
O
—
LGPL0/LSDA10
LGPL1/LSDWE
LGPL2/LOE/LSDRAS
LGPL3/LSDCAS
U19
U22
V28
V27
V23
5, 9
5, 9
5, 8, 9
5, 9
21
O
O
O
LGPL4/LGTA/LUPWAIT/
LPBSE
I/O
LGPL5
V22
T27
O
I
OV
OV
OV
OV
5, 9
—
DD
DD
DD
DD
LSYNC_IN
LSYNC_OUT
T28
O
O
—
LWE[0:1]/LSDDQM[0:1]/
LBS[0:1]
AB28, AB27
1, 5, 9
LWE[2:3]/LSDDQM[2:3]/
LBS[2:3]
T23, P24
O
OV
1, 5, 9
DD
DMA
DMA_DREQ[0:1]
DMA_DACK[0:1]
DMA_DDONE[0:1]
H5, G4
H6, G5
H7, G6
I
OV
OV
OV
—
—
—
DD
DD
DD
O
O
Programmable Interrupt Controller
MCP
UDE
AG17
AG16
I
I
OV
OV
—
—
DD
DD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
58
Package and Pin Listings
Table 43. MPC8541E Pinout Listing (continued)
Power
Notes
Signal
Package Pin Number
Pin Type
Supply
IRQ[0:7]
IRQ8
AA18, Y18, AB18, AG24, AA21, Y19, AA19, AG25
I
I
OV
OV
OV
OV
OV
OV
—
9
DD
DD
DD
DD
DD
DD
AB20
Y20
IRQ9/DMA_DREQ3
IRQ10/DMA_DACK3
IRQ11/DMA_DDONE3
IRQ_OUT
I
1
AF26
AH24
AB21
I/O
I/O
O
1
1
2, 4
Ethernet Management Interface
EC_MDC
EC_MDIO
F1
E1
O
OV
OV
5, 9
—
DD
DD
I/O
Gigabit Reference Clock
EC_GTX_CLK125
E2
I
LV
—
DD
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_TXD[7:4]
TSEC1_TXD[3:0]
TSEC1_TX_EN
TSEC1_TX_ER
TSEC1_TX_CLK
TSEC1_GTX_CLK
TSEC1_CRS
A6, F7, D7, C7
O
O
O
O
I
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
—
9, 18
11
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
B7, A7, G8, E8
C8
B8
C6
—
B6
O
I
—
C3
—
TSEC1_COL
G7
I
—
TSEC1_RXD[7:0]
TSEC1_RX_DV
TSEC1_RX_ER
TSEC1_RX_CLK
D4, B4, D3, D5, B5, A5, F6, E6
I
—
D2
E5
D6
I
—
I
—
I
—
Three-Speed Ethernet Controller (Gigabit Ethernet 2)
TSEC2_TXD[7:4]
TSEC2_TXD[3:0]
TSEC2_TX_EN
TSEC2_TX_ER
TSEC2_TX_CLK
TSEC2_GTX_CLK
B10, A10, J10, K11
O
O
O
O
I
LV
LV
LV
LV
LV
LV
—
5, 9, 18
11
DD
DD
DD
DD
DD
DD
J11, H11, G11, E11
B11
D11
D10
C10
—
—
O
—
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
59
Package and Pin Listings
Table 43. MPC8541E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
TSEC2_CRS
D9
I
I
I
I
I
I
LV
LV
LV
LV
LV
LV
—
—
—
—
—
—
DD
DD
DD
DD
DD
DD
TSEC2_COL
F8
TSEC2_RXD[7:0]
TSEC2_RX_DV
TSEC2_RX_ER
TSEC2_RX_CLK
F9, E9, C9, B9, A9, H9, G10, F10
H8
A8
E10
DUART
UART_CTS[0,1]
UART_RTS[0,1]
UART_SIN[0,1]
UART_SOUT[0,1]
Y2, Y3
Y1, AD1
P11, AD5
N6, AD2
I
O
I
OV
OV
OV
OV
—
—
—
—
DD
DD
DD
DD
O
2
I C interface
IIC_SDA
IIC_SCL
AH22
AH23
I/O
I/O
OV
OV
4, 19
4, 19
DD
DD
System Control
AH16
HRESET
I
O
I
OV
OV
OV
OV
OV
—
18
—
DD
DD
DD
DD
DD
HRESET_REQ
SRESET
AG20
AF20
CKSTP_IN
CKSTP_OUT
M11
I
—
G1
O
2, 4
Debug
TRIG_IN
N12
G2
I
OV
OV
OV
OV
OV
OV
—
DD
DD
DD
DD
DD
DD
TRIG_OUT/READY
MSRCID[0:1]
MSRCID[2:3]
MSRCID4
O
O
O
O
O
6, 9, 18
J9, G3
F3, F5
F2
5, 6, 9
6
6
6
MDVAL
F4
Clock
SYSCLK
RTC
AH21
AB23
AF22
I
I
OV
OV
OV
—
—
—
DD
DD
DD
CLK_OUT
O
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
60
Package and Pin Listings
Table 43. MPC8541E Pinout Listing (continued)
Power
Notes
Signal
Package Pin Number
JTAG
Pin Type
Supply
TCK
TDI
AF21
AG21
AF19
AF23
AG23
I
I
OV
OV
OV
OV
OV
—
12
11
12
12
DD
DD
DD
DD
DD
TDO
TMS
TRST
O
I
I
DFT
LSSD_MODE
L1_TSTCLK
L2_TSTCLK
TEST_SEL0
TEST_SEL1
AG19
AB22
AG22
AH20
AG26
I
I
I
I
I
OV
OV
OV
OV
OV
20
20
20
3
DD
DD
DD
DD
DD
3
Thermal Management
THERM0
THERM1
AG2
AH3
—
—
—
14
14
—
Power Management
ASLEEP
AG18
—
—
9, 18
Power and Ground Signals
AH19
AV
AV
AV
AV
AV
1
2
3
4
5
Powerfor e500
PLL (1.2 V)
AV
1
2
3
4
5
—
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
AH18
AH17
AF28
AE28
Power for CCB
PLL (1.2 V)
AV
AV
AV
AV
Powerfor CPM
PLL (1.2 V)
Powerfor PCI1
PLL (1.2 V)
Powerfor PCI2
PLL (1.2 V)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
61
Package and Pin Listings
Table 43. MPC8541E Pinout Listing (continued)
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
GND
A12, A17, B3, B14, B20, B26, B27, C2, C4, C11,C17,
C19, C22, C27, D8, E3, E12, E24, F11, F18, F23, G9,
G12, G25, H4, H12, H14, H17, H20, H22, H27, J19,
J24, K5, K9, K18, K23, K28, L6, L20, L25, M4, M12,
M14, M16, M22, M27, N2, N13, N15, N17, P12, P14,
P16, P23, R13, R15, R17, R20, R26, T3, T8, T10,
T12, T14, T16, U6, U13, U15, U16, U17, U21, V7,
V10, V26, W5, W18, W23, Y8, Y16, AA6, AA13, AB4,
AB11, AB19, AC6, AC9, AD3, AD8, AD17, AF2, AF4,
AF10, AF13, AF15, AF27, AG3, AG7
—
—
—
GV
A14, A20, A25, A26, A27, A28, B17, B22, B28, C12, Power for DDR
GV
—
—
DD
DD
C28, D16, D19, D21, D24, D28, E17, E22, F12, F15,
F19, F25, G13, G18, G20, G23, G28, H19, H24, J12,
J17, J22, J27, K15, K20, K25, L13, L23, L28, M25,
N21
DRAM I/O
Voltage
(2.5 V)
LV
A4, C5, E7, H10
Reference
Voltage;
LV
DD
DD
Three-Speed
Ethernet I/O
(2.5 V, 3.3 V)
MV
N27
Reference
VoltageSignal;
DDR
MV
—
REF
REF
No Connects
AA24, AA25, AA3, AA4, AA7 AA8, AB24, AB25,
AC24, AC25, AD23, AD24, AD25, AE23, AE24,
AE25, AE26, AE27, AF24, AF25, H1, H2, J1, J2, J3,
J4, J5, J6, M1, N1, N10, N11, N4, N5, N7, N8, N9,
P10, P8, P9, R10, R11, T24, T25, U24, U25, V24,
V25, W24, W25, W9, Y24, Y25, Y5, Y6, Y9, AH26,
AH28, AG28, AH1, AG1, AH2, B1, B2, A2, A3
—
—
16
OV
D1, E4, H3, K4, K10, L7, M5, N3, P22, R19, R25, T2,
PCI, 10/100
OV
—
DD
DD
T7, U5, U20, U26, V8, W4, W13, W19, W21, Y7, Y23, Ethernet, and
AA5, AA12, AA16, AA20, AB7, AB9, AB26, AC5,
AC11, AC17, AD4, AE1, AE8, AE10, AE15, AF7,
AF12, AG27, AH4
other Standard
(3.3 V)
RESERVED
SENSEVDD
C1, T11, U11, AF1
L12
—
—
15
13
Power for Core
(1.2 V)
V
DD
SENSEVSS
K12
—
—
13
—
V
M13, M15, M17, N14, N16, P13, P15, P17, R12, R14, Power for Core
V
DD
DD
R16, T13, T15, T17, U12, U14
(1.2 V)
CPM
PA[8:31]
J7, J8, K8, K7, K6, K3, K2, K1, L1, L2, L3, L4, L5, L8,
L9, L10, L11, M10, M9, M8, M7, M6, M3, M2
I/0
OV
—
DD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
62
Package and Pin Listings
Table 43. MPC8541E Pinout Listing (continued)
Power
Notes
Signal
Package Pin Number
Pin Type
Supply
PB[18:31]
P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, R6,
R7
I/0
I/0
OV
OV
—
—
DD
DD
PC[0, 1, 4–29]
R8, R9, T9, T6, T5, T4, T1, U1, U2, U3, U4, U7, U8,
U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2, W3,
W6, W7, W8
PD[7, 14–25, 29–31]
Y4, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4,
AC3, AC2, AC1, AD6, AE3, AE2
I/0
OV
—
DD
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV
3. This pin must always be pulled down to GND.
.
DD
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8541E is in
the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If an
external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is
intended to be high during reset.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or
pull-down resistors. See Section 15.2, “Platform/System PLL Ratio.”
8. The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up
or pull-down resistors. See the Section 15.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin therefore is described as an I/O for boundary scan.
10. This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. Refer to the PCI Specification.
11. This output is actively driven during reset rather than being three-stated during reset.
12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13. These pins are connected to the V /GND planes internally and may be used by the core power supply to improve tracking
DD
and regulation.
14. Internal thermally sensitive resistor.
15. No connections should be made to these pins.
16. These pins are not connected for any functional use.
17. PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OV when
DD
using 64-bit buffer mode (pins PCI_AD[63:32] and PCI2_C_BE[7:4]).
18. If this pin is connected to a device that pulls down during reset, an external pull-up is required to that is strong enough to
pull this signal to a logic 1 during reset.
19. Recommend a pull-up resistor (~1 kΩ) be placed on this pin to OV
.
DD
20. These are test signals for factory use only and must be pulled up (100Ω το 1kΩ) to OV for normal machine operation.
DD
21. If this signal is used as both an input and an output, a weak pull-up (~10kΩ) is required on this pin.
22. MSYNC_IN and MSYNC_OUT should be connected together for proper operation.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
63
Clocking
15 Clocking
This section describes the PLL configuration of the MPC8541E. Note that the platform clock is identical
to the CCB clock.
15.1 Clock Ranges
Table 44 provides the clocking specifications for the processor core and Table 44 provides the clocking
specifications for the memory bus.
Table 44. Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
533 MHz
600 MHz
667 MHz
833 MHz
1000 MHz
Unit Notes
Min
400
Max
Min
400
Max
Min
400
Max
Min
400
Max
Min
400
Max
e500 core
processor
frequency
533
600
667
833
1000
MHz 1, 2, 3
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
3. 1000 MHz frequency supports only a 1.3 V core.
Table 45. Memory Bus Clocking Specifications
Maximum Processor Core
Frequency
Characteristic
Unit
Notes
533, 600, 667, 883, 1000 MHz
Min
Max
Memory bus frequency
Notes:
100
166
MHz
1, 2, 3
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that
the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL
Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
2. The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
3. 1000 MHz frequency supports only a 1.3 V core.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
64
Freescale Semiconductor
Clocking
15.2 Platform/System PLL Ratio
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in Table 46.
There is no default for this PLL ratio; these signals must be pulled to the desired values.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
Table 46. CCB Clock Ratio
Binary Value of
Ratio Description
LA[28:31] Signals
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
16:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
2:1 ratio CCB clock: SYSCLK (PCI bus)
3:1 ratio CCB clock: SYSCLK (PCI bus)
4:1 ratio CCB clock: SYSCLK (PCI bus)
5:1 ratio CCB clock: SYSCLK (PCI bus)
6:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
8:1 ratio CCB clock: SYSCLK (PCI bus)
9:1 ratio CCB clock: SYSCLK (PCI bus)
10:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
12:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
Reserved
Reserved
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
65
Clocking
15.3 e500 Core PLL Ratio
Table 47 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in Table 47.
Table 47. e500 Core to CCB Ratio
Binary Value of LALE, LGPL2 Signals
Ratio Description
00
01
10
11
2:1 e500 core:CCB
5:2 e500 core:CCB
3:1 e500 core:CCB
7:2 e500 core:CCB
15.4 Frequency Options
Table 48 shows the expected frequency values for the platform frequency when using a CCB to SYSCLK
ratio in comparison to the memory bus speed.
Table 48. Frequency Options with Respect to Memory Bus Speeds
CCB to SYSCLK
SYSCLK (MHz)
Ratio
17
25
33
42
67
83
100
111
133
Platform/CCB Frequency (MHz)
2
3
200
300
222
333
267
200
267
333
250
333
4
5
208
250
333
6
200
267
300
333
8
200
225
250
300
9
10
12
16
200
267
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
66
Thermal
16 Thermal
This section describes the thermal specifications of the MPC8541E.
16.1 Thermal Characteristics
Table 49 provides the package thermal characteristics for the MPC8541E.
Table 49. Package Thermal Characteristics
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection on four layer board (2s2p)
Junction-to-ambient (@200 ft/min or 1.0 m/s) on four layer board (2s2p)
Junction-to-ambient (@400 ft/min or 2.0 m/s) on four layer board (2s2p)
Junction-to-board thermal
R
R
R
17
14
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2
1, 2
3
θJMA
θJMA
θJMA
13
R
10
θJB
θJC
Junction-to-case thermal
R
0.96
4
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance
2. Per JEDEC JESD51–6 with the board horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1). Cold plate temperature is used for case temperature; measured value includes the thermal resistance of the
interface layer.
16.2 Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA)
package for air-cooled applications. Proper thermal control design is primarily dependent on the
system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment
method to the heat sink is illustrated in Figure 42. The heat sink should be attached to the printed-circuit
board with the spring force centered over the die. This spring force should not exceed 10 pounds force.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
67
Thermal
FC-PBGA Package
Heat Sink
Heat Sink
Clip
Thermal Interface Material
Lid
Die
Printed-Circuit Board
Figure 42. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the MPC8541E.
There are several commercially-available heat sinks from the following vendors:
Aavid Thermalloy
603-224-9988
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech
408-749-7601
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
408-436-8770
800-522-6752
603-635-5102
Internet: www.mei-millennium.com
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
68
Thermal
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several
heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics,
and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that allows the
MPC8541E to function in various environments.
16.2.1 Recommended Thermal Model
For system thermal modeling, the MPC8541E thermal model is shown in Figure 44. Five cuboids are used
to represent this device. To simplify the model, the solder balls and substrate are modeled as a single block
29x29x1.6 mm with the conductivity adjusted accordingly. The die is modeled as 8.7 x 9.3 mm at a
thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed resistance between the die and
substrate assuming a conductivity of 4.4 W/m•K in the thickness dimension of 0.07 mm. The lid attach
adhesive is also modeled as a collapsed resistance with dimensions of 8.7 x 9.3 x 0.05 mm and the
conductivity of 1.07 W/m•K. The nickel plated copper lid is modeled as 11 x 11 x 1 mm.
Conductivity
Value
Unit
Lid
(11 × 11 × 1 mm)
Adhesive
k
k
k
360
360
360
W/(m × K)
Lid
x
y
z
Bump/underfill
Die
z
Substrate and solder balls
Lid Adhesive—Collapsed resistance
(8.7 × 9.3 × 0.05 mm)
Side View of Model (Not to Scale)
k
1.07
z
Die
(8.7 × 9.3 × 0.75 mm)
x
Bump/Underfill—Collapsed resistance
(8.7 × 9.3 × 0.07 mm)
Substrate
k
4.4
z
Substrate and Solder Balls
(25 × 25 × 1.6 mm)
Heat Source
k
k
k
14.2
14.2
1.2
x
y
z
y
Top View of Model (Not to Scale)
Figure 43. MPC8541E Thermal Model
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
69
Thermal
16.2.2 Internal Package Conduction Resistance
For the packaging technology, shown in Table 49, the intrinsic internal conduction thermal resistance paths
are as follows:
•
•
The die junction-to-case thermal resistance
The die junction-to-board thermal resistance
Figure 44 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Internal Resistance
Printed-Circuit Board
Radiation
Convection
External Resistance
(Note the internal versus external package resistance)
Figure 44. Package with Heat Sink Mounted to a Printed-Circuit Board
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is
conducted through the silicon and through the lid, then through the heat sink attach material (or thermal
interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that
the heat sink attach material and heat sink thermal resistance are the dominant terms.
16.2.3 Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal
contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 45 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.
As shown, the performance of these thermal interface materials improves with increasing contact pressure.
The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a
thermal resistance approximately six times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 41). Therefore, the synthetic grease offers the best thermal performance, especially at the low
interface pressure.
When removing the heat sink for re-work, it is preferable to slide the heat sink off slowly until the thermal
interface material loses its grip. If the support fixture around the package prevents sliding off the heat sink,
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
70
Freescale Semiconductor
Thermal
the heat sink should be slowly removed. Heating the heat sink to 40–50°C with an air gun can soften the
interface material and make the removal easier. The use of an adhesive for heat sink attach is not
recommended.
Silicone Sheet (0.006 in.)
Bare Joint
2
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
1.5
1
0.5
0
0
10
20
30
Contact Pressure (psi)
Figure 45. Thermal Performance of Select Thermal Interface Materials
40
50
60
70
80
The system board designer can choose between several types of thermal interface. There are several
commercially-available thermal interfaces provided by the following vendors:
Chomerics, Inc.
781-935-4850
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
800-248-2481
Midland, MI 48686-0997
Internet: www.dowcorning.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
888-642-7674
800-347-4572
Internet: www.microsi.com
The Bergquist Company
th
18930 West 78 St.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
71
Thermal
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
Thermagon Inc.
888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
16.2.4 Heat Sink Selection Examples
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
16.2.4.1 Case 1
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
T = T + T + (θ + θ
+ θ ) × P
SA D
J
I
R
JC
INT
where
T is the die-junction temperature
J
T is the inlet cabinet ambient temperature
I
T is the air temperature rise within the computer cabinet
R
θ
θ
θ
is the junction-to-case thermal resistance
JC
is the adhesive or interface material thermal resistance
INT
is the heat sink base-to-ambient thermal resistance
SA
P is the power dissipated by the device. See Table 4 and Table 5.
D
During operation the die-junction temperatures (T ) should be maintained within the range specified in
J
Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature
and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T )
A
may range from 30° to 40°C. The air temperature rise within a cabinet (T ) may be in the range of 5° to
R
10°C. The thermal resistance of some thermal interface material (θ ) may be about 1°C/W. For the
INT
purposes of this example, the θ value given in Table 49 that includes the thermal grease interface and is
JC
documented in note 4 is used. If a thermal pad is used, θ
must be added.
INT
Assuming a T of 30°C, a T of 5°C, a FC-PBGA package θ = 0.96, and a power consumption (P ) of
I
R
JC
D
8.0 W, the following expression for T is obtained:
J
Die-junction temperature: T = 30°C + 5°C + (0.96°C/W + θ ) × 8.0 W
J
SA
The heat sink-to-ambient thermal resistance (θ ) versus airflow velocity for a Thermalloy heat sink
SA
#2328B is shown in Figure 46.
Assuming an air velocity of 2 m/s, we have an effective θ
of about 3.3°C/W, thus
SA+
T = 30°C + 5°C + (0.96°C/W + 3.3°C/W) × 8.0 W,
J
resulting in a die-junction temperature of approximately 69°C which is well within the maximum
operating temperature of the component.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
72
Freescale Semiconductor
Thermal
8
7
6
5
4
3
2
1
Thermalloy #2328B Pin-fin Heat Sink
(25 × 28 × 15 mm)
0
0.5
1
1.5
2
2.5
3
3.5
Approach Air Velocity (m/s)
Figure 46. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
16.2.4.2 Case 2
Every system application has different conditions that the thermal management solution must solve. As an
alternate example, assume that the air reaching the component is 85 °C with an approach velocity of 1
m/sec. For a maximum junction temperature of 105 °C at 8 W, the total thermal resistance of junction to
case thermal resistance plus thermal interface material plus heat sink thermal resistance must be less than
2.5 °C/W. The value of the junction to case thermal resistance in Table 49 includes the thermal interface
resistance of a thin layer of thermal grease as documented in footnote 4 of the table. Assuming that the
heat sink is flat enough to allow a thin layer of grease or phase change material, then the heat sink must be
less than 1.5 °C/W.
Millennium Electronics (MEI) has tooled a heat sink MTHERM-1051 for this requirement assuming a
compactPCI environment at 1 m/sec and a heat sink height of 12 mm. The MEI solution is illustrated in
Figure 47 and Figure 48. This design has several significant advantages:
•
•
•
The heat sink is clipped to a plastic frame attached to the application board with screws or plastic
inserts at the corners away from the primary signal routing areas.
The heat sink clip is designed to apply the force holding the heat sink in place directly above the
die at a maximum force of less than 10 lbs.
For applications with significant vibration requirements, silicone damping material can be applied
between the heat sink and plastic frame.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
73
Thermal
The spring mounting should be designed to apply the force only directly above the die. By localizing the
force, rocking of the heat sink is minimized. One suggested mounting method attaches a plastic fence to
the board to provide the structure on which the heat sink spring clips. The plastic fence also provides the
opportunity to minimize the holes in the printed-circuit board and to locate them at the corners of the
package. Figure 47 and provide exploded views of the plastic fence, heat sink, and spring clip.
Figure 47. Exploded Views (1) of a Heat Sink Attachment using a Plastic Fence
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
74
Freescale Semiconductor
Thermal
Figure 48. Exploded Views (2) of a Heat Sink Attachment using a Plastic Force
The die junction-to-ambient and the heat sink-to-ambient thermal resistances are common figure-of-merits
used for comparing the thermal performance of various microelectronic packaging technologies, one
should exercise caution when only using this metric in determining thermal management because no single
parameter can adequately describe three-dimensional heat flow. The final die-junction operating
temperature is not only a function of the component-level thermal resistance, but the system level design
and its operating conditions. In addition to the component’s power consumption, a number of factors affect
the final operating die-junction temperature: airflow, board population (local heat flux of adjacent
components), system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today’s
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation convection
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models
for the boards, as well as, system-level designs.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
75
System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8541E.
17.1 System Clocking
The MPC8541E includes five PLLs.
1. The platform PLL (AV 1) generates the platform clock from the externally supplied SYSCLK
DD
input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL
ratio configuration bits as described in Section 15.2, “Platform/System PLL Ratio.”
2. The e500 Core PLL (AV 2) generates the core clock as a slave to the platform clock. The
DD
frequency ratio between the e500 core clock and the platform clock is selected using the e500
PLL ratio configuration bits as described in Section 15.3, “e500 Core PLL Ratio.”
3. The CPM PLL (AV 3) is slaved to the platform clock and is used to generate clocks used
DD
internally by the CPM block. The ratio between the CPM PLL and the platform clock is fixed and
not under user control.
4. The PCI1 PLL (AV 4) generates the clocking for the first PCI bus.
DD
5. The PCI2 PLL (AV 5) generates the clock for the second PCI bus.
DD
17.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AV 1,
DD
AV 2, AV 3, AV 4, and AV 5 respectively). The AV level should always be equivalent to V ,
DD
DD
DD
DD
DD
DD
and preferably these voltages are derived directly from V through a low frequency filter scheme such
DD
as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 49, one to each of the five AV pins. By
DD
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
DD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
76
Freescale Semiconductor
System Design Information
Figure 49 shows the PLL power supply filter circuit.
10 Ω
V
AV (or L2AV
)
DD
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 49. PLL Power Supply Filter Circuit
17.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8541E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8541E system, and the
MPC8541E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each V , OV , GV , and LV pins
DD
DD
DD
DD
of the MPC8541E. These decoupling capacitors should receive their power from separate V , OV
,
DD
DD
GV , LV , and GND power planes in the PCB, utilizing short traces to minimize inductance.
DD
DD
Capacitors may be placed directly under the device using a standard escape pattern. Others may surround
the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V , OV , GV , and LV planes, to enable quick recharging of the smaller chip
DD
DD
DD
DD
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
17.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV , GV , or LV as required. Unused active high
DD
DD
DD
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V , GV , LV , OV , and GND pins of
DD
DD
DD
DD
the MPC8541E.
17.5 Output Buffer DC Impedance
The MPC8541E drivers are characterized over process, voltage, and temperature. For all buses, the driver
2
is a push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
DD
or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 50). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
77
System Design Information
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
P
OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
OV
DD
R
N
SW2
SW1
Pad
Data
R
P
OGND
Figure 50. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V = R
while driving logic 1 with an external precision differential termination resistor of value R . The
× I
. Second, the output voltage is measured
1
source
source
term
measured voltage is V = 1/(1/R + 1/R )) × I
. Solving for the output impedance gives R
= R
2
1
2
source
source term
× (V /V – 1). The drive current is then I
= V /R
.
1
2
source
1
source
Table 50 summarizes the signal impedance targets. The driver impedance are targeted at minimum V
,
DD
nominal OV , 105°C.
DD
Table 50. Impedance Characteristics
Local Bus, Ethernet, DUART, Control, Configuration, Power
Impedance
PCI
DDR DRAM Symbol Unit
Management
43 Target
43 Target
NA
R
N
25 Target 20 Target
25 Target 20 Target
Z
Z
Ω
Ω
Ω
0
0
R
P
Differential
NA
NA
Z
DIFF
Note: Nominal supply voltages. See Table 1, T = 105°C.
j
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
78
System Design Information
17.6 Configuration Pin Multiplexing
The MPC8541E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up
devices.
17.7 Pull-Up Resistor Requirements
The MPC8541E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type
pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 52. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion give
unpredictable results.
TSEC1_TXD[3:0] must not be pulled low during reset. Some PHY chips have internal pulldowns that
could cause this to happen. If such PHY chips are used, then a pullup must be placed on these signals strong
enough to restore these signals to a logical 1 during reset.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
17.8 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture. The
device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not
interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using
only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply
tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common
on-chip processor (COP) function.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
79
System Design Information
The COP function of these processors allow a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 51 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 51, for connection to the target system, and is
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have
been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others
use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as
with an IC). Regardless of the numbering, the signal placement recommended in Figure 51 is common to
all known emulators.
2
4
1
3
COP_TDO
COP_TDI
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
5
7
6
8
COP_TCK
COP_TMS
COP_SRESET
9
10
12
NC
NC
11
KEY
13
15
COP_HRESET
No pin
GND
COP_CHKSTP_OUT
16
Figure 51. COP Connector Physical Pinout
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
80
Freescale Semiconductor
System Design Information
17.8.1 Termination of Unused Signals
If the JTAG interface and COP header are not used, Freescale recommends the following connections:
•
TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in Figure 52. If this is not possible, the isolation resistor allows future access to TRST in
case a JTAG interface may need to be wired onto the system in future debug situations.
•
•
Tie TCK to OV through a 10 kΩ resistor. This prevents TCK from changing state and reading
DD
incorrect data into the device.
No connection is required for TDI, TMS, or TDO.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
81
System Design Information
OV
DD
10 kΩ
10 kΩ
6
1
SRESET
SRESET
HRESET
From Target
Board Sources
(if any)
HRESET
COP_HRESET
13
11
10 kΩ
10 kΩ
10 kΩ
10 kΩ
COP_SRESET
5
1
TRST
COP_TRST
4
2
1
3
2
10 Ω
4
COP_VDD_SENSE
NC
6
5
5
7
6
8
COP_CHKSTP_OUT
CKSTP_OUT
15
10 kΩ
9
10
12
3
14
11
10 kΩ
KEY
13
15
COP_CHKSTP_IN
COP_TMS
No pin
CKSTP_IN
TMS
8
9
1
16
COP_TDO
COP_TDI
COP_TCK
COP Connector
Physical Pinout
TDO
3
TDI
7
2
TCK
10 kΩ
NC
NC
10
4
12
16
Notes:
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid
accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 52. JTAG Interface Connection
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
82
Freescale Semiconductor
Document Revision History
18 Document Revision History
Table 51 provides a revision history for this hardware specification.
Table 51. Document Revision History
Rev. No.
Date
Substantive Change(s)
4.2
1/2008
Added “Note: Rise/Fall Time on CPM Input Pins” and following note text to Section 10.2, “CPM AC
Timing Specifications.”
4.1
4
07/2007
12/2006
Inserted Figure 3, ““Maximum AC Waveforms on PCI interface for 3.3-V Signaling.”
Updated Section 2.1.2, “Power Sequencing.”
Updated back page information.
3.2
3.1
11/2006
10/2005
Updated Section 2.1.2, “Power Sequencing.”
Replaced Section 17.8, “JTAG Configuration Signals.”
Table 4: Added footnote 2 about junction temperature.
Table 4: Added max. power values for 1000 MHz core frequency.
Removed Figure 3, “Maximum AC Waveforms on PCI Interface for 3.3-V Signaling.”
Table 30: Modified note to t
rom 8 to 9
LBKSKEW f
Table 30: Changed t
and t
values.
LBKHOZ1
LBKHOV2
Table 30: Added note 3 to t
.
LBKHOV1
Table 30 and Table 31: Modified note 3.
Table 31: Added note 3 to t
.
LBKLOV1
Table 31: Modified values for t
, t
, t
, t
, t
, and t
.
LBKHKT LBKLOV1 LBKLOV2 LBKLOV3 LBKLOZ1
LBKLOZ2
Figure 21: Changed Input Signals: LAD[0:31]/LDP[0:3].
Table 43: Modified note for signal CLK_OUT.
Table 43: PCI1_CLK and PCI2_CLK changed from I/O to I.
Table 52: Added column for Encryption Acceleration.
3
2
8/29/2005 Table 4: Modified max. power values.
Table 43: Modified notes for signals TSEC1_TXD[3:0], TSEC2_TXD[3:0], TRIG_OUT/READY,
MSRCID4, and MDVAL.
8/2005
6/2005
6/2005
Previous revision’s history listed incorrect cross references. Table 2 is now correctly listed as
Table 27 and Table 31 is now listed as Table 31.
Table 7: Added note 2.
Table 14: Modified min and max values for t
DDKHMP
1
0
Table 27: Changed LV to OV for the supply voltage Ethernet management interface.
dd dd
Table 4: Modified footnote 4 and changed typical power for the 1000MHz core frequency.
Table 31: Corrected symbols for body rows 9–15, effectively changing them from a high state to a
low state.
Initial Release.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
83
Device Nomenclature
19 Device Nomenclature
Ordering information for the parts fully covered by this specification document is provided in
Section 19.1, “Nomenclature of Parts Fully Addressed by this Document.”
19.1 Nomenclature of Parts Fully Addressed by this Document
Table 52 provides the Freescale part numbering nomenclature for the MPC8541E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
Table 52. Part Numbering Nomenclature
MPC nnnn
pp
aa
a
r
t
Product
Code Identifier Acceleration
Part
Encryption
Temperature
Processor
Frequency
Platform
Frequency
Revision
Level
2
Package
1
3
4
Range
MPC
8541
Blank = not
included
Blank = 0 to 105°C PX = FC-PBGA AJ = 533 MHz
C = –40 to 105°C VT = FC-PBGA AK = 600 MHz
D = 266 MHz
E = 300 MHz
F = 333 MHz
E = included
(lead free)
AL = 667 MHz
AP = 833 MHz
AQ = 1000 MHZ
Notes:
1. For Temperature Range=C, Processor Frequency is limited to 667 MHz with a Platform Frequency selector of 333 MHz,
Processor Frequency is limited to 533 MHz with a Platform Frequency selector of 266 MHz.
2. See Section 14, “Package and Pin Listings,” for more information on available package types.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
4. Contact you local Freescale field applications engineer (FAE).
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
84
Freescale Semiconductor
Device Nomenclature
19.2 Part Marking
Parts are marked as the example shown in Figure 53.
MPCnnnn
tppaaar
MMMMM
ATWLYYWWA
CCCCC
85xx
FC-PBGA
Notes:
MMMMM is the 5-digit mask number.
ATWLYYWWA is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 53. Part Marking for FC-PBGA Device
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
85
Device Nomenclature
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MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
86
Device Nomenclature
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
87
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any products herein. Freescale Semiconductor makes no warranty, representation or
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Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
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The Power Architecture and Power.org word marks and the Power and Power.org logos
and related marks are trademarks and service marks licensed by Power.org. The
described product contains a PowerPC processor core. The PowerPC name is a
trademark of IBM Corp. and used under license. IEEE 802.3 and 1149.1 are registered
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Document Number: MPC8541EEC
Rev. 4.2
1/2008
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32-BIT, 667MHz, RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
NXP
MPC8541VTALDX
32-BIT, 1420MHz, RISC PROCESSOR, CBGA360, 25 X 25 MM, 2.40 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, HCTE, CERAMIC, BGA-360
NXP
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