MPC8377EVRALG_技术文档

Document Number: MPC8377EEC

Rev. 10, 07/2014

Freescale Semiconductor

Technical Data

MPC8377E

PowerQUICC II Pro Processor

Hardware Specifications

Contents

This document provides an overview of the MPC8377E

PowerQUICC II Pro processor features, including a block

diagram showing the major functional components. This

chip is a cost-effective, low-power, highly integrated host

processor that addresses the requirements of several

printing and imaging, consumer, and industrial

applications, including main CPUs and I/O processors in

printing systems, networking switches and line cards,

wireless LANs (WLANs), network access servers (NAS),

VPN routers, intelligent NIC, and industrial controllers.

This chip extends the PowerQUICC family, adding higher

CPU performance, additional functionality, and faster

interfaces while addressing the requirements related to

time-to-market, price, power consumption, and package

size.

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 13

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . 15

6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . 16

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 23

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11. Enhanced Secure Digital Host Controller (eSDHC) 43

12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

13. I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

15. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

16. Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 68

17. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

18. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

19. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

20. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

21. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 77

22. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 87

23. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

24. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

25. System Design Information . . . . . . . . . . . . . . . . . . 119

26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 121

27. Document Revision History . . . . . . . . . . . . . . . . . . 123

1 Overview

This chip incorporates the e300c4s core, which includes

32 KB of L1 instruction and data caches and on-chip

memory management units (MMUs). The device offers

two enhanced three-speed 10, 100, 1000 Mbps Ethernet

interfaces, a DDR1/DDR2 SDRAM memory controller, a

flexible, a 32-bit local bus controller, a 32-bit PCI

controller, an optional dedicated security engine, a USB

2.0 dual-role controller, a programmable interrupt

2

controller, dual I C controllers, a 4-channel DMA controller, an enhanced secured digital host controller,

and a general-purpose I/O port. This figure shows the block diagram of the chip.

MPC8377E

DUART

Dual I²C

e300 Core

Timers

GPIO

SPI

Interrupt

Controller

32 KB

I-Cache

DDR1/DDR2

SDRAM

Controller

Enhanced

Local Bus

D-Cache

Security

USB 2.0

Hi-Speed

SD/MMC

Controller

PCI

Express

SATA

eTSEC

x1

x2

PHY PHY

RGMII, RMII, RGMII, RMII,

RTBI, MII RTBI, MII

DMA

PCI

Host Device

Figure 1. MPC8377E Block Diagram and Features

The following features are supported in the chip:

•

e300c4s core built on Power Architecture® technology with 32 KB instruction cache and 32 KB

data cache, a floating point unit, and two integer units

•

DDR1/DDR2 memory controller supporting a 32/64-bit interface

Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MT/s operation

32-bit local bus interface running up to 133-MT/s

USB 2.0 (full/high speed) support

Power management controller for low-power consumption

High degree of software compatibility with previous-generation PowerQUICC processor-based

designs for backward compatibility and easier software migration

•

Optional security engine provides acceleration for control and data plane security protocols

The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive

cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator

provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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In addition to the security engine, new high-speed interfaces, such as PCI Express and SATA are included.

This table compares the differences between MPC837xE derivatives and provides the number of ports

available for each interface.

Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E

Descriptions

MPC8377E

MPC8378E

MPC8379E

SGMII

PCI Express®

SATA

0

2

0

4

1.1

DDR Memory Controller

The DDR1/DDR2 memory controller includes the following features:

•

Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM

Support for up to 400-MT/s data rate

Support up to 4 chip selects

64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with ×8/×16/×32 data ports (no

direct ×4 support)

•

Support for up to 32 simultaneous open pages

Supports auto refresh

On-the-fly power management using CKE

1.8-/2.5-V SSTL2 compatible I/O

1.2

USB Dual-Role Controller

The USB controller includes the following features:

•

Supports USB on-the-go mode, including both device and host functionality, when using an

external ULPI (UTMI + low-pin interface) PHY

•

Complies with USB Specification, Rev. 2.0

Supports operation as a stand-alone USB device

— Supports one upstream facing port

— Supports three programmable USB endpoints

Supports operation as a stand-alone USB host controller

— Supports USB root hub with one downstream-facing port

— Enhanced host controller interface (EHCI) compatible

•

Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation;

low-speed operation is supported only in host mode

Supports UTMI + low pin interface (ULPI)

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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1.3

Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)

The eTSECs include the following features:

•

Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI

Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,

IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards

•

Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating

mode

MII management interface for external PHY control and status

1.4

Integrated Programmable Interrupt Controller (IPIC)

The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a

flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with

the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.

Interrupts can also be redirected to an external interrupt controller.

1.5

Power Management Controller (PMC)

The power management controller includes the following features:

•

Provides power management when the device is used in both host and agent modes

Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states

Support for PME generation in PCI agent mode, PME detection in PCI host mode

Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)

Supports MPC8349E backward-compatibility mode

1.6

Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC

family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time

clocks, A/D converters, and ISDN devices.

The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface

(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an

independent baud-rate generator, and a control unit.

2

1.7

DMA Controller, Dual I C, DUART, Enhanced Local Bus Controller

(eLBC), and Timers

The device provides an integrated four-channel DMA controller with the following features:

•

Allows chaining (both extended and direct) through local memory-mapped chain descriptors

(accessible by local masters)

•

Supports misaligned transfers

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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2

There are two I C controllers. These synchronous, multi-master buses can be connected to additional

devices for expansion and system development.

The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550

programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.

The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides

a seamless interface to many types of memory devices and peripherals. The memory controller is

responsible for controlling eight memory banks shared by a NAND Flash control machine (FCM), a

general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As

such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash,

EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other

peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with

data signals to reduce the device pin count.

The enhanced local bus controller also includes a number of data checking and protection features, such

as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle

is terminated within a user-specified period. The local bus can operate at up to 133 MT/s.

The system timers include the following features: periodic interrupt timer, real time clock, software

watchdog timer, and two general-purpose timer blocks.

1.8

Security Engine

The optional security engine is optimized to handle all the algorithms associated with IPSec,

IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto

execution units (EUs). The execution units are as follows:

•

Data encryption standard execution unit (DEU), supporting DES and 3DES

Advanced encryption standard unit (AESU), supporting AES

Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any

algorithm

•

One crypto-channel supporting multi-command descriptor chains

1.9

PCI Controller

The PCI controller includes the following features:

•

PCI Specification Revision 2.3 compatible

Single 32-bit data PCI interface operates at up to 66 MT/s

PCI 3.3-V compatible (not 5-V compatible)

Support for host and agent modes

On-chip arbitration, supporting 5 external masters on PCI

Selectable hardware-enforced coherency

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1.10 PCI Express Controller

The PCI Express controller includes the following features:

•

PCI Express 1.0a compatible

Two ×1 links or one ×2 link width

Auto-detection of number of connected lanes

Selectable operation as root complex or endpoint

Both 32- and 64-bit addressing

128-byte maximum payload size

Support for MSI and INTx interrupt messages

Virtual channel 0 only

Selectable Traffic Class

Full 64-bit decode with 32-bit wide windows

Dedicated four channel descriptor-based DMA engine per interface

1.11 Serial ATA (SATA) Controllers

The serial ATA (SATA) controllers have the following features:

•

Supports Serial ATA Rev 2.5 Specification

Spread spectrum clocking on receive

Asynchronous notification

Hot Plug including asynchronous signal recovery

Link power management

Native command queuing

Staggered spin-up and port multiplier support

Port multiplier support

SATA 1.5 and 3.0 Gb/s operation

Interrupt driven

Power management support

Error handling and diagnostic features

— Far end/near end loopback

— Failed CRC error reporting

— Increased ALIGN insertion rates

Scrambling and CONT override

•

1.12 Enhanced Secured Digital Host Controller (eSDHC)

The enhanced SD host controller (eSDHC) has the following features:

•

Conforms to SD Host Controller Standard Specification, Rev 2.0 with Test Event register support.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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•

Compatible with the MMC System Specification, Rev 4.0

Compatible with the SD Memory Card Specification, Rev 2.0, and supports High Capacity SD

memory cards

•

Compatible with the SDIO Card Specification Rev, 1.2

Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,

MMCplus, MMC 4x, and RS-MMC cards

•

SD bus clock frequency up to 50 MT/s

Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC modes

Supports internal DMA capabilities

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the chip. The

device is currently targeted to these specifications. Some of these specifications are independent of the I/O

cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

This table provides the absolute maximum ratings.

1

Table 2. Absolute Maximum Ratings

Characteristic

Symbol

Max Value

Unit

Note

Core supply voltage

V_DD

AV_DD

GV_DD

–0.3 to 1.1

V

—

PLL supply voltage (e300 core, eLBC, and system)

DDR1 and DDR2 DRAM I/O voltage

–0.3 to 2.75

–0.3 to 1.98

Three-speed Ethernet I/O, MII management voltage

LV_DD[1,2]

OV_DD

–0.3 to 3.63

V

—

PCI, DUART, system control and power management, I²C, and

JTAG I/O voltage

Local bus

SerDes

LBV_DD

L[1,2]_nV_DD

MV_IN

–0.3 to 3.63

V

—

6

–0.3 to 1.1

Input voltage

DDR DRAM signals

–0.3 to (GV_DD+ 0.3)

–0.3 to (LV_DD+ 0.3)

–0.3 to (OV_DD+ 0.3)

2, 4

—

DDR DRAM reference

Three-speed Ethernet signals

MV_REF

LV_IN

PCI, DUART, CLKIN, system control and power

management, I²C, and JTAG signals

OV_IN

3, 4, 5

Local Bus

LB_IN

–0.3 to (LBV_DD+ 0.3)

V

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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1

Table 2. Absolute Maximum Ratings (continued)

Characteristic

Symbol

Max Value

–55 to 150

Unit

Note

Storage temperature range

T_STG

°C

—

Notes:

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause

permanent damage to the device.

2. Caution: MV_INmust not exceed GV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OV_INmust not exceed OV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. (M,O)V_INand MV_REFmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

5. Overshoot/undershoot by OV_INon the PCI interface does not comply to the PCI Electrical Specification for 3.3-V operation,

as shown in Figure 2.

6. L[1,2]_nV_DDincludes SDAV_{DD_0}, XCOREV_DD, and XPADV_DDpower inputs.

2.1.2

Power Supply Voltage Specification

This table provides recommended operating conditions for the device. Note that the values in this table are

the recommended and tested operating conditions. Proper device operation outside of these conditions is

not guaranteed.

Table 3. Recommended Operating Conditions

Recommended

Characteristic

Symbol

Unit

Note

Value

Core supply voltage

up to 667 MT/s

800 MT/s

V_DD

1.0 50 mV

1.05 50 mV

1.0 50 mV

1.05 50 mV

V

1

PLL supply voltage (e300 core, eLBC and

system)

up to 667 MT/s

800 MT/s

AV_DD

1, 2

1

DDR1 and DDR2 DRAM I/O voltage

GV_DD

LV_DD[1,2]

OV_DD

2.5 V 125 mV

1.8 V 90 mV

Three-speed Ethernet I/O, MII management voltage

3.3 V 165 mV

2.5 V 125 mV

V

—

1

PCI, local bus, DUART, system control and power management, I²C, and

JTAG I/O voltage

3.3 V 165 mV

Local Bus

LBV_DD

1.8 V 90 mV

2.5 V 125 mV

3.3 V 165 mV

—

SerDes

up to 667 MT/s

800 MT/s

L[1,2]_nV_DD

1.0 50 mV

V

1, 3

1.05 V 50 mV

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

8

Table 3. Recommended Operating Conditions (continued)

Recommended

Value

Characteristic

Symbol

Unit

Note

Operating temperature range

commerical

T_a

T_j

T_a=0 (min)—

T_j=125 (max)

°C

—

extended temperature

T_a

T_j

T_a=–40 (min)—

T_j=125 (max)

°C

—

Notes:

1. GV_DD, OV_DD, AV_DD, and V_DDmust track each other and must vary in the same direction—either in the positive or negative

direction.

2. AV_DDis the input to the filter discussed in Section 25.1, “PLL Power Supply Filtering,” and is not necessarily the voltage at

the AVDD pin.

3. L[1,2]_nV_DD, SDAV_{DD_0}, XCOREV_DD, and XPADV_DDpower inputs.

This figure shows the undershoot and overshoot voltages at the interfaces of the device.

G/L/O/LBV_DD+ 20%

G/L/O/LBV_DD+ 5%

G/L/O/LBV_DD

V_IH

GND

GND – 0.3 V

V_IL

GND – 0.7 V

Not to Exceed 10%

of tinterface1

Note:

1. Note that t_interfacerefers to the clock period associated with the bus clock interface.

2. Note that with the PCI overshoot allowed (as specified above), the device does

not fully comply with the maximum AC ratings and device protection guideline outlined in

the PCI Rev. 2.3 Specification (Section 4.2.2.3).

Figure 2. Overshoot/Undershoot Voltage for GV /LV /OV /LBV

DD

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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2.1.3

Output Driver Characteristics

This table provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

Table 4. Output Drive Capability

Driver Type¹

Local bus interface utilities signals

Output Impedance (Ω)

Supply Voltage

Notes

45

40

25

LBV_DD= 2.5 V, 3.3 V

LBV_DD= 1.8 V

OV_DD= 3.3 V

—

2

PCI signals

DDR1 signal

18 full-strength mode

36 half-strength mode

GV_DD= 2.5 V

DDR2 signal

18 full-strength mode

36 half-strength mode

GV_DD= 1.8 V

2

eTSEC 10/100/1000 signals

45

LV_DD= 2.5 V, 3.3 V

OV_DD= 3.3 V

—

DUART, system control, I²C, JTAG, SPI, and USB

GPIO signals

Note:

OV_DD= 3.3 V

1. Specialized SerDes output capabilities are described in the relevant sections of these specifications (such as

PCI Express and SATA)

2. 18 ohms output impedance corresponds to full drive strength setting. 36 ohms output impedance corresponds to half

drive strength. DDR automatic hardware calibration is only available for full drive strength.

2.2

Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device

operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are

supplied before the core voltage, there may be a period of time that all input and output pins will actively

be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to

eliminate excessive current draw, apply the core voltages (V and AV ) before the I/O voltages and

DD

assert PORESET before the power supplies fully ramp up. V and AV must reach 90% of their

DD

nominal value before GV , LV , and OV reach 10% of their value, see the following figure. I/O

DD

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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10

voltage supplies—GV , LV , and OV —do not have any ordering requirements with respect to one

DD

another.

I/O Voltage (GVDD, LVDD, and OVDD)

Core Voltage (VDD_,AVDD)

V

0.7 V

90%

t

0

Figure 3. Power-Up Sequencing Example

Note that the SerDes power supply (L[1,2]_nV ) should follow the same timing as the core supply

DD

(V ).

DD

The device does not require the core supply voltage and I/O supply voltages to be powered down in any

particular order.

3 Power Characteristics

The estimated typical power dissipation for the chip device is shown in this table.

1

Table 5. Power Dissipation

Core Frequency CSB/DDR Frequency

Sleep Power

Typical Application Typical Application Max Application

at T_j= 125°C (W) ³at T_j= 125°C (W) ⁴

(MT/s)

at T_j= 65°C (W) ²at T_j= 65°C (W) ²

333

167

400

266

300

225

333

250

355

266

1.45

1.9

1.8

2.0

1.9

2.0

1.9

2.0

1.9

2.0

3.2

3.0

3.3

3.1

3.2

3.1

3.3

3.2

3.3

3.2

3.8

3.6

4.0

3.8

3.7

3.9

3.8

4.0

3.9

333

400

450

500

533

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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1

Table 5. Power Dissipation (continued)

Core Frequency CSB/DDR Frequency

Sleep Power

Typical Application Typical Application Max Application

(MT/s)

at T_j= 65°C (W) ²at T_j= 65°C (W) ²

at T_j= 125°C (W) ³at T_j= 125°C (W) ⁴

400

300

333

266

400

1.45

2.1

2.0

2.1

2.0

2.5

3.4

3.3

3.8

4.1

4.0

4.1

3.9

4.3

600

667

800

Notes:

1. The values do not include I/O supply power (OV_DD, LV_DD, GV_DD) or AV_DD. For I/O power values, see Table 6.

2. Typical power is based on a voltage of V_DD= 1.0 V for core frequencies ≤ 667 MT/s or V_DD= 1.05 V for core frequencies of

800 MT/s, and running a Dhrystone benchmark application.

3. Typical power is based on a voltage of V_DD= 1.0 V for core frequencies ≤ 667 MT/s or V_DD= 1.05 V for core frequencies of

800 MT/s, and running a Dhrystone benchmark application.

4. Maximum power is based on a voltage of V_DD= 1.0 V for core frequencies ≤ 667 MT/s or V_DD= 1.05 V for core frequencies

of 800 MT/s, worst case process, and running an artificial smoke test.

This table shows the estimated typical I/O power dissipation for the device.

Table 6. Typical I/O Power Dissipation

GV_DD

(1.8 V)

GV_DD/LBV_DDOV_DDLV_DDLV_DDL[1,2]_nV_DD

Interface

Parameter

Unit

Comments

(2.5 V)

(3.3 V) (3.3 V) (2.5 V)

(1.0 V)

200 MT/s data

rate, 32-bit

0.28

0.41

0.31

0.46

0.33

0.48

0.35

0.51

0.38

0.35

—

W

—

200 MT/s data

rate, 64-bit

0.49

0.4

—

W

266 MT/s data

rate, 32-bit

266 MT/s data

rate, 64-bit

0.56

0.43

0.6

300 MT/s data

rate, 32-bit

DDR I/O

65%

utilization

2 pair of

clocks

300 MT/s data

rate, 64-bit

333 MT/s data

rate, 32-bit

0.45

0.64

—

333 MT/s data

rate, 64-bit

400 MT/s

data rate,

32-bit

400 MT/s

data rate,

64-bit

0.56

—

W

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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12

Table 6. Typical I/O Power Dissipation (continued)

GV_DD

(1.8 V)

GV_DD/LBV_DDOV_DDLV_DDLV_DDL[1,2]_nV_DD

Interface

Parameter

Unit

Comments

(2.5 V)

(3.3 V) (3.3 V) (2.5 V)

(1.0 V)

PCI I/O

Load =

30 pf

33 MT/s, 32-bit

66 MT/s, 32-bit

—

0.04

0.07

—

W

—

167 MT/s, 32-bit

133 MT/s, 32-bit

83 MT/s, 32-bit

66 MT/s, 32-bit

50 MT/s, 32-bit

MII or RMII

0.09

0.07

0.05

0.04

0.03

—

0.17

0.14

0.09

0.07

0.06

—

0.29

0.24

0.15

0.13

0.1

—

W

—

Local Bus

I/O

Load =

25 pf

—

0.02

Multiply by

number of

interfaces used.

eTSEC I/O

Load =

25 pf

USB

(60 MT/s

Clock)

RGMII or RTBI

12 Mbps

—

0.01

0.2

—

0.05

—

W

—

480 Mbps

—

SerDes

per lane

—

0.029

—

W

—

Other I/O

0.01

Note: The values given are for typical, and not worst case, switching.

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the chip. Note that the

PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on whether

the device is configured as a host or agent device. CLKIN is used when the device is in host mode.

4.1

DC Electrical Characteristics

This table provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.

Table 7. CLKIN DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

—

V_IH

V_IL

I_IN

2.7

–0.3

—

OV_DD+ 0.3

V

1

0.4

10

30

CLKIN Input current

PCI_CLK Input current

0 V ≤ V_IN≤ OV_DD

μA

—

0 V ≤ V_IN≤ 0.5 V or

I_IN

—

OV_DD– 0.5 V ≤ V_IN≤ OV_DD

Note:

1. In PCI agent mode, this specification does not comply with PCI 2.3 Specification.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

13

4.2

AC Electrical Characteristics

The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on

whether the device is configured in PCI host or PCI agent mode. This table provides the clock input

(CLKIN/PCI_CLK) AC timing specifications for the device.

Table 8. CLKIN AC Timing Specifications

Parameter

Symbol

Min

Typical

Max

Unit

Note

CLKIN/PCI_CLK frequency

CLKIN/PCI_CLK cycle time

CLKIN/PCI_CLK rise and fall time

CLKIN/PCI_CLK duty cycle

CLKIN/PCI_CLK jitter

f_CLKIN

t_CLKIN

25

15

0.6

40

—

66.666

40

MT/s

ns

1, 6

—

2

t_KH, t_KL

t_KHK/t_CLKIN

—

1.0

—

2.3

ns

60

%

3

—

150

ps

4, 5

Notes:

1. Caution: The system, core and security block must not exceed their respective maximum or minimum operating

frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter-short term and long term-and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low

to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.

4.3

eTSEC Gigabit Reference Clock Timing

This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.

Table 9. EC_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LV_DD= 2.5 0.125 mV/ 3.3 V 165 mV

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Note

EC_GTX_CLK125 frequency

EC_GTX_CLK125 cycle time

EC_GTX_CLK rise and fall time

t_G125

—

125

8

—

MT/s

ns

—

1

t

_G125R/t_G125F

—

ns

LV_DD= 2.5 V

LV_DD= 3.3 V

0.75

1.0

EC_GTX_CLK125 duty cycle

1000Base-T for RGMII, RTBI

t_G125H/t_G125

—

%

2

47

—

53

EC_GTX_CLK125 jitter

—

150

ps

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LV_DD= 2.5 V and from 0.6 and 2.7 V for

LV_DD= 3.3 V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The

EC_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle

generated by the eTSEC GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications,” for the duty cycle for

10Base-T and 100Base-T reference clock.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

14

Freescale Semiconductor

5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the chip.

5.1

RESET DC Electrical Characteristics

This table provides the DC electrical characteristics for the RESET pins of the device.

Table 10. RESET Pins DC Electrical Characteristics

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

V_IH

V_IL

—

2.0

–0.3

—

OV_DD+ 0.3

V

Input low voltage

Input current

0.8

30

I_IN

—

μA

V

Output high voltage

Output low voltage

Notes:

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

I_OL= 3.2 mA

2.4

—

0.5

0.4

V

—

V

• This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.

• HRESET and SRESET are open drain pin, thus V_OHis not relevant for these pins.

5.2

RESET AC Electrical Characteristics

This table provides the reset initialization AC timing specifications of the device.

Table 11. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Note

Required assertion time of HRESET to activate reset flow

32

—

t_{PCI_SYNC_IN}

t_CLKIN

1

2

Required assertion time of PORESET with stable clock applied to CLKIN when

the device is in PCI host mode

Required assertion time of PORESET with stable clock applied to PCI_CLK when

the device is in PCI agent mode

32

—

t_{PCI_SYNC_IN}

1

HRESET assertion (output)

512

16

4

—

t_{PCI_SYNC_IN}

t_CLKIN

1

2

HRESET negation to negation (output)

Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],

CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET

when the device is in PCI host mode

Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],

CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET

when the device is in PCI agent mode

4

0

—

t_{PCI_SYNC_IN}

1

Input hold time for POR config signals with respect to negation of HRESET

ns

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

15

Table 11. RESET Initialization Timing Specifications (continued)

Parameter/Condition

Min

Max

Unit

Note

Time for the device to turn off POR config signals with respect to the assertion of

HRESET

—

4

ns

3

Time for the device to start driving functional output signals multiplexed with the

POR configuration signals with respect to the negation of HRESET

1

—

t_{PCI_SYNC_IN}

1, 3

Notes:

1. t_{PCI_SYNC_IN}is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary

clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the

MPC8379E Integrated Host Processor Reference Manual for more details.

2. t_CLKINis the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the

MPC8379E Integrated Host Processor Reference Manual for more details.

3. POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.

Table 12 provides the PLL lock times.

Table 12. PLL Lock Times

Parameter

Min

Max

Unit

Note

PLL lock times

—

100

μs

—

Note:

• The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL

ratio. See Section 23, “Clocking,” for more information.

6 DDR1 and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip.

Note that DDR1 SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.

DD

6.1

DDR1 and DDR2 SDRAM DC Electrical Characteristics

This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

device when GV (typ) = 1.8 V.

DD

Table 13. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V

DD

Parameter

I/O supply voltage

Symbol

Min

Max

Unit

Note

GV_DD

MV_REF

V_TT

1.71

0.49 × GV_DD

MV_REF– 0.04

MV_REF+ 0.140

–0.3

1.89

0.51 × GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

MV_REF– 0.140

50

V

1

2, 5

3

I/O reference voltage

I/O termination voltage

Input high voltage

V

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

Output high current (V_OUT= 1.40 V)

I_OZ

–50

μA

mA

I_OH

–13.4

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

16

Table 13. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V (continued)

DD

Parameter

Symbol

Min

Max

Unit

Note

Output low current (V_OUT= 0.3 V)

I_OL

13.4

—

mA

—

Notes:

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to be equal to 0.5 × GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak

noise on MV_REFmay not exceed 2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV_REF. This rail should track variations in the DC level of MV_REF

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

.

Table 14 provides the DDR2 capacitance when GV (typ) = 1.8 V.

DD

Table 14. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V

DD

Parameter

Symbol

Min

Max

Unit

Note

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 1.8 V 0.090 V, f = 1 MT/s, T_A= 25°C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

This table provides the recommended operating conditions for the DDR SDRAM component(s) when

GV (typ) = 2.5 V.

DD

Table 15. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V

DD

Parameter

I/O supply voltage

Symbol

Min

Max

Unit

Note

GV_DD

MV_REF

V_TT

2.375

0.49 × GV_DD

MV_REF– 0.04

MV_REF+ 0.18

–0.3

2.625

0.51 × GV_DD

MV_REF+ 0.04

GV_DD+ 0.3

MV_REF– 0.18

50

V

1

2, 5

3

I/O reference voltage

I/O termination voltage

Input high voltage

V

V_IH

V

—

4

Input low voltage

V_IL

V

Output leakage current

Output high current (V_OUT= 1.9 V)

Output low current (V_OUT= 0.38 V)

Notes:

I_OZ

–50

μA

mA

I_OH

–15.2

—

I_OL

15.2

—

1. GV_DDis expected to be within 50 mV of the DRAM GV_DDat all times.

2. MV_REFis expected to be equal to 0.5 × GV_DD, and to track GV_DDDC variations as measured at the receiver. Peak-to-peak

noise on MV_REFmay not exceed 2% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV_REF. This rail should track variations in the DC level of MV_REF

4. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

17

Table 16 provides the DDR capacitance when GV (typ) = 2.5 V.

DD

Table 16. DDR SDRAM Capacitance for GV (typ) = 2.5 V

DD

Parameter

Symbol

Min

Max

Unit

Note

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Note:

C_IO

6

8

pF

1

C_DIO

—

0.5

1. This parameter is sampled. GV_DD= 2.5 V 0.125 V, f = 1 MT/s, T_A= 25°C, V_OUT= GV_DD/2, V_OUT(peak-to-peak) = 0.2 V.

This table provides the current draw characteristics for MV

.

REF

Table 17. Current Draw Characteristics for MV

REF

Parameter

Symbol

Min

Typ

Max

Unit

Note

Current draw for MV_REF

I_MVREF

μA

1, 2

DDR1

DDR2

—

250

150

600

400

Note:

1. The voltage regulator for MV_REFmust be able to supply up to the stated maximum current.

2. This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.

6.2

DDR1 and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR1 and DDR2 SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.

Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

Parameter

Symbol

Min

Max

Unit

AC input low voltage

AC input high voltage

V_IL

—

MV_REF– 0.25

—

V

V_IH

MV_REF+ 0.25

This table provides the input AC timing specifications for the DDR1 SDRAM when GV (typ) = 2.5 V.

DD

Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface

Parameter

Symbol

Min

Max

Unit

AC input low voltage

AC input high voltage

V_IL

—

MV_REF– 0.31

—

V

V_IH

MV_REF+ 0.31

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

18

This table provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.

Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications

Parameter

Symbol

Min

Max

Unit

Note

Controller skew for MDQS-MDQ/MECC/MDM

400 MT/s data rate

t_CISKEW

ps

1, 2

3

—

–500

–750

500

750

333 MT/s data rate

266 MT/s data rate

Note:

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that

will be captured with MDQSn. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW. This can be

determined by the following equation: t_DISKEW= [T/4 – ꢀt_CISKEWꢀ] where T is the MCK clock period and ꢀt_CISKEWꢀ is the

absolute value of t_CISKEW

.

3. This specification applies only to DDR2 interface.

6.2.2

DDR1 and DDR2 SDRAM Output AC Timing Specifications

This table shows the DDR1 and DDR2 SDRAM output AC timing specifications.

Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications

Parameter

Symbol¹

Min

Max

Unit

Note

MCKn cycle time, MCKn/MCKn crossing

t_MCK

5

12

ns

2

ADDR/CMD output setup with respect to MCK

400 MT/s data rate

t_DDKHAS

3, 7

1.95

2.40

3.15

4.20

—

333 MT/s data rate

266 MT/s data rate

200 MT/s data rate

ADDR/CMD output hold with respect to MCK

400 MT/s data rate

t_DDKHAX

t_DDKHCS

t_DDKHCX

t_DDKHMH

ns

3, 7

4, 8

1.95

2.40

3.15

4.20

—

333 MT/s data rate

266 MT/s data rate

200 MT/s data rate

MCSn output setup with respect to MCK

400 MT/s data rate

1.95

2.40

3.15

4.20

—

333 MT/s data rate

266 MT/s data rate

200 MT/s data rate

MCSn output hold with respect to MCK

400 MT/s data rate

1.95

2.40

3.15

4.20

—

333 MT/s data rate

266 MT/s data rate

200 MT/s data rate

MCK to MDQS skew

–0.6

0.6

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

19

Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)

Parameter

Symbol¹

Min

Max

Unit

Note

MDQ//MDM output setup with respect to MDQS

400 MT/s data rate

t_DDKHDS,

t_DDKLDS

ps

5, 8

550

800

1100

1200

—

333 MT/s data rate

266 MT/s data rate

200 MT/s data rate

MDQ//MDM output hold with respect to MDQS

400 MT/s data rate

t_DDKHDX,

t_DDKLDX

ps

5, 8

700

800

1100

1200

—

333 MT/s data rate

266 MT/s data rate

200 MT/s data rate

MDQS preamble start

MDQS epilogue end

Notes:

t_DDKHMP

t_DDKHME

–0.5 × t_MCK–0.6

–0.6

–0.5 × t_MCK+ 0.6

ns

6, 8

0.6

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

t_DDKHASsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until

outputs (A) are setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock

reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, MODT, and MDQ/MDM/MDQS.

4. Note that t_DDKHMHfollows the symbol conventions described in Note 1. For example, t_DDKHMHdescribes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through

control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock

adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set

to the same adjustment value. See the MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description

and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or

data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCKn at the pins of the microprocessor. Note that t_DDKHMPfollows the

symbol conventions described in Note 1.

7. Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.

8. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

The minimum frequency for DDR2 is 250 MT/s data rate (125 MT/s clock), 167 MT/s data rate (83 MT/s

clock) for DDR1. This figure shows the DDR1 and DDR2 SDRAM output timing for the MCK to MDQS

skew measurement (t

).

DDKHMH

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

20

MCK[n]

t_MCK

t_{DDKHMHmax) = 0.6 ns}

MDQS

t_{DDKHMH(min) = –0.6 ns}

Figure 4. DDR Timing Diagram for t

DDKHMH

This figure shows the DDR1 and DDR2 SDRAM output timing diagram.

MCK[n]

t_MCK

t_DDKHAS,t_DDKHCS

t_DDKHAX,t_DDKHCX

ADDR/CMD

Write A0

t_DDKHMP

NOOP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHDS

t_DDKHME

t_DDKLDS

D0

D1

t_DDKLDX

t_DDKHDX

Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

21

This figure provides AC test load for the DDR bus.

GVDD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 6. DDR AC Test Load

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the chip.

7.1

DUART DC Electrical Characteristics

This table provides the DC electrical characteristics for the DUART interface of the device.

Table 22. DUART DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

V_IH

V_IL

2

OV_DD+ 0.3

V

Low-level input voltage OV_DD

–0.3

0.8

—

High-level output voltage,

V_OH

OV_DD– 0.2

I_OH= –100 μA

Low-level output voltage,

I_OL= 100 μA

V_OL

—

0.2

30

V

Input current,

I_IN

—

μA

(0 V ≤V_IN≤ OV_DD

)

Note: The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 2.

7.2

DUART AC Electrical Specifications

this table provides the AC timing parameters for the DUART interface of the device.

Table 23. DUART AC Timing Specifications

Parameter

Value

Unit

Note

Minimum baud rate

Maximum baud rate

Oversample rate

Notes:

256

> 1,000,000

16

baud

—

1

2

1. Actual attainable baud rate will be limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8^thsampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16^thsample.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

22

Freescale Semiconductor

8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet

controller.

8.1

Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)—MII/RGMII/RTBI/RMII DC Electrical

Characteristics

The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit

media independent interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent

interface (RMII) signals, management data input/output (MDIO) and management data clock (MDC).

The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated

at 2.5 V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface

(RGMII) Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification

Version 1.2.

8.1.1

MII, RMII, RGMII, and RTBI DC Electrical Characteristics

MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 24 and

Table 25. The RGMII and RTBI signals in Table 25 are based on a 2.5 V CMOS interface voltage as

defined by JEDEC EIA/JESD8-5.

Table 24. MII and RMII DC Electrical Characteristics

Parameter

Supply voltage 3.3 V

Symbol

Min

Max

Unit

Note

LV_DD1

LV_DD2

3.13

3.47

V

1

Output high voltage

(LV_DD1/LV_DD2= Min, I_OH= –4.0 mA)

V_OH

2.40

LV_DD1/LV_DD2+ 0.3

0.50

V

—

Output low voltage

V_OL

GND

(LV_DD1/LV_DD2= Min, I_OL= 4.0 mA)

Input high voltage

Input low voltage

Input high current

V_IH

V_IL

I_IH

2.0

–0.3

—

LV_DD1/LV_DD2+ 0.3

V

—

1

0.90

30

μA

(V_IN= LV_DD1, V_IN= LV_DD2

)

Input low current

(V_IN= GND)

I_IL

–600

—

μA

—

Notes:

1. LV_DD1supports eTSEC 1. LV_DD2supports eTSEC 2.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

23

Table 25. RGMII and RTBI DC Electrical Characteristics

Parameter

Supply voltage 2.5 V

Symbol

Min

Max

Unit

Note

LV_DD1

LV_DD2

2.37

2.63

V

1

Output high voltage

(LV_DD1/LV_DD2= Min, IOH = –1.0 mA)

V_OH

2.00

LV_DD1/LV_DD2+ 0.3

0.40

V

—

Output low voltage

V_OL

GND – 0.3

(LV_DD1/LV_DD2= Min, I_OL= 1.0 mA)

Input high voltage

Input low voltage

Input high current

V_IH

V_IL

I_IH

1.7

–0.3

—

LV_DD1/LV_DD2+ 0.3

V

—

1

0.70

–20

μA

(V_IN= LV_DD1, V_IN= LV_DD2

)

Input low current

(V_IN= GND)

I_IL

–20

—

μA

—

Notes:

1. LV_DD1supports eTSEC 1. LV_DD2supports eTSEC 2.

8.2

MII, RGMII, RMII, and RTBI AC Timing Specifications

The AC timing specifications for MII, RGMII, RMII, and RTBI are presented in this section.

8.2.1

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.1.1

MII Transmit AC Timing Specifications

This table provides the MII transmit AC timing specifications.

Table 26. MII Transmit AC Timing Specifications

At recommended operating conditions with LV_DDof 3.3 V 5%.

Parameter

Symbol¹

Min

Typical

Max

Unit

TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

t_MTX

_MTXH/t_MTX

t_MTKHDX

—

35

1

400

40

—

5

—

65

15

ns

%

t

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

ns

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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24

Table 26. MII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 3.3 V 5%.

Parameter

Symbol¹

Min

Typical

Max

Unit

TX_CLK data clock rise (20%–80%)

TX_CLK data clock fall (80%–20%)

Note:

t_MTXR

t_MTXF

1.0

—

4.0

ns

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII

transmit timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

This figure shows the MII transmit AC timing diagram.

t_MTXR

t_MTX

TX_CLK

t_MTXF

t_MTXH

TXD[3:0]

TX_EN

TX_ER

t_MTKHDX

Figure 7. MII Transmit AC Timing Diagram

8.2.1.2

MII Receive AC Timing Specifications

This table provides the MII receive AC timing specifications.

Table 27. MII Receive AC Timing Specifications

At recommended operating conditions with LV_DDof 3.3 V 5%.

Parameter

Symbol¹

Min

Typical

Max

Unit

Input low voltage

V_IL

V_IH

—

1.9

—

0.7

—

65

—

V

Input high voltage

V

RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

t_MRX

400

40

—

ns

%

ns

t_MRX

—

t_MRXH/t_MRX

t_MRDVKH

t_MRDXKH

35

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

10.0

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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25

Table 27. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 3.3 V 5%.

Parameter

Symbol¹

Min

Typical

Max

Unit

RX_CLK clock rise time (20%–80%)

RX_CLK clock fall time (80%–20%)

Note:

t_MRXR

t_MRXF

1.0

—

4.0

ns

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKH

symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the

t

_MRXclock reference (K) going to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with

respect to the time data input signals (D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state

or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock

of a particular functional. For example, the subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

This figure provides the AC test load for eTSEC.

Output

LVDD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 8. eTSEC AC Test Load

This figure shows the MII receive AC timing diagram.

t_MRX

t_MRXR

RX_CLK

t_MRXF

Valid Data

t_MRXH

RXD[3:0]

RX_DV

RX_ER

t_MRDVKH

t_MRDXKL

Figure 9. MII Receive AC Timing Diagram

8.2.2

RGMII and RTBI AC Timing Specifications

This table presents the RGMII and RTBI AC timing specifications.

Table 28. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LV_DDof 2.5 V 5%.

Parameter

Symbol¹

Min

Typical

Max

Unit

Note

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)

Clock period

t_SKRGT

t_RGT

–600

1.0

0

600

2.8

8.8

ps

ns

—

2

—

7.2

8.0

3

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

26

Table 28. RGMII and RTBI AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 2.5 V 5%.

Parameter

Symbol¹

Min

Typical

Max

Unit

Note

Duty cycle for 1000Base-T

t_RGTH/t_RGT

t_RGTR

45

40

—

47

50

—

55

60

%

4

3, 4

—

5

Duty cycle for 10BASE-T and 100BASE-TX

Rise time (20%–80%)

0.75

—

ns

%

Fall time (20%–80%)

t_RGTF

—

EC_GTX_CLK125 reference clock period

t_G12

8.0

—

EC_GTX_CLK125 reference clock duty cycle

t_G125H/t_G125

53

—

measured at 0.5 × LV_DD1

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being

represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns 40 ns and 40 ns 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed

transitioned between

5. This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention.

This figure provides the AC test load for eTSEC.

Output

LVDD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 10. eTSEC AC Test Load

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

27

This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.

t_RGT

t_RGTH

GTX_CLK

(At Transmitter)

t_{SKRGT_TX}

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[8:5]

TXD[7:4]

TXD[3:0]

TXD[9]

TXERR

TXD[4]

TXEN

TX_CTL

t_{SKRGT_RX}

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[8:5]

RXD[7:4]

RXD[3:0]

t_{SKRGT_TX}

RXD[9]

RXERR

RXD[4]

RXDV

RX_CTL

t_{SKRGT_RX}

RX_CLK

(At PHY)

Figure 11. RGMII and RTBI AC Timing and Multiplexing Diagrams

8.2.3

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.3.1

RMII Transmit AC Timing Specifications

This table shows the RMII transmit AC timing specifications.

Table 29. RMII Transmit AC Timing Specifications

At recommended operating conditions with LV_DDof 3.3 V 5%.

Parameter

Symbol¹

Min

Typical

Max

Unit

REF_CLK clock period

t_RMT

t_RMTH

t_RMTJ

t_RMTR

15.0

35

20.0

50

25.0

65

ns

%

REF_CLK duty cycle

REF_CLK peak-to-peak jitter

Rise time REF_CLK (20%–80%)

—

250

2.0

ps

ns

1.0

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

28

Table 29. RMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 3.3 V 5%.

Parameter

Symbol¹

Min

Typical

Max

Unit

Fall time REF_CLK (80%–20%)

REF_CLK to RMII data TXD[1:0], TX_EN delay

Note:

t_RMTF

1.0

2.0

—

2.0

ns

t_RMTDX

10.0

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MTKHDXsymbolizes MII

transmit timing (MT) for the time t_MTXclock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of t_MTXrepresents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

This figure shows the RMII transmit AC timing diagram.

t_RMTR

t_RMT

REF_CLK

t_RMTF

t_RMTH

TXD[1:0]

TX_EN

TX_ER

t_RMTDX

Figure 12. RMII Transmit AC Timing Diagram

8.2.3.2

RMII Receive AC Timing Specifications

This table shows the RMII receive AC timing specifications.

Table 30. RMII Receive AC Timing Specifications

At recommended operating conditions with LV_DDof 3.3 V 5%.

Parameter/Condition

Symbol¹

Min

Typical

Max

Unit

Input low voltage at 3.3 LV_DD

Input high voltage at 3.3 LV_DD

REF_CLK clock period

V_IL

—

2.0

15.0

35

—

0.8

—

V

V_IH

V

t_RMR

t_RMRH

t_RMRJ

t_RMRR

t_RMRF

20.0

50

—

25.0

65

ns

%

ps

ns

REF_CLK duty cycle

REF_CLK peak-to-peak jitter

Rise time REF_CLK (20%–80%)

Fall time REF_CLK (80%–20%)

—

250

2.0

1.0

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

29

Table 30. RMII Receive AC Timing Specifications (continued)

At recommended operating conditions with LV_DDof 3.3 V 5%.

Parameter/Condition

Symbol¹

Min

Typical

Max

Unit

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge

Note:

t_RMRDV

t_RMRDX

4.0

2.0

—

ns

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MRDVKH

symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the

t_MRXclock reference (K) going to the high (H) state or setup time. Also, t_MRDXKLsymbolizes MII receive timing (GR) with

respect to the time data input signals (D) went invalid (X) relative to the t_MRXclock reference (K) going to the low (L) state

or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock

of a particular functional. For example, the subscript of t_MRXrepresents the MII (M) receive (RX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

This figure provides the AC test load for eTSEC.

Output

LVDD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 13. eTSEC AC Test Load

This figure shows the RMII receive AC timing diagram.

t_RMR

t_RMRR

REF_CLK

t_RMRF

Valid Data

t_RMRH

RXD[1:0]

CRS_DV

RX_ER

t_RMRDV

t_RMRDX

Figure 14. RMII Receive AC Timing Diagram

8.3

Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock).

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

30

Freescale Semiconductor

This figure provides the AC test load for eTSEC.

LVDD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 15. eTSEC AC Test Load

8.3.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. The DC electrical

characteristics for MDIO and MDC are provided in Table 31 and Table 32.

Table 31. MII Management DC Electrical Characteristics When Powered at 2.5 V

Parameter

Conditions

Symbol

Min

Max

Unit

Supply voltage (2.5 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

—

LV_DD1

V_OH

V_OL

V_IH

V_IL

2.37

2.00

2.63

V

I_OH= –1.0 mA

LV_DD1= Min

LV_DD1+ 0.3

I_OL= 1.0 mA

LV_DD1= Min

GND – 0.3

1.7

0.40

—

V

—

V

–0.3

0.70

20

V

V_IN= LV_DD1

I_IH

—

μA

I_IL

–15

—

Table 32. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter

Conditions

Symbol

Min

Max

Unit

Supply voltage (3.3 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

—

LV_DD1

V_OH

V_OL

V_IH

V_IL

3.135

2.10

GND

2.00

—

3.465

V

I_OH= –1.0 mA

I_OL= 1.0 mA

LV_DD1= Min

LV_DD1+ 0.3

0.50

—

V

—

V

0.80

30

V

LV_DD1= Max

V_IN¹= 2.1 V

V_IN= 0.5 V

I_IH

—

μA

I_IL

–600

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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31

8.3.2

MII Management AC Electrical Specifications

This table provides the MII management AC timing specifications.

Table 33. MII Management AC Timing Specifications

Parameter

MDC frequency

Symbol¹

Min

Typical

Max

Unit

Note

f_MDC

t_MDC

—

2.5

—

MT/s

ns

2

—

4

MDC period

80

400

MDC clock pulse width high

MDC to MDIO valid

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time (20%–80%)

MDC fall time (80%–20%)

Notes:

t_MDCH

32

—

ns

t_MDKHDV

t_MDKHDX

t_MDDVKH

t_MDDXKH

t_MDCR

2 × (t_{plb_clk}× 8)

—

ns

10

5

2 × (t_{plb_clk}× 8)

ns

2, 4

—

3

—

10

ns

0

ns

—

ns

t_MDCF

ns

3

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDX

symbolizes management data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input

signals (D) reach the valid state (V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time. For

rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed.

3. Guaranteed by design.

4. t_{plb_clk}is the platform (CSB) clock divided according to the SCCR[TSEC1CM].

This figure shows the MII management AC timing diagram.

t_MDCR

t_MDC

MDC

t_MDCF

t_MDCH

MDIO

(Input)

t^MDDVKH

t_MDDXKH

MDIO

(Output)

t_MDKHDX

Figure 16. MII Management Interface Timing Diagram

9 USB

This section provides the AC and DC electrical characteristics for the USB dual-role controllers.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

32

Freescale Semiconductor

9.1

USB DC Electrical Characteristics

This table provides the DC electrical characteristics for the ULPI interface at recommended

OV = 3.3 V ± 165 mV.

DD

Table 34. USB DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Note

High-level input voltage

Low-level input voltage

Input current

V_IH

V_IL

2

–0.3

OV_DD+ 0.3

V

1

0.8

30

I_IN

—

μA

V

2

High-level output voltage, I_OH= –100 μA

Low-level output voltage, I_OL= 100 μA

Notes:

V_OH

V_OL

OV_DD– 0.2

—

0.2

V

1. The minimum V_ILand maximum V_IHvalues are based on the respective minimum and maximum OV_INvalues found in

Table 3.

2. The symbol OV_INrepresents the input voltage of the supply and is referenced in Table 3.

9.2

USB AC Electrical Specifications

This table describes the general timing parameters of the USB interface of the device.

Table 35. USB General Timing Parameters (ULPI Mode Only)

Parameter

Symbol ¹

Min

Max

Unit

Note

USB clock cycle time

t_USCK

t_USIVKH

t_USIXKH

t_USKHOV

t_USKHOX

15

4

—

7

ns

2, 3, 4, 5

Input setup to USB clock—all inputs

Input hold to USB clock—all inputs

USB clock to output valid—all outputs

Output hold from USB clock—all outputs

Notes:

1

—

2

—

1. The symbols for timing specifications follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}for inputs

and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_USIXKHsymbolizes USB timing (US)

for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t_USKHOXsymbolizes

USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold

time.

2. All timings are in reference to the USB clock, USBDR_CLK.

3. All signals are measured from OV_DD/2 of the rising edge of the USB clock to 0.5 × OV_DDof the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered

through the component pin is less than or equal to that of the leakage current specification.

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

33

These two figures provide the AC test load and signals for the USB, respectively.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 17. USB AC Test Load

USBDR_CLK

t_USIXKH

t_USIVKH

Input Signals

t_USKHOX

t_USKHOV

Output Signals

Figure 18. USB Interface Timing Diagram

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the chip.

10.1 Local Bus DC Electrical Characteristics

This tables provide the DC electrical characteristics for the local bus interface.

Table 36. Local Bus DC Electrical Characteristics (LBV = 3.3 V)

DD

At recommended operating conditions with LBV_DD= 3.3 V.

Parameter

Conditions

Symbol

Min

Max

Unit

Supply voltage 3.3 V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

—

LBV_DD

V_OH

V_OL

V_IH

3.135

2.40

—

3.465

V

I_OH= –4.0 mA

LBV_DD= Min

—

0.50

I_OL= 4.0 mA

LBV_DD= Min

V

—

2.0

LBV_DD+ 0.3

0.90

V

V_IL

–0.3

—

V

V_IN¹= LBV_DD

V_IN¹= GND

I_IH

30

μA

I_IL

–30

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

34

Table 37. Local Bus DC Electrical Characteristics (LBV = 2.5 V)

DD

At recommended operating conditions with LBV_DD= 2.5 V.

Parameter

Conditions

Symbol

Min

Max

Unit

Supply voltage 2.5 V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

—

LBV_DD

V_OH

V_OL

V_IH

2.37

2.00

—

2.73

V

I_OH= –1.0 mA

LBV_DD= Min

—

0.40

I_OL= 1.0 mA

V

—

1.7

LBV_DD+ 0.3

0.70

V

V_IL

–0.3

—

V

V_IN¹= LBV_DD

V_IN¹= GND

I_IH

20

μA

I_IL

–20

—

Table 38. Local Bus DC Electrical Characteristics (LBV = 1.8 V)

DD

At recommended operating conditions with LBV_DD= 1.8 V.

Parameter

Conditions

Symbol

Min

Max

Unit

Supply voltage 1.8 V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

—

LBV_DD

V_OH

V_OL

V_IH

1.71

1.89

V

I_OH= –1.0 mA

LBV_DD= Min

LBV_DD– 0.45

—

0.45

I_OL= 1.0 mA

—

0.65 × LBV_DD

–0.3

V

—

LBV_DD+ 0.3

0.35 × LBV_DD

10

V

V_IL

V

V_IN¹= LBV_DD

V_IN¹= GND

I_IH

—

μA

I_IL

–10

—

10.2 Local Bus AC Electrical Specifications

This table describes the general timing parameters of the local bus interface of the device when in PLL

enable mode.

Table 39. Local Bus General Timing Parameters—PLL Enable Mode

Parameter

Symbol¹

Min

Max

Unit

Note

Local bus cycle time

t_LBK

7.5

1.5

1.0

1.5

3

15

—

ns

2

3, 4

5

Input setup to local bus clock (except LUPWAIT/LGTA)

Input hold from local bus clock

t_LBIVKH

t_LBIXKH

—

LUPWAIT/LGTA input setup to local bus clock

LALE output fall to LAD output transition (LATCH hold time)

Local bus clock to LALE rise

t_LBIVKH1

t_LBOTOT1

t_LBOTOT2

t_LBOTOT3

t_LBKHLR

t_LBKHOV

—

6

2.5

—

7

4.5

—

3

Local bus clock to output valid (except LALE)

—

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

35

Table 39. Local Bus General Timing Parameters—PLL Enable Mode (continued)

Parameter

Symbol¹

Min

Max

Unit

Note

Local bus clock to output high impedance for LAD/LDP

Output hold from local bus clock for LAD/LDP

Notes:

t_LBKHOZ

t_LBKHOX

—

1

3.8

—

ns

3, 8

3

1. The symbols used for timing specifications herein follow the pattern of t_{(First two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1

symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes

high (H), in this case for clock one(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go

high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to rising edge of LSYNC_IN at LBV_DD/2 and the 0.5 × LBV_DDof the signal in question.

3. All signals are measured from LBV_DD/2 of the rising/falling edge of LSYNC_IN to 0.5 × LBV_DDof the signal in question.

4. Input timings are measured at the pin.

5. t_LBOTOT1should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on

LAD output pins.

6. t_LBOTOT2should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load

on LAD output pins.

7. t_LBOTOT3should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

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Freescale Semiconductor

This table describes the general timing parameters of the local bus interface of the device when in PLL

bypass mode.

Table 40. Local Bus General Timing Parameters—PLL Bypass Mode

Parameter

Symbol¹

Min

Max

Unit

Note

Local bus cycle time

t_LBK

15

7.0

1.0

1.5

3.0

2.5

—

ns

2

3, 4

5

Input setup to local bus clock

t_LBIVKH

Input hold from local bus clock

t_LBIXKH

—

LALE output fall to LAD output transition (LATCH hold time)

Local bus clock to LALE rise

t_LBOTOT1

t_LBOTOT2

t_LBOTOT3

t_LBKHLR

t_LBKHOV

t_LBKHOZ

—

6

—

7

4.5

3.0

4.0

—

3

Local bus clock to output valid

—

Local bus clock to output high impedance for LAD/LDP

Notes:

—

3, 8

1. The symbols used for timing specifications herein follow the pattern of t_{(First two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_LBIXKH1

symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t_LBKclock reference (K) goes

high (H), in this case for clock one(1). Also, t_LBKHOXsymbolizes local bus timing (LB) for the t_LBKclock reference (K) to go

high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from LBV_DD/2 of the rising/falling edge of LCLK0 to 0.5 × LBV_DDof the signal in question for 3.3-V

signaling levels.

4. Input timings are measured at the pin.

5. t_LBOTOT1should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on

LAD output pins.

6. t_LBOTOT2should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load

on LAD output pins.

7. t_LBOTOT3should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

This figure provides the AC test load for the local bus.

OVDD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 19. Local Bus AC Test Load

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This figures show the local bus signals.

LSYNC_IN

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBIXKH

t_LBIVKH

Input Signal:

LGTA

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

t_LBKHOX

t_LBKHOV

LA[27:31]/LBCTL/LBCKE/LOE

t_LBKHOZ

t_LBKHOX

t_LBKHOV

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ

t_LBKHOX

t_LBKHOV

Output (Address) Signal:

LAD[0:31]

t_LBOTOT

t_LBKHLR

LALE

Figure 20. Local Bus Signals, Non-special Signals Only (PLL Enable Mode)

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38

LCLK[n]

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]

t_LBIXKH

t_LBIVKH

Input Signal:

LGTA

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

t_LBKHOV

LA[27:31]/LBCTL/LBCKE/LOE

t_LBKHOZ

t_LBKHOV

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ

t_LBKHOV

Output (Address) Signal:

LAD[0:31]

t_LBOTOT

t_LBKHLR

LALE

Figure 21. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode)

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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LSYNC_IN

T1

T3

t_LBKHOV

t_LBKHOX

GPCM Mode Output Signals:

LCS[0:7]/LWE[0:3]

t_LBIXKH

t_LBIVKH

t_LBKHOX

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOV

UPM Mode Output Signals:

LCS[0:7]/LBS[0:1]/LGPL[0:5]

t_LBKHOZ

t_LBKHOX

t_LBKHOV

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ

t_LBKHOX

t_LBKHOV

Output (Address) Signal:

LAD[0:31]

Figure 22. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode)

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40

LCLK

T1

T3

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:7]/LWE[0:3]

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOV

UPM Mode Output Signals:

LCS[0:7]/LBS[0:1]/LGPL[0:5]

t_LBKHOZ

t_LBKHOV

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ

t_LBKHOV

Output (Address) Signal:

LAD[0:31]

Figure 23. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Bypass Mode)

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41

LSYNC_IN

T1

T2

T3

T4

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:7]/LWE[0:3]

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]

t_LBKHOX

t_LBKHOV

UPM Mode Output Signals:

LCS[0:7]/LBS[0:1]/LGPL[0:5]

t_LBKHOZ

t_LBKHOX

t_LBKHOV

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ

t_LBKHOX

t_LBKHOV

Output (Address) Signal:

LAD[0:31]

Figure 24. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode)

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LCLK

T1

T2

T3

T4

t_LBKHOZ

t_LBKHOV

GPCM Mode Output Signals:

LCS[0:7]/LWE[0:3]

t_LBIXKH

t_LBIVKH

UPM Mode Input Signal:

LUPWAIT

t_LBIXKH

t_LBIVKH

Input Signals:

LAD[0:31]

t_LBKHOV

UPM Mode Output Signals:

LCS[0:7]/LBS[0:1]/LGPL[0:5]

t_LBKHOZ

t_LBKHOV

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

t_LBKHOZ

t_LBKHOV

Output (Address) Signal:

LAD[0:31]

Figure 25. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Bypass Mode)

11 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the

chip.

The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the

SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full-

and high-speed modes.

Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed

mode, data is driven at the rising edge of the clock.

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43

Due to the special implementation of the eSDHC, there are constraints regarding the clock and data signals

propagation delay on the user board. The constraints are for minimum and maximum delays, as well as

skew between the CLK and DAT/CMD signals.

In full speed mode, there is no need to add special delay on the data or clock signals. The user should make

sure to meet the timing requirements as described further within this document.

If the system is designed to support both high-speed and full-speed cards, the high-speed constraints

should be fulfilled. If the systems is designed to operate up to 25 MT/s only, full-speed mode is

recommended.

11.1 eSDHC DC Electrical Characteristics

This table provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device.

Table 41. eSDHC interface DC Electrical Characteristics

Parameter

Input high voltage

Symbol

Condition

Min

Max

Unit

V_IH

V_IL

—

0.625 × OV_DD

–0.3

OV_DD+ 0.3

V

Input low voltage

Input current

0.25 × OV_DD

I_IN

—

30

—

μA

V

Output high voltage

V_OH

I_OH= –100 uA,

at OV_DD(min)

0.75 × OV_DD

Output low voltage

V_OL

I_OL= +100 uA,

at OV_DD(min)

—

0.125 × OV_DD

V

11.2 eSDHC AC Timing Specifications (Full-Speed Mode)

This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.

This table provides the eSDHC AC timing specifications for full-speed mode as defined in Figure 27 and

Figure 28.

Table 42. eSDHC AC Timing Specifications for Full-Speed Mode

At recommended operating conditions OV_DD= 3.3 V 165 mV.

Parameter

Symbol¹

Min

Max

Unit

Note

SD_CLK clock frequency—full speed mode

SD_CLK clock cycle

f_SFSCK

t_SFSCK

f_SIDCK

0

25

—

MT/s

ns

—

2

40

0

SD_CLK clock frequency—identification mode

SD_CLK clock low time

400

—

KHz

ns

t_SFSCKL

t_SFSCKH

t_SFSCKR

15

—

SD_CLK clock high time

—

ns

2

SD_CLK clock rise and fall times

/

5

ns

2

t_SFSCKF

Input setup times: SD_CMD, SD_DATx, SD_CD to

SD_CLK

t_SFSIVKH

5

—

ns

2

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44

Table 42. eSDHC AC Timing Specifications for Full-Speed Mode (continued)

At recommended operating conditions OV_DD= 3.3 V 165 mV.

Parameter

Symbol¹

Min

Max

Unit

Note

Input hold times: SD_CMD, SD_DATx, SD_CD to

t_SFSIXKH

0

—

ns

2

SD_CLK

SD_CLK delay within device

Output valid: SD_CLK to SD_CMD, SD_DATx valid

Output hold: SD_CLK to SD_CMD, SD_DATx valid

SD card input setup

t_{INT_CLK_DLY}

t_SFSKHOV

t_SFSKHOX

t_ISU

1.5

—

0

—

4

ns

—

ns

4

2

—

14

—

3

5

SD card input hold

t_IH

5

3

SD card output valid

t_ODLY

—

0

3

SD card output hold

t_OH

3

Notes:

1. The symbols used for timing specifications herein follow the pattern of t_{(first three letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first three letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_SFSIXKH

symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K)

going to high (H). Also t_SFSKHOVsymbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with

respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol

representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Measured at capacitive load of 40 pF.

3. For reference only, according to the SD card specifications.

4. Average, for reference only.

This figure provides the eSDHC clock input timing diagram.

eSDHC

External Clock

VM

operational mode

t_SFSCKL

t_SFSCKH

t_SFSCK

t_SFSCKF

t_SFSCKR

VM = Midpoint Voltage (OV_DD/2)

Figure 26. eSDHC Clock Input Timing Diagram

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45

11.2.1 Full-Speed Output Path (Write)

This figure provides the data and command output timing diagram.

t_SFSCK(clock cycle)

SD CLK at the

Driving

MPC8377E pin

Edge

t_{CLK_DELAY}

SD CLK at

the card pin

Sampling

edge

Output valid time: t_SFSKHOV

Output hold time: t_SFSKHOX

Output from the

t_SFSCKL

MPC8377E Pins

Input at the

MPC8377E pins

t_{DATA_DELAY}

t_IH(5 ns)

t_ISU(5 ns)

Figure 27. Full Speed Output Path

11.2.1.1 Full-Speed Write Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

No clock delay:

t

+ t

< t

SFSCKL

Eqn. 1

SFSKHOV

DATA_DELAY

ISU

With clock delay:

t

+ t

< t

+ t

CLK_DELAY

Eqn. 2

Eqn. 3

SFSKHOV

DATA_DELAY

ISU

SFSCKL

t

+ t

< t

+ t

– t

ISU SFSKHOV

DATA_DELAY

SFSCKL

SFSCK

CLK_DELAY

This means that data can be delayed versus clock up to 11 ns in ideal case of t

= 20 ns:

SFSCKL

t

+ 20 < 40 + t

– 5 – 4

DATA_DELAY

CLK_DELAY

< 11 + t

DATA_DELAY

CLK_DELAY

11.2.1.2 Full-Speed Write Meeting Hold (Minimum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

t

< t

+ t

– t

IH

Eqn. 4

CLK_DELAY

SFSCKL

SFSKHOX

DATA_DELAY

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Freescale Semiconductor

46

t

+ t – t

< t + t

SFSCKL DATA_DELAY

Eqn. 5

CLK_DELAY

IH

SFSKHOX

This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of

t

= 20 ns:

SFSCLKL

t

+ 5 – 0 < 20 + t

CLK_DELAY

DATA_DELAY

< 15 + t

CLK_DELAY

DATA_DELAY

11.2.1.3 Full-Speed Write Combined Formula

The following equation is the combined formula to calculate the allowed skew range between the

SD_CLK and SD_DAT/CMD signals on the PCB.

t

+ t – t

< t

+ t

< t

+ t

– t

SFSKHOV

Eqn. 6

CLK_DELAY

IH

SFSKHOX

SFSCKL

DATA_DELAY

SFSCK CLK_DELAY

ISU

11.2.2 Full-Speed Input Path (Read)

This figure provides the data and command input timing diagram.

t_SFSCK(clock cycle)

SD CLK at the

MPC8377E pin

Sampling

edge

t_{CLK_DELAY}

SD CLK at

the card pin

Driving

edge

t_{DATA_DELAY}

t_ODLY

t_OH

Output from the

SD card pins

Input at the

MPC8377E pins

(MPC8377E input hold)

t_SFSIXKH

t_SFSIVKH

Figure 28. Full Speed Input Path

11.2.2.1 Full-Speed Read Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed combined propagation delay range of the

SD_CLK and SD_DAT/CMD signals on the PCB.

t

+ t

< t

SFSCK

Eqn. 7

Eqn. 8

CLK_DELAY

DATA_DELAY

ODLY

SFSIVKH

t

+ t

< t

– t

CLK_DELAY

DATA_DELAY

SFSCK

ODLY

SFSIVKH INT_CLK_DLY

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47

11.2.2.2 Full-Speed Read Meeting Hold (Minimum Delay)

There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.

t

+ t + t

> t

SFSIXKH

Eqn. 9

CLK_DELAY

OH

DATA_DELAY

This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.

11.3 eSDHC AC Timing Specifications (High-Speed Mode)

This table provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 30 and

Figure 31.

Table 43. eSDHC AC Timing Specifications for High-Speed Mode

At recommended operating conditions OV_DD= 3.3 V 165 mV.

Parameter

Symbol¹

Min

Max

Unit

Note

SD_CLK clock frequency—high speed mode

SD_CLK clock cycle

f_SHSCK

t_SHSCK

f_SIDCK

0

20

0

50

—

MT/s

ns

—

2

SD_CLK clock frequency—identification mode

SD_CLK clock low time

400

—

KHz

ns

t_SHSCKL

t_SHSCKH

t_SHSCKR/

7

SD_CLK clock high time

7

—

ns

2

SD_CLK clock rise and fall times

—

3

ns

2

t_SHSCKF

Input setup times: SD_CMD, SD_DATx, SD_CD to

SD_CLK

t_SHSIVKH

5

—

ns

2

Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid

SD_CLK delay within device

t_SHSIXKH

t_SHSKHOV

t_SHSKHOX

t_{INT_CLK_DLY}

t_ISU

0

—

0

—

4

ns

2

4

3

—

14

—

1.5

6

SD Card Input Setup

SD Card Input Hold

t_IH

2

SD Card Output Valid

t_ODLY

—

2.5

SD Card Output Hold

t_OH

Notes:

1. The symbols used for timing specifications herein follow the pattern of t_{(first three letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first three letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_SFSIXKH

symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K)

going to high (H). Also t_SFSKHOVsymbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with

respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol

representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Measured at capacitive load of 40 pF.

3. For reference only, according to the SD card specifications.

4. Average, for reference only.

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Freescale Semiconductor

This figure provides the eSDHC clock input timing diagram.

eSDHC

External Clock

VM

operational mode

t_SHSCKL

t_SHSCKH

t_SHSCK

t_SHSCKF

t_SHSCKR

VM = Midpoint Voltage (OVDD/2)

Figure 29. eSDHC Clock Input Timing Diagram

11.3.1 High-Speed Output Path (Write)

This figure provides the data and command output timing diagram.

t_SHSCK(clock cycle)

SD CLK at the

Driving

MPC8377E pin

Edge

t_{CLK_DELAY}

SD CLK at

the card Pin

Sampling

edge

Output valid time: t_SHSKHOV

Output hold time: t_SHSKHOX

t_SHSCKL

Output from the

MPC8377E pins

Input at the

SD card pins

t_{DATA_DELAY}

t_IH(2 ns)

t_ISU(6 ns)

Figure 30. High Speed Output Path

11.3.1.1 High-Speed Write Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

Zero clock delay:

t

+ t

< t

SHSCKL

Eqn. 10

SHSKHOV

DATA_DELAY

ISU

With clock delay:

t

+ t

< t

+ t

CLK_DELAY

Eqn. 11

Eqn. 12

SHSKHOV

DATA_DELAY

ISU

SHSCKL

t

– t

< t

– t

DATA_DELAY

CLK_DELAY

SHSCKL

ISU SHSKHOV

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49

This means that data delay should be equal or less than the clock delay in the ideal case where

= 10 ns:

t

SHSCLKL

t – t

DATA_DELAY CLK_DELAY

< 10 – 6 – 4

t – t

DATA_DELAY CLK_DELAY

< 0

11.3.1.2 High-Speed Write Meeting Hold (Minimum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

t

< t

+ t

– t

Eqn. 13

Eqn. 14

CLK_DELAY

SHSCKL

SHSKHOX

DATA_DELAY

IH

t

– t

< t

+ t

– t

CLK_DELAY

DATA_DELAY

SHSCKL

SHSKHOX

IH

This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of

= 10 ns:

t

SHSCLKL

t – t

CLK_DELAY DATA_DELAY

< 10 + 0 – 2

t – t

CLK_DELAY DATA_DELAY

< 8

11.3.2 High-Speed Input Path (Read)

This figure provides the data and command input timing diagram.

t_SHSCK(Clock Cycle)

1/2 Cycle

Wrong Edge

Right Edge

SD CLK at the

MPC8377E Pin

Sampling

Edge

t_{CLK_DELAY}

Driving

Edge

SD CLK at

the Card Pin

t_ODLY

t_OH

t_{DATA_DELAY}

Output from the

SD Card Pins

Input at the

MPC8377E Pins

t_SHSIVKH

(MPC8377E Input Setup)

(MPC8377E Input Hold)

t_SHSIXKH

Figure 31. High-Speed Input Path

For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was

driven by the SD card. Since in this mode the SD card drives the data at the rising edge of the clock, a

sufficient delay to the clock and the data must exist to ensure it will not be sampled at the wrong internal

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50

Freescale Semiconductor

clock falling edge. Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample

the data, and therefore used in the equations.

11.3.2.1 High-Speed Read Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed combined propagation delay range of the

SD_CLK and SD_DAT/CMD signals on the PCB.

t

+ t

< 1.5 × t

Eqn. 15

Eqn. 16

CLK_DELAY

DATA_DELAY

ODLY

SHSIVKH

SHSCK

t

+ t

< 1.5 × t

– t

ODLY SHSIVKH

CLK_DELAY

DATA_DELAY

SHSCK

This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle:

t

+ t

< 30 – 14 – 5

CLK_DELAY

DATA_DELAY

< 11

CLK_DELAY

11.3.2.2 High-Speed Read Meeting Hold (Minimum Delay)

The following equations show how to calculate the allowed combined propagation delay range of the

SD_CLK and SD_DAT/CMD signals on the PCB.

0.5 × t

< t

+ t

+ t – t

+ t

INT_CLK_DLY

Eqn. 17

Eqn. 18

SHSCK

CLK_DELAY

DATA_DELAY

OH

SHSIXKH

– t

+ t

– t

< t

+ t

CLK_DELAY DATA_DELAY

SHSCK

OH

SHSIXKH

INT_CLK_DLY

This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:

10 – 2.5 + (–1.5) < t + t

CLK_DELAY

DATA_DELAY

6 < t

+ t

DATA_DELAY

CLK_DELAY

11.3.2.3 High-Speed Read Combined Formula

The following equation is the combined formula to calculate the propagation delay range of the SD_CLK

and SD_DAT/CMD signals on the PCB.

0.5 × t

– t

+ t

< t

+ t

< 1.5 × t

– t

SHSIVKH

Eqn. 19

SHSCK

OH

SHSIXKH

CLK_DELAY

DATA_DELAY

SHSCK

ODLY

12 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of

the chip.

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51

12.1 JTAG DC Electrical Characteristics

This table provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the chip.

Table 44. JTAG interface DC Electrical Characteristics

Parameter

Input high voltage

Symbol

Condition

Min

Max

Unit

V_IH

V_IL

—

2.5

–0.3

—

OV_DD+ 0.3

V

Input low voltage

Input current

0.8

30

I_IN

—

μA

V

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –8.0 mA

I_OL= 8.0 mA

2.4

—

0.5

0.4

V

I

= 3.2 mA

OL

—

V

OL

12.2 JTAG AC Timing Specifications

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.

This table provides the JTAG AC timing specifications as defined in Figure 33 through Figure 36.

1

Table 45. JTAG AC Timing Specifications (Independent of CLKIN)

Parameter

Symbol²

Min

Max

Unit

Note

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

f_JTG

t _JTG

0

33.3

—

2

MT/s

ns

—

3

30

15

0

t_JTKHKL

t_JTGR& t_JTGF

t_TRST

ns

25

—

ns

Input setup times:

ns

Boundary-scan data

t_JTDVKH

t_JTIVKH

4

—

4

TMS, TDI

Input hold times:

Valid times:

ns

Boundary-scan data

TMS, TDI

t_JTDXKH

t_JTIXKH

10

—

Boundary-scan data

TDO

t_JTKLDV

t_JTKLOV

2

11

—

Output hold times:

Boundary-scan data

TDO

t_JTKLDX

t_JTKLOX

2

—

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52

1

Table 45. JTAG AC Timing Specifications (Independent of CLKIN) (continued)

Parameter

Symbol²

Min

Max

Unit

Note

JTAG external clock to output high impedance:

ns

Boundary-scan data

TDO

t_JTKLDZ

t_JTKLOZ

2

19

9

5

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t_TCLKto the midpoint of the signal in

question. The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see

Figure 17). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKH

symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to

the t_JTGclock reference (K) going to the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect

to the time data input signals (D) went invalid (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note

that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t_TCLK

.

5. Non-JTAG signal output timing with respect to t_TCLK

.

This figure provides the AC test load for TDO and the boundary-scan outputs of the device.

Z₀= 50 Ω

OVDD/2

Output

R_L= 50 Ω

Figure 32. AC Test Load for the JTAG Interface

This figure provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t_JTKHKL

VM

t_JTGR

t_JTGF

t_JTG

VM = Midpoint Voltage (OVDD/2)

Figure 33. JTAG Clock Input Timing Diagram

This figure provides the TRST timing diagram.

TRST

VM

t_TRST

VM = Midpoint Voltage (OVDD/2)

Figure 34. TRST Timing Diagram

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

53

This figure provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t_JTDVKH

t_JTDXKH

Boundary

Data Inputs

Input

Data Valid

t_JTKLDV

t_JTKLDX

Boundary

Data Outputs

Output Data Valid

t_JTKLDZ

Output Data Valid

Boundary

Data Outputs

VM = Midpoint Voltage (OVDD/2)

Figure 35. Boundary-Scan Timing Diagram

This figure provides the test access port timing diagram.

JTAG

VM

External Clock

t_JTIVKH

t_JTIXKH

Input

TDI, TMS

TDO

Data Valid

t_JTKLOV

t_JTKLOX

Output Data Valid

t_JTKLOZ

Output Data Valid

TDO

VM = Midpoint Voltage (OVDD/2)

Figure 36. Test Access Port Timing Diagram

MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10

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54

13 I²C

2

This section describes the DC and AC electrical characteristics for the I C interface of the chip.

2

13.1 I C DC Electrical Characteristics

2

This table provides the DC electrical characteristics for the I C interface of the chip.

2

Table 46. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V 165 mV.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage level

Input low voltage level

Low level output voltage

V_IH

V_IL

0.7 × OV_DD

OV_DD+ 0.3

0.3 × OV_DD

0.2 × OV_DD

250

V

—

1

–0.3

0

V_OL

V

Output fall time from V_IH(min) to V_IL(max) with a bus capacitance

from 10 to 400 pF

t

20 + 0.1 × C_B

ns

2

I2KLKV

Pulse width of spikes which must be suppressed by the input filter t_I2KHKL

0

50

10

30

ns

pF

μA

3

—

4

Capacitance for each I/O pin

C_I

—

Input current

I_IN

(0 V ≤ V_IN≤ OV_DD

)

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C_B= capacitance of one bus line in pF.

3. Refer to the MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter

used.

4. I/O pins will obstruct the SDA and SCL lines if OV_DDis switched off.

2

13.2 I C AC Electrical Specifications

2

This table provides the AC timing parameters for the I C interface of the device.

2

Table 47. I C AC Electrical Specifications

All values refer to V_IH(min) and V_IL(max) levels (see Table 46).

Parameter

Symbol¹

Min

Max

Unit

Note

SCL clock frequency

f_I2C

t_I2CL

0

400

—

kHz

μs

—

Low period of the SCL clock

High period of the SCL clock

1.3

0.6

t_I2CH

—

μs

Setup time for a repeated START condition

t_I2SVKH

t_I2SXKL

—

μs

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

—

μs

Data setup time

t_I2DVKH

100

—

ns

—

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55

2

Table 47. I C AC Electrical Specifications (continued)

All values refer to V_IH(min) and V_IL(max) levels (see Table 46).

Parameter

Symbol¹

Min

Max

Unit

Note

Data hold time

t_I2DXKL

μs

2, 3

CBUS compatible masters

I²C bus devices

—

0

—

0.9

Setup time for STOP condition

t

0.6

1.3

—

μs

V

—

I2PVKH

Bus free time between a STOP and START condition

t_I2KHDX

V_NL

Noise margin at the LOW level for each connected device (including

hysteresis)

0.1 × OV_DD

Noise margin at the HIGH level for each connected device (including

hysteresis)

V_NH

0.2 × OV_DD

—

V

—

Notes:

1. The symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKH

symbolizes I²C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t_I2Cclock

reference (K) going to the high (H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with

respect to the start condition (S) went invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time.

Also, t_I2PVKHsymbolizes I²C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid

state (V) relative to the t_I2Cclock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. This chip provides a hold time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL signal) to bridge the

undefined region of the falling edge of SCL.

3. The maximum t_I2DVKHhas only to be met if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

2

This figure provides the AC test load for the I C.

Output

OVDD/2

Z₀= 50 Ω

R_L= 50 Ω

2

Figure 37. I C AC Test Load

2

This figure shows the AC timing diagram for the I C bus.

SDA

t_I2CF

t_I2CL

t_I2DVKH

t_I2KHKL

t_I2CF

t_I2SXKL

t_I2CR

SCL

t_I2SXKL

t_I2CH

t_I2SVKH

t_I2PVKH

t_I2DXKL

S

Sr

P

S

2

Figure 38. I C Bus AC Timing Diagram

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56

14 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the chip.

14.1 PCI DC Electrical Characteristics

This table provides the DC electrical characteristics for the PCI interface of the device. The DC

characteristics of the PORESET signal, which can be used as PCI RST in applications where the device is

a PCI agent, deviates from the standard PCI levels.

Table 48. PCI DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Input current

V_OUT≥ V_OH(min) or

V_OUT≤ V_OL(max)

I_OH= –500 μA

V_IH

V_IL

2.0

–0.5

OV_DD+ 0.5

0.3 × OV_DD

—

V

V_OH

V_OL

I_IN

0.9 × OV_DD

—

V

I

_OL= 1500 μA

0.1 × OV_DD

30

V

0 V ≤ V_IN≤ OV_DD

—

μA

Note:

• The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 2.

14.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the device. Note that the

PCI_CLK/PCI_SYNC_IN or CLKIN signal is used as the PCI input clock depending on whether the chip

is configured as a host or agent device. CLKIN is used when the device is in host mode.

This table shows the PCI AC timing specifications at 66 MT/s.

.

Table 49. PCI AC Timing Specifications at 66 MT/s

PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OV_DD, VIH = 0.7 × OV_DD

.

Parameter

Clock to output valid

Symbol¹

Min

Max

Unit

Note

t_PCKHOV

t_PCKHOX

t_PCKHOZ

t_PCIVKH

—

1

6.0

—

ns

2

Output hold from clock

Clock to output high impedance

Input setup to clock

2

—

3.0

14

—

2, 3

2, 4

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57

Table 49. PCI AC Timing Specifications at 66 MT/s (continued)

PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OV_DD, VIH = 0.7 × OV_DD

.

Parameter

Input hold from cock

Symbol¹

Min

Max

Unit

Note

t_PCIXKH

t_PCKOSK

0.25

—

ns

2, 4, 6

5

Output clock skew

0.5

Notes:

1. Note that the symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_PCIVKH

symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the

PCI_SYNC_IN clock, t_SYS, reference (K) going to the high (H) state or setup time. Also, t_PCRHFVsymbolizes PCI timing (PC)

with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

5. PCI specifications allows 1 ns skew for 66 MT/s but includes the total allowed skew, board, connectors, etc.

6. Value does not comply with the PCI 2.3 Local Bus Specifications.

This table shows the PCI AC timing specifications at 33 MT/s.

Table 50. PCI AC Timing Specifications at 33 MT/s

PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OV_DD, V_IH= 0.7 × OV_DD

.

Parameter

Clock to output valid

Symbol¹

Min

Max

Unit

Note

t

—

2

11

—

ns

2

PCKHOV

Output hold from clock

Clock to output high impedance

Input setup to clock

Input hold from clock

Output clock skew

Notes:

t

PCKHOX