MPC5601F0VLH4_技术文档

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5602P

Rev. 4.1, 09/2011

MPC5602P

MPC5602P Microcontroller

Data Sheet

100 LQFP (14 mm x 14 mm)

64 LQFP (10 mm x 10 mm)

• Up to 64 MHz, single issue, 32-bit CPU core complex

(e200z0h)

– 1 FlexCAN interface (2.0B Active) with 32 message

buffers

– Compliant with Power Architecture embedded category

– Variable Length Encoding (VLE)

• Memory organization

– Up to 256 KB on-chip code flash memory with ECC and

erase/program controller

– Optional: additional 64 (4 × 16) KB on-chip data flash

memory with ECC for EEPROM emulation

– Up to 20 KB on-chip SRAM with ECC

• Fail-safe protection

– 1 safety port based on FlexCAN with 32 message

buffers and up to 8 Mbit/s at 64 MHz capability usable

as second CAN when not used as safety port

• One 10-bit analog-to-digital converter (ADC)

– Up to 16 input channels (16 ch on 100 LQFP and 12 ch

on 64 LQFP)

– Conversion time < 1 µs including sampling time at full

precision

– Programmable Cross Triggering Unit (CTU)

– 4 analog watchdogs with interrupt capability

• On-chip CAN/UART bootstrap loader with Boot Assist

Module (BAM)

– Programmable watchdog timer

– Non-maskable interrupt

– Fault collection unit

• Nexus L1 interface

• 1 FlexPWM unit

• Interrupts and events

– 8 complementary or independent outputs with ADC

synchronization signals

– Polarity control, reload unit

– 16-channel eDMA controller

– 16 priority level controller

– Up to 25 external interrupts

– Integrated configurable dead time unit and inverter fault

input pins

– 16-bit resolution

– PIT implements four 32-bit timers

– 120 interrupts are routed via INTC

• General purpose I/Os

– Lockable configuration

– Individually programmable as input, output or special

function

• Clock generation

– 4–40 MHz main oscillator

– 37 on 64 LQFP

– 64 on 100 LQFP

– 16 MHz internal RC oscillator

– Software-controlled FMPLL capable of up to 64 MHz

• Voltage supply

• 1 general purpose eTimer unit

– 6 timers each with up/down capabilities

– 16-bit resolution, cascadeable counters

– Quadrature decode with rotation direction flag

– Double buffer input capture and output compare

• Communications interfaces

– 3.3 V or 5 V supply for I/Os and ADC

– On-chip single supply voltage regulator with external

ballast transistor

• Operating temperature ranges: –40 to 125 °C or –40 to

105 °C

– Up to 2 LINFlex modules (1× Master/Slave, 1× Master

only)

– Up to 3 DSPI channels with automatic chip select

generation (up to 8/4/4 chip selects)

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

Table of Contents

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1

3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . 33

3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 33

3.4 Recommended operating conditions. . . . . . . . . . . . . . 36

3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40

3.5.1 Package thermal characteristics . . . . . . . . . . . 40

3.5.2 General notes for specifications at maximum

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.5.1 High performance e200z0 core processor. . . . . .7

1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8

1.5.3 Enhanced direct memory access (eDMA) . . . . . .8

1.5.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.5.5 Static random access memory (SRAM). . . . . . . .9

1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . .9

1.5.7 System status and configuration module (SSCM)10

1.5.8 System clocks and clock generation . . . . . . . . .10

1.5.9 Frequency-modulated phase-locked loop (FMPLL)

10

1.5.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.5.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . .11

1.5.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . .11

1.5.13 System timer module (STM) . . . . . . . . . . . . . . .11

1.5.14 Software watchdog timer (SWT) . . . . . . . . . . . .11

1.5.15 Fault collection unit (FCU). . . . . . . . . . . . . . . . .12

1.5.16 System integration unit – Lite (SIUL). . . . . . . . .12

1.5.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . .12

1.5.18 Error correction status module (ECSM). . . . . . .13

1.5.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .13

1.5.20 Controller area network (FlexCAN) . . . . . . . . . .13

1.5.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . .14

1.5.22 Serial communication interface module (LINFlex)14

1.5.23 Deserial serial peripheral interface (DSPI) . . . .15

1.5.24 Pulse width modulator (FlexPWM) . . . . . . . . . .15

1.5.25 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.5.26 Analog-to-digital converter (ADC) module. . . . .17

1.5.27 Cross triggering unit (CTU) . . . . . . . . . . . . . . . .17

1.5.28 Nexus Development Interface (NDI) . . . . . . . . .18

1.5.29 Cyclic redundancy check (CRC) . . . . . . . . . . . .18

1.5.30 IEEE 1149.1 JTAG controller. . . . . . . . . . . . . . .19

1.5.31 On-chip voltage regulator (VREG). . . . . . . . . . .19

Package pinouts and signal descriptions . . . . . . . . . . . . . . . .19

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.2.1 Power supply and reference voltage pins . . . . .21

2.2.2 System pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.2.3 Pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . .23

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

junction temperature . . . . . . . . . . . . . . . . . . . . 40

3.6 Electromagnetic interference (EMI) characteristics. . . 42

3.7 Electrostatic discharge (ESD) characteristics . . . . . . . 42

3.8 Power management electrical characteristics . . . . . . . 42

3.8.1 Voltage regulator electrical characteristics. . . . 42

3.8.2 Voltage monitor electrical characteristics . . . . . 44

3.9 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . 44

3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 47

3.10.1 NVUSRO register. . . . . . . . . . . . . . . . . . . . . . . 47

3.10.2 DC electrical characteristics (5 V) . . . . . . . . . . 47

3.10.3 DC electrical characteristics (3.3 V) . . . . . . . . . 50

3.10.4 Input DC electrical characteristics definition . . 51

3.10.5 I/O pad current specification. . . . . . . . . . . . . . . 52

3.11 Main oscillator electrical characteristics . . . . . . . . . . . 53

3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 54

3.13 16 MHz RC oscillator electrical characteristics . . . . . . 56

3.14 Analog-to-digital converter (ADC) electrical characteristics

56

3.14.1 Input impedance and ADC accuracy . . . . . . . . 57

3.14.2 ADC conversion characteristics . . . . . . . . . . . . 62

3.15 Flash memory electrical characteristics. . . . . . . . . . . . 63

3.15.1 Program/Erase characteristics. . . . . . . . . . . . . 63

3.15.2 Flash memory power supply DC characteristics64

3.15.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 65

3.16 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . 65

3.17 AC timing characteristics. . . . . . . . . . . . . . . . . . . . . . . 66

3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . . 66

3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 69

3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . . 73

3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 80

4.1.1 100 LQFP mechanical outline drawing . . . . . . 80

4.1.2 64 LQFP mechanical outline drawing . . . . . . . 84

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2

3

4

5

6

MPC5602P Microcontroller Data Sheet, Rev. 4.1

2

Freescale Semiconductor

1

Introduction

1.1

Document overview

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5601P/2P series of

microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical

characteristics. For functional characteristics, refer to the device reference manual.

1.2

Description

This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive

application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis

applications—specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as airbag

applications.

®

This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture

technology.

The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture

embedded category. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power

consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported

with software drivers, operating systems and configuration code to assist with users implementations.

1.3

Device comparison

Table 1 provides a summary of different members of the MPC5602P family and their features to enable a comparison among

the family members and an understanding of the range of functionality offered within this family.

Table 1. MPC5602P device comparison

Feature

MPC5601P

MPC5602P

Code flash memory (with ECC)

Data flash memory / EE option (with ECC)

SRAM (with ECC)

192 KB

256 KB

64 KB (optional feature)

12 KB

20 KB

Processor core

32-bit e200z0h

Instruction set

VLE (variable length encoding)

CPU performance

0–64 MHz

FMPLL (frequency-modulated phase-locked loop) module

INTC (interrupt controller) channels

PIT (periodic interrupt timer)

eDMA (enhanced direct memory access) channels

FlexCAN (controller area network)

Safety port

1

120

1 (with four 32-bit timers)

16

1^1,2

2^1,2

Yes (via FlexCAN module) Yes (via second FlexCAN

module)

FCU (fault collection unit)

CTU (cross triggering unit)

eTimer

Yes

No

Yes

1 (16-bit, 6 channels)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

3

Table 1. MPC5602P device comparison (continued)

Feature

MPC5601P

MPC5602P

FlexPWM (pulse-width modulation) channels

No

8

(capture capability not

supported)

Analog-to-digital converter (ADC)

LINFlex

1 (10-bit, 16 channels)

1

2

(1 × Master/Slave)

(1 × Master/Slave,

1 × Master only)

DSPI (deserial serial peripheral interface)

CRC (cyclic redundancy check) unit

Junction temperature sensor

JTAG controller

1

3

Yes

No

Yes

Nexus port controller (NPC)

Yes (Nexus L1+)

Supply

Digital power supply

Analog power supply

Internal RC oscillator

External crystal oscillator

3.3 V or 5 V single supply with external transistor

3.3 V or 5 V

16 MHz

4–40 MHz

Packages

64 LQFP

100 LQFP

Temperature

Standard ambient temperature

–40 to 125 °C

1

Each FlexCAN module has 32 message buffers.

2

One FlexCAN module can act as a safety port with a bit rate as high as 8 Mbit/s at 64 MHz.

1.4

Block diagram

Figure 1 shows a top-level block diagram of the MPC5602P MCU. Table 2 summarizes the functions of the blocks.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

4

Freescale Semiconductor

External ballast

1.2 V regulator

e200z0 Core

32-bit

general

purpose

registers

control

XOSC

Integer

execution

unit

Special

purpose

registers

Exception

handler

Interrupt

controller

16 MHz

RC oscillator

Variable

length

encoded

instructions

Instruction

unit

FMPLL_0

(System)

Branch

prediction

unit

Load/store

unit

JTAG

Nexus port

controller

Nexus 1

eDMA

16 channels

Data

32-bit

Instruction

32-bit

Master

Crossbar switch (XBAR, AMBA 2.0 v6 AHB)

Slave Slave

Slave

Code Flash Data Flash

(with ECC) (with ECC)

SRAM

(with ECC)

Peripheral bridge

Legend:

ADC

BAM

CRC

CTU

Analog-to-digital converter

Boot assist module

Cyclic redundancy check

Cross triggering unit

LINFlex

MC_ME

Serial communication interface (LIN support)

MC_CGM Clock generation module

Mode entry module

MC_PCU Power control unit

DSPI

ECSM

eDMA

eTimer

FCU

Deserial serial peripheral interface

Error correction status module

Enhanced direct memory access

Enhanced timer

Fault collection unit

Flash memory

MC_RGM Reset generation module

PIT

Periodic interrupt timer

System Integration unit Lite

Static random-access memory

System status and configuration module

System timer module

SIUL

SRAM

SSCM

STM

Flash

FlexCAN Controller area network

FlexPWM Flexible pulse width modulation

SWT

Software watchdog timer

Wakeup unit

External oscillator

WKPU

XOSC

XBAR

FMPLL

INTC

Frequency-modulated phase-locked loop

Interrupt controller

Crossbar switch

JTAG

JTAG controller

Figure 1. MPC5602P block diagram

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

5

Table 2. MPC5602P series block summary

Function

Block

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Boot assist module (BAM)

Block of read-only memory containing VLE code which is executed according to

the boot mode of the device

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Controller area network (FlexCAN) Supports the standard CAN communications protocol

Cross triggering unit (CTU)

Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Crossbar switch (XBAR)

Supports simultaneous connections between two master ports and three slave

ports; supports a 32-bit address bus width and a 32-bit data bus width

Cyclic redundancy check (CRC) CRC checksum generator

Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices

(DSPI)

Enhanced direct memory access Performs complex data transfers with minimal intervention from a host processor

(eDMA)

via “n” programmable channels

Enhanced timer (eTimer)

Provides enhanced programmable up/down modulo counting

Error correction status module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

External oscillator (XOSC)

Provides an output clock used as input reference for FMPLL_0 or as reference

clock for specific modules depending on system needs

Fault collection unit (FCU)

Flash memory

Provides functional safety to the device

Provides non-volatile storage for program code, constants and variables

Frequency-modulated

phase-locked loop (FMPLL)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC)

JTAG controller

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol) messages

efficiently with a minimum of CPU load

Mode entry module (MC_ME)

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control unit,

reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Periodic interrupt timer (PIT)

Peripheral bridge (PBRIDGE)

Power control unit (MC_PCU)

Produces periodic interrupts and triggers

Is the interface between the system bus and on-chip peripherals

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

MPC5602P Microcontroller Data Sheet, Rev. 4.1

6

Freescale Semiconductor

Table 2. MPC5602P series block summary (continued)

Function

Block

Pulse width modulator (FlexPWM) Contains four PWM submodules, each of which capable of controlling a single

half-bridge power stage and two fault input channels

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the device

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

System status and configuration Provides system configuration and status data (such as memory size and status,

module (SSCM)

device mode and security status), device identification data, debug status port

enable and selection, and bus and peripheral abort enable/disable

System timer module (STM)

Provides a set of output compare events to support AUTOSAR¹and operating

system tasks

System watchdog timer (SWT)

Wakeup unit (WKPU)

Provides protection from runaway code

Supports up to 18 external sources that can generate interrupts or wakeup

events, of which 1 can cause non-maskable interrupt requests or wakeup events

1

AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)

Feature details

1.5

1.5.1

High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

•

High performance e200z0 core processor for managing peripherals and interrupts

Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

Harvard architecture

Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions

— Results in smaller code size footprint

— Minimizes impact on performance

•

Branch processing acceleration using lookahead instruction buffer

Load/store unit

— 1-cycle load latency

— Misaligned access support

— No load-to-use pipeline bubbles

•

Thirty-two 32-bit general purpose registers (GPRs)

Separate instruction bus and load/store bus Harvard architecture

Hardware vectored interrupt support

Reservation instructions for implementing read-modify-write constructs

Long cycle time instructions, except for guarded loads, do not increase interrupt latency

Extensive system development support through Nexus debug port

Non-maskable interrupt support

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

7

1.5.2

Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and three slave ports. The

crossbar supports a 32-bit address bus width and a 32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers

must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master

port, arbitration logic will select the higher priority master and grant it ownership of the slave port. All other masters requesting

that slave port will be stalled until the higher priority master completes its transactions. Requesting masters will be treated with

equal priority and will be granted access a slave port in round-robin fashion, based upon the ID of the last master to be granted

access.

The crossbar provides the following features:

•

3 master ports:

— e200z0 core complex instruction port

— e200z0 core complex Load/Store Data port

— eDMA

•

3 slave ports:

— Flash memory (Code and Data)

— SRAM

— Peripheral bridge

•

32-bit internal address, 32-bit internal data paths

Fixed Priority Arbitration based on Port Master

Temporary dynamic priority elevation of masters

1.5.3

Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data

movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture

includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,

along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.

The eDMA module provides the following features:

•

16 channels support independent 8-, 16- or 32-bit single value or block transfers

Supports variable-sized queues and circular queues

Source and destination address registers are independently configured to either post-increment or to remain constant

Each transfer is initiated by a peripheral, CPU, or eDMA channel request

Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block

transfer

•

DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer and CTU

Programmable DMA channel multiplexer allows assignment of any DMA source to any available DMA channel with

as many as 30 request sources

•

eDMA abort operation through software

1.5.4

Flash memory

The MPC5602P provides 320 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used

for instruction and/or data storage. The flash memory module is interfaced to the system bus by a dedicated flash memory

controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The

module contains four 128-bit wide prefetch buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array

accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

8

Freescale Semiconductor

The flash memory module provides the following features:

•

As much as 320 KB flash memory

— 6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory

— 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory

— Full Read-While-Write (RWW) capability between code flash memory and data flash memory

•

Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to

prefetch code or data or both)

•

Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page buffer miss at 64 MHz

Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

Hardware and software configurable read and write access protections on a per-master basis

Configurable access timing allowing use in a wide range of system frequencies

Multiple-mapping support and mapping-based block access timing (up to 31 additional cycles) allowing use for

emulation of other memory types

•

Software programmable block program/erase restriction control

Erase of selected block(s)

Read page sizes

— Code flash memory: 128 bits (4 words)

— Data flash memory: 32 bits (1 word)

ECC with single-bit correction, double-bit detection for data integrity

— Code flash memory: 64-bit ECC

•

— Data flash memory: 32-bit ECC

•

Embedded hardware program and erase algorithm

Erase suspend and program abort

Censorship protection scheme to prevent flash memory content visibility

Hardware support for EEPROM emulation

1.5.5

Static random access memory (SRAM)

The MPC5602P SRAM module provides up to 20 KB of general-purpose memory.

ECC handling is done on a 32-bit boundary and is completely software compatible with MPC55xx family devices containing

an e200z6 core and 64-bit wide ECC.

The SRAM module provides the following features:

•

Supports read/write accesses mapped to the SRAM from any master

Up to 20 KB general purpose SRAM

Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory

Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if

back-to-back with a read to same memory block

1.5.6

Interrupt controller (INTC)

The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests, suitable for statically

scheduled hard real-time systems. The INTC handles 128 selectable-priority interrupt sources.

For high-priority interrupt requests, the time from the assertion of the interrupt request by the peripheral to the execution of the

interrupt service routine (ISR) by the processor has been minimized. The INTC provides a unique vector for each interrupt

request source for quick determination of which ISR has to be executed. It also provides a wide number of priorities so that

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

9

lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of

interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority

ceiling protocol (PCP) for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so

that all tasks which share the same resource can not preempt each other.

The INTC provides the following features:

•

Unique 9-bit vector for each separate interrupt source

8 software triggerable interrupt sources

16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

Ability to modify the ISR or task priority: modifying the priority can be used to implement the priority ceiling protocol

for accessing shared resources.

•

1 external high priority interrupt (NMI) directly accessing the main core and I/O processor (IOP) critical interrupt

mechanism

1.5.7

System status and configuration module (SSCM)

The system status and configuration module (SSCM) provides central device functionality.

The SSCM includes these features:

•

System configuration and status

— Memory sizes/status

— Device mode and security status

— Determine boot vector

— Search code flash for bootable sector

— DMA status

•

Debug status port enable and selection

Bus and peripheral abort enable/disable

1.5.8

System clocks and clock generation

The following list summarizes the system clock and clock generation on the MPC5602P:

•

Lock detect circuitry continuously monitors lock status

Loss of clock (LOC) detection for PLL outputs

Programmable output clock divider (1, 2, 4, 8)

FlexPWM module and eTimer module running at the same frequency as the e200z0h core

Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by user application

1.5.9

Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further, the FMPLL supports

programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all

software configurable.

The FMPLL has the following major features:

•

Input clock frequency: 4–40 MHz

Maximum output frequency: 64 MHz

Voltage controlled oscillator (VCO)—frequency 256–512 MHz

Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to relock

MPC5602P Microcontroller Data Sheet, Rev. 4.1

10

Freescale Semiconductor

•

Frequency-modulated PLL

— Modulation enabled/disabled through software

— Triangle wave modulation

•

Programmable modulation depth (±0.25% to ±4% deviation from center frequency): programmable modulation

frequency dependent on reference frequency

Self-clocked mode (SCM) operation

1.5.10 Main oscillator

The main oscillator provides these features:

•

Input frequency range: 4–40 MHz

Crystal input mode or oscillator input mode

PLL reference

1.5.11 Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a capacitor. The voltage

at the capacitor is compared by the stable bandgap reference voltage.

The RC oscillator provides these features:

•

Nominal frequency 16 MHz

±5% variation over voltage and temperature after process trim

Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the

PLL

•

RC oscillator is used as the default system clock during startup

1.5.12 Periodic interrupt timer (PIT)

The PIT module implements these features:

•

4 general-purpose interrupt timers

32-bit counter resolution

Clocked by system clock frequency

Each channel usable as trigger for a DMA request

1.5.13 System timer module (STM)

The STM implements these features:

•

One 32-bit up counter with 8-bit prescaler

Four 32-bit compare channels

Independent interrupt source for each channel

Counter can be stopped in debug mode

1.5.14 Software watchdog timer (SWT)

The SWT has the following features:

•

32-bit time-out register to set the time-out period

Programmable selection of window mode or regular servicing

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

11

•

Programmable selection of reset or interrupt on an initial time-out

Master access protection

Hard and soft configuration lock bits

Reset configuration inputs allow timer to be enabled out of reset

1.5.15 Fault collection unit (FCU)

The FCU provides an independent fault reporting mechanism even if the CPU is malfunctioning.

The FCU module has the following features:

•

FCU status register reporting the device status

Continuous monitoring of critical fault signals

User selection of critical signals from different fault sources inside the device

Critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device

and/or other circuitry (for example, a safety relay)

•

Faults are latched into a register

1.5.16 System integration unit – Lite (SIUL)

The MPC5602P SIUL controls MCU pad configuration, external interrupt, general purpose I/O (GPIO), and internal peripheral

multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and

discrete input/output control of the I/O pins of the MCU.

The SIUL provides the following features:

•

Centralized general purpose input output (GPIO) control of up to 49 input/output pins and 16 analog input-only pads

(package dependent)

•

All GPIO pins can be independently configured to support pull-up, pull-down, or no pull

Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

All peripheral pins, except ADC channels, can be alternatively configured as both general purpose input or output pins

ADC channels support alternative configuration as general purpose inputs

Direct readback of the pin value is supported on all pins through the SIUL

Configurable digital input filter that can be applied to some general purpose input pins for noise elimination

Up to 4 internal functions can be multiplexed onto 1 pin

1.5.17 Boot and censorship

Different booting modes are available in the MPC5602P: booting from internal flash memory and booting via a serial link.

The default booting scheme uses the internal flash memory (an internal pull-down resistor is used to select this mode).

Optionally, the user can boot via FlexCAN or LINFlex (using the boot assist module software).

A censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile memory.

1.5.17.1 Boot assist module (BAM)

The BAM is a block of read-only memory that is programmed once and is identical for all MPC560xP devices that are based

on the e200z0h core. The BAM program is executed every time the device is powered on if the alternate boot mode has been

selected by the user.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

12

Freescale Semiconductor

The BAM provides the following features:

•

Serial bootloading via FlexCAN or LINFlex

Ability to accept a password via the used serial communication channel to grant the legitimate user access to the

non-volatile memory

1.5.18 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform

configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,

and information on platform memory errors reported by error-correcting codes and/or generic access error information for

certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes

these features:

•

Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented

For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the

MPC5602P.

The sources of the ECC errors are:

•

Flash memory

SRAM

1.5.19 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

•

Duplicated periphery

Master access privilege level per peripheral (per master: read access enable; write access enable)

Write buffering for peripherals

Checker applied on PBRIDGE output toward periphery

Byte endianess swap capability

1.5.20 Controller area network (FlexCAN)

The MPC5602P MCU contains one controller area network (FlexCAN) module. This module is a communication controller

implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used

primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in

the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module contains 32 message

buffers.

The FlexCAN module provides the following features:

•

Full implementation of the CAN protocol specification, version 2.0B

— Standard data and remote frames

— Extended data and remote frames

— Up to 8-bytes data length

— Programmable bit rate up to 1 Mbit/s

•

32 message buffers of up to 8-bytes data length

Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

Programmable loop-back mode supporting self-test operation

3 programmable mask registers

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

13

•

Programmable transmit-first scheme: lowest ID or lowest buffer number

Time stamp based on 16-bit free-running timer

Global network time, synchronized by a specific message

Maskable interrupts

Independent of the transmission medium (an external transceiver is assumed)

High immunity to EMI

Short latency time due to an arbitration scheme for high-priority messages

Transmit features

— Supports configuration of multiple mailboxes to form message queues of scalable depth

— Arbitration scheme according to message ID or message buffer number

— Internal arbitration to guarantee no inner or outer priority inversion

— Transmit abort procedure and notification

Receive features

•

— Individual programmable filters for each mailbox

— 8 mailboxes configurable as a 6-entry receive FIFO

— 8 programmable acceptance filters for receive FIFO

Programmable clock source

— System clock

— Direct oscillator clock to avoid PLL jitter

1.5.21 Safety port (FlexCAN)

The MPC5602P MCU has a second CAN controller synthesized to run at high bit rates to be used as a safety port. The CAN

module of the safety port provides the following features:

•

Identical to the FlexCAN module

Bit rate up to 8 Mbit/s at 64 MHz CPU clock using direct connection between CAN modules (no physical transceiver

required)

•

32 message buffers of up to 8-bytes data length

Can be used as a second independent CAN module

1.5.22 Serial communication interface module (LINFlex)

The LINFlex (local interconnect network flexible) on the MPC5602P features the following:

•

Supports LIN Master mode (both instances), LIN Slave mode (only one instance) and UART mode

LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications

Handles LIN frame transmission and reception without CPU intervention

LIN features

— Autonomous LIN frame handling

— Message buffer to store Identifier and up to 8 data bytes

— Supports message length of up to 64 bytes

— Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing, checksum, and time-out)

— Classic or extended checksum calculation

— Configurable Break duration of up to 36-bit times

— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

— Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

— Interrupt-driven operation with 16 interrupt sources

MPC5602P Microcontroller Data Sheet, Rev. 4.1

14

Freescale Semiconductor

•

LIN slave mode features:

— Autonomous LIN header handling

— Autonomous LIN response handling

— Optional discarding of irrelevant LIN responses using ID filter

UART mode:

— Full-duplex operation

— Standard non return-to-zero (NRZ) mark/space format

— Data buffers with 4-byte receive, 4-byte transmit

— Configurable word length (8-bit or 9-bit words)

— Error detection and flagging

— Parity, Noise and Framing errors

— Interrupt-driven operation with four interrupt sources

— Separate transmitter and receiver CPU interrupt sources

— 16-bit programmable baud-rate modulus counter and 16-bit fractional

— 2 receiver wake-up methods

1.5.23 Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for communication between the

MPC5602P MCU and external devices.

The DSPI modules provide these features:

•

Full duplex, synchronous transfers

Master or slave operation

Programmable master bit rates

Programmable clock polarity and phase

End-of-transmission interrupt flag

Programmable transfer baud rate

Programmable data frames from 4 to 16 bits

Up to 8 chip select lines available:

— 8 on DSPI_0

— 4 each on DSPI_1 and DSPI_2

•

8 clock and transfer attributes registers

Chip select strobe available as alternate function on one of the chip select pins for deglitching

FIFOs for buffering up to 4 transfers on the transmit and receive side

Queueing operation possible through use of the I/O processor or eDMA

General purpose I/O functionality on pins when not used for SPI

1.5.24 Pulse width modulator (FlexPWM)

The pulse width modulator module (PWM) contains four PWM submodules each of which is set up to control a single

half-bridge power stage. There are also three fault channels.

This PWM is capable of controlling most motor types: AC induction motors (ACIM), permanent magnet AC motors (PMAC),

both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper

motors.

The FlexPWM block implements the following features:

•

16-bit resolution for center, edge-aligned, and asymmetrical PWMs

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

15

•

Clock frequency same as that used for e200z0h core

PWM outputs can operate as complementary pairs or independent channels

Can accept signed numbers for PWM generation

Independent control of both edges of each PWM output

Synchronization to external hardware or other PWM supported

Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

•

Multiple ADC trigger events can be generated per PWM cycle via hardware

Write protection for critical registers

Fault inputs can be assigned to control multiple PWM outputs

Programmable filters for fault inputs

Independently programmable PWM output polarity

Independent top and bottom deadtime insertion

Each complementary pair can operate with its own PWM frequency and deadtime values

Individual software-control for each PWM output

All outputs can be programmed to change simultaneously via a “Force Out” event

PWMX pin can optionally output a third PWM signal from each submodule

Channels not used for PWM generation can be used for buffered output compare functions

Channels not used for PWM generation can be used for input capture functions

Enhanced dual-edge capture functionality

eDMA support with automatic reload

2 fault inputs

Capture capability for PWMA, PWMB, and PWMX channels not supported

1.5.25 eTimer

The MPC5602P includes one eTimer module which provides six 16-bit general purpose up/down timer/counter units with the

following features:

•

Clock frequency same as that used for the e200z0h core

Individual channel capability

— Input capture trigger

— Output compare

— Double buffer (to capture rising edge and falling edge)

— Separate prescaler for each counter

— Selectable clock source

— 0–100% pulse measurement

— Rotation direction flag (quad decoder mode)

Maximum count rate

•

— External event counting: max. count rate = peripheral clock/2

— Internal clock counting: max. count rate = peripheral clock

Counters are:

— Cascadable

— Preloadable

•

Programmable count modulo

Quadrature decode capabilities

MPC5602P Microcontroller Data Sheet, Rev. 4.1

16

Freescale Semiconductor

•

Counters can share available input pins

Count once or repeatedly

Pins available as GPIO when timer functionality not in use

1.5.26 Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

•

1 on-chip analog-to-digital converter

— 10-bit AD resolution

— 1 sample and hold unit

— Conversion time, including sampling time, less than 1 µs (at full precision)

— Typical sampling time is 150 ns minimum (at full precision)

— DNL/INL ±1 LSB

— TUE < 1.5 LSB

— Single-ended input signal up to 3.3 V/5.0 V

— 3.3 V/5.0 V input reference voltage

— ADC and its reference can be supplied with a voltage independent from V

DDIO

— ADC supply can be equal or higher than V

DDIO

— ADC supply and ADC reference are not independent from each other (both internally bonded to same pad)

— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

Digital part:

•

16 input channels

4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in

the appropriate ADC result location

•

2 modes of operation: Motor Control mode or Regular mode

Regular mode features

— Register based interface with the CPU: control register, status register and 1 result register per channel

— ADC state machine managing 3 request flows: regular command, hardware injected command and software

injected command

— Selectable priority between software and hardware injected commands

— DMA compatible interface

•

CTU-controlled mode features

— Triggered mode only

— 4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)

— Result alignment circuitry (left justified and right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit part

— DMA compatible interfaces

1.5.27 Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU

load during the PWM period and with minimized CPU load for dynamic configuration.

It implements the following features:

•

Double buffered trigger generation unit with up to 8 independent triggers generated from external triggers

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

17

•

Trigger generation unit configurable in sequential mode or in triggered mode

Each trigger can be appropriately delayed to compensate the delay of external low pass filter

Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

Double buffered ADC command list pointers to minimize ADC-trigger unit update

Double buffered ADC conversion command list with up to 24 ADC commands

Each trigger capable of generating consecutive commands

ADC conversion command allows to control ADC channel, single or synchronous sampling, independent result queue

selection

1.5.28 Nexus Development Interface (NDI)

The NDI (Nexus Development Interface) block provides real-time development support capabilities for the MPC5602P Power

Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for

MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several

individual Nexus blocks that are selected to provide the development support interface for this device. The NDI block interfaces

to the host processor and internal busses to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard.

The development support provided includes access to the MCU’s internal memory map and access to the processor’s internal

registers during run time.

The NDI provides the following features:

•

Configured via the IEEE 1149.1

All Nexus port pins operate at V

Nexus 2+ features supported

— Static debug

(no dedicated power supply)

DDIO

— Watchpoint messaging

— Ownership trace messaging

— Program trace messaging

— Real time read/write of any internally memory mapped resources through JTAG pins

— Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of

information

— Watchpoint triggering, watchpoint triggers program tracing

Auxiliary Output Port

•

— 4 MDO (Message Data Out) pins

— MCKO (Message Clock Out) pin

— 2 MSEO (Message Start/End Out) pins

— EVTO (Event Out) pin

Auxiliary Input Port

— EVTI (Event In) pin

1.5.29 Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:

•

Support for CRC-16-CCITT (x25 protocol):

16

12

5

— x + x + x + 1

Support for CRC-32 (Ethernet protocol):

32

26

23

22

16

12

11

10

8

7

5

4

2

— x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency

MPC5602P Microcontroller Data Sheet, Rev. 4.1

18

Freescale Semiconductor

1.5.30 IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent

to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format.

The JTAGC block is compliant with the IEEE standard.

The JTAG controller provides the following features:

•

IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)

Selectable modes of operation include JTAGC/debug or normal system operation.

5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

— BYPASS

— IDCODE

— EXTEST

— SAMPLE

— SAMPLE/PRELOAD

•

5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC

— ACCESS_AUX_TAP_ONCE

3 test data registers:

— Bypass register

— Boundary scan register (size parameterized to support a variety of boundary scan chain lengths)

— Device identification register

•

TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

1.5.31 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

•

Uses external NPN (negative-positive-negative) transistor

Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic

Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

2

Package pinouts and signal descriptions

2.1

Package pinouts

The LQFP pinouts are shown in the following figures. For pin signal descriptions, please refer to Table 5.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

19

A[4]

NMI

A[6]

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VPP_TEST

D[14]]

2

A[7]

3

D[12]

D[13

VSS_LV_COR1

VDD_LV_COR1

A[3]

A[8]

A[5]

VDD_HV_IO1

VSS_HV_IO1

D[9]

4

5

6

7

8

64 LQFP

VDD_HV_IO2

VSS_HV_IO2

TDO

VDD_HV_OSC

VSS_HV_OSC

XTAL

9

10

11

12

13

14

15

16

TCK

EXTAL

TMS

RESET

TDI

D[8]

C[12]

VSS_LV_COR0

VDD_LV_COR0

C[11]

Figure 2. 64-pin LQFP pinout(top view)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

20

Freescale Semiconductor

75 A[4]

NMI

A[6]

1

74 VPP_TEST

73 D[14]

2

D[1]

3

72 C[14]

A[7]

4

71 C[13]

C[4]

5

70 D[12]

A[8]

6

69 N.C.

C[5]

7

68 N.C.

A[5]

8

67 D[13]

C[7]

9

66 VSS_LV_COR1

65 VDD_LV_COR1

64 A[3]

C[3]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

N.C.

63 VDD_HV_IO2

62 VSS_HV_IO2

61 TDO

VDD_HV_IO1

VSS_HV_IO1

D[9]

100 LQFP

60 TCK

VDD_HV_OSC

VSS_HV_OSC

XTAL

59 TMS

58 TDI

57 A[2]

EXTAL

RESET

D[8]

56 C[12]

55 C[11]

54 D[11]

D[5]

D[6]

VSS_LV_COR0

VDD_LV_COR0

53 D[10]

52 A[1]

51 A[0]

Figure 3. 100-pin LQFP pinout (top view)

2.2

Pin description

The following sections provide signal descriptions and related information about the functionality and configuration of the

MPC5602P devices.

2.2.1

Power supply and reference voltage pins

Table 3 lists the power supply and reference voltage for the MPC5602P devices.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

21

Table 3. Supply pins

Supply

Symbol

Description

64-pin 100-pin

VREG control and power supply pins. Pins available on 64-pin and 100-pin packages

BCTRL

Voltage regulator external NPN ballast base control pin

Voltage regulator supply voltage

31

32

47

50

V_{DD_HV_REG}

(3.3 V or 5.0 V)

ADC_0 reference and supply voltage. Pins available on 64-pin and 100-pin packages

1

V_{DD_HV_ADC0}

ADC_0 supply and high reference voltage

ADC_0 ground and low reference voltage

28

39

40

V_{SS_HV_ADC0}

29

Power supply pins (3.3 V or 5.0 V). Pins available on 64-pin and 100-pin packages

Input/output supply voltage

V_{DD_HV_IO1}

V_{SS_HV_IO1}

V_{DD_HV_IO2}

V_{SS_HV_IO2}

V_{DD_HV_IO3}

V_{SS_HV_IO3}

6

13

14

63

62

87

88

16

17

Input/output ground

7

Input/output supply voltage and data Flash memory supply voltage

Input/output ground and Flash memory HV ground

Input/output supply voltage and code Flash memory supply voltage

Input/output ground and code Flash memory HV ground

40

39

55

56

9

V_{DD_HV_OSC}

V_{SS_HV_OSC}

Crystal oscillator amplifier supply voltage

Crystal oscillator amplifier ground

10

Power supply pins (1.2 V). Pins available on 64-pin and 100-pin packages

V_{DD_LV_COR0}

V_{SS_LV_COR0}

V_{DD_LV_COR1}

V_{SS_LV_COR1}

V_{DD_LV_COR2}

V_{SS_LV_COR2}

1.2 V supply pins for core logic and PLL. Decoupling capacitor must be

connected between these pins and the nearest V_{SS_LV_COR}pin.

16

15

42

43

58

59

25

24

65

66

92

93

1.2 V supply pins for core logic and PLL. Decoupling capacitor must be

connected between these pins and the nearest V_{DD_LV_COR}pin.

1.2 V supply pins for core logic and data Flash. Decoupling capacitor

must be connected between these pins and the nearest V_{SS_LV_COR}pin.

1.2 V supply pins for core logic and data Flash. Decoupling capacitor

must be connected between these pins and the nearest V_{DD_LV_COR}pin.

1.2 V supply pins for core logic and code Flash. Decoupling capacitor

must be connected between these pins and the nearest V_{SS_LV_COR}pin.

1.2 V supply pins for core logic and code Flash. Decoupling capacitor

must be connected betwee.n these pins and the nearest V_{DD_LV_COR}pin.

1

Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a

double-bonding connection on V_{DD_HV_ADCx}/V_{SS_HV_ADCx}pins.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

22

Freescale Semiconductor

2.2.2

System pins

Table 4 and Table 5 contain information on pin functions for the MPC5602P devices. The pins listed in Table 4 are

single-function pins. The pins shown in Table 5 are multi-function pins, programmable via their respective pad configuration

register (PCR) values.

Table 4. System pins

Pad speed¹

Symbol

Description

Direction

SRC = 0 SRC = 1 64-pin 100-pin

Dedicated pins

NMI

Non-maskable Interrupt

Input only

—

Slow

—

1

XTAL

Analog output of the oscillator amplifier

circuit—needs to be grounded if oscillator is

used in bypass mode

11

18

EXTAL

Analog input of the oscillator amplifier circuit,

when the oscillator is not in bypass mode

Analog input for the clock generator when the

oscillator is in bypass mode

—

12

19

TDI

TMS

TCK

TDO

JTAG test data input

JTAG state machine control

JTAG clock

Input only

Output only

Slow

—

35

36

37

38

58

59

60

61

—

JTAG test data output

Fast

Reset pin

RESET

Bidirectional reset with Schmitt trigger

characteristics and noise filter

Bidirectional Medium

—

13

20

74

Test pin

VPP_TEST Pin for testing purpose only. To be tied to ground

in normal operating mode.

—

47

1

SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

2.2.3

Pin multiplexing

Table 5 defines the pin list and muxing for the MPC5602P devices.

Each row of Table 5 shows all the possible ways of configuring each pin, via alternate functions. The default function assigned

to each pin after reset is the ALT0 function.

MPC5602P devices provide three main I/O pad types, depending on the associated functions:

•

Slow pads are the most common, providing a compromise between transition time and low electromagnetic emission.

Medium pads provide fast enough transition for serial communication channels with controlled current to reduce

electromagnetic emission.

•

Fast pads provide maximum speed. They are used for improved NEXUS debugging capability.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.

For more information, see “Pad AC Specifications” in the device data sheet.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

23

Table 5. Pin muxing

Pad speed⁵

Port

PCR

Alternate

I/O

Functions

Peripheral³

pin register function^1,2

direction⁴

SRC = 0 SRC = 1 64-pin 100-pin

Port A (16-bit)

A[0]

A[1]

A[2]

PCR[0]

PCR[1]

PCR[2]

ALT0

ALT1

ALT2

ALT3

—

GPIO[0]

ETC[0]

SCK

F[0]

EIRQ[0]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

I/O

O

Slow

Medium

—

51

52

57

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[1]

ETC[1]

SOUT

F[1]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

I/O

O

I

EIRQ[1]

ALT0

ALT1

ALT2

ALT3

—

GPIO[2]

ETC[2]

—

A[3]

SIN

SIUL

eTimer_0

—

FlexPWM_0

DSPI_2

MC_RGM

SIUL

I/O

—

O

I

—

ABS[0]

EIRQ[2]

I

A[3]

A[4]

PCR[3]

PCR[4]

ALT0

ALT1

ALT2

ALT3

—

GPIO[3]

ETC[3]

CS0

B[3]

ABS[1]

EIRQ[3]

SIUL

eTimer_0

DSPI_2

FlexPWM_0

MC_RGM

SIUL

I/O

O

I

Slow

Medium

41

48

64

75

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[4]

—

CS1

ETC[4]

FAB

EIRQ[4]

SIUL

—

DSPI_2

eTimer_0

MC_RGM

SIUL

I/O

—

O

I/O

I

—

I

A[5]

A[6]

A[7]

PCR[5]

PCR[6]

PCR[7]

ALT0

ALT1

ALT2

ALT3

—

GPIO[5]

CS0

—

CS7

SIUL

DSPI_1

—

DSPI_0

SIUL

I/O

—

O

Slow

Medium

5

2

3

8

2

4

EIRQ[5]

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[6]

SCK

—

EIRQ[6]

SIUL

DSPI_1

—

SIUL

I/O

—

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[7]

SOUT

—

EIRQ[7]

SIUL

DSPI_1

—

SIUL

I/O

O

—

I

MPC5602P Microcontroller Data Sheet, Rev. 4.1

24

Freescale Semiconductor

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Port

PCR

Alternate

Functions

Peripheral³

pin register function^1,2

direction⁴

SRC = 0 SRC = 1 64-pin 100-pin

A[8]

A[9]

PCR[8]

ALT0

ALT1

ALT2

ALT3

—

GPIO[8]

—

SIN

EIRQ[8]

SIUL

—

DSPI_1

SIUL

I/O

—

I

Slow

Medium

4

6

—

I

PCR[9]

ALT0

ALT1

ALT2

ALT3

—

GPIO[9]

CS1

—

B[3]

SIUL

DSPI_2

I/O

O

—

O

I

Slow

Medium

60

52

53

54

61

94

81

82

83

95

—

FlexPWM_0

FAULT[0]

A[10] PCR[10]

A[11] PCR[11]

A[12] PCR[12]

A[13] PCR[13]

ALT0

ALT1

ALT2

ALT3

—

GPIO[10]

CS0

B[0]

X[2]

EIRQ[9]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

O

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[11]

SCK

A[0]

A[2]

EIRQ[10]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

O

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[12]

SOUT

A[2]

B[2]

EIRQ[11]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

O

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[13]

—

SIUL

—

FlexPWM_0

—

DSPI_2

FlexPWM_0

SIUL

I/O

—

O

—

I

B[2]

—

SIN

—

FAULT[0]

EIRQ[12]

I

A[14] PCR[14]

A[15] PCR[15]

ALT0

ALT1

ALT2

ALT3

—

GPIO[14]

TXD

SIUL

Safety Port_0

I/O

O

—

I

Slow

Medium

63

64

99

—

SIUL

EIRQ[13]

ALT0

ALT1

ALT2

ALT3

—

GPIO[15]

—

SIUL

—

I/O

—

I

100

—

RXD

EIRQ[14]

Safety Port_0

SIUL

—

I

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

25

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Port

PCR

Alternate

Functions

Peripheral³

pin register function^1,2

direction⁴

SRC = 0 SRC = 1 64-pin 100-pin

Port B (16-bit)

B[0] PCR[16]

B[1] PCR[17]

ALT0

ALT1

ALT2

ALT3

—

GPIO[16]

TXD

SIUL

FlexCAN_0

—

I/O

O

—

I

Slow

Medium

49

50

76

77

—

DEBUG[0]

EIRQ[15]

SSCM

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[17]

—

SIUL

—

I/O

—

I

—

DEBUG[1]

RXD

EIRQ[16]

SSCM

FlexCAN_0

SIUL

—

I

B[2] PCR[18]

B[3] PCR[19]

B[6] PCR[22]

B[7] PCR[23]

ALT0

ALT1

ALT2

ALT3

—

GPIO[18]

TXD

SIUL

LIN_0

—

SSCM

SIUL

I/O

O

—

I

Slow

—

Medium

—

51

—

62

20

79

80

96

29

—

DEBUG[2]

EIRQ[17]

ALT0

ALT1

ALT2

ALT3

—

GPIO[19]

—

SIUL

—

SSCM

LIN_0

I/O

—

I

—

DEBUG[3]

RXD

ALT0

ALT1

ALT2

ALT3

—

GPIO[22]

CLKOUT

CS2

SIUL

Control

DSPI_2

—

I/O

O

—

I

—

EIRQ[18]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[23]

—

AN[0]

RXD

SIUL

—

ADC_0

LIN_0

Input only

—

B[8] PCR[24]

ALT0

ALT1

ALT2

ALT3

—

GPIO[24]

—

AN[1]

ETC[5]

SIUL

—

22

24

31

35

—

ADC_0

eTimer_0

—

B[9] PCR[25]

ALT0

ALT1

ALT2

ALT3

—

GPIO[25]

—

AN[11]

SIUL

—

ADC_0

MPC5602P Microcontroller Data Sheet, Rev. 4.1

26

Freescale Semiconductor

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Port

PCR

Alternate

Functions

Peripheral³

pin register function^1,2

direction⁴

SRC = 0 SRC = 1 64-pin 100-pin

B[10] PCR[26]

B[11] PCR[27]

B[12] PCR[28]

B[13] PCR[29]

ALT0

ALT1

ALT2

ALT3

—

GPIO[26]

—

AN[12]

SIUL

—

ADC_0

Input only

—

25

26

27

30

36

37

38

42

ALT0

ALT1

ALT2

ALT3

—

GPIO[27]

—

AN[13]

SIUL

—

ADC_0

Input only

ALT0

ALT1

ALT2

ALT3

—

GPIO[28]

—

AN[14]

SIUL

—

ADC_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[29]

SIUL

—

ADC_0

—

AN[6]

—

emu. AN[0] emu. ADC_1⁶

—

RXD

LIN_1

B[14] PCR[30]

ALT0

ALT1

ALT2

ALT3

—

GPIO[30]

SIUL

—

ADC_0

Input only

—

44

—

AN[7]

—

emu. AN[1] emu. ADC_1⁶

—

ETC[4]

EIRQ[19]

eTimer_0

SIUL

B[15] PCR[31]

ALT0

ALT1

ALT2

ALT3

—

GPIO[31]

SIUL

—

ADC_0

Input only

—

43

—

AN[8]

—

emu. AN[2] emu. ADC_1⁶

—

EIRQ[20]

SIUL

Port C (16-bit)

C[0] PCR[32]

ALT0

ALT1

ALT2

ALT3

—

GPIO[32]

SIUL

—

ADC_0

Input only

—

45

—

AN[9]

—

emu. AN[3] emu. ADC_1⁶

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

27

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Port

PCR

Alternate

Functions

Peripheral³

pin register function^1,2

direction⁴

SRC = 0 SRC = 1 64-pin 100-pin

C[1] PCR[33]

C[2] PCR[34]

C[3] PCR[35]

C[4] PCR[36]

C[5] PCR[37]

C[6] PCR[38]

C[7] PCR[39]

ALT0

ALT1

ALT2

ALT3

—

GPIO[33]

SIUL

—

ADC_0

Input only

—

19

21

—

28

30

10

5

—

AN[2]

ALT0

ALT1

ALT2

ALT3

—

GPIO[34]

SIUL

—

ADC_0

Input only

—

AN[3]

ALT0

ALT1

ALT2

ALT3

—

GPIO[35]

CS1

—

TXD

SIUL

DSPI_0

—

LIN_1

SIUL

I/O

O

—

O

I

Slow

Medium

EIRQ[21]

ALT0

ALT1

ALT2

ALT3

—

GPIO[36]

CS0

X[1]

DEBUG[4]

EIRQ[22]

SIUL

DSPI_0

FlexPWM_0

SSCM

I/O

O

—

I

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[37]

SCK

SIUL

DSPI_0

—

SSCM

SIUL

I/O

—

I

7

—

DEBUG[5]

EIRQ[23]

ALT0

ALT1

ALT2

ALT3

—

GPIO[38]

SOUT

B[1]

DEBUG[6]

EIRQ[24]

SIUL

DSPI_0

FlexPWM_0

SSCM

I/O

O

—

I

98

9

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[39]

—

A[1]

DEBUG[7]

SIN

SIUL

—

FlexPWM_0

SSCM

I/O

—

O

—

I

DSPI_0

C[8] PCR[40]

C[9] PCR[41]

ALT0

ALT1

ALT2

ALT3

GPIO[40]

CS1

SIUL

DSPI_1

—

I/O

O

—

O

Slow

Medium

57

—

91

84

—

CS6

DSPI_0

ALT0

ALT1

ALT2

ALT3

GPIO[41]

CS3

SIUL

DSPI_2

—

I/O

O

—

O

—

X[3]

FlexPWM_0

MPC5602P Microcontroller Data Sheet, Rev. 4.1

28

Freescale Semiconductor

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Port

PCR

Alternate

Functions

Peripheral³

pin register function^1,2

direction⁴

SRC = 0 SRC = 1 64-pin 100-pin

C[10] PCR[42]

ALT0

ALT1

ALT2

ALT3

—

GPIO[42]

CS2

—

A[3]

FAULT[1]

SIUL

DSPI_2

I/O

O

—

O

I

Slow

Medium

—

78

—

FlexPWM_0

C[11] PCR[43]

C[12] PCR[44]

C[13] PCR[45]

ALT0

ALT1

ALT2

ALT3

GPIO[43]

ETC[4]

CS2

SIUL

eTimer_0

DSPI_2

—

I/O

O

Slow

Medium

33

34

—

55

56

71

—

ALT0

ALT1

ALT2

ALT3

GPIO[44]

ETC[5]

CS3

SIUL

eTimer_0

DSPI_2

—

I/O

O

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[45]

SIUL

—

CTU_0

I/O

—

I

—

EXT_IN

—

EXT_SYNC FlexPWM_0

I

C[14] PCR[46]

C[15] PCR[47]

ALT0

ALT1

ALT2

ALT3

GPIO[46]

—

EXT_TGR

—

SIUL

—

CTU_0

—

I/O

—

O

Slow

Medium

—

72

85

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[47]

—

A[1]

EXT_IN

SIUL

—

I/O

—

O

I

FlexPWM_0

CTU_0

—

EXT_SYNC FlexPWM_0

I

Port D (16-bit)

D[0] PCR[48]

D[1] PCR[49]

D[2] PCR[50]

D[3] PCR[51]

ALT0

ALT1

ALT2

ALT3

GPIO[48]

SIUL

—

I/O

—

O

Slow

Medium

—

86

3

—

B[1]

FlexPWM_0

ALT0

ALT1

ALT2

ALT3

GPIO[49]

—

SIUL

—

I/O

—

O

—

EXT_TRG

CTU_0

ALT0

ALT1

ALT2

ALT3

GPIO[50]

SIUL

—

I/O

—

O

97

89

—

X[3]

FlexPWM_0

ALT0

ALT1

ALT2

ALT3

GPIO[51]

SIUL

—

I/O

—

O

—

A[3]

FlexPWM_0

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

29

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Port

PCR

Alternate

Functions

Peripheral³

pin register function^1,2

direction⁴

SRC = 0 SRC = 1 64-pin 100-pin

D[4] PCR[52]

D[5] PCR[53]

D[6] PCR[54]

ALT0

ALT1

ALT2

ALT3

GPIO[52]

SIUL

—

I/O

—

O

Slow

Medium

—

90

22

23

—

B[3]

FlexPWM_0

ALT0

ALT1

ALT2

ALT3

GPIO[53]

CS3

SIUL

DSPI_0

FCU_0

—

I/O

O

F[0]

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[54]

CS2

SIUL

DSPI_0

—

I/O

O

—

I

—

FAULT[1]

FlexPWM_0

D[7] PCR[55]

D[8] PCR[56]

D[9] PCR[57]

D[10] PCR[58]

D[11] PCR[59]

D[12] PCR[60]

ALT0

ALT1

ALT2

ALT3

GPIO[55]

CS3

SIUL

I/O

O

Slow

Medium

17

14

8

26

21

15

53

54

70

DSPI_1

FCU_0

DSPI_0

F[1]

CS4

O

ALT0

ALT1

ALT2

ALT3

GPIO[56]

CS2

SIUL

DSPI_1

—

I/O

O

—

O

—

CS5

DSPI_0

ALT0

ALT1

ALT2

ALT3

GPIO[57]

X[0]

TXD

SIUL

FlexPWM_0

LIN_1

I/O

O

—

ALT0

ALT1

ALT2

ALT3

GPIO[58]

SIUL

FlexPWM_0

I/O

O

—

45

A[0]

—

ALT0

ALT1

ALT2

ALT3

GPIO[59]

SIUL

FlexPWM_0

I/O

O

—

B[0]

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[60]

X[1]

—

RXD

SIUL

FlexPWM_0

—

I/O

O

—

I

—

LIN_1

D[13] PCR[61]

D[14] PCR[62]

ALT0

ALT1

ALT2

ALT3

GPIO[61]

SIUL

FlexPWM_0

I/O

O

—

Slow

Medium

44

46

67

73

A[1]

—

ALT0

ALT1

ALT2

ALT3

GPIO[62]

SIUL

FlexPWM_0

I/O

O

—

B[1]

—

MPC5602P Microcontroller Data Sheet, Rev. 4.1

30

Freescale Semiconductor

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Port

PCR

Alternate

Functions

Peripheral³

pin register function^1,2

direction⁴

SRC = 0 SRC = 1 64-pin 100-pin

D[15] PCR[63]

ALT0

ALT1

ALT2

ALT3

—

GPIO[63]

—

SIUL

—

ADC_0

Input only

—

41

—

AN[10]

—

emu. AN[4] emu. ADC_1⁶

Port E (16-bit)

E[0] PCR[64]

E[1] PCR[65]

E[2] PCR[66]

E[3] PCR[67]

E[4] PCR[68]

E[5] PCR[69]

E[6] PCR[70]

E[7] PCR[71]

ALT0

ALT1

ALT2

ALT3

—

GPIO[64]

—

AN[15]

SIUL

—

ADC_0

Input only

—

18

23

30

—

46

27

32

42

44

43

45

41

ALT0

ALT1

ALT2

ALT3

—

GPIO[65]

SIUL

—

ADC_0

—

AN[4]

ALT0

ALT1

ALT2

ALT3

—

GPIO[66]

SIUL

—

ADC_0

—

AN[5]

ALT0

ALT1

ALT2

ALT3

—

GPIO[67]

SIUL

—

ADC_0

—

AN[6]

ALT0

ALT1

ALT2

ALT3

—

GPIO[68]

SIUL

—

ADC_0

—

AN[7]

ALT0

ALT1

ALT2

ALT3

—

GPIO[69]

SIUL

—

ADC_0

—

AN[8]

ALT0

ALT1

ALT2

ALT3

—

GPIO[70]

SIUL

—

ADC_0

—

AN[9]

ALT0

ALT1

ALT2

ALT3

—

GPIO[71]

—

AN[10]

SIUL

—

ADC_0

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

31

1

2

ALT0 is the primary (default) function for each port after reset.

Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module.

PCR.PA = 00  ALT0; PCR.PA = 01  ALT1; PCR.PA = 10  ALT2; PCR.PA = 11  ALT3. This is intended to

select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of

the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is

reported as “—”.

3

4

Module included on the MCU.

Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by

setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.

5

6

Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

ADC0.AN emulates ADC1.AN. This feature is used to provide software compatibility between MPC5602P and

MPC5604P. Refer to ADC chapter of reference manual for more details.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

32

Freescale Semiconductor

3

Electrical characteristics

3.1

Introduction

This section contains device electrical characteristics as well as temperature and power considerations.

This microcontroller contains input protection against damage due to high static voltages. However, it is advisable to take

precautions to avoid application of any voltage higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This can be done by the

DD

SS

internal pull-up or pull-down resistors, which are provided by the device for most general purpose pins.

The following tables provide the device characteristics and its demands on the system.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller

Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol

“SR” for System Requirement is included in the Symbol column.

CAUTION

All of the following parameter values can vary depending on the application and must be

confirmed during silicon characterization or silicon reliability trial.

3.2

Parameter classification

The electrical parameters are guaranteed by various methods. To give the customer a better understanding, the classifications

listed in Table 6 are used and the parameters are tagged accordingly in the tables where appropriate.

Table 6. Parameter classifications

Classification tag

Tag description

P

C

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

T

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical column

are within this category.

D

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

3.3

Absolute maximum ratings

1

Table 7. Absolute maximum ratings

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_SS

SR Device ground

—

0

V

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

33

1

Table 7. Absolute maximum ratings (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

2

V_{DD_HV_IOx}

SR 3.3 V/5.0 V input/output supply

voltage (supply).

—

–0.3

6.0

V

Code flash memory supply with

V_{DD_HV_IO3}and data flash memory

with V_{DD_HV_IO2}

V_{SS_HV_IOx}

SR 3.3 V/5.0 V input/output supply

voltage (ground).

—

–0.1

0.1

V

Code flash memory ground with

V_{SS_HV_IO3}and data flash memory

with V_{SS_HV_IO2}

V_{DD_HV_OSC}SR 3.3 V/5.0 V crystal oscillator amplifier

supply voltage (supply)

—

–0.3

6.0

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}+ 0.3

V_{SS_HV_OSC}SR 3.3 V/5.0 V crystal oscillator amplifier

supply voltage (ground)

—

–0.1

–0.3

–0.1

0.1

V

V_{DD_HV_ADC0}SR 3.3 V/5.0 V ADC_0 supply and high- V_{DD_HV_REG}

<

>

V_{DD_HV_REG}+ 0.3

reference voltage

2.7 V

V_{DD_HV_REG}

2.7 V

6.0

0.1

V_{SS_HV_ADC0}SR 3.3 V/5.0 V ADC_0 ground and low-

reference voltage

—

V

V_{DD_HV_REG}SR 3.3 V/5.0 V voltage-regulator supply

voltage

—

–0.3

6.0

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}+ 0.3

TV_DD

SR Slope characteristics on all V_DDduring

power up³

—

0.25

1.5

V/µs

V

V_{DD_LV_CORx}CC 1.2 V supply pins for core logic

(supply)

–0.1

V_{SS_LV_CORx}SR 1.2 V supply pins for core logic

(ground)

0.1

V

V_IN

SR Voltage on any pin with respect to

ground (V_{SS_HV_IOx}

–0.3

6.0

V

)

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}+ 0.3⁴

I_INJPAD

I_INJSUM

SR Input current on any pin during

overload condition

—

–10

–50

10

50

mA

SR Absolute sum of all input currents

during overload condition

—

T_STG

T_J

SR Storage temperature

—

–55

150

°C

SR Junction temperature under bias

40

MPC5602P Microcontroller Data Sheet, Rev. 4.1

34

Freescale Semiconductor

1

2

Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress

ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect

device reliability or cause permanent damage to the device.

The difference between each couple of voltage supplies must be less than 300 mV,

V_{DD_HV_IOy}– V_{DD_HV_IOx} < 300 mV.

Guaranteed by device validation.

Only when V_{DD_HV_IOx}< 5.2 V

3

4

Figure 4 shows the constraints of the different power supplies.

VDD_HV_xxx

6.0 V

VDD_HV_IOx

–0.3 V

6.0 V

Figure 4. Power supplies constraints (–0.3 V  V_{DD_HV_IOx} 6.0 V)

The MPC5602P supply architecture allows the ADC supply to be managed independently from the standard V

Figure 5 shows the constraints of the ADC power supply.

supply.

DD_HV

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

35

VDD_HV_ADCx

6.0 V

VDD_HV_REG

–0.3 V

2.7 V

6.0 V

Figure 5. Independent ADC supply (–0.3 V  V_{DD_HV_REG} 6.0 V)

3.4

Recommended operating conditions

Table 8. Recommended operating conditions (5.0 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max¹

V_SS

SR Device ground

—

0

V

2

V_{DD_HV_IOx}

SR 5.0 V input/output supply

voltage

4.5

5.5

V_{SS_HV_IOx}

SR Input/output ground

voltage

—

0

V

V_{DD_HV_OSC}

SR 5.0 V crystal oscillator

amplifier supply voltage

—

4.5

5.5

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

V_{SS_HV_OSC}

V_{DD_HV_REG}

SR 5.0 V crystal oscillator

amplifier reference voltage

—

0

V

SR 5.0 V voltage regulator

supply voltage

—

4.5

5.5

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

V_{DD_HV_ADC0}

SR 5.0 V ADC_0 supply and

high reference voltage

—

4.5

5.5

—

V

Relative to

V_{DD_HV_REG}– 0.1

V_{DD_HV_REG}

MPC5602P Microcontroller Data Sheet, Rev. 4.1

36

Freescale Semiconductor

Table 8. Recommended operating conditions (5.0 V) (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max¹

V_{SS_HV_ADC0}

SR ADC_0 ground and low

reference voltage

—

0

V

3,4

3

V_{DD_LV_REGCOR}

CC Internal supply voltage

SR Internal reference voltage

CC Internal supply voltage

SR Internal reference voltage

—

0

—

0

V

V_{SS_LV_REGCOR}

3,4

V_{DD_LV_CORx}

—

0

—

0

V

3

V_{SS_LV_CORx}

V

T_A

SR Ambient temperature

under bias

40

125

°C

1

2

3

Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, ADC electrical characteristics and

I/Os DC electrical specification may not be guaranteed.

The difference between each couple of voltage supplies must be less than 100 mV,

V_{DD_HV_IOy}– V_{DD_HV_IOx} < 100 mV.

To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced by an

on-chip voltage regulator—but for the device to function properly the low voltage grounds (V_{SS_LV_xxx}) must be shorted

to high voltage grounds (V_{SS_HV_xxx}) and the low voltage supply pins (V_{DD_LV_xxx}) must be connected to the external

ballast emitter.

4

The low voltage supplies (V_{DD_LV_xxx}) are not all independent.

– V_{DD_LV_COR1}and V_{DD_LV_COR2}are shorted internally via double bonding connections with lines that provide the low

voltage supply to the data flash memory module. Similarly, V_{SS_LV_COR1}and V_{SS_LV_COR2}are internally shorted.

– V_{DD_LV_REGCOR}and V_{DD_LV_RECORx}are physically shorted internally, as are V_{SS_LV_REGCOR}and V_{SS_LV_CORx}

.

Table 9. Recommended operating conditions (3.3 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max¹

V_SS

SR Device ground

—

0

V

2

V_{DD_HV_IOx}

SR 3.3 V input/output supply

voltage

3.0

3.6

V_{SS_HV_IOx}

SR Input/output ground

voltage

—

0

V

V_{DD_HV_OSC}

SR 3.3 V crystal oscillator

amplifier supply voltage

—

3.0

3.6

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

V_{SS_HV_OSC}

V_{DD_HV_REG}

SR 3.3 V crystal oscillator

amplifier reference voltage

—

0

V

SR 3.3 V voltage regulator

supply voltage

—

3.0

3.6

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

V_{DD_HV_ADC0}

SR 3.3 V ADC_0 supply and

high reference voltage

—

3.0

5.5

V

Relative to

V_{DD_HV_REG} 0.1

V_{DD_HV_REG}

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

37

Table 9. Recommended operating conditions (3.3 V) (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max¹

V_{SS_HV_ADC0}

SR ADC_0 ground and low

reference voltage

—

0

V

3,4

3

V_{DD_LV_REGCOR}

CC Internal supply voltage

—

0

—

0

V

V_{SS_LV_REGCOR}SR Internal reference voltage

3,4

V_{DD_LV_CORx}

V_{SS_LV_CORx}

T_A

CC Internal supply voltage

—

0

—

0

V

3

SR Internal reference voltage

V

SR Ambient temperature

under bias

40

125

°C

1

2

3

Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics

and I/Os DC electrical specification may not be guaranteed.

The difference between each couple of voltage supplies must be less than 100 mV,

V_{DD_HV_IOy}– V_{DD_HV_IOx} < 100 mV.

To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced

by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (V_{SS_LV_xxx}) must

be shorted to high voltage grounds (V_{SS_HV_xxx}) and the low voltage supply pins (V_{DD_LV_xxx}) must be connected

to the external ballast emitter.

4

The low voltage supplies (V_{DD_LV_xxx}) are not all independent.

– V_{DD_LV_COR1}and V_{DD_LV_COR2}are shorted internally via double bonding connections with lines that provide the

low voltage supply to the data flash memory module. Similarly, V_{SS_LV_COR1}and V_{SS_LV_COR2}are internally

shorted.

– V_{DD_LV_REGCOR}and V_{DD_LV_RECORx}are physically shorted internally, as are V_{SS_LV_REGCOR}and V_{SS_LV_CORx}

.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

38

Freescale Semiconductor

Figure 6 shows the constraints of the different power supplies.

VDD_HV_xxx

5.5 V

3.3 V

3.0 V

VDD_HV_IOx

5.5 V

3.0 V

3.3 V

Note: IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when

PAD3V5V is low, and in the range of 4.5–5.5 V when PAD3V5V is high.

Figure 6. Power supplies constraints (3.0 V  V_{DD_HV_IOx} 5.5 V)

The MPC5602P supply architecture allows the ADC supply to be managed independently from the standard V

Figure 7 shows the constraints of the ADC power supply.

supply.

DD_HV

VDD_HV_ADCx

5.5 V

3.0 V

VDD_HV_REG

3.0 V

5.5 V

Figure 7. Independent ADC supply (3.0 V  V_{DD_HV_REG} 5.5 V)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

39

3.5

Thermal characteristics

3.5.1

Package thermal characteristics

Table 10. LQFP thermal characteristics

Typical value

Symbol

Parameter

Conditions

Unit

100-pin

64-pin

R_JAThermal resistance junction-to-ambient, natural

convection¹

Single layer board—1s

Four layer board—2s2p

Single layer board—1s

Operating conditions

63

51

33

15

33

1

57

41

22

13

22

1

°C/W

R_JBThermal resistance junction-to-board²

R_JCtopThermal resistance junction-to-case (top)³

_JB

_JC

Junction-to-board, natural convection⁴

Junction-to-case, natural convection⁵

1

2

3

4

5

Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board meets JEDEC specification for

this package.

Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package. When Greek letters are not available, the symbols are typed as RthJB or Theta-JB.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used

for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the board and the junction temperature per

JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as

Psi-JC.

3.5.2

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T , can be obtained from Equation 1:

J

T = T + (R

* P )

Eqn. 1

J

A

JA

D

where:

T = ambient temperature for the package (°C)

A

R

= junction-to-ambient thermal resistance (°C/W)

JA

P = power dissipation in the package (W)

D

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal

performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value

obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which

value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a

single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low power dissipation and the components are well separated.

When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction-to-case thermal resistance

and a case-to-ambient thermal resistance:

R

= R

+ R

CA

Eqn. 2

JA

JC

MPC5602P Microcontroller Data Sheet, Rev. 4.1

40

Freescale Semiconductor

where:

R

= junction-to-ambient thermal resistance (°C/W)

= junction-to-case thermal resistance (°C/W)

= case-to-ambient thermal resistance (°C/W)

JA

JC

CA

R

is device related and cannot be influenced by the user. The user controls the thermal environment to change the

JC

case-to-ambient thermal resistance, R

. For instance, the user can change the size of the heat sink, the air flow around the

CA

device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the

printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal

Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at

JT

the top center of the package case using Equation 3:

T = T + ( x P )

Eqn. 3

J

T

JT

D

where:

T = thermocouple temperature on top of the package (°C)

T



= thermal characterization parameter (°C/W)

JT

P = power dissipation in the package (W)

D

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied

to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the

junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects

of the thermocouple wire.

References:

•

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134U.S.A.

(408) 943-6900

•

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at (800)

854-7179 or (303) 397-7956.

•

JEDEC specifications are available on the WEB at http://www.jedec.org.

C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller

Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

•

G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic

Packaging and Production, pp. 53–58, March 1998.

B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in

Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

41

3.6

Electromagnetic interference (EMI) characteristics

Table 11. EMI testing specifications

Level

(Typ)

Symbol

Parameter

Conditions

Clocks

Frequency

Unit

V_EMERadiated emissions V_DD= 5.0 V; T_A= 25 °C

Other device configuration,

f_OSC= 8 MHz

150 kHz–150 MHz 11 dBµV

f

_CPU= 64 MHz

150–1000 MHz

IEC level

13

M

8

No PLL frequency

test conditions and EM testing modulation

per standard IEC61967-2

—

f_OSC= 8 MHz

150 kHz–150 MHz

150–1000 MHz

IEC level

dBµV

f

_CPU= 64 MHz

12

N

±4% PLL frequency

modulation

—

V_DD= 3.3 V; T_A= 25 °C

f_OSC= 8 MHz

150 kHz–150 MHz

150–1000 MHz

IEC level

9

dBµV

f

_CPU= 64 MHz

12

M

7

Other device configuration,

test conditions and EM testing modulation

per standard IEC61967-2

No PLL frequency

—

f_OSC= 8 MHz

150 kHz–150 MHz

150–1000 MHz

IEC level

dBµV

f_CPU= 64 MHz

±4% PLL frequency

modulation

12

N

—

3.7

Electrostatic discharge (ESD) characteristics

1,2

Table 12. ESD ratings

Symbol

Parameter

Conditions

Value

Unit

V_ESD(HBM)

V_ESD(CDM)

SR Electrostatic discharge (Human Body Model)

SR Electrostatic discharge (Charged Device Model)

—

2000

V

750 (corners)

500 (other)

1

2

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

3.8

Power management electrical characteristics

Voltage regulator electrical characteristics

3.8.1

The internal voltage regulator requires an external NPN (BCP68, BCX68 or BC817) ballast to be connected as shown in

Figure 8. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to

limit the serial inductance of the board to less than 5 nH.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

42

Freescale Semiconductor

NOTE

The voltage regulator output cannot be used to drive external circuits. Output pins are to be

used only for decoupling capacitance.

V

must be generated using internal regulator and external NPN transistor. It is

DD_LV_COR

not possible to provide V

through external regulator.

DD_LV_COR

For the MPC5602P microcontroller, 10 µF should be placed between each of the three V

/V

supply pairs

DD_LV_CORx SS_LV_CORx

and also between the V

/V

pair. Additionally, 40 µF should be placed between the

DD_LV_REGCOR SS_LV_REGCOR

V

/V

pins.

DD_HV_REG SS_HV_REG

V

= 3.0 V to 3.6 V / 4.5 V to 5.5 V, T = –40 to 125 °C, unless otherwise specified.

DD

A

VDD_HV_REG

MPC5602P

C_DEC3

BCP68,

BCX68,

BC817

BCTRL

VDD_LV_COR

C_DEC2

C_DEC1

Figure 8. Voltage regulator configuration

Table 13. Voltage regulator electrical characteristics

Value

Min Typ Max

Symbol

C

Parameter

Conditions

Unit

V_{DD_LV_REGCOR}CC P Output voltage under maximum Post-trimming

1.15

—

1.32

V

load run supply current

configuration

C_DEC1

SR — External decoupling/stability

ceramic capacitor

Bipolar BCP68 or BCX68 or

BC817SU

Three capacitances of 10 µF

19.5

30

—

µF

Bipolar BC817

One capacitance of 22 µF

14.3

—

22

—

R_REG

SR — Resulting ESR of either one or Absolute maximum value

all three C_DEC1between 100 kHz and 10 MHz

45 m

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

43

Table 13. Voltage regulator electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions

Unit

Min Typ Max

C_DEC2

C_DEC3

SR — External decoupling/stability

ceramic capacitor

Four capacitances of 440 nF 1200 1760

each

—

nF

µF

SR — External decoupling/stability

ceramic capacitor on

Two capacitances of 10 µF

each

2 × 10

—

VDD_HV_REG

3.8.2

Voltage monitor electrical characteristics

The device implements a power on reset module to ensure correct power-up initialization, as well as three low voltage detectors

to monitor the V and the V voltage while device is supplied:

DD

DD_LV

•

POR monitors V during the power-up phase to ensure device is maintained in a safe reset state

DD

LVDHV3 monitors V to ensure device reset below minimum functional supply

DD

LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range

DD

LVDLVCOR monitors low voltage digital power domain

Table 14. Low voltage monitor electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

V_PORH

T

P

Power-on reset threshold

—

1.5

1.0

—

2.7

—

V

V_PORUP

Supply for functional POR module

T_A= 25 °C

V_{REGLVDMOK_H}

V_{REGLVDMOK_L}

V_{FLLVDMOK_H}

V_{FLLVDMOK_L}

V_{IOLVDMOK_H}

V_{IOLVDMOK_L}

V_{IOLVDM5OK_H}

V_{IOLVDM5OK_L}

V_{MLVDDOK_H}

V_{MLVDDOK_L}

Regulator low voltage detector high threshold

Regulator low voltage detector low threshold

Flash low voltage detector high threshold

Flash low voltage detector low threshold

I/O low voltage detector high threshold

I/O low voltage detector low threshold

I/O 5 V low voltage detector high threshold

I/O 5 V low voltage detector low threshold

Digital supply low voltage detector high

Digital supply low voltage detector low

—

2.95

—

2.6

—

2.95

—

2.6

—

2.95

—

2.6

—

4.4

—

3.8

—

1.145

—

1.08

1

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= 40 °C to T_{A MAX}, unless otherwise specified

3.9

Power up/down sequencing

To prevent an overstress event or a malfunction within and outside the device, the MPC5602P implements the following

sequence to ensure each module is started only when all conditions for switching it ON are available:

•

A POWER_ON module working on voltage regulator supply controls the correct start-up of the regulator. This is a

key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5 V. Associated

POWER_ON (or POR) signal is active low.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

44

Freescale Semiconductor

•

Several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage

regulator, I/Os, flash memory and low voltage domain). LVDs are gated low when POWER_ON is active.

A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active

high and released to all modules including I/Os, flash memory and 16 MHz RC oscillator needed during power-up

phase and reset phase. When POWER_OK is low the associated modules are set into a safe state.

V_LVDHV3H

V_PORH

3.3V

VDD_HV_REG

V_{POR_UP}

0V

3.3V

POWER_ON

LVDM (HV)

0V

3.3V

0V

V_{MLVDOK_H}

VDD_LV_REGCOR

1.2V

0V

3.3V

LVDD (LV)

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

~1us

1.2V

0V

Internal Reset Generation Module

FSM

P0

P1

Figure 9. Power-up typical sequence

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

45

V_LVDHV3L

3.3V

V_PORH

VDD_HV_REG

0V

3.3V

LVDM (HV)

POWER_ON

0V

3.3V

0V

1.2V

0V

VDD_LV_REGCOR

LVDD (LV)

3.3V

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

Internal Reset Generation Module

FSM

1.2V

0V

IDLE

P0

Figure 10. Power-down typical sequence

V_LVDHV3H

V_LVDHV3L

3.3V

VDD_HV_REG

0V

3.3V

LVDM (HV)

POWER_ON

0V

3.3V

0V

1.2V

0V

VDD_LV_REGCOR

LVDD (LV)

3.3V

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

~1us

Internal Reset Generation Module

1.2V

0V

FSM

IDLE

P0

P1

Figure 11. Brown-out typical sequence

MPC5602P Microcontroller Data Sheet, Rev. 4.1

46

Freescale Semiconductor

3.10 DC electrical characteristics

3.10.1 NVUSRO register

Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are

controlled via bit values in the non-volatile user options (NVUSRO) register.

For a detailed description of the NVUSRO register, please refer to the device reference manual.

3.10.1.1 NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 15 shows how NVUSRO[PAD3V5V]

controls the device configuration.

Table 15. PAD3V5V field description

Value¹

Description

0

1

High voltage supply is 5.0 V

High voltage supply is 3.3 V

1

Default manufacturing value before flash initialization is ‘1’ (3.3 V).

3.10.1.2 NVUSRO[OSCILLATOR_MARGIN] field description

The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 16 shows how

NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.

Table 16. OSCILLATOR_MARGIN field description

Value¹

Description

0

1

Low consumption configuration (4 MHz/8 MHz)

High margin configuration (4 MHz/16 MHz)

1

Default manufacturing value before flash initialization is ‘1’.

3.10.2 DC electrical characteristics (5 V)

Table 17 gives the DC electrical characteristics at 5 V (4.5 V < V

< 5.5 V, NVUSRO[PAD3V5V] = 0).

DD_HV_IOx

Table 17. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)

Value

Symbol

C

Parameter

Conditions

Unit

Min

Max

V_IL

D

P

D

T

Low level input voltage

—

0.4¹

—

0.35 V_{DD_HV_IOx}

—

V

—

V_IH

High level input voltage

—

0.65 V_{DD_HV_IOx}

—

0.1 V_{DD_HV_IOx}

—

V_{DD_HV_IOx}+ 0.4¹

V_HYS

Schmitt trigger hysteresis

—

V_{OL_S}

P

Slow, low level output voltage

I_OL= 3 mA

0.1 V_{DD_HV_IOx}

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

47

Table 17. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) (continued)

Value

Symbol

C

Parameter

Conditions

Unit

Min

Max

V_{OH_S}

V_{OL_M}

V_{OH_M}

V_{OL_F}

V_{OH_F}

I_PU

P

Slow, high level output voltage

Medium, low level output voltage

Medium, high level output voltage

Fast, low level output voltage

Fast, high level output voltage

Equivalent pull-up current

I_OH= 3 mA

I_OL= 3 mA

I_OH= 3 mA

I_OL= 14 mA

I_OH= 14 mA

V_IN= V_IL

0.8 V_{DD_HV_IOx}

—

V

—

0.1 V_{DD_HV_IOx}

0.8 V_{DD_HV_IOx}

—

V

—

0.1 V_{DD_HV_IOx}

V

0.8 V_{DD_HV_IOx}

—

V

130

—

µA

V_IN= V_IH

10

—

I_PD

P

Equivalent pull-down current

V_IN= V_IL

10

µA

V_IN= V_IH

—

130

1

I_IL

P

D

Input leakage current

(all bidirectional ports)

T_A= 40 to 125 °C

1

µA

pF

Input leakage current

(all ADC input-only ports)

T_A= 40 to 125 °C

0.5

0.5

10

C_IN

Input capacitance

—

1

“SR” parameter values must not exceed the absolute maximum ratings shown in Table 7.

Table 18. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)

Value¹

Symbol

C

Parameter

Conditions

Unit

Typ Max

I_{DD_LV_CORx}

T

P

T

RUN—Maximum mode²

V_{DD_LV_CORx}externally

forced at 1.3 V

40 MHz

64 MHz

40 MHz

64 MHz

—

44

52

38

45

1.5

1

55

65

46

54

10

19

mA

RUN—Typical mode³

P

T

HALT mode⁴

STOP mode⁵

—

I_{DD_FLASH}

Flash during read

V_{DD_HV_FL}at 5.0 V

—

8

Flash during erase operation V_{DD_HV_FL}at 5.0 V

on 1 flash module

—

15

I_{DD_ADC}

I_{DD_OSC}

T

ADC

V_{DD_HV_ADC0}at 5.0 V

f_ADC= 16 MHz

ADC_0

8 MHz

3

4

Oscillator

V_{DD_HV_OSC}at 5.0 V

2.6

3.2

1

2

All values to be confirmed after characterization/data collection.

Maximum mode: FlexPWM, ADC, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0 enabled, 125 °C ambient.

I/O supply current excluded.

3

Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0, 105 °C ambient. I/O supply current

excluded.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

48

Freescale Semiconductor

4

5

Halt mode configurations: Code fetched from SRAM, code flash memory and data flash memory in low power

mode, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.

STOP “P” mode Device Under Test (DUT) configuration: Code fetched from SRAM, code flash memory and data

flash memory off, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

49

3.10.3 DC electrical characteristics (3.3 V)

Table 19 gives the DC electrical characteristics at 3.3 V (3.0 V < V

Figure 12.

< 3.6 V, NVUSRO[PAD3V5V] = 1); see

DD_HV_IOx

1

Table 19. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)

Value

Symbol C

Parameter

Conditions

Unit

Min

Max

V_IL

V_IH

D Low level input voltage

—

0.4²

—

V

P

—

0.35 V_{DD_HV_IOx}

P High level input voltage

D

—

0.65 V_{DD_HV_IOx}

—

V

—

V_{DD_HV_IOx}+ 0.4²

V

V_HYST Schmitt trigger hysteresis

—

0.1 V_{DD_HV_IOx}

—

0.5

—

V

V_{OL_S}P Slow, low level output voltage

V_{OH_S}P Slow, high level output voltage

V_{OL_M}P Medium, low level output voltage

V_{OH_M}P Medium, high level output voltage

V_{OL_F}P Fast, low level output voltage

V_{OH_F}P Fast, high level output voltage

I_OL= 1.5 mA

I_OH= 1.5 mA

I_OL= 2 mA

I_OH= 2 mA

I_OL= 11 mA

I_OH= 11 mA

V_IN= V_IL

V_IN= V_IH

V_IN= V_IL

V_IN= V_IH

T_A= 40 to 125 °C

—

V

V_{DD_HV_IOx} 0.8

V

—

0.5

—

V

V_{DD_HV_IOx} 0.8

V

—

0.5

—

V

V_{DD_HV_IOx} 0.8

V

I_PU

P Equivalent pull-up current

130

—

µA

10

—

I_PD

P Equivalent pull-down current

10

µA

—

130

1

I_IL

P Input leakage current (all

bidirectional ports)

—

µA

pF

P Input leakage current (all ADC

input-only ports)

T_A= 40 to 125 °C

—

0.5

10

C_IN

D Input capacitance

—

1

2

These specifications are design targets and subject to change per device characterization.

“SR” parameter values must not exceed the absolute maximum ratings shown in Table 7.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

50

Freescale Semiconductor

Table 20. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)

Value¹

Symbol

C

Parameter

Conditions

Unit

Typ

Max

I_{DD_LV_CORx}

T

RUN—Maximum mode²

V_{DD_LV_CORx}externally

forced at 1.3 V

40 MHz

64 MHz

40 MHz

64 MHz

—

44

52

38

45

1.5

1

55

65

46

54

10

4

mA

RUN—Typical mode³

P

HALT mode⁴

STOP mode⁵

ADC

—

I_{DD_ADC}

I_{DD_OSC}

T

V_{DD_HV_ADC0}at 3.3 V

f_ADC= 16 MHz

ADC_0

3

Oscillator

V_{DD_HV_OSC}at 3.3 V

8 MHz

2.6

3.2

1

2

All values to be confirmed after characterization/data collection.

Maximum mode: FlexPWM, ADC, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0 enabled, 125 °C ambient.

I/O supply current excluded.

3

4

5

Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, PLL_0, 105 °C ambient. I/O supply current

excluded.

Halt mode configurations: Code fetched from SRAM, code flash memory and data flash memory in low power

mode, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.

STOP “P” mode Device Under Test (DUT) configuration: Code fetched from SRAM, code flash memory and data

flash memory off, OSC/PLL_0 are OFF, core clock frozen, all peripherals disabled.

3.10.4 Input DC electrical characteristics definition

Figure 12 shows the DC electrical characteristics behavior as function of time.

Figure 12. Input DC electrical characteristics definition

V

IN

V

DD

V

IH

V

HYS

V

IL

PDIx = ‘1’

(GPDI register of SIUL)

PDIx = ‘0’

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

51

3.10.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as

DD SS

described in Table 21.

Table 21. I/O supply segment

Supply segment

Package

1

2

3

4

5

100 LQFP

64 LQFP

pin15–pin26

pin8–pin17

pin27–pin46

pin18–pin30

pin51–pin61

pin33–pin38

pin64–pin86

pin41–pin54

pin89–pin10

pin57–pin5

Table 22. I/O consumption

Conditions¹

Value

Min Typ Max

Symbol

C

Parameter

Unit

,2

I_SWTSLW

CC D Dynamic I/O current C_L= 25 pF

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

—

20

16

29

17

mA

for SLOW

configuration

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

(2)

I_SWTMED

CC D Dynamic I/O current C_L= 25 pF

for MEDIUM

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

mA

configuration

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

(2)

I_SWTFST

CC D Dynamic I/O current C_L= 25 pF

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

110 mA

50

for FAST

configuration

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

I_RMSSLW

CC D Root medium square C_L= 25 pF, 2 MHz

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

—

2.3 mA

3.2

I/O current for SLOW

C_L= 25 pF, 4 MHz

configuration

C_L= 100 pF, 2 MHz

C_L= 25 pF, 2 MHz

C_L= 25 pF, 4 MHz

C_L= 100 pF, 2 MHz

6.6

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

1.6

2.3

4.7

I_RMSMEDCC D Root medium square C_L= 25 pF, 13 MHz V_DD= 5.0 V ± 10%,

6.6 mA

13.4

18.3

5

I/O current for

MEDIUM

configuration

PAD3V5V = 0

C_L= 25 pF, 40 MHz

C_L= 100 pF, 13 MHz

C_L= 25 pF, 13 MHz V_DD= 3.3 V ± 10%,

PAD3V5V = 1

C_L= 25 pF, 40 MHz

8.5

C_L= 100 pF, 13 MHz

11

MPC5602P Microcontroller Data Sheet, Rev. 4.1

52

Freescale Semiconductor

Table 22. I/O consumption (continued)

Conditions¹

Value

Symbol

C

Parameter

Unit

Min Typ Max

I_RMSFST

CC D Root medium square C_L= 25 pF, 40 MHz V_DD= 5.0 V ± 10%,

—

22

33

56

14

20

35

70

65

mA

I/O current for FAST

configuration

PAD3V5V = 0

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

C_L= 25 pF, 40 MHz V_DD= 3.3 V ± 10%,

PAD3V5V = 1

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

I_AVGSEG

SR D Sum of all the static

I/O current within a

supply segment

V

_DD= 5.0 V ± 10%, PAD3V5V = 0

_DD= 3.3 V ± 10%, PAD3V5V = 1

mA

V

1

2

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= –40 to 125 °C, unless otherwise specified

Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

3.11 Main oscillator electrical characteristics

The MPC5602P provides an oscillator/resonator driver.

Table 23. Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)

Value

Symbol

C

Parameter

Conditions

Unit

Min

Max

f_OSCSR — Oscillator frequency

4

6.5

1

40

25

—

30

26

23

19

16

8

MHz

mA/V

V

g_m

V_OSC

t_OSCSU

C_L

—

P Transconductance

T Oscillation amplitude on XTAL pin

T Start-up time^1,2

8

ms

CC T XTAL load capacitance³

4 MHz

5

pf

T

8 MHz

5

12 MHz

16 MHz

20 MHz

40 MHz

5

1

The start-up time is dependent upon crystal characteristics, board leakage, etc. High ESR and

excessive capacitive loads can cause long start-up time.

2

3

Value captured when amplitude reaches 90% of XTAL

This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals

specified for this oscillator, load capacitors should not exceed these limits.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

53

Table 24. Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)

Value

Symbol

C

Parameter

Conditions

Unit

Min

Max

f_OSCSR — Oscillator frequency

4

1

8

5

40

20

—

30

26

23

19

16

8

MHz

mA/V

V

g_m

V_OSC

t_OSCSU

C_L

—

P Transconductance

T Oscillation amplitude on XTAL pin

T Start-up time^1,2

ms

CC T XTAL load capacitance³

4 MHz

pf

T

8 MHz

12 MHz

16 MHz

20 MHz

40 MHz

1

The start-up time is dependent upon crystal characteristics, board leakage, etc. High ESR and

excessive capacitive loads can cause long start-up time.

2

3

Value captured when amplitude reaches 90% of XTAL

This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals

specified for this oscillator, load capacitors should not exceed these limits.

Table 25. Input clock characteristics

Value

Symbol

Parameter

Unit

Min

Typ

Max

f_OSC

f_CLK

t_rCLK

t_DC

SR Oscillator frequency

4

—

50

40

64

MHz

ns

SR Frequency in bypass

SR Rise/fall time in bypass

SR Duty cycle

—

1

47.5

52.5

%

3.12 FMPLL electrical characteristics

Table 26. FMPLL electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

f_{ref_crystal}

f_{ref_ext}

D

PLL reference frequency range²

Crystal reference

4

40

16

MHz

f_PLLIN

Phase detector input frequency range

(after pre-divider)

—

4

f_FMPLLOUT

f_FREE

D

P

Clock frequency range in normal mode

Free-running frequency

—

16

20

64

MHz

Measured using clock

division—typically /16

150

MPC5602P Microcontroller Data Sheet, Rev. 4.1

54

Freescale Semiconductor

Table 26. FMPLL electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

t_CYC

f_LORL

f_LORH

f_SCM

D

T

System clock period

—

1.6

24

20

4

—

1 / f_SYS

3.7

56

ns

Loss of reference frequency window³

Lower limit

Upper limit

MHz

Self-clocked mode frequency^4,5

—

150

4

MHz

% f_CLKOUT

ns

C_JITTER

CLKOUT period Short-term jitter¹⁰

f_SYSmaximum

_PLLIN= 16 MHz

jitter^6,7,8,9

Long-term jitter

f

10

(average over 2 ms

interval)

(resonator), f_PLLCLKat

64 MHz, 4000 cycles

t_lpll

t_dc

f_LCK

f_UL

D

PLL lock time^{11, 12}

—

40

200

60

6

µs

Duty cycle of reference

Frequency LOCK range

Frequency un-LOCK range

Modulation depth

—

%

—

6

% f_SYS

18

18

f_CS

Center spread

Down spread

—

±0.25 ±4.0¹³

f_DS

0.5

8.0

f_MOD

Modulation frequency¹⁴

—

70

kHz

1

2

3

V_{DD_LV_CORx}= 1.2 V ±10%; V_SS= 0 V; T_A= –40 to 125 °C, unless otherwise specified

Considering operation with PLL not bypassed.

“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked

mode.

4

5

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside

the f_LORwindow.

f_VCOself clock range is 20–150 MHz. f_SCMrepresents f_SYSafter PLL output divider (ERFD) of 2 through 16 in

enhanced mode.

6

7

This value is determined by the crystal manufacturer and board design.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum

f_SYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock

signal. Noise injected into the PLL circuitry via V_{DD_LV_COR0}and V_{SS_LV_COR0}and variation in crystal oscillator

frequency increase the C_JITTERpercentage for a given interval.

8

9

Proper PC board layout procedures must be followed to achieve specifications.

Values are obtained with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of

C_JITTERand either f_CSor f_DS(depending on whether center spread or down spread modulation is enabled).

¹⁰Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.

¹¹This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for

this PLL, load capacitors should not exceed these limits.

¹²This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits

in the synthesizer control register (SYNCR).

¹³This value is true when operating at frequencies above 60 MHz, otherwise f_CSis 2% (above 64 MHz).

¹⁴Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

55

3.13 16 MHz RC oscillator electrical characteristics

Table 27. 16 MHz RC oscillator electrical characteristics

Value

Typ

Symbol

C

Parameter

Conditions

Unit

Min

Max

f_RC

P RC oscillator frequency

T_A= 25 °C

—

16

—

5

MHz

%

_RCMVARP Fast internal RC oscillator variation over

temperature and supply with respect to f_RCat

T_A= 25 °C in high-frequency configuration

5

3.14 Analog-to-digital converter (ADC) electrical characteristics

The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

56

Freescale Semiconductor

Offset Error (E )

Gain Error (E )

G

O

1023

1022

1021

1020

1019

1 LSB ideal = V

/ 1024

DD_ADC

1018

(2)

code out

7

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(5)

4

3

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

1017 1018 1019 1020 1021 1022 1023

(LSB

V

)

ideal

in(A)

Offset Error (E )

O

Figure 13. ADC characteristics and error definitions

3.14.1 Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor

with good high-frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as

possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; it sources charge during

the sampling phase, when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC

filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be

measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal

(bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being

S

substantially a switched capacitance, with a frequency equal to the ADC conversion rate, it can be seen as a resistive path to

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

57

ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 k is obtained (R = 1

S

EQ

/ (fc × C ), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage

S

partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit

S

F

L

SW

AD

must be designed to respect the Equation 4:

Eqn. 4

R + R + R + R

+ R

S

F

L

SW

AD

1

2

--------------------------------------------------------------------------

V



 -- LSB

A

R

EQ

Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (R

SW

and R ) can be neglected with respect to external resistances.

AD

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Sampling

Selection

Source

Filter

Current Limiter

R

AD

S

F

L

SW1

V

C

S

A

F

P1

P2

R : Source impedance

S

R : Filter resistance

F

C : Filter capacitance

F

R : Current limiter resistance

L

R

: Channel selection switch impedance

SW1

: Sampling switch impedance

AD

C : Pin capacitance (two contributions, C and C )

P2

P

P1

C : Sampling capacitance

S

Figure 14. Input equivalent circuit

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are

F

P1

P2

initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 14): A charge sharing phenomenon

A

is installed when the sampling phase is started (A/D switch closed).

MPC5602P Microcontroller Data Sheet, Rev. 4.1

58

Freescale Semiconductor

Voltage Transient on C_S

V

CS

V

A

V <0.5 LSB

V

A2

1

2

₁< (R_SW+ R_AD) C_S<< t_s

V

A1



₂= R_L(C_S+ C_P1+ C_P2)

t

s

Figure 15. Transient behavior during sampling phase

In particular two different transient periods can be distinguished:

•

A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C

P1 P2 S S

is supposed initially completely discharged): considering a worst case (since the time constant in reality would be

faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,

P2

P1

P

P1

P2

P

S

and the time constant is

Eqn. 5

C  C

P

S

--------------------

 



= R

+ R

1

SW

AD

C + C

P

S

Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is

S

faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time t

is always much longer than the internal time constant:

s

Eqn. 6



 R

+ R

  C « t_s

1

SW

AD

S

The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance

P1

P2

S

A1

according to Equation 7:

Eqn. 7

V

 C + C + C  = V  C + C



A1

S

P1

P2

A

P1

P2

•

A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance

F

R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality

L

P2

S

P1

would be faster), the time constant is:

Eqn. 8



 R  C + C + C

P1 P2



2

L

S

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

59

In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed

well before the end of sampling time t , a constraints on R sizing is obtained:

s

L

Eqn. 9

10   = 10  R  C + C + C   t_s

P1 P2

2

L

S

Of course, R shall be sized also according to the current limitation constraints, in combination with R (source

L

S

impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V

F

P1 P2

S

A2

(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge

A1

balance assuming now C already charged at V ):

S

A1

Eqn. 10

V

 C + C + C + C  = V  C + V  C + C + C 

P1 P2 A1 P1 P2

A2

S

F

A

F

S

The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to

F

provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of

S

A

F F

the filter is very high with respect to the sampling time (t ). The filter is typically designed to act as anti-aliasing.

s

Analog Source Bandwidth (V )

A

t

f

2 R C (Conversion Rate vs. Filter Pole)

F F

c

Noise

 f (Anti-aliasing Filtering Condition)

F

0

2 f f (Nyquist)

0

C

f

0

f

Anti-Aliasing Filter (f = RC Filter pole)

Sampled Signal Spectrum (f = conversion Rate)

C

F

f

C

F

0

f

Figure 16. Spectral representation of input signal

Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),

0

F

according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater

C

0

than or at least equal to twice the conversion period (T ). Again the conversion period t is longer than the sampling time t ,

C

c

s

which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a

specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the

F

sampling time t , so the charge level on C cannot be modified by the analog signal source during the time in which the sampling

s

S

switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage

drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled

S

voltage on C :

S

MPC5602P Microcontroller Data Sheet, Rev. 4.1

60

Freescale Semiconductor

Eqn. 11

V

C

+ C + C

P2

----------- = -------------------------------------------------------

A

P1

F

V

C

+ C + C + C

A2

P1

P2 S

F

From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of

A

half a count, a constraint is evident on C value:

F

Eqn. 12

C

 2048  C

F

S

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

61

3.14.2 ADC conversion characteristics

Table 28. ADC conversion characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

f_CK

SR — ADC clock frequency (depends on

ADC configuration)

—

3³

—

60 MHz

(The duty cycle depends on ADC

clock²frequency)

f_s

t_s

SR — Sampling frequency

— D Sampling time⁴

—

125

—

1.53 MHz

f

_ADC= 20 MHz, INPSAMP = 3

—

28.2

—

ns

µs

f_ADC= 9 MHz, INPSAMP = 255

t_c

— P Conversion time⁵

f_ADC= 20 MHz⁶, INPCMP = 1 0.650

t_{ADC_PU}SR — ADC power-up delay (time needed for

ADC to settle exiting from software

—

1.5

power down; PWDN bit = 0)

7

C_S

— D ADC input sampling capacitance

— D ADC input pin capacitance 1

— D ADC input pin capacitance 2

—

5

—

2.5

3

pF

k

mA

7

C_P1

C_P2

1

7

R_SW1

— D Internal resistance of analog source V_{DD_HV_ADC0}= 5 V ± 10%

V_{DD_HV_ADC0}= 3.3 V ± 10%

0.6

3

7

R_AD

I_INJ

— D Internal resistance of analog source

T Input current injection

—

2

—

Current injection on one ADC

input, different from the

converted one. Remains

within TUE specification

5

INL

CC P Integral non-linearity

No overload

1.5

1.0

—

±1

—

1.5 LSB

1.0 LSB

DNL CC P Differential non-linearity

No overload

E_O

E_G

CC T Offset error

CC T Gain error

—

LSB

—

TUE CC P Total unadjusted error without current

injection

2.5

2.5 LSB

TUE CC T Total unadjusted error with current

injection

—

3

—

3

LSB

1

V_DD= 3.3 V to 3.6 V / 4.5 V to 5.5 V, T_A= 40 °C to T_{A MAX}, unless otherwise specified and analog input voltage

from V_{SS_HV_ADC0}to V_{DD_HV_ADC0}

.

2

3

4

AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which the precision is lost.

During the sampling time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_s. After the end of

the sampling time t_s, changes of the analog input voltage have no effect on the conversion result. Values for the

sample clock t_sdepend on programming.

5

This parameter includes the sampling time t_s.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

62

Freescale Semiconductor

6

7

20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.

See Figure 14.

3.15 Flash memory electrical characteristics

3.15.1 Program/Erase characteristics

Table 29. Program and erase specifications

Value

Symbol

C

Parameter

Unit

Initial

Min

Typ¹

Max³

Max²

T_wprogramP Word Program Time for data flash memory⁴

—

30

22

70

50

500

17.5

4.1

µs

s

T_dwprogramP Double Word Program Time for code flash memory⁴

T_BKPRG

P Bank Program (256 KB)^4,5

P Bank Program (64 KB)^4,5

0.73

0.49

300

0.83

1.2

500

s

T_16kpperaseP 16 KB Block Pre-program and Erase Time for code

flash memory

5000

ms

16 KB Block Pre-program and Erase Time for data

flash memory

—

700

800

5000

T_32kpperaseP 32 KB Block Pre-program and Erase Time

T_128kpperaseP 128 KB Block Pre-program and Erase Time

—

400

800

600

5000

7500

ms

1300

1

Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to

change pending device characterization.

2

3

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

The maximum program and erase times occur after the specified number of program/erase cycles. These maximum

values are characterized but not guaranteed.

4

5

Actual hardware programming times. This does not include software overhead.

Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will

require more than one pulse, adding a small overhead to total bank programming time (see “Initial Max” column).

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

63

Table 30. Flash memory module life

Value

Symbol

C

Parameter

Conditions

Unit

Min

100,000

Typ

P/E

C Number of program/erase cycles per

block for 16 KB blocks over the operating

temperature range (T_J)

—

cycles

P/E

C Number of program/erase cycles per

block for 32 KB blocks over the operating

temperature range (T_J)

—

10,000 100,000 cycles

1,000 100,000 cycles

C Number of program/erase cycles per

block for 128 KB blocks over the operating

temperature range (T_J)

Retention C Minimum data retention at 85 °C average Blocks with 0–1,000 P/E cycles

20

10

5

—

years

ambient temperature¹

Blocks with 10,000 P/E cycles

Blocks with 100,000 P/E cycles

1

Ambient temperature averaged over duration of application, not to exceed recommended product operating

temperature range.

Table 31. Flash memory read access timing

Symbol

C

Parameter

Conditions¹

Max value Unit

f_max

C Maximum working frequency for code flash memory at given

number of wait states in worst conditions

2 wait states

0 wait states

8 wait states

66

18

66

MHz

f_max

C Maximum working frequency for data flash memory at given

number of wait states in worst conditions

MHz

1

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= 40 to 125 °C, unless otherwise specified

3.15.2 Flash memory power supply DC characteristics

Table 32 shows the power supply DC characteristics on external supply.

Table 32. Flash memory power supply DC electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

I_FLPWCC D Sum of the current consumption on V_{DD_HV_IOx}

and V_{DD_LV_CORx}during low-power mode

Code flash memory

—

900 µA

I_FPWDCC D Sum of the current consumption on V_{DD_HV_IOx}

and V_{DD_LV_CORx}during power-down mode

Code flash memory

Data flash memory

—

150 µA

150

1

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= 40 to 125 °C, unless otherwise specified.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

64

Freescale Semiconductor

3.15.3 Start-up/Switch-off timings

Table 33. Start-up time/Switch-off time

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

T_FLARSTEXITCC T Delay for Flash module to exit reset mode

T

Code flash memory

Data flash memory

—

125 µs

125

0.5

T_FLALPEXITCC D Delay for Flash module to exit low-power mode Code flash memory

T_FLAPDEXITCC T Delay for Flash module to exit power-down

Code flash memory

Data flash memory

Code flash memory

30

mode

T

30

T_FLALPENTRYCC D Delay for Flash module to enter low-power

mode

0.5

1

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= 40 to 125 °C, unless otherwise specified.

3.16 AC specifications

3.16.1 Pad AC specifications

Table 34. Output pin transition times

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

t_tr

CC D Output transition time output pin²

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

—

50

100

125

40

ns

SLOW configuration

T

D

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

T

50

D

75

t_tr

CC D Output transition time output pin²

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

SIUL.PCRx.SRC = 1

10

ns

MEDIUM configuration

T

20

D

T

40

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

12

25

D

40

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

65

Table 34. Output pin transition times (continued)

Conditions¹

Value

Symbol

C

Parameter

Unit

Min Typ Max

t_tr

CC D Output transition time output pin²

FAST configuration

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

SIUL.PCRx.SRC = 1

—

4

6

ns

12

4

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

7

12

4

3

t_SYMCC T Symmetric transition time, same drive V_DD= 5.0 V ± 10%, PAD3V5V = 0

strength between N and P transistor

ns

V_DD= 3.3 V ± 10%, PAD3V5V = 1

5

1

2

3

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= 40 °C to T_{A MAX}, unless otherwise specified.

C_Lincludes device and package capacitances (C_PKG< 5 pF).

Transition timing of both positive and negative slopes will differ maximum 50%.

V_{DD_HV_IOx}/2

Pad

Data Input

Rising

Edge

Falling

Edge

Output

Delay

Output

Delay

V_OH

V_OL

Pad

Output

Figure 17. Pad output delay

3.17 AC timing characteristics

3.17.1 RESET pin characteristics

The MPC5602P implements a dedicated bidirectional RESET pin.

MPC5602P Microcontroller Data Sheet, Rev. 4.1

66

Freescale Semiconductor

V

DD

V

DDMIN

V_RESET

V

IH

V

IL

device reset forced by V_RESET

device start-up phase

t_POR

Figure 18. Start-up reset requirements

V_RESET

hw_rst

‘1’

V

DD

V

IH

V

IL

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

Figure 19. Noise filtering on reset signal

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

67

Table 35. RESET electrical characteristics

Value²

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_IH

V_IL

SR P Input high level CMOS

(Schmitt Trigger)

—

0.65V_DD

—

V_DD+ 0.4

V

SR P Input low level CMOS

(Schmitt Trigger)

0.4

0.1V_DD

—

0.35V_DD

—

V_HYSCC C Input hysteresis CMOS

(Schmitt Trigger)

V_OLCC P Output low level

Push Pull, I_OL= 2 mA,

V_DD= 5.0 V ± 10%, PAD3V5V = 0

(recommended)

0.1V_DD

Push Pull, I_OL= 1 mA,

—

0.1V_DD

0.5

V_DD= 5.0 V ± 10%, PAD3V5V = 1³

Push Pull, I_OL= 1 mA,

V_DD= 3.3 V ± 10%, PAD3V5V = 1

(recommended)

t_tr

CC D Output transition time

output pin⁴MEDIUM

configuration

C_L= 25 pF,

V_DD= 5.0 V ± 10%, PAD3V5V = 0

—

10

20

40

12

25

40

—

1

ns

C_L= 50 pF,

V_DD= 5.0 V ± 10%, PAD3V5V = 0

C_L= 100 pF,

V_DD= 5.0 V ± 10%, PAD3V5V = 0

—

C_L= 25 pF,

V_DD= 3.3 V ± 10%, PAD3V5V = 1

—

C_L= 50 pF,

V_DD= 3.3 V ± 10%, PAD3V5V = 1

—

C_L= 100 pF,

V_DD= 3.3 V ± 10%, PAD3V5V = 1

—

W_FRSTSR P RESET input filtered

pulse

—

ns

W_NFRSTSR P RESET input not filtered

pulse

—

500

—

t_PORCC D Maximum delay before Monotonic V_{DD_HV}supply ramp

ms

internal resetis released

after all V_{DD_HV}reach

nominal supply

|I_WPU

|

CC P Weak pull-up current

absolute value

V_DD= 3.3 V ± 10%, PAD3V5V = 1

V_DD= 5.0 V ± 10%, PAD3V5V = 0

10

—

150

250

µA

V

_DD= 5.0 V ± 10%, PAD3V5V = 1⁵

1

2

3

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= 40 to 125 °C, unless otherwise specified

All values need to be confirmed during device validation.

This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of

device reference manual).

MPC5602P Microcontroller Data Sheet, Rev. 4.1

68

Freescale Semiconductor

4

5

C_Lincludes device and package capacitance (C_PKG< 5 pF).

The configuration PAD3V5 = 1 when V_DD= 5 V is only transient configuration during power-up. All pads but RESET

and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

3.17.2 IEEE 1149.1 interface timing

Table 36. JTAG pin AC electrical characteristics

Value

No.

Symbol

C

Parameter

Conditions

Unit

Min Max

1

2

t_JCYC

CC D TCK cycle time

—

100

40

—

5

—

60

3

ns

t_JDC

CC D TCK clock pulse width (measured at V_{DD_HV_IOx}/2)

CC D TCK rise and fall times (40%–70%)

CC D TMS, TDI data setup time

3

t_TCKRISE

4

t_{TMSS, TDIS}

t_{TMSH, TDIH}

t_TDOV

t_TDOI

t

—

40

—

50

5

t

CC D TMS, TDI data hold time

25

—

0

6

CC D TCK low to TDO data valid

7

CC D TCK low to TDO data invalid

CC D TCK low to TDO high impedance

CC D TCK falling edge to output valid

8

t_TDOHZ

t_BSDV

t_BSDVZ

40

—

9

10

CC D TCK falling edge to output valid out of high

impedance

11

12

13

t_BSDHZ

t_BSDST

t_BSDHT

CC D TCK falling edge to output high impedance

CC D Boundary scan input valid to TCK rising edge

CC D TCK rising edge to boundary scan input invalid

—

50

—

ns

TCK

2

3

2

1

3

Figure 20. JTAG test clock input timing

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

69

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 21. JTAG test access port timing

MPC5602P Microcontroller Data Sheet, Rev. 4.1

70

Freescale Semiconductor

TCK

11

13

Output

Signals

12

Output

Signals

14

15

Input

Signals

Figure 22. JTAG boundary scan timing

3.17.3 Nexus timing

1

Table 37. Nexus debug port timing

Value

Typ

No.

Symbol

C

Parameter

Min

Unit

Max

1

2

t_TCYC

t_NTDIS

CC D TCK cycle time

4²

5

—

20

—

t_CYC

ns

CC D TDI data setup time

t_NTMSSCC D TMS data setup time

t_NTDIHCC D TDI data hold time

t_NTMSHCC D TMS data hold time

5

ns

3

25

10

—

ns

4

5

t_TDOV

t_TDOI

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

ns

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

71

1

2

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.

Lower frequency is required to be fully compliant to standard.

1

MCKO

2

3

4

MDO

MSEO

EVTO

Output Data Valid

Figure 23. Nexus output timing

TCK

EVTI

EVTO

5

Figure 24. Nexus event trigger and test clock timing

MPC5602P Microcontroller Data Sheet, Rev. 4.1

72

Freescale Semiconductor

TCK

6

7

TMS, TDI

9

8

TDO

Figure 25. Nexus TDI, TMS, TDO timing

3.17.4 External interrupt timing (IRQ pin)

1

Table 38. External interrupt timing

Value

No.

Symbol

C

Parameter

Conditions

Unit

Min Max

1

2

3

t_IPWL

t_IPWH

t_ICYC

CC

D

IRQ pulse width low

—

4

—

t_CYC

IRQ pulse width high

IRQ edge to edge time²

4 + N³

1

IRQ timing specified at f_SYS= 64 MHz and V_{DD_HV_IOx}= 3.0 V to 5.5 V, T_A= T_Lto T_H, and C_L= 200 pF with

SRC = 0b00

2

3

Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

N = ISR time to clear the flag

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

73

IRQ

1

2

3

Figure 26. External interrupt timing

3.17.5 DSPI timing

1

Table 39. DSPI timing

Value

No. Symbol

C

Parameter

Conditions

Unit

Min

Max

1

t_SCKCC

D

DSPI cycle time

Master (MTFE = 0)

60

16

26

—

ns

Slave (MTFE = 0)

2

3

4

5

6

t_CSCCC

t_ASCCC

t_SDCCC

D

CS to SCK delay

After SCK delay

—

ns

—

SCK duty cycle

0.4 * t_SCK0.6 * t_SCKns

t_A

CC

Slave access time

Slave SOUT disable time

SS active to SOUT valid

—

30

16

ns

t_DISCC

SS inactive to SOUT high

impedance or invalid

7

8

9

t_PCSCCC

t_PASCCC

t_SUICC

D

PCSx to PCSS time

PCSS to PCSx time

Data setup time for inputs

—

13

35

4

—

ns

—

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

Slave

35

5

4

10

t_HI

CC

D

Data hold time for inputs

ns

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

11

5

MPC5602P Microcontroller Data Sheet, Rev. 4.1

74

Freescale Semiconductor

1

Table 39. DSPI timing (continued)

Value

No. Symbol

C

Parameter

Conditions

Unit

Min

Max

11 t_SUOCC

D

Data valid (after SCK edge) Master (MTFE = 0)

Slave

—

2

6

12

36

12

—

ns

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

12 t_HOCC

D

Data hold time for outputs

ns

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

6

2

1

All timing are provided with 50 pF capacitance on output, 1 ns transition time on input signal

2

3

PCSx

1

4

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

10

9

Last Data

SIN

First Data

Data

12

11

Last Data

SOUT

Note: Numbers shown reference Table 39.

Figure 27. DSPI classic SPI timing – Master, CPHA = 0

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

75

PCSx

SCK Output

(CPOL=0)

10

SCK Output

(CPOL=1)

9

Data

First Data

Last Data

SIN

12

11

SOUT

Last Data

First Data

Note: Numbers shown reference Table 39.

Figure 28. DSPI classic SPI timing – Master, CPHA = 1

3

2

SS

1

4

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

5

11

12

Data

6

First Data

Last Data

SOUT

SIN

9

10

Data

Last Data

First Data

Note: Numbers shown reference Table 39.

Figure 29. DSPI classic SPI timing – Slave, CPHA = 0

MPC5602P Microcontroller Data Sheet, Rev. 4.1

76

Freescale Semiconductor

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

Data

SOUT

SIN

First Data

10

9

Last Data

First Data

Note: Numbers shown reference Table 39.

Figure 30. DSPI classic SPI timing – Slave, CPHA = 1

3

PCSx

4

1

2

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

9

10

SIN

First Data

12

Last Data

Data

11

SOUT

First Data

Data

Note: Numbers shown reference Table 39.

Figure 31. DSPI modified transfer format timing – Master, CPHA = 0

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

77

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

10

9

SIN

Last Data

First Data

Data

12

Data

11

First Data

Last Data

SOUT

Note: Numbers shown reference Table 39.

Figure 32. DSPI modified transfer format timing – Master, CPHA = 1

3

2

SS

1

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

12

11

6

5

First Data

9

Data

Last Data

10

SOUT

SIN

Last Data

First Data

Note: Numbers shown reference Table 39.

Figure 33. DSPI modified transfer format timing – Slave, CPHA = 0

MPC5602P Microcontroller Data Sheet, Rev. 4.1

78

Freescale Semiconductor

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

First Data

10

Data

SOUT

SIN

9

First Data

Last Data

Note: Numbers shown reference Table 39.

Figure 34. DSPI modified transfer format timing – Slave, CPHA = 1

8

7

PCSS

PCSx

Note: Numbers shown reference Table 39.

Figure 35. DSPI PCS Strobe (PCSS) timing

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

79

4

Package characteristics

Package mechanical data

4.1

4.1.1

100 LQFP mechanical outline drawing

MPC5602P Microcontroller Data Sheet, Rev. 4.1

80

Freescale Semiconductor

Figure 36. 100 LQFP package mechanical drawing (part 1)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

81

Figure 37. 100 LQFP package mechanical drawing (part 2)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

82

Freescale Semiconductor

Figure 38. 100 LQFP package mechanical drawing (part 3)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

83

4.1.2

64 LQFP mechanical outline drawing

Figure 39. 64 LQFP package mechanical drawing (part 1)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

84

Freescale Semiconductor

Figure 40. 64LQFP package mechanical drawing (part 2)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

85

Figure 41. 64LQFP package mechanical drawing (part 3)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

86

Freescale Semiconductor

5

Ordering information

Figure 42. Commercial product code structure

Example code:

M

PC

56

0

2

P

E

F0

M

LL

4

R

Qualification Status

Power Architecture Core

Automotive Platform

Core Version

Flash Size (core dependent)

Product

Optional Fields

Fab & Mask Revision

Temperature spec.

Package Code

Frequency

R = Tape & Reel (blank if Tray)

Qualification Status

M = MC status

S = Automotive qualified

P = PC status

Flash Size (z0 core)

1 = 192 KB

2 = 256 KB

Temperature spec.

V = –40 to 105 °C

M = –40 to 125 °C

Product

P = MPC560xP family

Package Code

LH = 64 LQFP

LL = 100 LQFP

Automotive Platform

56 = Power Architecture in 90 nm

Optional fields

Core Version

0 = e200z0

E = Data Flash (blank if none)

Frequency

4 = 40 MHz

6 = 64 MHz

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

87

6

Document revision history

Table 40 summarizes revisions to this document.

Table 40. Revision history

Revision

Date

Description of

1

2

05 Aug 2009 Initial release.

07 Apr 2010 Editorial updates

Updated the following items in the “MPC5602P device comparison” table:

• The heading

• The “SRAM” row

• The “FlexCAN” row

• The “CTU” row

• The “FlexPWM” row

• The “LINFlex” row

• The “DSPI” row

• The “Nexus” row

• Deleted the footnote No. 3

Added the “Wakeup unit” block in the MPC5602P block diagram

Updated the “Absolute Maximum Ratings“ table

Updated the “Recommended operating conditions (5.0 V)“ table

Updated the “Recommended operating conditions (3.3 V)“ table

Updated the “Thermal characteristics for 100-pin LQFP“ table:

• _JT: changed the typical value

Updated the “EMI testing specifications“ table: replaced all values in “Level (Max)“

column with TBD

Updated the “Electrical characteristics“ section:

• Added the “Introduction” section

• Added the “Parameter classification“ section

• Added the “NVUSRO register“ section

• Added the “Power supplies constraints (–0.3 V  V_{DD_HV_IOx} 6.0 V)” figure

• Added the “Independent ADC supply (–0.3 V  V_{DD_HV_REG} 6.0 V)“ figure

• Added the “Power supplies constraints (3.0 V  V_{DD_HV_IOx} 5.5 V)“ figure

• Added the “Independent ADC supply (3.0 V  V_{DD_HV_REG} 5.5 V)“ figure

Updated the “Power management electrical characteristics” section

Updated the “Power Up/Down sequencing” section

Updated the “DC electrical characteristics“ section

• Deleted the “NVUSRO register” section

• Updated the “DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)“ section:

– Deleted all rows concerning RESET

– Deleted “I_VPP“ row

– Added the max value for C_IN

• Updated the “DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 0)“ section:

– Deleted all rows concerning RESET

– Deleted “I_VPP“ row

– Added the max value for C_IN

Added the “I/O pad current specification“ section

Updated the Orderable part number summarytable.

2

07 Apr 2010 Added “Appendix A”

(continued)

MPC5602P Microcontroller Data Sheet, Rev. 4.1

88

Freescale Semiconductor

Table 40. Revision history (continued)

Description of

Revision

Date

3

16 Dec 2010 “Introduction” section:

• Changed title (was “Overview“)

• Updated contents

“MPC5602P device comparison” table:

• Added sentence above table

• Removed “FlexRay” row

“MPC5602P block diagram”: added the following blocks: MC_CGM, MC_ME, MC_PCU,

MC_RGM, CRC, and SSCM

Added “MPC5602P series block summary” table

“Pin muxing” section: removed information on “Symmetric pads”

“Electrical characteristics” section:

• Updated “Caution” note

• Demoted “NVUSRO register” section to subsection of “DC electrical characteristics”

section

• “NVUSRO register” section: deleted “NVUSRO[WATCHDOG_EN] field description“

section

Updated “EMI testing specifications” table

“Low voltage monitor electrical characteristics” table: updated V_{MLVDDOK_H}max value

“DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)” table: removed _{VOL_SYM}

and V_{OH_SYM}rows

,

“Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)” table:

• I_{DD_LV_CORE}, RUN—Maximum mode, 40/64 MHz: updated typ/max values

• I_{DD_LV_CORE}, RUN—Airbag mode, 40/64 MHz: updated typ/max values

• I_{DD_LV_CORE}, RUN—Maximum mode, “P” parameter classification: removed

• I_{DD_FLASH}: removed rows

• I_{DD_ADC}, Maximum mode: updated typ/max values

• I_{DD_OSC}: updated max value

Updated “DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)” table

“Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)” table:

• I_{DD_LV_CORE}, RUN—Maximum mode, 40/64 MHz: updated typ/max values

• I_{DD_LV_CORE}, RUN—Airbag mode, 40/64 MHz: updated typ/max values

• I_{DD_FLASH}: removed rows

• I_{DD_ADC}, Maximum mode: updated typ/max values

• I_{DD_OSC}: updated max value

Added “I/O consumption” table

Removed “I/O weight” table

Updated “Main oscillator electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)” table

Updated “Main oscillator electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)” table

“Input clock characteristics” table: updated f_CLKmax value

“PLLMRFM electrical specifications (V_DDPLL= 1.08 V to 1.32 V, V_SS= V_SSPLL= 0 V,

T_A= T_Lto T_H)” table:

• Updated supply voltage range for V_DDPLLin the table title

• Updated f_SCMmax value

• Updated C_JITTERrow

• Updated f_MODmax value

Updated “16 MHz RC oscillator electrical characteristics” table

Updated “ADC conversion characteristics” table

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

89

Table 40. Revision history (continued)

Description of

Revision

Date

3

16 Dec 2010 “Program and erase specifications” table:

• T_wprogram: updated initial max and max values

• T_BKPRG, 64 KB: updated initial max and max values

• added information about “erase time” for Data Flash

“Flash module life” table:

(continued)

• P/E, 32 KB: added typ value

• P/E, 128 KB: added typ value

Replaced “Pad AC specifications (5.0 V, NVUSRO[PAD3V5V] = 0)” and “Pad AC

specifications (3.3 V, INVUSRO[PAD3V5V] = 1)” tables with “Output pin transition

times” table

“JTAG pin AC electrical characteristics” table:

• t_TDOV: updated max value

• t_TDOHZ: added min value and removed max value

“Nexus debug port timing” table: removed the rows “t_MCYC”, “t_MDOV”, “t_MSEOV”, and

“t_EVTOV

”

Updated “External interrupt timing (IRQ pin)” table

Updated “FlexCAN timing” table

Updated “DSPI timing” table

Updated “Ordering information” section

MPC5602P Microcontroller Data Sheet, Rev. 4.1

90

Freescale Semiconductor

Table 40. Revision history (continued)

Description of

Revision

Date

4

11 May 2011 Editorial and formatting changes throughout

Section 1, “Introduction: Reorganized contents

MPC5602P block diagram: reorganized blocks above and below peripheral bridge; made

arrow going from peripheral bridge to crossbar switch bidirectional

Updated Section 1.5, “Feature list:

• changed core feature from “64 MHz” to “Up to 64 MHz”

• memory organization

• moved “16-channel eDMA controller” item to “Interrupts and events” item

• LINFlex: changed “2 LINFlex modules” to “Up to 2 LINFlex modules”

• DSPI: changed “3 DSPI channels“ to “Up to 3 DSPI channels”

• ADC: changed “16 input channels“ to “Up to 16 input channels”

Added Section 1.5, “Feature details

64-pin and 100-pin LQFP pinout diagrams: replaced instances of HV_AD0 with

HV_ADC0

System pins: updated “XTAL” and “EXTAL” rows

Updated LQFP thermal characteristics

Updated EMI testing specifications

Section 3.8.1, “Voltage regulator electrical characteristics: removed BCP56 from named

BJTs; replaced two configuration diagrams and two electrical characteristics tables

with single diagram and single table

Voltage regulator electrical characteristics: updated V_{DD_LV_REGCOR}row

Low voltage monitor electrical characteristics: updated V_{MLVDDOK_H}max value—was

1.15 V; is 1.145 V

Supply current (5.0 V, NVUSRO[PAD3V5V] = 0): changed symbol I_{DD_LV_CORE}to

I_{DD_LV_CORx}; changed parameter classification from T to P for I_{DD_LV_CORx}

RUN—Maximum mode at 64 MHz; added I_{DD_FLASH}characteristics; replaced

instances of “Airbag” mode with “Typical mode”

Supply current (3.3 V, NVUSRO[PAD3V5V] = 1): changed symbol I_{DD_LV_CORE}to

I_{DD_LV_CORx}; replaced instances of “Airbag” mode with “Typical mode”

DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1): corrected parameter

description for V_{OL_F}—was “Fast, high level output voltage”; is “Fast, low level output

voltage”

Added Section 3.10.4, “Input DC electrical characteristics definition

Main oscillator output electrical characteristics tables: replaced instances of EXTAL with

XTAL; added load capacitance parameter

FMPLL electrical characteristics: updated conditions and table title; removed f_sysrow;

updated f_FMPLLOUTvalues; replaced instances of V_DDPLLwith V_{DD_LV_COR0}; replaced

instances of V_SSPLLwith V_{SS_LV_COR0}

16 MHz RC oscillator electrical characteristics: removed rows _RCMTRIMand _RCMSTEP

ADC characteristics and error definitions: updated symbols

ADC conversion characteristics: updated symbols; added row t_{ADC_PU}

Added Section 3.15.2, “Flash memory power supply DC characteristics

Added Section 3.15.3, “Start-up/Switch-off timings

Removed section “Generic timing diagrams”

4

11 May 2011 Updated Start-up reset requirements diagram

Removed FlexCAN timing characteristics

(cont’d)

RESET electrical characteristics: added row for t_POR

In the range of figures “DSPI Classic SPI Timing — Master, CPHA = 0” to “DSPI PCS

Strobe (PCSS) Timing”: added note

Table A-1: added “DUT”, “NPN”, and “RISC”

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

91

Table 40. Revision history (continued)

Description of

Revision

Date

4.1

15 Sep 2011 Deleted the “Freescale Confidential Proprietary, NDA Required” label (the document is

Public).

MPC5602P Microcontroller Data Sheet, Rev. 4.1

92

Freescale Semiconductor

Appendix A Abbreviations

Table A-1 lists abbreviations used in this document.

Table A-1. Abbreviations

Abbreviation

Meaning

CMOS

CPHA

CPOL

CS

Complementary metal–oxide–semiconductor

Clock phase

Clock polarity

Peripheral chip select

Device under test

DUT

ECC

Error code correction

Event out

EVTO

GPIO

MC

General purpose input / output

Modulus counter

MCKO

MCU

MDO

MSEO

MTFE

NPN

Message clock out

Microcontroller unit

Message data out

Message start/end out

Modified timing format enable

Negative-positive-negative

Non-volatile user options register

Post trimming frequency

Pulse width modulation

Reduced instruction set computer

Serial communications clock

Serial data out

NVUSRO

PTF

PWM

RISC

SCK

SOUT

TBC

To be confirmed

TBD

To be defined

TCK

Test clock input

TDI

Test data input

TDO

Test data output

TMS

Test mode select

MPC5602P Microcontroller Data Sheet, Rev. 4.1

Freescale Semiconductor

93

MPC5602P Microcontroller Data Sheet, Rev. 4.1

94

Freescale Semiconductor

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale Semiconductor assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale Semiconductor data sheets and/or specifications can and do vary

in different applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Freescale Semiconductor product

could create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and

its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of,

directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Freescale

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

www.freescale.com/support

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

Semiconductor was negligent regarding the design or manufacture of the part.

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064

RoHS-compliant and/or Pb-free versions of Freescale products have the functionality

and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free

counterparts. For further information, see http://www.freescale.com or contact your

Freescale sales representative.

Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor China Ltd.

Exchange Building 23F

No. 118 Jianguo Road

Chaoyang District

For information on Freescale’s Environmental Products program, go to

http://www.freescale.com/epp.

Beijing 100022

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

All other product or service names are the property of their respective owners.

China

+86 10 5879 8000

support.asia@freescale.com

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or +1-303-675-2140

Fax: +1-303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Document Number: MPC5602P

Rev. 4.1

09/2011


型号：	MPC5601F0VLH4
厂家：	NXP
描述：	32-BIT, FLASH, 64MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BCD, LQFP-64 控制器 CD 微控制器微控制器和处理器
文件：	总95页 (文件大小：1689K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC5601F0VLH4 [NXP]

相关型号：

MPC5601F0VLL6R

MPC5601PEF0MLH4R

MPC5601PEF0MLH6

MPC5601PEF0MLH6R

MPC5601PEF0MLL4R

MPC5601PEF0MLL6

MPC5601PEF0MLL6R

MPC5601PEF0VLH4R

MPC5601PEF0VLH6R

MPC5601PEF0VLL4R

MPC5601PEF0VLL6R

MPC5602B